From be43b20eaf35ea202835f1cc438e5e8e88e7a9c3 Mon Sep 17 00:00:00 2001 From: Marcus Chang Date: Thu, 11 Jan 2018 13:38:54 -0800 Subject: [PATCH 001/133] Increase clock tolerance in Flash HAL test The current 0.1% clock tolerance is too small for certain platforms which natural variance is larger than this. This commit increases the tolerance to 0.5% instead. Sample output from time_cpu_cycles called repeatedly in init, before running any flash tests: [1515706585.63][CONN][RXD] diff: 49316 [1515706585.69][CONN][RXD] diff: 49256 [1515706585.75][CONN][RXD] diff: 49286 [1515706585.81][CONN][RXD] diff: 49256 [1515706585.87][CONN][RXD] diff: 49225 [1515706585.94][CONN][RXD] diff: 49286 [1515706585.99][CONN][RXD] diff: 49317 [1515706586.06][CONN][RXD] diff: 49255 [1515706586.12][CONN][RXD] diff: 49286 [1515706586.18][CONN][RXD] diff: 49285 [1515706586.24][CONN][RXD] diff: 49286 [1515706586.31][CONN][RXD] diff: 49347 [1515706586.36][CONN][RXD] diff: 49347 [1515706586.43][CONN][RXD] diff: 49286 [1515706586.49][CONN][RXD] diff: 49286 [1515706586.55][CONN][RXD] diff: 49256 [1515706586.61][CONN][RXD] diff: 49286 [1515706586.68][CONN][RXD] diff: 49346 [1515706586.74][CONN][RXD] diff: 49347 [1515706586.80][CONN][RXD] diff: 49256 Notice the outliers will cause intermittent CI failures. --- TESTS/mbed_hal/flash/functional_tests/main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/mbed_hal/flash/functional_tests/main.cpp b/TESTS/mbed_hal/flash/functional_tests/main.cpp index 156899410a..0170d2255e 100644 --- a/TESTS/mbed_hal/flash/functional_tests/main.cpp +++ b/TESTS/mbed_hal/flash/functional_tests/main.cpp @@ -28,7 +28,7 @@ using namespace utest::v1; #define TEST_CYCLES 1000000 -#define ALLOWED_DRIFT_PPM 1000 //0.1% +#define ALLOWED_DRIFT_PPM 5000 //0.5% /* return values to be checked are documented at: From 70c0af19b9cd753fe1fe3469647cfee38787dfc1 Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Fri, 5 Jan 2018 17:39:44 -0600 Subject: [PATCH 002/133] ESP8266 test config and tcp_echo test fix for ESP8266 --- TESTS/netsocket/tcp_echo/main.cpp | 19 +++++++----- tools/test_configs/ESP8266Interface.json | 37 ++++++++++++++++++++++++ tools/test_configs/config_paths.json | 3 +- tools/test_configs/target_configs.json | 2 +- 4 files changed, 52 insertions(+), 9 deletions(-) create mode 100644 tools/test_configs/ESP8266Interface.json diff --git a/TESTS/netsocket/tcp_echo/main.cpp b/TESTS/netsocket/tcp_echo/main.cpp index c195cda4df..13776ebc10 100644 --- a/TESTS/netsocket/tcp_echo/main.cpp +++ b/TESTS/netsocket/tcp_echo/main.cpp @@ -28,13 +28,13 @@ using namespace utest::v1; -#ifndef MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE -#define MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE 256 +#ifndef MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE +#define MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE 256 #endif namespace { - char tx_buffer[MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; - char rx_buffer[MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; + char tx_buffer[MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; + char rx_buffer[MBED_CONF_APP_TCP_CLIENT_ECHO_BUFFER_SIZE] = {0}; } void prep_buffer(char *tx_buffer, size_t tx_size) { @@ -44,7 +44,7 @@ void prep_buffer(char *tx_buffer, size_t tx_size) { } void test_tcp_echo() { - + int n = 0; NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION; int err = MBED_CONF_APP_CONNECT_STATEMENT; @@ -86,7 +86,12 @@ void test_tcp_echo() { prep_buffer(tx_buffer, sizeof(tx_buffer)); #if defined(MBED_CONF_APP_TCP_ECHO_PREFIX) - sock.recv(rx_buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX)); + n = sock.recv(rx_buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX)); + if (n >= 0) { + printf("recv-ed prefix: %d bytes - %.*s \n", n, n, rx_buffer); + } else { + printf("Network error in receiving prefix: %d\n", n); + } #endif /* MBED_CONF_APP_TCP_ECHO_PREFIX */ const int ret = sock.send(tx_buffer, sizeof(tx_buffer)); if (ret >= 0) { @@ -95,7 +100,7 @@ void test_tcp_echo() { printf("Network error %d\n", ret); } - int n = sock.recv(rx_buffer, sizeof(rx_buffer)); + n = sock.recv(rx_buffer, sizeof(rx_buffer)); if (n >= 0) { printf("recv %d bytes - %.*s \n", n, n, rx_buffer); } else { diff --git a/tools/test_configs/ESP8266Interface.json b/tools/test_configs/ESP8266Interface.json new file mode 100644 index 0000000000..eba1c0cb4a --- /dev/null +++ b/tools/test_configs/ESP8266Interface.json @@ -0,0 +1,37 @@ +{ + "config": { + "header-file": { + "help" : "String for including your driver header file", + "value" : "\"ESP8266Interface.h\"" + }, + "object-construction" : { + "value" : "new ESP8266Interface( D1, D0, false )" + }, + "connect-statement" : { + "help" : "Must use 'net' variable name, replace WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL with your WiFi settings", + "value" : "((ESP8266Interface *)net)->connect(WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL)" + }, + "echo-server-addr" : { + "help" : "IP address of echo server", + "value" : "\"195.34.89.241\"" + }, + "echo-server-port" : { + "help" : "Port of echo server", + "value" : "7" + }, + "tcp-echo-prefix" : { + "help" : "Some servers send a prefix before echoed message", + "value" : "\"u-blox AG TCP/UDP test service\\n\"" + }, + "tcp-client-echo-buffer-size" : { + "help" : "Number of bytes to be send to echo server", + "value" : "200" + }, + "ESP8266-TX": { + "value":"D1" + }, + "ESP8266-RX": { + "value":"D0" + } + } +} diff --git a/tools/test_configs/config_paths.json b/tools/test_configs/config_paths.json index 3b85ad608e..17937fa28f 100644 --- a/tools/test_configs/config_paths.json +++ b/tools/test_configs/config_paths.json @@ -4,5 +4,6 @@ "HEAPBLOCKDEVICE_AND_ETHERNET": "HeapBlockDeviceAndEthernetInterface.json", "ODIN_WIFI" : "OdinInterface.json", "ODIN_ETHERNET" : "Odin_EthernetInterface.json", - "REALTEK_WIFI" : "RealtekInterface.json" + "REALTEK_WIFI" : "RealtekInterface.json", + "ESP8266_WIFI" : "ESP8266Interface.json" } diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index a48e6e16fe..c25c546faa 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -9,7 +9,7 @@ }, "K64F": { "default_test_configuration": "HEAPBLOCKDEVICE_AND_ETHERNET", - "test_configurations": ["HEAPBLOCKDEVICE_AND_ETHERNET"] + "test_configurations": ["HEAPBLOCKDEVICE_AND_ETHERNET", "ESP8266_WIFI", "ETHERNET"] }, "NUCLEO_F429ZI": { "default_test_configuration": "HEAPBLOCKDEVICE_AND_ETHERNET", From a22d968996c1b87a97527e5e743a8e0be74e7e50 Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Mon, 8 Jan 2018 14:14:01 -0600 Subject: [PATCH 003/133] Fix tcp_hello_world test to receive all the data from http response --- TESTS/netsocket/tcp_hello_world/main.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/TESTS/netsocket/tcp_hello_world/main.cpp b/TESTS/netsocket/tcp_hello_world/main.cpp index 155e5fca29..b6e36dd538 100644 --- a/TESTS/netsocket/tcp_hello_world/main.cpp +++ b/TESTS/netsocket/tcp_hello_world/main.cpp @@ -76,9 +76,15 @@ void test_tcp_hello_world() { sock.send(buffer, strlen(buffer)); // Server will respond with HTTP GET's success code - const int ret = sock.recv(buffer, sizeof(buffer) - 1); - buffer[ret] = '\0'; + int ret = 0; + int bytes_recvd = 0; + do { + ret += bytes_recvd; + bytes_recvd = sock.recv(buffer+ret, sizeof(buffer) - 1 - ret); + }while(bytes_recvd > 0); + buffer[ret] = '\0'; + // Find 200 OK HTTP status in reply bool found_200_ok = find_substring(buffer, buffer + ret, HTTP_OK_STR, HTTP_OK_STR + strlen(HTTP_OK_STR)); // Find "Hello World!" string in reply From cbe539d1d8051f4cb199eb05ad8e5ac310e4b5ce Mon Sep 17 00:00:00 2001 From: deepikabhavnani Date: Thu, 11 Jan 2018 14:28:17 -0600 Subject: [PATCH 004/133] Fix: Sector/Size overflow from uint32_t FATFilesystem declares sector count and size as uint32_t and block device class arguments are addr and size which is uint64_t While passing arguments to program/read/write API's of block device, multiplication of uint32_t*uint32_t was not typecasted properly to uint64_t which resulted in MSB truncation. Eg. If block 0x800000 is accessed with block size 0x200, addr to be passed (0x800000*0x200)0x100000000, but actual address passed was 0x0 which resulted in over-writting the root directory, and hence corrupted filesystem --- features/filesystem/fat/FATFileSystem.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/features/filesystem/fat/FATFileSystem.cpp b/features/filesystem/fat/FATFileSystem.cpp index 152cc96b33..d7c9309bb9 100644 --- a/features/filesystem/fat/FATFileSystem.cpp +++ b/features/filesystem/fat/FATFileSystem.cpp @@ -196,7 +196,9 @@ DRESULT disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count) { debug_if(FFS_DBG, "disk_read(sector %d, count %d) on pdrv [%d]\n", sector, count, pdrv); DWORD ssize = disk_get_sector_size(pdrv); - int err = _ffs[pdrv]->read(buff, sector*ssize, count*ssize); + bd_addr_t addr = (bd_addr_t)sector*ssize; + bd_size_t size = (bd_size_t)count*ssize; + int err = _ffs[pdrv]->read(buff, addr, size); return err ? RES_PARERR : RES_OK; } @@ -204,12 +206,14 @@ DRESULT disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count) { debug_if(FFS_DBG, "disk_write(sector %d, count %d) on pdrv [%d]\n", sector, count, pdrv); DWORD ssize = disk_get_sector_size(pdrv); - int err = _ffs[pdrv]->erase(sector*ssize, count*ssize); + bd_addr_t addr = (bd_addr_t)sector*ssize; + bd_size_t size = (bd_size_t)count*ssize; + int err = _ffs[pdrv]->erase(addr, size); if (err) { return RES_PARERR; } - err = _ffs[pdrv]->program(buff, sector*ssize, count*ssize); + err = _ffs[pdrv]->program(buff, addr, size); if (err) { return RES_PARERR; } @@ -250,7 +254,9 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff) } else { DWORD *sectors = (DWORD*)buff; DWORD ssize = disk_get_sector_size(pdrv); - int err = _ffs[pdrv]->trim(sectors[0]*ssize, (sectors[1]-sectors[0]+1)*ssize); + bd_addr_t addr = (bd_addr_t)sectors[0]*ssize; + bd_size_t size = (bd_size_t)(sectors[1]-sectors[0]+1)*ssize; + int err = _ffs[pdrv]->trim(addr, size); return err ? RES_PARERR : RES_OK; } } From d1a75ecff1451d70c5f55b9e72d07c7eb96d519e Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Mon, 8 Jan 2018 13:24:15 +0100 Subject: [PATCH 005/133] DISCO_F407VG : alignment with other STM32 - clock source is now a user choice - IAR tool chain is available --- .../TARGET_DISCO_F407VG/PinNames.h | 14 +- .../TARGET_DISCO_F407VG/system_clock.c | 58 +- .../TOOLCHAIN_IAR/startup_stm32f407xx.S | 636 ++++++++++++++++++ .../device/TOOLCHAIN_IAR/stm32f407xx.icf | 32 + targets/targets.json | 10 +- 5 files changed, 715 insertions(+), 35 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h index 1968bebf0f..0c542e3b91 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h @@ -197,13 +197,13 @@ typedef enum { ADC_VBAT = 0xF2, // Generic signals namings - LED1 = PD_13, - LED2 = PD_12, - LED3 = PD_13, - LED4 = PD_12, - LED5 = PD_14, - LED6 = PD_15, - LED_RED = LED1, + LED1 = PD_13, // LD3 as LD1 is not a user LED + LED2 = PD_12, // LD4 as LD2 is not a user LED + LED3 = PD_13, // orange + LED4 = PD_12, // green + LED5 = PD_14, // red + LED6 = PD_15, // blue + LED_RED = LED5, USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c index 5610e67950..5a042fb752 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c @@ -17,25 +17,20 @@ /** * This file configures the system clock as follows: *----------------------------------------------------------------------------- - * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI - * | (external 8 MHz clock) | (internal 16 MHz) - * | 2- PLL_HSE_XTAL | - * | (external 8 MHz xtal) | + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 168 | 168 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 168 | 168 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 42 | 42 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 84 | 84 - *----------------------------------------------------------------------------- - * USB capable (48 MHz precise clock) | YES | NO + * SYSCLK(MHz) | 168 + * AHBCLK (MHz) | 168 + * APB1CLK (MHz) | 42 + * APB2CLK (MHz) | 84 + * USB capable | YES *----------------------------------------------------------------------------- **/ #include "stm32f4xx.h" - +#include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ @@ -44,16 +39,20 @@ This value must be a multiple of 0x200. */ -/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ -#define USE_PLL_HSE_EXTC (1) /* Use external clock */ -#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ +#if ((CLOCK_SOURCE) & USE_PLL_HSI) uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + /** * @brief Setup the microcontroller system @@ -110,20 +109,23 @@ void SystemInit(void) */ void SetSysClock(void) { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ -#if USE_PLL_HSE_EXTC != 0 if (SetSysClock_PLL_HSE(1) == 0) #endif { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) /* 2- If fail try to start with HSE and external xtal */ -#if USE_PLL_HSE_XTAL != 0 if (SetSysClock_PLL_HSE(0) == 0) #endif { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) { + if (SetSysClock_PLL_HSI() == 0) +#endif + { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + MBED_ASSERT(1); } } } @@ -133,14 +135,14 @@ void SetSysClock(void) //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz } -#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; /* The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency, to update the voltage scaling value @@ -186,15 +188,16 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 1; // OK } -#endif +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ +#if ((CLOCK_SOURCE) & USE_PLL_HSI) /******************************************************************************/ /* PLL (clocked by HSI) used as System clock source */ /******************************************************************************/ uint8_t SetSysClock_PLL_HSI(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; /* The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency, to update the voltage scaling value @@ -232,3 +235,4 @@ uint8_t SetSysClock_PLL_HSI(void) return 1; // OK } +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S new file mode 100644 index 0000000000..57738bbdc3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/startup_stm32f407xx.S @@ -0,0 +1,636 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and RNG + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf new file mode 100644 index 0000000000..a45f159055 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_IAR/stm32f407xx.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000187; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000188; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x7000; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block HEAP, block CSTACK }; diff --git a/targets/targets.json b/targets/targets.json index 6adc2b076f..5cf3ce2580 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1550,10 +1550,18 @@ "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"], - "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], + "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI", + "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + } + }, "macros_add": ["USB_STM_HAL"], "overrides": {"lse_available": 0}, "device_has_add": ["ANALOGOUT"], + "release_versions": ["2", "5"], "device_name": "STM32F407VG" }, "DISCO_F429ZI": { From b2ef8fc667bdc773e2eea152502410919eec462c Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 15 Dec 2017 14:45:11 +0100 Subject: [PATCH 006/133] STM32F2: Add Flash API support --- .../TARGET_NUCLEO_F207ZG/device/flash_data.h | 54 ++++ targets/TARGET_STM/TARGET_STM32F2/flash_api.c | 268 ++++++++++++++++++ targets/TARGET_STM/TARGET_STM32F2/objects.h | 7 + targets/targets.json | 2 +- 4 files changed, 330 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/flash_data.h create mode 100644 targets/TARGET_STM/TARGET_STM32F2/flash_api.c diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/flash_data.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/flash_data.h new file mode 100644 index 0000000000..f39e40d693 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/flash_data.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include + +#if DEVICE_FLASH + +#define FLASH_SIZE ((uint32_t)0x100000) + +/* Base address of the Flash sectors */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c new file mode 100644 index 0000000000..e4953e7d38 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c @@ -0,0 +1,268 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #if DEVICE_FLASH + +#include "flash_api.h" +#include "flash_data.h" +#include "platform/mbed_critical.h" + +static uint32_t GetSector(uint32_t Address); +static uint32_t GetSectorSize(uint32_t Sector); + +/** Initialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +/** Uninitialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +static int32_t flash_unlock(void) +{ + /* Allow Access to Flash control registers and user Falsh */ + if (HAL_FLASH_Unlock()) { + return -1; + } else { + return 0; + } +} + +static int32_t flash_lock(void) +{ + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + if (HAL_FLASH_Lock()) { + return -1; + } else { + return 0; + } +} + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + static FLASH_EraseInitTypeDef EraseInitStruct; + uint32_t FirstSector; + uint32_t SectorError = 0; + int32_t status = 0; + + if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Get the 1st sector to erase */ + FirstSector = GetSector(address); + + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; + EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; + EraseInitStruct.Sector = FirstSector; + EraseInitStruct.NbSectors = 1; + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { + status = -1; + } + + flash_lock(); + + return status; +} + +/** Program one page starting at defined address + * + * The page should be at page boundary, should not cross multiple sectors. + * This function does not do any check for address alignments or if size + * is aligned to a page size. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int32_t status = 0; + + if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + return -1; + } + + if (flash_unlock() != HAL_OK) { + return -1; + } + + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + + __HAL_FLASH_DATA_CACHE_RESET(); + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + __HAL_FLASH_DATA_CACHE_ENABLE(); + + while ((size > 0) && (status == 0)) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) { + status = -1; + } else { + size--; + address++; + data++; + } + } + + flash_lock(); + + return status; +} + +/** Get sector size + * + * @param obj The flash object + * @param address The sector starting address + * @return The size of a sector (in our case considering 1 sector = 1 page) + */ +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + return MBED_FLASH_INVALID_SIZE; + } else { + return (GetSectorSize(GetSector(address))); + } +} + +/** Get page size + * + * @param obj The flash object + * @param address The page starting address + * @return The size of a page (in our case the minimum programmable size) + */ +uint32_t flash_get_page_size(const flash_t *obj) +{ + // Flash of STM32F2 devices can be programed 1 byte at a time + return 1; +} + +/** Get start address for the flash region + * + * @param obj The flash object + * @return The start address for the flash region + */ +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +/** Get the flash region size + * + * @param obj The flash object + * @return The flash region size + */ +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +/** + * @brief Gets the sector of a given address + * @param None + * @retval The sector of a given address + */ +static uint32_t GetSector(uint32_t address) +{ + uint32_t sector = 0; + uint32_t tmp = address - ADDR_FLASH_SECTOR_0; + /* This function supports 1Mb and 2Mb flash sizes */ +#if defined(ADDR_FLASH_SECTOR_16) + if (address & 0x100000) { // handle 2nd bank + /* Sector will be at least 12 */ + sector = FLASH_SECTOR_12; + tmp -= 0x100000; + address -= 0x100000; + } +#endif + if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize + sector += tmp >>14; + } +#if defined(ADDR_FLASH_SECTOR_5) + else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size + sector += FLASH_SECTOR_4; + } else { + sector += 4 + (tmp >>17); + } +#else + // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one. + else { //64k sector size + sector += FLASH_SECTOR_4; + } +#endif + return sector; +} + +/** + * @brief Gets sector Size + * @param None + * @retval The size of a given sector + */ +static uint32_t GetSectorSize(uint32_t Sector) +{ + uint32_t sectorsize = 0x00; +#if defined(FLASH_SECTOR_16) + if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ + (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\ + (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { + sectorsize = 16 * 1024; + } else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) { +#else +if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ + (Sector == FLASH_SECTOR_3)) { + sectorsize = 16 * 1024; + } else if(Sector == FLASH_SECTOR_4) { +#endif + sectorsize = 64 * 1024; + } else { + sectorsize = 128 * 1024; + } + return sectorsize; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h index a961a63a44..7359e18a6c 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h @@ -145,6 +145,13 @@ struct can_s { }; #endif +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + #define GPIO_IP_WITHOUT_BRR #include "gpio_object.h" diff --git a/targets/targets.json b/targets/targets.json index 5cf3ce2580..e75f1f59fb 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -903,7 +903,7 @@ }, "detect_code": ["0835"], "macros_add": ["USBHOST_OTHER"], - "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC"], + "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], "device_name": "STM32F207ZG" From 6c3a1cb6e9869f3826a9612a3b5df9138b2c4f19 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 18 Dec 2017 15:38:35 +0100 Subject: [PATCH 007/133] STM32F2: Remove flash functions doc --- targets/TARGET_STM/TARGET_STM32F2/flash_api.c | 76 ++++--------------- 1 file changed, 13 insertions(+), 63 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c index e4953e7d38..321647cf09 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c @@ -23,26 +23,6 @@ static uint32_t GetSector(uint32_t Address); static uint32_t GetSectorSize(uint32_t Sector); -/** Initialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_init(flash_t *obj) -{ - return 0; -} - -/** Uninitialize the flash peripheral and the flash_t object - * - * @param obj The flash object - * @return 0 for success, -1 for error - */ -int32_t flash_free(flash_t *obj) -{ - return 0; -} - static int32_t flash_unlock(void) { /* Allow Access to Flash control registers and user Falsh */ @@ -64,13 +44,16 @@ static int32_t flash_lock(void) } } -/** Erase one sector starting at defined address - * - * The address should be at sector boundary. This function does not do any check for address alignments - * @param obj The flash object - * @param address The sector starting address - * @return 0 for success, -1 for error - */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + int32_t flash_erase_sector(flash_t *obj, uint32_t address) { static FLASH_EraseInitTypeDef EraseInitStruct; @@ -104,17 +87,6 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return status; } -/** Program one page starting at defined address - * - * The page should be at page boundary, should not cross multiple sectors. - * This function does not do any check for address alignments or if size - * is aligned to a page size. - * @param obj The flash object - * @param address The sector starting address - * @param data The data buffer to be programmed - * @param size The number of bytes to program - * @return 0 for success, -1 for error - */ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) { int32_t status = 0; @@ -155,13 +127,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, return status; } -/** Get sector size - * - * @param obj The flash object - * @param address The sector starting address - * @return The size of a sector (in our case considering 1 sector = 1 page) - */ -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { return MBED_FLASH_INVALID_SIZE; @@ -170,34 +136,18 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) } } -/** Get page size - * - * @param obj The flash object - * @param address The page starting address - * @return The size of a page (in our case the minimum programmable size) - */ uint32_t flash_get_page_size(const flash_t *obj) { // Flash of STM32F2 devices can be programed 1 byte at a time return 1; } -/** Get start address for the flash region - * - * @param obj The flash object - * @return The start address for the flash region - */ -uint32_t flash_get_start_address(const flash_t *obj) +uint32_t flash_get_start_address(const flash_t *obj) { return FLASH_BASE; } -/** Get the flash region size - * - * @param obj The flash object - * @return The flash region size - */ -uint32_t flash_get_size(const flash_t *obj) +uint32_t flash_get_size(const flash_t *obj) { return FLASH_SIZE; } From ddeea847c6ea1547d7036eea302fa5bc8a485b00 Mon Sep 17 00:00:00 2001 From: Bartek Szatkowski Date: Wed, 27 Dec 2017 14:46:00 +0000 Subject: [PATCH 008/133] Add notes about ISR safety to RTOS doxygen --- rtos/ConditionVariable.h | 17 +++++++++++- rtos/EventFlags.h | 21 ++++++++++++++- rtos/Mail.h | 19 +++++++++++++- rtos/MemoryPool.h | 15 +++++++++-- rtos/Mutex.h | 22 +++++++++++++++- rtos/Queue.h | 18 +++++++++++-- rtos/RtosTimer.h | 14 ++++++++++ rtos/Semaphore.h | 12 +++++++++ rtos/Thread.h | 57 +++++++++++++++++++++++++++++++++++++--- 9 files changed, 184 insertions(+), 11 deletions(-) diff --git a/rtos/ConditionVariable.h b/rtos/ConditionVariable.h index dd091ec3d4..6debad61a3 100644 --- a/rtos/ConditionVariable.h +++ b/rtos/ConditionVariable.h @@ -118,7 +118,10 @@ struct Waiter; */ class ConditionVariable : private mbed::NonCopyable { public: - /** Create and Initialize a ConditionVariable object */ + /** Create and Initialize a ConditionVariable object + * + * @note This function may be called from ISR context. + */ ConditionVariable(Mutex &mutex); /** Wait for a notification @@ -142,6 +145,8 @@ public: * * mutex.unlock(); * @endcode + * + * @note This function cannot be called from ISR context. */ void wait(); @@ -176,21 +181,31 @@ public: * * mutex.unlock(); * @endcode + * + * @note This function cannot be called from ISR context. */ bool wait_for(uint32_t millisec); /** Notify one waiter on this condition variable that a condition changed. * * @note - The thread calling this function must be the owner of the ConditionVariable's mutex + * + * @note This function may be called from ISR context. */ void notify_one(); /** Notify all waiters on this condition variable that a condition changed. * * @note - The thread calling this function must be the owner of the ConditionVariable's mutex + * + * @note This function may be called from ISR context. */ void notify_all(); + /** ConditionVariable destructor + * + * @note This function may be called from ISR context. + */ ~ConditionVariable(); protected: diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index 5beb5e5ef1..291b7112d5 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -46,29 +46,40 @@ namespace rtos { */ class EventFlags : private mbed::NonCopyable { public: - /** Create and Initialize a EventFlags object */ + /** Create and Initialize a EventFlags object + * + * @note This function cannot be called from ISR context. + */ EventFlags(); /** Create and Initialize a EventFlags object @param name name to be used for this EventFlags. It has to stay allocated for the lifetime of the thread. + + @note This function cannot be called from ISR context. */ EventFlags(const char *name); /** Set the specified Event Flags. @param flags specifies the flags that shall be set. @return event flags after setting or error code if highest bit set (@a osFlagsError). + + @note This function may be called from ISR context. */ uint32_t set(uint32_t flags); /** Clear the specified Event Flags. @param flags specifies the flags that shall be cleared. (default: 0x7fffffff - all flags) @return event flags before clearing or error code if highest bit set (@a osFlagsError). + + @note This function may be called from ISR context. */ uint32_t clear(uint32_t flags = 0x7fffffff); /** Get the currently set Event Flags. @return set event flags. + + @note This function may be called from ISR context. */ uint32_t get() const; @@ -77,6 +88,8 @@ public: @param timeout timeout value or 0 in case of no time-out. (default: osWaitForever) @param clear specifies wether to clear the flags after waiting for them. (default: true) @return event flags before clearing or error code if highest bit set (@a osFlagsError). + + @note This function may be called from ISR context if the timeout parameter is set to 0. */ uint32_t wait_all(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true); @@ -85,9 +98,15 @@ public: @param timeout timeout value or 0 in case of no time-out. (default: osWaitForever) @param clear specifies wether to clear the flags after waiting for them. (default: true) @return event flags before clearing or error code if highest bit set (@a osFlagsError). + + @note This function may be called from ISR context if the timeout parameter is set to 0. */ uint32_t wait_any(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true); + /** Event flags destructor + + @note This function cannot be called from ISR context. + */ ~EventFlags(); private: diff --git a/rtos/Mail.h b/rtos/Mail.h index c9ae7f372f..7c1ebd88af 100644 --- a/rtos/Mail.h +++ b/rtos/Mail.h @@ -55,12 +55,17 @@ namespace rtos { template class Mail : private mbed::NonCopyable > { public: - /** Create and Initialise Mail queue. */ + /** Create and Initialise Mail queue. + * + * @note This function cannot be called from ISR context. + */ Mail() { }; /** Check if the mail queue is empty * * @return True if the mail queue is empty, false if not + * + * @note This function may be called from ISR context. */ bool empty() const { return _queue.empty(); @@ -69,6 +74,8 @@ public: /** Check if the mail queue is full * * @return True if the mail queue is full, false if not + * + * @note This function may be called from ISR context. */ bool full() const { return _queue.full(); @@ -77,6 +84,8 @@ public: /** Allocate a memory block of type T @param millisec timeout value or 0 in case of no time-out. (default: 0). @return pointer to memory block that can be filled with mail or NULL in case error. + + @note This function may be called from ISR context if the millisec parameter is set to 0. */ T* alloc(uint32_t millisec=0) { return _pool.alloc(); @@ -85,6 +94,8 @@ public: /** Allocate a memory block of type T and set memory block to zero. @param millisec timeout value or 0 in case of no time-out. (default: 0). @return pointer to memory block that can be filled with mail or NULL in case error. + + @note This function may be called from ISR context if the millisec parameter is set to 0. */ T* calloc(uint32_t millisec=0) { return _pool.calloc(); @@ -93,6 +104,8 @@ public: /** Put a mail in the queue. @param mptr memory block previously allocated with Mail::alloc or Mail::calloc. @return status code that indicates the execution status of the function. + + @note This function may be called from ISR context. */ osStatus put(T *mptr) { return _queue.put(mptr); @@ -101,6 +114,8 @@ public: /** Get a mail from a queue. @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return event that contains mail information or error code. + + @note This function may be called from ISR context if the millisec parameter is set to 0. */ osEvent get(uint32_t millisec=osWaitForever) { osEvent evt = _queue.get(millisec); @@ -113,6 +128,8 @@ public: /** Free a memory block from a mail. @param mptr pointer to the memory block that was obtained with Mail::get. @return status code that indicates the execution status of the function. + + @note This function may be called from ISR context. */ osStatus free(T *mptr) { return _pool.free(mptr); diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h index d76a99e794..a145a0cdbb 100644 --- a/rtos/MemoryPool.h +++ b/rtos/MemoryPool.h @@ -50,7 +50,10 @@ template class MemoryPool : private mbed::NonCopyable > { MBED_STATIC_ASSERT(pool_sz > 0, "Invalid memory pool size. Must be greater than 0."); public: - /** Create and Initialize a memory pool. */ + /** Create and Initialize a memory pool. + * + * @note This function cannot be called from ISR context. + */ MemoryPool() { memset(_pool_mem, 0, sizeof(_pool_mem)); memset(&_obj_mem, 0, sizeof(_obj_mem)); @@ -63,13 +66,18 @@ public: MBED_ASSERT(_id); } - /** Destroy a memory pool */ + /** Destroy a memory pool + * + * @note This function cannot be called from ISR context. + */ ~MemoryPool() { osMemoryPoolDelete(_id); } /** Allocate a memory block of type T from a memory pool. @return address of the allocated memory block or NULL in case of no memory available. + + @note This function may be called from ISR context. */ T* alloc(void) { return (T*)osMemoryPoolAlloc(_id, 0); @@ -77,6 +85,8 @@ public: /** Allocate a memory block of type T from a memory pool and set memory block to zero. @return address of the allocated memory block or NULL in case of no memory available. + + @note This function may be called from ISR context. */ T* calloc(void) { T *item = (T*)osMemoryPoolAlloc(_id, 0); @@ -92,6 +102,7 @@ public: is NULL or invalid, or osErrorResource if given memory block is in an invalid memory pool state. + @note This function may be called from ISR context. */ osStatus free(T *block) { return osMemoryPoolFree(_id, (void*)block); diff --git a/rtos/Mutex.h b/rtos/Mutex.h index 1b9e22a27f..a453ff5be9 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -40,18 +40,26 @@ namespace rtos { /** The Mutex class is used to synchronize the execution of threads. This is for example used to protect access to a shared resource. + @note Member functions of this class cannot be used in ISR context. If you require Mutex functionality within + ISR handler consider using @a Semaphore. + @note Memory considerations: The mutex control structures will be created on current thread's stack, both for the mbed OS and underlying RTOS objects (static or dynamic RTOS memory pools are not being used). */ class Mutex : private mbed::NonCopyable { public: - /** Create and Initialize a Mutex object */ + /** Create and Initialize a Mutex object + * + * @note This function cannot be called from ISR context. + */ Mutex(); /** Create and Initialize a Mutex object @param name name to be used for this mutex. It has to stay allocated for the lifetime of the thread. + + @note This function cannot be called from ISR context. */ Mutex(const char *name); @@ -63,11 +71,15 @@ public: @a osErrorParameter internal error. @a osErrorResource the mutex could not be obtained when no timeout was specified. @a osErrorISR this function cannot be called from the interrupt service routine. + + @note This function cannot be called from ISR context. */ osStatus lock(uint32_t millisec=osWaitForever); /** Try to lock the mutex, and return immediately @return true if the mutex was acquired, false otherwise. + + @note This function cannot be called from ISR context. */ bool trylock(); @@ -77,14 +89,22 @@ public: @a osErrorParameter internal error. @a osErrorResource the mutex was not locked or the current thread wasn't the owner. @a osErrorISR this function cannot be called from the interrupt service routine. + + @note This function cannot be called from ISR context. */ osStatus unlock(); /** Get the owner the this mutex @return the current owner of this mutex. + + @note This function cannot be called from ISR context. */ osThreadId get_owner(); + /** Mutex destructor + * + * @note This function cannot be called from ISR context. + */ ~Mutex(); private: diff --git a/rtos/Queue.h b/rtos/Queue.h index 67a04653db..d07d384e5d 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -52,7 +52,10 @@ namespace rtos { template class Queue : private mbed::NonCopyable > { public: - /** Create and initialize a message Queue. */ + /** Create and initialize a message Queue. + * + * @note This function cannot be called from ISR context. + */ Queue() { memset(&_obj_mem, 0, sizeof(_obj_mem)); osMessageQueueAttr_t attr = { 0 }; @@ -63,7 +66,10 @@ public: _id = osMessageQueueNew(queue_sz, sizeof(T*), &attr); MBED_ASSERT(_id); } - + /** Queue destructor + * + * @note This function cannot be called from ISR context. + */ ~Queue() { osMessageQueueDelete(_id); } @@ -71,6 +77,8 @@ public: /** Check if the queue is empty * * @return True if the queue is empty, false if not + * + * @note This function may be called from ISR context. */ bool empty() const { return osMessageQueueGetCount(_id) == 0; @@ -79,6 +87,8 @@ public: /** Check if the queue is full * * @return True if the queue is full, false if not + * + * @note This function may be called from ISR context. */ bool full() const { return osMessageQueueGetSpace(_id) == 0; @@ -93,6 +103,8 @@ public: @a osErrorTimeout the message could not be put into the queue in the given time. @a osErrorResource not enough space in the queue. @a osErrorParameter internal error or non-zero timeout specified in an ISR. + + @note This function may be called from ISR context if the millisec parameter is set to 0. */ osStatus put(T* data, uint32_t millisec=0, uint8_t prio=0) { return osMessageQueuePut(_id, &data, prio, millisec); @@ -106,6 +118,8 @@ public: @a osOK no message is available in the queue and no timeout was specified. @a osEventTimeout no message has arrived during the given timeout period. @a osErrorParameter a parameter is invalid or outside of a permitted range. + + @note This function may be called from ISR context if the millisec parameter is set to 0. */ osEvent get(uint32_t millisec=osWaitForever) { osEvent event; diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h index c5e6276468..fd4a9396cb 100644 --- a/rtos/RtosTimer.h +++ b/rtos/RtosTimer.h @@ -93,6 +93,8 @@ public: @deprecated Replaced with RtosTimer(Callback, os_timer_type) @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details + + @note This function cannot be called from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Replaced with RtosTimer(Callback, os_timer_type)") @@ -107,6 +109,8 @@ public: @param type osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic) @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details + + @note This function cannot be called from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.2", "The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details") @@ -123,6 +127,8 @@ public: RtosTimer(callback(obj, method), os_timer_type). @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details + + @note This function cannot be called from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -140,6 +146,8 @@ public: @a osErrorISR @a stop cannot be called from interrupt service routines. @a osErrorParameter internal error. @a osErrorResource the timer is not running. + + @note This function cannot be called from ISR context. */ osStatus stop(void); @@ -150,9 +158,15 @@ public: @a osErrorISR @a start cannot be called from interrupt service routines. @a osErrorParameter internal error or incorrect parameter value. @a osErrorResource internal error (the timer is in an invalid timer state). + + @note This function cannot be called from ISR context. */ osStatus start(uint32_t millisec); + /** RtosTimer destructor + * + * @note This function cannot be called from ISR context. + */ ~RtosTimer(); private: diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index 88b479c5e4..a374bccf21 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -46,18 +46,24 @@ class Semaphore : private mbed::NonCopyable { public: /** Create and Initialize a Semaphore object used for managing resources. @param count number of available resources; maximum index value is (count-1). (default: 0). + + @note This function cannot be called from ISR context. */ Semaphore(int32_t count=0); /** Create and Initialize a Semaphore object used for managing resources. @param count number of available resources @param max_count maximum number of available resources + + @note This function cannot be called from ISR context. */ Semaphore(int32_t count, uint16_t max_count); /** Wait until a Semaphore resource becomes available. @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return number of available tokens, before taking one; or -1 in case of incorrect parameters + + @note This function may be called from ISR context if the millisec parameter is set to 0. */ int32_t wait(uint32_t millisec=osWaitForever); @@ -66,9 +72,15 @@ public: @a osOK the token has been correctly released. @a osErrorResource the maximum token count has been reached. @a osErrorParameter internal error. + + @note This function may be called from ISR context. */ osStatus release(void); + /** Semaphore destructor + * + * @note This function cannot be called from ISR context. + */ ~Semaphore(); private: diff --git a/rtos/Thread.h b/rtos/Thread.h index d67ad3acf8..dd3957e8de 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -80,6 +80,8 @@ public: @param stack_size stack size (in bytes) requirements for the thread function. (default: OS_STACK_SIZE). @param stack_mem pointer to the stack area to be used by this thread (default: NULL). @param name name to be used for this thread. It has to stay allocated for the lifetime of the thread (default: NULL) + + @note This function cannot be called from ISR context. */ Thread(osPriority priority=osPriorityNormal, uint32_t stack_size=OS_STACK_SIZE, @@ -103,6 +105,8 @@ public: error("oh no!"); } @endcode + + @note This function cannot be called from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Thread-spawning constructors hide errors. " @@ -131,6 +135,8 @@ public: error("oh no!"); } @endcode + + @note This function cannot be called from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -161,6 +167,8 @@ public: error("oh no!"); } @endcode + + @note This function cannot be called from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -192,6 +200,8 @@ public: error("oh no!"); } @endcode + + @note This function cannot be called from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Thread-spawning constructors hide errors. " @@ -208,6 +218,8 @@ public: @param task function to be executed by this thread. @return status code that indicates the execution status of the function. @note a thread can only be started once + + @note This function cannot be called from ISR context. */ osStatus start(mbed::Callback task); @@ -217,6 +229,8 @@ public: @return status code that indicates the execution status of the function. @deprecated The start function does not support cv-qualifiers. Replaced by start(callback(obj, method)). + + @note This function cannot be called from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -229,28 +243,38 @@ public: /** Wait for thread to terminate @return status code that indicates the execution status of the function. @note not callable from interrupt + + @note This function cannot be called from ISR context. */ osStatus join(); /** Terminate execution of a thread and remove it from Active Threads @return status code that indicates the execution status of the function. + + @note This function cannot be called from ISR context. */ osStatus terminate(); /** Set priority of an active thread @param priority new priority value for the thread function. @return status code that indicates the execution status of the function. + + @note This function cannot be called from ISR context. */ osStatus set_priority(osPriority priority); /** Get priority of an active thread @return current priority value of the thread function. + + @note This function cannot be called from ISR context. */ osPriority get_priority(); /** Set the specified Thread Flags for the thread. @param signals specifies the signal flags of the thread that should be set. @return signal flags after setting or osFlagsError in case of incorrect parameters. + + @note This function may be called from ISR context. */ int32_t signal_set(int32_t signals); @@ -279,37 +303,51 @@ public: /** State of this Thread @return the State of this Thread + + @note This function cannot be called from ISR context. */ State get_state(); /** Get the total stack memory size for this Thread @return the total stack memory size in bytes + + @note This function cannot be called from ISR context. */ uint32_t stack_size(); /** Get the currently unused stack memory for this Thread @return the currently unused stack memory in bytes + + @note This function cannot be called from ISR context. */ uint32_t free_stack(); /** Get the currently used stack memory for this Thread @return the currently used stack memory in bytes + + @note This function cannot be called from ISR context. */ uint32_t used_stack(); /** Get the maximum stack memory usage to date for this Thread @return the maximum stack memory usage to date in bytes + + @note This function cannot be called from ISR context. */ uint32_t max_stack(); /** Get thread name @return thread name or NULL if the name was not set. + + @note This function may be called from ISR context. */ const char *get_name(); /** Clears the specified Thread Flags of the currently running thread. @param signals specifies the signal flags of the thread that should be cleared. @return signal flags before clearing or osFlagsError in case of incorrect parameters. + + @note This function cannot be called from ISR context. */ static int32_t signal_clr(int32_t signals); @@ -317,38 +355,51 @@ public: @param signals wait until all specified signal flags are set or 0 for any single signal flag. @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return event flag information or error code. @note if @a millisec is set to 0 and flag is no set the event carries osOK value. - @note not callable from interrupt + + @note This function cannot be called from ISR context. */ static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever); /** Wait for a specified time period in millisec: @param millisec time delay value @return status code that indicates the execution status of the function. - @note not callable from interrupt + + @note This function cannot be called from ISR context. */ static osStatus wait(uint32_t millisec); /** Pass control to next thread that is in state READY. @return status code that indicates the execution status of the function. - @note not callable from interrupt + + @note This function cannot be called from ISR context. */ static osStatus yield(); /** Get the thread id of the current running thread. @return thread ID for reference by other functions or NULL in case of error. + + @note This function may be called from ISR context. */ static osThreadId gettid(); /** Attach a function to be called by the RTOS idle task @param fptr pointer to the function to be called + + @note This function may be called from ISR context. */ static void attach_idle_hook(void (*fptr)(void)); /** Attach a function to be called when a task is killed @param fptr pointer to the function to be called + + @note This function may be called from ISR context. */ static void attach_terminate_hook(void (*fptr)(osThreadId id)); + /** Thread destructor + * + * @note This function cannot be called from ISR context. + */ virtual ~Thread(); private: From ad14bfde4e90966bc1e967a69d4e2e07406befe9 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:36:24 -0600 Subject: [PATCH 009/133] Copy edit ConditionVariable.h Copy edit docs changes for active voice. --- rtos/ConditionVariable.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/rtos/ConditionVariable.h b/rtos/ConditionVariable.h index 6debad61a3..c69722d897 100644 --- a/rtos/ConditionVariable.h +++ b/rtos/ConditionVariable.h @@ -120,7 +120,7 @@ class ConditionVariable : private mbed::NonCopyable { public: /** Create and Initialize a ConditionVariable object * - * @note This function may be called from ISR context. + * @note You may call this function from ISR context. */ ConditionVariable(Mutex &mutex); @@ -146,7 +146,7 @@ public: * mutex.unlock(); * @endcode * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ void wait(); @@ -182,7 +182,7 @@ public: * mutex.unlock(); * @endcode * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ bool wait_for(uint32_t millisec); @@ -204,7 +204,7 @@ public: /** ConditionVariable destructor * - * @note This function may be called from ISR context. + * @note You may call this function from ISR context. */ ~ConditionVariable(); From 9c5536112e9639c27ed80bcf2e01fe28e0eefc16 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:38:48 -0600 Subject: [PATCH 010/133] Copy edit EventFlags.h Copy edit file for active voice and agreement. --- rtos/EventFlags.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index 291b7112d5..0571ec7b85 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -46,9 +46,9 @@ namespace rtos { */ class EventFlags : private mbed::NonCopyable { public: - /** Create and Initialize a EventFlags object + /** Create and Initialize an EventFlags object * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ EventFlags(); @@ -56,7 +56,7 @@ public: @param name name to be used for this EventFlags. It has to stay allocated for the lifetime of the thread. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ EventFlags(const char *name); @@ -72,14 +72,14 @@ public: @param flags specifies the flags that shall be cleared. (default: 0x7fffffff - all flags) @return event flags before clearing or error code if highest bit set (@a osFlagsError). - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ uint32_t clear(uint32_t flags = 0x7fffffff); /** Get the currently set Event Flags. @return set event flags. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ uint32_t get() const; @@ -89,7 +89,7 @@ public: @param clear specifies wether to clear the flags after waiting for them. (default: true) @return event flags before clearing or error code if highest bit set (@a osFlagsError). - @note This function may be called from ISR context if the timeout parameter is set to 0. + @note You may call this function from ISR context if the timeout parameter is set to 0. */ uint32_t wait_all(uint32_t flags = 0, uint32_t timeout = osWaitForever, bool clear = true); @@ -105,7 +105,7 @@ public: /** Event flags destructor - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ ~EventFlags(); From bdc21ed97851b7d3e0722c6e9e0beb32f354fba3 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:41:37 -0600 Subject: [PATCH 011/133] Copy edit Mail.h Copy edit file for active voice and American English. --- rtos/Mail.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/rtos/Mail.h b/rtos/Mail.h index 7c1ebd88af..c0fdc76fc4 100644 --- a/rtos/Mail.h +++ b/rtos/Mail.h @@ -55,9 +55,9 @@ namespace rtos { template class Mail : private mbed::NonCopyable > { public: - /** Create and Initialise Mail queue. + /** Create and Initialize Mail queue. * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ Mail() { }; @@ -65,7 +65,7 @@ public: * * @return True if the mail queue is empty, false if not * - * @note This function may be called from ISR context. + * @note You may call this function from ISR context. */ bool empty() const { return _queue.empty(); @@ -75,7 +75,7 @@ public: * * @return True if the mail queue is full, false if not * - * @note This function may be called from ISR context. + * @note You may call this function from ISR context. */ bool full() const { return _queue.full(); @@ -85,7 +85,7 @@ public: @param millisec timeout value or 0 in case of no time-out. (default: 0). @return pointer to memory block that can be filled with mail or NULL in case error. - @note This function may be called from ISR context if the millisec parameter is set to 0. + @note You may call this function from ISR context if the millisec parameter is set to 0. */ T* alloc(uint32_t millisec=0) { return _pool.alloc(); @@ -95,7 +95,7 @@ public: @param millisec timeout value or 0 in case of no time-out. (default: 0). @return pointer to memory block that can be filled with mail or NULL in case error. - @note This function may be called from ISR context if the millisec parameter is set to 0. + @note You may call this function from ISR context if the millisec parameter is set to 0. */ T* calloc(uint32_t millisec=0) { return _pool.calloc(); @@ -105,7 +105,7 @@ public: @param mptr memory block previously allocated with Mail::alloc or Mail::calloc. @return status code that indicates the execution status of the function. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ osStatus put(T *mptr) { return _queue.put(mptr); @@ -115,7 +115,7 @@ public: @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return event that contains mail information or error code. - @note This function may be called from ISR context if the millisec parameter is set to 0. + @note You may call this function from ISR context if the millisec parameter is set to 0. */ osEvent get(uint32_t millisec=osWaitForever) { osEvent evt = _queue.get(millisec); @@ -129,7 +129,7 @@ public: @param mptr pointer to the memory block that was obtained with Mail::get. @return status code that indicates the execution status of the function. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ osStatus free(T *mptr) { return _pool.free(mptr); From 9dfa3bda4bb6bc80ee9506c9ca325c6284359b34 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:43:45 -0600 Subject: [PATCH 012/133] Copy edit MemoryPool.h Copy edit file for active voice. --- rtos/MemoryPool.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h index a145a0cdbb..bfcd392ecc 100644 --- a/rtos/MemoryPool.h +++ b/rtos/MemoryPool.h @@ -52,7 +52,7 @@ class MemoryPool : private mbed::NonCopyable > { public: /** Create and Initialize a memory pool. * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ MemoryPool() { memset(_pool_mem, 0, sizeof(_pool_mem)); @@ -68,7 +68,7 @@ public: /** Destroy a memory pool * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ ~MemoryPool() { osMemoryPoolDelete(_id); @@ -77,7 +77,7 @@ public: /** Allocate a memory block of type T from a memory pool. @return address of the allocated memory block or NULL in case of no memory available. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ T* alloc(void) { return (T*)osMemoryPoolAlloc(_id, 0); @@ -86,7 +86,7 @@ public: /** Allocate a memory block of type T from a memory pool and set memory block to zero. @return address of the allocated memory block or NULL in case of no memory available. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ T* calloc(void) { T *item = (T*)osMemoryPoolAlloc(_id, 0); @@ -102,7 +102,7 @@ public: is NULL or invalid, or osErrorResource if given memory block is in an invalid memory pool state. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ osStatus free(T *block) { return osMemoryPoolFree(_id, (void*)block); From b6a1662790db29ac5078cc1c48538c961dba5f6d Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:46:08 -0600 Subject: [PATCH 013/133] Copy edit Mutex.h Copy edit file for active voice. --- rtos/Mutex.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/rtos/Mutex.h b/rtos/Mutex.h index a453ff5be9..4273d14722 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -40,8 +40,8 @@ namespace rtos { /** The Mutex class is used to synchronize the execution of threads. This is for example used to protect access to a shared resource. - @note Member functions of this class cannot be used in ISR context. If you require Mutex functionality within - ISR handler consider using @a Semaphore. + @note You cannot use member functions of this class in ISR context. If you require Mutex functionality within + ISR handler, consider using @a Semaphore. @note Memory considerations: The mutex control structures will be created on current thread's stack, both for the mbed OS @@ -51,7 +51,7 @@ class Mutex : private mbed::NonCopyable { public: /** Create and Initialize a Mutex object * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ Mutex(); @@ -59,7 +59,7 @@ public: @param name name to be used for this mutex. It has to stay allocated for the lifetime of the thread. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ Mutex(const char *name); @@ -72,7 +72,7 @@ public: @a osErrorResource the mutex could not be obtained when no timeout was specified. @a osErrorISR this function cannot be called from the interrupt service routine. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osStatus lock(uint32_t millisec=osWaitForever); @@ -97,13 +97,13 @@ public: /** Get the owner the this mutex @return the current owner of this mutex. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osThreadId get_owner(); /** Mutex destructor * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ ~Mutex(); From 06b8b8ccffc0634b5cd0415bb5c97d73e15c4d3e Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:48:11 -0600 Subject: [PATCH 014/133] Copy edit Queue.h Copy edit file for active voice. --- rtos/Queue.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/rtos/Queue.h b/rtos/Queue.h index d07d384e5d..0190c047f8 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -54,7 +54,7 @@ class Queue : private mbed::NonCopyable > { public: /** Create and initialize a message Queue. * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ Queue() { memset(&_obj_mem, 0, sizeof(_obj_mem)); @@ -68,7 +68,7 @@ public: } /** Queue destructor * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ ~Queue() { osMessageQueueDelete(_id); @@ -78,7 +78,7 @@ public: * * @return True if the queue is empty, false if not * - * @note This function may be called from ISR context. + * @note You may call this function from ISR context. */ bool empty() const { return osMessageQueueGetCount(_id) == 0; @@ -88,7 +88,7 @@ public: * * @return True if the queue is full, false if not * - * @note This function may be called from ISR context. + * @note You may call this function from ISR context. */ bool full() const { return osMessageQueueGetSpace(_id) == 0; @@ -104,7 +104,7 @@ public: @a osErrorResource not enough space in the queue. @a osErrorParameter internal error or non-zero timeout specified in an ISR. - @note This function may be called from ISR context if the millisec parameter is set to 0. + @note You may call this function from ISR context if the millisec parameter is set to 0. */ osStatus put(T* data, uint32_t millisec=0, uint8_t prio=0) { return osMessageQueuePut(_id, &data, prio, millisec); @@ -119,7 +119,7 @@ public: @a osEventTimeout no message has arrived during the given timeout period. @a osErrorParameter a parameter is invalid or outside of a permitted range. - @note This function may be called from ISR context if the millisec parameter is set to 0. + @note You may call this function from ISR context if the millisec parameter is set to 0. */ osEvent get(uint32_t millisec=osWaitForever) { osEvent event; From 6d77c7fc8e71426b22b78eaf84d46a758c48a2a0 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:50:38 -0600 Subject: [PATCH 015/133] Copy edit RtosTimer.h Copy edit file for active voice. --- rtos/RtosTimer.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h index fd4a9396cb..27e0c5aeee 100644 --- a/rtos/RtosTimer.h +++ b/rtos/RtosTimer.h @@ -94,7 +94,7 @@ public: @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Replaced with RtosTimer(Callback, os_timer_type)") @@ -110,7 +110,7 @@ public: @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.2", "The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details") @@ -128,7 +128,7 @@ public: @deprecated The RtosTimer has been superseded by the EventQueue. See RtosTimer.h for more details - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -147,7 +147,7 @@ public: @a osErrorParameter internal error. @a osErrorResource the timer is not running. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osStatus stop(void); @@ -159,13 +159,13 @@ public: @a osErrorParameter internal error or incorrect parameter value. @a osErrorResource internal error (the timer is in an invalid timer state). - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osStatus start(uint32_t millisec); /** RtosTimer destructor * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ ~RtosTimer(); From 5e289cba3b94d59e9baa251cb91b42a02b3e5bc6 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 17:52:40 -0600 Subject: [PATCH 016/133] Copy edit Semaphore.h Copy edit file for active voice. --- rtos/Semaphore.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index a374bccf21..e8fc22205a 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -47,7 +47,7 @@ public: /** Create and Initialize a Semaphore object used for managing resources. @param count number of available resources; maximum index value is (count-1). (default: 0). - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ Semaphore(int32_t count=0); @@ -55,7 +55,7 @@ public: @param count number of available resources @param max_count maximum number of available resources - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ Semaphore(int32_t count, uint16_t max_count); @@ -63,7 +63,7 @@ public: @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return number of available tokens, before taking one; or -1 in case of incorrect parameters - @note This function may be called from ISR context if the millisec parameter is set to 0. + @note You may call this function from ISR context if the millisec parameter is set to 0. */ int32_t wait(uint32_t millisec=osWaitForever); @@ -73,13 +73,13 @@ public: @a osErrorResource the maximum token count has been reached. @a osErrorParameter internal error. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ osStatus release(void); /** Semaphore destructor * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ ~Semaphore(); From 09f6c63219876491f56c28623471a0b849f41c70 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Mon, 8 Jan 2018 18:01:02 -0600 Subject: [PATCH 017/133] Copy edit Thread.h Copy edit file for active voice. --- rtos/Thread.h | 52 +++++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/rtos/Thread.h b/rtos/Thread.h index dd3957e8de..9f82ec0ed0 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -81,7 +81,7 @@ public: @param stack_mem pointer to the stack area to be used by this thread (default: NULL). @param name name to be used for this thread. It has to stay allocated for the lifetime of the thread (default: NULL) - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ Thread(osPriority priority=osPriorityNormal, uint32_t stack_size=OS_STACK_SIZE, @@ -106,7 +106,7 @@ public: } @endcode - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Thread-spawning constructors hide errors. " @@ -136,7 +136,7 @@ public: } @endcode - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -168,7 +168,7 @@ public: } @endcode - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -201,7 +201,7 @@ public: } @endcode - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ MBED_DEPRECATED_SINCE("mbed-os-5.1", "Thread-spawning constructors hide errors. " @@ -219,7 +219,7 @@ public: @return status code that indicates the execution status of the function. @note a thread can only be started once - @note This function cannot be called from ISR context. + @note You cannot call this function ISR context. */ osStatus start(mbed::Callback task); @@ -230,7 +230,7 @@ public: @deprecated The start function does not support cv-qualifiers. Replaced by start(callback(obj, method)). - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ template MBED_DEPRECATED_SINCE("mbed-os-5.1", @@ -244,14 +244,14 @@ public: @return status code that indicates the execution status of the function. @note not callable from interrupt - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osStatus join(); /** Terminate execution of a thread and remove it from Active Threads @return status code that indicates the execution status of the function. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osStatus terminate(); @@ -259,14 +259,14 @@ public: @param priority new priority value for the thread function. @return status code that indicates the execution status of the function. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osStatus set_priority(osPriority priority); /** Get priority of an active thread @return current priority value of the thread function. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ osPriority get_priority(); @@ -274,7 +274,7 @@ public: @param signals specifies the signal flags of the thread that should be set. @return signal flags after setting or osFlagsError in case of incorrect parameters. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ int32_t signal_set(int32_t signals); @@ -304,42 +304,42 @@ public: /** State of this Thread @return the State of this Thread - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ State get_state(); /** Get the total stack memory size for this Thread @return the total stack memory size in bytes - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ uint32_t stack_size(); /** Get the currently unused stack memory for this Thread @return the currently unused stack memory in bytes - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ uint32_t free_stack(); /** Get the currently used stack memory for this Thread @return the currently used stack memory in bytes - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ uint32_t used_stack(); /** Get the maximum stack memory usage to date for this Thread @return the maximum stack memory usage to date in bytes - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ uint32_t max_stack(); /** Get thread name @return thread name or NULL if the name was not set. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ const char *get_name(); @@ -347,7 +347,7 @@ public: @param signals specifies the signal flags of the thread that should be cleared. @return signal flags before clearing or osFlagsError in case of incorrect parameters. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ static int32_t signal_clr(int32_t signals); @@ -356,7 +356,7 @@ public: @param millisec timeout value or 0 in case of no time-out. (default: osWaitForever). @return event flag information or error code. @note if @a millisec is set to 0 and flag is no set the event carries osOK value. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever); @@ -364,41 +364,41 @@ public: @param millisec time delay value @return status code that indicates the execution status of the function. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ static osStatus wait(uint32_t millisec); /** Pass control to next thread that is in state READY. @return status code that indicates the execution status of the function. - @note This function cannot be called from ISR context. + @note You cannot call this function from ISR context. */ static osStatus yield(); /** Get the thread id of the current running thread. @return thread ID for reference by other functions or NULL in case of error. - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ static osThreadId gettid(); /** Attach a function to be called by the RTOS idle task @param fptr pointer to the function to be called - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ static void attach_idle_hook(void (*fptr)(void)); /** Attach a function to be called when a task is killed @param fptr pointer to the function to be called - @note This function may be called from ISR context. + @note You may call this function from ISR context. */ static void attach_terminate_hook(void (*fptr)(osThreadId id)); /** Thread destructor * - * @note This function cannot be called from ISR context. + * @note You cannot call this function from ISR context. */ virtual ~Thread(); From 72c648ae62834db9109823de08d24f34b8fbb418 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 9 Jan 2018 14:10:14 +0100 Subject: [PATCH 018/133] STM32 LOWPOWERTIMER : introduce LPTIM feature STM32L0, L4, F7 and few F4 chip are supporting LPTIM feature. We propose to allow user to use LPTIM for MBED LowPowerTimer API instead of using RTC wakeup timers. By default, all targets that are supporting this feature have been configured. --- targets/TARGET_STM/lp_ticker.c | 256 ++++++++++++++++++++++++++++++- targets/TARGET_STM/rtc_api.c | 17 +- targets/TARGET_STM/rtc_api_hal.h | 5 + targets/TARGET_STM/sleep.c | 4 - targets/targets.json | 83 +++++++++- 5 files changed, 350 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index dfe84aff75..3404994aa7 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -27,12 +27,264 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ -#include "device.h" #if DEVICE_LOWPOWERTIMER #include "rtc_api_hal.h" +#if MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM + +LPTIM_HandleTypeDef LptimHandle; + +volatile uint32_t lp_SlaveCounter = 0; +volatile uint32_t lp_oc_int_part = 0; +volatile uint16_t lp_TickPeriod_us; +volatile uint8_t lp_Fired = 0; + +static void LPTIM1_IRQHandler(void); +static void (*irq_handler)(void); + + +void lp_ticker_init(void) +{ + /* Check if LPTIM is already configured */ +#if (TARGET_STM32L0) + if (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET) { + return; + } +#else + if (__HAL_RCC_LPTIM1_IS_CLK_ENABLED()) { + return; + } +#endif + + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + +#if MBED_CONF_TARGET_LSE_AVAILABLE + + /* Enable LSE clock */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + + /* Select the LSE clock as LPTIM peripheral clock */ + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; +#if (TARGET_STM32L0) + RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSE; +#else + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE; +#endif + +#else /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + /* Enable LSI clock */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + + /* Select the LSI clock as LPTIM peripheral clock */ + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; +#if (TARGET_STM32L0) + RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSI; +#else + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; +#endif + +#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */ + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("HAL_RCC_OscConfig ERROR\n"); + return; + } + + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) { + error("HAL_RCCEx_PeriphCLKConfig ERROR\n"); + return; + } + + __HAL_RCC_LPTIM1_CLK_ENABLE(); + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + + /* Initialize the LPTIM peripheral */ + LptimHandle.Instance = LPTIM1; + LptimHandle.State = HAL_LPTIM_STATE_RESET; + LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + + /* Prescaler impact: + tick period = Prescaler division factor / LPTIM clock + Example with LPTIM clock = 32768 Hz LSE + Prescaler = LPTIM_PRESCALER_DIV1 => lp_TickPeriod_us = 31us => 2s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV2 => lp_TickPeriod_us = 61us => 4s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV4 => lp_TickPeriod_us = 122us => 8s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV8 => lp_TickPeriod_us = 244us => 16s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV16 => lp_TickPeriod_us = 488us => 32s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV32 => lp_TickPeriod_us = 976us => 64s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV64 => lp_TickPeriod_us = 1.9ms => 128s with 16b timer + Prescaler = LPTIM_PRESCALER_DIV128 => lp_TickPeriod_us = 3.9ms => 256s with 16b timer + */ + LptimHandle.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV2; + lp_TickPeriod_us = 2 * 1000000 / RTC_CLOCK; + + LptimHandle.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; +#if (TARGET_STM32L4) + LptimHandle.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; + LptimHandle.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; +#endif /* TARGET_STM32L4 */ + + if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK) { + error("HAL_LPTIM_Init ERROR\n"); + return; + } + + NVIC_SetVector(LPTIM1_IRQn, (uint32_t)LPTIM1_IRQHandler); + NVIC_EnableIRQ(LPTIM1_IRQn); + +#if !(TARGET_STM32L4) + /* EXTI lines are not configured by default */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); +#endif + + __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_ARRM); + __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPM); + __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPOK); + HAL_LPTIM_Counter_Start(&LptimHandle, 0xFFFF); +} + +static void LPTIM1_IRQHandler(void) +{ + LptimHandle.Instance = LPTIM1; + + if (lp_Fired) { + lp_Fired = 0; + if (irq_handler) { + irq_handler(); + } + } + + /* Compare match interrupt */ + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPM) != RESET) { + if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_CMPM) != RESET) { + /* Clear Compare match flag */ + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM); + + if (lp_oc_int_part > 0) { + lp_oc_int_part--; + } else { + if (irq_handler) { + irq_handler(); + } + } + } + } + + /* Compare write interrupt */ + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) != RESET) { + if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_CMPOK) != RESET) { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK); + } + } + + /* Autoreload match interrupt */ + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) != RESET) { + if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_ARRM) != RESET) { + /* Clear Autoreload match flag */ + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_ARRM); + lp_SlaveCounter++; + } + } + +#if !(TARGET_STM32L4) + __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); +#endif +} + + +uint32_t lp_ticker_read_TickCounter(void) +{ + uint16_t cntH_old, cntH, cntL; + + LptimHandle.Instance = LPTIM1; + + /* same algo as us_ticker_read in us_ticker_16b.c */ + do { + cntH_old = lp_SlaveCounter; + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) == SET) { + cntH_old += 1; + } + cntL = LPTIM1->CNT; + cntH = lp_SlaveCounter; + if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) == SET) { + cntH += 1; + } + } while (cntH_old != cntH); + uint32_t lp_time = (uint32_t)(cntH << 16 | cntL); + return lp_time; +} + +uint32_t lp_ticker_read(void) +{ + lp_ticker_init(); + return lp_ticker_read_TickCounter() * (uint32_t)lp_TickPeriod_us; +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + // Disable IRQs + core_util_critical_section_enter(); + + uint32_t timestamp_TickCounter = timestamp / (uint32_t)lp_TickPeriod_us; + + LptimHandle.Instance = LPTIM1; + irq_handler = (void (*)(void))lp_ticker_irq_handler; + + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK); + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM); + __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp_TickCounter & 0xFFFF); + + /* CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed */ + while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) { + } + + /* same algo as us_ticker_set_interrupt in us_ticker_16b.c */ + uint32_t current_time_TickCounter = lp_ticker_read_TickCounter(); + uint32_t delta = timestamp_TickCounter - current_time_TickCounter; + lp_oc_int_part = (delta - 1) >> 16; + if ( ((delta - 1) & 0xFFFF) >= 0x8000 && + __HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPM) == SET ) { + ++lp_oc_int_part; + } + + // Enable IRQs + core_util_critical_section_exit(); +} + +void lp_ticker_fire_interrupt(void) +{ + lp_Fired = 1; + NVIC_SetPendingIRQ(LPTIM1_IRQn); +} + +void lp_ticker_disable_interrupt(void) +{ + LptimHandle.Instance = LPTIM1; + __HAL_LPTIM_DISABLE_IT(&LptimHandle, LPTIM_IT_CMPM); +} + +void lp_ticker_clear_interrupt(void) +{ + LptimHandle.Instance = LPTIM1; + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM); +} + +#else /* MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ + void lp_ticker_init(void) { rtc_init(); @@ -74,4 +326,6 @@ void lp_ticker_clear_interrupt(void) NVIC_ClearPendingIRQ(RTC_WKUP_IRQn); } +#endif /* MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ + #endif /* DEVICE_LOWPOWERTIMER */ diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 0f851a2e52..9e91753c86 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -31,15 +31,14 @@ #if DEVICE_RTC #include "rtc_api_hal.h" -#include "mbed_error.h" #include "mbed_mktime.h" static RTC_HandleTypeDef RtcHandle; -#if DEVICE_LOWPOWERTIMER +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM static void (*irq_handler)(void); static void RTC_IRQHandler(void); -#endif +#endif /* DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ void rtc_init(void) { @@ -55,7 +54,7 @@ void rtc_init(void) } #if MBED_CONF_TARGET_LSE_AVAILABLE - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; @@ -78,7 +77,7 @@ void rtc_init(void) __HAL_RCC_BACKUPRESET_RELEASE(); // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! RCC_OscInitStruct.LSEState = RCC_LSE_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_ON; @@ -108,7 +107,7 @@ void rtc_init(void) RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; /* PREDIV_A : 7-bit asynchronous prescaler */ -#if DEVICE_LOWPOWERTIMER +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM /* PREDIV_A is set to a small value to improve the SubSeconds resolution */ /* with a 32768Hz clock, PREDIV_A=7 gives a precision of 244us */ RtcHandle.Init.AsynchPrediv = 7; @@ -294,7 +293,7 @@ void rtc_synchronize(void) } } -#if DEVICE_LOWPOWERTIMER +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM static void RTC_IRQHandler(void) { @@ -342,7 +341,7 @@ void rtc_set_wake_up_timer(uint32_t delta) NVIC_EnableIRQ(RTC_WKUP_IRQn); RtcHandle.Instance = RTC; - if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, 0xFFFF & WakeUpCounter, WakeUpClock[DivIndex-1]) != HAL_OK) { + if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, 0xFFFF & WakeUpCounter, WakeUpClock[DivIndex - 1]) != HAL_OK) { error("rtc_set_wake_up_timer init error (%d)\n", DivIndex); } } @@ -353,6 +352,6 @@ void rtc_deactivate_wake_up_timer(void) HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle); } -#endif /* DEVICE_LOWPOWERTIMER */ +#endif /* DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ #endif /* DEVICE_RTC */ diff --git a/targets/TARGET_STM/rtc_api_hal.h b/targets/TARGET_STM/rtc_api_hal.h index ca948ca36b..5013b3bbeb 100644 --- a/targets/TARGET_STM/rtc_api_hal.h +++ b/targets/TARGET_STM/rtc_api_hal.h @@ -35,6 +35,11 @@ #include "rtc_api.h" #include "ticker_api.h" #include "lp_ticker_api.h" +#include "us_ticker_api.h" +#include "hal_tick.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include "mbed_debug.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index fb232ec8b7..b4e36c892d 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -29,12 +29,8 @@ */ #if DEVICE_SLEEP -#include "cmsis.h" -#include "us_ticker_api.h" #include "sleep_api.h" #include "rtc_api_hal.h" -#include "hal_tick.h" -#include "mbed_critical.h" extern void HAL_SuspendTick(void); extern void HAL_ResumeTick(void); diff --git a/targets/targets.json b/targets/targets.json index e75f1f59fb..699c928905 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1025,6 +1025,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0744"], @@ -1084,6 +1088,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0743"], @@ -1244,6 +1252,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "macros_add": ["USBHOST_OTHER"], @@ -1268,6 +1280,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"], @@ -1292,6 +1308,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "supported_form_factors": ["ARDUINO"], @@ -1314,6 +1334,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0780"], @@ -1333,6 +1357,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0790"], @@ -1351,6 +1379,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0715"], @@ -1369,6 +1401,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0760"], @@ -1403,6 +1439,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0770"], @@ -1421,9 +1461,13 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, - "detect_code": ["0770"], + "detect_code": ["0779"], "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32L433RC", @@ -1439,6 +1483,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0765"], @@ -1476,6 +1524,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0827"], @@ -1614,6 +1666,11 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 + } }, "overrides": {"lse_available": 0}, @@ -1632,6 +1689,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0833"], @@ -1653,6 +1714,10 @@ "usb_speed": { "help": "Select the USB speed/connector (0=FullSpeed, 1=HighSpeed)", "value": "1" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0815"], @@ -1672,6 +1737,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI", "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0817"], @@ -1690,6 +1759,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "supported_form_factors": ["ARDUINO"], @@ -1709,6 +1782,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0820"], @@ -3538,6 +3615,10 @@ "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", "value": "USE_PLL_MSI", "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 } }, "detect_code": ["0823"], From 44bf90b7164b1f990d405005bc0b25ce17c6abd6 Mon Sep 17 00:00:00 2001 From: Tero Heinonen Date: Tue, 19 Dec 2017 15:41:59 +0200 Subject: [PATCH 019/133] mesh-api documentation removed All documentation is now in Handbook --- .../FEATURE_NANOSTACK/mbed-mesh-api/README.md | 141 ------------------ 1 file changed, 141 deletions(-) delete mode 100644 features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md deleted file mode 100644 index eb50e73fb9..0000000000 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/README.md +++ /dev/null @@ -1,141 +0,0 @@ -# mbed mesh API - -ARM mbed mesh API allows the client to use the IPv6 mesh network. - -The client can use the `LoWPANNDInterface` or `ThreadInterface` object for connecting to the mesh network and when successfully connected, the client can create a socket by using the [mbed C++ socket API](https://developer.mbed.org/teams/NetworkSocketAPI/code/NetworkSocketAPI/docs/tip/) to start communication with a remote peer. - -For ethernet `NanostackEthernetInterface` is provided. - -## Supported mesh networking modes - -Currently, 6LoWPAN-ND (neighbour discovery) and Thread bootstrap modes are supported. - -## Module Configuration - -This module supports static configuration via **mbed configuration system** by using the `mbed_app.json` file. The application needs to create the configuration file if it wants to use other than default settings. - -An example of the configuration file: - -``` -{ - "target_overrides": { - "*": { - "target.features_add": ["IPV6"], - "mbed-mesh-api.6lowpan-nd-channel": 12, - "mbed-mesh-api.6lowpan-nd-channel-mask": "(1<<12)", - "mbed-mesh-api.heap-size": 10000 - } - } -} -``` - -### Configurable parameters in section mbed-mesh-api - -| Parameter name | Value | Description | -| --------------- | ------------- | ----------- | -| heap-size | number [0-0xfffe] | Nanostack's internal heap size | -| use-malloc-for-heap | `false` or `true` | Use `malloc()` for reserving the internal heap. Default: `false` | - -### Thread related configuration parameters - -| Parameter name | Value | Description | -| --------------- | ------------- | ----------- | -| thread-pskd | string [6-255 chars] | Human-scaled commissioning credentials. | -| thread-use-static-link-config | boolean | True: Use the below link config, False: Use commissioning, ignore the below link config. | -| thread-device-type | enum from mesh_device_type_t | Supported device operating modes: MESH_DEVICE_TYPE_THREAD_ROUTER, MESH_DEVICE_TYPE_THREAD_SLEEPY_END_DEVICE, MESH_DEVICE_TYPE_THREAD_MINIMAL_END_DEVICE | -| thread-config-channel-mask | number [0-0x07fff800] | Channel mask, 0x07fff800 scans all channels. | -| thread-config-channel-page | number [0, 2]| Channel page, 0 for 2,4 GHz and 2 for sub-GHz radios. | -| thread-config-channel | number [0-27] | RF channel to use. | -| thread-config-panid | number [0-0xFFFF] | Network identifier. | -| thread-config-network-name | string [1-16] | -| thread-config-commissioning-dataset-timestamp | [0-0xFFFFFFFFFFFFFFFF] | [48 bit timestamp seconds]-[15 bit timestamp ticks]-[U bit] | -|thread-config-extended-panid | byte array [8] | Extended PAN ID | -| thread-master-key | byte array [16]| Network master key. | -| thread-config-ml-prefix | byte array [8] | Mesh local prefix. | -| thread-config-pskc | byte array [16] | Pre-Shared Key for the Commissioner. | -| thread-security-policy | number [0-0xFF] | Commissioning security policy bits | - -### 6LoWPAN related configuration parameters - -| Parameter name | Type | Description | -| --------------- | ---------| ----------- | -| 6lowpan-nd-channel-mask | number [0-0x07fff800] | Channel mask, bit-mask of channels to use | -| 6lowpan-nd-channel-page | number [0, 2] | 0 for 2,4 GHz and 2 for sub-GHz radios | -| 6lowpan-nd-channel | number [0-27] | RF channel to use when `channel_mask` is not defined | -| 6lowpan-nd-panid-filter | number [0-0xffff] | Beacon PAN ID filter, 0xffff means no filtering | -| 6lowpan-nd-security-mode | "NONE" or "PSK" | To use either no security, or Pre shared network key | -| 6lowpan-nd-psk-key-id | number | PSK key id when PSK is enabled | -| 6lowpan-nd-psk-key | byte array [16] | Pre shared network key | -| 6lowpan-nd-sec-level | number [1-7] | Network security level. Use default `5` | -| 6lowpan-nd-device-type | "NET_6LOWPAN_ROUTER" or "NET_6LOWPAN_HOST" | Device mode. Router is routing packets from other device, creating a mesh network. | - -## Usage notes - -This module should not be used directly by the applications. The applications should use the `LoWPANNDInterface`, `ThreadInterface` or `NanostackEthernetInterface` directly. - -When using Ethernet interface, there is no configuration options available. It is using dynamic mode to learn the IPv6 prefix from the network. No static configuration is supported. - -### Network connection states - -After the initialization, the network state is `MESH_DISCONNECTED`. After a successful connection, the state changes to `MESH_CONNECTED` and when disconnected from the network the state is changed back to `MESH_DISCONNECTED`. - -In case of connection errors, the state is changed to some of the connection error states. In an error state, there is no need to make a `disconnect` request and the client is allowed to attempt connecting again. - -## Getting started - -See the example application [mbed-os-example-mesh-minimal](https://github.com/ARMmbed/mbed-os-example-mesh-minimal) for usage. - -## Usage example for 6LoWPAN ND mode - -Create a network interface and driver objects. - -``` -LoWPANNDInterface mesh; -NanostackRfPhyNcs36510 rf_phy; -``` - -Initialize interface with given PHY driver. - -``` -mesh.initialize(&rf_phy); -``` - -Then connect to network: - -``` - if (mesh.connect()) { - printf("Connection failed!\r\n"); - return -1; - } - - printf("connected. IP = %s\r\n", mesh.get_ip_address()); -``` - -## Usage example for 6LoWPAN Thread mode - -Basically the same as for ND, but the network interface uses different class: - -``` -ThreadInterface mesh; -mesh.connect(); -``` - -## Usage example with Ethernet - -API is still the same, you just need to provide a driver that implements `NanostackEthernetPhy` API. - -``` -NanostackEthernetInterface eth; -NanostackEthernetPhyK64F phy; - -int main() { - eth.initialize(&phy); - - if (eth.connect()) { - printf("Connection failed!\r\n"); - return -1; - } - - printf("connected. IP = %s\r\n", eth.get_ip_address()); -} -``` From 544d6b5d888c075505dfcf0292010f3e2a85369d Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Thu, 30 Nov 2017 10:03:20 -0600 Subject: [PATCH 020/133] Clarify TCPSocket::recv() and UDPSocket::recvfrom() documentation. --- features/netsocket/TCPSocket.h | 4 +++- features/netsocket/UDPSocket.h | 15 ++++++++------- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/features/netsocket/TCPSocket.h b/features/netsocket/TCPSocket.h index 7b12ba3a9e..39c547d7af 100644 --- a/features/netsocket/TCPSocket.h +++ b/features/netsocket/TCPSocket.h @@ -111,7 +111,9 @@ public: * @param data Destination buffer for data received from the host * @param size Size of the buffer in bytes * @return Number of received bytes on success, negative error - * code on failure + * code on failure. If no data is available to be received + * and the peer has performed an orderly shutdown, + * recv() returns 0. */ nsapi_size_or_error_t recv(void *data, nsapi_size_t size); diff --git a/features/netsocket/UDPSocket.h b/features/netsocket/UDPSocket.h index 02f39e9ed6..a4570fa80e 100644 --- a/features/netsocket/UDPSocket.h +++ b/features/netsocket/UDPSocket.h @@ -94,17 +94,18 @@ public: nsapi_size_or_error_t sendto(const SocketAddress &address, const void *data, nsapi_size_t size); - /** Receive a packet over a UDP socket + /** Receive a datagram over a UDP socket * - * Receives data and stores the source address in address if address - * is not NULL. Returns the number of bytes received into the buffer. + * Receives a datagram and stores the source address in address if address + * is not NULL. Returns the number of bytes written into the buffer. If the + * datagram is larger than the buffer, the excess data is silently discarded. * - * By default, recvfrom blocks until data is sent. If socket is set to - * non-blocking or times out, NSAPI_ERROR_WOULD_BLOCK is returned - * immediately. + * By default, recvfrom blocks until a datagram is received. If socket is set to + * non-blocking or times out with no datagram, NSAPI_ERROR_WOULD_BLOCK + * is returned. * * @param address Destination for the source address or NULL - * @param data Destination buffer for data received from the host + * @param data Destination buffer for datagram received from the host * @param size Size of the buffer in bytes * @return Number of received bytes on success, negative error * code on failure From ae5a5862f184891fcbe2fdd1d3a2d0bf67fd2e76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tero=20J=C3=A4=C3=A4sk=C3=B6?= Date: Wed, 8 Nov 2017 13:12:00 +0200 Subject: [PATCH 021/133] platform: make C++ allocation wrappers log the correct caller address The C++ "operator new" and "operator delete" (and their array variants) were logging the the caller address wrong. In practice if one used "operator new", the logged caller address pointed to mbed_retarget.cpp, not to the client. Fix this by exposing the alloc wrappers to the the retarget. Note: this fixes only the ARMCC variants, as the GCC ones have different different API and implementation. --- platform/mbed_alloc_wrappers.cpp | 16 +++++++++-- platform/mbed_retarget.cpp | 49 ++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/platform/mbed_alloc_wrappers.cpp b/platform/mbed_alloc_wrappers.cpp index accfe26b5d..eeb78411ba 100644 --- a/platform/mbed_alloc_wrappers.cpp +++ b/platform/mbed_alloc_wrappers.cpp @@ -245,9 +245,16 @@ extern "C" { void *SUPER_REALLOC(void *ptr, size_t size); void *SUPER_CALLOC(size_t nmemb, size_t size); void SUPER_FREE(void *ptr); + void *malloc_wrapper(size_t size, void* caller); + void free_wrapper(void *ptr, void* caller); } + extern "C" void* SUB_MALLOC(size_t size) { + return malloc_wrapper(size, MBED_CALLER_ADDR()); +} + +extern "C" void* malloc_wrapper(size_t size, void* caller) { void *ptr = NULL; #ifdef MBED_MEM_TRACING_ENABLED mbed_mem_trace_lock(); @@ -272,12 +279,13 @@ extern "C" void* SUB_MALLOC(size_t size) { ptr = SUPER_MALLOC(size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR()); + mbed_mem_trace_malloc(ptr, size, caller); mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return ptr; } + extern "C" void* SUB_REALLOC(void *ptr, size_t size) { void *new_ptr = NULL; #ifdef MBED_MEM_TRACING_ENABLED @@ -337,6 +345,10 @@ extern "C" void *SUB_CALLOC(size_t nmemb, size_t size) { } extern "C" void SUB_FREE(void *ptr) { + free_wrapper(ptr, MBED_CALLER_ADDR()); +} + +extern "C" void free_wrapper(void *ptr, void* caller) { #ifdef MBED_MEM_TRACING_ENABLED mbed_mem_trace_lock(); #endif @@ -354,7 +366,7 @@ extern "C" void SUB_FREE(void *ptr) { SUPER_FREE(ptr); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mbed_mem_trace_free(ptr, MBED_CALLER_ADDR()); + mbed_mem_trace_free(ptr, caller); mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED } diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp index 2be38c6fa1..11fcfa6989 100644 --- a/platform/mbed_retarget.cpp +++ b/platform/mbed_retarget.cpp @@ -1022,6 +1022,53 @@ extern "C" void __cxa_guard_abort(int *guard_object_p) #endif +#if defined(MBED_MEM_TRACING_ENABLED) && (defined(__CC_ARM) || defined(__ICCARM__)) + +// If the memory tracing is enabled, the wrappers in mbed_alloc_wrappers.cpp +// provide the implementation for these. Note: this needs to use the wrappers +// instead of malloc()/free() as the caller address would point to wrappers, +// not the caller of "new" or "delete". +extern "C" void* malloc_wrapper(size_t size, const void* caller); +extern "C" void free_wrapper(void *ptr, const void* caller); + +void *operator new(std::size_t count) +{ + void *buffer = malloc_wrapper(count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new out of memory\r\n"); + } + return buffer; +} + +void *operator new[](std::size_t count) +{ + void *buffer = malloc_wrapper(count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new[] out of memory\r\n"); + } + return buffer; +} + +void *operator new(std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(count, MBED_CALLER_ADDR()); +} + +void *operator new[](std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(count, MBED_CALLER_ADDR()); +} + +void operator delete(void *ptr) +{ + free_wrapper(ptr, MBED_CALLER_ADDR()); +} +void operator delete[](void *ptr) +{ + free_wrapper(ptr, MBED_CALLER_ADDR()); +} + +#else void *operator new(std::size_t count) { void *buffer = malloc(count); @@ -1059,6 +1106,8 @@ void operator delete[](void *ptr) free(ptr); } +#endif + /* @brief standard c library clock() function. * * This function returns the number of clock ticks elapsed since the start of the program. From e86a2b090f5113417fa17a3d433e183328ae004c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tero=20J=C3=A4=C3=A4sk=C3=B6?= Date: Fri, 24 Nov 2017 16:08:28 +0200 Subject: [PATCH 022/133] platform: Fix C++ allocation wrappers for GCC compilation Fix the caller address logging on the GCC compilation too. Previously the code logged the caller address as C++ wrapper, not the actual caller of the C++ operator new or delete. --- platform/mbed_alloc_wrappers.cpp | 14 ++++++++-- platform/mbed_retarget.cpp | 46 ++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/platform/mbed_alloc_wrappers.cpp b/platform/mbed_alloc_wrappers.cpp index eeb78411ba..58f153c70d 100644 --- a/platform/mbed_alloc_wrappers.cpp +++ b/platform/mbed_alloc_wrappers.cpp @@ -81,12 +81,18 @@ extern "C" { void * __real__realloc_r(struct _reent * r, void * ptr, size_t size); void __real__free_r(struct _reent * r, void * ptr); void* __real__calloc_r(struct _reent * r, size_t nmemb, size_t size); + void* malloc_wrapper(struct _reent * r, size_t size, void * caller); + void free_wrapper(struct _reent * r, void * ptr, void* caller); } // TODO: memory tracing doesn't work with uVisor enabled. #if !defined(FEATURE_UVISOR) extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) { + return malloc_wrapper(r, size, MBED_CALLER_ADDR()); +} + +extern "C" void * malloc_wrapper(struct _reent * r, size_t size, void * caller) { void *ptr = NULL; #ifdef MBED_MEM_TRACING_ENABLED mbed_mem_trace_lock(); @@ -111,7 +117,7 @@ extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) { ptr = __real__malloc_r(r, size); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR()); + mbed_mem_trace_malloc(ptr, size, caller); mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED return ptr; @@ -160,6 +166,10 @@ extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) } extern "C" void __wrap__free_r(struct _reent * r, void * ptr) { + free_wrapper(r, ptr, MBED_CALLER_ADDR()); +} + +extern "C" void free_wrapper(struct _reent * r, void * ptr, void * caller) { #ifdef MBED_MEM_TRACING_ENABLED mbed_mem_trace_lock(); #endif @@ -177,7 +187,7 @@ extern "C" void __wrap__free_r(struct _reent * r, void * ptr) { __real__free_r(r, ptr); #endif // #ifdef MBED_HEAP_STATS_ENABLED #ifdef MBED_MEM_TRACING_ENABLED - mbed_mem_trace_free(ptr, MBED_CALLER_ADDR()); + mbed_mem_trace_free(ptr, caller); mbed_mem_trace_unlock(); #endif // #ifdef MBED_MEM_TRACING_ENABLED } diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp index 11fcfa6989..8d3dbe3936 100644 --- a/platform/mbed_retarget.cpp +++ b/platform/mbed_retarget.cpp @@ -1068,7 +1068,53 @@ void operator delete[](void *ptr) free_wrapper(ptr, MBED_CALLER_ADDR()); } +#elif defined(MBED_MEM_TRACING_ENABLED) && defined(__GNUC__) + +#include + +extern "C" void* malloc_wrapper(struct _reent * r, size_t size, void * caller); +extern "C" void free_wrapper(struct _reent * r, void * ptr, void * caller); + +void *operator new(std::size_t count) +{ + void *buffer = malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new out of memory\r\n"); + } + return buffer; +} + +void *operator new[](std::size_t count) +{ + void *buffer = malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); + if (NULL == buffer) { + error("Operator new[] out of memory\r\n"); + } + return buffer; +} + +void *operator new(std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); +} + +void *operator new[](std::size_t count, const std::nothrow_t& tag) +{ + return malloc_wrapper(_REENT, count, MBED_CALLER_ADDR()); +} + +void operator delete(void *ptr) +{ + free_wrapper(_REENT, ptr, MBED_CALLER_ADDR()); +} + +void operator delete[](void *ptr) +{ + free_wrapper(_REENT, ptr, MBED_CALLER_ADDR()); +} + #else + void *operator new(std::size_t count) { void *buffer = malloc(count); From 6ca58de840e5bdc1e556d2884c6ae963af88b999 Mon Sep 17 00:00:00 2001 From: Daniel Schuler Date: Mon, 18 Dec 2017 18:19:31 -0800 Subject: [PATCH 023/133] Add presentation format descriptor support for NRF52 --- .../source/btle/custom/custom_helper.cpp | 7 +++++ .../source/btle/custom/custom_helper.h | 2 ++ .../TARGET_NRF5/source/nRF5xGattServer.cpp | 26 +++++++++++++++---- 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp index 2a8e600c0a..bc46d3d58d 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp @@ -210,6 +210,8 @@ error_t custom_add_in_characteristic(uint16_t service_handle, bool has_variable_len, const uint8_t *userDescriptionDescriptorValuePtr, uint16_t userDescriptionDescriptorValueLen, + const uint8_t *presentationFormatDescriptorValuePtr, + uint16_t presentationFormatDescriptorValueLen, bool readAuthorization, bool writeAuthorization, ble_gatts_char_handles_t *p_char_handle) @@ -238,6 +240,11 @@ error_t custom_add_in_characteristic(uint16_t service_handle, char_md.char_user_desc_max_size = userDescriptionDescriptorValueLen; char_md.char_user_desc_size = userDescriptionDescriptorValueLen; } + if ((presentationFormatDescriptorValueLen > 0) && (presentationFormatDescriptorValuePtr != NULL)) { + ASSERT_TRUE( sizeof(ble_gatts_char_pf_t) == sizeof(GattCharacteristic::PresentationFormat_t), ERROR_INVALID_PARAM ); + ASSERT_TRUE( presentationFormatDescriptorValueLen == sizeof(GattCharacteristic::PresentationFormat_t), ERROR_INVALID_PARAM ); + char_md.p_char_pf = const_cast(reinterpret_cast(presentationFormatDescriptorValuePtr)); + } /* Attribute declaration */ ble_gatts_attr_md_t attr_md = {0}; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h index af47fb9852..93480b873b 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h @@ -52,6 +52,8 @@ error_t custom_add_in_characteristic(uint16_t service_handle, bool has_variable_len, const uint8_t *userDescriptionDescriptorValuePtr, uint16_t userDescriptionDescriptorValueLen, + const uint8_t *presentationFormatDescriptorValuePtr, + uint16_t presentationFormatDescriptorValueLen, bool readAuthorization, bool writeAuthorization, ble_gatts_char_handles_t *p_char_handle); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp index 5ab02d702b..8bcdd7d07a 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp @@ -131,6 +131,7 @@ ble_error_t nRF5xGattServer::addService(GattService &service) } GattCharacteristic *p_char = service.getCharacteristic(i); GattAttribute *p_description_descriptor = NULL; + GattAttribute *p_presentation_format_descriptor = NULL; /* Skip any incompletely defined, read-only characteristics. */ if ((p_char->getValueAttribute().getValuePtr() == NULL) && @@ -141,11 +142,13 @@ ble_error_t nRF5xGattServer::addService(GattService &service) nordicUUID = custom_convert_to_nordic_uuid(p_char->getValueAttribute().getUUID()); - /* The user-description descriptor is a special case which needs to be - * handled at the time of adding the characteristic. The following block - * is meant to discover its presence. */ + /* The user-description and presentation-format descriptors are special cases + * that need to be handled at the time of adding each characteristic. The + * following block is meant to discover their presence. */ const uint8_t *userDescriptionDescriptorValuePtr = NULL; uint16_t userDescriptionDescriptorValueLen = 0; + const uint8_t *presentationFormatDescriptorValuePtr = NULL; + uint16_t presentationFormatDescriptorValueLen = 0; for (uint8_t j = 0; j < p_char->getDescriptorCount(); j++) { GattAttribute *p_desc = p_char->getDescriptor(j); if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) { @@ -153,6 +156,11 @@ ble_error_t nRF5xGattServer::addService(GattService &service) userDescriptionDescriptorValuePtr = p_desc->getValuePtr(); userDescriptionDescriptorValueLen = p_desc->getLength(); } + if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT) { + p_presentation_format_descriptor = p_desc; + presentationFormatDescriptorValuePtr = p_desc->getValuePtr(); + presentationFormatDescriptorValueLen = p_desc->getLength(); + } } ASSERT_TRUE ( ERROR_NONE == @@ -166,6 +174,8 @@ ble_error_t nRF5xGattServer::addService(GattService &service) p_char->getValueAttribute().hasVariableLength(), userDescriptionDescriptorValuePtr, userDescriptionDescriptorValueLen, + presentationFormatDescriptorValuePtr, + presentationFormatDescriptorValueLen, p_char->isReadAuthorizationEnabled(), p_char->isWriteAuthorizationEnabled(), &nrfCharacteristicHandles[characteristicCount]), @@ -179,6 +189,10 @@ ble_error_t nRF5xGattServer::addService(GattService &service) nrfCharacteristicHandles[characteristicCount].user_desc_handle ); } + if (p_presentation_format_descriptor) { + // The handle is not available from the SoftDevice + p_presentation_format_descriptor->setHandle(GattAttribute::INVALID_HANDLE); + } characteristicCount++; /* Add optional descriptors if any */ @@ -188,8 +202,10 @@ ble_error_t nRF5xGattServer::addService(GattService &service) } GattAttribute *p_desc = p_char->getDescriptor(j); - /* skip the user-description-descriptor here; this has already been handled when adding the characteristic (above). */ - if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) { + /* skip the user-description or presentation-format descriptor here; + * they have already been handled when adding the characteristic (above). */ + if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC + || p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT) { continue; } From 3ca6c55feb306964a7141fe5dd112ce8e6a4d65b Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Mon, 15 Jan 2018 16:13:15 +0100 Subject: [PATCH 024/133] Allow overriding of DCDC settings per target Allow custom targets to override the DCDC settings by defining EMU_DCDCINIT_STK_DEFAULT to target-specific initialization values. --- .../TARGET_EFM32PG_STK3401/device_peripherals.h | 5 +++++ .../TARGET_EFM32PG12_STK3402/device_peripherals.h | 5 +++++ .../TARGET_EFR32MG1_BRD4150/device_peripherals.h | 5 +++++ .../TARGET_TB_SENSE_1/device_peripherals.h | 5 +++++ .../TARGET_TB_SENSE_12/device_peripherals.h | 5 +++++ .../TARGET_EFM32/common/mbed_overrides.c | 8 ++++++-- 6 files changed, 31 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h index 3147299bbd..05bad32dc9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h index d9cd0fef8a..d3f9b7d58a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h index 13cbb9af1a..1a1c9c9f83 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h index 976dce7aba..ccac629438 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_TB_SENSE_1/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h index 976dce7aba..ccac629438 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_TB_SENSE_12/device_peripherals.h @@ -54,4 +54,9 @@ cmuOscMode_Crystal, \ } #endif + +/* DCDC settings */ +#if !defined(EMU_DCDCINIT_STK_DEFAULT) +#define EMU_DCDCINIT_STK_DEFAULT EMU_DCDCINIT_DEFAULT +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c index e3ded3571f..bc8f479a6c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c @@ -39,9 +39,13 @@ void mbed_sdk_init() CHIP_Init(); #if defined(_SILICON_LABS_32B_SERIES_1) - EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; +#if defined(EMU_NO_DCDC) + EMU_DCDCPowerOff(); +#else + EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_STK_DEFAULT; EMU_DCDCInit(&dcdcInit); - +#endif + #if (CORE_CLOCK_SOURCE == HFXO) // Only init HFXO if not already done (e.g. by bootloader) if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) { From 388041afeb9e091900703e17ce01e11c0b9df24c Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Fri, 12 Jan 2018 14:44:44 -0600 Subject: [PATCH 025/133] littlefs: Fix block addr overflow deepikabhavnani did the hard work in tracking this issue down. Block addresses are not cast to the correct type until after multiplying to convert to byte addresses. This results in an overflow when the storage is larger than 4 GB. --- features/filesystem/littlefs/LittleFileSystem.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/features/filesystem/littlefs/LittleFileSystem.cpp b/features/filesystem/littlefs/LittleFileSystem.cpp index 56d799b35b..93b1b920f2 100644 --- a/features/filesystem/littlefs/LittleFileSystem.cpp +++ b/features/filesystem/littlefs/LittleFileSystem.cpp @@ -85,19 +85,19 @@ static int lfs_totype(int type) static int lfs_bd_read(const struct lfs_config *c, lfs_block_t block, lfs_off_t off, void *buffer, lfs_size_t size) { BlockDevice *bd = (BlockDevice *)c->context; - return bd->read(buffer, block*c->block_size + off, size); + return bd->read(buffer, (bd_addr_t)block*c->block_size + off, size); } static int lfs_bd_prog(const struct lfs_config *c, lfs_block_t block, lfs_off_t off, const void *buffer, lfs_size_t size) { BlockDevice *bd = (BlockDevice *)c->context; - return bd->program(buffer, block*c->block_size + off, size); + return bd->program(buffer, (bd_addr_t)block*c->block_size + off, size); } static int lfs_bd_erase(const struct lfs_config *c, lfs_block_t block) { BlockDevice *bd = (BlockDevice *)c->context; - return bd->erase(block*c->block_size, c->block_size); + return bd->erase((bd_addr_t)block*c->block_size, c->block_size); } static int lfs_bd_sync(const struct lfs_config *c) From 54bd620b6f631aca7105452dd70087d1ec9d786b Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Mon, 15 Jan 2018 15:56:55 +0100 Subject: [PATCH 026/133] Fix for #5840 This commit fixes #5840. Fix verified by running mbed_hal-lp_ticker test suite with preloaded RTC counter such that it wrapped in the middle of the suite. Also removes explicit sleep blocking from the us_ticker implementation, since sleep blocking for us tickers is done at mbed HAL level now. This was causing one of the lp_ticker tests to fail. --- .../TARGET_EFM32/common/clocking.h | 15 +- .../TARGET_EFM32/lp_ticker.c | 141 +++++------------ .../TARGET_EFM32/rtc_api.c | 145 ++++++++++++++---- .../TARGET_EFM32/rtc_api_HAL.h | 22 ++- .../TARGET_EFM32/us_ticker.c | 10 -- 5 files changed, 177 insertions(+), 156 deletions(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h index 022148984c..b9ad628edc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h @@ -24,6 +24,8 @@ #ifndef MBED_CLOCKING_H #define MBED_CLOCKING_H +#include "em_cmu.h" + /* Clock definitions */ #define LFXO 0 #define HFXO 1 @@ -51,8 +53,8 @@ #ifndef CORE_CLOCK_SOURCE #define CORE_CLOCK_SOURCE HFRCO #if defined(_CMU_HFRCOCTRL_BAND_MASK) -#define HFRCO_FREQUENCY_ENUM _CMU_HFRCOCTRL_BAND_21MHZ -#define HFRCO_FREQUENCY 21000000 +#define HFRCO_FREQUENCY_ENUM _CMU_HFRCOCTRL_BAND_21MHZ +#define HFRCO_FREQUENCY 21000000 #elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) #define HFRCO_FREQUENCY_ENUM cmuHFRCOFreq_32M0Hz #define HFRCO_FREQUENCY 32000000 @@ -103,4 +105,13 @@ # endif #endif +/* Adjust this to change speed of RTC and LP ticker ticks */ +#define RTC_CLOCKDIV cmuClkDiv_8 +/* Adjust this to match RTC_CLOCKDIV as integer value */ +#define RTC_CLOCKDIV_INT 8U +/* Adjust this to match RTC_CLOCKDIV as shift for 1 second worth of ticks. + * E.g. with 32768 Hz crystal and CLOCKDIV of 8, 1 second is 4096 ticks. + * 4096 equals 1 << 12, so RTC_FREQ_SHIFT needs to be 12. */ +#define RTC_FREQ_SHIFT 12U + #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c index 684ed188c9..9c08b32090 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c @@ -25,14 +25,25 @@ #include "clocking.h" #if DEVICE_LOWPOWERTIMER +/******************************************************************************* + * The Silicon Labs lp_ticker implementation is mapped on top of an extended RTC + * API, since the RTC is available in the lowest energy modes. By default, the + * RTC counter is configured to run at 4kHz, giving us a quarter-ms resolution + * for the low power timer, which should be good enough for a low power use + * case. + * + * On Silicon Labs devices, the lowest width RTC implementation has a 24-bit + * counter, which gets extended with a further 32-bit software counter. This + * gives 56 bits of actual width, which with the default speed maps to + * 557462 years before the extended RTC counter wraps around. We are pretty + * certain no device is going to have that amount of uptime. + * (At max speed the wraparound is at 69730 years, which is unlikely as well) + ******************************************************************************/ + #include "rtc_api.h" #include "rtc_api_HAL.h" #include "lp_ticker_api.h" - #include "mbed_critical.h" -#if (defined RTCC_COUNT) && (RTCC_COUNT > 0) -#include "em_rtcc.h" -#endif static int rtc_reserved = 0; @@ -57,135 +68,55 @@ void lp_ticker_free() } } -#ifndef RTCC_COUNT - -/* RTC API */ - void lp_ticker_set_interrupt(timestamp_t timestamp) { - uint64_t timestamp_ticks; - uint64_t current_ticks = RTC_CounterGet(); - timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)); - - /* Initialize RTC */ - lp_ticker_init(); + uint64_t rtc_compare_value; + uint64_t current_ticks = rtc_get_full(); + timestamp_t current_time = lp_ticker_read(); /* calculate offset value */ timestamp_t offset = timestamp - current_time; - if(offset > 0xEFFFFFFF) offset = 100; + + /* If the requested timestamp is too far in the future, we might not be able + * to set the interrupt accurately due to potentially having ticked between + * calculating the timestamp to set and us calculating the offset. */ + if(offset > 0xFFFF0000) offset = 100; /* map offset to RTC value */ // ticks = offset * RTC frequency div 1000000 - timestamp_ticks = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000; - timestamp_ticks += current_ticks; + rtc_compare_value = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000; - /* RTC has 24 bit resolution */ - timestamp_ticks &= 0xFFFFFF; - - /* check for RTC limitation */ - if((timestamp_ticks - RTC_CounterGet()) >= 0x800000) timestamp_ticks = RTC_CounterGet() + 2; - - /* Set callback */ - RTC_FreezeEnable(true); - RTC_CompareSet(0, (uint32_t)timestamp_ticks); - RTC_IntEnable(RTC_IF_COMP0); - RTC_FreezeEnable(false); -} - -void lp_ticker_fire_interrupt(void) -{ - RTC_IntSet(RTC_IFS_COMP0); -} - -inline void lp_ticker_disable_interrupt() -{ - RTC_IntDisable(RTC_IF_COMP0); -} - -inline void lp_ticker_clear_interrupt() -{ - RTC_IntClear(RTC_IF_COMP0); -} - -timestamp_t lp_ticker_read() -{ - lp_ticker_init(); - - uint64_t ticks_temp; - uint64_t ticks = RTC_CounterGet(); - - /* ticks = counter tick value - * timestamp = value in microseconds - * timestamp = ticks * 1.000.000 / RTC frequency - */ - - ticks_temp = (ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT); - return (timestamp_t) (ticks_temp & 0xFFFFFFFF); -} - -#else - -/* RTCC API */ - -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - uint64_t timestamp_ticks; - uint64_t current_ticks = RTCC_CounterGet(); - timestamp_t current_time = ((uint64_t)(current_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)); - - /* Initialize RTC */ - lp_ticker_init(); - - /* calculate offset value */ - timestamp_t offset = timestamp - current_time; - if(offset > 0xEFFFFFFF) offset = 100; - - /* map offset to RTC value */ - // ticks = offset * RTC frequency div 1000000 - timestamp_ticks = ((uint64_t)offset * (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) / 1000000; - // checking the rounding. If timeout is wanted between RTCC ticks, irq should be configured to - // trigger in the latter RTCC-tick. Otherwise ticker-api fails to send timer event to its client - if(((timestamp_ticks * 1000000) / (LOW_ENERGY_CLOCK_FREQUENCY / RTC_CLOCKDIV_INT)) < offset){ - timestamp_ticks++; + /* If RTC offset is less then 2 RTC ticks, the interrupt won't fire */ + if(rtc_compare_value < 2) { + rtc_compare_value = 2; } - timestamp_ticks += current_ticks; + rtc_compare_value += current_ticks; - /* RTCC has 32 bit resolution */ - timestamp_ticks &= 0xFFFFFFFF; - - /* check for RTCC limitation */ - if((timestamp_ticks - RTCC_CounterGet()) >= 0x80000000) timestamp_ticks = RTCC_CounterGet() + 2; - - /* init channel */ - RTCC_CCChConf_TypeDef ccchConf = RTCC_CH_INIT_COMPARE_DEFAULT; - RTCC_ChannelInit(0,&ccchConf); - /* Set callback */ - RTCC_ChannelCCVSet(0, (uint32_t)timestamp_ticks); - RTCC_IntEnable(RTCC_IF_CC0); + rtc_set_comp0_value(rtc_compare_value, true); } -void lp_ticker_fire_interrupt(void) +inline void lp_ticker_fire_interrupt(void) { - RTCC_IntSet(RTCC_IFS_CC0); + rtc_force_comp0(); } inline void lp_ticker_disable_interrupt() { - RTCC_IntDisable(RTCC_IF_CC0); + rtc_enable_comp0(false); } inline void lp_ticker_clear_interrupt() { - RTCC_IntClear(RTCC_IF_CC0); + /* No need to clear interrupt flag, since that already happens at RTC level */ } timestamp_t lp_ticker_read() { lp_ticker_init(); - + uint64_t ticks_temp; - uint64_t ticks = RTCC_CounterGet(); + uint64_t ticks = rtc_get_full(); /* ticks = counter tick value * timestamp = value in microseconds @@ -196,6 +127,4 @@ timestamp_t lp_ticker_read() return (timestamp_t) (ticks_temp & 0xFFFFFFFF); } -#endif /* RTCC */ - #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c index 41db7d1128..81e64cbc00 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c @@ -37,17 +37,21 @@ #include "em_rtcc.h" #endif -static bool rtc_inited = false; -static time_t time_base = 0; -static uint32_t useflags = 0; -static uint32_t time_extend = 0; +static bool rtc_inited = false; +static bool rtc_cancelled = false; +static time_t time_base = 0; +static uint32_t useflags = 0; +static uint32_t time_extend = 0; +static uint32_t extended_comp0 = 0; -static void (*comp0_handler)(void) = NULL; - -#ifndef RTCC_COUNT +static void (*comp0_handler)(void) = NULL; +#ifndef RTCC_PRESENT /* Using RTC API */ -#define RTC_NUM_BITS (24) + +#if RTC_CLOCKDIV_INT > 16 +#error invalid prescaler value RTC_CLOCKDIV_INT, since LP ticker resolution will exceed 1ms. +#endif void RTC_IRQHandler(void) { @@ -60,24 +64,31 @@ void RTC_IRQHandler(void) } if (flags & RTC_IF_COMP0) { RTC_IntClear(RTC_IF_COMP0); - if (comp0_handler != NULL) { + if (comp0_handler != NULL && ((time_extend == extended_comp0) || (rtc_cancelled))) { + rtc_cancelled = false; comp0_handler(); } } } -uint32_t rtc_get_32bit(void) -{ - uint32_t pending = (RTC_IntGet() & RTC_IF_OF) ? 1 : 0; - return (RTC_CounterGet() + ((time_extend + pending) << RTC_NUM_BITS)); -} - uint64_t rtc_get_full(void) { uint64_t ticks = 0; - ticks += time_extend; - ticks = ticks << RTC_NUM_BITS; - ticks += RTC_CounterGet(); + + do + { + ticks = RTC_CounterGet(); + + if (RTC_IntGet() & RTC_IF_OF) { + RTC_IntClear(RTC_IF_OF); + /* RTC has overflowed in a critical section, so handle the overflow here */ + time_extend += 1; + } + + ticks += (uint64_t)time_extend << RTC_BITS; + } + while ( (ticks & RTC_MAX_VALUE) != RTC_CounterGet() ); + return ticks; } @@ -131,10 +142,38 @@ void rtc_free_real(uint32_t flags) } } -#else +void rtc_enable_comp0(bool enable) +{ + RTC_FreezeEnable(true); + if (!enable) { + RTC_IntDisable(RTC_IF_COMP0); + } else { + RTC_IntEnable(RTC_IF_COMP0); + } + RTC_FreezeEnable(false); +} +void rtc_set_comp0_value(uint64_t value, bool enable) +{ + rtc_enable_comp0(false); + + /* Set callback */ + RTC_FreezeEnable(true); + extended_comp0 = (uint32_t) (value >> RTC_BITS); + RTC_CompareSet(0, (uint32_t) (value & RTC_MAX_VALUE)); + RTC_FreezeEnable(false); + + rtc_enable_comp0(enable); +} + +void rtc_force_comp0(void) +{ + rtc_cancelled = true; + RTC_IntSet(RTC_IFS_COMP0); +} + +#else /* Using RTCC API */ -#define RTCC_NUM_BITS (32) void RTCC_IRQHandler(void) { @@ -149,23 +188,30 @@ void RTCC_IRQHandler(void) if (flags & RTCC_IF_CC0) { RTCC_IntClear(RTCC_IF_CC0); - if (comp0_handler != NULL) { + if (comp0_handler != NULL && ((time_extend == extended_comp0) || (rtc_cancelled))) { comp0_handler(); } } } -uint32_t rtc_get_32bit(void) -{ - return RTCC_CounterGet(); -} - uint64_t rtc_get_full(void) { uint64_t ticks = 0; - ticks += time_extend; - ticks = ticks << RTCC_NUM_BITS; - ticks += RTCC_CounterGet(); + + do + { + ticks = RTCC_CounterGet(); + + if (RTCC_IntGet() & RTCC_IF_OF) { + RTCC_IntClear(RTCC_IF_OF); + /* RTCC has overflowed in critical section, so handle the rollover here */ + time_extend += 1; + } + + ticks += (uint64_t)time_extend << RTC_BITS; + } + while ( (ticks & RTC_MAX_VALUE) != RTCC_CounterGet() ); + return ticks; } @@ -184,10 +230,18 @@ void rtc_init_real(uint32_t flags) init.enable = 1; init.precntWrapOnCCV0 = false; init.cntWrapOnCCV1 = false; -#if RTC_CLOCKDIV_INT == 8 +#if RTC_CLOCKDIV_INT == 1 + init.presc = rtccCntPresc_1; +#elif RTC_CLOCKDIV_INT == 2 + init.presc = rtccCntPresc_2; +#elif RTC_CLOCKDIV_INT == 4 + init.presc = rtccCntPresc_4; +#elif RTC_CLOCKDIV_INT == 8 init.presc = rtccCntPresc_8; +#elif RTC_CLOCKDIV_INT == 16 + init.presc = rtccCntPresc_16; #else -#error invalid prescaler value RTC_CLOCKDIV_INT +#error invalid prescaler value RTC_CLOCKDIV_INT, since LP ticker resolution will exceed 1ms. #endif /* Enable Interrupt from RTC */ @@ -220,6 +274,35 @@ void rtc_free_real(uint32_t flags) } } +void rtc_enable_comp0(bool enable) +{ + if(!enable) { + RTCC_IntDisable(RTCC_IF_CC0); + } else { + RTCC_IntEnable(RTCC_IF_CC0); + } +} + +void rtc_set_comp0_value(uint64_t value, bool enable) +{ + rtc_enable_comp0(false); + + /* init channel */ + RTCC_CCChConf_TypeDef ccchConf = RTCC_CH_INIT_COMPARE_DEFAULT; + RTCC_ChannelInit(0,&ccchConf); + /* Set callback */ + extended_comp0 = (uint32_t) (value >> RTC_BITS); + RTCC_ChannelCCVSet(0, (uint32_t) (value & RTC_MAX_VALUE)); + + rtc_enable_comp0(enable); +} + +void rtc_force_comp0(void) +{ + rtc_cancelled = true; + RTCC_IntSet(RTCC_IFS_CC0); +} + #endif /* RTCC_COUNT */ void rtc_set_comp0_handler(uint32_t handler) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h index a265e13e47..702c42ccd7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h @@ -26,15 +26,18 @@ #include #include "rtc_api.h" -#include "em_rtc.h" +#include "clocking.h" -#define RTC_CLOCKDIV cmuClkDiv_8 -#define RTC_CLOCKDIV_INT 8 -#define RTC_FREQ_SHIFT 12 +#define RTC_INIT_LPTIMER (1U << 1) +#define RTC_INIT_RTC (1U << 0) - -#define RTC_INIT_LPTIMER (1 << 1) -#define RTC_INIT_RTC (1 << 0) +#if defined(RTCC_PRESENT) +#define RTC_BITS (32U) +#define RTC_MAX_VALUE (0xFFFFFFFFUL) +#elif defined(RTC_PRESENT) +#define RTC_BITS (24U) +#define RTC_MAX_VALUE (0xFFFFFFUL) +#endif #ifdef __cplusplus extern "C" { @@ -42,6 +45,11 @@ extern "C" { /* Purpose of this file: extend rtc_api.h to include EFM-specific stuff*/ void rtc_set_comp0_handler(uint32_t handler); +void rtc_enable_comp0(bool enable); +void rtc_set_comp0_value(uint64_t value, bool enable); +void rtc_force_comp0(void); + +uint64_t rtc_get_full(void); void rtc_init_real(uint32_t flags); void rtc_free_real(uint32_t flags); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c index 93d5772bc6..74ac081768 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c @@ -25,11 +25,9 @@ #include "us_ticker_api.h" #include "device.h" #include "mbed_assert.h" -#include "mbed_sleep.h" #include "em_cmu.h" #include "em_timer.h" #include "clocking.h" -#include "sleep_api.h" /** * Timer functions for microsecond ticker. @@ -158,10 +156,6 @@ void us_ticker_set_interrupt(timestamp_t timestamp) uint32_t goal = timestamp; uint32_t trigger; - if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) == 0) { - //Timer was disabled, but is going to be enabled. Set sleep mode. - sleep_manager_lock_deep_sleep(); - } TIMER_IntDisable(US_TICKER_TIMER, TIMER_IEN_CC0); /* convert us delta value back to timer ticks */ @@ -215,10 +209,6 @@ void us_ticker_fire_interrupt(void) void us_ticker_disable_interrupt(void) { - if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) != 0) { - //Timer was enabled, but is going to get disabled. Clear sleepmode. - sleep_manager_unlock_deep_sleep(); - } /* Disable compare channel interrupts */ TIMER_IntDisable(US_TICKER_TIMER, TIMER_IEN_CC0); } From 0b5fe8de99fa479bd87b44c835680d797bf67563 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 6 Dec 2017 13:18:14 +0100 Subject: [PATCH 027/133] STM32: update init procedure - STDIO_UART define is no more used - configuring a new serial with the same UART as STDIO is no more allowed --- targets/TARGET_STM/serial_api.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index 89914d7bae..29050a5b7c 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -42,6 +42,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { struct serial_s *obj_s = SERIAL_S(obj); int IndexNumber = 0; + uint8_t stdio_config = 0; // Determine the UART to use (UART_1, UART_2, ...) UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); @@ -51,6 +52,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); MBED_ASSERT(obj_s->uart != (UARTName)NC); + if ((tx == STDIO_UART_TX) || (rx == STDIO_UART_RX)) { + stdio_config = 1; + } + else { + if (uart_tx == pinmap_peripheral(STDIO_UART_TX, PinMap_UART_TX)) { + error("Error: new serial object is using same UART as STDIO"); + } + } + // Enable USART clock #if defined(USART1_BASE) if (obj_s->uart == UART_1) { @@ -216,7 +226,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) // Configure UART obj_s->baudrate = 9600; // baudrate default value - if (obj_s->uart == STDIO_UART) { + if (stdio_config) { #if MBED_CONF_PLATFORM_STDIO_BAUD_RATE obj_s->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json #endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */ @@ -239,8 +249,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) init_uart(obj); /* init_uart will be called again in serial_baud function, so don't worry if init_uart returns HAL_ERROR */ - // For stdio management - if (obj_s->uart == STDIO_UART) { // STDIO_UART defined in PeripheralNames.h + // For stdio management in platform/mbed_board.c and platform/mbed_retarget.cpp + if (stdio_config) { stdio_uart_inited = 1; memcpy(&stdio_uart, obj, sizeof(serial_t)); } From 12106236e1b0e2cff659b570eaa1d35d9904b577 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 13:32:26 +0100 Subject: [PATCH 028/133] STM32F0: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../TARGET_DISCO_F051R8/PeripheralNames.h | 4 ---- .../TARGET_DISCO_F051R8/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F030R8/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F030R8/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F031K6/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F031K6/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F042K6/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F042K6/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F070RB/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F070RB/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F072RB/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F072RB/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F091RC/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F091RC/PinNames.h | 20 +++++++++++++++---- 14 files changed, 112 insertions(+), 56 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h index cd7c25c8c0..f200e31f11 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { UART_2 = (int)USART2_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h index c7b5fd6754..d3093d1ae9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h @@ -127,6 +127,18 @@ typedef enum { // D14 = PB_9, // D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // STM32F0-Discovery(STM32F051R8) connector namings PA0 = PA_0, PA1 = PA_1, @@ -188,10 +200,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h index cd46695e13..26f11f6d45 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_2 = (int)USART2_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h index 68256c2a4d..53a0430cef 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h @@ -127,6 +127,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -135,10 +147,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h index 2b4906c1d2..78b420b992 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h @@ -44,10 +44,6 @@ typedef enum { UART_1 = (int)USART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h index a5f7d1c6d3..5c43458fdc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h @@ -97,15 +97,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PA_9, I2C_SDA = PA_10, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h index 40a30114c1..4ebdb23883 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_2 = (int)USART2_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE // for compilation diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h index a148910e59..24b39a36b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h @@ -110,15 +110,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PA_9, I2C_SDA = PA_10, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h index 08f32ca262..7cdddd7a86 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h @@ -47,10 +47,6 @@ typedef enum { UART_4 = (int)USART4_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h index 400c744a36..1e9cff29d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h index 52b2b82eb2..9f37e1a64b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h @@ -51,10 +51,6 @@ typedef enum { UART_4 = (int)USART4_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h index 400c744a36..1e9cff29d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h index 5acb24b75f..f2616871d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_8 = (int)USART8_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h index 3c33d81d85..b09d491482 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h @@ -124,6 +124,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -132,10 +144,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, From fc91827a52566c81baa3316f355be7635ca12389 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 13:42:47 +0100 Subject: [PATCH 029/133] STM32F1: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../TARGET_BLUEPILL_F103C8/PeripheralNames.h | 4 ---- .../TARGET_BLUEPILL_F103C8/PinNames.h | 20 +++++++++++++++---- .../TARGET_DISCO_F100RB/PeripheralNames.h | 4 ---- .../TARGET_DISCO_F100RB/PinNames.h | 15 ++++++++++++-- .../TARGET_NUCLEO_F103RB/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F103RB/PinNames.h | 20 +++++++++++++++---- 6 files changed, 45 insertions(+), 22 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h index d886153259..2b92feedda 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h index a5849893da..cd2e2e9416 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h @@ -132,15 +132,27 @@ typedef enum { C14 = PC_14, C15 = PC_15, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PC_13, LED2 = PC_13, LED3 = PC_13, LED4 = PC_13, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h index 28dba655c0..803ce05731 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h index a8a684f69c..fa65262c88 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h @@ -143,6 +143,17 @@ typedef enum { PB14 = PB_14, PB15 = PB_15, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif // Generic signals namings LED1 = PC_9, @@ -152,8 +163,8 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - USBTX = PA_2, - USBRX = PA_3, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h index d886153259..2b92feedda 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h index f3c5dd5ee2..70edef80c3 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h @@ -119,6 +119,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -127,10 +139,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, From 2bf52220241b05fbd3309995fb1df5e1a294cfff Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 13:46:09 +0100 Subject: [PATCH 030/133] STM32F2: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../TARGET_NUCLEO_F207ZG/PinNames.h | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h index 6e998e8e3d..b5227168fb 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h @@ -227,6 +227,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -235,10 +247,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, - SERIAL_RX = PD_9, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = PB_5, // Conflict between D11 and RMII RX Data Valid (PA7) @@ -275,10 +287,6 @@ typedef enum { NC = (int)0xFFFFFFFF } PinName; -#define STDIO_UART_TX SERIAL_TX -#define STDIO_UART_RX SERIAL_RX -#define STDIO_UART UART_3 - #ifdef __cplusplus } #endif From 3812bdb1bcca4a6e71a5c2038a9382741a13016f Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 13:53:18 +0100 Subject: [PATCH 031/133] STM32F3: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../TARGET_NUCLEO_F302R8/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F302R8/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F303K8/PeripheralNames.h | 6 +----- .../TARGET_NUCLEO_F303K8/PinNames.h | 20 +++++++++++++++---- .../TARGET_DISCO_F303VC/PeripheralNames.h | 4 ---- .../TARGET_DISCO_F303VC/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F303RE/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F303RE/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F303ZE/PeripheralNames.h | 5 ----- .../TARGET_NUCLEO_F303ZE/PinNames.h | 20 +++++++++++++++---- .../TARGET_DISCO_F334C8/PeripheralNames.h | 4 ---- .../TARGET_DISCO_F334C8/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F334R8/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F334R8/PinNames.h | 20 +++++++++++++++---- 14 files changed, 113 insertions(+), 58 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h index 4c9aa7c4a1..84dc52f019 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_2 = (int)SPI2_BASE, SPI_3 = (int)SPI3_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h index d5aebd0b64..cd4bab1df2 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PB_13, LED2 = PB_13, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h index e670237813..a7c5821bf7 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h @@ -49,13 +49,9 @@ typedef enum { typedef enum { UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE // defined for compilation issue. UART3 is not present on STM32F303K8 + UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h index 65b8674ddf..c27ed38491 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h @@ -115,6 +115,18 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, @@ -123,10 +135,10 @@ typedef enum { USER_BUTTON = 0x20, // no user button on the board // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h index 834ab70364..271640d391 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h index c24d17702b..ed39a9e770 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h @@ -177,6 +177,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PE_9, LED2 = PE_8, @@ -191,10 +203,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h index ff95fc7be8..b711ad9302 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h index 456c8b11b8..8fbd953fb1 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h @@ -131,6 +131,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -139,10 +151,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h index 6b86154e45..02772cf554 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h @@ -55,11 +55,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX SERIAL_TX -#define STDIO_UART_RX SERIAL_RX -#define STDIO_UART UART_3 - - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h index fb36d0c13e..e7ce2730b4 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h @@ -198,6 +198,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -206,10 +218,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = SERIAL_TX, // Virtual Com Port - USBRX = SERIAL_RX, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h index c646d1d65d..924634dbbf 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PB_3 -#define STDIO_UART_RX PB_4 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h index ea7db7d750..f5466954c1 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h @@ -113,6 +113,18 @@ typedef enum { // D14 = PB_9, // D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PB_3, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_4, +#endif + // Generic signals namings LED1 = PB_6, LED2 = PB_7, @@ -121,10 +133,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PB_3, - SERIAL_RX = PB_4, - USBTX = PB_3, - USBRX = PB_4, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h index efde3b3829..ea97b1188f 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h index fce0ab472e..65022e77ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h @@ -126,6 +126,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -134,10 +146,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, From 4edae1a028d2d7c838a332304c79352a6086b33c Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 13:58:39 +0100 Subject: [PATCH 032/133] STM32F7: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../TARGET_DISCO_F746NG/PeripheralNames.h | 4 ---- .../TARGET_DISCO_F746NG/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F746ZG/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F746ZG/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F756ZG/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F756ZG/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_F767ZI/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_F767ZI/PinNames.h | 20 +++++++++++++++---- .../TARGET_DISCO_F769NI/PeripheralNames.h | 4 ---- .../TARGET_DISCO_F769NI/PinNames.h | 20 +++++++++++++++---- 10 files changed, 80 insertions(+), 40 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h index 9b1a41f133..0c00d43bf5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PB_7 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h index 8209a21c19..b096114d9d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h @@ -246,6 +246,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_7, +#endif + // Generic signals namings LED1 = PI_1, // LD1 = GREEN LED2 = PI_1, @@ -254,10 +266,10 @@ typedef enum { USER_BUTTON = PI_11, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, // Virtual Com Port - SERIAL_RX = PB_7, // Virtual Com Port - USBTX = PA_9, // Virtual Com Port - USBRX = PB_7, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h index 6a73f9ce76..66fc3645d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h index 9ef300297c..36aa261a22 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -197,10 +209,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h index 6a73f9ce76..66fc3645d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h index 9ef300297c..36aa261a22 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -197,10 +209,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h index fc1991862d..2383be6c21 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h index 9ef300297c..36aa261a22 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -197,10 +209,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h index 92e0fd8b70..2383be6c21 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h index db69e9cdca..b13a5687da 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h @@ -246,6 +246,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PJ_13, // LD1 = RED LED2 = PJ_5, // LD2 = GREEN @@ -254,10 +266,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, // Virtual Com Port - SERIAL_RX = PA_10, // Virtual Com Port - USBTX = PA_9, // Virtual Com Port - USBRX = PA_10, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, From c92c7cfbc6978c8bc71366a8b2c2abb9e95d2a0d Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 14:04:36 +0100 Subject: [PATCH 033/133] STM32L0: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../PeripheralNames.h | 4 ---- .../TARGET_DISCO_L072CZ_LRWAN1/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L011K4/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L011K4/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L031K6/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L031K6/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L073RZ/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L073RZ/PinNames.h | 20 +++++++++++++++---- .../TARGET_DISCO_L053C8/PeripheralNames.h | 4 ---- .../TARGET_DISCO_L053C8/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L053R8/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L053R8/PinNames.h | 20 +++++++++++++++---- 12 files changed, 96 insertions(+), 48 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h index 087804bb40..79e6801366 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h index b037f50420..8d94482bf2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h @@ -121,16 +121,28 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PB_5, // Green LED2 = PA_5, // Red LED3 = PB_6, // Blue LED4 = PB_7, // Red USER_BUTTON = PB_2, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h index 4978a8872e..52829dbb0e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralNames.h @@ -45,10 +45,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h index ca50932104..4b36ff0e1f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h @@ -109,15 +109,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h index b2e9f9f495..0b6d2595aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralNames.h @@ -45,10 +45,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, } SPIName; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h index 8302724210..76e1367ad2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h @@ -105,15 +105,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h index d203852621..7b21915eca 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h index e78f283d6b..8f1f4cab85 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h index f6add44db2..c0393f75ee 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h index d72a5b19e3..29a4c0ae3f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h @@ -110,6 +110,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PB_4, LED2 = PA_5, @@ -118,10 +130,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h index 0d54dc1761..c0393f75ee 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h index e78f283d6b..8f1f4cab85 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, From 346d4cd9862ca99618b91ed9f30a737d7d32688b Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 14:09:27 +0100 Subject: [PATCH 034/133] STM32L1: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../TARGET_MOTE_L152RC/PeripheralNames.h | 4 ---- .../TARGET_MOTE_L152RC/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L152RE/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L152RE/PinNames.h | 20 +++++++++++++++---- 4 files changed, 32 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h index cb931d9cfb..b627a8fc10 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h index 7949eb0588..7cf0167b21 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h @@ -122,16 +122,28 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PB_1, LED2 = PC_3, LED3 = PB_10, LED4 = PB_10, //USER_BUTTON = PC_13, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h index 22f96fb3dd..116fcec4f5 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h @@ -52,10 +52,6 @@ typedef enum { UART_5 = (int)UART5_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h index 3ede104dce..e03dd6e4c3 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -130,10 +142,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, From cd3a35e79c9837bc219f2013e401f41a861656a3 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 14:16:17 +0100 Subject: [PATCH 035/133] STM32L4: STDIO_UART_TX and STDIO_UART_RX can be now user defined --- .../TARGET_NUCLEO_L432KC/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L432KC/PinNames.h | 20 +++++++++++++++---- .../PeripheralNames.h | 4 ---- .../TARGET_DISCO_L475VG_IOT01A/PinNames.h | 20 +++++++++++++++---- .../TARGET_DISCO_L476VG/PeripheralNames.h | 4 ---- .../TARGET_DISCO_L476VG/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L476RG/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L476RG/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L486RG/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L486RG/PinNames.h | 20 +++++++++++++++---- .../TARGET_NUCLEO_L496ZG/PeripheralNames.h | 4 ---- .../TARGET_NUCLEO_L496ZG/PinNames.h | 20 +++++++++++++++---- .../TARGET_STM/TARGET_STM32L4/serial_device.c | 4 +++- 13 files changed, 99 insertions(+), 49 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h index f5ee2b01ae..4c8d454ccc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralNames.h @@ -50,10 +50,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_15 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_3 = (int)SPI3_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h index f0f0f79cac..4f91b2a7f2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h @@ -109,15 +109,27 @@ typedef enum { D12 = PB_4, D13 = PB_3, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_15, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PB_3, LED3 = PB_3, LED4 = PB_3, - SERIAL_TX = PA_2, - SERIAL_RX = PA_15, - USBTX = PA_2, - USBRX = PA_15, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_6, I2C_SDA = PB_7, SPI_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h index 77a1a05d9b..2a66882a1c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PB_6 -#define STDIO_UART_RX PB_7 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h index 9c2ea68f50..42a23b3940 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h @@ -205,6 +205,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PB_6, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_7, +#endif + // Generic signals namings LED1 = D13, // Green LED (LD1) LED2 = PB_14, // Green LED (LD2) @@ -216,10 +228,10 @@ typedef enum { BUTTON3 = USER_BUTTON, BUTTON4 = USER_BUTTON, BUTTON5 = USER_BUTTON, - SERIAL_TX = PB_6, - SERIAL_RX = PB_7, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h index 9f8ff325af..bc8f43ffa8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PD_5 -#define STDIO_UART_RX PD_6 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h index fcb2a4148f..3e3d9966ab 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h @@ -131,6 +131,18 @@ typedef enum { ADC_VREF = 0xF1, ADC_VBAT = 0xF2, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_5, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_6, +#endif + // Generic signals namings LED1 = PE_8, // LD5 Green LED2 = PB_2, // LD4 Red @@ -149,10 +161,10 @@ typedef enum { BUTTON4 = JOYSTICK_UP, BUTTON5 = JOYSTICK_DOWN, - SERIAL_TX = PD_5, - SERIAL_RX = PD_6, - USBTX = PD_5, - USBRX = PD_6, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h index e89a97bb1e..bc8f43ffa8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h index c78b39cfbc..11a6ce08bf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h index e89a97bb1e..bc8f43ffa8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h index c78b39cfbc..11a6ce08bf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h @@ -123,6 +123,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h index c87dfc103e..b3a010be10 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { LPUART_1 = (int)LPUART1_BASE } UARTName; -#define STDIO_UART_TX SERIAL_TX -#define STDIO_UART_RX SERIAL_RX -#define STDIO_UART LPUART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h index e51ea37f50..91565d925a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h @@ -245,6 +245,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PG_7, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PG_8, +#endif + // Generic signals namings LED1 = PC_7, LED2 = PB_7, @@ -254,10 +266,10 @@ typedef enum { // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PG_7, // Virtual Com Port - SERIAL_RX = PG_8, // Virtual Com Port - USBTX = PG_7, // Virtual Com Port - USBRX = PG_8, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index 916f9d45f6..1ae5e9f24f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -34,8 +34,10 @@ #if defined (TARGET_STM32L432xC) #define UART_NUM (3) +#elif defined (TARGET_STM32L433xC) + #define UART_NUM (4) #else - #define UART_NUM (6) // max value + #define UART_NUM (6) // max value (TARGET_STM32L475xG / TARGET_STM32L476xG / TARGET_STM32L486xG / TARGET_STM32L496xG) #endif uint32_t serial_irq_ids[UART_NUM] = {0}; From 5bdeb1442450a8b8e81229852644a42e8f389459 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 7 Dec 2017 11:56:49 +0100 Subject: [PATCH 036/133] STM32F4: STDIO_UART_TX and STDIO_UART_RX can be now user defined NB for UBLOX targets: usb_rx and usb_tx config name are still available in order to not break current applications. --- .../TARGET_DISCO_F401VC/PeripheralNames.h | 4 --- .../TARGET_DISCO_F401VC/PinNames.h | 20 ++++++++--- .../TARGET_NUCLEO_F401RE/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F401RE/PinNames.h | 20 ++++++++--- .../TARGET_ARCH_MAX/PeripheralNames.h | 4 --- .../TARGET_ARCH_MAX/PinNames.h | 16 +++++++-- .../TARGET_DISCO_F407VG/PeripheralNames.h | 4 --- .../TARGET_DISCO_F407VG/PinNames.h | 20 ++++++++--- .../TARGET_NUCLEO_F410RB/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F410RB/PinNames.h | 20 ++++++++--- .../TARGET_ELMO_F411RE/PeripheralNames.h | 4 --- .../TARGET_ELMO_F411RE/PinNames.h | 20 ++++++++--- .../TARGET_NUCLEO_F411RE/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F411RE/PinNames.h | 20 ++++++++--- .../TARGET_NUCLEO_F412ZG/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F412ZG/PinNames.h | 20 ++++++++--- .../TARGET_DISCO_F413ZH/PeripheralNames.h | 4 --- .../TARGET_DISCO_F413ZH/PinNames.h | 20 ++++++++--- .../TARGET_DISCO_F429ZI/PeripheralNames.h | 4 --- .../TARGET_DISCO_F429ZI/PinNames.h | 20 ++++++++--- .../TARGET_NUCLEO_F429ZI/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F429ZI/PinNames.h | 20 ++++++++--- .../TARGET_UBLOX_C030/PeripheralNames.h | 4 --- .../TARGET_UBLOX_C030/PinNames.h | 16 +++++++-- .../PeripheralNames.h | 3 -- .../TARGET_MBED_CONNECT_ODIN/PinNames.h | 21 +++++++++-- .../TARGET_MTB_UBLOX_ODIN_W2/PinNames.h | 21 +++++++++-- .../TARGET_UBLOX_EVK_ODIN_W2/PinNames.h | 21 +++++++++-- .../TARGET_NUCLEO_F439ZI/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F439ZI/PinNames.h | 20 ++++++++--- .../TARGET_B96B_F446VE/PeripheralNames.h | 4 --- .../TARGET_B96B_F446VE/PinNames.h | 20 ++++++++--- .../TARGET_NUCLEO_F446RE/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F446RE/PinNames.h | 20 ++++++++--- .../TARGET_NUCLEO_F446ZE/PeripheralNames.h | 4 --- .../TARGET_NUCLEO_F446ZE/PinNames.h | 20 ++++++++--- .../TARGET_DISCO_F469NI/PeripheralNames.h | 4 --- .../TARGET_DISCO_F469NI/PinNames.h | 19 +++++++--- targets/targets.json | 35 +++---------------- 39 files changed, 329 insertions(+), 171 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h index 23f8aea00e..bf3ae14ca4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h index 3c967a8aa1..b229bc4d2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h @@ -113,6 +113,18 @@ typedef enum { ADC_VREF = 0xF1, ADC_VBAT = 0xF2, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PD_12, LED2 = PD_13, @@ -122,10 +134,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h index 23f8aea00e..bf3ae14ca4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h index df02114393..c89ff31a0f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h index 5d22cf38cb..10be44289a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralNames.h @@ -56,10 +56,6 @@ typedef enum { UART_6 = (int)USART6_BASE, } UARTName; -#define STDIO_UART_TX PC_6 -#define STDIO_UART_RX PC_7 -#define STDIO_UART UART_6 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h index 0b4d432f6c..41d2701c46 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h @@ -222,13 +222,25 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PC_6, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PC_7, +#endif + // Generic signals namings LED1 = PB_3, LED2 = PD_8, LED3 = PD_9, LED4 = PD_10, - USBTX = PC_6, /* USART6 */ - USBRX = PC_7, + USBTX = STDIO_UART_TX, /* USART6 */ + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, /* I2C1 */ I2C_SDA = PB_9, SPI_MOSI = PC_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h index e25c70514f..10be44289a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PeripheralNames.h @@ -56,10 +56,6 @@ typedef enum { UART_6 = (int)USART6_BASE, } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h index 0c542e3b91..d645d3cca8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h @@ -196,6 +196,18 @@ typedef enum { ADC_VREF = 0xF1, ADC_VBAT = 0xF2, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PD_13, // LD3 as LD1 is not a user LED LED2 = PD_12, // LD4 as LD2 is not a user LED @@ -207,10 +219,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, /* USART2 */ - SERIAL_RX = PA_3, - USBTX = PA_2, /* USART2 */ - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, /* USART2 */ + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, /* USART2 */ + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, /* I2C1 */ I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h index caa92c00d7..63cdc8161b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PeripheralNames.h @@ -51,10 +51,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h index da18af2592..eb97596939 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h index 68f0eff9d2..c03d011251 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, ELMO_RF_SPI2 = SPI_1, SPI_2 = (int)SPI2_BASE, ELMO_SPI1 = SPI_2, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h index 0b7c41698d..e81c7b8479 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PinNames.h @@ -125,6 +125,18 @@ typedef enum { D14 = PC_9, D15 = PA_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_1, @@ -133,10 +145,10 @@ typedef enum { USER_BUTTON = PB_7, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h index 9046d68c2d..697d107c41 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h index df02114393..c89ff31a0f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h index 78bc359403..c85180daf4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralNames.h @@ -33,10 +33,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h index bf01717695..8298412355 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h @@ -175,6 +175,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -184,10 +196,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, - SERIAL_RX = PD_9, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h index 26bfcfcced..a271aefdb5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h @@ -43,10 +43,6 @@ typedef enum { UART_10 = (int)UART10_BASE } UARTName; -#define STDIO_UART_TX PG_14 -#define STDIO_UART_RX PG_9 -#define STDIO_UART UART_6 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h index 4b75ed608a..7b7f67f32f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h @@ -222,6 +222,18 @@ typedef enum { D14 = PB_11, D15 = PB_10, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PG_14, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PG_9, +#endif + // Generic signals namings LED1 = PC_5, // Green = LD3 on the board LED2 = PE_3, // Red = LD4 on the board @@ -230,10 +242,10 @@ typedef enum { LED_RED = LED2, USER_BUTTON = PA_0, BUTTON1 = USER_BUTTON, - SERIAL_TX = PG_14, - SERIAL_RX = PG_9, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h index fb1cdab06b..3a7aa557b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h index 00be7f8dac..24cc223867 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h @@ -211,6 +211,18 @@ typedef enum { ADC_VREF = 0xF1, ADC_VBAT = 0xF2, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // Generic signals namings LED1 = PG_13, // Corresponds to LD3 on MB1075B LED2 = PG_14, // Corresponds to LD4 on MB1075B @@ -220,10 +232,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_9, - SERIAL_RX = PA_10, - USBTX = PA_9, - USBRX = PA_10, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, SPI_MOSI = PA_7, SPI_MISO = PA_6, SPI_SCK = PA_5, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h index 1690d9e13f..d2c2320ba5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h index f4f612d1e2..25c07fa737 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h @@ -235,6 +235,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -244,10 +256,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h index e818a08f30..0f0b59fcef 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h @@ -54,10 +54,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h index 2b0656381b..aa912fba41 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h @@ -145,9 +145,21 @@ typedef enum { SPI_CLK = D13, SPI_NSS = D10, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // ST-Link - USBRX = PA_10, - USBTX = PA_9, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = PA_13, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h index fcd76d0152..3a7aa557b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h @@ -57,9 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h index ea26b94807..26e1426dfe 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h @@ -155,9 +155,26 @@ typedef enum { SPI_SCK = SPI0_SCK, SPI_CS = SPI0_CS, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = PA_9, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = PA_10, +#endif + // DAPLink - USBRX = MBED_CONF_TARGET_USB_RX, - USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = PA_15, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h index ed2efe8318..788bb04f72 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h @@ -179,9 +179,26 @@ typedef enum { SPI_SCK = SPI0_SCK, SPI_CS = SPI0_CS, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = PA_11, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = PA_13, +#endif + // DAPLink - USBRX = MBED_CONF_TARGET_USB_RX, - USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = PA_15, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h index e6b09b7502..f9c8638263 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h @@ -178,9 +178,26 @@ typedef enum { BUTTON1 = SW0, BUTTON2 = SW1, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = D8, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = D2, +#endif + // ST-Link - USBRX = MBED_CONF_TARGET_USB_RX, - USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = PA_15, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h index 1690d9e13f..d2c2320ba5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h index 72c046868c..fdf2904ada 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h @@ -189,6 +189,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, // LD1 = GREEN LED2 = PB_7, // Blue @@ -198,10 +210,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = PD_8, // Virtual Com Port - USBRX = PD_9, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h index d018a67cea..a1a4d9c699 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralNames.h @@ -60,10 +60,6 @@ typedef enum { DMA_2 = (int)DMA2_BASE } DMAName; -#define STDIO_UART_TX PC_10 -#define STDIO_UART_RX PC_11 -#define STDIO_UART UART_4 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h index c311a7b2be..0435b5d875 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h @@ -154,6 +154,18 @@ typedef enum { D14 = PC_12, D15 = PB_10, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PC_10, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PC_11, +#endif + // Generic signals namings LED1 = PD_10, LED2 = LED1, @@ -163,10 +175,10 @@ typedef enum { USER_BUTTON = PD_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PC_10, - SERIAL_RX = PC_11, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h index 46e9b94e28..0382c324ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PA_2 -#define STDIO_UART_RX PA_3 -#define STDIO_UART UART_2 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h index b1a0b6ca2f..c496f8b210 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h @@ -122,6 +122,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + // Generic signals namings LED1 = PA_5, LED2 = PA_5, @@ -131,10 +143,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PA_2, - SERIAL_RX = PA_3, - USBTX = PA_2, - USBRX = PA_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PA_7, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h index 5245860102..0382c324ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralNames.h @@ -55,10 +55,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX SERIAL_TX -#define STDIO_UART_RX SERIAL_RX -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h index 0bb0d93433..2a107f9c0f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h @@ -190,6 +190,18 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_9, +#endif + // Generic signals namings LED1 = PB_0, LED2 = PB_7, @@ -199,10 +211,10 @@ typedef enum { USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PD_8, // Virtual Com Port - SERIAL_RX = PD_9, // Virtual Com Port - USBTX = SERIAL_TX, // Virtual Com Port - USBRX = SERIAL_RX, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h index 614256717e..210319584f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralNames.h @@ -57,10 +57,6 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PB_10 -#define STDIO_UART_RX PB_11 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h index 5d9786a21b..1a73dbc2e2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h @@ -237,6 +237,17 @@ typedef enum { D14 = PB_9, D15 = PB_8, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PB_10, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PB_11, +#endif // Generic signals namings LED1 = PG_6, @@ -248,10 +259,10 @@ typedef enum { USER_BUTTON = PA_0, // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = PB_10, - SERIAL_RX = PB_11, - USBTX = PB_10, - USBRX = PB_11, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, I2C_SCL = PB_8, I2C_SDA = PB_9, SPI_MOSI = PB_15, diff --git a/targets/targets.json b/targets/targets.json index 699c928905..24a4359bdd 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1903,18 +1903,13 @@ "supported_form_factors": ["ARDUINO"], "release_versions": ["5"], "config": { - "usb_tx": { + "stdio_uart_tx": { "help": "Value: D8(default) or D1", "value": "D8" }, - "usb_rx": { + "stdio_uart_rx": { "help": "Value: D2(default) or D0", "value": "D2" - }, - "stdio_uart": { - "help": "Value: UART_1(default) or UART_3", - "value": "UART_1", - "macro_name": "STDIO_UART" } } }, @@ -1922,39 +1917,19 @@ "inherits": ["MODULE_UBLOX_ODIN_W2"], "release_versions": ["5"], "config": { - "usb_tx": { + "stdio_uart_tx": { "help": "Value: PA_9(default) or PD_8", "value": "PA_9" }, - "usb_rx": { + "stdio_uart_rx": { "help": "Value: PA_10(default) or PD_9", "value": "PA_10" - }, - "stdio_uart": { - "help": "Value: UART_1(default) or UART_3", - "value": "UART_1", - "macro_name": "STDIO_UART" } } }, "MTB_UBLOX_ODIN_W2": { "inherits": ["MODULE_UBLOX_ODIN_W2"], - "release_versions": ["5"], - "config": { - "usb_tx": { - "help": "Value PA_11", - "value": "PA_11" - }, - "usb_rx": { - "help": "Value PA_13", - "value": "PA_13" - }, - "stdio_uart": { - "help": "Value: UART_1", - "value": "UART_1", - "macro_name": "STDIO_UART" - } - } + "release_versions": ["5"] }, "UBLOX_C030": { "inherits": ["FAMILY_STM32"], From 5e85ff9133fb95b8ed6a3b1132596f0241b48ef6 Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 5 Jan 2018 10:11:17 +0100 Subject: [PATCH 037/133] STM32 CAN: fix wrong ID and MASK filter --- targets/TARGET_STM/can_api.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 1f0d977b1a..246f5d1971 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -468,11 +468,11 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t sFilterConfig.FilterIdLow = 0x0; sFilterConfig.FilterMaskIdHigh = mask << 5; sFilterConfig.FilterMaskIdLow = 0x0; // allows both remote and data frames - } else if (format == CANExtended) { + } else { // format == CANExtended sFilterConfig.FilterIdHigh = id >> 13; // EXTID[28:13] - sFilterConfig.FilterIdLow = (0x00FF & (id << 3)) | (1 << 2); // EXTID[12:0] + sFilterConfig.FilterIdLow = (0xFFFF & (id << 3)) | (1 << 2); // EXTID[12:0] + IDE sFilterConfig.FilterMaskIdHigh = mask >> 13; - sFilterConfig.FilterMaskIdLow = (0x00FF & (mask << 3)) | (1 << 2); + sFilterConfig.FilterMaskIdLow = (0xFFFF & (mask << 3)) | (1 << 2); } sFilterConfig.FilterFIFOAssignment = 0; From c4bff4ef587dccc36192be7614e87e004fd9df3c Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 12 Jan 2018 11:52:47 +0100 Subject: [PATCH 038/133] STM32 LPT optimisation --- targets/TARGET_STM/lp_ticker.c | 11 ++--------- targets/TARGET_STM/rtc_api.c | 30 ++++++++++++++++++++++++++++-- targets/TARGET_STM/rtc_api_hal.h | 6 +++--- 3 files changed, 33 insertions(+), 14 deletions(-) diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index 3404994aa7..7b12b34736 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -292,15 +292,8 @@ void lp_ticker_init(void) uint32_t lp_ticker_read(void) { - uint32_t usecs = 0; - time_t time = 0; - - do { - time = rtc_read(); - usecs = rtc_read_subseconds(); - } while (time != rtc_read()); - - return (time * 1000000) + usecs; + uint32_t usecs = rtc_read_us(); + return usecs; } void lp_ticker_set_interrupt(timestamp_t timestamp) diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 9e91753c86..50e273c5ba 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -36,8 +36,12 @@ static RTC_HandleTypeDef RtcHandle; #if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM + +#define GET_TICK_PERIOD(VALUE) (2048 * 1000000 / VALUE) /* 1s / SynchPrediv value * 2^11 (value to get the maximum precision value with no u32 overflow) */ + static void (*irq_handler)(void); static void RTC_IRQHandler(void); +static uint32_t lp_TickPeriod_us = GET_TICK_PERIOD(4095); /* default SynchPrediv value = 4095 */ #endif /* DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */ void rtc_init(void) @@ -123,6 +127,10 @@ void rtc_init(void) RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; #endif /* TARGET_STM32F1 */ +#if DEVICE_LOWPOWERTIMER && !MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM + lp_TickPeriod_us = GET_TICK_PERIOD(RtcHandle.Init.SynchPrediv); +#endif + if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { error("RTC initialization failed"); } @@ -306,9 +314,27 @@ static void RTC_IRQHandler(void) } } -uint32_t rtc_read_subseconds(void) +uint32_t rtc_read_us(void) { - return 1000000.f * ((double)((RTC->PRER & RTC_PRER_PREDIV_S) - RTC->SSR) / ((RTC->PRER & RTC_PRER_PREDIV_S) + 1)); + RTC_TimeTypeDef timeStruct = {0}; + RTC_DateTypeDef dateStruct = {0}; + + RtcHandle.Instance = RTC; + HAL_RTC_GetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN); + + /* Reading RTC current time locks the values in calendar shadow registers until Current date is read + to ensure consistency between the time and date values */ + HAL_RTC_GetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN); + + if (timeStruct.SubSeconds > timeStruct.SecondFraction) { + /* SS can be larger than PREDIV_S only after a shift operation. In that case, the correct + time/date is one second less than as indicated by RTC_TR/RTC_DR. */ + timeStruct.Seconds -= 1; + } + uint32_t RTCTime = timeStruct.Seconds + timeStruct.Minutes * 60 + timeStruct.Hours * 60 * 60; + uint32_t Time_us = ((timeStruct.SecondFraction - timeStruct.SubSeconds) * lp_TickPeriod_us) >> 11; + + return (RTCTime * 1000000) + Time_us ; } void rtc_set_wake_up_timer(uint32_t delta) diff --git a/targets/TARGET_STM/rtc_api_hal.h b/targets/TARGET_STM/rtc_api_hal.h index 5013b3bbeb..ff1722a0e8 100644 --- a/targets/TARGET_STM/rtc_api_hal.h +++ b/targets/TARGET_STM/rtc_api_hal.h @@ -51,11 +51,11 @@ extern "C" { #define RTC_CLOCK LSI_VALUE #endif -/** Read the subsecond register. +/** Read RTC time with subsecond precision. * - * @return The remaining time as microseconds (0-999999) + * @return Time is microsecond */ -uint32_t rtc_read_subseconds(void); +uint32_t rtc_read_us(void); /** Program a wake up timer event in delta microseconds. * From a786d347db2e983b5f0e8b3996eb8c51d54e50ff Mon Sep 17 00:00:00 2001 From: Vincent Coubard Date: Wed, 17 Jan 2018 11:31:50 +0000 Subject: [PATCH 039/133] BLE: Fix inclusion of BLE.h (case) --- features/FEATURE_BLE/ble/pal/SimpleEventQueue.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h b/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h index a67c11bbb2..84ccacfd48 100644 --- a/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h +++ b/features/FEATURE_BLE/ble/pal/SimpleEventQueue.h @@ -20,7 +20,7 @@ #include #include "EventQueue.h" #include "ble/BLEInstanceBase.h" -#include "BLE/ble.h" +#include "ble/BLE.h" namespace ble { namespace pal { From 74fdd09939f62ca0e2a29cee0897351d6d906c77 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 18 Jan 2018 17:33:03 +0800 Subject: [PATCH 040/133] Add gpio_is_connected --- targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c | 5 +++++ targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c | 5 +++++ targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c | 5 +++++ targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c index 39f4e8e30b..27589ccc39 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c @@ -37,6 +37,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c index 1dac0de6af..9b7b15503e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_api.c @@ -37,6 +37,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c index 8a3a05332f..ac7a896ee2 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_api.c @@ -34,6 +34,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c index 39f4e8e30b..27589ccc39 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c @@ -37,6 +37,11 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << pin_index); // Return the pin mask } +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; From 0e9249a38198f22a51962daf2ef1b3a4fd122160 Mon Sep 17 00:00:00 2001 From: chrisyang Date: Mon, 15 Jan 2018 15:08:13 +0800 Subject: [PATCH 041/133] rtl8195am - move region headers to 0xb000 and 0xc000 The new layout is as follows: 0x000000 - 0x008000 => bootloader 0x008000 - 0x00b000 => system sectors 0x00b000 - 0x00c000 => region1 header 0x00c000 - 0x00d000 => region2 header 0x00d000 - 0x010000 => reserved 0x010000 - 0x040000 => mbed file system 0x040000 - 0x120000 => region1 image 0x120000 - 0x200000 => region2 image This is to ensure when daplink erases sections, both regions' headers are erased properly. --- targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c | 28 +++++++++--------- targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h | 11 +++++-- tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin | Bin 262144 -> 262144 bytes tools/targets/REALTEK_RTL8195AM.py | 3 +- 4 files changed, 24 insertions(+), 18 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c index 565b149a97..58127d457e 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c @@ -23,24 +23,24 @@ static flash_t flash_obj; -void OTA_ReadHeader(uint32_t base, imginfo_t *img) +void OTA_ReadHeader(uint32_t addr, imginfo_t *img) { uint32_t epoch_hi, epoch_lo; - if (base != OTA_REGION1_BASE || base != OTA_REGION2_BASE) { + if (addr != OTA_REGION1_HEADER || addr != OTA_REGION2_HEADER) { return; } - flash_ext_read_word(&flash_obj, base + OTA_TAG_OFS, &img->tag); - flash_ext_read_word(&flash_obj, base + OTA_VER_OFS, &img->ver); - flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS, &epoch_hi); - flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS + 4, &epoch_lo); + flash_ext_read_word(&flash_obj, addr + OTA_TAG_OFS, &img->tag); + flash_ext_read_word(&flash_obj, addr + OTA_VER_OFS, &img->ver); + flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS, &epoch_hi); + flash_ext_read_word(&flash_obj, addr + OTA_EPOCH_OFS + 4, &epoch_lo); img->timestamp = ((uint64_t)epoch_hi << 32) | (uint64_t) epoch_lo; - flash_ext_read_word(&flash_obj, base + OTA_SIZE_OFS, &img->size); - flash_ext_stream_read(&flash_obj, base + OTA_HASH_OFS, 32, img->hash); - flash_ext_stream_read(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign); - flash_ext_read_word(&flash_obj, base + OTA_CRC32_OFS, &img->crc32); + flash_ext_read_word(&flash_obj, addr + OTA_SIZE_OFS, &img->size); + flash_ext_stream_read(&flash_obj, addr + OTA_HASH_OFS, 32, img->hash); + flash_ext_stream_read(&flash_obj, addr + OTA_CAMPAIGN_OFS, 16, img->campaign); + flash_ext_read_word(&flash_obj, addr + OTA_CRC32_OFS, &img->crc32); } bool OTA_CheckHeader(imginfo_t *img) @@ -61,9 +61,9 @@ bool OTA_CheckHeader(imginfo_t *img) return true; } -void OTA_GetImageInfo(uint32_t base, imginfo_t *img) +void OTA_GetImageInfo(uint32_t header, imginfo_t *img) { - OTA_ReadHeader(base, img); + OTA_ReadHeader(header, img); if (!OTA_CheckHeader(img)) { img->timestamp = 0; @@ -77,8 +77,8 @@ uint32_t OTA_GetUpdateBase(void) { imginfo_t img1, img2; - OTA_GetImageInfo(OTA_REGION1_BASE, &img1); - OTA_GetImageInfo(OTA_REGION2_BASE, &img2); + OTA_GetImageInfo(OTA_REGION1_HEADER, &img1); + OTA_GetImageInfo(OTA_REGION2_HEADER, &img2); if (img1.valid && img2.valid) { if (img1.timestamp < img2.timestamp) { diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h index bea950e13e..7920c64b78 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h @@ -22,17 +22,20 @@ #define FLASH_SECTOR_SIZE 0x1000 #define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1) +#define OTA_REGION1_HEADER 0x0b000 +#define OTA_REGION2_HEADER 0x0c000 +#define OTA_REGION2_BASE 0x120000 #define OTA_REGION1_BASE 0x40000 #define OTA_REGION2_BASE 0x120000 #define OTA_REGION1_SIZE 0xe0000 #define OTA_REGION2_SIZE 0xe0000 #define OTA_REGION_SIZE 0xe0000 -#define OTA_MBED_FS_BASE 0xb000 +#define OTA_MBED_FS_BASE 0x10000 +#define OTA_MBED_FS_SIZE 0x30000 #define OTA_CRC32_LEN 0x44 #define OTA_HEADER_LEN 0x48 -#define OTA_HEADER_OFS 0x0 #define OTA_TAG_OFS 0x0 #define OTA_VER_OFS 0x4 #define OTA_EPOCH_OFS 0x8 @@ -57,6 +60,8 @@ typedef struct imginfo_s { uint8_t campaign[16]; uint32_t crc32; bool valid; + uint32_t header_addr; + uint32_t image_addr; } imginfo_t; #ifdef __cplusplus @@ -64,7 +69,7 @@ extern "C" { #endif extern void OTA_GetImageInfo(uint32_t base, imginfo_t *info); -extern uint32_t OTA_GetUpdateBase(void); +extern uint32_t OTA_GetUpdateRegion(void); extern uint32_t OTA_UpdateHeader(uint32_t base, imginfo_t *img); extern uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data); diff --git 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zz*4b0cCqKyAaQS60_l`LYl*iRO=Ujlq~c~aTCP>ly-z(1l)hLY2VX@_A{V^LYY z!tG)y0n=4GtO$NR2^J0J`|I#|$4(OYg^UUxvI$RBY@kE@f?QFbwb`3# z4tYM4z}X^rog2`4;h3`=IfX%|5BUV-T7}jL6|NFfSh|ICeMp*&!Km_DoVlP^yfBIX jRSO4QFVM3Ka^jut`>td6T?m8t^L-bY^YO5=YCH8mE{<(W diff --git a/tools/targets/REALTEK_RTL8195AM.py b/tools/targets/REALTEK_RTL8195AM.py index 24e9b79ceb..c5670df482 100644 --- a/tools/targets/REALTEK_RTL8195AM.py +++ b/tools/targets/REALTEK_RTL8195AM.py @@ -255,7 +255,9 @@ def create_daplink(image_bin, ram1_bin, ram2_bin): output = open(image_bin, "wb") append_image_file(ram1_bin, output) + append_image_file(ram2_bin, output) + output.seek(0xb000) line = "" for key in ['tag', 'ver', 'timestamp', 'size', 'hash', 'campaign']: line += RAM2_HEADER[key] @@ -264,7 +266,6 @@ def create_daplink(image_bin, ram1_bin, ram2_bin): RAM2_HEADER['crc32'] = format_number(crc32_checksum(line), 8) output.write(RAM2_HEADER['crc32']) - append_image_file(ram2_bin, output) output.close() # ---------------------------- From 9e813569f7144993644b974f09a76d0a2d9d6ff5 Mon Sep 17 00:00:00 2001 From: chrisyang Date: Tue, 16 Jan 2018 13:52:16 +0800 Subject: [PATCH 042/133] rtl8195am - reorder some defines properly in ota header file --- targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h | 1 - tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin | Bin 262144 -> 262144 bytes 2 files changed, 1 deletion(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h index 7920c64b78..81d89ad6d6 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h @@ -24,7 +24,6 @@ #define OTA_REGION1_HEADER 0x0b000 #define OTA_REGION2_HEADER 0x0c000 -#define OTA_REGION2_BASE 0x120000 #define OTA_REGION1_BASE 0x40000 #define OTA_REGION2_BASE 0x120000 #define OTA_REGION1_SIZE 0xe0000 diff --git a/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin b/tools/bootloaders/REALTEK_RTL8195AM/ram_1.bin index 05a44db71b3293a6722a82f6aecd3addb277df37..5179455fb5bd97b7ed828400355f94582695487c 100644 GIT binary patch delta 664 zcmXwzO=uHA6vt<>4Wy{)YMmM|0rlywcwk0W|i3v>7Y&6CXTB$;6QCg@_=|Ry; zKtYNJg|W5uCL(y~A#o21g8euZ8^vP^y-7`T>J}r3jl1jYf`|9!_kSP%H-!RSDA2ye z#rgSY`S#zHzB0AFCERR^0Ib^q9T5fxB4I(Om3*7@==T;}po%w|ZLL!^C1FLN>uu5Y z4k)i$ZJc#40}cLc@*E<*Oa5@W4oBw#ZKm zV=v?3bJC>??)>Fuz9*N8E6|c4WGLW|*9(UXmBFKopC8*#q`MJwe~YD*XB0D?Rdg{b zx${v8a$b^2;5Q7}nJzN@B{L7jcaVC;eu}FZmEl zCRoI0pfc0qP_|z1W$U4s-r)3O>1_RZN46d#%A>QyrAKq8^hUS#qIo?;m3~Y)@p$Jo z+jN0MXjo_C8`1RvkH~R`?FPt1lWaSw*FvxB?*q}jc<6_ z;qK0EdU0C0MHf?tDFUN0Pi_GR`bVlhcgV}iag{RhHy}ReK-kW1=rlW zup)1I>_o`hN1R4Y_0AA+_vo^PJc5sGRq!PD&=}yx+lUzI`bF}Yzy>L`ck4#KJ@}M} dx!{JCh%rHaP(e`O!y;t*AYN&4r*rpq?mh53zt8vle!uVUq*5rA zLj3%EIz6yZ^stH2LHz80XM80rfKL~%RI|3c&6D=@<>PL!>c?k#1|hC#>c z#Y1m^@}goDY`Y`S;GD^$CNG(M-sJZtUo!b!ejhoj`9(ZLC9EQs0eO+xQHFmGlqY0S0HN;Edu&(l&hdTPIhVLfAW@=(hdgeT>f zhocY{$cAGF7UUn!S}Nq Date: Wed, 17 Jan 2018 14:30:45 +0200 Subject: [PATCH 043/133] NSAPI: Add Nanostack multicast membership support Add support for recently introduced NSAPI generic socket options to control group membership. Previously applications using Nanostack would have had to use Nanostack's native socket options. --- .../NanostackInterface.cpp | 61 ++++++++++++++++--- 1 file changed, 54 insertions(+), 7 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp index 739871c540..c85cfca2a9 100644 --- a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.cpp @@ -128,6 +128,20 @@ static void convert_ns_addr_to_mbed(SocketAddress *s_addr, const ns_address_t *n s_addr->set_ip_bytes(ns_addr->address, NSAPI_IPv6); } +static int8_t find_interface_by_address(const uint8_t target_addr[16]) +{ + for (int if_id = 1; if_id <= 127; if_id++) { + int i = 0; + uint8_t if_addr[16]; + while (arm_net_address_list_get_next(if_id, &i, if_addr) == 0) { + if (memcmp(target_addr, if_addr, 16) == 0) { + return if_id; + } + } + } + return -1; +} + void* NanostackSocket::operator new(std::size_t sz) { return MALLOC(sz); } @@ -693,17 +707,50 @@ nsapi_error_t NanostackInterface::setsockopt(void *handle, int level, int optnam return NSAPI_ERROR_NO_SOCKET; } - nsapi_error_t ret; - NanostackLockGuard lock; - if (::socket_setsockopt(socket->socket_id, level, optname, optval, optlen) == 0) { - ret = NSAPI_ERROR_OK; - } else { - ret = NSAPI_ERROR_PARAMETER; + ns_ipv6_mreq_t ns_mreq; + + if (level == NSAPI_SOCKET) { + switch (optname) { + case NSAPI_ADD_MEMBERSHIP: + case NSAPI_DROP_MEMBERSHIP: { + if (optlen != sizeof(nsapi_ip_mreq_t)) { + return NSAPI_ERROR_PARAMETER; + } + const nsapi_ip_mreq_t *imr = static_cast(optval); + + /* Check address types are IPv6, or unspecified for interface */ + if (imr->imr_multiaddr.version != NSAPI_IPv6 || + (imr->imr_interface.version != NSAPI_UNSPEC && imr->imr_interface.version != NSAPI_IPv6)) { + return NSAPI_ERROR_PARAMETER; + } + + /* Convert all parameters to Nanostack native, and proceed with setsockopt */ + memcpy(ns_mreq.ipv6mr_multiaddr, imr->imr_multiaddr.bytes, 16); + if (imr->imr_interface.version == NSAPI_UNSPEC || memcmp(imr->imr_interface.bytes, ns_in6addr_any, 16) == 0) { + ns_mreq.ipv6mr_interface = 0; + } else { + // If this fails, Nanostack will itself fault the invalid -1 interface ID + ns_mreq.ipv6mr_interface = find_interface_by_address(imr->imr_interface.bytes); + } + + level = SOCKET_IPPROTO_IPV6; + optname = optname == NSAPI_ADD_MEMBERSHIP ? SOCKET_IPV6_JOIN_GROUP : SOCKET_IPV6_LEAVE_GROUP; + optval = &ns_mreq; + optlen = sizeof ns_mreq; + break; + } + default: + return NSAPI_ERROR_PARAMETER; + } } - return ret; + if (::socket_setsockopt(socket->socket_id, level, optname, optval, optlen) == 0) { + return NSAPI_ERROR_OK; + } else { + return NSAPI_ERROR_PARAMETER; + } } nsapi_error_t NanostackInterface::getsockopt(void *handle, int level, int optname, void *optval, unsigned *optlen) From c917231427d88b2ff81752b43783e0b2194e8846 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Wed, 27 Dec 2017 13:53:35 -0600 Subject: [PATCH 044/133] littlefs: Fixed issue with immediate exhaustion and small unaligned storage This was a small hole in the logic that handles initializing the lookahead buffer. To imitate exhaustion (so the block allocator will trigger a scan), the lookahead buffer is rewound a full lookahead and set up to look like it is exhausted. However, unlike normal allocation, this rewind was not kept aligned to a multiple of the scan size, which is limited by both the lookahead buffer and the total storage size. This bug went unnoticed for so long because it only causes problems when the block device is both: 1. Not aligned to the lookahead buffer (not a power of 2) 2. Smaller than the lookahead buffer While this seems like a strange corner case for a block device, this turned out to be very common for internal flash, especially when a handleful of blocks are reserved for code. --- .travis.yml | 9 ++++----- features/filesystem/littlefs/littlefs/.travis.yml | 7 +++---- features/filesystem/littlefs/littlefs/lfs.c | 6 +++--- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/.travis.yml b/.travis.yml index 15296cb3f1..40d81b43e7 100644 --- a/.travis.yml +++ b/.travis.yml @@ -142,11 +142,10 @@ matrix: # Run local littlefs tests - CFLAGS="-Wno-format" make -C$LITTLEFS/littlefs test QUIET=1 # Run local littlefs tests with set of variations - - CFLAGS="-Wno-format -DLFS_READ_SIZE=64 -DLFS_PROG_SIZE=64" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_BLOCK_COUNT=1023" make -C$LITTLEFS/littlefs test QUIET=1 - - CFLAGS="-Wno-format -DLFS_LOOKAHEAD=2048" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_READ_SIZE=64 -DLFS_PROG_SIZE=64" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make -C$LITTLEFS/littlefs test QUIET=1 + - CFLAGS="-Wno-format -DLFS_BLOCK_COUNT=1023 -DLFS_LOOKAHEAD=2048" make -C$LITTLEFS/littlefs test QUIET=1 # Self-hosting littlefs fuzz test with littlefs-fuse - make -Clittlefs_fuse - littlefs_fuse/lfs --format /dev/loop0 diff --git a/features/filesystem/littlefs/littlefs/.travis.yml b/features/filesystem/littlefs/littlefs/.travis.yml index d673c159ab..c17af8b17b 100644 --- a/features/filesystem/littlefs/littlefs/.travis.yml +++ b/features/filesystem/littlefs/littlefs/.travis.yml @@ -12,10 +12,9 @@ script: - make test QUIET=1 # run tests with a few different configurations - - CFLAGS="-DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make test QUIET=1 - - CFLAGS="-DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make test QUIET=1 - - CFLAGS="-DLFS_BLOCK_COUNT=1023" make test QUIET=1 - - CFLAGS="-DLFS_LOOKAHEAD=2048" make test QUIET=1 + - CFLAGS="-DLFS_READ_SIZE=1 -DLFS_PROG_SIZE=1" make test QUIET=1 + - CFLAGS="-DLFS_READ_SIZE=512 -DLFS_PROG_SIZE=512" make test QUIET=1 + - CFLAGS="-DLFS_BLOCK_COUNT=1023 -DLFS_LOOKAHEAD=2048" make test QUIET=1 # self-host with littlefs-fuse for fuzz test - make -C littlefs-fuse diff --git a/features/filesystem/littlefs/littlefs/lfs.c b/features/filesystem/littlefs/littlefs/lfs.c index cc6713a03d..f83624ec92 100644 --- a/features/filesystem/littlefs/littlefs/lfs.c +++ b/features/filesystem/littlefs/littlefs/lfs.c @@ -2039,9 +2039,9 @@ int lfs_mount(lfs_t *lfs, const struct lfs_config *cfg) { return err; } - // setup free lookahead - lfs->free.begin = -lfs->cfg->lookahead; - lfs->free.off = lfs->cfg->lookahead; + // setup free lookahead, rewind so first allocation triggers a scan + lfs->free.begin = -lfs_min(lfs->cfg->lookahead, lfs->cfg->block_count); + lfs->free.off = -lfs->free.begin; lfs->free.end = lfs->free.begin + lfs->free.off + lfs->cfg->block_count; // load superblock From 08a4b0e4b654b68cd8754dd3e372f29fc38963cc Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Tue, 9 Jan 2018 15:01:16 -0600 Subject: [PATCH 045/133] Added COMMON folder for tests A COMMON folder allows code reuse across different test cases. This avoids code duplication or code enterying the application space. The COMMON folder is uppercase to match naming conventions in Mbed OS. --- .../COMMON}/atomic_usage.cpp | 0 .../COMMON}/atomic_usage.h | 0 tools/test_api.py | 61 ++++++++++++++----- 3 files changed, 45 insertions(+), 16 deletions(-) rename features/filesystem/littlefs/{TESTS_COMMON => TESTS/COMMON}/atomic_usage.cpp (100%) rename features/filesystem/littlefs/{TESTS_COMMON => TESTS/COMMON}/atomic_usage.h (100%) diff --git a/features/filesystem/littlefs/TESTS_COMMON/atomic_usage.cpp b/features/filesystem/littlefs/TESTS/COMMON/atomic_usage.cpp similarity index 100% rename from features/filesystem/littlefs/TESTS_COMMON/atomic_usage.cpp rename to features/filesystem/littlefs/TESTS/COMMON/atomic_usage.cpp diff --git a/features/filesystem/littlefs/TESTS_COMMON/atomic_usage.h b/features/filesystem/littlefs/TESTS/COMMON/atomic_usage.h similarity index 100% rename from features/filesystem/littlefs/TESTS_COMMON/atomic_usage.h rename to features/filesystem/littlefs/TESTS/COMMON/atomic_usage.h diff --git a/tools/test_api.py b/tools/test_api.py index 2e7d60a275..4569ea3597 100644 --- a/tools/test_api.py +++ b/tools/test_api.py @@ -28,6 +28,7 @@ import argparse import datetime import threading import ctypes +import functools from types import ListType from colorama import Fore, Back, Style from prettytable import PrettyTable @@ -71,7 +72,6 @@ from tools.utils import argparse_filestring_type from tools.utils import argparse_uppercase_type from tools.utils import argparse_lowercase_type from tools.utils import argparse_many -from tools.utils import get_path_depth import tools.host_tests.host_tests_plugins as host_tests_plugins @@ -2019,9 +2019,15 @@ def find_tests(base_dir, target_name, toolchain_name, app_config=None): toolchain_name: name of the toolchain to use for scanning (ex. 'GCC_ARM') options: Compile options to pass to the toolchain (ex. ['debug-info']) app_config - location of a chosen mbed_app.json file + + returns a dictionary where keys are the test name, and the values are + lists of paths needed to biuld the test. """ + # Temporary structure: tests referenced by (name, base, group, case) tuple tests = {} + # List of common folders: (predicate function, path) tuple + commons = [] # Prepare the toolchain toolchain = prepare_toolchain([base_dir], None, target_name, toolchain_name, @@ -2042,32 +2048,52 @@ def find_tests(base_dir, target_name, toolchain_name, app_config=None): # Loop through all subdirectories for d in test_resources.inc_dirs: - # If the test case folder is not called 'host_tests' and it is + # If the test case folder is not called 'host_tests' or 'COMMON' and it is # located two folders down from the main 'TESTS' folder (ex. TESTS/testgroup/testcase) # then add it to the tests - path_depth = get_path_depth(relpath(d, walk_base_dir)) - if path_depth == 2: + relative_path = relpath(d, walk_base_dir) + relative_path_parts = os.path.normpath(relative_path).split(os.sep) + if len(relative_path_parts) == 2: test_group_directory_path, test_case_directory = os.path.split(d) test_group_directory = os.path.basename(test_group_directory_path) - # Check to make sure discoverd folder is not in a host test directory - if test_case_directory != 'host_tests' and test_group_directory != 'host_tests': + # Check to make sure discoverd folder is not in a host test directory or common directory + special_dirs = ['host_tests', 'COMMON'] + if test_group_directory not in special_dirs and test_case_directory not in special_dirs: test_name = test_path_to_name(d, base_dir) - tests[test_name] = d + tests[(test_name, walk_base_dir, test_group_directory, test_case_directory)] = [d] - return tests + # Also find any COMMON paths, we'll add these later once we find all the base tests + if 'COMMON' in relative_path_parts: + if relative_path_parts[0] != 'COMMON': + def predicate(base_pred, group_pred, (name, base, group, case)): + return base == base_pred and group == group_pred + commons.append((functools.partial(predicate, walk_base_dir, relative_path_parts[0]), d)) + else: + def predicate(base_pred, (name, base, group, case)): + return base == base_pred + commons.append((functools.partial(predicate, walk_base_dir), d)) + + # Apply common directories + for pred, path in commons: + for test_identity, test_paths in tests.iteritems(): + if pred(test_identity): + test_paths.append(path) + + # Drop identity besides name + return {name: paths for (name, _, _, _), paths in tests.iteritems()} def print_tests(tests, format="list", sort=True): """Given a dictionary of tests (as returned from "find_tests"), print them in the specified format""" if format == "list": for test_name in sorted(tests.keys()): - test_path = tests[test_name] + test_path = tests[test_name][0] print "Test Case:" print " Name: %s" % test_name print " Path: %s" % test_path elif format == "json": - print json.dumps(tests, indent=2) + print json.dumps({test_name: test_path[0] for test_name, test_paths in tests}, indent=2) else: print "Unknown format '%s'" % format sys.exit(1) @@ -2164,13 +2190,16 @@ def build_tests(tests, base_source_paths, build_path, target, toolchain_name, jobs_count = int(jobs if jobs else cpu_count()) p = Pool(processes=jobs_count) results = [] - for test_name, test_path in tests.iteritems(): - test_build_path = os.path.join(build_path, test_path) - src_path = base_source_paths + [test_path] - bin_file = None - test_case_folder_name = os.path.basename(test_path) + for test_name, test_paths in tests.iteritems(): + if type(test_paths) != ListType: + test_paths = [test_paths] - args = (src_path, test_build_path, target, toolchain_name) + test_build_path = os.path.join(build_path, test_paths[0]) + src_paths = base_source_paths + test_paths + bin_file = None + test_case_folder_name = os.path.basename(test_paths[0]) + + args = (src_paths, test_build_path, target, toolchain_name) kwargs = { 'jobs': 1, 'clean': clean, From 8801b0f0e9552de4c74a05250097feb9e9e67ba3 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Fri, 12 Jan 2018 14:02:31 +0200 Subject: [PATCH 046/133] Squashed 'features/nanostack/FEATURE_NANOSTACK/coap-service/' changes from d0a2597..8689fca 8689fca Reverting address check from transaction find (#89) ca3c3ab Fix transactions to handle all token lengths (#87) git-subtree-dir: features/nanostack/FEATURE_NANOSTACK/coap-service git-subtree-split: 8689fca7b18e03776dce7083a03bd570a8bc0d43 --- .../FEATURE_NANOSTACK/coap-service/Makefile | 3 --- .../source/coap_message_handler.c | 22 ++++++++++++------- .../source/include/coap_message_handler.h | 7 +++--- 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile b/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile index c808df6170..f104a78110 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/Makefile @@ -48,10 +48,7 @@ override CFLAGS += -I$(EVENTLOOP_DIR)/nanostack-event-loop/ COAPSERVICE_DIR := ../coap-service override CFLAGS += -I$(COAPSERVICE_DIR)/coap-service/ override CFLAGS += -I$(COAPSERVICE_DIR)/source/include/ - -ifeq (Linux,$(shell uname)) override CFLAGS += -DHAVE_DEBUG -endif LIB = libcoap-service.a diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c index 3d6c91a031..1a28037455 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/coap_message_handler.c @@ -46,13 +46,16 @@ static void own_free(void *ptr) static NS_LIST_DEFINE(request_list, coap_transaction_t, link); -static coap_transaction_t *transaction_find_client_by_token(uint8_t token[4]) +static coap_transaction_t *transaction_find_client_by_token(uint8_t *token, uint8_t token_len, const uint8_t address[static 16], uint16_t port) { + (void) address; + (void) port; coap_transaction_t *this = NULL; + ns_list_foreach(coap_transaction_t, cur_ptr, &request_list) { - if (memcmp(cur_ptr->token,token,4) == 0 && cur_ptr->client_request) { + if ((cur_ptr->token_len == token_len) && (memcmp(cur_ptr->token, token, token_len) == 0) && cur_ptr->client_request) { this = cur_ptr; - break; + break; } } return this; @@ -147,12 +150,13 @@ static int8_t coap_rx_function(sn_coap_hdr_s *resp_ptr, sn_nsdl_addr_s *address_ coap_transaction_t *this = NULL; (void)address_ptr; (void)param; + tr_warn("transaction was not handled %d", resp_ptr->msg_id); if (!resp_ptr) { return -1; } - if( resp_ptr->token_ptr ){ - this = transaction_find_client_by_token(resp_ptr->token_ptr); + if(resp_ptr->token_ptr){ + this = transaction_find_client_by_token(resp_ptr->token_ptr, resp_ptr->token_len, address_ptr->addr_ptr, address_ptr->port); } if (!this) { return 0; @@ -278,6 +282,7 @@ int16_t coap_message_handler_coap_msg_process(coap_msg_handler_t *handle, int8_t memcpy(transaction_ptr->remote_address, source_addr_ptr, 16); if (coap_message->token_len) { memcpy(transaction_ptr->token, coap_message->token_ptr, coap_message->token_len); + transaction_ptr->token_len = coap_message->token_len; } transaction_ptr->remote_port = port; if (cb(socket_id, coap_message, transaction_ptr) < 0) { @@ -292,7 +297,7 @@ int16_t coap_message_handler_coap_msg_process(coap_msg_handler_t *handle, int8_t } else { coap_transaction_t *this = NULL; if (coap_message->token_ptr) { - this = transaction_find_client_by_token(coap_message->token_ptr); + this = transaction_find_client_by_token(coap_message->token_ptr, coap_message->token_len, source_addr_ptr, port); } if (!this) { tr_error("client transaction not found"); @@ -352,8 +357,9 @@ uint16_t coap_message_handler_request_send(coap_msg_handler_t *handle, int8_t se do{ randLIB_get_n_bytes_random(token,4); - }while(transaction_find_client_by_token(token)); + }while(transaction_find_client_by_token(token, 4, destination_addr, destination_port)); memcpy(transaction_ptr->token,token,4); + transaction_ptr->token_len = 4; request.token_ptr = transaction_ptr->token; request.token_len = 4; @@ -464,7 +470,7 @@ int8_t coap_message_handler_response_send_by_msg_id(coap_msg_handler_t *handle, response.payload_len = payload_len; response.payload_ptr = (uint8_t *) payload_ptr; // Cast away const and trust that nsdl doesn't modify... response.content_format = content_type; - response.token_len = 4; + response.token_len = transaction_ptr->token_len; response.token_ptr = transaction_ptr->token; response.msg_code = message_code; if (transaction_ptr->req_msg_type == COAP_MSG_TYPE_CONFIRMABLE) { diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h index a484216900..35c6af129b 100644 --- a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h +++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_message_handler.h @@ -50,18 +50,19 @@ typedef struct coap_msg_handler_s { typedef struct coap_transaction { uint8_t remote_address[16]; uint8_t local_address[16]; - uint8_t token[4]; + uint8_t token[8]; uint32_t create_time; + uint8_t *data_ptr; + coap_message_handler_response_recv *resp_cb; uint16_t remote_port; uint16_t msg_id; uint16_t data_len; int8_t service_id; uint8_t options; - uint8_t *data_ptr; + uint8_t token_len; sn_coap_msg_type_e req_msg_type; bool client_request: 1; - coap_message_handler_response_recv *resp_cb; ns_list_link_t link; } coap_transaction_t; From 4e38baf6379b68da1af468ebf8c783a18a8fc988 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Thu, 18 Jan 2018 17:08:59 +0000 Subject: [PATCH 047/133] Adding MTB MTS_Dragonfly as a new target --- .../PeripheralNames.h | 82 + .../TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c | 212 + .../TARGET_MTB_MTS_DRAGONFLY/PinNames.h | 230 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S | 373 + .../TOOLCHAIN_ARM_MICRO/stm32f411re.sct | 47 + .../TOOLCHAIN_ARM_STD/startup_stm32f411xe.S | 346 + .../device/TOOLCHAIN_ARM_STD/stm32f411re.sct | 47 + .../device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_STM32F41x.S | 297 + .../TOOLCHAIN_IAR/startup_stm32f411xe.S | 523 + .../device/TOOLCHAIN_IAR/stm32f411xe.icf | 32 + .../TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h | 38 + .../device/cmsis_nvic.h | 41 + .../device/hal_tick.h | 66 + .../device/stm32f411xe.h | 8683 +++++++++++++++++ .../device/stm32f4xx.h | 271 + .../device/system_clock.c | 246 + .../device/system_stm32f4xx.h | 125 + .../TARGET_MTB_MTS_DRAGONFLY/objects.h | 63 + .../onboard_modem_api.c | 65 + targets/targets.json | 41 + .../MTB_MTS_DRAGONFLY/bootloader.bin | Bin 0 -> 55608 bytes tools/targets/__init__.py | 5 + 23 files changed, 11986 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/hal_tick.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f4xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c create mode 100644 tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h new file mode 100644 index 0000000000..15a5c2bc7a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PB_6 +#define STDIO_UART_RX PB_7 +#define STDIO_UART UART_1 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c new file mode 100644 index 0000000000..7c2b21786f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralPins.c @@ -0,0 +1,212 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO +// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK +// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h new file mode 100644 index 0000000000..941228cae4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h @@ -0,0 +1,230 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + // Not connected + NC = -1, + + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Module pins + // Defined based on the external pin (40-pin connector) alternate function mapping (Page 15 of MTQ-H5-B01 device guide) + // Device guide used: S000628,Version1.4 + P_1 = PB_6, + P_2 = PA_14, + P_3 = PA_15, + P_4 = PB_4, + P_5 = NC, + P_6 = NC, + P_7 = NC, + P_8 = NC, + P_9 = PA_2, + P_10 = PA_7, + P_11 = PB_1, + P_12 = PA_1, + P_13 = NC, + P_14 = PB_5, + P_15 = PA_5, + P_16 = PB_8, + P_17 = PB_15, + P_18 = PC_2, + P_19 = PB_0, + P_20 = PC_0, + P_21 = PC_1, + P_22 = PC_4, + P_23 = PB_13, + P_24 = PC_9, + P_25 = PB_9, + P_26 = PA_6, + P_27 = PC_8, + P_28 = NC, + P_29 = PA_0, + P_30 = PA_9, + P_31 = PA_8, + P_32 = PA_3, + P_33 = NC, + P_34 = NC, + P_35 = NC, + P_36 = NC, + P_37 = NC, + P_38 = PB_3, + P_39 = PA_13, + P_40 = PB_7, + + //DAPLink + USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = MBED_CONF_TARGET_USB_RX, + SWDIO = PA_13, + SWCLK = PA_14, + + I2C1_SCL = PB_8, + I2C1_SDA = PB_9, + I2C3_SCL = PA_8, + I2C3_SDA = PC_9, + + I2C_SCL = I2C1_SCL, + I2C_SDA = I2C1_SDA, + + SPI1_MOSI = PB_5, + SPI1_MISO = PA_6, + SPI1_SCK = PA_5, + SPI2_MOSI = PB_15, + SPI2_MISO = PC_2, + SPI2_SCK = PB_13, + + SPI_MOSI = SPI1_MOSI, + SPI_MISO = SPI1_MISO, + SPI_SCK = SPI1_SCK, + SPI_CS1 = PA_3, //LCD CS + SPI_CS2 = PA_15, //SD Card CS + + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + SERIAL_RTS = PA_0, + SERIAL_CTS = PA_1, + SERIAL_DCD = PA_7, + SERIAL_DSR = PA_9, + SERIAL_DTR = PA_8, + SERIAL_RI = PB_1, + + WAKEUP = PA_0, + + // Generic signals namings + LED1 = PA_7, + LED2 = PC_4, + LED3 = PB_13, //MTB mapped to LINK_STATUS pin on module. + SW1 = PB_4, + GPIO1 = PC_8, + GPIO3 = PB_1, + AIN0 = PB_0, + AIN1 = PC_0, + AIN2 = PC_1, + + //Standardized button names + BUTTON1 = SW1, + + RADIO_TX = PC_7, + RADIO_RX = PC_6, + RADIO_RTS = PB_10, + RADIO_CTS = PB_12, + RADIO_DCD = NC, + RADIO_DSR = NC, + RADIO_DTR = NC, + RADIO_RI = NC, + MDMPWRON = PC_13, // 3G_ONOFF DragonFly Design Guide, Page No. 16 + MDMTXD = RADIO_TX, // Transmit Data + MDMRXD = RADIO_RX, // Receive Data + MDMRTS = RADIO_RTS, // Request to Send + MDMCTS = RADIO_CTS, // Clear to Send + MDMDCD = RADIO_DCD, // Data Carrier Detect + MDMDSR = RADIO_DSR, // Data Set Ready + MDMDTR = RADIO_DTR, // Data Terminal Ready + MDMRI = RADIO_RI, // Ring Indicator + +} PinName; + +#define ACTIVE_HIGH_POLARITY 1 +#define ACTIVE_LOW_POLARITY 0 + +#define MDM_PIN_POLARITY ACTIVE_HIGH_POLARITY + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S new file mode 100644 index 0000000000..aa7d51ad14 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S @@ -0,0 +1,373 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct new file mode 100644 index 0000000000..491087ba47 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/stm32f411re.sct @@ -0,0 +1,47 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region + + ER_IROM1 0x08010000 0x70000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM + RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S new file mode 100644 index 0000000000..effaaf1e52 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S @@ -0,0 +1,346 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct new file mode 100644 index 0000000000..491087ba47 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/stm32f411re.sct @@ -0,0 +1,47 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +; FIRST 64 KB FLASH FOR BOOTLOADER +; REST 448 KB FLASH FOR APPLICATION +LR_IROM1 0x08010000 0x70000 { ; load region size_region + + ER_IROM1 0x08010000 0x70000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM + RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld new file mode 100644 index 0000000000..a832fffb7e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld @@ -0,0 +1,153 @@ +/* Linker script for STM32F411 */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + /* First 64kB of flash reserved for bootloader */ + /* Other 448kB for application */ + FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K +/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */ + RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S new file mode 100644 index 0000000000..b7f10ce5fc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S @@ -0,0 +1,297 @@ +/* File: startup_STM32F40x.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 09 July 2012 + * + * Copyright (c) 2011, 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WWDG_IRQHandler /* Window WatchDog */ + .long PVD_IRQHandler /* PVD through EXTI Line detection */ + .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .long FLASH_IRQHandler /* FLASH */ + .long RCC_IRQHandler /* RCC */ + .long EXTI0_IRQHandler /* EXTI Line0 */ + .long EXTI1_IRQHandler /* EXTI Line1 */ + .long EXTI2_IRQHandler /* EXTI Line2 */ + .long EXTI3_IRQHandler /* EXTI Line3 */ + .long EXTI4_IRQHandler /* EXTI Line4 */ + .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long EXTI9_5_IRQHandler /* External Line[9:5]s */ + .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .long TIM2_IRQHandler /* TIM2 */ + .long TIM3_IRQHandler /* TIM3 */ + .long TIM4_IRQHandler /* TIM4 */ + .long I2C1_EV_IRQHandler /* I2C1 Event */ + .long I2C1_ER_IRQHandler /* I2C1 Error */ + .long I2C2_EV_IRQHandler /* I2C2 Event */ + .long I2C2_ER_IRQHandler /* I2C2 Error */ + .long SPI1_IRQHandler /* SPI1 */ + .long SPI2_IRQHandler /* SPI2 */ + .long USART1_IRQHandler /* USART1 */ + .long USART2_IRQHandler /* USART2 */ + .long 0 /* Reserved */ + .long EXTI15_10_IRQHandler /* External Line[15:10]s */ + .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .long 0 /* Reserved */ + .long SDIO_IRQHandler /* SDIO */ + .long TIM5_IRQHandler /* TIM5 */ + .long SPI3_IRQHandler /* SPI3 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long OTG_FS_IRQHandler /* USB OTG FS */ + .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .long USART6_IRQHandler /* USART6 */ + .long I2C3_EV_IRQHandler /* I2C3 event */ + .long I2C3_ER_IRQHandler /* I2C3 error */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long FPU_IRQHandler /* FPU */ + .long SPI4_IRQHandler /* SPI4 */ + .long SPI5_IRQHandler /* SPI5 */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler WWDG_IRQHandler + def_irq_default_handler PVD_IRQHandler + def_irq_default_handler TAMP_STAMP_IRQHandler + def_irq_default_handler RTC_WKUP_IRQHandler + def_irq_default_handler FLASH_IRQHandler + def_irq_default_handler RCC_IRQHandler + def_irq_default_handler EXTI0_IRQHandler + def_irq_default_handler EXTI1_IRQHandler + def_irq_default_handler EXTI2_IRQHandler + def_irq_default_handler EXTI3_IRQHandler + def_irq_default_handler EXTI4_IRQHandler + def_irq_default_handler DMA1_Stream0_IRQHandler + def_irq_default_handler DMA1_Stream1_IRQHandler + def_irq_default_handler DMA1_Stream2_IRQHandler + def_irq_default_handler DMA1_Stream3_IRQHandler + def_irq_default_handler DMA1_Stream4_IRQHandler + def_irq_default_handler DMA1_Stream5_IRQHandler + def_irq_default_handler DMA1_Stream6_IRQHandler + def_irq_default_handler ADC_IRQHandler + def_irq_default_handler EXTI9_5_IRQHandler + def_irq_default_handler TIM1_BRK_TIM9_IRQHandler + def_irq_default_handler TIM1_UP_TIM10_IRQHandler + def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler + def_irq_default_handler TIM1_CC_IRQHandler + def_irq_default_handler TIM2_IRQHandler + def_irq_default_handler TIM3_IRQHandler + def_irq_default_handler TIM4_IRQHandler + def_irq_default_handler I2C1_EV_IRQHandler + def_irq_default_handler I2C1_ER_IRQHandler + def_irq_default_handler I2C2_EV_IRQHandler + def_irq_default_handler I2C2_ER_IRQHandler + def_irq_default_handler SPI1_IRQHandler + def_irq_default_handler SPI2_IRQHandler + def_irq_default_handler USART1_IRQHandler + def_irq_default_handler USART2_IRQHandler + def_irq_default_handler EXTI15_10_IRQHandler + def_irq_default_handler RTC_Alarm_IRQHandler + def_irq_default_handler OTG_FS_WKUP_IRQHandler + def_irq_default_handler DMA1_Stream7_IRQHandler + def_irq_default_handler SDIO_IRQHandler + def_irq_default_handler TIM5_IRQHandler + def_irq_default_handler SPI3_IRQHandler + def_irq_default_handler DMA2_Stream0_IRQHandler + def_irq_default_handler DMA2_Stream1_IRQHandler + def_irq_default_handler DMA2_Stream2_IRQHandler + def_irq_default_handler DMA2_Stream3_IRQHandler + def_irq_default_handler DMA2_Stream4_IRQHandler + def_irq_default_handler OTG_FS_IRQHandler + def_irq_default_handler DMA2_Stream5_IRQHandler + def_irq_default_handler DMA2_Stream6_IRQHandler + def_irq_default_handler DMA2_Stream7_IRQHandler + def_irq_default_handler USART6_IRQHandler + def_irq_default_handler I2C3_EV_IRQHandler + def_irq_default_handler I2C3_ER_IRQHandler + def_irq_default_handler FPU_IRQHandler + def_irq_default_handler SPI4_IRQHandler + def_irq_default_handler SPI5_IRQHandler + def_irq_default_handler DEF_IRQHandler + + .end diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S new file mode 100644 index 0000000000..1b782c36dc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S @@ -0,0 +1,523 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf new file mode 100644 index 0000000000..87e12d26bb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/stm32f411xe.icf @@ -0,0 +1,32 @@ +/* [ROM = 512kb = 0x80000] */ +define symbol __intvec_start__ = 0x08010000; +define symbol __region_ROM_start__ = 0x08010000; +define symbol __region_ROM_end__ = 0x0807FFFF; + +/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000198; +define symbol __region_RAM_end__ = 0x2001FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +/* Stack: 4kB - 408B for vector table */ +/* Heap: 64kB */ +define symbol __size_cstack__ = 0xe68; +define symbol __size_heap__ = 0x10000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h new file mode 100644 index 0000000000..f0c2b2a907 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h new file mode 100644 index 0000000000..e44a1ce9f6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/cmsis_nvic.h @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/hal_tick.h new file mode 100644 index 0000000000..cedecee545 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/hal_tick.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "stm32f4xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() + +#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() + +#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h new file mode 100644 index 0000000000..c9e8ed9d04 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f411xe.h @@ -0,0 +1,8683 @@ +/** + ****************************************************************************** + * @file stm32f411xe.h + * @author MCD Application Team + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - peripherals registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f411xe + * @{ + */ + +#ifndef __STM32F411xE_H +#define __STM32F411xE_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /* __FPU_PRESENT */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ +#define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ +#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END 0x0807FFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) +#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U) +/* Legacy define */ +#define ADC_BASE ADC1_COMMON_BASE +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) + + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000U +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U + +#define USB_OTG_GLOBAL_BASE 0x000U +#define USB_OTG_DEVICE_BASE 0x800U +#define USB_OTG_IN_ENDPOINT_BASE 0x900U +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U +#define USB_OTG_EP_REG_SIZE 0x20U +#define USB_OTG_HOST_BASE 0x400U +#define USB_OTG_HOST_PORT_BASE 0x440U +#define USB_OTG_HOST_CHANNEL_BASE 0x500U +#define USB_OTG_HOST_CHANNEL_SIZE 0x20U +#define USB_OTG_PCGCCTL_BASE 0xE00U +#define USB_OTG_FIFO_BASE 0x1000U +#define USB_OTG_FIFO_SIZE 0x1000U + +#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +/* Legacy define */ +#define ADC ADC1_COMMON +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F4) +#define STM32F4 +#endif /* STM32F4 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \ + !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \ + !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \ + !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */ + /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */ + /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */ + #define STM32F411xE /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, + and STM32F446ZE Devices */ + /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, + STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */ + /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG + and STM32F479NG Devices */ + /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */ + /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */ + /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */ + /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */ + /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG, + STM32F413RG, STM32F413VG and STM32F413ZG Devices */ + /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS version number V2.6.1 + */ +#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F410Tx) + #include "stm32f410tx.h" +#elif defined(STM32F410Cx) + #include "stm32f410cx.h" +#elif defined(STM32F410Rx) + #include "stm32f410rx.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#elif defined(STM32F446xx) + #include "stm32f446xx.h" +#elif defined(STM32F469xx) + #include "stm32f469xx.h" +#elif defined(STM32F479xx) + #include "stm32f479xx.h" +#elif defined(STM32F412Cx) + #include "stm32f412cx.h" +#elif defined(STM32F412Zx) + #include "stm32f412zx.h" +#elif defined(STM32F412Rx) + #include "stm32f412rx.h" +#elif defined(STM32F412Vx) + #include "stm32f412vx.h" +#elif defined(STM32F413xx) + #include "stm32f413xx.h" +#elif defined(STM32F423xx) + #include "stm32f423xx.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0U, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c new file mode 100644 index 0000000000..eee454211d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c @@ -0,0 +1,246 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 50 | 50 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "mbed_debug.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif + + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (0) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ +#if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) { + while(1) { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/******************************************************************************/ +/* Hard Fault Handler */ +/******************************************************************************/ +void HardFault_Handler(void) +{ + debug("Hard Fault\n"); + NVIC_SystemReset(); +} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h new file mode 100644 index 0000000000..113f67cfe6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h new file mode 100644 index 0000000000..16467b7c87 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/objects.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c new file mode 100644 index 0000000000..ea532df442 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if MBED_CONF_NSAPI_PRESENT + +#include "cellular/onboard_modem_api.h" +#include "gpio_api.h" +#include "platform/mbed_wait_api.h" +#include "PinNames.h" + +#if MODEM_ON_BOARD + +static void press_power_button(int time_ms) +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, MDMPWRON, 1); + gpio_write(&gpio, 0); + wait_ms(time_ms); + gpio_write(&gpio, 1); +} + +void onboard_modem_init() +{ + //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed +} + +void onboard_modem_deinit() +{ + //does nothing at the moment, TODO: MultiTech to add hardware de-initialization stuff if needed +} +void onboard_modem_power_up() +{ + /* keep the power line low for 200 milisecond */ + press_power_button(200); + /* give modem a little time to respond */ + wait_ms(100); +} + +void onboard_modem_power_down() +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, MDMPWRON, 0); + /* keep the power line low for more than 10 seconds. + * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes + * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10 + * seconds only */ + wait_ms(10*1000); +} +#endif //MODEM_ON_BOARD +#endif //MBED_CONF_NSAPI_PRESENT diff --git a/targets/targets.json b/targets/targets.json index 24a4359bdd..a5f81fec96 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1844,6 +1844,47 @@ "release_versions": ["2", "5"], "device_name": "STM32F411RE" }, + "MTB_MTS_DRAGONFLY": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32F4", "STM32F411RE"], + "config": { + "modem_is_on_board": { + "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.", + "value": 1, + "macro_name": "MODEM_ON_BOARD" + }, + "modem_data_connection_type": { + "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.", + "value": 1, + "macro_name": "MODEM_ON_BOARD_UART" + }, + "usb_tx": { + "help": "Value PB_6", + "value": "PB_6" + }, + "usb_rx": { + "help": "Value PB_7", + "value": "PB_7" + }, + "stdio_uart": { + "help": "Value: UART_1", + "value": "UART_1", + "macro_name": "STDIO_UART" + } + }, + "overrides": { + "lse_available": 0 + }, + "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"], + "post_binary_hook": { + "function": "MTSCode.combine_bins_mtb_mts_dragonfly", + "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"] + }, + "release_versions": ["2", "5"], + "device_name": "STM32F411RE", + "bootloader_supported": true + }, "XDOT_L151CC": { "inherits": ["FAMILY_STM32"], "core": "Cortex-M3", diff --git a/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin b/tools/bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin new file mode 100644 index 0000000000000000000000000000000000000000..e5c640df1c3841c1d363c2e5273684b816ec9944 GIT binary patch literal 55608 zcmb@u33yaR)<0Z#=`~wJ0)$Qoo$df3&C(D+7H4ca$t4RIHWl|~appFQ#${&EamEgd zB8r9tFeIR890x%p3B(aKCL=DmPB+WEfxr-Tq#@DQ+ga$F?xg$s)$N2qU%&5rpXdLF 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z@hC=({}*U+jq@giI7X{({EgQy-$=&@ma)&)EufFM{vX%a>z7!2JuTGhZdiy7Ke+3k zuG80-;i#^8d(!$KGd(w?jBox8 zucCa6ENx%~S|ve`gN{YCyx{!6CssDpKx;}XWo}tjC4>YhlFQdRu@q6AJZ<`nnYZ3{d*L1S zaz{nw%4`4USc`1M!c7y!UR_Jf<}O&mN)|6+b4u}5hHC+?B3#9|=HR-Q{ueJ{^XM6V z=i?V=B%+^O`o#WR``xU+{-YfFM4!)*Kio||kpx!xqqxb3-Wy`m<^Q+8Md;b*95a{- z%=rc;Ro%lXSFS1+=CW%;7a4b?n~t+9x6=6)TyqKpd%?=WJ7UQmV)+HkY-SBhLDZwr z;(oG-DIQJcGIYb_XS7cK=h1Lj=24<)HcbjYCa<^je|#_7j(s_KO=KK+H;&0X2~*%+ z!DRl2Ddl^4T}FT?dan8l)BYS66%lXmNdMzMU&Br+{{R2Q~DX&(S@*$5uB Rb1T#SY#Y;V#d9j}{{lgj;28h_ literal 0 HcmV?d00001 diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index fc4b221a28..020fe5ca19 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -458,6 +458,11 @@ class MTSCode(object): """A hoof for the MTS Dragonfly""" MTSCode._combine_bins_helper("MTS_DRAGONFLY_F411RE", binf) + @staticmethod + def combine_bins_mtb_mts_dragonfly(t_self, resources, elf, binf): + """A hook for the MTB MTS Dragonfly""" + MTSCode._combine_bins_helper("MTB_MTS_DRAGONFLY", binf) + class MCU_NRF51Code(object): """NRF51 Hooks""" @staticmethod From 09bb1c49194737a696bb364bb89b8e927fed203d Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Fri, 5 Jan 2018 16:00:35 -0600 Subject: [PATCH 048/133] Kinetis USB improvements and fixes Make the following improvements and fixes: 1. Update the Kinetis USB driver so that endpointReadResult only reads the result of the last read and does not trigger a new read. Instead move the code to trigger new reads into endpointRead. 2. Fix the race condition in controlIn caused by a call to EP0read() followed immediately by EP0readStage(). This is done by setting up to read the next setup packet (ignoring the status stage) in endpointReadResult rather than in EP0readStage. This makes the function EP0readStage unnecissary. 3. Remove the Kinetis workaround in controlOut in USBDevice.cpp since point 2 fixes this bug. For more info on this see the PR which added this workaround - https://github.com/ARMmbed/mbed-os/pull/414 --- .../USBDevice/USBDevice/USBDevice.cpp | 19 --- .../targets/TARGET_Freescale/USBHAL_KL25Z.cpp | 108 ++++++++++++++---- 2 files changed, 85 insertions(+), 42 deletions(-) diff --git a/features/unsupported/USBDevice/USBDevice/USBDevice.cpp b/features/unsupported/USBDevice/USBDevice/USBDevice.cpp index dc3efc96f4..7ec03f2579 100644 --- a/features/unsupported/USBDevice/USBDevice/USBDevice.cpp +++ b/features/unsupported/USBDevice/USBDevice/USBDevice.cpp @@ -187,27 +187,8 @@ bool USBDevice::controlOut(void) /* Check we should be transferring data OUT */ if (transfer.direction != HOST_TO_DEVICE) { -#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) - /* - * We seem to have a pending device-to-host transfer. The host must have - * sent a new control request without waiting for us to finish processing - * the previous one. This appears to happen when we're connected to certain - * USB 3.0 host chip set. Do a zeor-length send to tell the host we're not - * ready for the new request - that'll make it resend - and then just - * pretend we were successful here so that the pending transfer can finish. - */ - uint8_t buf[1] = { 0 }; - EP0write(buf, 0); - - /* execute our pending ttransfer */ - controlIn(); - - /* indicate success */ - return true; - #else /* for other platforms, count on the HAL to handle this case */ return false; - #endif } /* Read from endpoint */ diff --git a/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp b/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp index b95437d219..71bf529900 100644 --- a/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp @@ -22,6 +22,7 @@ #include "fsl_common.h" #endif #include "USBHAL.h" +#include "mbed_critical.h" USBHAL * USBHAL::instance; @@ -64,6 +65,13 @@ typedef struct BDT { uint32_t address; // Addr } BDT; +typedef enum { + CTRL_XFER_READY, + CTRL_XFER_IN, + CTRL_XFER_NONE, + CTRL_XFER_OUT +} ctrl_xfer_t; + // there are: // * 4 bidirectionnal endpt -> 8 physical endpt // * as there are ODD and EVEN buffer -> 8*2 bdt @@ -73,6 +81,7 @@ uint8_t * endpoint_buffer[NUMBER_OF_PHYSICAL_ENDPOINTS * 2]; static uint8_t set_addr = 0; static uint8_t addr = 0; +static ctrl_xfer_t ctrl_xfer = CTRL_XFER_READY; static uint32_t Data1 = 0x55555555; @@ -223,11 +232,16 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran. bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket; bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf; - bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK; + bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_DTS_MASK; bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0; + if (log_endpoint == 0) { + // Prepare for setup packet + bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info |= BD_OWN_MASK; + } } - Data1 |= (1 << endpoint); + // First transfer will be a DATA0 packet + Data1 &= ~(1 << endpoint); return true; } @@ -239,13 +253,35 @@ void USBHAL::EP0setup(uint8_t *buffer) { } void USBHAL::EP0readStage(void) { - Data1 &= ~1UL; // set DATA0 - bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK); + // Not needed } void USBHAL::EP0read(void) { - uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0); - bdt[idx].byte_count = MAX_PACKET_SIZE_EP0; + if (ctrl_xfer == CTRL_XFER_READY) { + // Transfer is done so ignore call + return; + } + if (ctrl_xfer == CTRL_XFER_IN) { + ctrl_xfer = CTRL_XFER_READY; + // Control transfer with a data IN stage. + // The next packet received will be the status packet - an OUT packet using DATA1 + // + // PROBLEM: + // If a Setup packet is received after status packet of + // a Control In transfer has been received in the RX buffer + // but before the processor has had a chance the prepare + // this buffer for the Setup packet, the Setup packet + // will be dropped. + // + // WORKAROUND: + // Set data toggle to DATA0 so if the status stage of a + // Control In transfer arrives it will be ACKed by hardware + // but will be discarded without filling the RX buffer. + // This allows a subsequent SETUP packet to be stored + // without any processor intervention. + Data1 &= ~1UL; // set DATA0 + } + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); } uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { @@ -255,6 +291,15 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { } void USBHAL::EP0write(uint8_t *buffer, uint32_t size) { + if (ctrl_xfer == CTRL_XFER_READY) { + // Transfer is done so ignore call + return; + } + if ((ctrl_xfer == CTRL_XFER_NONE) || (ctrl_xfer == CTRL_XFER_OUT)) { + // Prepare for next setup packet + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); + ctrl_xfer = CTRL_XFER_READY; + } endpointWrite(EP0IN, buffer, size); } @@ -262,13 +307,34 @@ void USBHAL::EP0getWriteResult(void) { } void USBHAL::EP0stall(void) { + if (ctrl_xfer == CTRL_XFER_READY) { + // Transfer is done so ignore call + return; + } + ctrl_xfer = CTRL_XFER_READY; + core_util_critical_section_enter(); stallEndpoint(EP0OUT); + // Prepare for next setup packet + // Note - time between stalling and setting up the endpoint + // must be kept to a minimum to prevent a dropped SETUP + // packet. + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); + core_util_critical_section_exit(); } EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { - endpoint = PHY_TO_LOG(endpoint); - uint32_t idx = EP_BDT_IDX(endpoint, RX, 0); + uint8_t log_endpoint = PHY_TO_LOG(endpoint); + + uint32_t idx = EP_BDT_IDX(log_endpoint, RX, 0); bdt[idx].byte_count = maximumSize; + if ((Data1 >> endpoint) & 1) { + bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK; + } + else { + bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK; + } + + Data1 ^= (1 << endpoint); return EP_PENDING; } @@ -307,18 +373,14 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_ buffer[n] = ep_buf[n]; } - if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) { - if (setup && (buffer[6] == 0)) // if no setup data stage, - Data1 &= ~1UL; // set DATA0 - else - Data1 ^= (1 << endpoint); - } - - if (((Data1 >> endpoint) & 1)) { - bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK; - } - else { - bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK; + if (setup) { + // Record the setup type + if (buffer[6] == 0) { + ctrl_xfer = CTRL_XFER_NONE; + } else { + uint8_t in_xfer = (buffer[0] >> 7) & 1; + ctrl_xfer = in_xfer ? CTRL_XFER_IN : CTRL_XFER_OUT; + } } USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; @@ -351,9 +413,9 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) } if ((Data1 >> endpoint) & 1) { - bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK; - } else { bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK; + } else { + bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK; } Data1 ^= (1 << endpoint); @@ -450,7 +512,7 @@ void USBHAL::usbisr(void) { // setup packet if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) { - Data1 &= ~0x02; + Data1 |= 0x02 | 0x01; // set DATA1 for TX and RX bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK; bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK; From 183526bc0486c9759c6c811a8ab963ffbbe17263 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Mon, 15 Jan 2018 21:09:31 -0600 Subject: [PATCH 049/133] Fix LPC17XX and LPC40XX USB race condition If a SETUP packet arrives shortly after an IN then the packets will be processed in the wrong order - SETUP first then IN. This causes the subsequent control transfer to fail. Fix this problem by processing IN packets before processing SETUP packets. --- .../targets/TARGET_NXP/USBHAL_LPC17.cpp | 25 ++++++++++++++----- .../targets/TARGET_NXP/USBHAL_LPC40.cpp | 25 ++++++++++++++----- 2 files changed, 38 insertions(+), 12 deletions(-) diff --git a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp index 61dc87e0aa..5d516f5304 100644 --- a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp @@ -590,6 +590,25 @@ void USBHAL::usbisr(void) { if (LPC_USB->USBDevIntSt & EP_SLOW) { // (Slow) Endpoint Interrupt + // Process IN packets before SETUP packets + // Note - order of OUT and SETUP does not matter as OUT packets + // are clobbered by SETUP packets and thus ignored. + // + // A SETUP packet can arrive at any time where as an IN packet is + // only sent after calling EP0write and an OUT packet after EP0read. + // The functions EP0write and EP0read are called only in response to + // a setup packet or IN/OUT packets sent in response to that + // setup packet. Therefore, if an IN or OUT packet is pending + // at the same time as a SETUP packet, the IN or OUT packet belongs + // to the previous control transfer and should either be processed + // before the SETUP packet (in the case of IN) or dropped (in the + // case of OUT as SETUP clobbers the OUT data). + if (LPC_USB->USBEpIntSt & EP(EP0IN)) { + selectEndpointClearInterrupt(EP0IN); + LPC_USB->USBDevIntClr = EP_SLOW; + EP0in(); + } + // Process each endpoint interrupt if (LPC_USB->USBEpIntSt & EP(EP0OUT)) { if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) { @@ -601,12 +620,6 @@ void USBHAL::usbisr(void) { LPC_USB->USBDevIntClr = EP_SLOW; } - if (LPC_USB->USBEpIntSt & EP(EP0IN)) { - selectEndpointClearInterrupt(EP0IN); - LPC_USB->USBDevIntClr = EP_SLOW; - EP0in(); - } - for (uint8_t num = 2; num < 16*2; num++) { if (LPC_USB->USBEpIntSt & EP(num)) { selectEndpointClearInterrupt(num); diff --git a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp index a5d7b44401..7147366239 100644 --- a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp @@ -595,6 +595,25 @@ void USBHAL::usbisr(void) { if (LPC_USB->DevIntSt & EP_SLOW) { // (Slow) Endpoint Interrupt + // Process IN packets before SETUP packets + // Note - order of OUT and SETUP does not matter as OUT packets + // are clobbered by SETUP packets and thus ignored. + // + // A SETUP packet can arrive at any time where as an IN packet is + // only sent after calling EP0write and an OUT packet after EP0read. + // The functions EP0write and EP0read are called only in response to + // a setup packet or IN/OUT packets sent in response to that + // setup packet. Therefore, if an IN or OUT packet is pending + // at the same time as a SETUP packet, the IN or OUT packet belongs + // to the previous control transfer and should either be processed + // before the SETUP packet (in the case of IN) or dropped (in the + // case of OUT as SETUP clobbers the OUT data). + if (LPC_USB->EpIntSt & EP(EP0IN)) { + selectEndpointClearInterrupt(EP0IN); + LPC_USB->DevIntClr = EP_SLOW; + EP0in(); + } + // Process each endpoint interrupt if (LPC_USB->EpIntSt & EP(EP0OUT)) { if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) { @@ -606,12 +625,6 @@ void USBHAL::usbisr(void) { LPC_USB->DevIntClr = EP_SLOW; } - if (LPC_USB->EpIntSt & EP(EP0IN)) { - selectEndpointClearInterrupt(EP0IN); - LPC_USB->DevIntClr = EP_SLOW; - EP0in(); - } - for (uint8_t num = 2; num < 16*2; num++) { if (LPC_USB->EpIntSt & EP(num)) { selectEndpointClearInterrupt(num); From 379daa653d0b4555ee04782e359ed3eba78d9407 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Mon, 15 Jan 2018 21:18:32 -0600 Subject: [PATCH 050/133] Fix LPC17XX and LPC40XX USB data throttling Only clear the USB read buffer when endpointRead is called. This allows data to be read with endpointReadResult without also allowing USB to transfer more data. Instead additional data is transferred explicitly with a call to endpointRead. --- .../USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp | 12 ++++++------ .../USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp index 5d516f5304..6c047e8363 100644 --- a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC17.cpp @@ -275,11 +275,6 @@ uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) { LPC_USB->USBCtrl = 0; - if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { - SIEselectEndpoint(endpoint); - SIEclearBuffer(); - } - return size; } @@ -431,7 +426,7 @@ void USBHAL::EP0setup(uint8_t *buffer) { } void USBHAL::EP0read(void) { - // Not required + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); } void USBHAL::EP0readStage(void) { @@ -456,6 +451,11 @@ void USBHAL::EP0stall(void) { } EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { + // Don't clear isochronous endpoints + if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { + SIEselectEndpoint(endpoint); + SIEclearBuffer(); + } return EP_PENDING; } diff --git a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp index 7147366239..248dd63b19 100644 --- a/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_NXP/USBHAL_LPC40.cpp @@ -276,11 +276,6 @@ uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) { LPC_USB->Ctrl = 0; - if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { - SIEselectEndpoint(endpoint); - SIEclearBuffer(); - } - return size; } @@ -436,7 +431,7 @@ void USBHAL::EP0setup(uint8_t *buffer) { } void USBHAL::EP0read(void) { - // Not required + endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0); } void USBHAL::EP0readStage(void) { @@ -461,6 +456,11 @@ void USBHAL::EP0stall(void) { } EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { + // Don't clear isochronous endpoints + if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) { + SIEselectEndpoint(endpoint); + SIEclearBuffer(); + } return EP_PENDING; } From 597633d4455627055d92e3b56a469ac32463c3bf Mon Sep 17 00:00:00 2001 From: Abdelhak Bougouffa Date: Sat, 2 Dec 2017 17:08:43 +0100 Subject: [PATCH 051/133] Replace the old deprecated callbacks --- features/unsupported/USBHost/USBHost/USBDeviceConnected.h | 4 ++-- features/unsupported/USBHost/USBHost/USBEndpoint.h | 4 ++-- features/unsupported/USBHost/USBHost/USBHost.cpp | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/features/unsupported/USBHost/USBHost/USBDeviceConnected.h b/features/unsupported/USBHost/USBHost/USBDeviceConnected.h index f74c4b6e4b..88dd6dbbbf 100644 --- a/features/unsupported/USBHost/USBHost/USBDeviceConnected.h +++ b/features/unsupported/USBHost/USBHost/USBDeviceConnected.h @@ -106,7 +106,7 @@ public: template inline void onDisconnect(uint8_t intf_nb, T* tptr, void (T::*mptr)(void)) { if ((mptr != NULL) && (tptr != NULL)) { - intf[intf_nb].detach.attach(tptr, mptr); + intf[intf_nb].detach = callback(tptr, mptr); } } @@ -118,7 +118,7 @@ public: */ inline void onDisconnect(uint8_t intf_nb, void (*fn)(void)) { if (fn != NULL) { - intf[intf_nb].detach.attach(fn); + intf[intf_nb].detach = fn; } } diff --git a/features/unsupported/USBHost/USBHost/USBEndpoint.h b/features/unsupported/USBHost/USBHost/USBEndpoint.h index 5b1287f421..d0d9fd4231 100644 --- a/features/unsupported/USBHost/USBHost/USBEndpoint.h +++ b/features/unsupported/USBHost/USBHost/USBEndpoint.h @@ -89,7 +89,7 @@ public: template inline void attach(T* tptr, void (T::*mptr)(void)) { if((mptr != NULL) && (tptr != NULL)) { - rx.attach(tptr, mptr); + rx = callback(tptr, mptr); } } @@ -100,7 +100,7 @@ public: */ inline void attach(void (*fptr)(void)) { if(fptr != NULL) { - rx.attach(fptr); + rx = fptr; } } diff --git a/features/unsupported/USBHost/USBHost/USBHost.cpp b/features/unsupported/USBHost/USBHost/USBHost.cpp index b9424f73f1..518d00d94f 100644 --- a/features/unsupported/USBHost/USBHost/USBHost.cpp +++ b/features/unsupported/USBHost/USBHost/USBHost.cpp @@ -312,7 +312,7 @@ USBHost::USBHost() : usbThread(osPriorityNormal, USB_THREAD_STACK) } #endif - usbThread.start(this, &USBHost::usb_process); + usbThread.start(callback(this, &USBHost::usb_process)); } USBHost::Lock::Lock(USBHost* pHost) : m_pHost(pHost) From 9c464a03380bb3ae0927211c1181407d6912ba67 Mon Sep 17 00:00:00 2001 From: Abdelhak Bougouffa Date: Sat, 2 Dec 2017 17:09:46 +0100 Subject: [PATCH 052/133] Add checking for MAX_HUB_NB in a part of code that depend on MAX_HUB_NB --- features/unsupported/USBHost/USBHost/USBHost.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/features/unsupported/USBHost/USBHost/USBHost.cpp b/features/unsupported/USBHost/USBHost/USBHost.cpp index 518d00d94f..704e28001c 100644 --- a/features/unsupported/USBHost/USBHost/USBHost.cpp +++ b/features/unsupported/USBHost/USBHost/USBHost.cpp @@ -88,11 +88,14 @@ void USBHost::usb_process() /* check that hub is connected to root port */ if (usb_msg->hub_parent) { /* a hub device must be present */ +#if MAX_HUB_NB + for (k = 0; k < MAX_HUB_NB; k++) { if ((&hubs[k] == usb_msg->hub_parent) && (hub_in_use[k])) { hub_unplugged=false; } } +#endif } else { hub_unplugged = false; } From 88fbf6b3412667b4d4c1414ea8388fb237c2f621 Mon Sep 17 00:00:00 2001 From: iotvietmember Date: Tue, 17 Oct 2017 12:07:18 +0700 Subject: [PATCH 053/133] Add detect_code=0xC006 to the VBLUNO51 boards configuration. Add detect_code=0xC006 to the VBLUNO51 boards configuration. Disbale UART Hard flow control feature. Signed-off-by: iotvietmember --- targets/targets.json | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index a5f81fec96..adf96948c5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3600,23 +3600,31 @@ "VBLUNO51_LEGACY": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "extra_labels_add": ["VBLUNO51"] }, "VBLUNO51_BOOT": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K_BOOT"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "extra_labels_add": ["VBLUNO51"], "macros_add": ["TARGET_VBLUNO51"] }, "VBLUNO51_OTA": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K_OTA"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "extra_labels_add": ["VBLUNO51"], "macros_add": ["TARGET_VBLUNO51"] }, "VBLUNO51": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF51_32K_UNIFIED"], + "detect_code": ["C006"], + "overrides": {"uart_hwfc": 0}, "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2"], "device_name": "nRF51822_xxAC" From 0ffd251cd2e3bef272bbc86237426ad3e5f247ad Mon Sep 17 00:00:00 2001 From: "c.mandl" Date: Mon, 20 Nov 2017 10:02:08 +0100 Subject: [PATCH 054/133] Added Netbeans Exporter --- tools/export/__init__.py | 7 +- tools/export/nb/__init__.py | 190 ++++++++++++++++++++++++++ tools/export/nb/configurations.tmpl | 205 ++++++++++++++++++++++++++++ tools/export/nb/mbedignore.tmpl | 2 + tools/export/nb/project.tmpl | 28 ++++ 5 files changed, 431 insertions(+), 1 deletion(-) create mode 100644 tools/export/nb/__init__.py create mode 100644 tools/export/nb/configurations.tmpl create mode 100644 tools/export/nb/mbedignore.tmpl create mode 100644 tools/export/nb/project.tmpl diff --git a/tools/export/__init__.py b/tools/export/__init__.py index 501be59d15..8ae710fd27 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -33,6 +33,7 @@ from tools.export import embitz, coide, kds, simplicity, atmelstudio, mcuxpresso from tools.export import sw4stm32, e2studio, zip, cmsis, uvision, cdt, vscode from tools.export import gnuarmeclipse from tools.export import qtcreator +from tools.export import nb from tools.targets import TARGET_NAMES EXPORTERS = { @@ -57,11 +58,15 @@ EXPORTERS = { 'eclipse_iar' : cdt.EclipseIAR, 'eclipse_armc5' : cdt.EclipseArmc5, 'gnuarmeclipse': gnuarmeclipse.GNUARMEclipse, + #'netbeans': nb.Netbeans, 'mcuxpresso': mcuxpresso.MCUXpresso, 'qtcreator': qtcreator.QtCreator, 'vscode_gcc_arm' : vscode.VSCodeGcc, 'vscode_iar' : vscode.VSCodeIAR, - 'vscode_armc5' : vscode.VSCodeArmc5 + 'vscode_armc5' : vscode.VSCodeArmc5, + 'netbeans_gcc_arm' : nb.NetbeansGcc, + 'netbeans_iar' : nb.NetbeansIAR, + 'netbeans_armc5' : nb.NetbeansArmc5 } ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN = """ diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py new file mode 100644 index 0000000000..cdfee42fbe --- /dev/null +++ b/tools/export/nb/__init__.py @@ -0,0 +1,190 @@ +import re +import os +import copy + +from os.path import relpath, join, exists +from os import makedirs + +from tools.export.makefile import Makefile, GccArm, Armc5, IAR + + +class Netbeans(Makefile): + """Generic Netbeans project. Intended to be subclassed by classes that + specify a type of Makefile. + """ + + @property + def flags(self): + """Returns a dictionary of toolchain flags. + Keys of the dictionary are: + cxx_flags - c++ flags + c_flags - c flags + ld_flags - linker flags + asm_flags - assembler flags + common_flags - common options + + The difference from the parent function is that it does not + add macro definitions, since they are passed separately. + """ + + config_header = self.toolchain.get_config_header() + flags = {key + "_flags": copy.deepcopy(value) for key, value + in self.toolchain.flags.iteritems()} + if config_header: + config_header = relpath(config_header, + self.resources.file_basepath[config_header]) + flags['c_flags'] += self.toolchain.get_config_option(config_header) + flags['cxx_flags'] += self.toolchain.get_config_option( + config_header) + return flags + + def generate(self): + """Generate Makefile, configurations.xml & project.xml Netbeans project file + """ + super(Netbeans, self).generate() + + defines = [] # list of tuples ('D'/'U', [key, value]) (value is optional) + forced_includes = [] # list of strings + sources = [] # list of strings + headers = [] # list of strings + + next_is_include = False + for f in self.flags['c_flags'] + self.flags['cxx_flags']: + f = f.strip() + if next_is_include: + forced_includes.append(f) + next_is_include = False + continue + if f.startswith('-D'): + defines.append(('D', f[2:].split('=', 1))) + elif f.startswith('-U'): + defines.append(('U', [f[2:]])) + elif f == "-include": + next_is_include = True + + # Convert all Backslashes to Forward Slashes + self.resources.win_to_unix() + + for r_type in ['c_sources', 's_sources', 'cpp_sources']: + sources.extend(getattr(self.resources, r_type)) + + for r_type in ['headers']: + headers.extend(getattr(self.resources, r_type)) + + starting_dot = re.compile(r'(^[.]/|^[.]$)') + sources = [starting_dot.sub('', field) for field in sources] + headers = [starting_dot.sub('', field) for field in headers] + include_paths = [starting_dot.sub('', field) for field in self.resources.inc_dirs] + + headers.sort() + sources.sort() + + headers_output = create_netbeans_file_list(headers) + sources_output = create_netbeans_file_list(sources) + ctx = { + 'name': self.project_name, + 'elf_location': join('BUILD', self.project_name) + '.elf', + 'c_symbols': self.toolchain.get_symbols(), + 'asm_symbols': self.toolchain.get_symbols(True), + 'c_flags': self.flags['c_flags'], + 'cxx_flags': self.flags['cxx_flags'], + 'ld_flags': self.flags['ld_flags'], + 'asm_flags': self.flags['asm_flags'], + 'common_flags': self.flags['common_flags'], + 'target': self.target, + 'include_paths': include_paths, + 'sources': sources, + 'headers': headers, + 'headers_folder': headers_output, + 'sources_folder': sources_output, + 'load_exe': str(self.LOAD_EXE).lower() + } + + if not exists(join(self.export_dir, 'nbproject')): + makedirs(join(self.export_dir, 'nbproject')) + + self.gen_file('nb/configurations.tmpl', ctx, 'nbproject/configurations.xml') + self.gen_file('nb/project.tmpl', ctx, 'nbproject/project.xml') + self.gen_file('nb/mbedignore.tmpl', ctx, '.mbedignore') + + +def create_netbeans_file_list(file_list): + output = [] + prev_dir = '' + folder_count = 1 + for idx, item in enumerate(file_list): + cur_dir = os.path.dirname(item) + dir_temp = os.path.normpath(cur_dir) + prev_dir_temp = os.path.normpath(prev_dir) + dir_list = dir_temp.split(os.sep) + prev_dir_list = prev_dir_temp.split(os.sep) + dir_depth = len(dir_list) + + # print 'PREV_DIR: ' + str(prev_dir_list) + + # print 'CURR_DIR: ' + str(dir_list) + + # Current File is in Directory: Compare the given dir with previous Dir + if cur_dir and prev_dir != cur_dir: + # evaluate all matched items (from current and previous list) + matched = [] + for element in dir_list: + if element in prev_dir_list: + matched.append(element) + + # calculate difference between matched and length + diff = dir_depth - len(matched) + + # print 'MATCHED: ' + str(matched) + + # if previous dir was not root + if prev_dir != '': + # if the elements count is not equal we calculate the difference + if len(dir_list) != len(prev_dir_list): + dir_depth_prev = len(prev_dir_list) + delta = dir_depth_prev - len(matched) + + for i in range(dir_depth_prev - delta, dir_depth_prev): + output.append('') + + # if the elements count is equal, we subtract the matched length from the total length + else: + for i in range(len(matched), len(dir_list)): + output.append('') + + for i in range(dir_depth - diff, dir_depth): + output.append('') + folder_count += 1 + + # Current File is in root + else: + # Close Tag if we are in root and the previous dir wasn't + if cur_dir == '' and prev_dir != '': + for i in range(0, len(prev_dir_list)): + output.append('') + + # Save the Current Dir + prev_dir = cur_dir + output.append('' + str(item) + '') + # if last iteration close all open tags + if idx == len(file_list) - 1 and cur_dir != '': + for i in range(0, len(dir_list)): + output.append('') + + return output + + +class NetbeansGcc(Netbeans, GccArm): + LOAD_EXE = True + NAME = "Netbeans-GCC-ARM" + + +class NetbeansArmc5(Netbeans, Armc5): + LOAD_EXE = False + NAME = "Netbeans-Armc5" + + +class NetbeansIAR(Netbeans, IAR): + LOAD_EXE = True + NAME = "Netbeans-IAR" diff --git a/tools/export/nb/configurations.tmpl b/tools/export/nb/configurations.tmpl new file mode 100644 index 0000000000..93241d6934 --- /dev/null +++ b/tools/export/nb/configurations.tmpl @@ -0,0 +1,205 @@ + + + + + + + {% for header in headers_folder -%} + {{ header }} + {% endfor %} + + + + + {% for source in sources_folder -%} + {{ source }} + {% endfor %} + + + + + Makefile + + + Makefile + + + + default + true + false + + + + + {% for include in include_paths -%} + {{ include }} + {% endfor %} + + + {% for flag in c_flags -%} + {{ flag }} + {% endfor %} + + + {% for symbol in c_symbols -%} + {{ symbol }} + {% endfor %} + + + + + {% for include in include_paths -%} + {{ include }} + {% endfor %} + + + {% for flag in cxx_flags -%} + {{ flag }} + {% endfor %} + + + {% for symbol in c_symbols -%} + {{ symbol }} + {% endfor %} + + + + 5 + + + 5 + + {% for include in include_paths -%} + {{ include }} + {% endfor %} + + + {% for flag in asm_flags -%} + {{ flag }} + {% endfor %} + + + {% for symbol in asm_symbols -%} + {{ symbol }} + {% endfor %} + + + + + {% for flag in ld_flags -%} + {{ flag }} + {% endfor %} + + + + + {% for h in headers -%} + + + {% endfor %} + {% for s in sources -%} + + + {% endfor %} + + + + + + + default + true + false + + + {% for h in headers -%} + + + {% endfor %} + {% for s in sources -%} + + + {% endfor %} + + 5 + + {% for include in include_paths -%} + {{ include }} + {% endfor %} + + + {% for flag in c_flags -%} + {{ flag }} + {% endfor %} + + + {% for symbol in c_symbols -%} + {{ symbol }} + {% endfor %} + + + + 5 + + {% for include in include_paths -%} + {{ include }} + {% endfor %} + + + {% for flag in cxx_flags -%} + {{ flag }} + {% endfor %} + + + {% for symbol in c_symbols -%} + {{ symbol }} + {% endfor %} + + + + 5 + + + 5 + + {% for include in include_paths -%} + {{ include }} + {% endfor %} + + + {% for flag in asm_flags -%} + {{ flag }} + {% endfor %} + + + {% for symbol in asm_symbols -%} + {{ symbol }} + {% endfor %} + + + + + {% for flag in ld_flags -%} + {{ flag }} + {% endfor %} + + + + + + + + diff --git a/tools/export/nb/mbedignore.tmpl b/tools/export/nb/mbedignore.tmpl new file mode 100644 index 0000000000..805fc686b5 --- /dev/null +++ b/tools/export/nb/mbedignore.tmpl @@ -0,0 +1,2 @@ +nbproject/private/*.cpp +nbproject/private/*.c diff --git a/tools/export/nb/project.tmpl b/tools/export/nb/project.tmpl new file mode 100644 index 0000000000..c73b0eebbd --- /dev/null +++ b/tools/export/nb/project.tmpl @@ -0,0 +1,28 @@ + + + org.netbeans.modules.cnd.makeproject + + + {{name}} + + cpp + + UTF-8 + + + + + Debug + 1 + + + Release + 1 + + + + false + + + + From 979e54b031f11b7b9d01573ce6c72f21c9c1de98 Mon Sep 17 00:00:00 2001 From: "c.mandl" Date: Mon, 20 Nov 2017 10:05:06 +0100 Subject: [PATCH 055/133] Removed commented Line --- tools/export/__init__.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tools/export/__init__.py b/tools/export/__init__.py index 8ae710fd27..c70c762047 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -58,7 +58,6 @@ EXPORTERS = { 'eclipse_iar' : cdt.EclipseIAR, 'eclipse_armc5' : cdt.EclipseArmc5, 'gnuarmeclipse': gnuarmeclipse.GNUARMEclipse, - #'netbeans': nb.Netbeans, 'mcuxpresso': mcuxpresso.MCUXpresso, 'qtcreator': qtcreator.QtCreator, 'vscode_gcc_arm' : vscode.VSCodeGcc, From 103244da8ca9d883dea333fd58d6153d8e2b0538 Mon Sep 17 00:00:00 2001 From: "c.mandl" Date: Fri, 24 Nov 2017 09:45:46 +0100 Subject: [PATCH 056/133] Refactoring of Netbeans Exporter...still some more work to do, because linking still not works --- tools/export/__init__.py | 6 +- tools/export/nb/Makefile.tmpl | 128 ++++++++ tools/export/nb/__init__.py | 434 ++++++++++++++++++++-------- tools/export/nb/configurations.tmpl | 204 ++++++------- tools/export/nb/project.tmpl | 4 +- 5 files changed, 531 insertions(+), 245 deletions(-) create mode 100644 tools/export/nb/Makefile.tmpl diff --git a/tools/export/__init__.py b/tools/export/__init__.py index c70c762047..c15669618f 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -58,14 +58,12 @@ EXPORTERS = { 'eclipse_iar' : cdt.EclipseIAR, 'eclipse_armc5' : cdt.EclipseArmc5, 'gnuarmeclipse': gnuarmeclipse.GNUARMEclipse, + 'netbeans': nb.GNUARMNetbeans, 'mcuxpresso': mcuxpresso.MCUXpresso, 'qtcreator': qtcreator.QtCreator, 'vscode_gcc_arm' : vscode.VSCodeGcc, 'vscode_iar' : vscode.VSCodeIAR, - 'vscode_armc5' : vscode.VSCodeArmc5, - 'netbeans_gcc_arm' : nb.NetbeansGcc, - 'netbeans_iar' : nb.NetbeansIAR, - 'netbeans_armc5' : nb.NetbeansArmc5 + 'vscode_armc5' : vscode.VSCodeArmc5 } ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN = """ diff --git a/tools/export/nb/Makefile.tmpl b/tools/export/nb/Makefile.tmpl new file mode 100644 index 0000000000..05de621e85 --- /dev/null +++ b/tools/export/nb/Makefile.tmpl @@ -0,0 +1,128 @@ +# +# There exist several targets which are by default empty and which can be +# used for execution of your targets. These targets are usually executed +# before and after some main targets. They are: +# +# .build-pre: called before 'build' target +# .build-post: called after 'build' target +# .clean-pre: called before 'clean' target +# .clean-post: called after 'clean' target +# .clobber-pre: called before 'clobber' target +# .clobber-post: called after 'clobber' target +# .all-pre: called before 'all' target +# .all-post: called after 'all' target +# .help-pre: called before 'help' target +# .help-post: called after 'help' target +# +# Targets beginning with '.' are not intended to be called on their own. +# +# Main targets can be executed directly, and they are: +# +# build build a specific configuration +# clean remove built files from a configuration +# clobber remove all built files +# all build all configurations +# help print help mesage +# +# Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and +# .help-impl are implemented in nbproject/makefile-impl.mk. +# +# Available make variables: +# +# CND_BASEDIR base directory for relative paths +# CND_DISTDIR default top distribution directory (build artifacts) +# CND_BUILDDIR default top build directory (object files, ...) +# CONF name of current configuration +# CND_PLATFORM_${CONF} platform name (current configuration) +# CND_ARTIFACT_DIR_${CONF} directory of build artifact (current configuration) +# CND_ARTIFACT_NAME_${CONF} name of build artifact (current configuration) +# CND_ARTIFACT_PATH_${CONF} path to build artifact (current configuration) +# CND_PACKAGE_DIR_${CONF} directory of package (current configuration) +# CND_PACKAGE_NAME_${CONF} name of package (current configuration) +# CND_PACKAGE_PATH_${CONF} path to package (current configuration) +# +# NOCDDL + + +# Environment +MKDIR=mkdir +CP=cp +CCADMIN=CCadmin + + +# build +build: .build-post + +.build-pre: +# Add your pre 'build' code here... + +.build-post: .build-impl +# Add your post 'build' code here... + + +# clean +clean: .clean-post + +.clean-pre: +# Add your pre 'clean' code here... + +.clean-post: .clean-impl +# Add your post 'clean' code here... + + +# clobber +clobber: .clobber-post + +.clobber-pre: +# Add your pre 'clobber' code here... + +.clobber-post: .clobber-impl +# Add your post 'clobber' code here... + + +# all +all: .all-post + +.all-pre: +# Add your pre 'all' code here... + +.all-post: .all-impl +# Add your post 'all' code here... + + +# build tests +build-tests: .build-tests-post + +.build-tests-pre: +# Add your pre 'build-tests' code here... + +.build-tests-post: .build-tests-impl +# Add your post 'build-tests' code here... + + +# run tests +test: .test-post + +.test-pre: build-tests +# Add your pre 'test' code here... + +.test-post: .test-impl +# Add your post 'test' code here... + + +# help +help: .help-post + +.help-pre: +# Add your pre 'help' code here... + +.help-post: .help-impl +# Add your post 'help' code here... + + + +# include project implementation makefile +include nbproject/Makefile-impl.mk + +# include project make variables +include nbproject/Makefile-variables.mk diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index cdfee42fbe..2a3357d986 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -1,20 +1,34 @@ -import re import os import copy -from os.path import relpath, join, exists +from os.path import relpath, join, exists, dirname, basename from os import makedirs +from json import load -from tools.export.makefile import Makefile, GccArm, Armc5, IAR +from tools.export.exporters import Exporter, apply_supported_whitelist +from tools.targets import TARGET_MAP +from tools.utils import NotSupportedException +from tools.build_api import prepare_toolchain + +POST_BINARY_WHITELIST = set([ + "TEENSY3_1Code.binary_hook", + "MCU_NRF51Code.binary_hook", + "LPCTargetCode.lpc_patch", + "LPC4088Code.binary_hook" +]) -class Netbeans(Makefile): - """Generic Netbeans project. Intended to be subclassed by classes that - specify a type of Makefile. - """ +class GNUARMNetbeans(Exporter): + NAME = 'GNU ARM Netbeans' + TOOLCHAIN = 'GCC_ARM' - @property - def flags(self): + @classmethod + def is_target_supported(cls, target_name): + target = TARGET_MAP[target_name] + return apply_supported_whitelist( + cls.TOOLCHAIN, POST_BINARY_WHITELIST, target) + + def toolchain_flags(self, toolchain): """Returns a dictionary of toolchain flags. Keys of the dictionary are: cxx_flags - c++ flags @@ -23,168 +37,352 @@ class Netbeans(Makefile): asm_flags - assembler flags common_flags - common options - The difference from the parent function is that it does not - add macro definitions, since they are passed separately. + The difference from the above is that it takes a parameter. """ + # Note: use the config options from the currently selected toolchain. config_header = self.toolchain.get_config_header() + flags = {key + "_flags": copy.deepcopy(value) for key, value - in self.toolchain.flags.iteritems()} + in toolchain.flags.iteritems()} if config_header: config_header = relpath(config_header, self.resources.file_basepath[config_header]) - flags['c_flags'] += self.toolchain.get_config_option(config_header) - flags['cxx_flags'] += self.toolchain.get_config_option( - config_header) + header_options = self.toolchain.get_config_option(config_header) + flags['c_flags'] += header_options + flags['cxx_flags'] += header_options return flags - def generate(self): - """Generate Makefile, configurations.xml & project.xml Netbeans project file - """ - super(Netbeans, self).generate() + @staticmethod + def get_defines_and_remove_from_flags(flags_in, str_key): + defines = [] + flags_temp = copy.deepcopy(flags_in) + for f in flags_temp[str_key]: + f = f.strip() + if f.startswith('-D'): + defines.append(f[2:]) + flags_in[str_key].remove(f) - defines = [] # list of tuples ('D'/'U', [key, value]) (value is optional) - forced_includes = [] # list of strings - sources = [] # list of strings - headers = [] # list of strings + return defines + @staticmethod + def get_includes_and_remove_from_flags(flags_in, str_key): + includes = [] + flags_temp = copy.deepcopy(flags_in) next_is_include = False - for f in self.flags['c_flags'] + self.flags['cxx_flags']: + for f in flags_temp[str_key]: f = f.strip() if next_is_include: - forced_includes.append(f) + includes.append(f) + flags_in[str_key].remove(f) next_is_include = False continue - if f.startswith('-D'): - defines.append(('D', f[2:].split('=', 1))) - elif f.startswith('-U'): - defines.append(('U', [f[2:]])) - elif f == "-include": + if f == "-include": + flags_in[str_key].remove(f) next_is_include = True + return includes + + @staticmethod + def get_c_std_and_remove_from_flag(flags_in, str_key): + comp_std = '' + c_std = { + 'c90': 'c90', 'c89': 'c90', 'gnu90': 'gnu90', 'gnu89': 'gnu90', + 'c99': 'c99', 'c9x': 'c99', 'gnu99': 'gnu99', 'gnu9x': 'gnu98', + 'c11': 'c11', 'c1x': 'c11', 'gnu11': 'gnu11', 'gnu1x': 'gnu11' + } + cpp_std = { + 'c++98': 'cpp98', 'c++03': 'cpp98', + 'gnu++98': 'gnucpp98', 'gnu++03': 'gnucpp98', + 'c++0x': 'cpp0x', 'gnu++0x': 'gnucpp0x', + 'c++11': 'cpp11', 'gnu++11': 'gnucpp11', + 'c++1y': 'cpp1y', 'gnu++1y': 'gnucpp1y', + 'c++14': 'cpp14', 'gnu++14': 'gnucpp14', + 'c++1z': 'cpp1z', 'gnu++1z': 'gnucpp1z', + } + + flags_temp = copy.deepcopy(flags_in) + for f in flags_temp[str_key]: + f = f.strip() + if f.startswith('-std='): + comp_std = f[len('-std='):] + flags_in[str_key].remove(f) + elif f.startswith('-'): + std = f[len('-'):] + if std in c_std or std in cpp_std: + comp_std = std + flags_in[str_key].remove(f) + return comp_std + + def validate_resources(self): + if not self.resources.linker_script: + raise NotSupportedException("No linker script found.") + + def create_jinja_ctx(self): + + self.validate_resources() # Convert all Backslashes to Forward Slashes self.resources.win_to_unix() + print 'Include folders: {0}'.format(len(self.resources.inc_dirs)) + + print 'Symbols: {0}'.format(len(self.toolchain.get_symbols())) + + self.ld_script = self.filter_dot( + self.resources.linker_script) + print 'Linker script: {0}'.format(self.ld_script) + + # Read in all profiles, we'll extract compiler options. + profiles = self.get_all_profiles() + + profile_ids = [s.lower() for s in profiles] + profile_ids.sort() + + self.options = {} + for prof_id in profile_ids: + # There are 4 categories of options, a category common too + # all tools and a specific category for each of the tools. + opts = {} + opts['defines'] = {} + opts['common'] = {} + opts['as'] = {} + opts['c'] = {} + opts['cpp'] = {} + opts['ld'] = {} + + opts['id'] = prof_id + opts['name'] = opts['id'].capitalize() + + print + print 'Build configuration: {0}'.format(opts['name']) + + profile = profiles[prof_id] + + # A small hack, do not bother with src_path again, + # pass an empty string to avoid crashing. + src_paths = [''] + target_name = self.toolchain.target.name + + toolchain = prepare_toolchain( + src_paths, "", target_name, self.TOOLCHAIN, build_profile=[profile]) + + flags = self.toolchain_flags(toolchain) + + print 'Common flags:', ' '.join(flags['common_flags']) + print 'C++ flags:', ' '.join(flags['cxx_flags']) + print 'C flags:', ' '.join(flags['c_flags']) + print 'ASM flags:', ' '.join(flags['asm_flags']) + print 'Linker flags:', ' '.join(flags['ld_flags']) + + opts['defines'] = self.get_defines_and_remove_from_flags(flags, 'common_flags') + opts['forced_includes'] = self.get_includes_and_remove_from_flags(flags, 'common_flags') + opts['common'] = flags['common_flags'] + opts['as'] = flags['asm_flags'] + opts['c'] = flags['c_flags'] + opts['cpp'] = flags['cxx_flags'] + opts['ld'] = flags['ld_flags'] + + self.options[prof_id] = opts + + sources = [] # list of strings + + forced_includes = self.get_includes_and_remove_from_flags(flags, 'c_flags') + forced_includes += self.get_includes_and_remove_from_flags(flags, 'cxx_flags') + + # Remove Duplicates + forced_includes = list(set(forced_includes)) + + c_std = self.get_c_std_and_remove_from_flag(flags, 'c_flags') + cpp_std = self.get_c_std_and_remove_from_flag(flags, 'cxx_flags') + + # Make one list of all resources for r_type in ['c_sources', 's_sources', 'cpp_sources']: sources.extend(getattr(self.resources, r_type)) - for r_type in ['headers']: - headers.extend(getattr(self.resources, r_type)) + # Remove all leading './' + c_sources = [self.filter_dot(field) for field in getattr(self.resources, 'c_sources')] + cpp_sources = [self.filter_dot(field) for field in getattr(self.resources, 'cpp_sources')] + s_sources = [self.filter_dot(field) for field in getattr(self.resources, 's_sources')] + headers = [self.filter_dot(field) for field in getattr(self.resources, 'headers')] + sources = [self.filter_dot(field) for field in sources] + include_paths = [self.filter_dot(field) for field in self.resources.inc_dirs] - starting_dot = re.compile(r'(^[.]/|^[.]$)') - sources = [starting_dot.sub('', field) for field in sources] - headers = [starting_dot.sub('', field) for field in headers] - include_paths = [starting_dot.sub('', field) for field in self.resources.inc_dirs] + if 'nbproject' in include_paths: + include_paths.remove('nbproject') - headers.sort() - sources.sort() - - headers_output = create_netbeans_file_list(headers) - sources_output = create_netbeans_file_list(sources) - ctx = { + jinja_ctx = { 'name': self.project_name, 'elf_location': join('BUILD', self.project_name) + '.elf', 'c_symbols': self.toolchain.get_symbols(), 'asm_symbols': self.toolchain.get_symbols(True), - 'c_flags': self.flags['c_flags'], - 'cxx_flags': self.flags['cxx_flags'], + 'c_flags': flags['c_flags'], + 'cxx_flags': flags['cxx_flags'], 'ld_flags': self.flags['ld_flags'], 'asm_flags': self.flags['asm_flags'], 'common_flags': self.flags['common_flags'], 'target': self.target, 'include_paths': include_paths, - 'sources': sources, + 'forced_includes': forced_includes, + 'c_sources': c_sources, + 'cpp_sources': cpp_sources, + 's_sources': s_sources, 'headers': headers, - 'headers_folder': headers_output, - 'sources_folder': sources_output, - 'load_exe': str(self.LOAD_EXE).lower() + 'headers_folder': self.get_netbeans_file_list(sorted(headers)), + 'sources_folder': self.get_netbeans_file_list(sorted(sources)), + 'options': self.options, + 'c_std': self.get_netbeans_c_std(c_std), + 'cpp_std': self.get_netbeans_cpp_std(cpp_std), + 'linker_script': self.ld_script, } + return jinja_ctx + + def generate(self): + """Generate Makefile, configurations.xml & project.xml Netbeans project file + """ + # super(Netbeans, self).generate() + + jinja_ctx = self.create_jinja_ctx() + + print + print 'Create a GNU ARM Netbeans C++ managed project' + print 'Project name: {0}'.format(self.project_name) + print 'Target: {0}'.format(self.toolchain.target.name) + print 'Toolchain: {0}'.format(self.TOOLCHAIN) if not exists(join(self.export_dir, 'nbproject')): makedirs(join(self.export_dir, 'nbproject')) - self.gen_file('nb/configurations.tmpl', ctx, 'nbproject/configurations.xml') - self.gen_file('nb/project.tmpl', ctx, 'nbproject/project.xml') - self.gen_file('nb/mbedignore.tmpl', ctx, '.mbedignore') + self.gen_file('nb/configurations.tmpl', jinja_ctx, 'nbproject/configurations.xml') + self.gen_file('nb/project.tmpl', jinja_ctx, 'nbproject/project.xml') + self.gen_file('nb/mbedignore.tmpl', jinja_ctx, '.mbedignore') + self.gen_file('nb/Makefile.tmpl', jinja_ctx, 'Makefile') + print + print 'Done. Import the \'{0}\' project in Netbeans.'.format(self.project_name) -def create_netbeans_file_list(file_list): - output = [] - prev_dir = '' - folder_count = 1 - for idx, item in enumerate(file_list): - cur_dir = os.path.dirname(item) - dir_temp = os.path.normpath(cur_dir) - prev_dir_temp = os.path.normpath(prev_dir) - dir_list = dir_temp.split(os.sep) - prev_dir_list = prev_dir_temp.split(os.sep) - dir_depth = len(dir_list) + # ------------------------------------------------------------------------- - # print 'PREV_DIR: ' + str(prev_dir_list) + @staticmethod + def filter_dot(str_in): + """ + Remove the './' prefix, if present. + This function assumes that resources.win_to_unix() + replaced all windows backslashes with slashes. + """ + if str_in is None: + return None + if str_in[:2] == './': + return str_in[2:] + return str_in - # print 'CURR_DIR: ' + str(dir_list) + # ------------------------------------------------------------------------- - # Current File is in Directory: Compare the given dir with previous Dir - if cur_dir and prev_dir != cur_dir: - # evaluate all matched items (from current and previous list) - matched = [] - for element in dir_list: - if element in prev_dir_list: - matched.append(element) + @staticmethod + def get_all_profiles(): + tools_path = dirname(dirname(dirname(__file__))) + file_names = [join(tools_path, "profiles", fn) for fn in os.listdir( + join(tools_path, "profiles")) if fn.endswith(".json")] - # calculate difference between matched and length - diff = dir_depth - len(matched) + # print file_names - # print 'MATCHED: ' + str(matched) + # profile_names = [basename(fn).replace(".json", "") + # for fn in file_names] + # print profile_names - # if previous dir was not root - if prev_dir != '': - # if the elements count is not equal we calculate the difference - if len(dir_list) != len(prev_dir_list): - dir_depth_prev = len(prev_dir_list) - delta = dir_depth_prev - len(matched) + profiles = {} - for i in range(dir_depth_prev - delta, dir_depth_prev): + for fn in file_names: + content = load(open(fn)) + profile_name = basename(fn).replace(".json", "") + profiles[profile_name] = content + + return profiles + + @staticmethod + def get_netbeans_file_list(file_list): + output = [] + prev_dir = '' + folder_count = 1 + for idx, item in enumerate(file_list): + cur_dir = os.path.dirname(item) + dir_temp = os.path.normpath(cur_dir) + prev_dir_temp = os.path.normpath(prev_dir) + dir_list = dir_temp.split(os.sep) + prev_dir_list = prev_dir_temp.split(os.sep) + dir_depth = len(dir_list) + + # print 'PREV_DIR: ' + str(prev_dir_list) + + # print 'CURR_DIR: ' + str(dir_list) + + # Current File is in Directory: Compare the given dir with previous Dir + if cur_dir and prev_dir != cur_dir: + # evaluate all matched items (from current and previous list) + matched = [] + for element in dir_list: + if element in prev_dir_list: + matched.append(element) + + # calculate difference between matched and length + diff = dir_depth - len(matched) + + # print 'MATCHED: ' + str(matched) + + # if previous dir was not root + if prev_dir != '': + # if the elements count is not equal we calculate the difference + if len(dir_list) != len(prev_dir_list): + dir_depth_prev = len(prev_dir_list) + delta = dir_depth_prev - len(matched) + + for i in range(dir_depth_prev - delta, dir_depth_prev): + output.append('') + + # if the elements count is equal, we subtract the matched length from the total length + else: + for i in range(len(matched), len(dir_list)): + output.append('') + + for i in range(dir_depth - diff, dir_depth): + output.append('') + folder_count += 1 + + # Current File is in root + else: + # Close Tag if we are in root and the previous dir wasn't + if cur_dir == '' and prev_dir != '': + for i in range(0, len(prev_dir_list)): output.append('') - # if the elements count is equal, we subtract the matched length from the total length - else: - for i in range(len(matched), len(dir_list)): - output.append('') - - for i in range(dir_depth - diff, dir_depth): - output.append('') - folder_count += 1 - - # Current File is in root - else: - # Close Tag if we are in root and the previous dir wasn't - if cur_dir == '' and prev_dir != '': - for i in range(0, len(prev_dir_list)): + # Save the Current Dir + prev_dir = cur_dir + output.append('' + str(item) + '') + # if last iteration close all open tags + if idx == len(file_list) - 1 and cur_dir != '': + for i in range(0, len(dir_list)): output.append('') - # Save the Current Dir - prev_dir = cur_dir - output.append('' + str(item) + '') - # if last iteration close all open tags - if idx == len(file_list) - 1 and cur_dir != '': - for i in range(0, len(dir_list)): - output.append('') + return output - return output + @staticmethod + def get_netbeans_c_std(c_std): + c_std_netbeans = 0 + if '89' in c_std: + c_std_netbeans = 2 + elif '99' in c_std: + c_std_netbeans = 3 + elif '11' in c_std: + c_std_netbeans = 10 + return c_std_netbeans - -class NetbeansGcc(Netbeans, GccArm): - LOAD_EXE = True - NAME = "Netbeans-GCC-ARM" - - -class NetbeansArmc5(Netbeans, Armc5): - LOAD_EXE = False - NAME = "Netbeans-Armc5" - - -class NetbeansIAR(Netbeans, IAR): - LOAD_EXE = True - NAME = "Netbeans-IAR" + @staticmethod + def get_netbeans_cpp_std(cpp_std): + cpp_std_netbeans = 0 + if '98' in cpp_std: + cpp_std_netbeans = 4 + elif '11' in cpp_std: + cpp_std_netbeans = 8 + elif '14' in cpp_std: + cpp_std_netbeans = 11 + return cpp_std_netbeans diff --git a/tools/export/nb/configurations.tmpl b/tools/export/nb/configurations.tmpl index 93241d6934..6f0c69992c 100644 --- a/tools/export/nb/configurations.tmpl +++ b/tools/export/nb/configurations.tmpl @@ -1,8 +1,6 @@ - - @@ -10,6 +8,11 @@ {{ header }} {% endfor %} + + {{ linker_script }} + @@ -21,6 +24,10 @@ {{ source }} {% endfor %} + + Makefile + ^(nbproject)$ + + . + Makefile - + {% for id in options -%} + {% set opts = options[id] %} + default true @@ -43,37 +56,53 @@ + {{ c_std }} - {% for include in include_paths -%} - {{ include }} - {% endfor %} + {% for inc_dir in include_paths -%}{% if inc_dir -%} + {{ inc_dir }} + {% endif -%} + {% endfor -%} - - {% for flag in c_flags -%} - {{ flag }} - {% endfor %} + + {% for inc_file in forced_includes -%} + {{ inc_file }} + {% endfor -%} + + {%- for flag in c_flags -%}{{ flag+" "}}{%- endfor -%} + {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%} + {% for item in opts['defines'] -%} + {{ item }} + {% endfor -%} {% for symbol in c_symbols -%} {{ symbol }} - {% endfor %} + {% endfor -%} + {{ cpp_std }} - {% for include in include_paths -%} - {{ include }} - {% endfor %} + {% for inc_dir in include_paths -%}{% if inc_dir -%} + {{ inc_dir }} + {% endif -%} + {% endfor -%} - - {% for flag in cxx_flags -%} - {{ flag }} - {% endfor %} + + {% for inc_file in forced_includes -%} + {{ inc_file }} + {% endfor -%} + + {%- for flag in cxx_flags -%}{{ flag+" "}}{%- endfor -%} + {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%} + {% for item in opts['defines'] -%} + {{ item }} + {% endfor -%} {% for symbol in c_symbols -%} {{ symbol }} - {% endfor %} + {% endfor -%} @@ -82,124 +111,57 @@ 5 - {% for include in include_paths -%} - {{ include }} - {% endfor %} + {% for inc_dir in include_paths -%}{% if inc_dir -%} + {{ inc_dir }} + {% endif -%} + {% endfor -%} - - {% for flag in asm_flags -%} - {{ flag }} - {% endfor %} + + {% for inc_file in forced_includes -%} + {{ inc_file }} + {% endfor -%} + + {%- for flag in asm_flags -%}{{ flag+" "}}{%- endfor -%} + {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%} {% for symbol in asm_symbols -%} {{ symbol }} - {% endfor %} + {% endfor -%} - - {% for flag in ld_flags -%} - {{ flag }} - {% endfor %} - + arm-none-eabi-gcc + {%- for symbol in opts['ld'] -%}{{ symbol+" "}}{%- endfor -%} - {% for h in headers -%} - {% endfor %} - {% for s in sources -%} - - - {% endfor %} - - - - - - - default - true - false - - - {% for h in headers -%} - - - {% endfor %} - {% for s in sources -%} - - - {% endfor %} - - 5 - - {% for include in include_paths -%} - {{ include }} - {% endfor %} - - - {% for flag in c_flags -%} - {{ flag }} - {% endfor %} - - - {% for symbol in c_symbols -%} - {{ symbol }} - {% endfor %} - + {% endfor -%} + {% for s in c_sources -%} + + - - 5 - - {% for include in include_paths -%} - {{ include }} - {% endfor %} - - - {% for flag in cxx_flags -%} - {{ flag }} - {% endfor %} - - - {% for symbol in c_symbols -%} - {{ symbol }} - {% endfor %} - + + {% endfor -%} + {% for s in cpp_sources -%} + + - - 5 - - - 5 - - {% for include in include_paths -%} - {{ include }} - {% endfor %} - - - {% for flag in asm_flags -%} - {{ flag }} - {% endfor %} - - - {% for symbol in asm_symbols -%} - {{ symbol }} - {% endfor %} - - - - - {% for flag in ld_flags -%} - {{ flag }} - {% endfor %} - - - - + + {% endfor -%} + {% for s in s_sources -%} + + + {% endfor -%} + + + + + + {% endfor -%} diff --git a/tools/export/nb/project.tmpl b/tools/export/nb/project.tmpl index c73b0eebbd..3d4ea0d1bf 100644 --- a/tools/export/nb/project.tmpl +++ b/tools/export/nb/project.tmpl @@ -4,9 +4,9 @@ {{name}} - + c cpp - + h UTF-8 From f3a42f400a9be943cdfa38ac31b24eaa9581c415 Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Mon, 27 Nov 2017 17:03:39 +0100 Subject: [PATCH 057/133] Fixed Linking with Linker Script --- tools/export/nb/Makefile.tmpl | 13 ++++++++++++- tools/export/nb/__init__.py | 14 ++++++++++++++ tools/export/nb/configurations.tmpl | 9 ++++++++- 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/tools/export/nb/Makefile.tmpl b/tools/export/nb/Makefile.tmpl index 05de621e85..a7254417b1 100644 --- a/tools/export/nb/Makefile.tmpl +++ b/tools/export/nb/Makefile.tmpl @@ -49,6 +49,11 @@ MKDIR=mkdir CP=cp CCADMIN=CCadmin +BUILDDIR = BUILD +PLATFORM = {{target}} +ELF2BIN = 'arm-none-eabi-objcopy' +TARGET = ${CND_DISTDIR}/${CONF}/${CND_PLATFORM}/{{name}} + # build build: .build-post @@ -58,7 +63,10 @@ build: .build-post .build-post: .build-impl # Add your post 'build' code here... - + $(ELF2BIN) -O binary ${TARGET}.elf ${TARGET}.bin + +@echo "===== bin file ready to flash: $(TARGET).bin =====" + $(ELF2BIN) -O ihex ${TARGET}.elf ${TARGET}.hex + cp ${TARGET}.* ${CND_BUILDDIR}/${CONF}/${CND_PLATFORM} # clean clean: .clean-post @@ -126,3 +134,6 @@ include nbproject/Makefile-impl.mk # include project make variables include nbproject/Makefile-variables.mk + +CND_BUILDDIR = ${BUILDDIR} +CND_PLATFORM = ${PLATFORM} diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index 2a3357d986..0b797a79b1 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -28,6 +28,10 @@ class GNUARMNetbeans(Exporter): return apply_supported_whitelist( cls.TOOLCHAIN, POST_BINARY_WHITELIST, target) + @staticmethod + def prepare_sys_lib(libname): + return "-l" + libname + def toolchain_flags(self, toolchain): """Returns a dictionary of toolchain flags. Keys of the dictionary are: @@ -207,11 +211,19 @@ class GNUARMNetbeans(Exporter): sources = [self.filter_dot(field) for field in sources] include_paths = [self.filter_dot(field) for field in self.resources.inc_dirs] + sys_libs = [self.prepare_sys_lib(lib) for lib + in self.toolchain.sys_libs] + preproc = " ".join([part for part + in ([basename(self.toolchain.preproc[0])] + + self.toolchain.preproc[1:] + + self.toolchain.ld[1:])]) + if 'nbproject' in include_paths: include_paths.remove('nbproject') jinja_ctx = { 'name': self.project_name, + 'target': self.toolchain.target.name, 'elf_location': join('BUILD', self.project_name) + '.elf', 'c_symbols': self.toolchain.get_symbols(), 'asm_symbols': self.toolchain.get_symbols(True), @@ -233,6 +245,8 @@ class GNUARMNetbeans(Exporter): 'c_std': self.get_netbeans_c_std(c_std), 'cpp_std': self.get_netbeans_cpp_std(cpp_std), 'linker_script': self.ld_script, + 'linker_libs': sys_libs, + 'pp_cmd': preproc } return jinja_ctx diff --git a/tools/export/nb/configurations.tmpl b/tools/export/nb/configurations.tmpl index 6f0c69992c..8eeeac258d 100644 --- a/tools/export/nb/configurations.tmpl +++ b/tools/export/nb/configurations.tmpl @@ -131,8 +131,10 @@ + ${CND_DISTDIR}/${CND_CONF}/{{target}}/{{name}}.elf + ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld arm-none-eabi-gcc - {%- for symbol in opts['ld'] -%}{{ symbol+" "}}{%- endfor -%} + -T ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld {%- for symbol in opts['ld'] -%}{{" "+symbol}}{%- endfor -%} {%- for item in linker_libs -%}{{" "+item}}{%- endfor -%} {% for h in headers -%} @@ -156,6 +158,11 @@ {% endfor -%} + + {{pp_cmd}} -o $@ $< + Create ELF File using Link Script + ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld + From be3d5748dbe8740a76b7ec6cb506595a9532e27d Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Tue, 28 Nov 2017 07:14:14 +0100 Subject: [PATCH 058/133] Removed commented Line --- tools/export/nb/__init__.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index 0b797a79b1..e642ef4d39 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -253,8 +253,6 @@ class GNUARMNetbeans(Exporter): def generate(self): """Generate Makefile, configurations.xml & project.xml Netbeans project file """ - # super(Netbeans, self).generate() - jinja_ctx = self.create_jinja_ctx() print From c2ebdf32c69a77f5d21c92295ed812cb2debed0c Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Tue, 28 Nov 2017 07:15:41 +0100 Subject: [PATCH 059/133] Removed another block of unused (commented) code --- tools/export/nb/__init__.py | 6 ------ 1 file changed, 6 deletions(-) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index e642ef4d39..71afddd57b 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -295,12 +295,6 @@ class GNUARMNetbeans(Exporter): file_names = [join(tools_path, "profiles", fn) for fn in os.listdir( join(tools_path, "profiles")) if fn.endswith(".json")] - # print file_names - - # profile_names = [basename(fn).replace(".json", "") - # for fn in file_names] - # print profile_names - profiles = {} for fn in file_names: From eed506178311bf165e6a8c96c5db5addb7231306 Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Tue, 28 Nov 2017 07:42:13 +0100 Subject: [PATCH 060/133] Refactoring of function get_netbeans_file_list(file_list) to have a clearer code --- tools/export/nb/__init__.py | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index 71afddd57b..b7a4610ccf 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -309,7 +309,8 @@ class GNUARMNetbeans(Exporter): output = [] prev_dir = '' folder_count = 1 - for idx, item in enumerate(file_list): + dir_depth = 0 + for item in (file_list): cur_dir = os.path.dirname(item) dir_temp = os.path.normpath(cur_dir) prev_dir_temp = os.path.normpath(prev_dir) @@ -317,10 +318,6 @@ class GNUARMNetbeans(Exporter): prev_dir_list = prev_dir_temp.split(os.sep) dir_depth = len(dir_list) - # print 'PREV_DIR: ' + str(prev_dir_list) - - # print 'CURR_DIR: ' + str(dir_list) - # Current File is in Directory: Compare the given dir with previous Dir if cur_dir and prev_dir != cur_dir: # evaluate all matched items (from current and previous list) @@ -332,8 +329,6 @@ class GNUARMNetbeans(Exporter): # calculate difference between matched and length diff = dir_depth - len(matched) - # print 'MATCHED: ' + str(matched) - # if previous dir was not root if prev_dir != '': # if the elements count is not equal we calculate the difference @@ -364,10 +359,10 @@ class GNUARMNetbeans(Exporter): # Save the Current Dir prev_dir = cur_dir output.append('' + str(item) + '') - # if last iteration close all open tags - if idx == len(file_list) - 1 and cur_dir != '': - for i in range(0, len(dir_list)): - output.append('') + + if cur_dir != '': + # close all open tags + output.append('' * dir_depth) return output From 24e2fc86ed7e1feff83f88b8f23b0c1dfe6cb65b Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Wed, 29 Nov 2017 08:01:31 +0100 Subject: [PATCH 061/133] Removed unnecessary list comprehension --- tools/export/nb/__init__.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index b7a4610ccf..bfd610f05a 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -213,10 +213,9 @@ class GNUARMNetbeans(Exporter): sys_libs = [self.prepare_sys_lib(lib) for lib in self.toolchain.sys_libs] - preproc = " ".join([part for part - in ([basename(self.toolchain.preproc[0])] + + preproc = " ".join([basename(self.toolchain.preproc[0])] + self.toolchain.preproc[1:] + - self.toolchain.ld[1:])]) + self.toolchain.ld[1:]) if 'nbproject' in include_paths: include_paths.remove('nbproject') From 33be40c613b86001fece602be54bd9e52a2b381f Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Tue, 9 Jan 2018 15:57:52 +0100 Subject: [PATCH 062/133] Fixed indention in Line 217 and 218 --- tools/export/nb/__init__.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index bfd610f05a..79f335d081 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -214,8 +214,8 @@ class GNUARMNetbeans(Exporter): sys_libs = [self.prepare_sys_lib(lib) for lib in self.toolchain.sys_libs] preproc = " ".join([basename(self.toolchain.preproc[0])] + - self.toolchain.preproc[1:] + - self.toolchain.ld[1:]) + self.toolchain.preproc[1:] + + self.toolchain.ld[1:]) if 'nbproject' in include_paths: include_paths.remove('nbproject') From 25a5c0d8442d5f4e4200b4d551e599c51c0a76fc Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Tue, 9 Jan 2018 16:13:08 +0100 Subject: [PATCH 063/133] Removed getattr() where it was not needed --- tools/export/nb/__init__.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index 79f335d081..d9980ed2dc 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -204,10 +204,10 @@ class GNUARMNetbeans(Exporter): sources.extend(getattr(self.resources, r_type)) # Remove all leading './' - c_sources = [self.filter_dot(field) for field in getattr(self.resources, 'c_sources')] - cpp_sources = [self.filter_dot(field) for field in getattr(self.resources, 'cpp_sources')] - s_sources = [self.filter_dot(field) for field in getattr(self.resources, 's_sources')] - headers = [self.filter_dot(field) for field in getattr(self.resources, 'headers')] + c_sources = [self.filter_dot(field) for field in self.resources.c_sources] + cpp_sources = [self.filter_dot(field) for field in self.resources.cpp_sources] + s_sources = [self.filter_dot(field) for field in self.resources.s_sources] + headers = [self.filter_dot(field) for field in self.resources.headers] sources = [self.filter_dot(field) for field in sources] include_paths = [self.filter_dot(field) for field in self.resources.inc_dirs] From 6cb6f5810cbdc41cddeb1158a3e48484e9ef0870 Mon Sep 17 00:00:00 2001 From: Clemens Mandl Date: Tue, 9 Jan 2018 16:54:56 +0100 Subject: [PATCH 064/133] Small Refactoring of variable definitions and removed some unnecessary brackets --- tools/export/nb/__init__.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index d9980ed2dc..97c9c6632d 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -123,7 +123,8 @@ class GNUARMNetbeans(Exporter): raise NotSupportedException("No linker script found.") def create_jinja_ctx(self): - + self.options = {} + flags = {} self.validate_resources() # Convert all Backslashes to Forward Slashes self.resources.win_to_unix() @@ -141,8 +142,6 @@ class GNUARMNetbeans(Exporter): profile_ids = [s.lower() for s in profiles] profile_ids.sort() - - self.options = {} for prof_id in profile_ids: # There are 4 categories of options, a category common too # all tools and a specific category for each of the tools. @@ -231,7 +230,6 @@ class GNUARMNetbeans(Exporter): 'ld_flags': self.flags['ld_flags'], 'asm_flags': self.flags['asm_flags'], 'common_flags': self.flags['common_flags'], - 'target': self.target, 'include_paths': include_paths, 'forced_includes': forced_includes, 'c_sources': c_sources, @@ -305,11 +303,12 @@ class GNUARMNetbeans(Exporter): @staticmethod def get_netbeans_file_list(file_list): - output = [] + cur_dir = '' prev_dir = '' + output = [] folder_count = 1 dir_depth = 0 - for item in (file_list): + for item in file_list: cur_dir = os.path.dirname(item) dir_temp = os.path.normpath(cur_dir) prev_dir_temp = os.path.normpath(prev_dir) From 875425161a0c34821f0a04b1444c799234bf698b Mon Sep 17 00:00:00 2001 From: "c.mandl" Date: Mon, 15 Jan 2018 10:44:36 +0100 Subject: [PATCH 065/133] Added Compiler Toolchain Varibales in Templates and modfied generation of jinja --- tools/export/nb/Makefile.tmpl | 2 +- tools/export/nb/__init__.py | 7 ++++++- tools/export/nb/configurations.tmpl | 5 ++++- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/tools/export/nb/Makefile.tmpl b/tools/export/nb/Makefile.tmpl index a7254417b1..511311c6ef 100644 --- a/tools/export/nb/Makefile.tmpl +++ b/tools/export/nb/Makefile.tmpl @@ -51,7 +51,7 @@ CCADMIN=CCadmin BUILDDIR = BUILD PLATFORM = {{target}} -ELF2BIN = 'arm-none-eabi-objcopy' +ELF2BIN = '{{elf2bin_cmd}}' TARGET = ${CND_DISTDIR}/${CONF}/${CND_PLATFORM}/{{name}} diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index 97c9c6632d..c435b0d37d 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -243,7 +243,12 @@ class GNUARMNetbeans(Exporter): 'cpp_std': self.get_netbeans_cpp_std(cpp_std), 'linker_script': self.ld_script, 'linker_libs': sys_libs, - 'pp_cmd': preproc + 'pp_cmd': preproc, + 'cc_cmd': self.toolchain.cc[0], + 'cppc_cmd': self.toolchain.cppc[0], + 'asm_cmd': self.toolchain.asm[0], + 'ld_cmd': self.toolchain.ld[0], + 'elf2bin_cmd': self.toolchain.elf2bin } return jinja_ctx diff --git a/tools/export/nb/configurations.tmpl b/tools/export/nb/configurations.tmpl index 8eeeac258d..b53397a025 100644 --- a/tools/export/nb/configurations.tmpl +++ b/tools/export/nb/configurations.tmpl @@ -79,6 +79,7 @@ {{ symbol }} {% endfor -%} + {{cc_cmd}} {{ cpp_std }} @@ -104,6 +105,7 @@ {{ symbol }} {% endfor -%} + {{cppc_cmd}} 5 @@ -129,11 +131,12 @@ {{ symbol }} {% endfor -%} + {{asm_cmd}} ${CND_DISTDIR}/${CND_CONF}/{{target}}/{{name}}.elf ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld - arm-none-eabi-gcc + {{ld_cmd}} -T ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld {%- for symbol in opts['ld'] -%}{{" "+symbol}}{%- endfor -%} {%- for item in linker_libs -%}{{" "+item}}{%- endfor -%} From cc3a66b01168e09c5cf7b228a4c02b05aed65f26 Mon Sep 17 00:00:00 2001 From: Przemyslaw Stekiel Date: Fri, 19 Jan 2018 13:16:05 +0100 Subject: [PATCH 066/133] Provide fix for issue #5835 - Tickers update should be atomic Synchronise only (and all) the public functions. --- hal/mbed_ticker_api.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hal/mbed_ticker_api.c b/hal/mbed_ticker_api.c index 114a5a4628..765a077c0e 100644 --- a/hal/mbed_ticker_api.c +++ b/hal/mbed_ticker_api.c @@ -110,7 +110,6 @@ static us_timestamp_t convert_timestamp(us_timestamp_t ref, timestamp_t timestam */ static void update_present_time(const ticker_data_t *const ticker) { - ticker_event_queue_t *queue = ticker->queue; uint32_t ticker_time = ticker->interface->read(); if (ticker_time == ticker->queue->tick_last_read) { @@ -252,11 +251,16 @@ static void schedule_interrupt(const ticker_data_t *const ticker) void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler) { initialize(ticker); + + core_util_critical_section_enter(); set_handler(ticker, handler); + core_util_critical_section_exit(); } void ticker_irq_handler(const ticker_data_t *const ticker) { + core_util_critical_section_enter(); + ticker->interface->clear_interrupt(); /* Go through all the pending TimerEvents */ @@ -284,6 +288,8 @@ void ticker_irq_handler(const ticker_data_t *const ticker) } schedule_interrupt(ticker); + + core_util_critical_section_exit(); } void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id) @@ -296,13 +302,14 @@ void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, ticker->queue->present_time, timestamp ); - core_util_critical_section_exit(); // defer to ticker_insert_event_us ticker_insert_event_us( ticker, obj, absolute_timestamp, id ); + + core_util_critical_section_exit(); } void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id) @@ -343,6 +350,7 @@ void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *o schedule_interrupt(ticker); core_util_critical_section_exit(); + } void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj) @@ -377,7 +385,11 @@ timestamp_t ticker_read(const ticker_data_t *const ticker) us_timestamp_t ticker_read_us(const ticker_data_t *const ticker) { initialize(ticker); + + core_util_critical_section_enter(); update_present_time(ticker); + core_util_critical_section_exit(); + return ticker->queue->present_time; } From 51b7ed1114183b9fa3570a6d803f0aced4b2d23e Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Wed, 17 Jan 2018 11:14:41 +0000 Subject: [PATCH 067/133] RTX idle: sleep without locked deep sleep fix If tickless is enabled, it should not be locking deepsleep --- rtos/TARGET_CORTEX/mbed_rtx_idle.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index bb2be1c421..f41b562c54 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -198,9 +198,7 @@ static void default_idle_hook(void) if (ticks_to_sleep) { os_timer->schedule_tick(ticks_to_sleep); - sleep_manager_lock_deep_sleep(); sleep(); - sleep_manager_unlock_deep_sleep(); os_timer->cancel_tick(); // calculate how long we slept From 133a3ddbae34639876a19d379f28fb61eb3e9553 Mon Sep 17 00:00:00 2001 From: Jani Suonpera Date: Wed, 17 Jan 2018 10:39:16 +0200 Subject: [PATCH 068/133] Update CoAP to 4.0.11 This PR implement https://tools.ietf.org/html/rfc7959#section-2.5 "The error code 4.13 (Request Entity Too Large) can be returned at any time by a server that does not currently have the resources to store blocks for a block-wise request payload transfer that it would intend to implement in an atomic fashion. (Note that a 4.13 response to a request that does not employ Block1 is a hint for the client to try sending Block1, and a 4.13 response with a smaller SZX in its Block1 Option than requested is a hint to try a smaller SZX.) --- features/FEATURE_COMMON_PAL/mbed-coap/module.json | 2 +- .../mbed-coap/source/sn_coap_protocol.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/module.json b/features/FEATURE_COMMON_PAL/mbed-coap/module.json index 265a343e7a..454251ee02 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/module.json +++ b/features/FEATURE_COMMON_PAL/mbed-coap/module.json @@ -1,6 +1,6 @@ { "name": "mbed-coap", - "version": "4.0.10", + "version": "4.0.11", "description": "COAP library", "keywords": [ "coap", diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c index 1e14055faf..234de67866 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c @@ -1756,6 +1756,15 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn /* Check block size */ block_temp = (src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 & 0x07); + uint16_t block_size = 1u << (block_temp + 4); + if (block_size > handle->sn_coap_block_data_size) { + // Include maximum size that stack can handle into response + tr_error("sn_coap_handle_blockwise_message - (recv block1) COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE!"); + src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; + src_coap_blockwise_ack_msg_ptr->options_list_ptr->size1 = handle->sn_coap_block_data_size; + sn_coap_protocol_linked_list_blockwise_payload_remove_oldest(handle); + } + if (block_temp > sn_coap_convert_block_size(handle->sn_coap_block_data_size)) { src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 &= 0xFFFFF8; src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 |= sn_coap_convert_block_size(handle->sn_coap_block_data_size); From 60b86327062672890fd18e736cd7582a47e65653 Mon Sep 17 00:00:00 2001 From: Antti Yli-Tokola Date: Wed, 17 Jan 2018 12:32:19 +0200 Subject: [PATCH 069/133] mbed-coap update to version 4.1.0 - New API to control whether coap itself sends a next GET(block2) request or not - Fixes error IOTCLT-2203 mbed-coap does not handle PUT or POST if they indicate a smaller block size preference --- .../FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md | 10 + .../mbed-coap/mbed-coap/sn_coap_protocol.h | 23 ++ .../FEATURE_COMMON_PAL/mbed-coap/module.json | 2 +- .../include/sn_coap_protocol_internal.h | 1 + .../mbed-coap/source/sn_coap_builder.c | 10 +- .../mbed-coap/source/sn_coap_protocol.c | 343 ++++++++++-------- 6 files changed, 231 insertions(+), 158 deletions(-) diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md index 15bd3813d1..395463ff02 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md +++ b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md @@ -1,5 +1,15 @@ # Change Log +## [v4.1.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.1.0) + +-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.10...v4.1.0) + + **New feature:** + - New API to disable automatic GET(BLOCK2) request sending. + + **Closed issues:** + - IOTCLT-2203 mbed-coap does not handle PUT or POST if they indicate a smaller block size preference + ## [v4.0.10](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.10) -[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.9...v4.0.10) diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h index b9fbdc63ac..2ec2aee887 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h @@ -213,6 +213,29 @@ extern void sn_coap_protocol_block_remove(struct coap_s *handle, sn_nsdl_addr_s */ extern int8_t sn_coap_protocol_delete_retransmission(struct coap_s *handle, uint16_t msg_id); +/** + * \fn int8_t sn_coap_convert_block_size(uint16_t block_size) + * + * \brief Utility function to convert block size. + * + * \param block_size Block size to convert. + * + * \return Value of range 0 - 6 + */ +extern int8_t sn_coap_convert_block_size(uint16_t block_size); + +/** + * \fn int8_t sn_coap_protocol_handle_block2_response_internally(struct coap_s *handle, uint8_t handle_response) + * + * \brief This function change the state whether CoAP library sends the block 2 response automatically or not. + * + * \param *handle Pointer to CoAP library handle + * \param handle_response 1 if CoAP library handles the response sending otherwise 0. + * + * \return 0 = success, -1 = failure + */ +extern int8_t sn_coap_protocol_handle_block2_response_internally(struct coap_s *handle, uint8_t handle_response); + #endif /* SN_COAP_PROTOCOL_H_ */ #ifdef __cplusplus diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/module.json b/features/FEATURE_COMMON_PAL/mbed-coap/module.json index 454251ee02..6255054aca 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/module.json +++ b/features/FEATURE_COMMON_PAL/mbed-coap/module.json @@ -1,6 +1,6 @@ { "name": "mbed-coap", - "version": "4.0.11", + "version": "4.1.0", "description": "COAP library", "keywords": [ "coap", diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h b/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h index 19f057f278..d8c85b54ab 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h @@ -229,6 +229,7 @@ struct coap_s { uint8_t sn_coap_resending_count; uint8_t sn_coap_resending_intervall; uint8_t sn_coap_duplication_buffer_size; + uint8_t sn_coap_internal_block2_resp_handling; /* If this is set then coap itself sends a next GET request automatically */ }; #ifdef __cplusplus diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c index 4aac0d1142..726055ad6c 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_builder.c @@ -63,18 +63,22 @@ sn_coap_hdr_s *sn_coap_build_response(struct coap_s *handle, sn_coap_hdr_s *coap return NULL; } - if (coap_packet_ptr->msg_type == COAP_MSG_TYPE_CONFIRMABLE) { + if (msg_code == COAP_MSG_CODE_REQUEST_GET) { + // Blockwise message response is new GET + coap_res_ptr->msg_type = COAP_MSG_TYPE_CONFIRMABLE; + coap_res_ptr->msg_code = (sn_coap_msg_code_e)msg_code; + /* msg_id needs to be set by the caller in this case */ + } + else if (coap_packet_ptr->msg_type == COAP_MSG_TYPE_CONFIRMABLE) { coap_res_ptr->msg_type = COAP_MSG_TYPE_ACKNOWLEDGEMENT; coap_res_ptr->msg_code = (sn_coap_msg_code_e)msg_code; coap_res_ptr->msg_id = coap_packet_ptr->msg_id; } - else if (coap_packet_ptr->msg_type == COAP_MSG_TYPE_NON_CONFIRMABLE) { coap_res_ptr->msg_type = COAP_MSG_TYPE_NON_CONFIRMABLE; coap_res_ptr->msg_code = (sn_coap_msg_code_e)msg_code; /* msg_id needs to be set by the caller in this case */ } - else { handle->sn_coap_protocol_free( coap_res_ptr ); return NULL; diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c index 234de67866..86020085ab 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c @@ -64,7 +64,6 @@ static void sn_coap_protocol_linked_list_blockwise_payload_remo static uint32_t sn_coap_protocol_linked_list_blockwise_payloads_get_len(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr); static void sn_coap_protocol_linked_list_blockwise_remove_old_data(struct coap_s *handle); static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, sn_coap_hdr_s *received_coap_msg_ptr, void *param); -static int8_t sn_coap_convert_block_size(uint16_t block_size); static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *handle, sn_coap_hdr_s *source_header_ptr); #endif #if ENABLE_RESENDINGS @@ -182,10 +181,10 @@ struct coap_s *sn_coap_protocol_init(void *(*used_malloc_func_ptr)(uint16_t), vo /* If pointer = 0, then re-sending does not return error when failed */ handle->sn_coap_rx_callback = used_rx_callback_ptr; - + // Handles internally all GET req responses + handle->sn_coap_internal_block2_resp_handling = true; #if ENABLE_RESENDINGS /* If Message resending is not used at all, this part of code will not be compiled */ - /* * * * Create Linked list for storing active resending messages * * * */ ns_list_init(&handle->linked_list_resent_msgs); handle->sn_coap_resending_queue_msgs = SN_COAP_RESENDING_QUEUE_SIZE_MSGS; @@ -220,6 +219,16 @@ struct coap_s *sn_coap_protocol_init(void *(*used_malloc_func_ptr)(uint16_t), vo return handle; } +int8_t sn_coap_protocol_handle_block2_response_internally(struct coap_s *handle, uint8_t build_response) +{ + if (handle == NULL) { + return -1; + } + + handle->sn_coap_internal_block2_resp_handling = build_response; + return 0; +} + int8_t sn_coap_protocol_set_block_size(struct coap_s *handle, uint16_t block_size) { (void) handle; @@ -1841,178 +1850,204 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn else { //This is response to request we made if (received_coap_msg_ptr->msg_code > COAP_MSG_CODE_REQUEST_DELETE) { - uint32_t block_number = 0; + if (handle->sn_coap_internal_block2_resp_handling) { + uint32_t block_number = 0; - /* Store blockwise payload to Linked list */ - //todo: add block number to stored values - just to make sure all packets are in order - sn_coap_protocol_linked_list_blockwise_payload_store(handle, - src_addr_ptr, - received_coap_msg_ptr->payload_len, - received_coap_msg_ptr->payload_ptr, - received_coap_msg_ptr->options_list_ptr->block1 >> 4); + /* Store blockwise payload to Linked list */ + //todo: add block number to stored values - just to make sure all packets are in order + sn_coap_protocol_linked_list_blockwise_payload_store(handle, + src_addr_ptr, + received_coap_msg_ptr->payload_len, + received_coap_msg_ptr->payload_ptr, + received_coap_msg_ptr->options_list_ptr->block2 >> 4); + /* If not last block (more value is set) */ + if (received_coap_msg_ptr->options_list_ptr->block2 & 0x08) { + coap_blockwise_msg_s *previous_blockwise_msg_ptr = NULL; + //build and send ack + received_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_BLOCKWISE_MSG_RECEIVING; - /* If not last block (more value is set) */ - if (received_coap_msg_ptr->options_list_ptr->block2 & 0x08) { - coap_blockwise_msg_s *previous_blockwise_msg_ptr = NULL; - //build and send ack - received_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_BLOCKWISE_MSG_RECEIVING; - - ns_list_foreach(coap_blockwise_msg_s, msg, &handle->linked_list_blockwise_sent_msgs) { - if (received_coap_msg_ptr->msg_id == msg->coap_msg_ptr->msg_id) { - previous_blockwise_msg_ptr = msg; - break; + ns_list_foreach(coap_blockwise_msg_s, msg, &handle->linked_list_blockwise_sent_msgs) { + if (received_coap_msg_ptr->msg_id == msg->coap_msg_ptr->msg_id) { + previous_blockwise_msg_ptr = msg; + break; + } } - } - if (!previous_blockwise_msg_ptr || !previous_blockwise_msg_ptr->coap_msg_ptr) { - tr_error("sn_coap_handle_blockwise_message - (send block2) previous message null!"); - sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); - return 0; - } - - src_coap_blockwise_ack_msg_ptr = sn_coap_parser_alloc_message(handle); - if (src_coap_blockwise_ack_msg_ptr == NULL) { - tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate message!"); - return 0; - } - - ns_list_remove(&handle->linked_list_blockwise_sent_msgs, previous_blockwise_msg_ptr); - if( previous_blockwise_msg_ptr->coap_msg_ptr ){ - if(previous_blockwise_msg_ptr->coap_msg_ptr->payload_ptr){ - handle->sn_coap_protocol_free(previous_blockwise_msg_ptr->coap_msg_ptr->payload_ptr); - previous_blockwise_msg_ptr->coap_msg_ptr->payload_ptr = 0; + if (!previous_blockwise_msg_ptr || !previous_blockwise_msg_ptr->coap_msg_ptr) { + tr_error("sn_coap_handle_blockwise_message - (send block2) previous message null!"); + sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); + return 0; } - sn_coap_parser_release_allocated_coap_msg_mem(handle, previous_blockwise_msg_ptr->coap_msg_ptr); - previous_blockwise_msg_ptr->coap_msg_ptr = 0; - } - handle->sn_coap_protocol_free(previous_blockwise_msg_ptr); - previous_blockwise_msg_ptr = 0; - /* * * Then build CoAP Acknowledgement message * * */ + src_coap_blockwise_ack_msg_ptr = sn_coap_parser_alloc_message(handle); + if (src_coap_blockwise_ack_msg_ptr == NULL) { + tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate message!"); + return 0; + } - if (sn_coap_parser_alloc_options(handle, src_coap_blockwise_ack_msg_ptr) == NULL) { - tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate options!"); - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); - src_coap_blockwise_ack_msg_ptr = 0; - sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); - return NULL; - } + /* * * Then build CoAP Acknowledgement message * * */ - src_coap_blockwise_ack_msg_ptr->msg_id = message_id++; - if (message_id == 0) { - message_id = 1; - } + if (sn_coap_parser_alloc_options(handle, src_coap_blockwise_ack_msg_ptr) == NULL) { + tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate options!"); + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); + src_coap_blockwise_ack_msg_ptr = 0; + sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); + return NULL; + } - /* Update block option */ - block_temp = received_coap_msg_ptr->options_list_ptr->block2 & 0x07; + src_coap_blockwise_ack_msg_ptr->msg_id = message_id++; + if (message_id == 0) { + message_id = 1; + } - block_number = received_coap_msg_ptr->options_list_ptr->block2 >> 4; - block_number ++; + /* Update block option */ + block_temp = received_coap_msg_ptr->options_list_ptr->block2 & 0x07; - src_coap_blockwise_ack_msg_ptr->options_list_ptr->block2 = (block_number << 4) | block_temp; + block_number = received_coap_msg_ptr->options_list_ptr->block2 >> 4; + block_number ++; - /* Then get needed memory count for Packet data */ - dst_packed_data_needed_mem = sn_coap_builder_calc_needed_packet_data_size_2(src_coap_blockwise_ack_msg_ptr ,handle->sn_coap_block_data_size); + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block2 = (block_number << 4) | block_temp; - /* Then allocate memory for Packet data */ - dst_ack_packet_data_ptr = handle->sn_coap_protocol_malloc(dst_packed_data_needed_mem); - if (dst_ack_packet_data_ptr == NULL) { - tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate packet!"); - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); - src_coap_blockwise_ack_msg_ptr->options_list_ptr = 0; - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); - src_coap_blockwise_ack_msg_ptr = 0; - sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); - return NULL; - } - memset(dst_ack_packet_data_ptr, 0, dst_packed_data_needed_mem); + /* Set BLOCK2 (subsequent) GET msg code and copy uri path from previous msg*/ + if (received_coap_msg_ptr->msg_code == COAP_MSG_CODE_RESPONSE_CONTENT) { + src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_REQUEST_GET; + if (previous_blockwise_msg_ptr->coap_msg_ptr->uri_path_ptr) { + src_coap_blockwise_ack_msg_ptr->uri_path_len = previous_blockwise_msg_ptr->coap_msg_ptr->uri_path_len; + src_coap_blockwise_ack_msg_ptr->uri_path_ptr = handle->sn_coap_protocol_malloc(previous_blockwise_msg_ptr->coap_msg_ptr->uri_path_len); + if (!src_coap_blockwise_ack_msg_ptr->uri_path_ptr) { + sn_coap_parser_release_allocated_coap_msg_mem(handle, src_coap_blockwise_ack_msg_ptr); + tr_error("sn_coap_handle_blockwise_message - failed to allocate for uri path ptr!"); + return NULL; + } + memcpy(src_coap_blockwise_ack_msg_ptr->uri_path_ptr, previous_blockwise_msg_ptr->coap_msg_ptr->uri_path_ptr, previous_blockwise_msg_ptr->coap_msg_ptr->uri_path_len); + } + if (previous_blockwise_msg_ptr->coap_msg_ptr->token_ptr) { + src_coap_blockwise_ack_msg_ptr->token_len = previous_blockwise_msg_ptr->coap_msg_ptr->token_len; + src_coap_blockwise_ack_msg_ptr->token_ptr = handle->sn_coap_protocol_malloc(previous_blockwise_msg_ptr->coap_msg_ptr->token_len); + if (!src_coap_blockwise_ack_msg_ptr->token_ptr) { + sn_coap_parser_release_allocated_coap_msg_mem(handle, src_coap_blockwise_ack_msg_ptr); + tr_error("sn_coap_handle_blockwise_message - failed to allocate for token ptr!"); + return NULL; + } + memcpy(src_coap_blockwise_ack_msg_ptr->token_ptr, previous_blockwise_msg_ptr->coap_msg_ptr->token_ptr, previous_blockwise_msg_ptr->coap_msg_ptr->token_len); + } + } - /* * * Then build Acknowledgement message to Packed data * * */ - if ((sn_coap_builder_2(dst_ack_packet_data_ptr, src_coap_blockwise_ack_msg_ptr, handle->sn_coap_block_data_size)) < 0) { - tr_error("sn_coap_handle_blockwise_message - (send block2) builder failed!"); + ns_list_remove(&handle->linked_list_blockwise_sent_msgs, previous_blockwise_msg_ptr); + if (previous_blockwise_msg_ptr->coap_msg_ptr) { + if (previous_blockwise_msg_ptr->coap_msg_ptr->payload_ptr) { + handle->sn_coap_protocol_free(previous_blockwise_msg_ptr->coap_msg_ptr->payload_ptr); + previous_blockwise_msg_ptr->coap_msg_ptr->payload_ptr = 0; + } + sn_coap_parser_release_allocated_coap_msg_mem(handle, previous_blockwise_msg_ptr->coap_msg_ptr); + previous_blockwise_msg_ptr->coap_msg_ptr = 0; + } + handle->sn_coap_protocol_free(previous_blockwise_msg_ptr); + previous_blockwise_msg_ptr = 0; + + /* Then get needed memory count for Packet data */ + dst_packed_data_needed_mem = sn_coap_builder_calc_needed_packet_data_size_2(src_coap_blockwise_ack_msg_ptr ,handle->sn_coap_block_data_size); + + /* Then allocate memory for Packet data */ + dst_ack_packet_data_ptr = handle->sn_coap_protocol_malloc(dst_packed_data_needed_mem); + + if (dst_ack_packet_data_ptr == NULL) { + tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate packet!"); + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); + src_coap_blockwise_ack_msg_ptr->options_list_ptr = 0; + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); + src_coap_blockwise_ack_msg_ptr = 0; + sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); + return NULL; + } + memset(dst_ack_packet_data_ptr, 0, dst_packed_data_needed_mem); + + /* * * Then build Acknowledgement message to Packed data * * */ + if ((sn_coap_builder_2(dst_ack_packet_data_ptr, src_coap_blockwise_ack_msg_ptr, handle->sn_coap_block_data_size)) < 0) { + tr_error("sn_coap_handle_blockwise_message - (send block2) builder failed!"); + handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); + dst_ack_packet_data_ptr = 0; + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); + src_coap_blockwise_ack_msg_ptr->options_list_ptr = 0; + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); + src_coap_blockwise_ack_msg_ptr = 0; + sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); + return NULL; + } + + /* * * Save to linked list * * */ + coap_blockwise_msg_s *stored_blockwise_msg_ptr; + + stored_blockwise_msg_ptr = handle->sn_coap_protocol_malloc(sizeof(coap_blockwise_msg_s)); + if (!stored_blockwise_msg_ptr) { + tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate blockwise message!"); + handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); + dst_ack_packet_data_ptr = 0; + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); + src_coap_blockwise_ack_msg_ptr->options_list_ptr = 0; + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); + src_coap_blockwise_ack_msg_ptr = 0; + sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); + return 0; + } + memset(stored_blockwise_msg_ptr, 0, sizeof(coap_blockwise_msg_s)); + + stored_blockwise_msg_ptr->timestamp = handle->system_time; + + stored_blockwise_msg_ptr->coap_msg_ptr = src_coap_blockwise_ack_msg_ptr; + stored_blockwise_msg_ptr->coap = handle; + ns_list_add_to_end(&handle->linked_list_blockwise_sent_msgs, stored_blockwise_msg_ptr); + + /* * * Then release memory of CoAP Acknowledgement message * * */ + handle->sn_coap_tx_callback(dst_ack_packet_data_ptr, + dst_packed_data_needed_mem, src_addr_ptr, param); + + #if ENABLE_RESENDINGS + uint32_t resend_time = sn_coap_calculate_new_resend_time(handle->system_time, handle->sn_coap_resending_intervall, 0); + sn_coap_protocol_linked_list_send_msg_store(handle, src_addr_ptr, + dst_packed_data_needed_mem, + dst_ack_packet_data_ptr, + resend_time, param); + #endif handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); dst_ack_packet_data_ptr = 0; - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); - src_coap_blockwise_ack_msg_ptr->options_list_ptr = 0; - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); - src_coap_blockwise_ack_msg_ptr = 0; - sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); - return NULL; } - /* * * Save to linked list * * */ - coap_blockwise_msg_s *stored_blockwise_msg_ptr; + //Last block received + else { + /* * * This is the last block when whole Blockwise payload from received * * */ + /* * * blockwise messages is gathered and returned to User * * */ - stored_blockwise_msg_ptr = handle->sn_coap_protocol_malloc(sizeof(coap_blockwise_msg_s)); - if (!stored_blockwise_msg_ptr) { - tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate blockwise message!"); - handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); - dst_ack_packet_data_ptr = 0; - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); - src_coap_blockwise_ack_msg_ptr->options_list_ptr = 0; - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); - src_coap_blockwise_ack_msg_ptr = 0; - sn_coap_parser_release_allocated_coap_msg_mem(handle, received_coap_msg_ptr); - return 0; + /* Store last Blockwise payload to Linked list */ + uint16_t payload_len = 0; + uint8_t *payload_ptr = sn_coap_protocol_linked_list_blockwise_payload_search(handle, src_addr_ptr, &payload_len); + uint16_t whole_payload_len = sn_coap_protocol_linked_list_blockwise_payloads_get_len(handle, src_addr_ptr); + uint8_t *temp_whole_payload_ptr = NULL; + + temp_whole_payload_ptr = handle->sn_coap_protocol_malloc(whole_payload_len); + if (!temp_whole_payload_ptr) { + tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate whole payload!"); + return 0; + } + + received_coap_msg_ptr->payload_ptr = temp_whole_payload_ptr; + received_coap_msg_ptr->payload_len = whole_payload_len; + + /* Copy stored Blockwise payloads to returned whole Blockwise payload pointer */ + while (payload_ptr != NULL) { + memcpy(temp_whole_payload_ptr, payload_ptr, payload_len); + + temp_whole_payload_ptr += payload_len; + + sn_coap_protocol_linked_list_blockwise_payload_remove_oldest(handle); + payload_ptr = sn_coap_protocol_linked_list_blockwise_payload_search(handle, src_addr_ptr, &payload_len); + } + received_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_BLOCKWISE_MSG_RECEIVED; + + //todo: remove previous msg from list } - memset(stored_blockwise_msg_ptr, 0, sizeof(coap_blockwise_msg_s)); - - stored_blockwise_msg_ptr->timestamp = handle->system_time; - - stored_blockwise_msg_ptr->coap_msg_ptr = src_coap_blockwise_ack_msg_ptr; - stored_blockwise_msg_ptr->coap = handle; - ns_list_add_to_end(&handle->linked_list_blockwise_sent_msgs, stored_blockwise_msg_ptr); - - /* * * Then release memory of CoAP Acknowledgement message * * */ - handle->sn_coap_tx_callback(dst_ack_packet_data_ptr, - dst_packed_data_needed_mem, src_addr_ptr, param); - -#if ENABLE_RESENDINGS - uint32_t resend_time = sn_coap_calculate_new_resend_time(handle->system_time, handle->sn_coap_resending_intervall, 0); - sn_coap_protocol_linked_list_send_msg_store(handle, src_addr_ptr, - dst_packed_data_needed_mem, - dst_ack_packet_data_ptr, - resend_time, param); -#endif - handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); - dst_ack_packet_data_ptr = 0; } - - //Last block received - else { - /* * * This is the last block when whole Blockwise payload from received * * */ - /* * * blockwise messages is gathered and returned to User * * */ - - /* Store last Blockwise payload to Linked list */ - uint16_t payload_len = 0; - uint8_t *payload_ptr = sn_coap_protocol_linked_list_blockwise_payload_search(handle, src_addr_ptr, &payload_len); - uint16_t whole_payload_len = sn_coap_protocol_linked_list_blockwise_payloads_get_len(handle, src_addr_ptr); - uint8_t *temp_whole_payload_ptr = NULL; - - temp_whole_payload_ptr = handle->sn_coap_protocol_malloc(whole_payload_len); - if (!temp_whole_payload_ptr) { - tr_error("sn_coap_handle_blockwise_message - (send block2) failed to allocate whole payload!"); - return 0; - } - - received_coap_msg_ptr->payload_ptr = temp_whole_payload_ptr; - received_coap_msg_ptr->payload_len = whole_payload_len; - - /* Copy stored Blockwise payloads to returned whole Blockwise payload pointer */ - while (payload_ptr != NULL) { - memcpy(temp_whole_payload_ptr, payload_ptr, payload_len); - - temp_whole_payload_ptr += payload_len; - - sn_coap_protocol_linked_list_blockwise_payload_remove_oldest(handle); - payload_ptr = sn_coap_protocol_linked_list_blockwise_payload_search(handle, src_addr_ptr, &payload_len); - } - received_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_BLOCKWISE_MSG_RECEIVED; - - //todo: remove previous msg from list - } - } //Now we send data to request @@ -2117,7 +2152,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn return received_coap_msg_ptr; } -static int8_t sn_coap_convert_block_size(uint16_t block_size) +int8_t sn_coap_convert_block_size(uint16_t block_size) { if (block_size == 16) { return 0; From 7566b814cd91f3080b3741df693f9a0f5a1f04ec Mon Sep 17 00:00:00 2001 From: Jani Suonpera Date: Thu, 18 Jan 2018 16:03:38 +0200 Subject: [PATCH 070/133] Update CoAP to 4.1.1 Combined CoAP changes 4.0.11 and 4.1.0 Fixed regression with 4.0.11 --- .../FEATURE_COMMON_PAL/mbed-coap/module.json | 2 +- .../mbed-coap/source/sn_coap_protocol.c | 46 +++++++++---------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/module.json b/features/FEATURE_COMMON_PAL/mbed-coap/module.json index 6255054aca..38599f15c3 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/module.json +++ b/features/FEATURE_COMMON_PAL/mbed-coap/module.json @@ -1,6 +1,6 @@ { "name": "mbed-coap", - "version": "4.1.0", + "version": "4.1.1", "description": "COAP library", "keywords": [ "coap", diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c index 86020085ab..5fd71f4c0c 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c @@ -1739,17 +1739,9 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn return NULL; } - // Response with COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE if the payload size is more than we can handle - - uint32_t max_size = SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE; if (!blocks_in_order) { tr_error("sn_coap_handle_blockwise_message - (recv block1) COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_INCOMPLETE!"); src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_INCOMPLETE; - } else if (received_coap_msg_ptr->options_list_ptr->size1 > max_size) { - // Include maximum size that stack can handle into response - tr_error("sn_coap_handle_blockwise_message - (recv block1) COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE!"); - src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; - src_coap_blockwise_ack_msg_ptr->options_list_ptr->size1 = max_size; } else if (received_coap_msg_ptr->msg_code == COAP_MSG_CODE_REQUEST_GET) { src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_CONTENT; } else if (received_coap_msg_ptr->msg_code == COAP_MSG_CODE_REQUEST_POST) { @@ -1760,23 +1752,31 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_DELETED; } - src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 = received_coap_msg_ptr->options_list_ptr->block1; - src_coap_blockwise_ack_msg_ptr->msg_type = COAP_MSG_TYPE_ACKNOWLEDGEMENT; - - /* Check block size */ - block_temp = (src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 & 0x07); - uint16_t block_size = 1u << (block_temp + 4); - if (block_size > handle->sn_coap_block_data_size) { - // Include maximum size that stack can handle into response - tr_error("sn_coap_handle_blockwise_message - (recv block1) COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE!"); - src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; - src_coap_blockwise_ack_msg_ptr->options_list_ptr->size1 = handle->sn_coap_block_data_size; - sn_coap_protocol_linked_list_blockwise_payload_remove_oldest(handle); + // Response with COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE if the payload size is more than we can handle + if (received_coap_msg_ptr->options_list_ptr->size1 > SN_COAP_MAX_INCOMING_BLOCK_MESSAGE_SIZE) { + // Include maximum size that stack can handle into response + tr_error("sn_coap_handle_blockwise_message - (recv block1) COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE!"); + src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; } + else { + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 = received_coap_msg_ptr->options_list_ptr->block1; + src_coap_blockwise_ack_msg_ptr->msg_type = COAP_MSG_TYPE_ACKNOWLEDGEMENT; - if (block_temp > sn_coap_convert_block_size(handle->sn_coap_block_data_size)) { - src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 &= 0xFFFFF8; - src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 |= sn_coap_convert_block_size(handle->sn_coap_block_data_size); + /* Check block size */ + block_temp = (src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 & 0x07); + uint16_t block_size = 1u << (block_temp + 4); + if (block_size > handle->sn_coap_block_data_size) { + // Include maximum size that stack can handle into response + tr_error("sn_coap_handle_blockwise_message - (recv block1) COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE!"); + src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; + src_coap_blockwise_ack_msg_ptr->options_list_ptr->size1 = handle->sn_coap_block_data_size; + sn_coap_protocol_linked_list_blockwise_payload_remove_oldest(handle); + } + + if (block_temp > sn_coap_convert_block_size(handle->sn_coap_block_data_size)) { + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 &= 0xFFFFF8; + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 |= sn_coap_convert_block_size(handle->sn_coap_block_data_size); + } } src_coap_blockwise_ack_msg_ptr->msg_id = received_coap_msg_ptr->msg_id; From 5cd5239047cce1202352db0cacc3dcf19157df2b Mon Sep 17 00:00:00 2001 From: Jani Suonpera Date: Mon, 22 Jan 2018 10:53:14 +0200 Subject: [PATCH 071/133] CHANGELOG updated --- features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md index 395463ff02..a80195d64d 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md +++ b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md @@ -1,5 +1,11 @@ # Change Log +## [v4.1.1](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.1.1) +**Closed issues:** +- IOTCLT-2203 mbed-coap does not handle PUT or POST if they indicate a smaller block size preference (fixed regression) + +-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.1.0...v4.1.1) + ## [v4.1.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.1.0) -[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.10...v4.1.0) From c4394af3343108e5fc6deb48093e606b6127c9df Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Mon, 8 Jan 2018 21:07:38 +0000 Subject: [PATCH 072/133] Adding MTB MXChip EMW3166 as a new target --- .../PeripheralNames.h | 79 +++++ .../PeripheralPins.c | 326 ++++++++++++++++++ .../TARGET_MTB_MXCHIP_EMW3166/PinNames.h | 267 ++++++++++++++ .../TARGET_MTB_MXCHIP_EMW3166/system_clock.c | 273 +++++++++++++++ targets/targets.json | 30 ++ 5 files changed, 975 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h new file mode 100644 index 0000000000..78bc359403 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PD_8 +#define STDIO_UART_RX PD_9 +#define STDIO_UART UART_3 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + FMPI2C_1 = (int)FMPI2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c new file mode 100644 index 0000000000..ad824e6498 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralPins.c @@ -0,0 +1,326 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - A0 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - LED1 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - A1 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - A3 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - A2 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - A4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - A5 + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { +// {PB_3, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PB_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, +// {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_10, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_FMPI2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PB_15, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PC_6, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PD_12, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, +// {PD_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, +// {PF_14, FMP_I, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N +// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 +// {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_9, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PB_14, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + +// {PF_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PF_4, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PF_5, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 +// {PF_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART3)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_SPI3)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_2, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, +// {PE_4, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_11, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h new file mode 100644 index 0000000000..c868d39bde --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h @@ -0,0 +1,267 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // Not connected + NC = (int)0xFFFFFFFF, + + //Module pins. + P_1 = NC, + P_2 = PB_2, + P_3 = NC, + P_4 = PB_15, + P_5 = PB_12, + P_6 = PB_13, + P_7 = PB_14, + P_8 = PC_6, + P_9 = PA_15, + P_10 = NC, + P_11 = NC, + P_12 = PC_7, + P_13 = NC, + P_14 = PC_0, + P_15 = NC, + P_16 = PC_13, + P_17 = PB_8, + P_18 = PB_9, + P_19 = PB_10, + P_20 = NC, + P_21 = NC, + P_22 = NC, + P_23 = NC, + P_24 = NC, + P_25 = PA_14, + P_26 = PA_13, + P_27 = PB_3, + P_28 = NC, + P_29 = PB_7, + P_30 = PB_6, + P_31 = PB_4, + P_32 = NC, + P_33 = PA_10, + P_34 = PA_5, + P_35 = PA_11, + P_36 = PA_12, + P_37 = PB_0, + P_38 = PA_4, + P_39 = NC, + P_40 = NC, + P_41 = NC, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + + // Generic signals namings + LED1 = PB_2, + LED2 = PB_10, + LED_RED = LED1, + LED_BLUE = LED2, + USER_BUTTON = PC_13, + + // Standardized button names + BUTTON1 = USER_BUTTON, + + SERIAL_TX = P_8, + SERIAL_RX = P_12, + + I2C_SCL = P_17, + I2C_SDA = P_18, + + SPI_MOSI = P_4, + SPI_MISO = P_7, + SPI_SCK = P_6, + SPI_CS = P_16, + + //DAPLink + USBRX = MBED_CONF_TARGET_USB_RX, + USBTX = MBED_CONF_TARGET_USB_TX, + SWDIO = P_26, + SWCLK = P_25, + NTRST = P_13, + + //MTB Aliases + //Left side (top view) + TGT_SWDIO = SWDIO, + TGT_SWCLK = SWCLK, + TGT_RESET = NTRST, + PB6 = P_30, + PB7 = P_29, + PC6 = SERIAL_TX, + PC7 = SERIAL_RX, + PB9 = I2C_SDA, + PB8 = I2C_SCL, + PB15 = SPI_MOSI, + PB14 = SPI_MISO, + PB13 = SPI_SCK, + PC13 = SPI_CS, + PC0 = P_14, + PA4 = P_38, + PA5 = P_34, + PB0 = P_37, + + //Right side (top view) + GND = NC, + PA11 = P_35, + PA12 = P_36, + PB4 = P_31, //CS for LCD + PB3 = P_27, //RESET for LCD + PA15 = P_9, //A0 for LCD + PA10 = P_33, + PB12 = P_5, + PB10 = LED2, + PB2 = LED1, + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c new file mode 100644 index 0000000000..a804597c5d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c @@ -0,0 +1,273 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 + * AHBCLK (MHz) | 100 + * APB1CLK (MHz) | 50 + * APB2CLK (MHz) | 100 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "nvic_addr.h" +#include "mbed_assert.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + uint8_t ret_HSIclk_status = SetSysClock_PLL_HSI(); + if (ret_HSIclk_status == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 200 MHz (1 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 100; // VCO output clock = 200 MHz (2 MHz * 100) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 100 MHz (200 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/targets.json b/targets/targets.json index adf96948c5..86877d7b1f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1078,6 +1078,36 @@ "device_name": "STM32F412ZG", "bootloader_supported": true }, + "MTB_MXCHIP_EMW3166": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG"], + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "device_has_add": ["CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], + "release_versions": ["2", "5"], + "device_name": "STM32F412ZG", + "bootloader_supported": true, + "config": { + "usb_tx": { + "help": "Value PB_6", + "value": "PB_6" + }, + "usb_rx": { + "help": "Value PB_7", + "value": "PB_7" + }, + "stdio_uart": { + "help": "Value: UART_1", + "value": "UART_1", + "macro_name": "STDIO_UART" + }, + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "value": "USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + } + } + }, "DISCO_F413ZH": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], From 51207deeffff4a8d68d097e0504706a245a1c8cf Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 19 Dec 2017 16:36:48 +0100 Subject: [PATCH 073/133] BL STM32746xG: Update scatter/link files --- .../device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct | 15 ++++++++++++--- .../device/TOOLCHAIN_ARM_STD/stm32f746xg.sct | 15 ++++++++++++--- .../device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld | 11 ++++++++++- .../device/TOOLCHAIN_IAR/stm32f746xg.icf | 9 ++++++--- 4 files changed, 40 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct index cb52146d47..897c962691 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) -LR_IROM1 0x08000000 0x100000 { ; load region size_region +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif - ER_IROM1 0x08000000 0x100000 { ; load address = execution address +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct index cb52146d47..897c962691 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) -LR_IROM1 0x08000000 0x100000 { ; load region size_region +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif - ER_IROM1 0x08000000 0x100000 { ; load address = execution address +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld index 198ac5c584..59c032d568 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld @@ -1,7 +1,16 @@ /* Linker script to configure memory regions. */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 1024K +#endif + MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM (rwx) : ORIGIN = 0x200001C8, LENGTH = 320K - 0x1C8 } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf index 99918b9898..4d8dfcaa4a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf @@ -1,7 +1,10 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } + /* [ROM = 1024kb = 0x100000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x080FFFFF; +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 320kb = 0x50000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; From 03b264c269504483d6a8f544d84f7f51721aa66e Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 19 Dec 2017 16:39:14 +0100 Subject: [PATCH 074/133] BL NUCLEO_F746ZG: enable bootloader --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 86877d7b1f..dfd87681b4 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1294,7 +1294,8 @@ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], - "device_name": "STM32F746ZG" + "device_name": "STM32F746ZG", + "bootloader_supported": true }, "NUCLEO_F756ZG": { "inherits": ["FAMILY_STM32"], From 00003cdc47a7beb4c90c19febc423760fa693938 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 8 Jan 2018 10:32:54 +0100 Subject: [PATCH 075/133] BL NUCLEO_F746ZG: change scb->vector assignment --- .../TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c index 12d4d52adc..613d4da059 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c @@ -30,6 +30,7 @@ **/ #include "stm32f7xx.h" +#include "nvic_addr.h" #include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -92,7 +93,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ #endif } From b89be917fde952879d955e3c664d189157f7821b Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 9 Jan 2018 17:06:48 +0100 Subject: [PATCH 076/133] Check cache before enabling it The mbed_sdk_init can be called either during cold boot or during application boot after bootloader has been executed. In case the bootloader has already enabled the cache, is is needed to not enable it again. --- targets/TARGET_STM/mbed_overrides.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index fbdccb8c5f..8df4ff2958 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -35,9 +35,16 @@ void mbed_sdk_init() HAL_Init(); #if TARGET_STM32F7 - // Enable CPU L1-Cache - SCB_EnableICache(); - SCB_EnableDCache(); + // The mbed_sdk_init can be called either during cold boot or during + // application boot after bootloader has been executed. + // In case the bootloader has already enabled the cache, + // is is needed to not enable it again. + if (SCB->CCR & (uint32_t)SCB_CCR_IC_Msk == 0) { // If ICache is disabled + SCB_EnableICache(); + } + if (SCB->CCR & (uint32_t)SCB_CCR_DC_Msk == 0) { // If DCache is disabled + SCB_EnableDCache(); + } #endif /* TARGET_STM32F7 */ /* Configure the System clock source, PLL Multiplier and Divider factors, From 248db987bc219f8853702d0cd919099e92e0e049 Mon Sep 17 00:00:00 2001 From: bcostm Date: Wed, 10 Jan 2018 10:01:56 +0100 Subject: [PATCH 077/133] NUCLEO_F767ZI: Add bootloader support --- .../TARGET_NUCLEO_F767ZI/system_clock.c | 3 ++- .../device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct | 15 ++++++++++++--- .../device/TOOLCHAIN_ARM_STD/stm32f767xi.sct | 15 ++++++++++++--- .../device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld | 11 ++++++++++- .../device/TOOLCHAIN_IAR/stm32f767xi.icf | 9 ++++++--- targets/targets.json | 3 ++- 6 files changed, 44 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c index 9e6db0524a..fdb245e65b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c @@ -30,6 +30,7 @@ **/ #include "stm32f7xx.h" +#include "nvic_addr.h" #include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -92,7 +93,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ #endif } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct index aaa6ed8f35..0534eeee59 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) -LR_IROM1 0x08000000 0x200000 { ; load region size_region +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif - ER_IROM1 0x08000000 0x200000 { ; load address = execution address +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + +; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct index aaa6ed8f35..0534eeee59 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) -LR_IROM1 0x08000000 0x200000 { ; load region size_region +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif - ER_IROM1 0x08000000 0x200000 { ; load address = execution address +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + +; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld index 359b884aee..e75663eb18 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld @@ -1,7 +1,16 @@ /* Linker script to configure memory regions. */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 2048K +#endif + MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM (rwx) : ORIGIN = 0x200001F8, LENGTH = 512K - 0x1F8 } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf index 1c73fc150d..40316b8e54 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf @@ -1,7 +1,10 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; } + /* [ROM = 2048kb = 0x200000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x081FFFFF; +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM = 512kb = 0x80000] Vector table dynamic copy: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; diff --git a/targets/targets.json b/targets/targets.json index dfd87681b4..4ec5655a28 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1351,7 +1351,8 @@ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], - "device_name": "STM32F767ZI" + "device_name": "STM32F767ZI", + "bootloader_supported": true }, "NUCLEO_L011K4": { "inherits": ["FAMILY_STM32"], From 1d0354d1ab6c0dbc26d6c1d93442894ffadf09a5 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 18 Jan 2018 17:48:06 +0100 Subject: [PATCH 078/133] STM32LX : HAL_RCC_OscConfig update in PLL configuration check PLL settings before retuuning error --- .../TARGET_STM32L0/device/stm32l0xx_hal_rcc.c | 14 +++++++++- .../TARGET_STM32L1/device/stm32l1xx_hal_rcc.c | 15 +++++++++-- .../TARGET_STM32L4/device/stm32l4xx_hal_rcc.c | 26 ++++++++++++++++++- 3 files changed, 51 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c index 91bff130e3..cf1597aa1b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.c @@ -709,7 +709,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - return HAL_ERROR; + /* MBED patch - ST internal ticket 42806 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) { + return HAL_ERROR; + } + /* MBED patch - ST internal ticket 42806 */ } } return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c index 4217e0bd16..c9c8f0e020 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c @@ -713,10 +713,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - return HAL_ERROR; + /* MBED patch - ST internal ticket 42806 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) { + return HAL_ERROR; + } + /* MBED patch - ST internal ticket 42806 */ } } - return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c index 222237da3d..4835c433d3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c @@ -803,7 +803,31 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - return HAL_ERROR; + /* MBED patch - ST internal ticket 42806 */ + if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR) { + return HAL_ERROR; + } + /* MBED patch - ST internal ticket 42806 */ } } return HAL_OK; From dd9dd9bbed5281a173ac260cdf2455409e1d7588 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cruz=20Monrreal=20II=C2=89?= Date: Mon, 22 Jan 2018 14:46:44 -0600 Subject: [PATCH 079/133] Removed RTC as a supported peripheral for NCS36510 --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 4ec5655a28..45480ba47b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3522,7 +3522,7 @@ "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"}, "macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"], "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], - "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG", "SPISLAVE"], + "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG", "SPISLAVE"], "release_versions": ["2", "5"] }, "NUMAKER_PFM_M453": { From 4ea39124ff98ece764062655736687336f0c2adc Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 22 Jan 2018 15:43:50 +0100 Subject: [PATCH 080/133] STM32: fix serial 7bit data format --- targets/TARGET_STM/serial_api.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index 29050a5b7c..27072730ff 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -474,11 +474,17 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b } switch (data_bits) { - case 9: - MBED_ASSERT(parity == UART_PARITY_NONE); - obj_s->databits = UART_WORDLENGTH_9B; + case 7: + if (parity != UART_PARITY_NONE) { + obj_s->databits = UART_WORDLENGTH_8B; + } else { +#if defined UART_WORDLENGTH_7B + obj_s->databits = UART_WORDLENGTH_7B; +#else + error("7-bit data format without parity is not supported"); +#endif + } break; - default: case 8: if (parity != UART_PARITY_NONE) { obj_s->databits = UART_WORDLENGTH_9B; @@ -486,15 +492,16 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b obj_s->databits = UART_WORDLENGTH_8B; } break; -#if defined UART_WORDLENGTH_7B - case 7: + case 9: if (parity != UART_PARITY_NONE) { - obj_s->databits = UART_WORDLENGTH_8B; + error("Parity is not supported with 9-bit data format"); } else { - obj_s->databits = UART_WORDLENGTH_7B; + obj_s->databits = UART_WORDLENGTH_9B; } break; -#endif + default: + error("Only 7, 8 or 9-bit data formats are supported"); + break; } if (stop_bits == 2) { From 9da55ffd57cd85245fceda61800b9b7bfd7ccb69 Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Fri, 19 Jan 2018 13:49:25 +0000 Subject: [PATCH 081/133] RZ_A1H: cmsis nvic include fix To get cmsis nvic definitions, this header file should be included in cmsis.h file. Fixes #5886 --- targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h index 0f9a540cdd..5d8b03f68f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h @@ -8,5 +8,6 @@ #define MBED_CMSIS_H #include "MBRZA1H.h" +#include "cmsis_nvic.h" #endif From c95ef84da6bbf7e7f1526333a6610202a369a0c9 Mon Sep 17 00:00:00 2001 From: adustm Date: Fri, 12 Jan 2018 15:49:27 +0100 Subject: [PATCH 082/133] Improve SRAM use for IAR toolchain Use the entire SRAM2 with NVIC buffer + stack Increase HEAP size to 0x10000 in SRAM1 Increase the available SRAM1 by 0x2000 --- .../device/TOOLCHAIN_IAR/stm32l475xx.icf | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf index 15c4254b3f..84020a40d9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf @@ -21,12 +21,11 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__]; define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; -/* Stack 1/8 and Heap 1/4 of RAM */ -define symbol __size_cstack__ = 0x8000; -define symbol __size_heap__ = 0xa000; +/* Stack complete SRAM2 and Heap 2/3 of SRAM1 */ +define symbol __size_cstack__ = 0x7e00; +define symbol __size_heap__ = 0x10000; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; initialize by copy with packing = zeros { readwrite }; do not initialize { section .noinit }; @@ -34,5 +33,5 @@ do not initialize { section .noinit }; place at address mem:__intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in SRAM1_region { readwrite, block STACKHEAP }; -place in SRAM2_region { }; +place in SRAM1_region { readwrite, block HEAP }; +place in SRAM2_region { block CSTACK }; From 33d2548d240c96b6d2facdb448f95760f42fad2c Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 23 Jan 2018 12:41:35 +0100 Subject: [PATCH 083/133] STM32F407 : correct ARM scatter file Alignment with STM32Cube_FW_F4_V1.18.0 done --- .../device/TOOLCHAIN_ARM_MICRO/STM32F407.sct | 17 ----- .../TOOLCHAIN_ARM_MICRO/STM32F407xx.sct | 18 +++++ ...rtup_STM32F40x.S => startup_STM32F407xx.S} | 72 ++++++++++++------- .../device/TOOLCHAIN_ARM_STD/STM32F407.sct | 17 ----- .../device/TOOLCHAIN_ARM_STD/STM32F407xx.sct | 18 +++++ ...rtup_STM32F40x.S => startup_STM32F407xx.S} | 72 ++++++++++++------- 6 files changed, 128 insertions(+), 86 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407.sct create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/{startup_STM32F40x.S => startup_STM32F407xx.S} (84%) delete mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407.sct create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct rename targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/{startup_STM32F40x.S => startup_STM32F407xx.S} (84%) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407.sct deleted file mode 100644 index acffd8ae00..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407.sct +++ /dev/null @@ -1,17 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00100000 { ; load region size_region - ER_IROM1 0x08000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x10000000 0x00010000 { ; CCM - } - RW_IRAM2 0x20000188 0x0001FE78 { - .ANY (+RW +ZI) - } -} - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct new file mode 100644 index 0000000000..7930116a81 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct @@ -0,0 +1,18 @@ +; ***************************************** +; *** Scatter-Loading Description File *** +; ***************************************** + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000188 0x0001FE78 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x10000000 0x00010000 { ; CCM + .ANY (CCMRAM) + } +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F40x.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F407xx.S similarity index 84% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F40x.S rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F407xx.S index 7de08f9a5b..9c458c8407 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F40x.S +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/startup_STM32F407xx.S @@ -1,23 +1,41 @@ -;/***************************************************************************** -; * @file: startup_STM32F40x.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the ST STM32F40x Device Series -; * @version: V1.20 -; * @date: 16. January 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M4 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs @@ -56,6 +74,8 @@ __heap_limit EQU (__initial_sp - Stack_Size) AREA RESET, DATA, READONLY EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler @@ -122,7 +142,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC + DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 @@ -153,10 +173,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD 0 ; Reserved DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY @@ -268,7 +290,7 @@ Default_Handler PROC EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] @@ -299,7 +321,6 @@ Default_Handler PROC EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] @@ -351,7 +372,7 @@ TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler -FSMC_IRQHandler +FMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler @@ -382,7 +403,6 @@ OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler -CRYP_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407.sct deleted file mode 100644 index acffd8ae00..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407.sct +++ /dev/null @@ -1,17 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00100000 { ; load region size_region - ER_IROM1 0x08000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x10000000 0x00010000 { ; CCM - } - RW_IRAM2 0x20000188 0x0001FE78 { - .ANY (+RW +ZI) - } -} - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct new file mode 100644 index 0000000000..7930116a81 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/STM32F407xx.sct @@ -0,0 +1,18 @@ +; ***************************************** +; *** Scatter-Loading Description File *** +; ***************************************** + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000188 0x0001FE78 { + .ANY (+RW +ZI) + } + RW_IRAM2 0x10000000 0x00010000 { ; CCM + .ANY (CCMRAM) + } +} + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F40x.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F407xx.S similarity index 84% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F40x.S rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F407xx.S index 3a5d312e4b..fd60b26061 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F40x.S +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_STD/startup_STM32F407xx.S @@ -1,23 +1,41 @@ -;/***************************************************************************** -; * @file: startup_STM32F40x.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * for the ST STM32F40x Device Series -; * @version: V1.20 -; * @date: 16. January 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M4 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* @@ -30,6 +48,8 @@ __initial_sp EQU 0x20020000 ; Top of RAM AREA RESET, DATA, READONLY EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler @@ -96,7 +116,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC + DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 @@ -127,10 +147,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD 0 ; Reserved DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY @@ -242,7 +264,7 @@ Default_Handler PROC EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] @@ -273,7 +295,6 @@ Default_Handler PROC EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] @@ -325,7 +346,7 @@ TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler -FSMC_IRQHandler +FMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler @@ -356,7 +377,6 @@ OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler -CRYP_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler From e7b7bea320fa9bb193c00c834a1f9ed0a44f41cd Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Thu, 25 Jan 2018 11:07:01 +0000 Subject: [PATCH 084/133] Revert "STM32F7: Add bootloader support" --- .../TARGET_NUCLEO_F746ZG/system_clock.c | 3 +-- .../device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct | 13 ++----------- .../device/TOOLCHAIN_ARM_STD/stm32f746xg.sct | 13 ++----------- .../device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld | 11 +---------- .../device/TOOLCHAIN_IAR/stm32f746xg.icf | 9 +++------ .../TARGET_NUCLEO_F767ZI/system_clock.c | 3 +-- .../device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct | 13 ++----------- .../device/TOOLCHAIN_ARM_STD/stm32f767xi.sct | 13 ++----------- .../device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld | 11 +---------- .../device/TOOLCHAIN_IAR/stm32f767xi.icf | 9 +++------ targets/TARGET_STM/mbed_overrides.c | 13 +++---------- targets/targets.json | 6 ++---- 12 files changed, 23 insertions(+), 94 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c index 613d4da059..12d4d52adc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c @@ -30,7 +30,6 @@ **/ #include "stm32f7xx.h" -#include "nvic_addr.h" #include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -93,7 +92,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct index 897c962691..cb52146d47 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO/stm32f746xg.sct @@ -1,4 +1,3 @@ -#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -28,18 +27,10 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x100000 -#endif - ; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region +LR_IROM1 0x08000000 0x100000 { ; load region size_region - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + ER_IROM1 0x08000000 0x100000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct index 897c962691..cb52146d47 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct @@ -1,4 +1,3 @@ -#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -28,18 +27,10 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x100000 -#endif - ; STM32F746NG: 1024 KB FLASH (0x100000) + 320 KB SRAM (0x50000) -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region +LR_IROM1 0x08000000 0x100000 { ; load region size_region - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + ER_IROM1 0x08000000 0x100000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld index 59c032d568..198ac5c584 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_GCC_ARM/STM32F746xG.ld @@ -1,16 +1,7 @@ /* Linker script to configure memory regions. */ - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 1024K -#endif - MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K RAM (rwx) : ORIGIN = 0x200001C8, LENGTH = 320K - 0x1C8 } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf index 4d8dfcaa4a..99918b9898 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_IAR/stm32f746xg.icf @@ -1,10 +1,7 @@ -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } - /* [ROM = 1024kb = 0x100000] */ -define symbol __intvec_start__ = MBED_APP_START; -define symbol __region_ROM_start__ = MBED_APP_START; -define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x080FFFFF; /* [RAM = 320kb = 0x50000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c index fdb245e65b..9e6db0524a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c @@ -30,7 +30,6 @@ **/ #include "stm32f7xx.h" -#include "nvic_addr.h" #include "mbed_assert.h" /*!< Uncomment the following line if you need to relocate your vector Table in @@ -93,7 +92,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct index 0534eeee59..aaa6ed8f35 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/stm32f767xi.sct @@ -1,4 +1,3 @@ -#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -28,18 +27,10 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x200000 -#endif - ; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region +LR_IROM1 0x08000000 0x200000 { ; load region size_region - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + ER_IROM1 0x08000000 0x200000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct index 0534eeee59..aaa6ed8f35 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct @@ -1,4 +1,3 @@ -#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2016, STMicroelectronics @@ -28,18 +27,10 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x200000 -#endif - ; STM32F767ZI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000) -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region +LR_IROM1 0x08000000 0x200000 { ; load region size_region - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + ER_IROM1 0x08000000 0x200000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld index e75663eb18..359b884aee 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/STM32F767xI.ld @@ -1,16 +1,7 @@ /* Linker script to configure memory regions. */ - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 2048K -#endif - MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K RAM (rwx) : ORIGIN = 0x200001F8, LENGTH = 512K - 0x1F8 } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf index 40316b8e54..1c73fc150d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_IAR/stm32f767xi.icf @@ -1,10 +1,7 @@ -if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; } - /* [ROM = 2048kb = 0x200000] */ -define symbol __intvec_start__ = MBED_APP_START; -define symbol __region_ROM_start__ = MBED_APP_START; -define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x081FFFFF; /* [RAM = 512kb = 0x80000] Vector table dynamic copy: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 8df4ff2958..fbdccb8c5f 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -35,16 +35,9 @@ void mbed_sdk_init() HAL_Init(); #if TARGET_STM32F7 - // The mbed_sdk_init can be called either during cold boot or during - // application boot after bootloader has been executed. - // In case the bootloader has already enabled the cache, - // is is needed to not enable it again. - if (SCB->CCR & (uint32_t)SCB_CCR_IC_Msk == 0) { // If ICache is disabled - SCB_EnableICache(); - } - if (SCB->CCR & (uint32_t)SCB_CCR_DC_Msk == 0) { // If DCache is disabled - SCB_EnableDCache(); - } + // Enable CPU L1-Cache + SCB_EnableICache(); + SCB_EnableDCache(); #endif /* TARGET_STM32F7 */ /* Configure the System clock source, PLL Multiplier and Divider factors, diff --git a/targets/targets.json b/targets/targets.json index 45480ba47b..3552deb09e 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1294,8 +1294,7 @@ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], - "device_name": "STM32F746ZG", - "bootloader_supported": true + "device_name": "STM32F746ZG" }, "NUCLEO_F756ZG": { "inherits": ["FAMILY_STM32"], @@ -1351,8 +1350,7 @@ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], - "device_name": "STM32F767ZI", - "bootloader_supported": true + "device_name": "STM32F767ZI" }, "NUCLEO_L011K4": { "inherits": ["FAMILY_STM32"], From 7b7f9b4b43fbaebfdb2d18c1f75241f8ec4cf857 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 24 Jan 2018 11:48:38 -0600 Subject: [PATCH 085/133] Update CMSIS pack Signed-off-by: Mahesh Mahadevan --- tools/arm_pack_manager/aliases.json | 2 +- tools/arm_pack_manager/index.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/arm_pack_manager/aliases.json b/tools/arm_pack_manager/aliases.json index 557a37f6b1..6c7443852e 100644 --- a/tools/arm_pack_manager/aliases.json +++ b/tools/arm_pack_manager/aliases.json @@ -1 +1 @@ -{"nRF51 PCA10028": "nRF51422_xxAC", "SAM4L-EK": "ATSAM4LC4C", "Apollo1 EVB": "APOLLO512-KBR", "NuTiny-SDK-M451": "M453VG6AE", "NuTiny-SDK-M0518": "M0518SD2AE", "STM32L073Z-EVAL": "STM32L073VZ", "TLE9879 EvalKit": "TLE9879QXA40", "STM32F401C-Discovery": "STM32F401VC", "NuTiny-SDK-M051": "M0516LDE", "Z32F0640100KITG": "Z32F06410AES", "SAMD51-XPRO": "ATSAMD51P20A", "NuTiny-SDK-NANO112": "NANO112VC2AN", "XMC4500 Relax Kit": "XMC4500-F100x1024", "TWR-K22F120M": "MK22FN512xxx12", "MCB1200": "LPC1227FBD64/301", "DB-MAX71637": "MAX71637", "XMC 2Go": "XMC1100-Q024x0064", "STM32H743I-EVAL": "STM32H743XI", "NUCLEO-L152RE": "STM32L152RE", "TWR-KV10Z32": "MKV10Z32xxx7", "XMC4800 Automation Board": "XMC4800-E196x2048", "FRDM-KW40Z": "MKW40Z160xxx4", "NuTiny-SDK-NM1200": "NM1200LBAE", "TWR-K70F120M": "MK70FN1M0xxx12", "STM32F769I-Discovery": "STM32F769NIHx", "TWR-KE18F": "MKE18F512xxx16", "MCBSTM32F400": "STM32F407IG", "SAML21-XPRO": "ATSAML21J18A", "STM32F030-Discovery": "STM32F030R8", "SAMA5D2-XULT": "ATSAMA5D27", "Apollo EVK": "APOLLO512-KBR", "NuTiny-SDK-NUC505": "NUC505YO13Y", "NuTiny-SDK-M058S": "M058SSAN", "TRK-KEA8": "SKEAZN8xxx4", "MCB1700": "LPC1758", "V2M-MPS2": "CMSDK_CM7", "MCB54110": "LPC54114J256BD64", "LPC1788-32 Developers Kit": "LPC1788", "Z32F1280100KITG": "Z32F12811ARS", "NuTiny-SDK-NUC472": "NUC472HI8AE", "EFM32GG-DK3750": "EFM32GG990F1024", "Colibri-VF50": "MVF50NN15xxxx40", "MCBSTM32F200": "STM32F207IG", "EVAL-ADuCM322EBZ": "ADuCM322", "FRDM-KL25Z": "MKL25Z128xxx4", "SN32F707B Starter Kit Rev1_0": "SN32F70*B", "NUCLEO-F446RE": "STM32F446RE", "NuTiny-SDK-NANO103": "NANO103SD3AE", "MCBNUC1xx": "NUC140VE3AN", "MCB11C14": "LPC11C14FBD48/301", "FRDM-KL02Z": "MKL02Z32xxx4", "Colibri-iMX7": "MCIMX7D7", "NuTiny-SDK-Mini55": "Mini54XZAE", "NuTiny-SDK-Mini57": "Mini57TDE", "SAM3S-EK": "ATSAM3S4C", "SF2_DEV_KIT": "M2S050", "NuTiny-SDK-NANO100BN": "NANO130KE3BN", "NuTiny-SDK-Mini58": "Mini58LDE", "uVision Simulator": "ARMCM0", "FRDM-K28F": "MK28FN2M0xxx15", "TRK-KEA64": "SKEAZN64xxx2", "XMC1200 Boot Kit": "XMC1201-T038x0200", "N5 Starter Kit": "nRF51422_xxAA", "Core031C_Board": "MM32x031", "EFM32HG-SLSTK3400A": "EFM32HG322F64", "EVAL-ADuCM320EBZ": "ADuCM320", "ADSP-CM419F EZ-BOARD M4": "ADSP-CM419F-BCZ_M4", "NOVPEK-iMX7": "MCIMX7D7", "XMC4700 Relax Kit": "XMC4700-F144x2048", "SAMG55-XPRO": "ATSAMG55J19", "Fixed Virtual Platform": "ARMCA5", "SAMHA1G16A-XPRO": "ATSAMHA1G16A", "FRDM-KE06Z": "MKE06Z128xxx4", "NUCLEO-F072RB": "STM32F072RB", "NuTiny-SDK-NUC100": "NUC100VE3DN", "MCBTMPM360": "TMPM362F10FG", "NuTiny-SDK-NUC121": "NUC121SC2AE", "NuTiny-SDK-NUC029AE": "NUC029FAE", "NuTiny-SDK-M0564": "M0564VG4AE", "V2M-MPS2 (IoT)": "IOTKit_ARMv8MML", "ADuCM4050 EZ-KIT": "ADuCM4050", "FRDM-K20D50M": "MK20DX128xxx5", "STM32756G-EVAL": "STM32F756NGHx", "SAM4L-XPRO": "ATSAM4LC4C", "FRDM-KL43Z": "MKL43Z256xxx4", "nRF52 PCA10036": "nRF52832_xxAA", "TWR-KV11Z75M": "MKV11Z128xxx7", "NuTiny-SDK-NUC029AN": "NUC029TAN", "TWR-VF65GS10": "MVF61NS15xxxx50", "TWR-KM34Z50": "MKM34Z128xxx5", "STM32L-Discovery": "STM32L152RB", "AC30M1464 MINI B/D": "AC30M1464", "IMX7-PHYBOARD-ZETA": "MCIMX7D7", "XMC1100 Boot Kit": "XMC1100-T038x0064", "TWR-KV46F150M": "MKV46F256xxx16", "Koala EVM": "STM32F429II", "EFM32WG-STK3800": "EFM32WG990F256", "MCB1313": "LPC1313FBD48", "NuTiny-SDK-M480": "M487JIDAE", "TWR-K65F180M": "MK65FN2M0xxx18", "EB_TMPM369FDFG": "TMPM369FDFG", "TS-R-IN32M3-EC": "R-IN32M3-EC", "XMC4300 Relax Kit": "XMC4300-F100x256", "LPCXpresso54114": "LPC54114J256BD64", "STM32F429I-Discovery": "STM32F429ZI", "Colibri-VF61": "MVF61NN15xxxx50", "NUCLEO-F091RC": "STM32F091RC", "SAMV71-XULTRA": "ATSAMV71Q21", "FRDM-KW41Z": "MKW41Z512xxx4", "TWR-KL43Z48M": "MKL43Z256xxx4", "STM32373C-EVAL": "STM32F373VC", "QN908XDK": "QN9080A", "STM32F746G-Discovery": "STM32F746NGHx", "TWR-K24F120M": "MK24FN256xxx12", "nRF52 PCA10040": "nRF52832_xxAA", "MCBSTM32C": "STM32F107VC", "FRDM-KL03Z": "MKL03Z32xxx4", "MCBSTM32E": "STM32F103ZG", "NUCLEO-F401RE": "STM32F401RE", "SF2_EVAL_KIT": "M2S025", "STM32303C-EVAL": "STM32F303VC", "AC33MA384A MINI B/D": "AC33MA384A", "SAML22-XPRO": "ATSAML22N18A", "XMC4800 Relax EtherCAT Kit": "XMC4800-F144x2048", "iMX7-Dual-COM": "MCIMX7D7", "TRK-KEA128": "SKEAZ128xxx4", "SAM4S-EK": "SAM4S16C", "TWR-K20D50M": "MK20DX128xxx5", "STM32F3-Discovery": "STM32F303VC", "LPCXpresso1125": "LPC1125JBD48/303", "STM32F4-Discovery": "STM32F407VG", "CMSIS_RTOS_Tutorial": "STM32F103RB", "SAM3X-EK": "ATSAM3X8H", "SF2_ADV_DEV_KIT": "M2S150", "SN32F760 Starter Kit Rev1_1": "SN32F76*", "Core103R_Board": "MM32x103", "NuTiny-SDK-Mini51": "Mini54LDE", "Apollo2 EVB": "AMAPH1KK-KBR", "FRDM-KE04Z": "MKE04Z8xxx4", "NuTiny-SDK-NUC123": "NUC123SD4AN0", "TWR-KL28Z72M": "MKL28Z512xxx7", "Apollo2 EVK": "AMAPH1KK-KBR", "LPC4330-Xplorer": "LPC4330", "NuTiny-SDK-NUC126": "NUC126VG4AE", "MCBTMPM330": "TMPM330FDFG", "NUCLEO-L476RG": "STM32L476RG", "STM32F334-Discovery": "STM32F334C8", "MCB1800": "LPC1850", "EFM32GG-STK3700": "EFM32GG990F1024", "GD32150C-START": "GD32F150C8", "AC33GA256 MINI B/D": "AC33GA256", "TS-R-IN32M3-CL": "R-IN32M3-CL", "TS-R-IN32M3-CEC": "R-IN32M3-EC", "EVAL-ADuCM320iQSPZ": "ADuCM320i", "AC33M8128/6128 MINI B/D": "AC33M8128", "SAM4S-XPRO": "ATSAM4SD32C", "STM32L053-Discovery": "STM32L053C8", "TWR-KM34Z50MV3": "MKM34Z128Axxx5", "PAC52XX EVK": "PAC52XX", "XMC4500 CPU Board - General Purpose (CPU_45A)": "XMC4500-F144x1024", "NuTiny-SDK-NUC122": "NUC122SD2AN", "Z32F3840100KITG": "Z32F38412ALS", "LPCXpresso54608": "LPC54608J512BD208", "MCIMX7ULP-EVK": "MCIMX7U5", "LPC824 LPCXpresso": "LPC824M201JHI33", "STM32439I-EVAL": "STM32F439NI", "EFM32TG-STK3300": "EFM32TG840F32", "AC33M4064/3064 MINI B/D": "AC33M4064", "NUCLEO-F030R8": "STM32F030R8", "NuTiny-SDK-NUC131": "NUC131SD2AE", "DK-TM4C129x": "TM4C129XNCZAD", "STM32F769I-EVAL": "STM32F769NIHx", "SF2_STARTER_KIT": "M2S010", "nRF51 PCA20006": "nRF51822_xxaa", "TS-R-IN32M4-CL2": "R-IN32M4-CL2", "MCIMX6SX-SABRE": "MCIMX6X1", "EVAL-ADICUP3029": "ADuCM3029", "SAM4C-EK": "ATSAM4C16C", "MCB1500": "LPC1549JBD100", "TWR-KW21D256": "MKW21D256xxx5", "STM32L476G-EVAL": "STM32L476ZG", "MCIMX7D-SABRE": "MCIMX7D7", "STM32F051-Discovery": "STM32F051R8", "NUCLEO-L053R8": "STM32L053R8", "FRDM-K64F": "MK64FN1M0VLL12", "TLE9869 EvalKit": "TLE9869QXA20", "NuTiny-SDK-NUC240": "NUC240VE3AE", "LPC84x LPCXpresso": "LPC845M301JBD64", "S32K144-EVB": "S32K144UAT0xxxx", "SAMD20-XPRO": "ATSAMD20J18", "SN32F770 Starter Kit Rev1_0": "SN32F70*B", "SAM4E-EK": "SAM4E16C", "MCB1343": "LPC1343FBD48", "LinkIt 7687 development board": "MT7687F", "XMC4500 CPU Board - General Purpose (CPU_45B)": "XMC4500-E144x1024", "SAM3N-EK": "ATSAM3N4C", "LinkIt 2523 development board": "MT2523x", "SAM3U-EK": "ATSAM3U4E", "ADSP-CM419F EZ-BOARD M0": "ADSP-CM419F-BCZ_M0", "ADuCM3029 EZ-KIT": "ADuCM3029", "NuTiny-SDK-NUC200": "NUC220VE3AN", "FRDM-KL82Z": "MKL81Z128xxx7", "XMC1300 Boot Kit": "XMC1302-T038x0200", "Bulb Board": "S6E1A12B0A", "MCBTMPM395": "TMPM395FWAXBG", "STM32F072-Discovery": "STM32F072RB", "BMSKTOPASM369": "TMPM369FDFG", "LPCXpresso54102": "LPC54102J512BD64", "NuTiny-SDK-NANO100AN": "NANO100VD3AN", "TWR-K60D100M": "MK60DN512xxx10", "TWR-K20D72M": "MK20DX256xxx7", "nRF51 PCA10031": "nRF51422_xxAC", "EK-TM4C1294XL": "TM4C1294NCPDT", "SK-FM3-176PMC-ETHERNET": "MB9BFD18T", "LPC4088-32 Developers Kit": "LPC4088FET208", "FRDM-KW36": "MKW36A512xxx4", "TLE984x Eval.Board": "TLE9844QX", "XMC4500 Relax Lite Kit": "XMC4500-F100x1024", "iMX6-SoloX-COM": "MCIMX6X4", "SAME70-XPLD": "ATSAME70Q21", "LPCXpresso11U68": "LPC11U68JBD100", "XMC4400 CPU Board - General Purpose (CPU_44A)": "XMC4400-F100x512", "NUCLEO-F103RB": "STM32F103RB", "EFM32ZG-STK3200": "EFM32ZG222F32", "XMC1400 Boot Kit": "XMC1402-Q040x0128", "MCBTWRK60": "MK60DN512xxx10", "MCB9B500": "MB9BF506R", "Z32F0642100KITG": "Z32F06423AKE", "ADSP-CM419F EZ-BOARD": "ADSP-CM419F", "LPC812 LPCXpresso": "LPC812M101JDH20", "TWR-KL82Z72M": "MKL82Z128xxx7", "SN32F100 Starter Kit": "SN32F10*", "NuTiny-SDK-M0519": "M0519VE3AE", "TWR-K64F120M": "MK64FN1M0xxx12", "MCB4300": "LPC4350", "XMC4200 CPU Board - Actuator (CPU_42A)": "XMC4200-F64x256", "EVAL-ADuCM360MKZ": "ADuCM360"} \ No newline at end of file +{"nRF51 PCA10028": "nRF51422_xxAC", "SAM4L-EK": "ATSAM4LC4C", "Apollo1 EVB": "APOLLO512-KBR", "NuTiny-SDK-M451": "M453VG6AE", "NuTiny-SDK-M0518": "M0518SD2AE", "STM32L073Z-EVAL": "STM32L073VZ", "TLE9879 EvalKit": "TLE9879QXA40", "STM32F401C-Discovery": "STM32F401VC", "NuTiny-SDK-M051": "M0516LDE", "TWR-K21D50M": "MK21DN512Axxx5", "MCB11C14": "LPC11C14FBD48/301", "TWR-K21F120M": "MK21FN1M0Axxx12", "STM32303E-EVAL": "STM32F303VE", "SAMD51-XPRO": "ATSAMD51P20A", "XMC4500 Relax Kit": "XMC4500-F100x1024", "TWR-K22F120M": "MK22FN512xxx12", "MCB1200": "LPC1227FBD64/301", "DB-MAX71637": "MAX71637", "XMC 2Go": "XMC1100-Q024x0064", "EFM32TG-STK3300": "EFM32TG840F32", "STM32H743I-EVAL": "STM32H743XI", "V2M-MPS3 (IoT)": "IOTKit_CM33_MPS3", "NUCLEO-L152RE": "STM32L152RE", "Colibri-VF61": "MVF61NN15xxxx50", "V2M-MPS2 (IoT)": "IOTKit_ARMv8MML", "FRDM-KW40Z": "MKW40Z160xxx4", "NuTiny-SDK-NM1200": "NM1200LBAE", "TWR-K70F120M": "MK70FN1M0xxx12", "STM32F769I-Discovery": "STM32F769NIHx", "HVP-KV46F150M": "MKV46F256xxx16", "S32K148-EVB": "S32K148UAxxxLQx", "MCBSTM32F400": "STM32F407IG", "SAML21-XPRO": "ATSAML21J18A", "AC33M4064/3064 MINI B/D": "AC33M4064", "SAMA5D2-XULT": "ATSAMA5D27", "Apollo EVK": "APOLLO512-KBR", "NuTiny-SDK-NUC505": "NUC505YO13Y", "NuTiny-SDK-M058S": "M058SSAN", "TRK-KEA8": "SKEAZN8xxx4", "NUCLEO-F446RE": "STM32F446RE", "Z32F0642100KITG": "Z32F06423AKE", "MCB54110": "LPC54114J256BD64", "STM32L496G-Discovery": "STM32L496AGIx", "NuTiny-SDK-NANO112": "NANO112VC2AN", "Z32F1280100KITG": "Z32F12811ARS", "NuTiny-SDK-NUC472": "NUC472HI8AE", "EFM32GG-DK3750": "EFM32GG990F1024", "Colibri-VF50": "MVF50NN15xxxx40", "MCBSTM32F200": "STM32F207IG", "FRDM-KL46Z": "MKL46Z256xxx4", "HVP-KV58F": "MKV58F1M0xxx24", "EVAL-ADuCM322EBZ": "ADuCM322", "MCBTMPM360": "TMPM362F10FG", "TWR-VF65GS10": "MVF61NS15xxxx50", "NuTiny-SDK-NANO103": "NANO103SD3AE", "MCBNUC1xx": "NUC140VE3AN", "Z32F0640100KITG": "Z32F06410AES", "LPCXpresso54114": "LPC54114J256", "Colibri-iMX7": "MCIMX7D7", "NuTiny-SDK-Mini55": "Mini54XZAE", "NuTiny-SDK-Mini57": "Mini57TDE", "FRDM-KE15Z": "MKE15Z256xxx7", "NuTiny-SDK-Mini51": "Mini54LDE", "NuTiny-SDK-NANO100BN": "NANO130KE3BN", "NuTiny-SDK-Mini58": "Mini58LDE", "XMC1400 Boot Kit": "XMC1402-Q040x0128", "FRDM-K28F": "MK28FN2M0xxx15", "NuTiny-SDK-NUC131": "NUC131SD2AE", "TRK-KEA64": "SKEAZN64xxx2", "SAM3N-EK": "ATSAM3N4C", "XMC1200 Boot Kit": "XMC1201-T038x0200", "N5 Starter Kit": "nRF51422_xxAA", "Core031C_Board": "MM32x031", "EFM32HG-SLSTK3400A": "EFM32HG322F64", "EVAL-ADuCM320EBZ": "ADuCM320", "ADSP-CM419F EZ-BOARD M4": "ADSP-CM419F-BCZ_M4", "XMC4700 Relax Kit": "XMC4700-F144x2048", "SAMG55-XPRO": "ATSAMG55J19", "Fixed Virtual Platform": "ARMCA5", "SAMHA1G16A-XPRO": "ATSAMHA1G16A", "FRDM-KE06Z": "MKE06Z128xxx4", "NUCLEO-F072RB": "STM32F072RB", "HVP-KV11Z75M": "MKV11Z128xxx7", "MCB1700": "LPC1758", "MCBTWRK60": "MK60DN512xxx10", "FRDM-K32W042": "K32W042S1M2xxx", "HVP-KV31F120M": "MKV31F512xxx12", "NuTiny-SDK-NUC029AE": "NUC029FAE", "NuTiny-SDK-M0564": "M0564VG4AE", "EV-COG-AD4050LZ": "ADuCM4x50", "FRDM-K20D50M": "MK20DX128xxx5", "STM32756G-EVAL": "STM32F756NGHx", "SAM4L-XPRO": "ATSAM4LC4C", "FRDM-KL43Z": "MKL43Z256xxx4", "nRF52 PCA10036": "nRF52832_xxAA", "TWR-KV11Z75M": "MKV11Z128xxx7", "NuTiny-SDK-NUC029AN": "NUC029TAN", "LPCXpresso54102": "LPC54102J512", "FRDM-KL02Z": "MKL02Z32xxx4", "XMC4800 Automation Board": "XMC4800-E196x2048", "STM32L-Discovery": "STM32L152RB", "IMX7-PHYBOARD-ZETA": "MCIMX7D7", "XMC1100 Boot Kit": "XMC1100-T038x0064", "TWR-KV46F150M": "MKV46F256xxx16", "Koala EVM": "STM32F429II", "EFM32WG-STK3800": "EFM32WG990F256", "MCB1313": "LPC1313FBD48", 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"SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S6110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}} From acfdaca56a026caca5b8c4ceacbedbd3e4e7ee5e Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 25 Jan 2018 15:46:36 +0100 Subject: [PATCH 086/133] MTB_XX : STDIO configuration Here is a proposition - to align with other STM32 - and to remove compilation warnings : [Warning] PeripheralNames.h@38,0: "STDIO_UART" redefined --- .../PeripheralNames.h | 4 ---- .../TARGET_MTB_MTS_DRAGONFLY/PinNames.h | 21 +++++++++++++++++-- .../PeripheralNames.h | 4 ---- .../TARGET_MTB_MXCHIP_EMW3166/PinNames.h | 20 ++++++++++++++++-- targets/targets.json | 20 +++++------------- 5 files changed, 42 insertions(+), 27 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h index 15a5c2bc7a..697d107c41 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PeripheralNames.h @@ -46,10 +46,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PB_6 -#define STDIO_UART_RX PB_7 -#define STDIO_UART UART_1 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h index 941228cae4..e9ee25c4e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h @@ -145,9 +145,26 @@ typedef enum { P_39 = PA_13, P_40 = PB_7, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = PB_6, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = PB_7, +#endif + //DAPLink - USBTX = MBED_CONF_TARGET_USB_TX, - USBRX = MBED_CONF_TARGET_USB_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, SWDIO = PA_13, SWCLK = PA_14, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h index 78bc359403..c85180daf4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PeripheralNames.h @@ -33,10 +33,6 @@ typedef enum { UART_6 = (int)USART6_BASE } UARTName; -#define STDIO_UART_TX PD_8 -#define STDIO_UART_RX PD_9 -#define STDIO_UART UART_3 - typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h index c868d39bde..3f31b59516 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h @@ -219,9 +219,25 @@ typedef enum { SPI_SCK = P_6, SPI_CS = P_16, + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = PB_6, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = PB_7, +#endif //DAPLink - USBRX = MBED_CONF_TARGET_USB_RX, - USBTX = MBED_CONF_TARGET_USB_TX, + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, SWDIO = P_26, SWCLK = P_25, NTRST = P_13, diff --git a/targets/targets.json b/targets/targets.json index 3552deb09e..8dfeb0f2f7 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1088,19 +1088,14 @@ "device_name": "STM32F412ZG", "bootloader_supported": true, "config": { - "usb_tx": { + "stdio_uart_tx": { "help": "Value PB_6", "value": "PB_6" }, - "usb_rx": { + "stdio_uart_rx": { "help": "Value PB_7", "value": "PB_7" }, - "stdio_uart": { - "help": "Value: UART_1", - "value": "UART_1", - "macro_name": "STDIO_UART" - }, "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSI", @@ -1889,19 +1884,14 @@ "value": 1, "macro_name": "MODEM_ON_BOARD_UART" }, - "usb_tx": { + "stdio_uart_tx": { "help": "Value PB_6", "value": "PB_6" }, - "usb_rx": { + "stdio_uart_rx": { "help": "Value PB_7", "value": "PB_7" - }, - "stdio_uart": { - "help": "Value: UART_1", - "value": "UART_1", - "macro_name": "STDIO_UART" - } + } }, "overrides": { "lse_available": 0 From 5651aa22da20b6a8bda1378413b494692818a332 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 25 Jan 2018 12:00:34 +0100 Subject: [PATCH 087/133] NUCLEO_F401RE : PeripheralPins file update Default SERIAL pins are now available for ADC and PWM when STDIO_UART_TX and STDIO_UART_RX are user defined https://os.mbed.com/teams/ST/wiki/STDIO Alternative pins have been also defined --- .../TARGET_NUCLEO_F401RE/PeripheralPins.c | 87 ++++++++++--------- .../TARGET_NUCLEO_F401RE/PinNames.h | 25 +++++- 2 files changed, 69 insertions(+), 43 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c index f25904562c..cf963a4e70 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,19 +30,35 @@ #include "PeripheralPins.h" -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: some pins are connected to the default STDIO_UART_TX and STDIO_UART_RX pins. +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== //*** ADC *** const PinMap PinMap_ADC[] = { {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 -// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // SERIAL_TX -// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // SERIAL_RX +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 +#endif {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 @@ -86,22 +102,25 @@ const PinMap PinMap_I2C_SCL[] = { //*** PWM *** -// TIM5 cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // TIM5 used by the us_ticker {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX -// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX -// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX -// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // TIM5 used by the us_ticker +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + {PA_2_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // TIM5 used by the us_ticker + {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + {PA_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // TIM5 used by the us_ticker + {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 +#endif {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 @@ -109,18 +128,18 @@ const PinMap PinMap_PWM[] = { {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_8_ALT0, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_9_ALT0, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N @@ -137,7 +156,7 @@ const PinMap PinMap_PWM[] = { //*** SERIAL *** const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX (default) {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, @@ -146,7 +165,7 @@ const PinMap PinMap_UART_TX[] = { }; const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX (default) {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, @@ -157,22 +176,12 @@ const PinMap PinMap_UART_RX[] = { const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - // {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - // {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs - // {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, - // {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - // {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 {NC, NC, 0} }; const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - // {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - // {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - // {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, - // {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - // {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 {NC, NC, 0} }; @@ -181,7 +190,7 @@ const PinMap PinMap_UART_CTS[] = { const PinMap PinMap_SPI_MOSI[] = { {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, @@ -191,7 +200,7 @@ const PinMap PinMap_SPI_MOSI[] = { const PinMap PinMap_SPI_MISO[] = { {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, @@ -201,7 +210,7 @@ const PinMap PinMap_SPI_MISO[] = { const PinMap PinMap_SPI_SCLK[] = { {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, @@ -210,9 +219,9 @@ const PinMap PinMap_SPI_SCLK[] = { const PinMap PinMap_SPI_SSEL[] = { {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, -// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, -// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {NC, NC, 0} diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h index c89ff31a0f..b581d5dbcf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h @@ -37,15 +37,24 @@ extern "C" { #endif +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200 +} ALTx; + typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -54,17 +63,25 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + PA_15_ALT0 = PA_15|ALT0, PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, PB_2 = 0x12, PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, + PB_8_ALT0 = PB_8|ALT0, PB_9 = 0x19, + PB_9_ALT0 = PB_9|ALT0, PB_10 = 0x1A, PB_12 = 0x1C, PB_13 = 0x1D, @@ -85,13 +102,13 @@ typedef enum { PC_11 = 0x2B, PC_12 = 0x2C, PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, + PC_14 = 0x2E, // Connected to RCC_OSC32_IN + PC_15 = 0x2F, // Connected to RCC_OSC32_OUT PD_2 = 0x32, - PH_0 = 0x70, - PH_1 = 0x71, + PH_0 = 0x70, // Connected to RCC_OSC_IN + PH_1 = 0x71, // Connected to RCC_OSC_OUT // ADC internal channels ADC_TEMP = 0xF0, From 1e5295b17c1a6e98748d5d0caed6ca59efefd6b0 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Wed, 24 Jan 2018 18:27:47 -0600 Subject: [PATCH 088/133] littlefs: Set specific hash for littlefs-fuse testing --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 40d81b43e7..4a038b3a0a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -127,6 +127,7 @@ matrix: before_script: # Setup and patch littlefs-fuse - git clone https://github.com/geky/littlefs-fuse littlefs_fuse + - git -C littlefs_fuse checkout 3f1ed6e37799e49e3710830dc6abb926d5503cf2 - echo '*' > littlefs_fuse/.mbedignore - rm -rf littlefs_fuse/littlefs/* - cp -r $(git ls-tree --name-only HEAD $LITTLEFS/littlefs/) littlefs_fuse/littlefs From a5598df4d77aef0f7ac3775b867ef74ad9910bec Mon Sep 17 00:00:00 2001 From: bcostm Date: Wed, 24 Jan 2018 14:45:18 +0100 Subject: [PATCH 089/133] Use RawSerial in MBED_11 test --- features/unsupported/tests/mbed/ticker/main.cpp | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/features/unsupported/tests/mbed/ticker/main.cpp b/features/unsupported/tests/mbed/ticker/main.cpp index fc1ed9ca30..c41fff20c0 100644 --- a/features/unsupported/tests/mbed/ticker/main.cpp +++ b/features/unsupported/tests/mbed/ticker/main.cpp @@ -1,11 +1,7 @@ #include "mbed.h" #include "test_env.h" -void print_char(char c = '*') -{ - printf("%c", c); - fflush(stdout); -} +RawSerial pc(USBTX, USBRX); Ticker flipper_1; DigitalOut led1(LED1); @@ -17,7 +13,7 @@ void flip_1() { } else { led1 = 1; led1_state = 1; } - print_char(); + pc.putc('*'); } Ticker flipper_2; From 52c7fe5167c73a06e74213610cf19914c1945865 Mon Sep 17 00:00:00 2001 From: Serge Camille Date: Wed, 24 Jan 2018 13:29:43 +0100 Subject: [PATCH 090/133] NXP LPC4088: Add missing SPI SSEL pin to Pinmap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Pin P5_3 (p31) was missing from the NXP LPC4088 SPI PinMap for SSEL. Adding this Pin allows usage of SPISlave with SSP2 using the SSEL pin. The pin and its SSP2_SSEL function is both documented in https://os.mbed.com/media/uploads/embeddedartists/lpc4088_qsb_pinning.xlsx as well as in UM10562 LPC408x/407x User manual Rev. 3 — 12 March 2014 chapter 7.4.1.4 Table 90 (https://www.nxp.com/docs/en/user-guide/UM10562.pdf). --- targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c index 6a71a44046..9fdf2331db 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c @@ -69,6 +69,7 @@ static const PinMap PinMap_SPI_SSEL[] = { {P1_28, SPI_0, 5}, {P2_23, SPI_0, 2}, {P4_21, SPI_1, 3}, + {P5_3, SPI_2, 2}, {NC , NC , 0} }; From c0b4f0c8dd7585a2ffd3dd98bd423c06ff62b2b6 Mon Sep 17 00:00:00 2001 From: PHST Date: Wed, 24 Jan 2018 08:20:38 +0100 Subject: [PATCH 091/133] Add missing EFM32 HAL flash init/deinit function calls --- targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c index 6e8fa3b229..307664bb98 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c @@ -35,6 +35,7 @@ int32_t flash_init(flash_t *obj) { (void)obj; + MSC_Init(); return 0; } @@ -46,6 +47,7 @@ int32_t flash_init(flash_t *obj) int32_t flash_free(flash_t *obj) { (void)obj; + MSC_Deinit(); return 0; } From e0882e1931e4a7a6fd4ce0050d4f92b40bad842a Mon Sep 17 00:00:00 2001 From: Michael Kaplan Date: Wed, 24 Jan 2018 08:10:35 +0100 Subject: [PATCH 092/133] CriticalSectionLock: fixing missing include Macro MBED_DEPRECATED_SINCE is defined in platform/mbed_toolchain.h which was not included. If someone used member functions lock or unlock (which are prefixed with MBED_DEPRECATED_SINCE since some time), there would be a compile error instead of a warning. Including mbed_toolchain.h fixes that. --- platform/CriticalSectionLock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/platform/CriticalSectionLock.h b/platform/CriticalSectionLock.h index cb619769c8..65baa879ab 100644 --- a/platform/CriticalSectionLock.h +++ b/platform/CriticalSectionLock.h @@ -19,6 +19,7 @@ #define MBED_CRITICALSECTIONLOCK_H #include "platform/mbed_critical.h" +#include "platform/mbed_toolchain.h" namespace mbed { From f047a93066198e221aa01fb16adcb2a20618e8b5 Mon Sep 17 00:00:00 2001 From: drewcassidy Date: Tue, 23 Jan 2018 19:19:43 -0800 Subject: [PATCH 093/133] fix typos in lint.py --- tools/targets/lint.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/targets/lint.py b/tools/targets/lint.py index 0202d45a31..826bbb56b8 100644 --- a/tools/targets/lint.py +++ b/tools/targets/lint.py @@ -163,7 +163,7 @@ BOARD_FORMAT_STRING = {1: "Board (%s)", def _generate_hierarchy_string(mcus, boards): global_errors = [] if len(mcus) < 1: - global_errors.append("No MCUS found in heirarchy") + global_errors.append("No MCUS found in hierarchy") mcus_string = "??? ->" elif len(mcus) > 3: global_errors.append("No name for targets %s" % ", ".join(mcus[3:])) @@ -174,7 +174,7 @@ def _generate_hierarchy_string(mcus, boards): mcus_string = MCU_FORMAT_STRING[len(mcus)] % tuple(mcus) if len(boards) < 1: - global_errors.append("no boards found in heirarchy") + global_errors.append("no boards found in hierarchy") boards_string = "???" elif len(boards) > 2: global_errors.append("no name for targets %s" % ", ".join(boards[2:])) @@ -187,7 +187,7 @@ def _generate_hierarchy_string(mcus, boards): def check_hierarchy(tgt): - """Atempts to assign labels to the heirarchy""" + """Atempts to assign labels to the hierarchy""" resolution_order = copy(tgt.resolution_order_names[:-1]) mcus, boards = _split_boards(resolution_order, tgt) From d5523167bf9fda3eca018eee86fee282a67dedbe Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 23 Jan 2018 15:18:14 +0100 Subject: [PATCH 094/133] STM32F0: fix usart irq management --- .../TARGET_STM/TARGET_STM32F0/serial_device.c | 141 +++++++++--------- 1 file changed, 71 insertions(+), 70 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 2ea47faeb3..060b114a21 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -87,47 +87,46 @@ static void uart2_irq(void) } #endif -#if defined USART3_BASE -static void uart3_irq(void) +// Used for both USART3_4_IRQn and USART3_8_IRQn +static void uart3_8_irq(void) { - uart_irq(2); -} +#if defined(USART3_BASE) + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) + { + uart_irq(2); + } #endif - -#if defined USART4_BASE -static void uart4_irq(void) -{ - uart_irq(3); -} +#if defined(USART4_BASE) + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART4) != RESET) + { + uart_irq(3); + } #endif - -#if defined USART5_BASE -static void uart5_irq(void) -{ - uart_irq(4); -} +#if defined(USART5_BASE) + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART5) != RESET) + { + uart_irq(4); + } #endif - -#if defined USART6_BASE -static void uart6_irq(void) -{ - uart_irq(5); -} +#if defined(USART6_BASE) + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART6) != RESET) + { + uart_irq(5); + } #endif - -#if defined USART7_BASE -static void uart7_irq(void) -{ - uart_irq(6); -} +#if defined(USART7_BASE) + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART7) != RESET) + { + uart_irq(6); + } #endif - -#if defined USART8_BASE -static void uart8_irq(void) -{ - uart_irq(7); -} +#if defined(USART8_BASE) + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART8) != RESET) + { + uart_irq(7); + } #endif +} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { @@ -156,53 +155,55 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) } #endif -#if defined (TARGET_STM32F091RC) - if (obj_s->uart == UART_3) { - irq_n = USART3_8_IRQn; - vector = (uint32_t)&uart3_irq; - } - - if (obj_s->uart == UART_4) { - irq_n = USART3_8_IRQn; - vector = (uint32_t)&uart4_irq; - } - - if (obj_s->uart == UART_5) { - irq_n = USART3_8_IRQn; - vector = (uint32_t)&uart5_irq; - } - - if (obj_s->uart == UART_6) { - irq_n = USART3_8_IRQn; - vector = (uint32_t)&uart6_irq; - } - - if (obj_s->uart == UART_7) { - irq_n = USART3_8_IRQn; - vector = (uint32_t)&uart7_irq; - } - - if (obj_s->uart == UART_8) { - irq_n = USART3_8_IRQn; - vector = (uint32_t)&uart8_irq; - } - -#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) - -#else #if defined(USART3_BASE) if (obj_s->uart == UART_3) { +#if defined(TARGET_STM32F091RC) + irq_n = USART3_8_IRQn; +#else irq_n = USART3_4_IRQn; - vector = (uint32_t)&uart3_irq; +#endif + vector = (uint32_t)&uart3_8_irq; } #endif #if defined(USART4_BASE) if (obj_s->uart == UART_4) { +#if defined(TARGET_STM32F091RC) + irq_n = USART3_8_IRQn; +#else irq_n = USART3_4_IRQn; - vector = (uint32_t)&uart4_irq; +#endif + vector = (uint32_t)&uart3_8_irq; } #endif + +// Below usart are available only on TARGET_STM32F091RC +#if defined(USART5_BASE) + if (obj_s->uart == UART_5) { + irq_n = USART3_8_IRQn; + vector = (uint32_t)&uart3_8_irq; + } +#endif + +#if defined(USART6_BASE) + if (obj_s->uart == UART_6) { + irq_n = USART3_8_IRQn; + vector = (uint32_t)&uart3_8_irq; + } +#endif + +#if defined(USART7_BASE) + if (obj_s->uart == UART_7) { + irq_n = USART3_8_IRQn; + vector = (uint32_t)&uart3_8_irq; + } +#endif + +#if defined(USART8_BASE) + if (obj_s->uart == UART_8) { + irq_n = USART3_8_IRQn; + vector = (uint32_t)&uart3_8_irq; + } #endif if (enable) { From 2538f9d000b35ba4c407e910d2f3e32fdf7964f9 Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 23 Jan 2018 17:34:16 +0100 Subject: [PATCH 095/133] STM32F0 usart irq: fix issue with F070/F072 --- .../TARGET_STM/TARGET_STM32F0/serial_device.c | 34 +++++++++++-------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 060b114a21..45ace51592 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -51,28 +51,34 @@ static uart_irq_handler irq_handler; * INTERRUPTS HANDLING ******************************************************************************/ -static void uart_irq(int id) +static uint32_t uart_irq(int id) { UART_HandleTypeDef * huart = &uart_handlers[id]; - + uint32_t status = 0; + if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) { irq_handler(serial_irq_ids[id], TxIrq); + status = 1; } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) { irq_handler(serial_irq_ids[id], RxIrq); /* Flag has been cleared when reading the content */ + status = 1; } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + status = 1; } } } + + return status; } static void uart1_irq(void) @@ -90,42 +96,42 @@ static void uart2_irq(void) // Used for both USART3_4_IRQn and USART3_8_IRQn static void uart3_8_irq(void) { +#if defined(TARGET_STM32F091RC) #if defined(USART3_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) - { + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) { uart_irq(2); } #endif #if defined(USART4_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART4) != RESET) - { + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART4) != RESET) { uart_irq(3); } #endif #if defined(USART5_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART5) != RESET) - { + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART5) != RESET) { uart_irq(4); } #endif #if defined(USART6_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART6) != RESET) - { + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART6) != RESET) { uart_irq(5); } #endif #if defined(USART7_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART7) != RESET) - { + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART7) != RESET) { uart_irq(6); } #endif #if defined(USART8_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART8) != RESET) - { + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART8) != RESET) { uart_irq(7); } #endif +#else // TARGET_STM32F070RB, TARGET_STM32F072RB + if (uart_irq(2) == 0) { // Check if it's USART3 + uart_irq(3); // Otherwise it's USART4 + } +#endif } void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) From 2c0daf8e1f776177716a5327ada03885ccbc166d Mon Sep 17 00:00:00 2001 From: bcostm Date: Wed, 24 Jan 2018 09:52:41 +0100 Subject: [PATCH 096/133] STM32F0: manage better uart3 & 4 irqs Manage the case where both uart3 and uart4 interrupts are arriving at the same time. --- .../TARGET_STM/TARGET_STM32F0/serial_device.c | 20 ++++++++----------- 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 45ace51592..62955239bc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -51,34 +51,27 @@ static uart_irq_handler irq_handler; * INTERRUPTS HANDLING ******************************************************************************/ -static uint32_t uart_irq(int id) +static void uart_irq(int id) { UART_HandleTypeDef * huart = &uart_handlers[id]; - uint32_t status = 0; - if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) { irq_handler(serial_irq_ids[id], TxIrq); - status = 1; } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) { irq_handler(serial_irq_ids[id], RxIrq); - /* Flag has been cleared when reading the content */ - status = 1; + /* Flag has been cleared when reading the content */ } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - status = 1; } } } - - return status; } static void uart1_irq(void) @@ -128,9 +121,12 @@ static void uart3_8_irq(void) } #endif #else // TARGET_STM32F070RB, TARGET_STM32F072RB - if (uart_irq(2) == 0) { // Check if it's USART3 - uart_irq(3); // Otherwise it's USART4 - } +#if defined(USART3_BASE) + uart_irq(2); +#endif +#if defined(USART4_BASE) + uart_irq(3); +#endif #endif } From 96227a861db077707d507bc1196274acf48431ff Mon Sep 17 00:00:00 2001 From: bcostm Date: Thu, 25 Jan 2018 11:23:53 +0100 Subject: [PATCH 097/133] STM32F0 uart irq: test IT flags for usart3/4 --- targets/TARGET_STM/TARGET_STM32F0/serial_device.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 62955239bc..733021e725 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -122,10 +122,14 @@ static void uart3_8_irq(void) #endif #else // TARGET_STM32F070RB, TARGET_STM32F072RB #if defined(USART3_BASE) - uart_irq(2); + if (USART3->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) { + uart_irq(2); + } #endif #if defined(USART4_BASE) - uart_irq(3); + if (USART4->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) { + uart_irq(3); + } #endif #endif } From 3205901e99095f275ee2868ab637e63380642895 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Mon, 4 Dec 2017 10:39:14 -0600 Subject: [PATCH 098/133] Fix local static initialization in USB The local static initialization in USB was causing multiple problems: -Configurable descriptor values are set only once -USB descriptor initialization causes a trap in debug builds since this is acquiring a mutex in an interrupt handler -Extra ram used since all descriptors are in RAM This patch fixes these problems by making fixed descriptors static const so they are stored in flash and never need to be initialized and by making descriptors that do change a member of the class so they are always initialized when requested rather than once though lazy static local initialization. --- .../USBDevice/USBAudio/USBAudio.cpp | 24 +++++---- .../unsupported/USBDevice/USBAudio/USBAudio.h | 20 ++++++-- .../USBDevice/USBDevice/USBDevice.cpp | 50 ++++++++++--------- .../USBDevice/USBDevice/USBDevice.h | 19 +++---- .../unsupported/USBDevice/USBHID/USBHID.cpp | 22 ++++---- .../unsupported/USBDevice/USBHID/USBHID.h | 10 ++-- .../USBDevice/USBHID/USBKeyboard.cpp | 10 ++-- .../USBDevice/USBHID/USBKeyboard.h | 5 +- .../unsupported/USBDevice/USBHID/USBMouse.cpp | 12 +++-- .../unsupported/USBDevice/USBHID/USBMouse.h | 5 +- .../USBDevice/USBHID/USBMouseKeyboard.cpp | 6 +-- .../USBDevice/USBHID/USBMouseKeyboard.h | 2 +- .../unsupported/USBDevice/USBMIDI/USBMIDI.cpp | 12 ++--- .../unsupported/USBDevice/USBMIDI/USBMIDI.h | 6 +-- .../unsupported/USBDevice/USBMSD/USBMSD.cpp | 12 ++--- .../unsupported/USBDevice/USBMSD/USBMSD.h | 6 +-- .../USBDevice/USBSerial/USBCDC.cpp | 18 ++++--- .../unsupported/USBDevice/USBSerial/USBCDC.h | 8 +-- 18 files changed, 142 insertions(+), 105 deletions(-) diff --git a/features/unsupported/USBDevice/USBAudio/USBAudio.cpp b/features/unsupported/USBDevice/USBAudio/USBAudio.cpp index fba5ead9d6..ce1f70c25a 100644 --- a/features/unsupported/USBDevice/USBAudio/USBAudio.cpp +++ b/features/unsupported/USBDevice/USBAudio/USBAudio.cpp @@ -56,6 +56,8 @@ USBAudio::USBAudio(uint32_t frequency_in, uint8_t channel_nb_in, uint32_t freque volume = 0; + _build_configurationDesc(); + // connect the device USBDevice::connect(); } @@ -377,8 +379,8 @@ void USBAudio::USBCallback_requestCompleted(uint8_t * buf, uint32_t length) { FEATURE_UNIT_DESCRIPTOR_LENGTH + \ 2*OUTPUT_TERMINAL_DESCRIPTOR_LENGTH) -uint8_t * USBAudio::configurationDesc() { - static uint8_t configDescriptor[] = { +void USBAudio::_build_configurationDesc() { + uint8_t configDescriptorTemp[] = { // Configuration 1 CONFIGURATION_DESCRIPTOR_LENGTH, // bLength CONFIGURATION_DESCRIPTOR, // bDescriptorType @@ -615,15 +617,19 @@ uint8_t * USBAudio::configurationDesc() { 0x00, // bLockDelayUnits LSB(0x0000), // wLockDelay MSB(0x0000), // wLockDelay - - // Terminator - 0 // bLength }; + + MBED_ASSERT(sizeof(configDescriptorTemp) == sizeof(configDescriptor)); + memcpy(configDescriptor, configDescriptorTemp, sizeof(configDescriptor)); +} + +const uint8_t * USBAudio::configurationDesc() { + return configDescriptor; } -uint8_t * USBAudio::stringIinterfaceDesc() { - static uint8_t stringIinterfaceDescriptor[] = { +const uint8_t * USBAudio::stringIinterfaceDesc() { + static const uint8_t stringIinterfaceDescriptor[] = { 0x0c, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'A',0,'u',0,'d',0,'i',0,'o',0 //bString iInterface - Audio @@ -631,8 +637,8 @@ uint8_t * USBAudio::stringIinterfaceDesc() { return stringIinterfaceDescriptor; } -uint8_t * USBAudio::stringIproductDesc() { - static uint8_t stringIproductDescriptor[] = { +const uint8_t * USBAudio::stringIproductDesc() { + static const uint8_t stringIproductDescriptor[] = { 0x16, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'M',0,'b',0,'e',0,'d',0,' ',0,'A',0,'u',0,'d',0,'i',0,'o',0 //bString iProduct - Mbed Audio diff --git a/features/unsupported/USBDevice/USBAudio/USBAudio.h b/features/unsupported/USBDevice/USBAudio/USBAudio.h index 14ee29125b..f1bdbe6d48 100644 --- a/features/unsupported/USBDevice/USBAudio/USBAudio.h +++ b/features/unsupported/USBDevice/USBAudio/USBAudio.h @@ -216,21 +216,21 @@ protected: * * @returns pointer to the string product descriptor */ - virtual uint8_t * stringIproductDesc(); + virtual const uint8_t * stringIproductDesc(); /* * Get string interface descriptor * * @returns pointer to the string interface descriptor */ - virtual uint8_t * stringIinterfaceDesc(); + virtual const uint8_t * stringIinterfaceDesc(); /* * Get configuration descriptor * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(); + virtual const uint8_t * configurationDesc(); /* * Called by USBDevice layer. Set interface/alternate of the device. @@ -270,6 +270,20 @@ protected: private: + /* + * Call to rebuild the configuration descriptor + * + * This function should be called on creation or when any + * value that is part of the configuration descriptor + * changes. + * @note This function uses ~200 bytes of stack so + * make sure your stack is big enough for it. + */ + void _build_configurationDesc(); + + // configuration descriptor + uint8_t configDescriptor[183]; + // stream available ? volatile bool available; diff --git a/features/unsupported/USBDevice/USBDevice/USBDevice.cpp b/features/unsupported/USBDevice/USBDevice/USBDevice.cpp index 7ec03f2579..438174fe2a 100644 --- a/features/unsupported/USBDevice/USBDevice/USBDevice.cpp +++ b/features/unsupported/USBDevice/USBDevice/USBDevice.cpp @@ -58,7 +58,7 @@ bool USBDevice::requestGetDescriptor(void) printf("device descr\r\n"); #endif transfer.remaining = DEVICE_DESCRIPTOR_LENGTH; - transfer.ptr = deviceDesc(); + transfer.ptr = (uint8_t*)deviceDesc(); transfer.direction = DEVICE_TO_HOST; success = true; } @@ -77,7 +77,7 @@ bool USBDevice::requestGetDescriptor(void) transfer.remaining = configurationDesc()[2] \ | (configurationDesc()[3] << 8); - transfer.ptr = configurationDesc(); + transfer.ptr = (uint8_t*)configurationDesc(); transfer.direction = DEVICE_TO_HOST; success = true; } @@ -94,7 +94,7 @@ bool USBDevice::requestGetDescriptor(void) printf("1\r\n"); #endif transfer.remaining = stringLangidDesc()[0]; - transfer.ptr = stringLangidDesc(); + transfer.ptr = (uint8_t*)stringLangidDesc(); transfer.direction = DEVICE_TO_HOST; success = true; break; @@ -103,7 +103,7 @@ bool USBDevice::requestGetDescriptor(void) printf("2\r\n"); #endif transfer.remaining = stringImanufacturerDesc()[0]; - transfer.ptr = stringImanufacturerDesc(); + transfer.ptr = (uint8_t*)stringImanufacturerDesc(); transfer.direction = DEVICE_TO_HOST; success = true; break; @@ -112,7 +112,7 @@ bool USBDevice::requestGetDescriptor(void) printf("3\r\n"); #endif transfer.remaining = stringIproductDesc()[0]; - transfer.ptr = stringIproductDesc(); + transfer.ptr = (uint8_t*)stringIproductDesc(); transfer.direction = DEVICE_TO_HOST; success = true; break; @@ -121,7 +121,7 @@ bool USBDevice::requestGetDescriptor(void) printf("4\r\n"); #endif transfer.remaining = stringIserialDesc()[0]; - transfer.ptr = stringIserialDesc(); + transfer.ptr = (uint8_t*)stringIserialDesc(); transfer.direction = DEVICE_TO_HOST; success = true; break; @@ -130,7 +130,7 @@ bool USBDevice::requestGetDescriptor(void) printf("5\r\n"); #endif transfer.remaining = stringIConfigurationDesc()[0]; - transfer.ptr = stringIConfigurationDesc(); + transfer.ptr = (uint8_t*)stringIConfigurationDesc(); transfer.direction = DEVICE_TO_HOST; success = true; break; @@ -139,7 +139,7 @@ bool USBDevice::requestGetDescriptor(void) printf("6\r\n"); #endif transfer.remaining = stringIinterfaceDesc()[0]; - transfer.ptr = stringIinterfaceDesc(); + transfer.ptr = (uint8_t*)stringIinterfaceDesc(); transfer.direction = DEVICE_TO_HOST; success = true; break; @@ -771,7 +771,7 @@ uint8_t * USBDevice::findDescriptor(uint8_t descriptorType) } /* Start at first descriptor after the configuration descriptor */ - ptr = &(configurationDesc()[CONFIGURATION_DESCRIPTOR_LENGTH]); + ptr = &(((uint8_t*)configurationDesc())[CONFIGURATION_DESCRIPTOR_LENGTH]); do { if (ptr[1] /* bDescriptorType */ == descriptorType) @@ -907,8 +907,8 @@ bool USBDevice::readEP_NB(uint8_t endpoint, uint8_t * buffer, uint32_t * size, u -uint8_t * USBDevice::deviceDesc() { - static uint8_t deviceDescriptor[] = { +const uint8_t * USBDevice::deviceDesc() { + uint8_t deviceDescriptorTemp[] = { DEVICE_DESCRIPTOR_LENGTH, /* bLength */ DEVICE_DESCRIPTOR, /* bDescriptorType */ LSB(USB_VERSION_2_0), /* bcdUSB (LSB) */ @@ -928,20 +928,22 @@ uint8_t * USBDevice::deviceDesc() { STRING_OFFSET_ISERIAL, /* iSerialNumber */ 0x01 /* bNumConfigurations */ }; + MBED_ASSERT(sizeof(deviceDescriptorTemp) == sizeof(deviceDescriptor)); + memcpy(deviceDescriptor, deviceDescriptorTemp, sizeof(deviceDescriptor)); return deviceDescriptor; } -uint8_t * USBDevice::stringLangidDesc() { - static uint8_t stringLangidDescriptor[] = { +const uint8_t * USBDevice::stringLangidDesc() { + static const uint8_t stringLangidDescriptor[] = { 0x04, /*bLength*/ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/ 0x09,0x04, /*bString Lang ID - 0x0409 - English*/ }; - return stringLangidDescriptor; + return (uint8_t *)stringLangidDescriptor; } -uint8_t * USBDevice::stringImanufacturerDesc() { - static uint8_t stringImanufacturerDescriptor[] = { +const uint8_t * USBDevice::stringImanufacturerDesc() { + static const uint8_t stringImanufacturerDescriptor[] = { 0x12, /*bLength*/ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/ 'm',0,'b',0,'e',0,'d',0,'.',0,'o',0,'r',0,'g',0, /*bString iManufacturer - mbed.org*/ @@ -949,8 +951,8 @@ uint8_t * USBDevice::stringImanufacturerDesc() { return stringImanufacturerDescriptor; } -uint8_t * USBDevice::stringIserialDesc() { - static uint8_t stringIserialDescriptor[] = { +const uint8_t * USBDevice::stringIserialDesc() { + static const uint8_t stringIserialDescriptor[] = { 0x16, /*bLength*/ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/ '0',0,'1',0,'2',0,'3',0,'4',0,'5',0,'6',0,'7',0,'8',0,'9',0, /*bString iSerial - 0123456789*/ @@ -958,8 +960,8 @@ uint8_t * USBDevice::stringIserialDesc() { return stringIserialDescriptor; } -uint8_t * USBDevice::stringIConfigurationDesc() { - static uint8_t stringIconfigurationDescriptor[] = { +const uint8_t * USBDevice::stringIConfigurationDesc() { + static const uint8_t stringIconfigurationDescriptor[] = { 0x06, /*bLength*/ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/ '0',0,'1',0, /*bString iConfiguration - 01*/ @@ -967,8 +969,8 @@ uint8_t * USBDevice::stringIConfigurationDesc() { return stringIconfigurationDescriptor; } -uint8_t * USBDevice::stringIinterfaceDesc() { - static uint8_t stringIinterfaceDescriptor[] = { +const uint8_t * USBDevice::stringIinterfaceDesc() { + static const uint8_t stringIinterfaceDescriptor[] = { 0x08, /*bLength*/ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/ 'U',0,'S',0,'B',0, /*bString iInterface - USB*/ @@ -976,8 +978,8 @@ uint8_t * USBDevice::stringIinterfaceDesc() { return stringIinterfaceDescriptor; } -uint8_t * USBDevice::stringIproductDesc() { - static uint8_t stringIproductDescriptor[] = { +const uint8_t * USBDevice::stringIproductDesc() { + static const uint8_t stringIproductDescriptor[] = { 0x16, /*bLength*/ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/ 'U',0,'S',0,'B',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0 /*bString iProduct - USB DEVICE*/ diff --git a/features/unsupported/USBDevice/USBDevice/USBDevice.h b/features/unsupported/USBDevice/USBDevice/USBDevice.h index a25ca1adfe..60a280ed65 100644 --- a/features/unsupported/USBDevice/USBDevice/USBDevice.h +++ b/features/unsupported/USBDevice/USBDevice/USBDevice.h @@ -165,60 +165,60 @@ public: virtual bool USBCallback_setInterface(uint16_t interface, uint8_t alternate) { return false; }; /* - * Get device descriptor. Warning: this method has to store the length of the report descriptor in reportLength. + * Get device descriptor. * * @returns pointer to the device descriptor */ - virtual uint8_t * deviceDesc(); + virtual const uint8_t * deviceDesc(); /* * Get configuration descriptor * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(){return NULL;}; + virtual const uint8_t * configurationDesc(){return NULL;}; /* * Get string lang id descriptor * * @return pointer to the string lang id descriptor */ - virtual uint8_t * stringLangidDesc(); + virtual const uint8_t * stringLangidDesc(); /* * Get string manufacturer descriptor * * @returns pointer to the string manufacturer descriptor */ - virtual uint8_t * stringImanufacturerDesc(); + virtual const uint8_t * stringImanufacturerDesc(); /* * Get string product descriptor * * @returns pointer to the string product descriptor */ - virtual uint8_t * stringIproductDesc(); + virtual const uint8_t * stringIproductDesc(); /* * Get string serial descriptor * * @returns pointer to the string serial descriptor */ - virtual uint8_t * stringIserialDesc(); + virtual const uint8_t * stringIserialDesc(); /* * Get string configuration descriptor * * @returns pointer to the string configuration descriptor */ - virtual uint8_t * stringIConfigurationDesc(); + virtual const uint8_t * stringIConfigurationDesc(); /* * Get string interface descriptor * * @returns pointer to the string interface descriptor */ - virtual uint8_t * stringIinterfaceDesc(); + virtual const uint8_t * stringIinterfaceDesc(); /* * Get the length of the report descriptor @@ -242,6 +242,7 @@ protected: uint16_t VENDOR_ID; uint16_t PRODUCT_ID; uint16_t PRODUCT_RELEASE; + uint8_t deviceDescriptor[18]; private: bool addRateFeedbackEndpoint(uint8_t endpoint, uint32_t maxPacket); diff --git a/features/unsupported/USBDevice/USBHID/USBHID.cpp b/features/unsupported/USBDevice/USBHID/USBHID.cpp index 9ace4c992e..da5059ed12 100644 --- a/features/unsupported/USBDevice/USBHID/USBHID.cpp +++ b/features/unsupported/USBDevice/USBHID/USBHID.cpp @@ -105,7 +105,7 @@ bool USBHID::USBCallback_request() { && (reportDescLength() != 0)) { transfer->remaining = reportDescLength(); - transfer->ptr = reportDesc(); + transfer->ptr = (uint8_t*)reportDesc(); transfer->direction = DEVICE_TO_HOST; success = true; } @@ -177,8 +177,8 @@ bool USBHID::USBCallback_setConfiguration(uint8_t configuration) { } -uint8_t * USBHID::stringIinterfaceDesc() { - static uint8_t stringIinterfaceDescriptor[] = { +const uint8_t * USBHID::stringIinterfaceDesc() { + static const uint8_t stringIinterfaceDescriptor[] = { 0x08, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'H',0,'I',0,'D',0, //bString iInterface - HID @@ -186,8 +186,8 @@ uint8_t * USBHID::stringIinterfaceDesc() { return stringIinterfaceDescriptor; } -uint8_t * USBHID::stringIproductDesc() { - static uint8_t stringIproductDescriptor[] = { +const uint8_t * USBHID::stringIproductDesc() { + static const uint8_t stringIproductDescriptor[] = { 0x16, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'H',0,'I',0,'D',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0 //bString iProduct - HID device @@ -197,8 +197,8 @@ uint8_t * USBHID::stringIproductDesc() { -uint8_t * USBHID::reportDesc() { - static uint8_t reportDescriptor[] = { +const uint8_t * USBHID::reportDesc() { + uint8_t reportDescriptorTemp[] = { USAGE_PAGE(2), LSB(0xFFAB), MSB(0xFFAB), USAGE(2), LSB(0x0200), MSB(0x0200), COLLECTION(1), 0x01, // Collection (Application) @@ -218,6 +218,8 @@ uint8_t * USBHID::reportDesc() { END_COLLECTION(0), }; reportLength = sizeof(reportDescriptor); + MBED_ASSERT(sizeof(reportDescriptorTemp) == sizeof(reportDescriptor)); + memcpy(reportDescriptor, reportDescriptorTemp, sizeof(reportDescriptor)); return reportDescriptor; } @@ -227,8 +229,8 @@ uint8_t * USBHID::reportDesc() { + (1 * HID_DESCRIPTOR_LENGTH) \ + (2 * ENDPOINT_DESCRIPTOR_LENGTH)) -uint8_t * USBHID::configurationDesc() { - static uint8_t configurationDescriptor[] = { +const uint8_t * USBHID::configurationDesc() { + uint8_t configurationDescriptorTemp[] = { CONFIGURATION_DESCRIPTOR_LENGTH, // bLength CONFIGURATION_DESCRIPTOR, // bDescriptorType LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB) @@ -275,5 +277,7 @@ uint8_t * USBHID::configurationDesc() { MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB) 1, // bInterval (milliseconds) }; + MBED_ASSERT(sizeof(configurationDescriptorTemp) == sizeof(configurationDescriptor)); + memcpy(configurationDescriptor, configurationDescriptorTemp, sizeof(configurationDescriptor)); return configurationDescriptor; } diff --git a/features/unsupported/USBDevice/USBHID/USBHID.h b/features/unsupported/USBDevice/USBHID/USBHID.h index faa75cb94a..0178283cc7 100644 --- a/features/unsupported/USBDevice/USBHID/USBHID.h +++ b/features/unsupported/USBDevice/USBHID/USBHID.h @@ -98,13 +98,14 @@ public: protected: uint16_t reportLength; + uint8_t reportDescriptor[27]; /* * Get the Report descriptor * * @returns pointer to the report descriptor */ - virtual uint8_t * reportDesc(); + virtual const uint8_t * reportDesc(); /* * Get the length of the report descriptor @@ -118,21 +119,21 @@ protected: * * @returns pointer to the string product descriptor */ - virtual uint8_t * stringIproductDesc(); + virtual const uint8_t * stringIproductDesc(); /* * Get string interface descriptor * * @returns pointer to the string interface descriptor */ - virtual uint8_t * stringIinterfaceDesc(); + virtual const uint8_t * stringIinterfaceDesc(); /* * Get configuration descriptor * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(); + virtual const uint8_t * configurationDesc(); /* @@ -164,6 +165,7 @@ protected: virtual bool USBCallback_setConfiguration(uint8_t configuration); private: + uint8_t configurationDescriptor[41]; HID_REPORT outputReport; uint8_t output_length; uint8_t input_length; diff --git a/features/unsupported/USBDevice/USBHID/USBKeyboard.cpp b/features/unsupported/USBDevice/USBHID/USBKeyboard.cpp index 3f02dd3182..900f97d087 100644 --- a/features/unsupported/USBDevice/USBHID/USBKeyboard.cpp +++ b/features/unsupported/USBDevice/USBHID/USBKeyboard.cpp @@ -352,8 +352,8 @@ const KEYMAP keymap[KEYMAP_SIZE] = { }; #endif -uint8_t * USBKeyboard::reportDesc() { - static uint8_t reportDescriptor[] = { +const uint8_t * USBKeyboard::reportDesc() { + static const uint8_t reportDescriptor[] = { USAGE_PAGE(1), 0x01, // Generic Desktop USAGE(1), 0x06, // Keyboard COLLECTION(1), 0x01, // Application @@ -501,8 +501,8 @@ bool USBKeyboard::mediaControl(MEDIA_KEY key) { + (1 * HID_DESCRIPTOR_LENGTH) \ + (2 * ENDPOINT_DESCRIPTOR_LENGTH)) -uint8_t * USBKeyboard::configurationDesc() { - static uint8_t configurationDescriptor[] = { +const uint8_t * USBKeyboard::configurationDesc() { + uint8_t configurationDescriptorTemp[] = { CONFIGURATION_DESCRIPTOR_LENGTH, // bLength CONFIGURATION_DESCRIPTOR, // bDescriptorType LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB) @@ -549,5 +549,7 @@ uint8_t * USBKeyboard::configurationDesc() { MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB) 1, // bInterval (milliseconds) }; + MBED_ASSERT(sizeof(configurationDescriptorTemp) == sizeof(configurationDescriptor)); + memcpy(configurationDescriptor, configurationDescriptorTemp, sizeof(configurationDescriptor)); return configurationDescriptor; } diff --git a/features/unsupported/USBDevice/USBHID/USBKeyboard.h b/features/unsupported/USBDevice/USBHID/USBKeyboard.h index d21293568c..e88f637fcb 100644 --- a/features/unsupported/USBDevice/USBHID/USBKeyboard.h +++ b/features/unsupported/USBDevice/USBHID/USBKeyboard.h @@ -148,7 +148,7 @@ public: * * @returns pointer to the report descriptor */ - virtual uint8_t * reportDesc(); + virtual const uint8_t * reportDesc(); /* * Called when a data is received on the OUT endpoint. Useful to switch on LED of LOCK keys @@ -173,7 +173,7 @@ protected: * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(); + virtual const uint8_t * configurationDesc(); private: //dummy otherwise it doesn,t compile (we must define all methods of an abstract class) @@ -181,6 +181,7 @@ private: return -1; }; + uint8_t configurationDescriptor[41]; uint8_t lock_status; }; diff --git a/features/unsupported/USBDevice/USBHID/USBMouse.cpp b/features/unsupported/USBDevice/USBHID/USBMouse.cpp index ac3016cae0..e7dfb6cdac 100644 --- a/features/unsupported/USBDevice/USBHID/USBMouse.cpp +++ b/features/unsupported/USBDevice/USBHID/USBMouse.cpp @@ -103,10 +103,10 @@ bool USBMouse::release(uint8_t button_) { } -uint8_t * USBMouse::reportDesc() { +const uint8_t * USBMouse::reportDesc() { if (mouse_type == REL_MOUSE) { - static uint8_t reportDescriptor[] = { + static const uint8_t reportDescriptor[] = { USAGE_PAGE(1), 0x01, // Genric Desktop USAGE(1), 0x02, // Mouse COLLECTION(1), 0x01, // Application @@ -141,7 +141,7 @@ uint8_t * USBMouse::reportDesc() { reportLength = sizeof(reportDescriptor); return reportDescriptor; } else if (mouse_type == ABS_MOUSE) { - static uint8_t reportDescriptor[] = { + static const uint8_t reportDescriptor[] = { USAGE_PAGE(1), 0x01, // Generic Desktop USAGE(1), 0x02, // Mouse COLLECTION(1), 0x01, // Application @@ -192,8 +192,8 @@ uint8_t * USBMouse::reportDesc() { + (1 * HID_DESCRIPTOR_LENGTH) \ + (2 * ENDPOINT_DESCRIPTOR_LENGTH)) -uint8_t * USBMouse::configurationDesc() { - static uint8_t configurationDescriptor[] = { +const uint8_t * USBMouse::configurationDesc() { + uint8_t configurationDescriptorTemp[] = { CONFIGURATION_DESCRIPTOR_LENGTH, // bLength CONFIGURATION_DESCRIPTOR, // bDescriptorType LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB) @@ -240,5 +240,7 @@ uint8_t * USBMouse::configurationDesc() { MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB) 1, // bInterval (milliseconds) }; + MBED_ASSERT(sizeof(configurationDescriptorTemp) == sizeof(configurationDescriptor)); + memcpy(configurationDescriptor, configurationDescriptorTemp, sizeof(configurationDescriptor)); return configurationDescriptor; } diff --git a/features/unsupported/USBDevice/USBHID/USBMouse.h b/features/unsupported/USBDevice/USBHID/USBMouse.h index 7aa4263343..9371b0e850 100644 --- a/features/unsupported/USBDevice/USBHID/USBMouse.h +++ b/features/unsupported/USBDevice/USBHID/USBMouse.h @@ -190,7 +190,7 @@ class USBMouse: public USBHID * * @returns pointer to the report descriptor */ - virtual uint8_t * reportDesc(); + virtual const uint8_t * reportDesc(); protected: /* @@ -198,11 +198,12 @@ class USBMouse: public USBHID * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(); + virtual const uint8_t * configurationDesc(); private: MOUSE_TYPE mouse_type; uint8_t button; + uint8_t configurationDescriptor[41]; bool mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z); }; diff --git a/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.cpp b/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.cpp index cd68091202..5c544a80b8 100644 --- a/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.cpp +++ b/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.cpp @@ -348,9 +348,9 @@ const KEYMAP keymap[KEYMAP_SIZE] = { #endif -uint8_t * USBMouseKeyboard::reportDesc() { +const uint8_t * USBMouseKeyboard::reportDesc() { if (mouse_type == REL_MOUSE) { - static uint8_t reportDescriptor[] = { + static const uint8_t reportDescriptor[] = { // Keyboard USAGE_PAGE(1), 0x01, USAGE(1), 0x06, @@ -442,7 +442,7 @@ uint8_t * USBMouseKeyboard::reportDesc() { reportLength = sizeof(reportDescriptor); return reportDescriptor; } else if (mouse_type == ABS_MOUSE) { - static uint8_t reportDescriptor[] = { + static const uint8_t reportDescriptor[] = { // Keyboard USAGE_PAGE(1), 0x01, diff --git a/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.h b/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.h index 1b19b10db2..fb2bbc6d9c 100644 --- a/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.h +++ b/features/unsupported/USBDevice/USBHID/USBMouseKeyboard.h @@ -195,7 +195,7 @@ class USBMouseKeyboard: public USBHID, public Stream * * @returns pointer to the report descriptor */ - virtual uint8_t * reportDesc(); + virtual const uint8_t * reportDesc(); /* * Called when a data is received on the OUT endpoint. Useful to switch on LED of LOCK keys diff --git a/features/unsupported/USBDevice/USBMIDI/USBMIDI.cpp b/features/unsupported/USBDevice/USBMIDI/USBMIDI.cpp index 084574a790..fb37d3d1db 100644 --- a/features/unsupported/USBDevice/USBMIDI/USBMIDI.cpp +++ b/features/unsupported/USBDevice/USBMIDI/USBMIDI.cpp @@ -157,8 +157,8 @@ bool USBMIDI::USBCallback_setConfiguration(uint8_t configuration) { } -uint8_t * USBMIDI::stringIinterfaceDesc() { - static uint8_t stringIinterfaceDescriptor[] = { +const uint8_t * USBMIDI::stringIinterfaceDesc() { + static const uint8_t stringIinterfaceDescriptor[] = { 0x0c, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'A',0,'u',0,'d',0,'i',0,'o',0 //bString iInterface - Audio @@ -166,8 +166,8 @@ uint8_t * USBMIDI::stringIinterfaceDesc() { return stringIinterfaceDescriptor; } -uint8_t * USBMIDI::stringIproductDesc() { - static uint8_t stringIproductDescriptor[] = { +const uint8_t * USBMIDI::stringIproductDesc() { + static const uint8_t stringIproductDescriptor[] = { 0x16, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'M',0,'b',0,'e',0,'d',0,' ',0,'A',0,'u',0,'d',0,'i',0,'o',0 //bString iProduct - Mbed Audio @@ -176,8 +176,8 @@ uint8_t * USBMIDI::stringIproductDesc() { } -uint8_t * USBMIDI::configurationDesc() { - static uint8_t configDescriptor[] = { +const uint8_t * USBMIDI::configurationDesc() { + static const uint8_t configDescriptor[] = { // configuration descriptor 0x09, 0x02, 0x65, 0x00, 0x02, 0x01, 0x00, 0xc0, 0x50, diff --git a/features/unsupported/USBDevice/USBMIDI/USBMIDI.h b/features/unsupported/USBDevice/USBMIDI/USBMIDI.h index cc5be5b7d8..c69cae14c4 100644 --- a/features/unsupported/USBDevice/USBMIDI/USBMIDI.h +++ b/features/unsupported/USBDevice/USBMIDI/USBMIDI.h @@ -85,21 +85,21 @@ protected: * * @returns pointer to the string product descriptor */ - virtual uint8_t * stringIproductDesc(); + virtual const uint8_t * stringIproductDesc(); /* * Get string interface descriptor * * @returns pointer to the string interface descriptor */ - virtual uint8_t * stringIinterfaceDesc(); + virtual const uint8_t * stringIinterfaceDesc(); /* * Get configuration descriptor * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(); + virtual const uint8_t * configurationDesc(); private: uint8_t data[MAX_MIDI_MESSAGE_SIZE+1]; diff --git a/features/unsupported/USBDevice/USBMSD/USBMSD.cpp b/features/unsupported/USBDevice/USBMSD/USBMSD.cpp index ee5ad24733..21d50f9b9f 100644 --- a/features/unsupported/USBDevice/USBMSD/USBMSD.cpp +++ b/features/unsupported/USBDevice/USBMSD/USBMSD.cpp @@ -589,8 +589,8 @@ bool USBMSD::USBCallback_setConfiguration(uint8_t configuration) { } -uint8_t * USBMSD::stringIinterfaceDesc() { - static uint8_t stringIinterfaceDescriptor[] = { +const uint8_t * USBMSD::stringIinterfaceDesc() { + static const uint8_t stringIinterfaceDescriptor[] = { 0x08, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'M',0,'S',0,'D',0 //bString iInterface - MSD @@ -598,8 +598,8 @@ uint8_t * USBMSD::stringIinterfaceDesc() { return stringIinterfaceDescriptor; } -uint8_t * USBMSD::stringIproductDesc() { - static uint8_t stringIproductDescriptor[] = { +const uint8_t * USBMSD::stringIproductDesc() { + static const uint8_t stringIproductDescriptor[] = { 0x12, //bLength STRING_DESCRIPTOR, //bDescriptorType 0x03 'M',0,'b',0,'e',0,'d',0,' ',0,'M',0,'S',0,'D',0 //bString iProduct - Mbed Audio @@ -608,8 +608,8 @@ uint8_t * USBMSD::stringIproductDesc() { } -uint8_t * USBMSD::configurationDesc() { - static uint8_t configDescriptor[] = { +const uint8_t * USBMSD::configurationDesc() { + static const uint8_t configDescriptor[] = { // Configuration 1 9, // bLength diff --git a/features/unsupported/USBDevice/USBMSD/USBMSD.h b/features/unsupported/USBDevice/USBMSD/USBMSD.h index ff750026c1..8d83c1a855 100644 --- a/features/unsupported/USBDevice/USBMSD/USBMSD.h +++ b/features/unsupported/USBDevice/USBMSD/USBMSD.h @@ -139,21 +139,21 @@ protected: * * @returns pointer to the string product descriptor */ - virtual uint8_t * stringIproductDesc(); + virtual const uint8_t * stringIproductDesc(); /* * Get string interface descriptor * * @returns pointer to the string interface descriptor */ - virtual uint8_t * stringIinterfaceDesc(); + virtual const uint8_t * stringIinterfaceDesc(); /* * Get configuration descriptor * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(); + virtual const uint8_t * configurationDesc(); /* * Callback called when a packet is received diff --git a/features/unsupported/USBDevice/USBSerial/USBCDC.cpp b/features/unsupported/USBDevice/USBSerial/USBCDC.cpp index d6dc16ef2f..ec46f0fda3 100644 --- a/features/unsupported/USBDevice/USBSerial/USBCDC.cpp +++ b/features/unsupported/USBDevice/USBSerial/USBCDC.cpp @@ -144,8 +144,8 @@ bool USBCDC::readEP_NB(uint8_t * buffer, uint32_t * size) { } -uint8_t * USBCDC::deviceDesc() { - static uint8_t deviceDescriptor[] = { +const uint8_t * USBCDC::deviceDesc() { + uint8_t deviceDescriptorTemp[] = { 18, // bLength 1, // bDescriptorType 0x10, 0x01, // bcdUSB @@ -161,11 +161,13 @@ uint8_t * USBCDC::deviceDesc() { 3, // iSerialNumber 1 // bNumConfigurations }; + MBED_ASSERT(sizeof(deviceDescriptorTemp) == sizeof(deviceDescriptor)); + memcpy(deviceDescriptor, deviceDescriptorTemp, sizeof(deviceDescriptor)); return deviceDescriptor; } -uint8_t * USBCDC::stringIinterfaceDesc() { - static uint8_t stringIinterfaceDescriptor[] = { +const uint8_t * USBCDC::stringIinterfaceDesc() { + static const uint8_t stringIinterfaceDescriptor[] = { 0x08, STRING_DESCRIPTOR, 'C',0,'D',0,'C',0, @@ -173,8 +175,8 @@ uint8_t * USBCDC::stringIinterfaceDesc() { return stringIinterfaceDescriptor; } -uint8_t * USBCDC::stringIproductDesc() { - static uint8_t stringIproductDescriptor[] = { +const uint8_t * USBCDC::stringIproductDesc() { + static const uint8_t stringIproductDescriptor[] = { 0x16, STRING_DESCRIPTOR, 'C',0,'D',0,'C',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0 @@ -185,8 +187,8 @@ uint8_t * USBCDC::stringIproductDesc() { #define CONFIG1_DESC_SIZE (9+8+9+5+5+4+5+7+9+7+7) -uint8_t * USBCDC::configurationDesc() { - static uint8_t configDescriptor[] = { +const uint8_t * USBCDC::configurationDesc() { + static const uint8_t configDescriptor[] = { // configuration descriptor 9, // bLength 2, // bDescriptorType diff --git a/features/unsupported/USBDevice/USBSerial/USBCDC.h b/features/unsupported/USBDevice/USBSerial/USBCDC.h index c41e425212..0f59c2c621 100644 --- a/features/unsupported/USBDevice/USBSerial/USBCDC.h +++ b/features/unsupported/USBDevice/USBSerial/USBCDC.h @@ -46,28 +46,28 @@ protected: * * @returns pointer to the device descriptor */ - virtual uint8_t * deviceDesc(); + virtual const uint8_t * deviceDesc(); /* * Get string product descriptor * * @returns pointer to the string product descriptor */ - virtual uint8_t * stringIproductDesc(); + virtual const uint8_t * stringIproductDesc(); /* * Get string interface descriptor * * @returns pointer to the string interface descriptor */ - virtual uint8_t * stringIinterfaceDesc(); + virtual const uint8_t * stringIinterfaceDesc(); /* * Get configuration descriptor * * @returns pointer to the configuration descriptor */ - virtual uint8_t * configurationDesc(); + virtual const uint8_t * configurationDesc(); /* * Send a buffer From 40125cf1215b2740816e0e049898216c3fba57bc Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Thu, 11 Jan 2018 14:08:09 -0600 Subject: [PATCH 099/133] Remove use of deprecated attach in USB Attach callbacks with the assignment operator rather than with the deprecated attach function. This fixes deprecation warnings. This patch also adds the ability to attach a Callback directly. --- .../unsupported/USBDevice/USBAudio/USBAudio.h | 49 ++++++++++++++++--- .../USBDevice/USBSerial/USBSerial.h | 13 ++++- 2 files changed, 54 insertions(+), 8 deletions(-) diff --git a/features/unsupported/USBDevice/USBAudio/USBAudio.h b/features/unsupported/USBDevice/USBAudio/USBAudio.h index f1bdbe6d48..e72f42e559 100644 --- a/features/unsupported/USBDevice/USBAudio/USBAudio.h +++ b/features/unsupported/USBDevice/USBAudio/USBAudio.h @@ -152,7 +152,7 @@ public: * */ void attach(void(*fptr)(void)) { - updateVol.attach(fptr); + updateVol = Callback(fptr); } /** attach a handler to Tx Done * @@ -160,7 +160,7 @@ public: * */ void attachTx(void(*fptr)(void)) { - txDone.attach(fptr); + txDone = Callback(fptr); } /** attach a handler to Rx Done * @@ -168,7 +168,7 @@ public: * */ void attachRx(void(*fptr)(void)) { - rxDone.attach(fptr); + rxDone = Callback(fptr); } /** Attach a nonstatic void/void member function to update the volume @@ -179,15 +179,52 @@ public: */ template void attach(T *tptr, void(T::*mptr)(void)) { - updateVol.attach(tptr, mptr); + updateVol = Callback(tptr, mptr); } + /** Attach a nonstatic void/void member function to Tx Done + * + * @param tptr Object pointer + * @param mptr Member function pointer + * + */ template void attachTx(T *tptr, void(T::*mptr)(void)) { - txDone.attach(tptr, mptr); + txDone = Callback(tptr, mptr); } + /** Attach a nonstatic void/void member function to Rx Done + * + * @param tptr Object pointer + * @param mptr Member function pointer + * + */ template void attachRx(T *tptr, void(T::*mptr)(void)) { - rxDone.attach(tptr, mptr); + rxDone = Callback(tptr, mptr); + } + + /** Attach a Callback to update the volume + * + * @param cb Callback to attach + * + */ + void attach(Callback &cb) { + updateVol = cb; + } + /** attach a Callback to Tx Done + * + * @param cb Callback to attach + * + */ + void attachTx(Callback &cb) { + txDone = cb; + } + /** attach a Callback to Rx Done + * + * @param cb Callback to attach + * + */ + void attachRx(Callback &cb) { + rxDone = cb; } diff --git a/features/unsupported/USBDevice/USBSerial/USBSerial.h b/features/unsupported/USBDevice/USBSerial/USBSerial.h index 825b03caf6..69ed61abf5 100644 --- a/features/unsupported/USBDevice/USBSerial/USBSerial.h +++ b/features/unsupported/USBDevice/USBSerial/USBSerial.h @@ -127,7 +127,7 @@ public: template void attach(T* tptr, void (T::*mptr)(void)) { if((mptr != NULL) && (tptr != NULL)) { - rx.attach(tptr, mptr); + rx = Callback(mptr, tptr); } } @@ -138,10 +138,19 @@ public: */ void attach(void (*fptr)(void)) { if(fptr != NULL) { - rx.attach(fptr); + rx = Callback(fptr); } } + /** + * Attach a Callback called when a packet is received + * + * @param cb Callback to attach + */ + void attach(Callback &cb) { + rx = cb; + } + /** * Attach a callback to call when serial's settings are changed. * From f0b9add71e50abb14568fafe3f3ff04206feb836 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Fri, 5 Jan 2018 15:02:43 -0600 Subject: [PATCH 100/133] Fix clearing of ISTAT in Kinetis USB The ISTAT register is write 1 to clear. Because of this ORing this register with itself fill clear all bits that are set. This patch updates the code to use plain assignment so only desired bit is cleared. --- .../USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp b/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp index 71bf529900..69471edf70 100644 --- a/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_Freescale/USBHAL_KL25Z.cpp @@ -500,7 +500,7 @@ void USBHAL::usbisr(void) { if (istat & 1<<7) { if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK) USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK; - USB0->ISTAT |= USB_ISTAT_STALL_MASK; + USB0->ISTAT = USB_ISTAT_STALL_MASK; } // token interrupt @@ -555,13 +555,13 @@ void USBHAL::usbisr(void) { // sleep interrupt if (istat & 1<<4) { - USB0->ISTAT |= USB_ISTAT_SLEEP_MASK; + USB0->ISTAT = USB_ISTAT_SLEEP_MASK; } // error interrupt if (istat & USB_ISTAT_ERROR_MASK) { USB0->ERRSTAT = 0xFF; - USB0->ISTAT |= USB_ISTAT_ERROR_MASK; + USB0->ISTAT = USB_ISTAT_ERROR_MASK; } } From c5d5718ed487160fc5b24c5e1529884d3cf22453 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Thu, 25 Jan 2018 15:27:35 -0600 Subject: [PATCH 101/133] Remove tickless assert for tick count Remove the assert that the tick count of the OS matches the tick count of the tickless timer as this occurs frequently when debugging. This is because the function svcRtxKernelResume only increments the OS's tick count until the next wakeup event so if the device was halted by a debugger past the next wakeup event the tick counts will be out of sync. --- rtos/TARGET_CORTEX/mbed_rtx_idle.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index f41b562c54..23830a8f5d 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -194,7 +194,6 @@ static void default_idle_hook(void) core_util_critical_section_enter(); uint32_t ticks_to_sleep = svcRtxKernelSuspend(); - MBED_ASSERT(os_timer->get_tick() == svcRtxKernelGetTickCount()); if (ticks_to_sleep) { os_timer->schedule_tick(ticks_to_sleep); From 706e133ee816e881d9decb1e4e4574075cf1a617 Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Fri, 10 Nov 2017 22:23:03 +0100 Subject: [PATCH 102/133] add cmake exporter for CLion use --- tools/export/__init__.py | 4 +- tools/export/cmake/CMakeLists.txt.tmpl | 94 +++++++++++ tools/export/cmake/README.md | 15 ++ tools/export/cmake/__init__.py | 225 +++++++++++++++++++++++++ 4 files changed, 337 insertions(+), 1 deletion(-) create mode 100644 tools/export/cmake/CMakeLists.txt.tmpl create mode 100644 tools/export/cmake/README.md create mode 100644 tools/export/cmake/__init__.py diff --git a/tools/export/__init__.py b/tools/export/__init__.py index c15669618f..914d43bca3 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -33,6 +33,7 @@ from tools.export import embitz, coide, kds, simplicity, atmelstudio, mcuxpresso from tools.export import sw4stm32, e2studio, zip, cmsis, uvision, cdt, vscode from tools.export import gnuarmeclipse from tools.export import qtcreator +from tools.export import cmake from tools.export import nb from tools.targets import TARGET_NAMES @@ -63,7 +64,8 @@ EXPORTERS = { 'qtcreator': qtcreator.QtCreator, 'vscode_gcc_arm' : vscode.VSCodeGcc, 'vscode_iar' : vscode.VSCodeIAR, - 'vscode_armc5' : vscode.VSCodeArmc5 + 'vscode_armc5' : vscode.VSCodeArmc5, + 'cmake_gcc_arm': cmake.GccArm } ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN = """ diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl new file mode 100644 index 0000000000..4bb1d11cc2 --- /dev/null +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -0,0 +1,94 @@ +# This file was automagically generated by mbed.org. +# If you would like to add your own targets, create a +# project.cmake file locally in your project directory. + +CMAKE_MINIMUM_REQUIRED(VERSION 3.9) +SET(CMAKE_SYSTEM_NAME Generic) +#SET(CMAKE_SYSTEM_PROCESSOR arm) +SET(CMAKE_CROSSCOMPILING TRUE) + +# force compiler settings +SET(CMAKE_C_COMPILER_WORKS TRUE) +SET(CMAKE_CXX_COMPILER_WORKS TRUE) + +SET(CMAKE_ASM_COMPILER_INIT "{{asm}}") +SET(CMAKE_C_COMPILER_INIT "{{cc}}") +SET(CMAKE_CXX_COMPILER_INIT "{{cxx}}") +SET(CMAKE_CXX_LINK_EXECUTABLE "{{ld}}") + +{% if pp -%} +SET(PREPROC "{{pp}}") +{%- endif %} +{% if hex_files %} +SET(SREC_CAT "srec_cat") +{%- endif %} + +# here starts the project +PROJECT({{name}} C CXX ASM) +#SET(CMAKE_VERBOSE_MAKEFILE ON) + +SET(CMAKE_C_FLAGS "{{cc_flags}} -include mbed_config.h") +SET(CMAKE_CXX_FLAGS "{{cxx_flags}} -include mbed_config.h") +SET(CMAKE_ASM_FLAGS "{{asm_flags}} -include mbed_config.h") +SET(CMAKE_LINKER_FLAGS "{{ld_flags}}") + +SET(LD_SYS_LIBS "{{ld_sys_libs|join(" ")}}") +SET(ELF2BIN {{elf2bin}}) + +SET(CMAKE_EXE_LINKER_FLAGS "{{ld_flags}} {{link_script_option}} ${LD_SYS_LIBS}") + +ADD_DEFINITIONS( + {% for d in symbols %}-D{{d}} + {% endfor %}) +INCLUDE_DIRECTORIES( + {% for p in include_paths %}{{p}} + {% endfor %}) + +{% for libname,libsrcs in libs.items() %} +# target for library "{{libname}}" +ADD_LIBRARY({{libname}} STATIC EXCLUDE_FROM_ALL + {% for libsrc in libsrcs %}{{libsrc}} + {% endfor %}) +{% endfor %} + +# executable {{name}} +ADD_EXECUTABLE({{name}} EXCLUDE_FROM_ALL + {% for src in sources %}{{src}} + {% endfor %}) +TARGET_LINK_LIBRARIES({{name}} + {% for libname in libs %}{{libname}} + {% endfor %}) + +########################################################################## +# mbed-cli specific targets +########################################################################## + +# detect the build type and select the corresponding cli profile +SET(MBED_BUILD_PROFILE "") +STRING(TOLOWER ${CMAKE_BUILD_TYPE} LOWERCASE_CMAKE_BUILD_TYPE) +IF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES debug) + SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/debug.json") +ELSEIF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES relwithdebinfo) + SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/develop.json") +ELSEIF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES release) + SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/release.json") +ELSEIF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES minsizerel) + SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/release.json") +ELSE() + MESSAGE(WARNING "Build type '${CMAKE_BUILD_TYPE}' is unknown, using debug profile") + SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/debug.json") +ENDIF() + +# optional custom target to build via mbed-cli +MESSAGE(STATUS "Creating target 01-{{name}} for mbed compilation...") +ADD_CUSTOM_TARGET(01-{{name}} ALL + COMMAND ${CMAKE_COMMAND} -E echo "mbed compile --build BUILD/${CMAKE_BUILD_TYPE} ${MBED_BUILD_PROFILE}" + COMMAND mbed compile --build BUILD/${CMAKE_BUILD_TYPE} --profile ${MBED_BUILD_PROFILE} + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + SOURCES ${SOURCE_FILES} ${SYS_SOURCE_FILES}) + +IF(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/project.cmake) + INCLUDE(${CMAKE_CURRENT_SOURCE_DIR}/project.cmake) +ELSE() + MESSAGE(STATUS "Add a local project.cmake file to add your own targets.") +ENDIF() \ No newline at end of file diff --git a/tools/export/cmake/README.md b/tools/export/cmake/README.md new file mode 100644 index 0000000000..338097d271 --- /dev/null +++ b/tools/export/cmake/README.md @@ -0,0 +1,15 @@ +# CLion CMakeLists.txt Generator + +This exporter generates a CMakeLists.txt file that can be used to +develop mbed using [IntelliJ CLion](https://www.jetbrains.com/clion/). + +It will not create a functional CMake build system that mimics the +mbed build system, but rather uses the mbed-cli itself to compile +the targets. The generated files help CLion to understand the +includes and dependencies of your code. + +Run the following command to create/overwrite your CMakeLists.txt. +``` +mbed export -i cmake_gcc_arm +``` +> Run the command again if files or libraries have been added or removed. \ No newline at end of file diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py new file mode 100644 index 0000000000..ee00bf1a2e --- /dev/null +++ b/tools/export/cmake/__init__.py @@ -0,0 +1,225 @@ +""" +mbed SDK +Copyright (c) 2011-2016 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" +import re +import shutil +from os import remove +from os.path import splitext, basename, exists +from subprocess import Popen, PIPE + +from jinja2.exceptions import TemplateNotFound + +from tools.export.exporters import Exporter +from tools.utils import NotSupportedException + + +class CMake(Exporter): + """Generic CMake template that mimics the behavior of the python build + system + """ + + TEMPLATE = 'CMakeLists.txt' + + MBED_CONFIG_HEADER_SUPPORTED = True + + PREPROCESS_ASM = False + + @classmethod + def is_target_supported(cls, target_name): + return True + + def generate(self): + """Generate the CMakefiles.txt + """ + self.resources.win_to_unix() + + sources = set(self.resources.c_sources + \ + self.resources.cpp_sources + \ + self.resources.s_sources + \ + self.resources.headers) + + libnames = [l[:-4] for l in self.resources.lib_refs] + libs = {re.sub(r'^[.]/', '', l): sorted([f for f in sources if f.startswith(l)]) for l in libnames} + libs = {k: v for k, v in libs.items() if len(v) != 0} + srcs = sorted([f for f in sources if f not in [item for sublist in libs.values() for item in sublist]]) + + libraries = [self.prepare_lib(basename(lib)) for lib + in self.resources.libraries] + sys_libs = [self.prepare_sys_lib(lib) for lib + in self.toolchain.sys_libs] + + ctx = { + 'name': self.project_name, + 'target': self.target, + 'sources': srcs, + 'libs': libs, + 'libraries': libraries, + 'ld_sys_libs': sys_libs, + 'include_paths': sorted(list(set(self.resources.inc_dirs))), + 'library_paths': sorted(self.resources.lib_dirs), + 'linker_script': self.resources.linker_script, + 'hex_files': self.resources.hex_files, + 'ar': basename(self.toolchain.ar), + 'cc': basename(self.toolchain.cc[0]), + 'cc_flags': " ".join(self.toolchain.cc[1:]), + 'cxx': basename(self.toolchain.cppc[0]), + 'cxx_flags': " ".join(self.toolchain.cppc[1:]), + 'asm': basename(self.toolchain.asm[0]), + 'asm_flags': " ".join(self.toolchain.asm[1:]), + 'symbols': self.toolchain.get_symbols(), + 'ld': basename(self.toolchain.ld[0]), + 'ld_flags': " ".join(self.toolchain.ld[1:]), + 'elf2bin': basename(self.toolchain.elf2bin), + 'link_script_ext': self.toolchain.LINKER_EXT, + 'link_script_option': self.LINK_SCRIPT_OPTION, + 'user_library_flag': self.USER_LIBRARY_FLAG, + 'needs_asm_preproc': self.PREPROCESS_ASM, + } + + if hasattr(self.toolchain, "preproc"): + ctx['pp'] = " ".join(["\'" + part + "\'" for part + in ([basename(self.toolchain.preproc[0])] + + self.toolchain.preproc[1:] + + self.toolchain.ld[1:])]) + else: + ctx['pp'] = None + + for templatefile in ['cmake/%s.tmpl' % self.TEMPLATE]: + try: + self.gen_file(templatefile, ctx, 'CMakeLists.txt') + break + except TemplateNotFound: + pass + else: + raise NotSupportedException("This make tool is in development") + + @staticmethod + def build(project_name, log_name="build_log.txt", cleanup=True): + """ Build Make project """ + # > Make -j + cmd = ["make", "-j"] + + # Build the project + p = Popen(cmd, stdout=PIPE, stderr=PIPE) + out, err = p.communicate() + ret_code = p.returncode + + out_string = "=" * 10 + "STDOUT" + "=" * 10 + "\n" + out_string += out + out_string += "=" * 10 + "STDERR" + "=" * 10 + "\n" + out_string += err + + if ret_code == 0: + out_string += "SUCCESS" + else: + out_string += "FAILURE" + + print out_string + + if log_name: + # Write the output to the log file + with open(log_name, 'w+') as f: + f.write(out_string) + + # Cleanup the exported and built files + if cleanup: + remove("CMakeLists.txt") + remove(log_name) + # legacy .build directory cleaned if exists + if exists('.build'): + shutil.rmtree('.build') + if exists('BUILD'): + shutil.rmtree('BUILD') + + if ret_code != 0: + # Seems like something went wrong. + return -1 + else: + return 0 + + +class GccArm(CMake): + """GCC ARM specific cmake target""" + NAME = 'CMake-GCC-ARM' + TOOLCHAIN = "GCC_ARM" + LINK_SCRIPT_OPTION = "-T" + USER_LIBRARY_FLAG = "-L" + + @staticmethod + def prepare_lib(libname): + if "lib" == libname[:3]: + libname = libname[3:-2] + return "-l" + libname + + @staticmethod + def prepare_sys_lib(libname): + return "-l" + libname + + +# class Arm(CMake): +# """ARM Compiler generic cmake target""" +# LINK_SCRIPT_OPTION = "--scatter" +# USER_LIBRARY_FLAG = "--userlibpath " +# +# @staticmethod +# def prepare_lib(libname): +# return libname +# +# @staticmethod +# def prepare_sys_lib(libname): +# return libname +# +# def generate(self): +# if self.resources.linker_script: +# new_script = self.toolchain.correct_scatter_shebang( +# self.resources.linker_script) +# if new_script is not self.resources.linker_script: +# self.resources.linker_script = new_script +# self.generated_files.append(new_script) +# return super(Arm, self).generate() +# +# +# class Armc5(Arm): +# """ARM Compiler 5 (armcc) specific makefile target""" +# NAME = 'CMake-ARMc5' +# TOOLCHAIN = "ARM" +# PREPROCESS_ASM = True +# +# +# class Armc6(Arm): +# """ARM Compiler 6 (armclang) specific generic makefile target""" +# NAME = 'CMake-ARMc6' +# TOOLCHAIN = "ARMC6" +# +# +# class IAR(CMake): +# """IAR specific cmake target""" +# NAME = 'CMake-IAR' +# TOOLCHAIN = "IAR" +# LINK_SCRIPT_OPTION = "--config" +# USER_LIBRARY_FLAG = "-L" +# +# @staticmethod +# def prepare_lib(libname): +# if "lib" == libname[:3]: +# libname = libname[3:] +# return "-l" + splitext(libname)[0] +# +# @staticmethod +# def prepare_sys_lib(libname): +# if "lib" == libname[:3]: +# libname = libname[3:] +# return "-l" + splitext(libname)[0] From bb6081eb5b814ae5afedc8d570022816996d5045 Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Wed, 15 Nov 2017 10:03:04 +0100 Subject: [PATCH 103/133] explain code, fix naming, work on linking --- tools/export/cmake/CMakeLists.txt.tmpl | 47 ++++++++------- tools/export/cmake/__init__.py | 83 ++++++++++++++++---------- 2 files changed, 75 insertions(+), 55 deletions(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index 4bb1d11cc2..6f0920cadb 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -11,31 +11,27 @@ SET(CMAKE_CROSSCOMPILING TRUE) SET(CMAKE_C_COMPILER_WORKS TRUE) SET(CMAKE_CXX_COMPILER_WORKS TRUE) -SET(CMAKE_ASM_COMPILER_INIT "{{asm}}") -SET(CMAKE_C_COMPILER_INIT "{{cc}}") -SET(CMAKE_CXX_COMPILER_INIT "{{cxx}}") -SET(CMAKE_CXX_LINK_EXECUTABLE "{{ld}}") - -{% if pp -%} -SET(PREPROC "{{pp}}") -{%- endif %} +SET(CMAKE_ASM_COMPILER_INIT "{{asm}}") +SET(CMAKE_C_COMPILER_INIT "{{cc}}") +SET(CMAKE_CXX_COMPILER_INIT "{{cxx}}") +SET(ELF2BIN "{{elf2bin}}") {% if hex_files %} SET(SREC_CAT "srec_cat") {%- endif %} # here starts the project -PROJECT({{name}} C CXX ASM) +PROJECT(cmake-{{name}} C CXX ASM) #SET(CMAKE_VERBOSE_MAKEFILE ON) +SET(LD_SYS_LIBS "{%- block sys_libs -%} -Wl,--start-group {{ld_sys_libs|join(" ")}} {{libraries|join(" ")}} -Wl,--end-group {%- endblock -%}") + SET(CMAKE_C_FLAGS "{{cc_flags}} -include mbed_config.h") SET(CMAKE_CXX_FLAGS "{{cxx_flags}} -include mbed_config.h") SET(CMAKE_ASM_FLAGS "{{asm_flags}} -include mbed_config.h") -SET(CMAKE_LINKER_FLAGS "{{ld_flags}}") - -SET(LD_SYS_LIBS "{{ld_sys_libs|join(" ")}}") -SET(ELF2BIN {{elf2bin}}) - -SET(CMAKE_EXE_LINKER_FLAGS "{{ld_flags}} {{link_script_option}} ${LD_SYS_LIBS}") +SET(CMAKE_CXX_LINK_FLAGS "{{ld_flags}}") +{% if pp -%} +SET(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_INK_FLAGS} {{link_script_option}} ${CMAKE_BINARY_DIR}/{{name}}.link_script.ld ${LD_SYS_LIBS}") +{%- endif %} ADD_DEFINITIONS( {% for d in symbols %}-D{{d}} @@ -44,21 +40,29 @@ INCLUDE_DIRECTORIES( {% for p in include_paths %}{{p}} {% endfor %}) -{% for libname,libsrcs in libs.items() %} +{% for libname,libsrcs in dependencies.items() %} # target for library "{{libname}}" -ADD_LIBRARY({{libname}} STATIC EXCLUDE_FROM_ALL +ADD_LIBRARY({{libname}} STATIC {% for libsrc in libsrcs %}{{libsrc}} {% endfor %}) {% endfor %} # executable {{name}} -ADD_EXECUTABLE({{name}} EXCLUDE_FROM_ALL +ADD_EXECUTABLE({{name}}.elf {% for src in sources %}{{src}} {% endfor %}) -TARGET_LINK_LIBRARIES({{name}} - {% for libname in libs %}{{libname}} +TARGET_LINK_LIBRARIES({{name}}.elf + {% for libname in dependencies %}{{libname}} {% endfor %}) +{% if pp -%} +add_custom_command(TARGET {{name}}.elf PRE_LINK + COMMAND "{{pp}}" {{pp_flags}} {{linker_script}} -o ${CMAKE_CURRENT_BINARY_DIR}/{{name}}.link_script.ld + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + BYPRODUCTS "${CMAKE_CURRENT_BINARY_DIR}/{{name}}.link_script.ld" + ) +{%- endif %} + ########################################################################## # mbed-cli specific targets ########################################################################## @@ -80,8 +84,7 @@ ELSE() ENDIF() # optional custom target to build via mbed-cli -MESSAGE(STATUS "Creating target 01-{{name}} for mbed compilation...") -ADD_CUSTOM_TARGET(01-{{name}} ALL +ADD_CUSTOM_TARGET(mbed-cli-build EXCLUDE_FROM_ALL COMMAND ${CMAKE_COMMAND} -E echo "mbed compile --build BUILD/${CMAKE_BUILD_TYPE} ${MBED_BUILD_PROFILE}" COMMAND mbed compile --build BUILD/${CMAKE_BUILD_TYPE} --profile ${MBED_BUILD_PROFILE} WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index ee00bf1a2e..c6dde08e7e 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -22,7 +22,8 @@ from subprocess import Popen, PIPE from jinja2.exceptions import TemplateNotFound -from tools.export.exporters import Exporter +from tools.export.exporters import Exporter, apply_supported_whitelist +from tools.targets import TARGET_MAP from tools.utils import NotSupportedException @@ -37,35 +38,55 @@ class CMake(Exporter): PREPROCESS_ASM = False + POST_BINARY_WHITELIST = set([ + "MCU_NRF51Code.binary_hook", + "TEENSY3_1Code.binary_hook", + "LPCTargetCode.lpc_patch", + "LPC4088Code.binary_hook" + ]) + @classmethod def is_target_supported(cls, target_name): - return True + target = TARGET_MAP[target_name] + return apply_supported_whitelist( + cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target) def generate(self): """Generate the CMakefiles.txt """ self.resources.win_to_unix() - sources = set(self.resources.c_sources + \ - self.resources.cpp_sources + \ - self.resources.s_sources + \ - self.resources.headers) + # get all source files including headers, adding headers allows IDEs to detect which files + # belong to the project, otherwise headers may be greyed out and not work with inspection + # (that is true for CLion and definitely for Visual Code) + allSourceFiles = set(self.resources.c_sources + + self.resources.cpp_sources + + self.resources.s_sources + + self.resources.headers) - libnames = [l[:-4] for l in self.resources.lib_refs] - libs = {re.sub(r'^[.]/', '', l): sorted([f for f in sources if f.startswith(l)]) for l in libnames} - libs = {k: v for k, v in libs.items() if len(v) != 0} - srcs = sorted([f for f in sources if f not in [item for sublist in libs.values() for item in sublist]]) + # create a list of dependencies (mbed add ...) + dependencies = [l[:-4] for l in self.resources.lib_refs] + # separate the individual dependency source files into a map with the dep name as key and an array if files + depSources = {re.sub(r'^[.]/', '', l): + sorted([f for f in allSourceFiles if f.startswith(l)]) for l in dependencies} + # delete dependencies that have no source files (may happen if a sub-dependency is ignored by .mbedignore) + depSources = {k: v for k, v in depSources.items() if len(v) != 0} - libraries = [self.prepare_lib(basename(lib)) for lib - in self.resources.libraries] - sys_libs = [self.prepare_sys_lib(lib) for lib - in self.toolchain.sys_libs] + # remove all source files that ended up being part of one of the dependencies + # we flatten the list of source files from all dependencies and + # then only add file to srcs if its not in that list + # (basically srcs = allSourcefiles - flatten(depSources.values()) + srcs = [f for f in allSourceFiles if f not in [item for sublist in depSources.values() for item in sublist]] + + # additional libraries + libraries = [self.prepare_lib(basename(lib)) for lib in self.resources.libraries] + sys_libs = [self.prepare_sys_lib(lib) for lib in self.toolchain.sys_libs] ctx = { 'name': self.project_name, 'target': self.target, 'sources': srcs, - 'libs': libs, + 'dependencies': depSources, 'libraries': libraries, 'ld_sys_libs': sys_libs, 'include_paths': sorted(list(set(self.resources.inc_dirs))), @@ -74,14 +95,15 @@ class CMake(Exporter): 'hex_files': self.resources.hex_files, 'ar': basename(self.toolchain.ar), 'cc': basename(self.toolchain.cc[0]), - 'cc_flags': " ".join(self.toolchain.cc[1:]), + 'cc_flags': " ".join(flag for flag in self.toolchain.cc[1:] if not flag == "-c"), 'cxx': basename(self.toolchain.cppc[0]), - 'cxx_flags': " ".join(self.toolchain.cppc[1:]), + 'cxx_flags': " ".join(flag for flag in self.toolchain.cppc[1:] if not flag == "-c"), 'asm': basename(self.toolchain.asm[0]), - 'asm_flags': " ".join(self.toolchain.asm[1:]), - 'symbols': self.toolchain.get_symbols(), + 'asm_flags': " ".join(flag for flag in self.toolchain.asm[1:] if not flag == "-c"), + 'symbols': sorted(self.toolchain.get_symbols()), 'ld': basename(self.toolchain.ld[0]), - 'ld_flags': " ".join(self.toolchain.ld[1:]), + # fix the missing underscore '_' (see + 'ld_flags': re.sub("--wrap,_(?!_)", "--wrap,__", " ".join(self.toolchain.ld[1:])), 'elf2bin': basename(self.toolchain.elf2bin), 'link_script_ext': self.toolchain.LINKER_EXT, 'link_script_option': self.LINK_SCRIPT_OPTION, @@ -90,21 +112,17 @@ class CMake(Exporter): } if hasattr(self.toolchain, "preproc"): - ctx['pp'] = " ".join(["\'" + part + "\'" for part - in ([basename(self.toolchain.preproc[0])] + - self.toolchain.preproc[1:] + - self.toolchain.ld[1:])]) + ctx['pp'] = basename(self.toolchain.preproc[0]) + ctx['pp_flags'] = " ".join(self.toolchain.preproc[1:] + + self.toolchain.ld[1:]) else: ctx['pp'] = None + ctx['pp_flags'] = None - for templatefile in ['cmake/%s.tmpl' % self.TEMPLATE]: - try: - self.gen_file(templatefile, ctx, 'CMakeLists.txt') - break - except TemplateNotFound: - pass - else: - raise NotSupportedException("This make tool is in development") + try: + self.gen_file('cmake/%s.tmpl' % self.TEMPLATE, ctx, 'CMakeLists.txt') + except TemplateNotFound: + pass @staticmethod def build(project_name, log_name="build_log.txt", cleanup=True): @@ -168,7 +186,6 @@ class GccArm(CMake): def prepare_sys_lib(libname): return "-l" + libname - # class Arm(CMake): # """ARM Compiler generic cmake target""" # LINK_SCRIPT_OPTION = "--scatter" From 5e669e0599dfe8717a3456be3a8c4780eef58f08 Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Sat, 18 Nov 2017 11:10:48 +0100 Subject: [PATCH 104/133] simplify the complicated removal of dependency sources add hex file generation --- tools/export/cmake/CMakeLists.txt.tmpl | 15 ++++++++++----- tools/export/cmake/__init__.py | 9 ++++----- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index 6f0920cadb..236ace8d61 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -30,7 +30,7 @@ SET(CMAKE_CXX_FLAGS "{{cxx_flags}} -include mbed_config.h") SET(CMAKE_ASM_FLAGS "{{asm_flags}} -include mbed_config.h") SET(CMAKE_CXX_LINK_FLAGS "{{ld_flags}}") {% if pp -%} -SET(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_INK_FLAGS} {{link_script_option}} ${CMAKE_BINARY_DIR}/{{name}}.link_script.ld ${LD_SYS_LIBS}") +SET(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} ${LD_SYS_LIBS} {{link_script_option}} ${CMAKE_BINARY_DIR}/{{name}}.link_script.ld") {%- endif %} ADD_DEFINITIONS( @@ -48,21 +48,26 @@ ADD_LIBRARY({{libname}} STATIC {% endfor %} # executable {{name}} -ADD_EXECUTABLE({{name}}.elf +ADD_EXECUTABLE({{name}} {% for src in sources %}{{src}} {% endfor %}) -TARGET_LINK_LIBRARIES({{name}}.elf - {% for libname in dependencies %}{{libname}} +TARGET_LINK_LIBRARIES({{name}} + {% for libname in dependencies.keys()|sort(reverse=true) %}{{libname}} {% endfor %}) {% if pp -%} -add_custom_command(TARGET {{name}}.elf PRE_LINK +add_custom_command(TARGET {{name}} PRE_LINK COMMAND "{{pp}}" {{pp_flags}} {{linker_script}} -o ${CMAKE_CURRENT_BINARY_DIR}/{{name}}.link_script.ld WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} BYPRODUCTS "${CMAKE_CURRENT_BINARY_DIR}/{{name}}.link_script.ld" ) {%- endif %} +add_custom_command(TARGET {{name}} POST_BUILD + COMMAND ${ELF2BIN} -O ihex $ $.hex + ) + + ########################################################################## # mbed-cli specific targets ########################################################################## diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index c6dde08e7e..f1bc47b076 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -73,10 +73,9 @@ class CMake(Exporter): depSources = {k: v for k, v in depSources.items() if len(v) != 0} # remove all source files that ended up being part of one of the dependencies - # we flatten the list of source files from all dependencies and - # then only add file to srcs if its not in that list - # (basically srcs = allSourcefiles - flatten(depSources.values()) - srcs = [f for f in allSourceFiles if f not in [item for sublist in depSources.values() for item in sublist]] + srcs = allSourceFiles + for dep in depSources.values(): + srcs.difference_update(dep) # additional libraries libraries = [self.prepare_lib(basename(lib)) for lib in self.resources.libraries] @@ -85,7 +84,7 @@ class CMake(Exporter): ctx = { 'name': self.project_name, 'target': self.target, - 'sources': srcs, + 'sources': sorted(srcs), 'dependencies': depSources, 'libraries': libraries, 'ld_sys_libs': sys_libs, From 441cd56acd23e0c19a223a8309c918bdc715e839 Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Fri, 12 Jan 2018 22:00:11 +0100 Subject: [PATCH 105/133] add handling of sub-dependencies, fix profile selection --- tools/export/cmake/CMakeLists.txt.tmpl | 5 +++-- tools/export/cmake/__init__.py | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index 236ace8d61..c67cf09059 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -51,6 +51,7 @@ ADD_LIBRARY({{libname}} STATIC ADD_EXECUTABLE({{name}} {% for src in sources %}{{src}} {% endfor %}) +SET_TARGET_PROPERTIES({{name}} PROPERTIES ENABLE_EXPORTS 1) TARGET_LINK_LIBRARIES({{name}} {% for libname in dependencies.keys()|sort(reverse=true) %}{{libname}} {% endfor %}) @@ -89,8 +90,8 @@ ELSE() ENDIF() # optional custom target to build via mbed-cli -ADD_CUSTOM_TARGET(mbed-cli-build EXCLUDE_FROM_ALL - COMMAND ${CMAKE_COMMAND} -E echo "mbed compile --build BUILD/${CMAKE_BUILD_TYPE} ${MBED_BUILD_PROFILE}" +ADD_CUSTOM_TARGET(mbed-cli-build + COMMAND ${CMAKE_COMMAND} -E echo "mbed compile --build BUILD/${CMAKE_BUILD_TYPE} --profile ${MBED_BUILD_PROFILE}" COMMAND mbed compile --build BUILD/${CMAKE_BUILD_TYPE} --profile ${MBED_BUILD_PROFILE} WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} SOURCES ${SOURCE_FILES} ${SYS_SOURCE_FILES}) diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index f1bc47b076..79e815d29d 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -67,7 +67,7 @@ class CMake(Exporter): # create a list of dependencies (mbed add ...) dependencies = [l[:-4] for l in self.resources.lib_refs] # separate the individual dependency source files into a map with the dep name as key and an array if files - depSources = {re.sub(r'^[.]/', '', l): + depSources = {re.sub(r'^[.]/', '', l).replace('/', '_'): sorted([f for f in allSourceFiles if f.startswith(l)]) for l in dependencies} # delete dependencies that have no source files (may happen if a sub-dependency is ignored by .mbedignore) depSources = {k: v for k, v in depSources.items() if len(v) != 0} From 49e5fd0b102520b319c23467263cca6b34fc94bd Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Fri, 12 Jan 2018 23:04:40 +0100 Subject: [PATCH 106/133] fix linker issue --- tools/export/cmake/CMakeLists.txt.tmpl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index c67cf09059..386ba3d817 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -55,6 +55,8 @@ SET_TARGET_PROPERTIES({{name}} PROPERTIES ENABLE_EXPORTS 1) TARGET_LINK_LIBRARIES({{name}} {% for libname in dependencies.keys()|sort(reverse=true) %}{{libname}} {% endfor %}) +# add dependencies for stdc++, c and nosys so the linker stage works +TARGET_LINK_LIBRARIES({{name}} stdc++ c nosys) {% if pp -%} add_custom_command(TARGET {{name}} PRE_LINK From e332d5c23df25b51946cd02b8e99e98c19ee76fc Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Fri, 12 Jan 2018 23:21:50 +0100 Subject: [PATCH 107/133] change linking stage (dependencies), print built hex file name --- tools/export/cmake/CMakeLists.txt.tmpl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index 386ba3d817..a466e05bfe 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -55,8 +55,8 @@ SET_TARGET_PROPERTIES({{name}} PROPERTIES ENABLE_EXPORTS 1) TARGET_LINK_LIBRARIES({{name}} {% for libname in dependencies.keys()|sort(reverse=true) %}{{libname}} {% endfor %}) -# add dependencies for stdc++, c and nosys so the linker stage works -TARGET_LINK_LIBRARIES({{name}} stdc++ c nosys) +# add syslibs dependencies to create the correct linker order +TARGET_LINK_LIBRARIES({{name}} {{ld_sys_libs|join(" ")}}) {% if pp -%} add_custom_command(TARGET {{name}} PRE_LINK @@ -68,6 +68,7 @@ add_custom_command(TARGET {{name}} PRE_LINK add_custom_command(TARGET {{name}} POST_BUILD COMMAND ${ELF2BIN} -O ihex $ $.hex + COMMAND ${CMAKE_COMMAND} -E echo "-- built: $.hex" ) From ca09a299d63df36e6d1db71692ad6e7cd10db939 Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Sat, 13 Jan 2018 11:25:22 +0100 Subject: [PATCH 108/133] add ci build operations --- tools/export/cmake/CMakeLists.txt.tmpl | 18 ++++++++++++---- tools/export/cmake/__init__.py | 30 +++++++++++++++++++++----- 2 files changed, 39 insertions(+), 9 deletions(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index a466e05bfe..5e0a6a4976 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -11,16 +11,26 @@ SET(CMAKE_CROSSCOMPILING TRUE) SET(CMAKE_C_COMPILER_WORKS TRUE) SET(CMAKE_CXX_COMPILER_WORKS TRUE) -SET(CMAKE_ASM_COMPILER_INIT "{{asm}}") -SET(CMAKE_C_COMPILER_INIT "{{cc}}") -SET(CMAKE_CXX_COMPILER_INIT "{{cxx}}") -SET(ELF2BIN "{{elf2bin}}") +# force cmake compilers +SET(CMAKE_ASM_COMPILER "{{asm}}") +SET(CMAKE_C_COMPILER "{{cc}}") +SET(CMAKE_CXX_COMPILER "{{cxx}}") +SET(ELF2BIN "{{elf2bin}}") {% if hex_files %} SET(SREC_CAT "srec_cat") {%- endif %} +# if the environment does not specify build type, set to Debug +IF(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE "Debug" + CACHE STRING "Choose the type of build, options are: Debug Release RelWithDebInfo MinSizeRel." + FORCE) +ENDIF() + # here starts the project PROJECT(cmake-{{name}} C CXX ASM) + +# uncomment below to have a verbose build process #SET(CMAKE_VERBOSE_MAKEFILE ON) SET(LD_SYS_LIBS "{%- block sys_libs -%} -Wl,--start-group {{ld_sys_libs|join(" ")}} {{libraries|join(" ")}} -Wl,--end-group {%- endblock -%}") diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index 79e815d29d..5d1387f04a 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -16,15 +16,14 @@ limitations under the License. """ import re import shutil -from os import remove -from os.path import splitext, basename, exists +from os import remove, getcwd, chdir, mkdir +from os.path import basename, exists from subprocess import Popen, PIPE from jinja2.exceptions import TemplateNotFound from tools.export.exporters import Exporter, apply_supported_whitelist from tools.targets import TARGET_MAP -from tools.utils import NotSupportedException class CMake(Exporter): @@ -126,14 +125,34 @@ class CMake(Exporter): @staticmethod def build(project_name, log_name="build_log.txt", cleanup=True): """ Build Make project """ - # > Make -j - cmd = ["make", "-j"] + + # change into our build directory + current_dir = getcwd() + if not exists("BUILD"): + mkdir("BUILD") + chdir("BUILD") + + # > run cmake initial command + cmd = ["cmake", ".."] # Build the project p = Popen(cmd, stdout=PIPE, stderr=PIPE) out, err = p.communicate() ret_code = p.returncode + if ret_code == 0: + # we create the cmake files inside BUILD, change into and run cmake + + # > run make -j + cmd = ["make", "-j"] + + p = Popen(cmd, stdout=PIPE, stderr=PIPE) + out, err = p.communicate() + ret_code = p.returncode + + # go back to the original directory + chdir(current_dir) + out_string = "=" * 10 + "STDOUT" + "=" * 10 + "\n" out_string += out out_string += "=" * 10 + "STDERR" + "=" * 10 + "\n" @@ -161,6 +180,7 @@ class CMake(Exporter): if exists('BUILD'): shutil.rmtree('BUILD') + if ret_code != 0: # Seems like something went wrong. return -1 From 0087bc28cbdc768bf54e26200d6454adce8a7296 Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Mon, 15 Jan 2018 15:51:43 +0100 Subject: [PATCH 109/133] add link library paths to build --- tools/export/cmake/CMakeLists.txt.tmpl | 8 ++++---- tools/export/cmake/__init__.py | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index 5e0a6a4976..7ffbb004a2 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -38,9 +38,9 @@ SET(LD_SYS_LIBS "{%- block sys_libs -%} -Wl,--start-group {{ld_sys_libs|join(" " SET(CMAKE_C_FLAGS "{{cc_flags}} -include mbed_config.h") SET(CMAKE_CXX_FLAGS "{{cxx_flags}} -include mbed_config.h") SET(CMAKE_ASM_FLAGS "{{asm_flags}} -include mbed_config.h") -SET(CMAKE_CXX_LINK_FLAGS "{{ld_flags}}") +SET(CMAKE_CXX_LINK_FLAGS "{{ld_flags}} {% for p in library_paths %} {{user_library_flag}}${CMAKE_CURRENT_SOURCE_DIR}/{{p}} {% endfor %}") {% if pp -%} -SET(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} ${LD_SYS_LIBS} {{link_script_option}} ${CMAKE_BINARY_DIR}/{{name}}.link_script.ld") +SET(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} ${LD_SYS_LIBS} {{link_script_option}} ${CMAKE_BINARY_DIR}/{{name}}_pp.link_script.ld") {%- endif %} ADD_DEFINITIONS( @@ -70,9 +70,9 @@ TARGET_LINK_LIBRARIES({{name}} {{ld_sys_libs|join(" ")}}) {% if pp -%} add_custom_command(TARGET {{name}} PRE_LINK - COMMAND "{{pp}}" {{pp_flags}} {{linker_script}} -o ${CMAKE_CURRENT_BINARY_DIR}/{{name}}.link_script.ld + COMMAND "{{pp}}" {{pp_flags}} {{linker_script}} -o ${CMAKE_CURRENT_BINARY_DIR}/{{name}}_pp.link_script.ld WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - BYPRODUCTS "${CMAKE_CURRENT_BINARY_DIR}/{{name}}.link_script.ld" + BYPRODUCTS "${CMAKE_CURRENT_BINARY_DIR}/{{name}}_pp.link_script.ld" ) {%- endif %} diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index 5d1387f04a..6a28cd9d54 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -88,7 +88,7 @@ class CMake(Exporter): 'libraries': libraries, 'ld_sys_libs': sys_libs, 'include_paths': sorted(list(set(self.resources.inc_dirs))), - 'library_paths': sorted(self.resources.lib_dirs), + 'library_paths': sorted([re.sub(r'^[.]/', '', l) for l in self.resources.lib_dirs]), 'linker_script': self.resources.linker_script, 'hex_files': self.resources.hex_files, 'ar': basename(self.toolchain.ar), From b055db154ba6e2d5789920f8d7b54d33036df33d Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Fri, 19 Jan 2018 13:14:35 +0100 Subject: [PATCH 110/133] use the normal name without cmake- prefix --- tools/export/cmake/CMakeLists.txt.tmpl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index 7ffbb004a2..7bf387f66a 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -28,7 +28,7 @@ IF(NOT CMAKE_BUILD_TYPE) ENDIF() # here starts the project -PROJECT(cmake-{{name}} C CXX ASM) +PROJECT({{name}} C CXX ASM) # uncomment below to have a verbose build process #SET(CMAKE_VERBOSE_MAKEFILE ON) From c983f0f891e198c29ab0ba324ba1eb0ce40f7c2d Mon Sep 17 00:00:00 2001 From: "Matthias L. Jugel" Date: Mon, 22 Jan 2018 18:19:24 +0100 Subject: [PATCH 111/133] flatten the compiled files list --- tools/export/cmake/CMakeLists.txt.tmpl | 10 --------- tools/export/cmake/__init__.py | 29 ++++++++------------------ 2 files changed, 9 insertions(+), 30 deletions(-) diff --git a/tools/export/cmake/CMakeLists.txt.tmpl b/tools/export/cmake/CMakeLists.txt.tmpl index 7bf387f66a..544e1af32e 100644 --- a/tools/export/cmake/CMakeLists.txt.tmpl +++ b/tools/export/cmake/CMakeLists.txt.tmpl @@ -50,21 +50,11 @@ INCLUDE_DIRECTORIES( {% for p in include_paths %}{{p}} {% endfor %}) -{% for libname,libsrcs in dependencies.items() %} -# target for library "{{libname}}" -ADD_LIBRARY({{libname}} STATIC - {% for libsrc in libsrcs %}{{libsrc}} - {% endfor %}) -{% endfor %} - # executable {{name}} ADD_EXECUTABLE({{name}} {% for src in sources %}{{src}} {% endfor %}) SET_TARGET_PROPERTIES({{name}} PROPERTIES ENABLE_EXPORTS 1) -TARGET_LINK_LIBRARIES({{name}} - {% for libname in dependencies.keys()|sort(reverse=true) %}{{libname}} - {% endfor %}) # add syslibs dependencies to create the correct linker order TARGET_LINK_LIBRARIES({{name}} {{ld_sys_libs|join(" ")}}) diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index 6a28cd9d54..9c1638e9d1 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -58,36 +58,26 @@ class CMake(Exporter): # get all source files including headers, adding headers allows IDEs to detect which files # belong to the project, otherwise headers may be greyed out and not work with inspection # (that is true for CLion and definitely for Visual Code) - allSourceFiles = set(self.resources.c_sources + - self.resources.cpp_sources + - self.resources.s_sources + - self.resources.headers) - - # create a list of dependencies (mbed add ...) - dependencies = [l[:-4] for l in self.resources.lib_refs] - # separate the individual dependency source files into a map with the dep name as key and an array if files - depSources = {re.sub(r'^[.]/', '', l).replace('/', '_'): - sorted([f for f in allSourceFiles if f.startswith(l)]) for l in dependencies} - # delete dependencies that have no source files (may happen if a sub-dependency is ignored by .mbedignore) - depSources = {k: v for k, v in depSources.items() if len(v) != 0} - - # remove all source files that ended up being part of one of the dependencies - srcs = allSourceFiles - for dep in depSources.values(): - srcs.difference_update(dep) + srcs = set(self.resources.c_sources + + self.resources.cpp_sources + + self.resources.s_sources + + self.resources.headers) + srcs = [re.sub(r'^[.]/', '', f) for f in srcs] # additional libraries libraries = [self.prepare_lib(basename(lib)) for lib in self.resources.libraries] sys_libs = [self.prepare_sys_lib(lib) for lib in self.toolchain.sys_libs] + # sort includes reverse, so the deepest dir comes first (ensures short includes) + includes = sorted([re.sub(r'^[.]/', '', l) for l in self.resources.inc_dirs], reverse=True) + ctx = { 'name': self.project_name, 'target': self.target, 'sources': sorted(srcs), - 'dependencies': depSources, 'libraries': libraries, 'ld_sys_libs': sys_libs, - 'include_paths': sorted(list(set(self.resources.inc_dirs))), + 'include_paths': includes, 'library_paths': sorted([re.sub(r'^[.]/', '', l) for l in self.resources.lib_dirs]), 'linker_script': self.resources.linker_script, 'hex_files': self.resources.hex_files, @@ -180,7 +170,6 @@ class CMake(Exporter): if exists('BUILD'): shutil.rmtree('BUILD') - if ret_code != 0: # Seems like something went wrong. return -1 From 47656776ddc1ba8c79b71b6c0086af7f014f5cdc Mon Sep 17 00:00:00 2001 From: Przemyslaw Stekiel Date: Wed, 13 Sep 2017 11:17:46 +0200 Subject: [PATCH 112/133] Add RTC time test. --- TESTS/mbed_drivers/rtc/main.cpp | 489 ++++++++++++++++++++++++++++++-- 1 file changed, 464 insertions(+), 25 deletions(-) diff --git a/TESTS/mbed_drivers/rtc/main.cpp b/TESTS/mbed_drivers/rtc/main.cpp index fae4d06e20..141dee2659 100644 --- a/TESTS/mbed_drivers/rtc/main.cpp +++ b/TESTS/mbed_drivers/rtc/main.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2017, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -16,41 +16,480 @@ */ #include "mbed.h" #include "greentea-client/test_env.h" -#include "unity/unity.h" -#include "utest/utest.h" +#include "unity.h" +#include "utest.h" +#include "rtos.h" +#include "rtc_api.h" + +#if !DEVICE_RTC +#error [NOT_SUPPORTED] test not supported +#endif using namespace utest::v1; -#define CUSTOM_TIME 1256729737 +/* On some boards RTC counter can not be + * Initialised with 0 value in such case + * drivers sets RTC counter to 1. */ +#define CUSTOM_TIME_0 1 +#define CUSTOM_TIME_1 1256729737 +#define CUSTOM_TIME_2 2147483637 -void test_case_rtc_strftime() { - greentea_send_kv("timestamp", CUSTOM_TIME); +#define DELAY_10_SEC 10 +#define MS_PER_SEC 1000 +#define RTC_DELTA 1 - char buffer[32] = {0}; - char kv_buff[64] = {0}; - set_time(CUSTOM_TIME); // Set RTC time to Wed, 28 Oct 2009 11:35:37 +static volatile int rtc_enabled_ret; +static volatile time_t rtc_time_val; +static volatile bool rtc_read_called; +static volatile bool rtc_write_called; +static volatile bool rtc_init_called; +static volatile bool rtc_isenabled_called; - for (int i=0; i<10; ++i) { - time_t seconds = time(NULL); - sprintf(kv_buff, "[%ld] ", seconds); - strftime(buffer, sizeof(buffer), "%Y-%m-%d %H:%M:%S %p", localtime(&seconds)); - strcat(kv_buff, buffer); - greentea_send_kv("rtc", kv_buff); - wait(1); - } +/* Stub of RTC read function. */ +static time_t read_rtc_stub(void) +{ + rtc_read_called = true; + + return rtc_time_val; +} + +/* Stub of RTC write function. */ +static void write_rtc_stub(time_t t) +{ + rtc_write_called = true; + + rtc_time_val = t; +} + +/* Stub of RTC init function. */ +static void init_rtc_stub(void) +{ + rtc_init_called = true; +} + +/* Stub of RTC isenabled function. */ +static int isenabled_rtc_stub(void) +{ + rtc_isenabled_called = true; + + return rtc_enabled_ret; +} + +/* This test verifies if attach_rtc provides availability to + * connect specific RTC driver functions. + * + * This is unit test to verify if correct functions are used + * to support RTC. + * + * Given specific RTC driver functions have been attached (stubs). + * When set_time/time functions are called. + * Then set_time/time functions use attached RTC functions. + */ +void test_attach_RTC_stub_funtions() +{ + time_t seconds = 0; + + /* Attache RTC read/write/init/isenabled stubs. */ + attach_rtc(read_rtc_stub, write_rtc_stub, init_rtc_stub, isenabled_rtc_stub); + + /* Init stub variables/set to unexpected. */ + rtc_write_called = false; + rtc_init_called = false; + + /* Call set_time() function. We expect that init and write RTC stubs + * will be executed. + */ + set_time(CUSTOM_TIME_1); + + /* Verify results. */ + TEST_ASSERT_EQUAL(true, rtc_write_called); + TEST_ASSERT_EQUAL(true, rtc_init_called); + + /* Init stub variables/set to unexpected. */ + rtc_time_val = CUSTOM_TIME_1; + rtc_enabled_ret = true; + rtc_isenabled_called = false; + rtc_read_called = false; + + /* Call time() function. We expect that isenabled and read RTC stubs + * are be executed. + */ + time(NULL); + + /* Verify results. */ + TEST_ASSERT_EQUAL(true, rtc_isenabled_called); + TEST_ASSERT_EQUAL(true, rtc_read_called); + + /* This part of the test can be executed only on RTC devices. */ + + /* Restore env. */ + attach_rtc(rtc_read, rtc_write, rtc_init, rtc_isenabled); + + /* Set to unexpected. */ + rtc_write_called = false; + rtc_init_called = false; + rtc_isenabled_called = false; + rtc_init_called = false; + + /* Set time. */ + set_time(CUSTOM_TIME_1); + + /* Get time. */ + seconds = time(NULL); + + /* Stub RTC functions should not be called now. */ + TEST_ASSERT_EQUAL(false, rtc_isenabled_called); + TEST_ASSERT_EQUAL(false, rtc_init_called); + TEST_ASSERT_EQUAL(false, rtc_write_called); + TEST_ASSERT_EQUAL(false, rtc_init_called); + + /* Check if time has been successfully set and retrieved. */ + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, seconds); +} + +/* This test verifies if attach_rtc provides availability to + * connect specific RTC driver functions. + * + * This is unit test to verify if correct functions are used + * to support RTC. + * + * Given specific RTC driver functions have been attached (original). + * When set_time/time functions are called. + * Then set_time/time functions use attached RTC functions. + */ +void test_attach_RTC_org_funtions() +{ + time_t seconds = 0; + + /* Attache original driver functions. */ + attach_rtc(rtc_read, rtc_write, rtc_init, rtc_isenabled); + + /* Set to unexpected. */ + rtc_write_called = false; + rtc_init_called = false; + rtc_isenabled_called = false; + rtc_init_called = false; + + /* Set time. */ + set_time(CUSTOM_TIME_1); + + /* Get time. */ + seconds = time(NULL); + + /* Stub RTC functions should not be called now. */ + TEST_ASSERT_EQUAL(false, rtc_isenabled_called); + TEST_ASSERT_EQUAL(false, rtc_init_called); + TEST_ASSERT_EQUAL(false, rtc_write_called); + TEST_ASSERT_EQUAL(false, rtc_init_called); + + /* Check if time has been successfully set and retrieved. */ + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, seconds); +} + +/* This test verifies if time() function returns + * current time when all RTC functions are + * defined and RTC is enabled. + * + * Note: Stubs are used instead of original RTC functions. + * + * Given environment has RTC functions defined and RTC is enabled. + * When time() functions is called. + * Then current time is returned. + */ +void test_time_RTC_func_defined_RTC_is_enabled() +{ + time_t seconds = 0; + + /* Attache RTC read/write/init/isenabled stubs. */ + attach_rtc(read_rtc_stub, write_rtc_stub, init_rtc_stub, isenabled_rtc_stub); + + /* Simulate that RTC is enabled. */ + rtc_enabled_ret = true; + + /* Simulate current time. */ + rtc_time_val = CUSTOM_TIME_1; + + /* Try to get current time. */ + seconds = time(NULL); + + /* Check if expected value has been returned. */ + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, seconds); +} + +/* This test verifies if time() function resets time + * when RTC functions are defined and RTC is disabled. + * + * Note: Stubs are used instead of original RTC functions. + * + * Given environment has RTC functions defined and RTC is disabled. + * When time() functions is called. + * Then function result is 0. + */ +void test_time_RTC_func_defined_RTC_is_disabled() +{ + time_t seconds = 0; + + /* Attache RTC read/write/init/isenabled stubs. */ + attach_rtc(read_rtc_stub, write_rtc_stub, init_rtc_stub, isenabled_rtc_stub); + + /* Simulate that RTC is disabled. */ + rtc_enabled_ret = false; + + /* Simulate current time. */ + rtc_time_val = CUSTOM_TIME_1; + + /* Try to get current time. */ + seconds = time(NULL); + + /* Check if expected value has been returned. */ + TEST_ASSERT_EQUAL(0, seconds); +} + +/* This test verifies if time() function can be successfully + * executed when isenabled RTC function is undefined. + * + * Note: Stubs are used instead of original RTC functions. + * + * Given environment has isenabled RTC function undefined. + * When time() functions is called. + * Then current time is returned. + */ +void test_time_isenabled_RTC_func_undefined() +{ + time_t seconds = 0; + + /* Attache RTC read/write/init stubs. */ + attach_rtc(read_rtc_stub, write_rtc_stub, init_rtc_stub, NULL); + + /* Simulate current time. */ + rtc_time_val = CUSTOM_TIME_1; + + /* Try to get current time. */ + seconds = time(NULL); + + /* Check if expected value has been returned. */ + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, seconds); +} + +/* This test verifies if time() function returns -1 if + * read RTC function is undefined. + * + * Note: Stubs are used instead of original RTC functions. + * + * Given environment has read RTC function undefined. + * When time() functions is called. + * Then -1 is returned. + */ +void test_time_read_RTC_func_undefined() +{ + time_t seconds = 0; + + /* Attache RTC write/init/isenabled stubs. */ + attach_rtc(NULL, write_rtc_stub, init_rtc_stub, isenabled_rtc_stub); + + /* Simulate current time. */ + rtc_time_val = CUSTOM_TIME_1; + + /* Try to get current time. */ + seconds = time(NULL); + + /* Check if expected value has been returned. */ + TEST_ASSERT_EQUAL((time_t)-1, seconds); +} + +/* This test verifies if time() function stores + * the result in given time buffer (if specified). + * + * Note: Stubs are used instead original RTC functions. + * Other test cases calls time() routine with + * undefined time buffer. + * + * Given environment has all RTC function defined, RTC is enabled and time buffer is passed to time() function. + * When time() functions is called. + * Then current time is stored in the specified buffer. + */ +void test_time_called_with_param() +{ + time_t seconds = 0; + time_t buffer = 0; + + /* Attache RTC read/write/init/isenabled stubs. */ + attach_rtc(read_rtc_stub, write_rtc_stub, init_rtc_stub, isenabled_rtc_stub); + + /* Simulate that RTC is enabled. */ + rtc_enabled_ret = true; + + /* Simulate current time. */ + rtc_time_val = CUSTOM_TIME_1; + + /* Try to get current time. */ + seconds = time(&buffer); + + /* Check if expected value has been returned. */ + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, seconds); + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, buffer); +} + +/* This test verifies if set_time() function inits the RTC + * and writes current time if RTC functions are defined. + * + * Note: Stubs are used instead of original RTC functions. + * + * Given environment has RTC functions defined. + * When set_time() functions is called. + * Then function initialises RTC and sets RTC time. + */ +void test_set_time_RTC_func_defined() +{ + /* Attache RTC read/write/init/isenabled stubs. */ + attach_rtc(read_rtc_stub, write_rtc_stub, init_rtc_stub, isenabled_rtc_stub); + + /* Set to unexpected. */ + rtc_time_val = 123; + rtc_init_called = false; + + /* Set current time. */ + rtc_time_val = 123; + + /* Set new RTC time. */ + set_time(CUSTOM_TIME_1); + + /* Check if RTC init has been performed and RTC time has been updated. */ + TEST_ASSERT_EQUAL(true, rtc_init_called); + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, time(NULL)); + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, rtc_time_val); +} + +/* This test verifies if set_time() function can be + * successfully executed when init RTC function is undefined. + * + * Note: Stubs are used instead of original RTC functions. + * + * Given environment has init RTC function undefined. + * When set_time() functions is called. + * Then function sets RTC time. + */ +void test_set_time_init_RTC_func_undefined() +{ + /* Attache RTC read/write/isenabled stubs. */ + attach_rtc(read_rtc_stub, write_rtc_stub, NULL, isenabled_rtc_stub); + + /* Set to unexpected. */ + rtc_time_val = 123; + + /* Set new RTC time. */ + set_time(CUSTOM_TIME_1); + + /* Check if RTC time has been updated. */ + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, time(NULL)); + TEST_ASSERT_EQUAL(CUSTOM_TIME_1, rtc_time_val); +} + +/* This test verifies if set_time() function can be + * successfully executed when write RTC function is undefined. + * + * Note: Stubs are used instead original RTC functions. + * + * Given environemt has write RTC function undefined. + * When set_time() function is called. + * Then function inits RTC and does not modify RTC time. + */ +void test_set_time_write_RTC_func_undefined() +{ + /* Attache RTC read/write/init/isenabled stubs. */ + attach_rtc(read_rtc_stub, NULL, init_rtc_stub, isenabled_rtc_stub); + + /* Set to unexpected. */ + rtc_time_val = 123; + rtc_init_called = false; + + /* Set new RTC time. */ + set_time(CUSTOM_TIME_1); + + /* Check if RTC has been initialized and RTC time has not been updated. */ + TEST_ASSERT_EQUAL(true, rtc_init_called); + TEST_ASSERT_EQUAL(123, time(NULL)); + TEST_ASSERT_EQUAL(123, rtc_time_val); +} + +/* This test verifies if RTC time can be successfully set. + * + * Note: Original RTC functions are used in this test. + * + * Given environment has RTC available. + * When set_time() functions is called. + * Then RTC time is retrieved. + */ +template +void test_functional_set() +{ + /* Set original RTC functions. */ + attach_rtc(rtc_read, rtc_write, rtc_init, rtc_isenabled); + + /* Set new RTC time. */ + set_time(timeValue); + + /* Get current time and verify that new value has been set. */ + TEST_ASSERT_EQUAL(timeValue, time(NULL)); +} + +/* This test verifies if RTC counts seconds. + * + * Note: Original RTC functions are used in this test. + * + * Given RTC has time set. + * When some time has passed (seconds). + * Then RTC time is updated. + */ +void test_functional_count() +{ + time_t seconds = 0; + + /* Set original RTC functions. */ + attach_rtc(rtc_read, rtc_write, rtc_init, rtc_isenabled); + + /* Set new RTC time. */ + set_time(CUSTOM_TIME_2); + + /* Wait 10 sec. */ + wait_ms(DELAY_10_SEC * MS_PER_SEC); + + /* Get time. */ + seconds = time(NULL); + + /* Verify that RTC counts seconds. */ + TEST_ASSERT_UINT_WITHIN(RTC_DELTA, (unsigned int)seconds, CUSTOM_TIME_2 + DELAY_10_SEC); +} + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(20, "default_auto"); + return verbose_test_setup_handler(number_of_cases); } Case cases[] = { - Case("RTC strftime", test_case_rtc_strftime), + Case("Unit Test: attach stub RTC functions.", test_attach_RTC_stub_funtions), + Case("Unit Test: attach original RTC functions.", test_attach_RTC_org_funtions), + + Case("Unit Test: time() - RTC functions are defined, RTC is enabled.", test_time_RTC_func_defined_RTC_is_enabled), + Case("Unit Test: time() - RTC functions are defined, RTC is disabled.", test_time_RTC_func_defined_RTC_is_disabled), + Case("Unit Test: time() - isenabled RTC function is undefined.", test_time_isenabled_RTC_func_undefined), + Case("Unit Test: time() - read RTC function is undefined.", test_time_read_RTC_func_undefined), + Case("Unit Test: time() - result is stored in given buffer.", test_time_called_with_param), + + Case("Unit Test: set_time() - RTC functions are defined.", test_set_time_RTC_func_defined), + Case("Unit Test: set_time() - init RTC function is undefined.", test_set_time_init_RTC_func_undefined), + Case("Unit Test: set_time() - write RTC function is undefined.", test_set_time_write_RTC_func_undefined), + + Case("Functional Test: set time - CUSTOM_TIME_0.", test_functional_set), + Case("Functional Test: set time - CUSTOM_TIME_1.", test_functional_set), + Case("Functional Test: set time - CUSTOM_TIME_2.", test_functional_set), + + Case("Functional Test: RTC counts seconds.", test_functional_count), }; -utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(20, "rtc_auto"); - return greentea_test_setup_handler(number_of_cases); -} - -Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); +Specification specification(test_setup, cases); int main() { - Harness::run(specification); + return !Harness::run(specification); } From baada694429fe21c96a27193b99d8e6ff1afcc5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cruz=20Monrreal=20II=C2=89?= Date: Sat, 27 Jan 2018 00:58:05 -0600 Subject: [PATCH 113/133] Update Mbed version block for patch release --- mbed.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mbed.h b/mbed.h index fd27fba1a2..07a803a1dd 100644 --- a/mbed.h +++ b/mbed.h @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 158 +#define MBED_LIBRARY_VERSION 159 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 7 -#define MBED_PATCH_VERSION 3 +#define MBED_PATCH_VERSION 4 #else // mbed 2 From d6db9b5263eb52d73f2e1f423959ad399b71a069 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Thu, 11 Jan 2018 16:27:33 -0600 Subject: [PATCH 114/133] littlefs: Fixed file truncation without writes In the open call, the LFS_O_TRUNC flag was correctly zeroing the file, but it wasn't actually writing the change out to disk. This went unnoticed because in the cases where the truncate was followed by a file write, the updated contents would be written out correctly. Marking the file as dirty if the file isn't already truncated fixes the problem with the least impact. Also added better test cases around truncating files. --- features/filesystem/littlefs/littlefs/lfs.c | 3 ++ .../littlefs/littlefs/tests/test_files.sh | 29 +++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/features/filesystem/littlefs/littlefs/lfs.c b/features/filesystem/littlefs/littlefs/lfs.c index f83624ec92..9678181fd3 100644 --- a/features/filesystem/littlefs/littlefs/lfs.c +++ b/features/filesystem/littlefs/littlefs/lfs.c @@ -1261,6 +1261,9 @@ int lfs_file_open(lfs_t *lfs, lfs_file_t *file, file->pos = 0; if (flags & LFS_O_TRUNC) { + if (file->size != 0) { + file->flags |= LFS_F_DIRTY; + } file->head = 0xffffffff; file->size = 0; } diff --git a/features/filesystem/littlefs/littlefs/tests/test_files.sh b/features/filesystem/littlefs/littlefs/tests/test_files.sh index 6086107c89..444346371b 100755 --- a/features/filesystem/littlefs/littlefs/tests/test_files.sh +++ b/features/filesystem/littlefs/littlefs/tests/test_files.sh @@ -34,7 +34,8 @@ tests/test.py << TEST lfs_size_t chunk = 31; srand(0); lfs_mount(&lfs, &cfg) => 0; - lfs_file_open(&lfs, &file[0], "$2", LFS_O_WRONLY | LFS_O_CREAT) => 0; + lfs_file_open(&lfs, &file[0], "$2", + ${3:-LFS_O_WRONLY | LFS_O_CREAT | LFS_O_TRUNC}) => 0; for (lfs_size_t i = 0; i < size; i += chunk) { chunk = (chunk < size - i) ? chunk : size - i; for (lfs_size_t b = 0; b < chunk; b++) { @@ -53,7 +54,10 @@ tests/test.py << TEST lfs_size_t chunk = 29; srand(0); lfs_mount(&lfs, &cfg) => 0; - lfs_file_open(&lfs, &file[0], "$2", LFS_O_RDONLY) => 0; + lfs_stat(&lfs, "$2", &info) => 0; + info.type => LFS_TYPE_REG; + info.size => size; + lfs_file_open(&lfs, &file[0], "$2", ${3:-LFS_O_RDONLY}) => 0; for (lfs_size_t i = 0; i < size; i += chunk) { chunk = (chunk < size - i) ? chunk : size - i; lfs_file_read(&lfs, &file[0], buffer, chunk) => chunk; @@ -78,10 +82,27 @@ echo "--- Large file test ---" w_test $LARGESIZE largeavacado r_test $LARGESIZE largeavacado +echo "--- Zero file test ---" +w_test 0 noavacado +r_test 0 noavacado + +echo "--- Truncate small test ---" +w_test $SMALLSIZE mediumavacado +r_test $SMALLSIZE mediumavacado +w_test $MEDIUMSIZE mediumavacado +r_test $MEDIUMSIZE mediumavacado + +echo "--- Truncate zero test ---" +w_test $SMALLSIZE noavacado +r_test $SMALLSIZE noavacado +w_test 0 noavacado +r_test 0 noavacado + echo "--- Non-overlap check ---" r_test $SMALLSIZE smallavacado r_test $MEDIUMSIZE mediumavacado r_test $LARGESIZE largeavacado +r_test 0 noavacado echo "--- Dir check ---" tests/test.py << TEST @@ -105,6 +126,10 @@ tests/test.py << TEST strcmp(info.name, "largeavacado") => 0; info.type => LFS_TYPE_REG; info.size => $LARGESIZE; + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, "noavacado") => 0; + info.type => LFS_TYPE_REG; + info.size => 0; lfs_dir_read(&lfs, &dir[0], &info) => 0; lfs_dir_close(&lfs, &dir[0]) => 0; lfs_unmount(&lfs) => 0; From 5fa45e827ae90830a7674c544b4883d67db4f83f Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 5 Jan 2018 17:29:05 +0100 Subject: [PATCH 115/133] L4 ST CUBE V1.11.0 Update to STM32CubeL4 V1.11.0 Conflicts solved: targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h --- .../TARGET_STM32L432xC/device/stm32l432xx.h | 7869 ++++++------ .../TARGET_STM32L432xC/device/stm32l4xx.h | 29 +- .../device/system_stm32l4xx.h | 2 - .../TARGET_STM32L433xC/device/stm32l433xx.h | 8491 +++++++------ .../TARGET_STM32L433xC/device/stm32l4xx.h | 29 +- .../device/system_stm32l4xx.h | 2 - .../TARGET_STM32L475xG/device/stm32l475xx.h | 9830 +++++++-------- .../TARGET_STM32L475xG/device/stm32l4xx.h | 29 +- .../device/system_stm32l4xx.h | 2 - .../TARGET_STM32L476xG/device/stm32l476xx.h | 9888 +++++++-------- .../TARGET_STM32L476xG/device/stm32l4xx.h | 29 +- .../device/system_stm32l4xx.h | 2 - .../TARGET_STM32L486xG/device/stm32l486xx.h | 9976 +++++++-------- .../TARGET_STM32L486xG/device/stm32l4xx.h | 21 +- .../device/system_stm32l4xx.h | 2 - .../TARGET_STM32L496xG/device/stm32l496xx.h | 10525 ++++++++-------- .../TARGET_STM32L496xG/device/stm32l4xx.h | 21 +- .../device/system_stm32l4xx.h | 2 - .../device/Release_Notes_stm32l4xx_hal.html | 94 +- .../TARGET_STM32L4/device/stm32_hal_legacy.h | 645 +- .../TARGET_STM32L4/device/stm32l4xx_hal.c | 18 +- .../TARGET_STM32L4/device/stm32l4xx_hal.h | 40 +- .../TARGET_STM32L4/device/stm32l4xx_hal_adc.c | 1433 ++- .../TARGET_STM32L4/device/stm32l4xx_hal_adc.h | 1418 ++- .../device/stm32l4xx_hal_adc_ex.c | 656 +- .../device/stm32l4xx_hal_adc_ex.h | 1078 +- .../TARGET_STM32L4/device/stm32l4xx_hal_can.c | 2719 ++-- .../TARGET_STM32L4/device/stm32l4xx_hal_can.h | 762 +- .../device/stm32l4xx_hal_can_legacy.h | 769 ++ .../device/stm32l4xx_hal_comp.c | 122 +- .../device/stm32l4xx_hal_comp.h | 254 +- .../device/stm32l4xx_hal_conf.h | 31 +- .../device/stm32l4xx_hal_cortex.c | 51 +- .../device/stm32l4xx_hal_cortex.h | 38 +- .../TARGET_STM32L4/device/stm32l4xx_hal_crc.c | 237 +- .../TARGET_STM32L4/device/stm32l4xx_hal_crc.h | 50 +- .../device/stm32l4xx_hal_crc_ex.c | 4 +- .../device/stm32l4xx_hal_crc_ex.h | 14 +- .../device/stm32l4xx_hal_cryp.c | 6 +- .../device/stm32l4xx_hal_cryp.h | 8 +- .../device/stm32l4xx_hal_cryp_ex.c | 62 +- .../device/stm32l4xx_hal_cryp_ex.h | 6 +- .../TARGET_STM32L4/device/stm32l4xx_hal_dac.c | 82 +- .../TARGET_STM32L4/device/stm32l4xx_hal_dac.h | 57 +- .../device/stm32l4xx_hal_dac_ex.c | 20 +- .../device/stm32l4xx_hal_dac_ex.h | 45 +- .../device/stm32l4xx_hal_dcmi.c | 17 +- .../device/stm32l4xx_hal_dcmi.h | 9 +- .../TARGET_STM32L4/device/stm32l4xx_hal_def.h | 6 +- .../device/stm32l4xx_hal_dfsdm.c | 307 +- .../device/stm32l4xx_hal_dfsdm.h | 69 +- .../device/stm32l4xx_hal_dfsdm_ex.c | 151 + .../device/stm32l4xx_hal_dfsdm_ex.h | 109 + .../TARGET_STM32L4/device/stm32l4xx_hal_dma.c | 501 +- .../TARGET_STM32L4/device/stm32l4xx_hal_dma.h | 203 +- .../device/stm32l4xx_hal_dma2d.c | 30 +- .../device/stm32l4xx_hal_dma2d.h | 68 +- .../device/stm32l4xx_hal_dma_ex.c | 319 + .../device/stm32l4xx_hal_dma_ex.h | 298 + .../TARGET_STM32L4/device/stm32l4xx_hal_dsi.c | 2379 ++++ .../TARGET_STM32L4/device/stm32l4xx_hal_dsi.h | 1296 ++ .../device/stm32l4xx_hal_firewall.c | 137 +- .../device/stm32l4xx_hal_firewall.h | 2 - .../device/stm32l4xx_hal_flash.c | 36 +- .../device/stm32l4xx_hal_flash.h | 139 +- .../device/stm32l4xx_hal_flash_ex.c | 197 +- .../device/stm32l4xx_hal_flash_ex.h | 52 +- .../device/stm32l4xx_hal_flash_ramfunc.c | 118 +- .../device/stm32l4xx_hal_flash_ramfunc.h | 5 +- .../device/stm32l4xx_hal_gfxmmu.c | 567 + .../device/stm32l4xx_hal_gfxmmu.h | 306 + .../device/stm32l4xx_hal_gpio.c | 2 - .../device/stm32l4xx_hal_gpio.h | 2 - .../device/stm32l4xx_hal_gpio_ex.h | 158 +- .../device/stm32l4xx_hal_hash.c | 59 +- .../device/stm32l4xx_hal_hash.h | 6 +- .../device/stm32l4xx_hal_hash_ex.c | 6 +- .../device/stm32l4xx_hal_hash_ex.h | 6 +- .../TARGET_STM32L4/device/stm32l4xx_hal_hcd.c | 8 +- .../TARGET_STM32L4/device/stm32l4xx_hal_hcd.h | 8 +- .../TARGET_STM32L4/device/stm32l4xx_hal_i2c.c | 795 +- .../TARGET_STM32L4/device/stm32l4xx_hal_i2c.h | 62 +- .../device/stm32l4xx_hal_i2c_ex.c | 28 +- .../device/stm32l4xx_hal_i2c_ex.h | 10 +- .../device/stm32l4xx_hal_irda.c | 278 +- .../device/stm32l4xx_hal_irda.h | 302 +- .../device/stm32l4xx_hal_irda_ex.h | 10 +- .../device/stm32l4xx_hal_iwdg.c | 2 - .../device/stm32l4xx_hal_iwdg.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_hal_lcd.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_hal_lcd.h | 2 - .../device/stm32l4xx_hal_lptim.c | 2 - .../device/stm32l4xx_hal_lptim.h | 2 - .../device/stm32l4xx_hal_ltdc.c | 1896 +++ .../device/stm32l4xx_hal_ltdc.h | 649 + .../device/stm32l4xx_hal_ltdc_ex.c | 167 + .../device/stm32l4xx_hal_ltdc_ex.h | 101 + .../device/stm32l4xx_hal_nand.c | 6 +- .../device/stm32l4xx_hal_nand.h | 6 +- .../TARGET_STM32L4/device/stm32l4xx_hal_nor.c | 6 +- .../TARGET_STM32L4/device/stm32l4xx_hal_nor.h | 6 +- .../device/stm32l4xx_hal_opamp.c | 2 - .../device/stm32l4xx_hal_opamp.h | 33 +- .../device/stm32l4xx_hal_opamp_ex.c | 5 +- .../device/stm32l4xx_hal_opamp_ex.h | 6 +- .../device/stm32l4xx_hal_ospi.c | 2564 ++++ .../device/stm32l4xx_hal_ospi.h | 968 ++ .../TARGET_STM32L4/device/stm32l4xx_hal_pcd.c | 8 +- .../TARGET_STM32L4/device/stm32l4xx_hal_pcd.h | 8 +- .../device/stm32l4xx_hal_pcd_ex.c | 34 +- .../device/stm32l4xx_hal_pcd_ex.h | 8 +- .../TARGET_STM32L4/device/stm32l4xx_hal_pwr.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_hal_pwr.h | 2 - .../device/stm32l4xx_hal_pwr_ex.c | 147 +- .../device/stm32l4xx_hal_pwr_ex.h | 30 +- .../device/stm32l4xx_hal_qspi.c | 311 +- .../device/stm32l4xx_hal_qspi.h | 46 +- .../TARGET_STM32L4/device/stm32l4xx_hal_rcc.c | 508 +- .../TARGET_STM32L4/device/stm32l4xx_hal_rcc.h | 825 +- .../device/stm32l4xx_hal_rcc_ex.c | 961 +- .../device/stm32l4xx_hal_rcc_ex.h | 1039 +- .../TARGET_STM32L4/device/stm32l4xx_hal_rng.c | 36 +- .../TARGET_STM32L4/device/stm32l4xx_hal_rng.h | 62 +- .../TARGET_STM32L4/device/stm32l4xx_hal_rtc.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_hal_rtc.h | 14 +- .../device/stm32l4xx_hal_rtc_ex.c | 2 - .../device/stm32l4xx_hal_rtc_ex.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_hal_sai.c | 260 +- .../TARGET_STM32L4/device/stm32l4xx_hal_sai.h | 94 +- .../device/stm32l4xx_hal_sai_ex.c | 142 + .../device/stm32l4xx_hal_sai_ex.h | 132 + .../TARGET_STM32L4/device/stm32l4xx_hal_sd.c | 542 +- .../TARGET_STM32L4/device/stm32l4xx_hal_sd.h | 28 +- .../device/stm32l4xx_hal_sd_ex.c | 550 + .../device/stm32l4xx_hal_sd_ex.h | 144 + .../device/stm32l4xx_hal_smartcard.c | 889 +- .../device/stm32l4xx_hal_smartcard.h | 484 +- .../device/stm32l4xx_hal_smartcard_ex.c | 297 +- .../device/stm32l4xx_hal_smartcard_ex.h | 224 +- .../device/stm32l4xx_hal_smbus.c | 896 +- .../device/stm32l4xx_hal_smbus.h | 144 +- .../TARGET_STM32L4/device/stm32l4xx_hal_spi.c | 302 +- .../TARGET_STM32L4/device/stm32l4xx_hal_spi.h | 214 +- .../device/stm32l4xx_hal_spi_ex.c | 8 +- .../device/stm32l4xx_hal_spi_ex.h | 2 - .../device/stm32l4xx_hal_sram.c | 6 +- .../device/stm32l4xx_hal_sram.h | 6 +- .../device/stm32l4xx_hal_swpmi.c | 2 - .../device/stm32l4xx_hal_swpmi.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_hal_tim.c | 619 +- .../TARGET_STM32L4/device/stm32l4xx_hal_tim.h | 304 +- .../device/stm32l4xx_hal_tim_ex.c | 331 +- .../device/stm32l4xx_hal_tim_ex.h | 87 +- .../TARGET_STM32L4/device/stm32l4xx_hal_tsc.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_hal_tsc.h | 2 - .../device/stm32l4xx_hal_uart.c | 1783 ++- .../device/stm32l4xx_hal_uart.h | 817 +- .../device/stm32l4xx_hal_uart_ex.c | 592 +- .../device/stm32l4xx_hal_uart_ex.h | 165 +- .../device/stm32l4xx_hal_usart.c | 1463 ++- .../device/stm32l4xx_hal_usart.h | 568 +- .../device/stm32l4xx_hal_usart_ex.c | 551 + .../device/stm32l4xx_hal_usart_ex.h | 160 +- .../device/stm32l4xx_hal_wwdg.c | 2 - .../device/stm32l4xx_hal_wwdg.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_adc.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_adc.h | 305 +- .../TARGET_STM32L4/device/stm32l4xx_ll_bus.h | 221 +- .../TARGET_STM32L4/device/stm32l4xx_ll_comp.c | 62 +- .../TARGET_STM32L4/device/stm32l4xx_ll_comp.h | 28 +- .../device/stm32l4xx_ll_cortex.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_crc.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_crc.h | 23 +- .../TARGET_STM32L4/device/stm32l4xx_ll_crs.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_crs.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_dac.c | 19 +- .../TARGET_STM32L4/device/stm32l4xx_ll_dac.h | 33 +- .../TARGET_STM32L4/device/stm32l4xx_ll_dma.c | 35 +- .../TARGET_STM32L4/device/stm32l4xx_ll_dma.h | 419 +- .../device/stm32l4xx_ll_dma2d.c | 33 +- .../device/stm32l4xx_ll_dma2d.h | 121 +- .../device/stm32l4xx_ll_dmamux.h | 1795 +++ .../TARGET_STM32L4/device/stm32l4xx_ll_exti.c | 10 +- .../TARGET_STM32L4/device/stm32l4xx_ll_exti.h | 41 +- .../TARGET_STM32L4/device/stm32l4xx_ll_fmc.c | 92 +- .../TARGET_STM32L4/device/stm32l4xx_ll_fmc.h | 41 +- .../TARGET_STM32L4/device/stm32l4xx_ll_gpio.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_gpio.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_i2c.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_i2c.h | 24 +- .../TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h | 2 - .../device/stm32l4xx_ll_lptim.c | 38 +- .../device/stm32l4xx_ll_lptim.h | 2 - .../device/stm32l4xx_ll_lpuart.c | 37 +- .../device/stm32l4xx_ll_lpuart.h | 711 +- .../device/stm32l4xx_ll_opamp.c | 2 - .../device/stm32l4xx_ll_opamp.h | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_pwr.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_pwr.h | 199 +- .../TARGET_STM32L4/device/stm32l4xx_ll_rcc.c | 387 +- .../TARGET_STM32L4/device/stm32l4xx_ll_rcc.h | 1775 ++- .../TARGET_STM32L4/device/stm32l4xx_ll_rng.c | 50 +- .../TARGET_STM32L4/device/stm32l4xx_ll_rng.h | 79 +- .../TARGET_STM32L4/device/stm32l4xx_ll_rtc.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_rtc.h | 29 +- .../device/stm32l4xx_ll_sdmmc.c | 90 +- .../device/stm32l4xx_ll_sdmmc.h | 199 +- .../TARGET_STM32L4/device/stm32l4xx_ll_spi.c | 2 - .../TARGET_STM32L4/device/stm32l4xx_ll_spi.h | 2 - .../device/stm32l4xx_ll_swpmi.c | 2 - .../device/stm32l4xx_ll_swpmi.h | 2 - .../device/stm32l4xx_ll_system.h | 52 +- .../TARGET_STM32L4/device/stm32l4xx_ll_tim.c | 54 +- .../TARGET_STM32L4/device/stm32l4xx_ll_tim.h | 139 +- .../device/stm32l4xx_ll_usart.c | 41 +- .../device/stm32l4xx_ll_usart.h | 968 +- .../TARGET_STM32L4/device/stm32l4xx_ll_usb.c | 8 +- .../TARGET_STM32L4/device/stm32l4xx_ll_usb.h | 8 +- .../device/stm32l4xx_ll_utils.c | 213 +- .../device/stm32l4xx_ll_utils.h | 18 +- .../TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h | 2 - 221 files changed, 68846 insertions(+), 39408 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h index 984f5abf52..5dc42a0c10 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l432xx.h * @author MCD Application Team - * @version V1.3.1 - * @date 21-April-2017 * @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File. * * This file contains: @@ -321,7 +319,7 @@ typedef struct /** * @brief Clock Recovery System */ -typedef struct +typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ @@ -574,7 +572,7 @@ typedef struct uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ } PWR_TypeDef; @@ -741,12 +739,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; @@ -865,42 +861,42 @@ typedef struct uint16_t RESERVED5; /*!< Reserved, 0x2A */ } USART_TypeDef; -/** +/** * @brief Universal Serial Bus Full Speed Device */ - + typedef struct { - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t RESERVEDC; /*!< Reserved */ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ - __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t RESERVEDD; /*!< Reserved */ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ - __IO uint16_t RESERVEDE; /*!< Reserved */ + __IO uint16_t RESERVEDE; /*!< Reserved */ } USB_TypeDef; @@ -933,7 +929,7 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 256 KB) base address */ #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ @@ -941,7 +937,6 @@ typedef struct #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ @@ -1165,72 +1160,72 @@ typedef struct /* Note: No specific macro feature on this device */ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ @@ -1248,56 +1243,56 @@ typedef struct #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ -#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Pos (0U) #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Pos (1U) #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Pos (3U) #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ -#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Pos (5U) #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ -#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Pos (6U) #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ @@ -1305,53 +1300,53 @@ typedef struct #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ @@ -1360,26 +1355,26 @@ typedef struct #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ -#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ -#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -1387,78 +1382,78 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ /******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ @@ -1466,63 +1461,63 @@ typedef struct #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ @@ -1530,7 +1525,7 @@ typedef struct #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Pos (0U) #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ @@ -1546,7 +1541,7 @@ typedef struct #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ -#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Pos (16U) #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ @@ -1563,7 +1558,7 @@ typedef struct #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Pos (0U) #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ @@ -1575,7 +1570,7 @@ typedef struct #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ -#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Pos (16U) #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ @@ -1588,7 +1583,7 @@ typedef struct #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Pos (0U) #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ @@ -1600,7 +1595,7 @@ typedef struct #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ -#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Pos (16U) #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ @@ -1613,7 +1608,7 @@ typedef struct #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -1621,7 +1616,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -1630,7 +1625,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -1639,7 +1634,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -1648,7 +1643,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -1658,7 +1653,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -1667,7 +1662,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -1676,7 +1671,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -1685,7 +1680,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -1694,7 +1689,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -1704,7 +1699,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -1713,7 +1708,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -1722,7 +1717,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -1731,7 +1726,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -1740,7 +1735,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -1750,7 +1745,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -1759,7 +1754,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -1769,7 +1764,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ @@ -1790,13 +1785,13 @@ typedef struct #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -1804,13 +1799,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Pos (6U) #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Pos (8U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ @@ -1819,7 +1814,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Pos (14U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ @@ -1828,7 +1823,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Pos (20U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ @@ -1837,7 +1832,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ -#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Pos (26U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ @@ -1847,7 +1842,7 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ @@ -1863,7 +1858,7 @@ typedef struct #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ -#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ @@ -1872,12 +1867,12 @@ typedef struct #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Pos (31U) #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ @@ -1893,7 +1888,7 @@ typedef struct #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ -#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ @@ -1902,12 +1897,12 @@ typedef struct #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Pos (31U) #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ @@ -1923,7 +1918,7 @@ typedef struct #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ -#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ @@ -1932,12 +1927,12 @@ typedef struct #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Pos (31U) #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ @@ -1953,7 +1948,7 @@ typedef struct #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ -#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ @@ -1962,12 +1957,12 @@ typedef struct #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ -#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Pos (31U) #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -1988,7 +1983,7 @@ typedef struct #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR2 register ******************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -2009,7 +2004,7 @@ typedef struct #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR3 register ******************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -2030,7 +2025,7 @@ typedef struct #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_JDR4 register ******************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -2051,7 +2046,7 @@ typedef struct #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -2075,7 +2070,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -2099,7 +2094,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ @@ -2123,7 +2118,7 @@ typedef struct #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ @@ -2134,7 +2129,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ -#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ @@ -2147,13 +2142,13 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -2161,13 +2156,13 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ @@ -2178,3475 +2173,3475 @@ typedef struct /******************************************************************************/ /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!

Update History

-

V1.7.1 +

V1.8.2 +/ 22-December-2017

+

Main +Changes

+
  • Maintenance Release of HAL and Low Layer drivers
+

   

HAL Drivers changes

+
  • HAL CAN driver
    • Rework of HAL CAN driver (compatibility break) 
      • A +new HAL CAN driver has been redesigned with new APIs, to bypass +limitations on CAN Tx/Rx FIFO management present with previous HAL CAN +driver version.
      • The +new HAL CAN driver is the recommended version. It is located as usual +in Drivers/STM32L4xx_HAL_Driver/Src and +Drivers/STM32L4xx_HAL_Driver/Inc folders. It can be enabled through +switch HAL_CAN_MODULE_ENABLED in stm32l4xx_hal_conf.h
      • The +legacy HAL CAN +driver is also present in the release in +Drivers/STM32L4xx_HAL_Driver/Src/Legacy and +Drivers/STM32L4xx_HAL_Driver/Inc/Legacy +folders for software compatibility reasons. Its usage is not +recommended as deprecated. It can however be enabled through +switch HAL_CAN_LEGACY_MODULE_ENABLED in +stm32l4xx_hal_conf.h
      • Short migration guide:
        • Fields of CAN_InitTypeDef structure are renamed : 
          • SJW +to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to +TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to +AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to +TransmitFifoPriority
        • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start()
        • HAL_CAN_Transmit() +is replaced by HAL_CAN_AddTxMessage() to place Tx request, then +HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion
        • HAL_CAN_Transmit_IT() +is replaced by HAL_CAN_ActivateNotification() to enable transmission with interrupt mode, then HAL_CAN_AddTxMessage() to place Tx request
        • HAL_CAN_Receive() +is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message
        • HAL_CAN_Receive_IT() +is replaced by HAL_CAN_ActivateNotification() to enable reception with interrupt mode, then HAL_CAN_GetRxMessage() in the receive callback to get Rx message
        • HAL_CAN_Sleep() is renamed to HAL_CAN_RequestSleep()
        • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback()
        • HAL_CAN_RxCpltCallback() is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback()
      • More complete "how to use the new driver" is detailed in the driver header section itself
  • HAL CORTEX driver
    • HAL_MPU_Enable() and HAL_MPU_Disable() functions moved to stm32l4xx_hal_cortex.c
  • HAL CRC driver
    • Fix GCC warning 
  • HAL FLASH driver
    • HAL_FLASH_Unlock() updated to not return HAL_ERROR if flash is already unlocked 
  • HAL OSPI driver
    • Cleanup IO Manager ports
  • HAL RCC driver
    • RCC_RTCCLKSOURCE_NO_CLK renamed to RCC_RTCCLKSOURCE_NONE
    • HAL_RCC_DeInit() updates
      • Clear of status flags
      • Wait for PLLs disable flags to clear PLLs configuration registers
    • Fix MISRA C-2004 rule 10.6 ('U' suffix)
  • HAL TIM driver
    • Fix MISRA C-2004 rule 10.6 ('U' suffix)

LL Drivers changes

+
  • LL CRC driver
    • Fix GCC warning
  • LL RCC driver
    • Add LL_RCC_PLL_SetMainSource() and LL_RCC_HSI_IsEnabledInStopMode() APIs
    • LL_RCC_DeInit() update
      • Clear of status flags
      • Wait for PLLs disable flags to clear PLLs configuration registers
    • Fix IS_LL_RCC_I2C_CLKSOURCE() assert macro

V1.8.1 +/ 13-October-2017

+

Main +Changes

+
  • Maintenance Release of HAL and Low Layer drivers
+

   

HAL Drivers changes

+
  • HAL generic driver
    • Fix compilation issue with ARMCC --gnu option on __packed declaration in stm32l4xx_hal_def.h
  • HAL ADC driver
    • Reuse LL ADC definitions
    • Fix MISRA C-2004 rule 19.10
  • HAL DSI driver
    • Fix +timing issue at highest optimization level on IAR on DSI Host, DSI +Wrapper, DSI PLL and DSI regulator enable/disable macros 
    • Add macro __HAL_DSI_RESET_HANDLE_STATE()
  • HAL FLASH driver
    • HAL_FLASH_Unlock() shall not return an error when Flash already unlocked
  • HAL I2C driver
    • Fix race condition in HAL_I2C_Master_Receive() and HAL_I2C_Slave_Receive()
    • Fix RD_WRN bit management in case of I2C_NO_STARTSTOP request
  • HAL OSPI driver
    • Add note on limitation of HAL_OSPI_AutoPolling() and HAL_OSPI_AutoPolling_IT() usage in octal mode (cf. Errata Sheet)
    • Fix compilation warning in C++
  • HAL QSPI driver
    • Fix MISRA C-2004 rules 10.3, 11.4 and 12.6
  • HAL RCC driver
    • Update +SDMMC1 clock source selection on STM32L4Rx/STM32L4Sx devices to +select PLL divider "P" output instead of internal multiplexor on +MSI, HSI48, PLLSAI1 or PLL "Q" outputs as SDMMC1 kernel clock source
    • Fix __HAL_RCC_GPIOB_IS_CLK_ENABLED() macro definition
  • HAL SDMMC driver
    • Fix management of peripheral flags depending on command or data transfers.
  • HAL SMBUS driver
    • Fix RD_WRN bit management in case of SMBUS_NO_STARTSTOP request

LL Drivers changes

+
  • LL DAC driver
    • Add missing definition for external triggers from TIM and LPTIM instances
  • LL DMA2D driver
    • Fix CodeSonar warning in LL_DMA2D_StructInit()
  • LL I2C driver
    • Fix RD_WRN bit management in case of LL_I2C_GENERATE_NOSTARTSTOP request in LL_I2C_HandleTransfer()
  • LL RCC driver
    • Update SDMMC1 clock +source selection on STM32L4Rx/STM32L4Sx devices to select PLL divider +"P" output instead of internal multiplexor on MSI, HSI48, PLLSAI1 or +PLL "Q" outputs as SDMMC1 kernel clock source
      • Add LL_RCC_SetSDMMCKernelClockSource(), LL_RCC_GetSDMMCKernelClockSource() and LL_RCC_GetSDMMCKernelClockFreq() APIs

V1.8.0 +/ 25-August-2017

+

Main +Changes

+ +
  • Release of HAL and Low Layer drivers to add support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/ STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
+
  • New OctoSPI, DSI, LTDC, GFXMMU peripherals supported in new HAL OSPI, HAL DSI, HAL LTDC and HAL GFXMMU drivers
  • Superset features device STM32L4S9xx API User Manual available (STM32L4S9xx_User_Manual.chm)  
   

HAL Drivers changes

+
  • HAL DSI driver (NEW):stm32l4xx_hal_dsi.h/.c files
  • HAL GFXMMU driver (NEW):stm32l4xx_hal_gfxmmu.h/.c files
  • HAL LTDC driver (NEW):stm32l4xx_hal_ltdc.h/.c and extension stm32l4xx_hal_ltdc_ex.h/.c files
  • HAL OSPI driver (NEW):stm32l4xx_hal_ospi.h/.c files
+
  • HAL generic driver
    • Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() APIs
    • Default HAL_Delay() implementation updated to insure minimum requested delay
    • Add +__HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE() and +__HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE() macros to set respectively SRAM2 +page protection attribute for page 0 to 31 and page 32 to 63
  • HAL CAN driver
    • Add FIFOs overrun error management (new error codes HAL_CAN_ERROR_FOV0 and HAL_CAN_ERROR_FOV1)
  • HAL CRYP driver
    • Fix zero padding in case of Data type
    • Fix phase setting related to payload suspension
    • Fix to not be too restrictive on input parameters in HAL_CRYPEx_AES_Auth() and  HAL_CRYPEx_AES_Auth_DMA()
  • HAL DAC driver
    • Fix Sample & Hold configuration in case of multi-channel
    • Rename DAC_HIGH_FREQUENCY_INTERFACE_MODE_ENABLE to DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ
  • HAL DMA driver
    • Fix DMAMUX synchronization signal configuration in HAL_DMAEx_ConfigMuxSync()
    • Support of DMAMUX1 peripheral via new DMA Extension APIs
      • HAL_DMAEx_ConfigMuxRequestGenerator()
      • HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator()
      • HAL_DMAEx_ConfigMuxSync()
      • HAL_DMAEx_MUX_IRQHandler()
  • HAL DFSDM driver extension (new stm32l4xx_hal_dfsdm_ex.h/.c)
    • New APIs HAL_DFSDMEx_ChannelSetPulsesSkipping() and HAL_DFSDMEx_ChannelGetPulsesSkipping()
  • HAL DFSDM driver
    • Fix +cast issue to return possible negative value in +HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterGetInjectedValue(), +HAL_DFSDM_FilterGetExdMaxValue() and HAL_DFSDM_FilterGetExdMinValue()
  • HAL FLASH driver
    • Add new LVE pin management in HAL_FLASHEx_ConfigLVEPin()
    • Fix timeout issue in private FLASH_WaitForLastOperation() API
    • Fix error status of HAL_FLASHEx_OBProgram(
  • FMC driver
    • New field NBLSetupTime added in FMC_NORSRAM_InitTypeDef structure
    • New field DataHoldTime added in FMC_NORSRAM_TimingTypeDef structure
  • HAL HASH driver
    • Update of context swap mechanism implemented in HAL_HASH_DMAFeed_ProcessSuspend() when input data are fed to the IP by DMA
  • HAL HCD/PCD driver
    • Add support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/ STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
  • HAL IRDA driver
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • IRDA_InitTypeDef structure update to add ClockPrescaler parameter
  • HAL PCD driver
    • Fix USB PCD lock/unlock and flush TX fifo during device reset
  • HAL PWR driver
    • Add PWR_REGULATOR_VOLTAGE_SCALE1_BOOST new parameter value for HAL_PWREx_ControlVoltageScaling() to use higher supply voltage (1.28V) with main regulator voltage in range 1 above 80Mhz (maximum frequency equals to 120Mhz) for STM32L4Rx/STM32L4Sx devices  
    • Add +SRAM3 retention management APIs: HAL_PWREx_EnableSRAM3ContentRetention() and HAL_PWREx_DisableSRAM3ContentRetention()
    • Add DSI pins pull-down management
      • new HAL_PWREx_EnableDSIPinsPDActivation() and HAL_PWREx_DisableDSIPinsPDActivation() APIs
  • HAL RCC driver
    • Add clock management of new peripherals: DSI, GFXMMU, LTDC, OSPI1, OSPI2, OSPIM
    • Add OctoSPI peripherals clock source frequency computation in HAL_RCCEx_GetPeriphCLKFreq()
    • Fix issue with main PLL divider M value to allow 1 to 16 value range on STM32L4Rx/STM32L4Sx devices
    • Fix SDMMC1 clock source selection possibilities in HAL_RCCEx_PeriphCLKConfig(), __HAL_RCC_SDMMC1_CONFIG() and __HAL_RCC_GET_SDMMC1_SOURCE()
    • Fix HAL_RCCEx_GetPeriphCLKFreq() to take into account PLLSAI1 and PLLSAI2 divider M values (1 to 16 range) on STM32L4Rx/STM32L4Sx devices
    • Add undershoot/overshoot management in HAL_RCC_ClockConfig() when switching to/from system clock from main PLL above 80Mhz
  • HAL RNG driver
    • Add support of Clock Error detection and Bypass mode management in new RNG_InitTypeDef and HAL_RNG_Init() API
      • parameters ClockErrorDetection and BypassMode added in new RNG_InitTypeDef
  • HAL RTC driver
    • Fix HAL_RTC_Init() to wait for synchronization and avoid RTC registers access timing issues
  • HAL SAI driver
    • Add FIFO flush in HAL_SAI_DMAStop()
    • Fix HAL_SAI_Transmit_DMA() to follow the slave TX mode sequence described in the Reference Manual
  • HAL SD driver
    • Major rework of HAL SD driver aligned with STM32F7 series
      • BlockSize parameter removed in Read&Write block APIs since 512 byte size is always read&write.
  • HAL SMARTCARD driver
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • SMARTCARD_InitTypeDef structure update to add ClockPrescaler parameter
    • Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only
      • new +HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_DisableFifoMode(), +HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_SetRxFifoThreshold(), +HAL_SMARTCARDEx_RxFifoFullCallback() and HAL_SMARTCARDEx_TxFifoEmptyCallback() +APIs
  • HAL SMBUS driver
    • Add Analog and digital filter configuration APIs: HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter() 
    • Add error management if occuring during STOP process
  • HAL SPI driver
    • Add control of RXFIFO emty at end of transmissing in Master transmission 2 lines mode
  • HAL SWPMI driver
    • Fix missing clock initialization before register update in HAL_SWPMI_Init()
  • HAL TIM driver
    • Add TIM_TIM1_ETR_GPIO and TIM_TIM8_ETR_GPIO definitions
    • Add TIM_TIM16_TI1_MSI, TIM_TIM16_TI1_HSE_32 and TIM_TIM16_TI1_MCO definitions for STM32L4Rx/STM32L4Sx
    • Add new AutoReloadPreload parameter in TIM_Base_InitTypeDef (user code impacted)
    • Fix wrong MOE disable conditions with new macro __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY()
  • HAL UART driver
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • UART_InitTypeDef structure update to add ClockPrescaler parameter
    • Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only
      • new +HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_DisableFifoMode(), +HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_SetRxFifoThreshold(), +HAL_UARTEx_RxFifoFullCallback() and HAL_UARTEx_TxFifoEmptyCallback() +APIs
    • Add SPI Slave mode management for STM32L4Rx/STM32L4Sx devices only
      • new HAL_UARTEx_EnableSlaveMode(), HAL_UARTEx_DisableSlaveMode() and HAL_UARTEx_ConfigNSS()
  • HAL USART driver (new stm32l4xx_hal_usart_ex.c)
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • USART_InitTypeDef structure update to add ClockPrescaler parameter
    • Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only
      • new +HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_DisableFifoMode(), +HAL_USARTEx_SetTxFifoThreshold(), HAL_USARTEx_SetRxFifoThreshold(), +HAL_USARTEx_RxFifoFullCallback() and HAL_USARTEx_TxFifoEmptyCallback() +APIs
    • Add SPI Slave mode management for STM32L4Rx/STM32L4Sx devices only
      • new HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_DisableSlaveMode() and HAL_USARTEx_ConfigNSS()

+

LL Drivers changes

  • LL DMAMUX driver (NEW):stm32l4xx_ll_dmamux.h
  • All LL drivers update to remove usage of CMSIS POSITION_VAL() macro and resort to xx_Pos position bit definition
  • LL ADC
    • Fix legacy APIs LL_ADC_REG_SetTrigSource() and LL_ADC_INJ_SetTrigSource()
  • LL BUS 
    • Add management of new peripherals: DSI, GFXMMU, LTDC, OSPI1, OSPI2, OSPIM
  • LL DMA
    • Fix simple write register access to clear DMA flags in LL_DMA_ClearFlag_XXX() APIs
  • LL DMA2D
    • Add management of output swapping mode (regular or bytes two by two) and line offset mode (pixel or byte)
  • LL EXTI 
    • Add management of EXTI line 40 (I2C4)
  • LL I2C
    • Fix LL_I2C_Init() to not set OAEN1 bit when Own Address 1 value is 0
  • LL LPUART / LL USART
    • Add management of Rx FIFO and Tx FIFO
  • LL PWR
    • Add +SRAM3 retention management APIs 
      • LL_PWR_EnableSRAM3Retention(), +LL_PWR_DisableSRAM3Retention() and LL_PWR_IsEnabledSRAM3Retention()
    • Add voltage range 1 boost mode APIs
      • LL_PWR_EnableRange1BoostMode(), LL_PWR_DisableRange1BoostMode() and LL_PWR_IsEnabledRange1BoostMode()
    • For compatibility purpose accross STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()
    • Add DSI pins pull-down management
      • new LL_PWR_EnableDSIPinsPDActivation(), LL_PWR_DisableDSIPinsPDActivation() and LL_PWR_IsEnabledDSIPinsPDActivation() APIs
  • LL RCC
    • Add management of new peripheral clock sources for DSI, LTDC, OSPI1, OSPI2 and SDMMC
    • Add +new definitions for main PLL divider M values above LL_RCC_PLLM_DIV_8 +and up to LL_RCC_PLLM_DIV_16 for STM32L4Rx/STM32L4Sx devices
    • Fix +in __LL_RCC_CALC_PLLCLK_SAI_FREQ(), __LL_RCC_CALC_PLLSAI1_SAI_FREQ(), +__LL_RCC_CALC_PLLSAI1_48M_FREQ(), __LL_RCC_CALC_PLLSAI1_ADC_FREQ(), +__LL_RCC_CALC_PLLSAI2_SAI_FREQ()
    • Fix +in LL_RCC_PLLSAI1_ConfigDomain_48M(), +LL_RCC_PLLSAI1_ConfigDomain_SAI(), LL_RCC_PLLSAI1_ConfigDomain_ADC(), +LL_RCC_PLLSAI1_GetP(), LL_RCC_PLLSAI2_ConfigDomain_SAI() and +LL_RCC_PLLSAI2_GetP()
    • Fix LL_RCC_GetSDMMCClockFreq() to take into account all SDMMC1 possible clock sources
    • Add HSI48 oscillator clock source value for RNG and USB: 
      • LL_RCC_RNG_CLKSOURCE_HSI48 and update LL_RCC_GetRNGClockFreq()
      • LL_RCC_USB_CLKSOURCE_HSI48 and update LL_RCC_GetUSBClockFreq()
    • General fixes
      • Renaming of RCC_DFSDM1CLKSOURCE_PCLK to RCC_DFSDM1CLKSOURCE_PCLK2
      • Renaming of RCC_SWPMI1CLKSOURCE_PCLK to RCC_SWPMI1CLKSOURCE_PCLK1
      • Renaming of RCC_LPTIMxCLKSOURCE_PCLK to RCC_LPTIMxCLKSOURCE_PCLK1
  • LL RNG
    • Add Clock Error detection and Bypass mode management in new LL_RNG_InitTypeDef and new LL_RNG_Init() API
      • new LL_RNG_EnableClkErrorDetect(), LL_RNG_DisableClkErrorDetect() and LL_RNG_IsEnableClkErrorDetect()
      • new LL_RNG_EnableBypassMode(), LL_RNG_DisableBypassMode() and LL_RNG_IsEnabledBypassMode
  • LL RTC
    • LL_RTC_TIME_Get() and LL_RTC_DATE_Get() implementations optimization (single register read access)
  • LL SYSTEM
    • Add SRAM2 page write protection APIs: LL_SYSCFG_EnableSRAM2PageWRP_0_31() and LL_SYSCFG_EnableSRAM2PageWRP_32_63()
  • LL TIM
    • Fix definition of TIM break input polarity (inverse values LL_TIM_BKIN_POLARITY_LOW / LL_TIM_BKIN_POLARITY_HIGH)
    • Fix LL_TIM_EnableUpdateEvent(), LL_TIM_DisableUpdateEvent() and LL_TIM_IsEnabledUpdateEvent()
  • LL UTILS
    • Add management of new flash latency ranges in UTILS_SetFlashLatency()
    • Add undershoot management when switching to system clock from main PLL above 80Mhz in LL_PLL_ConfigSystemClock_MSI(), LL_PLL_ConfigSystemClock_HSI() and LL_PLL_ConfigSystemClock_HSE()

V1.7.2 +/ 16-June-2017

+

Main +Changes

+
  • Maintenance Release of HAL and Low Layer drivers

 +

HAL Drivers changes

+
  • HAL CAN driver
    • Add overrun error management by the error callback
  • HAL CRC driver
    • Update of HAL_CRCEx_Polynomial_Set() to return an error when a non-supported polynomial length is passed as parameter
  • HAL CRYP driver
    • Update zero padding management with respect to data type
    • Phase setting and comments correction in case of payload phase suspension
    • Correct input parameters tests in HAL_CRYPEx_AES_Auth() and HAL_CRYPEx_AES_Auth_DMA() APIs
    • Correct interruptions and IP enabling flags setting for key derivation in IT mode
  • HAL DCMI driver
    • Comments correction to describe image size management when larger than maximum authorized DMA transfer size
  • HAL FLASH driver
    • Add software work-around in HAL_FLASH_Unlock() to clear OPTVERR flag on STM32L45x/L46x parts when initially improperly raised
    • Correct timeout issue in FLASH_WaitForLastOperation()
  • HAL HASH driver
    • Update of context swap mechanism implemented in HAL_HASH_DMAFeed_ProcessSuspend() when input data are fed to the IP by DMA

LL Drivers changes

+
  • LL RCC
    • Correct duplication of aRCC_APBAHBPrescTable
  • LL RTC
    • Simplication of implementation of function LL_RTC_DATE_Get()
  • LL TIM
    • Fix LL_TIM_EnableUpdateEvent(), LL_TIM_DisableUpdateEvent() and LL_TIM_IsEnabledUpdateEvent()

V1.7.1 / 21-April-2017

Main Changes

diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h index 901e9a1c15..0ae9d0b248 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32_hal_legacy.h @@ -2,9 +2,7 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -60,7 +58,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -92,10 +90,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -111,21 +109,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -138,7 +136,9 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -154,7 +154,7 @@ #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -226,7 +226,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -255,28 +255,27 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + + + /** * @} */ @@ -284,7 +283,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -360,11 +359,11 @@ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -377,12 +376,12 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -400,7 +399,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -432,18 +431,18 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -457,6 +456,78 @@ * @} */ +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE + + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + + #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX + #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 + #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 + #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + + #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT + #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING + #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING + #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + + +#endif /* STM32H7 */ + + +/** + * @} + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -469,7 +540,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -542,7 +613,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -572,7 +643,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -596,11 +667,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -609,14 +680,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -625,7 +696,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -637,18 +708,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -661,31 +732,27 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -693,15 +760,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -722,7 +789,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -740,7 +807,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -756,13 +823,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -863,7 +930,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -903,7 +970,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -928,7 +995,7 @@ #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U - + #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ @@ -963,7 +1030,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -978,39 +1045,39 @@ /** * @} - */ - + */ + #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ + */ #endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1023,11 +1090,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1037,12 +1104,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1050,7 +1117,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1131,6 +1198,8 @@ #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER @@ -1144,17 +1213,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1165,7 +1234,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1177,28 +1246,31 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1213,8 +1285,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1223,7 +1295,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1231,7 +1303,7 @@ #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 @@ -1243,7 +1315,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1313,7 +1385,6 @@ #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL @@ -1340,7 +1411,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1413,7 +1484,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1600,7 +1671,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1619,14 +1690,18 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST @@ -1642,11 +1717,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1657,7 +1732,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1666,7 +1741,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1695,8 +1770,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1761,7 +1836,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1769,37 +1844,37 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE @@ -1816,7 +1891,7 @@ #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE @@ -2044,6 +2119,21 @@ #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2235,13 +2325,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE @@ -2294,111 +2384,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2406,29 +2496,28 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2444,8 +2533,6 @@ #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE @@ -2467,8 +2554,6 @@ #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET @@ -2632,7 +2717,7 @@ #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) @@ -2640,6 +2725,30 @@ #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG @@ -2693,7 +2802,12 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) +#else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL @@ -2793,6 +2907,15 @@ #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + /** * @} */ @@ -2800,17 +2923,19 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ - +#if defined (STM32G0) +#else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT @@ -2846,7 +2971,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2871,26 +2996,26 @@ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if defined(STM32F4) +#if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2899,8 +3024,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -2922,6 +3047,24 @@ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#endif /** * @} */ @@ -2940,7 +3083,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -2972,7 +3115,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -2984,8 +3127,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3090,7 +3233,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3099,7 +3242,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3110,6 +3253,7 @@ * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ @@ -3135,11 +3279,22 @@ * @} */ +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c index 285da086c5..5e6dae988a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -67,11 +65,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32L4xx HAL Driver version number V1.7.1 + * @brief STM32L4xx HAL Driver version number */ #define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ +#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ @@ -253,7 +251,7 @@ __weak void HAL_MspDeInit(void) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) @@ -325,7 +323,7 @@ __weak uint32_t HAL_GetTick(void) * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. + * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) @@ -575,11 +573,11 @@ void HAL_SYSCFG_DisableMemorySwappingBank(void) #if defined(VREFBUF) /** * @brief Configure the internal voltage reference buffer voltage scale. - * @param VoltageScaling: specifies the output voltage to achieve + * @param VoltageScaling specifies the output voltage to achieve * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. * @retval None */ @@ -593,7 +591,7 @@ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) /** * @brief Configure the internal voltage reference buffer high impedance mode. - * @param Mode: specifies the high impedance mode + * @param Mode specifies the high impedance mode * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h index 7e98496f8f..aafa7c351c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -68,14 +66,21 @@ #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) +#define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) +#else #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -374,19 +379,32 @@ #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +/** @brief OCTOSPI mapped at 0x00000000. + */ +#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) +#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) + +#else /** @brief QUADSPI mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @brief Return the boot mode as configured by user. * @retval The boot mode as configured by user. The returned value can be one @@ -406,8 +424,8 @@ * @note Write protection can only be disabled by a system reset */ #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ - SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ - }while(0) + SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ + }while(0) #if defined(SYSCFG_SWPR2_PAGE63) /** @brief SRAM2 page 32 to 63 write protection enable macro @@ -432,7 +450,7 @@ #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) /** @brief Floating Point Unit interrupt enable/disable macros - * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts + * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts */ #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ @@ -467,7 +485,7 @@ #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) /** @brief Check SYSCFG flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing @@ -480,7 +498,7 @@ #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) /** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__: This parameter can be a value of : + * @param __FASTMODEPLUS__ This parameter can be a value of : * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c index 5617796431..c9c033cbc6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -47,8 +45,7 @@ (+) ADC channels selectable single/differential input. - (+) ADC offset on regular groups. - + (+) ADC offset shared on 4 offset instances. (+) ADC calibration (+) ADC conversion of regular group. @@ -83,10 +80,10 @@ other device clock parameters configuration: (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory) - RCC_ADCCLKSOURCE_PLLSAI2 enable: (optional: if asynchronous clock selected) + RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected) (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit; (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI2; + (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL; (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); (++) ADC clock source and clock prescaler are configured at ADC level with @@ -113,7 +110,7 @@ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). - + *** Configuration of ADC, group regular, channels parameters *** ================================================================ [..] @@ -271,20 +268,6 @@ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ - -#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\ - ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\ - ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ - -#define ADC_CFGR_WD_FIELDS ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \ - ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH)) /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no - conversion (neither regular nor injected) is on-going */ - -#define ADC_OFR_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ - - /* Delay to wait before setting ADEN once ADCAL has been reset must be at least 4 ADC clock cycles. @@ -297,23 +280,18 @@ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ - - -/* Delay for ADC voltage regulator startup time */ -/* Maximum delay is 10 microseconds */ -/* (refer device RM, parameter Tadcvreg_stup). */ -#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */ - /* Timeout to wait for current conversion on going to be completed. */ -/* Timeout fixed to worst case, for 1 channel. */ +/* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* - maximum sampling time (640.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ /* - ADC clock with prescaler 256 */ -/* 653 * 256 = 167168 clock cycles max */ +/* (from asynchronous clock, assuming clock frequency same as CPU for */ +/* this calculation) */ +/* - ADC oversampling ratio 256 */ +/* Calculation: 653 * 256 * 256 = 42795008 CPU clock cycles max */ /* Unit: cycles of CPU clock. */ -#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168) /*!< ADC conversion completion time-out value */ - +#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 42795008) /*!< ADC conversion completion time-out value */ @@ -348,8 +326,8 @@ * @brief Initialize the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level - * depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks - * or AHB clock. + * (refer to description of RCC configuration for ADC + * in header of this file). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can @@ -369,15 +347,13 @@ * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - ADC_Common_TypeDef *tmpADC_Common; - uint32_t tmpCFGR = 0; + uint32_t tmpCFGR = 0U; __IO uint32_t wait_loop_index = 0; /* Check ADC handle */ @@ -391,11 +367,11 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); assert_param(IS_ADC_DFSDMCFG_MODE(hadc)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); @@ -407,20 +383,18 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - if (hadc->Init.DiscontinuousConvMode == ENABLE) + if(hadc->Init.DiscontinuousConvMode == ENABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } - /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); - /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ - if (hadc->State == HAL_ADC_STATE_RESET) + if(hadc->State == HAL_ADC_STATE_RESET) { /* Init the low level hardware */ HAL_ADC_MspInit(hadc); @@ -432,29 +406,27 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) hadc->Lock = HAL_UNLOCKED; } - /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - /* Exit deep power down mode if still in that state */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD)) + if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0U) { - /* Exit deep power down mode */ - CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); + /* Disable ADC deep power down mode */ + LL_ADC_DisableDeepPowerDown(hadc->Instance); /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } - if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) - { + if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) + { /* Enable ADC internal voltage regulator */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN); + LL_ADC_EnableInternalRegulator(hadc->Instance); /* Delay for ADC stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2))); + wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); while(wait_loop_index != 0) { wait_loop_index--; @@ -464,7 +436,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ - if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) + if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -479,19 +451,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + if( (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + ) { - - /* Initialize the ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); /* Configuration of common ADC parameters */ - /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - - /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ @@ -515,8 +485,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ - - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler); + LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); } /* Configuration of ADC: */ @@ -541,19 +510,19 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Enable external trigger if trigger selection is different of software */ /* start. */ - /* - external trigger to start conversion Init.ExternalTrigConv */ - /* - external trigger polarity Init.ExternalTrigConvEdge */ - /* Note: parameter ExternalTrigConvEdge set to "trigger edge none" is */ - /* equivalent to software start. */ - if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - && (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE)) + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { - tmpCFGR |= ( hadc->Init.ExternalTrigConv | hadc->Init.ExternalTrigConvEdge); + tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) + | hadc->Init.ExternalTrigConvEdge + ); } - /* Update Configuration Register CFGR */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); - + /* Update Configuration Register CFGR */ + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ @@ -565,10 +534,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) tmpCFGR = ( ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); - + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); - - + if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); @@ -576,36 +544,31 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); - if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) - || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)) - { - /* Multi trigger is not applicable to software-triggered conversions */ - assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER)); - } - - - /* Configuration of Oversampler: */ - /* - Oversampling Ratio */ - /* - Right bit shift */ - /* - Triggered mode */ - /* - Oversampling mode (continued/resumed) */ - MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, - ADC_CFGR2_ROVSE | - hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode | - hadc->Init.Oversampling.OversamplingStopReset); + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + /* - Triggered mode */ + /* - Oversampling mode (continued/resumed) */ + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TROVS | + ADC_CFGR2_ROVSM, + ADC_CFGR2_ROVSE | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode | + hadc->Init.Oversampling.OversamplingStopReset + ); } else { - /* Disable Regular OverSampling */ - CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); + /* Disable ADC oversampling scope on ADC group regular */ + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ - - /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ @@ -613,12 +576,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ - /* parameter "NbrOfConversion" */ + /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) { - /* Set number of ranks in regular group sequencer */ - MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); + /* Set number of ranks in regular group sequencer */ + MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); } else { @@ -635,7 +598,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; - } /* if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) */ + } /* Return function status */ return tmp_hal_status; @@ -643,13 +606,20 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief Deinitialize the ADC peripheral registers to their default reset - * values, with deinitialization of the ADC MSP. - * @note Keep in mind that all ADCs use the same clock: disabling - * the clock will reset all ADCs. - * @note By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by - * reducing the leakage currents and is particularly interesting before - * entering STOP 1 or STOP 2 modes. - * @param hadc: ADC handle + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: + * all ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behavior in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: + * this saves more power by reducing leakage currents + * and is particularly interesting before entering MCU low-power modes. + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) @@ -828,7 +798,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /** * @brief Initialize the ADC MSP. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) @@ -843,8 +813,9 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /** * @brief DeInitialize the ADC MSP. - * @param hadc: ADC handle - * @note All ADCs use the same clock: disabling the clock will reset all ADCs. + * @param hadc ADC handle + * @note All ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) @@ -889,13 +860,14 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) * @note Case of multimode enabled (when multimode feature is available): * if ADC is Slave, ADC is enabled but conversion is not started, * if ADC is master, ADC is enabled and multimode conversion is started. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_TypeDef *tmpADC_Master; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -907,24 +879,17 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA)); - } - else - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - } - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - by default if ADC is Master or Independent or if multimode feature is not available - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ @@ -932,11 +897,29 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - - /* Clear regular group conversion flag and overrun flag */ + + /* Set ADC error code */ + /* Check if a conversion is on going on ADC group injected */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to regular conversions only */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -954,10 +937,9 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - /* Process unlocked */ - __HAL_UNLOCK(hadc); - /* Start ADC */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { @@ -968,11 +950,9 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - - } /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */ + } + + } } else { @@ -995,7 +975,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) @@ -1021,8 +1001,9 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) if (tmp_hal_status == HAL_OK) { /* Set ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } @@ -1035,25 +1016,27 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) /** * @brief Wait for regular group conversion to be completed. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. - * @note Depending on hadc->Init.EOCSelection, EOS or EOC is - * checked and cleared depending on AUTDLY bit status. - * @note HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a - * DMA-managed conversions configuration: indeed, EOC is immediately - * reset by the DMA reading the DR register when the converted data is - * available. Therefore, EOC is set for a too short period to be - * reliably polled. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart = 0; - uint32_t tmp_Flag_EOC = 0x00; - uint32_t tmp_cfgr = 0x00; - uint32_t tmp_eos_raised = 0x01; /* by default, assume that EOS is set, - tmp_eos_raised will be corrected - accordingly during API execution */ + uint32_t tickstart = 0U; + uint32_t tmp_Flag_End = 0U; + uint32_t tmp_cfgr = 0U; ADC_TypeDef *tmpADC_Master; /* Check the parameters */ @@ -1062,43 +1045,50 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { - tmp_Flag_EOC = ADC_FLAG_EOS; + tmp_Flag_End = ADC_FLAG_EOS; } /* If end of conversion selected to end of unitary conversion */ else /* ADC_EOC_SINGLE_CONV */ { - /* Check that the ADC is not in a DMA-based configuration. Otherwise, - returns an error. */ - - /* Check whether dual regular conversions are disabled or unavailable. */ - if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if(ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) { - /* Check DMAEN bit in handle ADC CFGR register */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET) - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - return HAL_ERROR; - } - } - else - { - /* Else need to check Common register CCR MDMA bit field. */ - if (ADC_MULTIMODE_DMA_ENABLED()) + /* Check ADC DMA mode in independant mode */ + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } + } + else + { + /* Check ADC DMA mode in multimode */ + if(ADC_MULTIMODE_DMA_ENABLED(hadc)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } } - - /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */ - tmp_Flag_EOC = ADC_FLAG_EOC; } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) + while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) @@ -1116,16 +1106,31 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti } } - /* Next, to clear the polled flag as well as to update the handle State, - EOS is checked and the relevant configuration register is retrieved. */ - /* 1. Check whether or not EOS is set */ - if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS)) + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) { - tmp_eos_raised = 0; + /* Check whether end of sequence is reached */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } } - /* 2. Check whether or not hadc is the handle of a Slave ADC with dual - regular conversions enabled. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) + + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ + if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) { /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); @@ -1136,57 +1141,31 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti tmpADC_Master = ADC_MASTER_REGISTER(hadc); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - + /* Clear polled flag */ - if (tmp_Flag_EOC == ADC_FLAG_EOS) + if (tmp_Flag_End == ADC_FLAG_EOS) { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); } else { - /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ - /* For regular groups, no new conversion will start before EOC is cleared.*/ - /* Note that 1. reading DR clears EOC. */ - /* 2. in multimode with dual regular conversions enabled (when */ - /* multimode feature is available), Master AUTDLY bit is */ - /* checked. */ - if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } } - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - /* If 1. EOS is set - 2. conversions are software-triggered - 3. CONT bit is reset (that of handle ADC or Master ADC if applicable) - Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset. - 4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY - can be set */ - if ((tmp_eos_raised) - && (ADC_IS_SOFTWARE_START_REGULAR(hadc)) - && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - /* Return function status */ return HAL_OK; } /** * @brief Poll for ADC event. - * @param hadc: ADC handle - * @param EventType: the ADC event type. + * @param hadc ADC handle + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) @@ -1194,7 +1173,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) * @arg @ref ADC_OVR_EVENT ADC Overrun event * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. * Indeed, the latter is reset only if hadc->Init.Overrun field is set * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten @@ -1212,7 +1191,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick count */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Check selected event flag */ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) @@ -1220,7 +1199,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1245,13 +1224,15 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy break; - /* Analog watchdog (level out of window) event */ + /* Analog watchdog (level out of window) event */ /* Note: In case of several analog watchdog enabled, if needed to know */ - /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */ - /* flags HAL_ADC_STATE_AWD/2/3 function. */ - /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */ - /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */ - /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */ + /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */ + /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */ + /* Check analog watchdog 1 flag */ case ADC_AWD_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); @@ -1336,13 +1317,13 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy * @note To guarantee a proper reset of all interruptions once all the needed * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure * a correct stop of the IT-based conversions. - * @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling * interruption. If required (e.g. in case of oversampling with trigger * mode), the user must: * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) * before calling HAL_ADC_Start_IT(). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) @@ -1361,11 +1342,27 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* State machine update: Check if an injected conversion is ongoing */ + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - by default if ADC is Master or Independent or if multimode feature is not available + - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ + if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } + + /* Set ADC error code */ + /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ @@ -1373,56 +1370,52 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) } else { - /* Set ADC error code to none */ + /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); - } - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */ - if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) - { - CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - /* Clear regular group conversion flag and overrun flag */ + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* By default, disable all interruptions before enabling the desired ones */ + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Disable all interruptions before enabling the desired ones */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - /* Enable required interruptions */ + /* Enable ADC end of conversion interrupt */ switch(hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); - break; + break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); - break; + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + break; } - + + /* Enable ADC overrun interrupt */ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is ADC_IT_OVR enabled; otherwise data overwrite is considered as normal behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - } + } /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion starts at next */ + /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) + if(ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) { /* Multimode feature is not available or ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. @@ -1446,12 +1439,11 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; - } - } /* if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); - /* Start ADC */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); + } + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { @@ -1469,21 +1461,19 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Next, set Slave injected interruptions */ switch(hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; - } - } /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc) ) */ - } /* if (tmp_hal_status == HAL_OK) */ + } + } + } + } else { /* Process unlocked */ @@ -1504,7 +1494,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) @@ -1535,7 +1525,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY), + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } @@ -1555,9 +1545,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() * is designed for single-ADC mode only. For multimode, the dedicated * HAL_ADCEx_MultiModeStart_DMA() function must be used. - * @param hadc: ADC handle - * @param pData: Destination Buffer address. - * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes) + * @param hadc ADC handle + * @param pData Destination Buffer address. + * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1583,30 +1573,33 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - } - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, - (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - - /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - - by default if ADC is Master or Independent or if multimode feature is not available - - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ + + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - by default if ADC is Master or Independent or if multimode feature is not available + - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + + /* Check if a conversion is on going on ADC group injected */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to regular conversions only */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; @@ -1625,46 +1618,47 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, - ADC_IT_OVR is enabled. */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + ADC_IT_OVR is enabled. */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - + /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); - + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (tmp_hal_status == HAL_OK) */ + __HAL_UNLOCK(hadc); + } } else { tmp_hal_status = HAL_ERROR; /* Process unlocked */ - __HAL_UNLOCK(hadc); - } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */ - + __HAL_UNLOCK(hadc); + } } else { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } @@ -1673,13 +1667,13 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on injected group. If injected group is under use, it + * @note: ADC peripheral disable is forcing stop of potential + * conversion on ADC group injected. If ADC group injected is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) @@ -1698,7 +1692,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { - /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ + /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -1709,7 +1703,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ @@ -1732,7 +1726,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - (HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY), + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } @@ -1757,11 +1751,11 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. - * To clear this flag, either use function: + * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADC_PollForConversion() + * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) @@ -1778,24 +1772,23 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /** * @brief Handle ADC interrupt request. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */ - ADC_TypeDef *tmpADC_Master; - uint32_t tmp_isr = hadc->Instance->ISR; - uint32_t tmp_ier = hadc->Instance->IER; - uint32_t tmp_cfgr = 0x0; - uint32_t tmp_cfgr_jqm = 0x0; + uint32_t tmp_isr = hadc->Instance->ISR; + uint32_t tmp_ier = hadc->Instance->IER; + uint32_t tmp_cfgr = 0x0; + ADC_TypeDef *tmpADC_Master; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - /* ====== Check End of Sampling flag for regular group ===== */ - if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + /* ========== Check End of Sampling flag for ADC group regular ========== */ + if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) @@ -1803,30 +1796,33 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); } - + /* End Of Sampling callback */ HAL_ADCEx_EndOfSamplingCallback(hadc); /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); - } + } - /* ====== Check End of Conversion or Sequence flags for regular group ===== */ - if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ + if((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - /* Disable interruption if no further conversion upcoming by regular */ - /* external trigger or by continuous mode, */ - /* and if scan sequence if completed. */ + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) { + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) { /* check CONT bit directly in handle ADC CFGR register */ @@ -1845,22 +1841,23 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Disable ADC end of sequence conversion interrupt */ - /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */ - /* in HAL_Start_IT(), it isn't disabled here because it can be used */ - /* by overrun IRQ process below. */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } else { @@ -1871,24 +1868,25 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } - } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */ - } /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc) */ + } + } /* Conversion complete callback */ - /* Note: HAL_ADC_ConvCpltCallback can resort to - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether - interruption has been triggered by end of conversion or end of - sequence. */ - HAL_ADC_ConvCpltCallback(hadc); - + /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ + /* to determine if conversion has been triggered from EOC or EOS, */ + /* possibility to use: */ + /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ + HAL_ADC_ConvCpltCallback(hadc); /* Clear regular group conversion flag */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); } - - /* ========== Check End of Conversion flag for injected group ========== */ + /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) { @@ -1899,75 +1897,66 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } - - /* Check whether interruptions can be disabled only if - - injected conversions are software-triggered when injected queue management is disabled - OR - - auto-injection is enabled, continuous mode is disabled (CONT = 0) - and regular conversions are software-triggered */ - /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ + if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) { - - /* First, retrieve proper registers to check */ - /* 1a. Are injected conversions that of a dual Slave ? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) + tmp_cfgr = READ_REG(hadc->Instance->CFGR); + } + else + { + tmpADC_Master = ADC_MASTER_REGISTER(hadc); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + } + + /* Disable interruption if no further conversion upcoming by injected */ + /* external trigger or by automatic injected conversion with regular */ + /* group having no further conversion upcoming (same conditions as */ + /* regular group interruption disabling above), */ + /* and if injected scan sequence is completed. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || + ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - check JQM bit directly in ADC CFGR register */ - tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); - } - else - { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - need to check JQM bit of Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR); - } - /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) - { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits directly in ADC CFGR register */ - tmp_cfgr = READ_REG(hadc->Instance->CFGR); - } - else - { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits of Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - } - - /* Secondly, check whether JEOC and JEOS interruptions can be disabled */ - if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM)) - && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc)))) ) - { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) + { + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } } - } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */ + } /* Injected Conversion complete callback */ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to @@ -1980,8 +1969,6 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } - - /* ========== Check Analog watchdog flags =================================================== */ /* ========== Check Analog watchdog 1 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) @@ -2005,7 +1992,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) HAL_ADCEx_LevelOutOfWindow2Callback(hadc); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - } + } /* ========== Check analog watchdog 3 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) @@ -2035,23 +2022,22 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) } else { - /* check DMA configuration, depending on multimode set or not, - or whether or not multimode feature is available */ + /* Check DMA configuration */ if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET) { /* Multimode not set or feature not available or ADC independent */ if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) { - overrun_error = 1; - } + overrun_error = 1; + } } else { /* Multimode (when feature is available) is enabled, Common Control Register MDMA bits must be checked. */ - if (ADC_MULTIMODE_DMA_ENABLED()) + if (ADC_MULTIMODE_DMA_ENABLED(hadc)) { - overrun_error = 1; + overrun_error = 1; } } } @@ -2064,17 +2050,18 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - /* Error callback */ + /* Error callback */ + /* Note: In case of overrun, ADC conversion data is preserved until */ + /* flag OVR is reset. */ + /* Therefore, old ADC conversion data can be retrieved in */ + /* function "HAL_ADC_ErrorCallback()". */ HAL_ADC_ErrorCallback(hadc); } - - /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since - old data is preserved until OVR is reset */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } - /* ========== Check Injected context queue overflow flag ========== */ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { @@ -2095,7 +2082,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /** * @brief Conversion complete callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) @@ -2110,7 +2097,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Conversion DMA half-transfer callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) @@ -2125,7 +2112,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog 1 callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) @@ -2147,7 +2134,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) @@ -2192,14 +2179,13 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". - * @param hadc: ADC handle - * @param sConfig: Structure of ADC channel assigned to ADC group regular. + * @param hadc ADC handle + * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_Common_TypeDef *tmpADC_Common; uint32_t tmpOffsetShifted; __IO uint32_t wait_loop_index = 0; @@ -2235,121 +2221,93 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* - Channel rank */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { + #if !defined (USE_FULL_ASSERT) + /* Correspondance for compatibility with legacy definition of */ + /* sequencer ranks in direct number format. This correspondance can */ + /* be done only on ranks 1 to 5 due to literal values. */ + /* Note: Sequencer ranks in direct number format are no more used */ + /* and are detected by activating USE_FULL_ASSERT feature. */ + if (sConfig->Rank <= 5U) + { + switch (sConfig->Rank) + { + case 2U: sConfig->Rank = ADC_REGULAR_RANK_2; break; + case 3U: sConfig->Rank = ADC_REGULAR_RANK_3; break; + case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break; + case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break; + /* case 1U */ + default: sConfig->Rank = ADC_REGULAR_RANK_1; + } + } + #endif - /* Regular sequence configuration */ - /* Clear the old SQx bits then set the new ones for the selected rank */ - /* For Rank 1 to 4 */ - if (sConfig->Rank < 5) - { - MODIFY_REG(hadc->Instance->SQR1, - ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank), - ADC_SQR1_RK(sConfig->Channel, sConfig->Rank)); - } - /* For Rank 5 to 9 */ - else if (sConfig->Rank < 10) + /* Set ADC group regular sequence: channel on the selected scan sequence rank */ + LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel sampling time */ + /* - Channel offset */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) + { +#if defined(ADC_SMPR1_SMPPLUS) + /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ + if(sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) { - MODIFY_REG(hadc->Instance->SQR2, - ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank), - ADC_SQR2_RK(sConfig->Channel, sConfig->Rank)); + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); } - /* For Rank 10 to 14 */ - else if (sConfig->Rank < 15) - { - MODIFY_REG(hadc->Instance->SQR3, - ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank), - ADC_SQR3_RK(sConfig->Channel, sConfig->Rank)); - } - /* For Rank 15 to 16 */ else - { - MODIFY_REG(hadc->Instance->SQR4, - ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank), - ADC_SQR4_RK(sConfig->Channel, sConfig->Rank)); - } - - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Channel sampling time */ - /* - Channel offset */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { - - /* Channel sampling time configuration */ - /* Clear the old sample time then set the new one for the selected channel */ - /* For channels 10 to 18 */ - if (sConfig->Channel >= ADC_CHANNEL_10) + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); + } +#else + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); +#endif + + /* Configure the offset: offset enable/disable, channel, offset value */ + + /* Shift the offset with respect to the selected ADC resolution. */ + /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); + + if(sConfig->OffsetNumber != ADC_OFFSET_NONE) + { + /* Set ADC selected offset number */ + LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); + + } + else + { + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is disabled. */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { - ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - else /* For channels 0 to 9 */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { - ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - - - /* Configure the offset: offset enable/disable, channel, offset value */ - - /* Shift the offset with respect to the selected ADC resolution. */ - /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); - - switch (sConfig->OffsetNumber) - { - /* Configure offset register i when applicable: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - case ADC_OFFSET_1: - MODIFY_REG(hadc->Instance->OFR1, - ADC_OFR_FIELDS, - ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_2: - MODIFY_REG(hadc->Instance->OFR2, - ADC_OFR_FIELDS, - ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_3: - MODIFY_REG(hadc->Instance->OFR3, - ADC_OFR_FIELDS, - ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_4: - MODIFY_REG(hadc->Instance->OFR4, - ADC_OFR_FIELDS, - ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted); - break; - - /* Case ADC_OFFSET_NONE */ - default : - /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. - If this is the case, offset OFRx is disabled since - sConfig->OffsetNumber = ADC_OFFSET_NONE. */ - if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); - } - if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); - } - if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); - } - if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) - { - CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); - } - break; - } /* switch (sConfig->OffsetNumber) */ - - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); + } + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); + } + } + } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ @@ -2357,51 +2315,31 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { + /* Set mode single-ended or differential input of the selected ADC channel */ + LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); + /* Configuration of differential mode */ - if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) + if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Disable differential mode (default mode: single-ended) */ - CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); } - else - { - /* Enable differential mode */ - SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); - - /* Sampling time configuration of channel ADC_IN+1 (negative input) */ - /* Clear the old sample time then set the new one for the selected */ - /* channel. */ - /* Starting from channel 9, SMPR2 register must be configured */ - if (sConfig->Channel >= ADC_CHANNEL_9) - { - ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1); - } - else /* For channels 0 to 8, SMPR1 must be configured */ - { - ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1); - } - } - - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ - /* paths. */ + /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ /* Configuration of common ADC parameters */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - - /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) ) { /* Configuration of common ADC parameters (continuation) */ @@ -2415,13 +2353,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); - + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2))); + wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); while(wait_loop_index != 0) { wait_loop_index--; @@ -2432,15 +2370,15 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); } } else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - { + { if (ADC_VREFINT_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); - } + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + } } } /* If the requested internal measurement path has already been */ @@ -2454,10 +2392,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf tmp_hal_status = HAL_ERROR; } } - - } /* if (ADC_IS_ENABLE(hadc) == RESET) */ - - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */ + } + } /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ @@ -2487,27 +2423,17 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". - * @note Analog watchdog thresholds can be modified while ADC conversion - * is on going. - * In this case, some constraints must be taken into account: - * the programmed threshold values are effective from the next - * ADC EOC (end of unitary conversion). - * Considering that registers write delay may happen due to - * bus activity, this might cause an uncertainty on the - * effective timing of the new programmed threshold values. - * @param hadc: ADC handle - * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration + * @note On this STM32 serie, analog watchdog thresholds cannot be modified + * while ADC conversion is on going. + * @param hadc ADC handle + * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; - - uint32_t tmpADCFlagAWD2orAWD3; - uint32_t tmpADCITAWD2orAWD3; + uint32_t tmpAWDHighThresholdShifted = 0U; + uint32_t tmpAWDLowThresholdShifted = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2531,136 +2457,162 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular and injected groups: */ + /* conversion on going on ADC groups regular and injected: */ /* - Analog watchdog channels */ /* - Analog watchdog thresholds */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { - - /* Analog watchdogs configuration */ + /* Analog watchdog configuration */ if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ - /* - Set the analog watchdog enable mode: regular and/or injected */ - /* groups, one or overall group of channels. */ - /* - Set the Analog watchdog channel (is not used if watchdog */ - /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_WD_FIELDS, - AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) ); - - /* Shift the offset with respect to the selected ADC resolution: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels, on groups regular and-or injected. */ + switch(AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + break; + + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); + break; + + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + case ADC_ANALOGWATCHDOG_ALL_INJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); + break; + + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); + break; + } + + /* Shift the offset in function of the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->TR1, - ADC_TR1_HT1 | ADC_TR1_LT1, - ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); - - /* Clear the ADC Analog watchdog flag (in case of left enabled by */ - /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ - /* or HAL_ADC_PollForEvent(). */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1); - - /* Configure ADC Analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) - { - /* Enable the ADC Analog watchdog interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1); - } - else - { - /* Disable the ADC Analog watchdog interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1); - } + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD1(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD1(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD1(hadc->Instance); + } } - /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ + /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - /* Shift the threshold with respect to the selected ADC resolution */ - /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ + switch(AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: + /* Update AWD by bitfield to keep the possibility to monitor */ + /* several channels by successive calls of this function. */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + SET_BIT(hadc->Instance->AWD2CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + else + { + SET_BIT(hadc->Instance->AWD3CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + case ADC_ANALOGWATCHDOG_ALL_INJEC: + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + break; + } + + /* Shift the thresholds in function of the selected ADC resolution */ + /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - + + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - /* Set the Analog watchdog channel or group of channels. This also */ - /* enables the watchdog. */ - /* Note: Conditional register reset, because several channels can be */ - /* set by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) + /* Update state, clear previous result related to AWD2 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD2(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) { - SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel)); + LL_ADC_EnableIT_AWD2(hadc->Instance); } else { - CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); + LL_ADC_DisableIT_AWD2(hadc->Instance); } - - /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, - ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); - - /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ - /* settings. */ - tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2; - tmpADCITAWD2orAWD3 = ADC_IT_AWD2; - - /* Update state, clear previous result related to AWD2 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); } /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { - /* Set the Analog watchdog channel or group of channels. This also */ - /* enables the watchdog. */ - /* Note: Conditional register reset, because several channels can be */ - /* set by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) + /* Update state, clear previous result related to AWD3 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD3(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) { - SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel)); + LL_ADC_EnableIT_AWD3(hadc->Instance); } else { - CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); + LL_ADC_DisableIT_AWD3(hadc->Instance); } - - /* Set the high and low thresholds */ - MODIFY_REG(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, - ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); - - /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ - /* settings. */ - tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3; - tmpADCITAWD2orAWD3 = ADC_IT_AWD3; - - /* Update state, clear previous result related to AWD3 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); - } - - /* Clear the ADC Analog watchdog flag (in case left enabled by */ - /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ - /* or HAL_ADC_PollForEvent(). */ - __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3); - - /* Configure ADC Analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) - { - __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3); - } - else - { - __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3); } } } - /* If a conversion is on going on regular or injected groups, no update */ + /* If a conversion is on going on ADC group regular or injected, no update */ /* could be done on neither of the AWD configuration structure parameters. */ else { @@ -2669,7 +2621,6 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -2706,7 +2657,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * For example: * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) @@ -2720,7 +2671,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) /** * @brief Return the ADC error code. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) @@ -2745,8 +2696,8 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) /** * @brief Stop ADC conversion. - * @param hadc: ADC handle - * @param ConversionGroup: ADC group regular and/or injected. + * @param hadc ADC handle + * @param ConversionGroup ADC group regular and/or injected. * This parameter can be one of the following values: * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. @@ -2808,7 +2759,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) { /* Stop conversions on regular group */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP); + LL_ADC_REG_StopConversion(hadc->Instance); } } @@ -2858,7 +2809,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio } } - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */ + } /* Return HAL status */ return HAL_OK; @@ -2870,12 +2821,13 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0; + __IO uint32_t wait_loop_index = 0; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -2896,30 +2848,44 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) } /* Enable the ADC peripheral */ - ADC_ENABLE(hadc); - + LL_ADC_Enable(hadc->Instance); + /* Delay for ADC stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles. */ + wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); + while(wait_loop_index != 0) + { + wait_loop_index--; + } + /* Wait for ADC effectively enabled */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) { /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit has been cleared (after a calibration), ADEN bit is reset by the calibration logic. - The workaround is to continue setting ADEN until ADRDY is becomes 1. + The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ - ADC_ENABLE(hadc); - - if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT) - { + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if(LL_ADC_IsEnabled(hadc->Instance) == 0) + { + LL_ADC_Enable(hadc->Instance); + } + + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } @@ -2933,7 +2899,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) * @brief Disable the selected ADC. * @note Prerequisite condition to use this function: ADC conversions must be * stopped. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) @@ -2949,7 +2915,8 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) if (ADC_DISABLING_CONDITIONS(hadc) != RESET) { /* Disable the ADC peripheral */ - ADC_DISABLE(hadc); + LL_ADC_Disable(hadc->Instance); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); } else { @@ -2987,7 +2954,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) @@ -2996,22 +2963,26 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA))) + if(HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))) { - /* Update ADC state machine */ + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ /* Is it the end of the regular sequence ? */ - if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS)) + if(HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS)) { /* Are conversions software-triggered ? */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Is CONT bit set ? */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET) + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -3022,11 +2993,11 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ - if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET) + if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } @@ -3036,20 +3007,24 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* Conversion complete callback */ HAL_ADC_ConvCpltCallback(hadc); } - else /* DMA or internal error occurred (or both) */ + else /* DMA and-or internal error occurred */ { - /* In case of internal error, */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* call Error Callback function */ + /* Call HAL ADC Error Callback function */ HAL_ADC_ErrorCallback(hadc); } + else + { + /* Call ADC DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } } } /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -3063,7 +3038,7 @@ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback. - * @param hdma: pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h index bd11ed33f1..522b91304b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -46,6 +44,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +/* Include low level driver */ +#include "stm32l4xx_ll_adc.h" + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -65,13 +66,13 @@ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADCEx_Oversampling_Ratio */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. - This parameter can be a value of @ref ADCEx_Right_Bit_Shift */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. - This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected @@ -79,7 +80,8 @@ typedef struct If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). - This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ + }ADC_OversamplingTypeDef; /** @@ -100,23 +102,23 @@ typedef struct */ typedef struct { - uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLLSAI1/PLLSAI2 clocks) and clock prescaler. - This parameter can be a value of @ref ADC_ClockPrescaler. - Note: The clock is common for all the ADCs. + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. + This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. + Note: The ADC clock configuration is common to all ADC instances. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. - Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level. - Note: This parameter can be modified only if all ADCs are disabled. */ + Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. + Note: This parameter can be modified only if all ADC instances are disabled. */ uint32_t Resolution; /*!< Configure the ADC resolution. - This parameter can be a value of @ref ADC_Resolution */ + This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). Refer to reference manual for alignments formats versus resolutions. - This parameter can be a value of @ref ADC_Data_align */ + This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. @@ -177,7 +179,7 @@ typedef struct uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. - This parameter can be a value of @ref ADC_Overrun. + This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). @@ -193,11 +195,12 @@ typedef struct ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM. - This parameter can be a value of @ref ADCEx_DFSDM_Mode_Configuration. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ + This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + +#endif }ADC_InitTypeDef; /** @@ -208,17 +211,17 @@ typedef struct * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another parameter - * (which fulfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) + * on the fly). */ typedef struct { uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_channels + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t Rank; /*!< Specify the rank in the regular group sequencer. - This parameter can be a value of @ref ADC_regular_rank + This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ @@ -226,7 +229,7 @@ typedef struct Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), @@ -236,7 +239,7 @@ typedef struct uint32_t SingleDiff; /*!< Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. - This parameter must be a value of @ref ADCEx_SingleDifferential + This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. @@ -246,7 +249,7 @@ typedef struct of another parameter update on the fly) */ uint32_t OffsetNumber; /*!< Select the offset number - This parameter can be a value of @ref ADCEx_OffsetNumber + This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. @@ -255,31 +258,31 @@ typedef struct 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ + }ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC analog watchdog * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. * ADC state can be either: - * ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. + * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. */ typedef struct { uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) - This parameter can be a value of @ref ADCEx_analog_watchdog_number. */ + This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. - For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected. - For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset - channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored. - This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */ + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). - This parameter can be a value of @ref ADC_channels. */ + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ @@ -297,11 +300,24 @@ typedef struct the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ }ADC_AnalogWDGConfTypeDef; +/** + * @brief ADC group injected contexts queue configuration + * @note Structure intended to be used only through structure "ADC_HandleTypeDef" + */ +typedef struct +{ + uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each + HAL_ADCEx_InjectedConfigChannel() call to finally initialize + JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ + + uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ +}ADC_InjectionConfigTypeDef; + /** @defgroup ADC_States ADC States * @{ */ -/** +/** * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. @@ -310,41 +326,60 @@ typedef struct * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy due to an internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ /** * @} */ +/** + * @brief ADC handle Structure definition + */ +typedef struct +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ + + ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ +}ADC_HandleTypeDef; /** * @} @@ -360,59 +395,59 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error (problem of clocking, - enable/disable, erroneous state, ...) */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ -#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ /** * @} */ -/** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler +/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ -#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ +#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ -#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock not divided */ -#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 2 */ -#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1) /*!< ADC asynchronous clock divided by 4 */ -#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 6 */ -#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock divided by 8 */ -#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 10 */ -#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 12 */ -#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16 */ -#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock divided by 32 */ -#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 64 */ -#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 128 */ -#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */ +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ /** * @} */ -/** @defgroup ADC_Resolution ADC Resolution +/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution * @{ */ -#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ -#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */ -#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */ -#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */ +#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ +#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ /** * @} */ -/** @defgroup ADC_Data_align ADC conversion data alignment +/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) /*!< Data right alignment */ -#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN) /*!< Data left alignment */ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ /** * @} */ @@ -420,8 +455,8 @@ typedef struct /** @defgroup ADC_Scan_mode ADC sequencer scan mode * @{ */ -#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */ -#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */ +#define ADC_SCAN_DISABLE (0x00000000U) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE (0x00000001U) /*!< Scan mode enabled */ /** * @} */ @@ -430,23 +465,23 @@ typedef struct * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) /*!< Event 0 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) /*!< Event 1 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) /*!< Event 2 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 3 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) /*!< Event 4 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 5 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 6 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 7 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) /*!< Event 8 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) /*!< Event 9 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) /*!< Event 10 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 11 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) /*!< Event 12 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */ -#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) /*!< Event 15 triggers regular group conversion start */ -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers regular group conversion start */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ +#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -454,10 +489,10 @@ typedef struct /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000) /*!< Regular conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ @@ -465,126 +500,282 @@ typedef struct /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions * @{ */ -#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of unitary conversion flag */ -#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence conversions flag */ -#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< Reserved for future use */ +#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ +#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ /** * @} */ -/** @defgroup ADC_Overrun ADC overrun +/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) /*!< Data preserved in case of overrun */ -#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD) /*!< Data overwritten in case of overrun */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} */ -/** @defgroup ADC_regular_rank ADC group regular sequencer rank +/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ -#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */ -#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */ -#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */ -#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */ -#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */ -#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */ -#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */ -#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */ -#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */ -#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */ -#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */ -#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */ -#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */ -#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */ -#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */ -#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */ +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ +#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ +#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ +#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ +#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ +#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ +#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ +#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ /** * @} */ -/** @defgroup ADC_channels ADC channels +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define ADC_CHANNEL_0 ((uint32_t)(0x00000000)) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0)) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1)) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2)) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3)) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0)) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1)) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2)) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4)) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0)) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1)) /*!< ADC channel 18 */ - -/* Note: VrefInt, TempSensor and Vbat internal channels are not available on all ADC's - (information present in Reference Manual) */ -#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17 /*!< ADC temperature sensor channel */ -#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 /*!< ADC Vbat channel */ -#define ADC_CHANNEL_VREFINT ADC_CHANNEL_0 /*!< ADC Vrefint channel */ +#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ +#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ +#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ +#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ +#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ +#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ +#if defined(ADC_SMPR1_SMPPLUS) +#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ +#endif +/** + * @} + */ +/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ +/* all ADC instances (refer to Reference Manual). */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ #if defined(ADC1) && !defined(ADC2) -#define ADC_CHANNEL_DAC1CH1 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, they cannot be used both simultenaeously. */ -#define ADC_CHANNEL_DAC1CH2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, they cannot be used both simultenaeously. */ +#define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ +#define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ #elif defined(ADC2) -#define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ -#define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_18) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ +#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ +#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ #if defined(ADC3) -#define ADC_CHANNEL_DAC1CH1_ADC3 (ADC_CHANNEL_14) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ -#define ADC_CHANNEL_DAC1CH2_ADC3 (ADC_CHANNEL_15) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ +#define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ +#define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ #endif #endif /** * @} */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup ADC_Private_Macro ADC Private Macros +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number * @{ */ +#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ +#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ +#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000U) /*!< No analog watchdog selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular + * @{ + */ +#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ +#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ +/** + * @} + */ + + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ +#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ +/** + * @} + */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ +#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ +#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ + +#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ + +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ +#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ +#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ + +#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ + +#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ + ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ + ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ + +/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ + ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ + ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) /** * @brief Return resolution bits in CFGR register RES[1:0] field. - * @param __HANDLE__: ADC handle. - * @retval 2-bit field RES of CFGR register. + * @param __HANDLE__ ADC handle + * @retval Value of bitfield RES in CFGR register. */ -#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES) +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (LL_ADC_GetResolution((__HANDLE__)->Instance)) /** * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Verification of ADC state: enabled or disabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ @@ -594,53 +785,52 @@ typedef struct /** * @brief Check if conversion is on going on regular group. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ -#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ - ) ? RESET : SET) +#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ + (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) /** * @brief Simultaneously clear and set specific bits of the handle State. * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the - * bit field to clear, the third and last parameter is the bit field to set. + * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Verify that a given value is aligned with the ADC resolution range. - * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits). - * @param __ADC_VALUE__: value checked against the resolution. + * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). + * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ - ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))) ) + ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= (0x0FFF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= (0x03FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= (0x00FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= (0x003F))) ) /** * @brief Verify the length of the scheduled regular conversions group. - * @param __LENGTH__: number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ -#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (16U))) /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. - * @param NUMBER: number of scheduled regular conversions in discontinuous mode. + * @param NUMBER number of scheduled regular conversions in discontinuous mode. * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large) */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) /** * @brief Verify the ADC clock setting. - * @param __ADC_CLOCK__: programmed ADC clock. + * @param __ADC_CLOCK__ programmed ADC clock. * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) */ #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ @@ -658,11 +848,10 @@ typedef struct ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) - /** * @brief Verify the ADC resolution setting. - * @param __RESOLUTION__: programmed ADC resolution. + * @param __RESOLUTION__ programmed ADC resolution. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ @@ -672,7 +861,7 @@ typedef struct /** * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. - * @param __RESOLUTION__: programmed ADC resolution when limited to 6 or 8 bits. + * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ @@ -680,26 +869,25 @@ typedef struct /** * @brief Verify the ADC converted data alignment. - * @param __ALIGN__: programmed ADC converted data alignment. + * @param __ALIGN__ programmed ADC converted data alignment. * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) - */ + */ #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) - /** * @brief Verify the ADC scan mode. - * @param __SCAN_MODE__: programmed ADC scan mode. + * @param __SCAN_MODE__ programmed ADC scan mode. * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) - */ + */ #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ - ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) - + ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) + /** * @brief Verify the ADC edge trigger setting for regular group. - * @param __EDGE__: programmed ADC edge trigger setting. + * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) - */ + */ #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ @@ -707,51 +895,50 @@ typedef struct /** * @brief Verify the ADC regular conversions external trigger. - * @param __REGTRIG__: programmed ADC regular conversions external trigger. + * @param __HANDLE__ ADC handle + * @param __REGTRIG__ programmed ADC regular conversions external trigger. * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) - */ -#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - \ - ((__REGTRIG__) == ADC_SOFTWARE_START) ) + */ +#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START) ) /** * @brief Verify the ADC regular conversions check for converted data availability. - * @param __EOC_SELECTION__: converted data availability check. + * @param __EOC_SELECTION__ converted data availability check. * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) - */ + */ #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ - ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) || \ - ((__EOC_SELECTION__) == ADC_EOC_SINGLE_SEQ_CONV) ) - + ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) + /** * @brief Verify the ADC regular conversions overrun handling. - * @param __OVR__: ADC regular conversions overrun handling. + * @param __OVR__ ADC regular conversions overrun handling. * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) - */ + */ #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ - ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) - + ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) + /** * @brief Verify the ADC conversions sampling time. - * @param __TIME__: ADC conversions sampling time. + * @param __TIME__ ADC conversions sampling time. * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) */ -#if defined (ADC_SMPR1_SMPPLUS) +#if defined(ADC_SMPR1_SMPPLUS) #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ @@ -774,7 +961,7 @@ typedef struct /** * @brief Verify the ADC regular channel setting. - * @param __CHANNEL__: programmed ADC regular channel. + * @param __CHANNEL__ programmed ADC regular channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ @@ -797,7 +984,7 @@ typedef struct /** * @} */ - + /* Private constants ---------------------------------------------------------*/ @@ -812,132 +999,683 @@ typedef struct /* Minimum ADC Clock frequency is 0.14 MHz */ /* Maximum conversion time is */ /* 653 / 0.14 MHz = 4.66 ms */ -#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5) /*!< ADC stop time-out value */ +#define ADC_STOP_CONVERSION_TIMEOUT ( 5U) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ /* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120) +#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) /** * @} */ -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Macro ADC Exported Macros +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. * @{ */ /** @brief Reset ADC handle state. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle * @retval None */ -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) - - -/** @brief Check whether the specified ADC interrupt source is enabled or not. - * @param __HANDLE__: ADC handle. - * @param __INTERRUPT__: ADC interrupt source to check +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) + +/** + * @brief Enable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source - * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR, ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \ - )? SET : RESET \ - ) - -/** - * @brief Enable an ADC interrupt. - * @param __HANDLE__: ADC handle. - * @param __INTERRUPT__: ADC Interrupt to enable - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source - * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR, ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. - * @retval None - */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable an ADC interrupt. - * @param __HANDLE__: ADC handle. - * @param __INTERRUPT__: ADC Interrupt to disable - * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source - * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR, ADC overrun interrupt source - * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source - * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source - * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + /** * @brief Check whether the specified ADC flag is set or not. - * @param __HANDLE__: ADC handle. - * @param __FLAG__: ADC flag to check + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag - * @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR, ADC overrun flag - * @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag - * @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag. - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @retval State of flag (TRUE or FALSE). */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) /** - * @brief Clear a specified ADC flag. - * @param __HANDLE__: ADC handle. - * @param __FLAG__: ADC flag to clear + * @brief Clear the specified ADC flag. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag - * @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR, ADC overrun flag - * @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag - * @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag. - * @note Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR). + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval None */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__)) - +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** + * @} + */ + +/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals ADC_CHANNEL_x. + * @note Example: + * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + +/** + * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n + * (1, 2, 3, 4) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * ADC_CHANNEL_1, ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 (7) + * @arg @ref ADC_CHANNEL_2 (7) + * @arg @ref ADC_CHANNEL_3 (7) + * @arg @ref ADC_CHANNEL_4 (7) + * @arg @ref ADC_CHANNEL_5 (7) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances.\n + * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). + * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + */ +#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) + * @arg @ref ADC_CHANNEL_VBAT (4) + * @arg @ref ADC_CHANNEL_DAC1CH1 (5) + * @arg @ref ADC_CHANNEL_DAC1CH2 (5) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) + * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) + * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) + * + * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n + * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n + * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n + * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n + * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n + * (6) On STM32L4, parameter available on devices with several ADC instances. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) +#endif + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ + __LL_ADC_COMMON_INSTANCE((__ADCx__)) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ + __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 serie, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 serie, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On STM32L4, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @} + */ /** * @} @@ -965,7 +1703,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); */ /** @addtogroup ADC_Exported_Functions_Group2 - * @brief IO operation functions + * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c index e43572a990..249566e9a9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.c @@ -2,22 +2,20 @@ ****************************************************************************** * @file stm32l4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions - * ++ Start, stop, get result of conversions of injected - * group, using 2 possible modes: polling, interruption. + * ++ Start, stop, get result of conversions of ADC group injected, + * using 2 possible modes: polling, interruption. * ++ Calibration * +++ ADC automatic self-calibration * +++ Calibration factors get or set * ++ Multimode feature when available * + Control functions - * ++ Channels configuration on injected group + * ++ Channels configuration on ADC group injected * + State functions - * ++ Injected group queues management + * ++ ADC group injected contexts queue management * Other functions (generic functions) are available in file * "stm32l4xx_hal_adc.c". * @@ -83,10 +81,6 @@ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ -#define ADC_CFGR2_INJ_FIELDS ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR |\ - ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated - when no conversion is on-going (neither regular nor injected) */ - /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ @@ -95,7 +89,7 @@ /* 112 / 140,000 = 0.8 ms */ /* At maximum CPU speed (80 MHz), this means */ /* 0.8 ms * 80 MHz = 64000 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT ((uint32_t) 64000) /*!< ADC calibration time-out value */ +#define ADC_CALIBRATION_TIMEOUT (64000U) /*!< ADC calibration time-out value */ /** * @} @@ -122,13 +116,13 @@ (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. - - (+) Start conversion of injected group. - (+) Stop conversion of injected group. - (+) Poll for conversion complete on injected group. - (+) Get result of injected channel conversion. - (+) Start conversion of injected group and enable interruptions. - (+) Stop conversion of injected group and disable interruptions. + + (+) Start conversion of ADC group injected. + (+) Stop conversion of ADC group injected. + (+) Poll for conversion complete on ADC group injected. + (+) Get result of ADC group injected channel conversion. + (+) Start conversion of ADC group injected and enable interruptions. + (+) Stop conversion of ADC group injected and disable interruptions. (+) When multimode feature is available, start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. @@ -144,9 +138,9 @@ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @param hadc ADC handle * @param SingleDiff Selection of single-ended or differential input - * This parameter can be one of the following values: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * This parameter can be one of the following values: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) @@ -157,7 +151,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + /* Process locked */ __HAL_LOCK(hadc); @@ -169,10 +163,13 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Select calibration mode single ended or differential ended */ MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff); @@ -186,8 +183,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ - /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -196,8 +194,10 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t } } - /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); } else { @@ -215,13 +215,12 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t } /** - * @brief Get the calibration factor from automatic conversion result. - * @param hadc: ADC handle. - * @param SingleDiff: Selection of single-ended or differential input - * This parameter can be one of the following values: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @retval Converted value + * @brief Get the calibration factor. + * @param hadc ADC handle. + * @param SingleDiff This parameter can be only: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @retval Calibration value. */ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) { @@ -229,7 +228,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - /* Return the selected ADC calibration value */ + /* Return the selected ADC calibration value */ if (SingleDiff == ADC_DIFFERENTIAL_ENDED) { return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT); @@ -241,13 +240,13 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single } /** - * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going. - * @param hadc: ADC handle. - * @param SingleDiff: Selection of single-ended or differential input. - * This parameter can be one of the following values: - * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended - * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended - * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum) + * @brief Set the calibration factor to overwrite automatic conversion result. + * ADC must be enabled and no conversion is ongoing. + * @param hadc ADC handle + * @param SingleDiff This parameter can be only: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) @@ -281,6 +280,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + /* Update ADC error code */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Update ADC state machine to error */ tmp_hal_status = HAL_ERROR; @@ -301,7 +302,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. - * @param hadc: ADC handle. + * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) @@ -353,9 +354,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - /* Update ADC state */ - /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY); + + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - by default if ADC is Master or Independent or if multimode feature is not available @@ -365,11 +370,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - - /* Clear injected group conversion flag */ + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ @@ -388,8 +397,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: set ADSTART only if JAUTO is cleared */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) { SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; @@ -400,19 +407,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* hadc is the handle of a Slave ADC with dual injected conversions enabled: ADSTART is not set */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* Process unlocked */ - __HAL_UNLOCK(hadc); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); - } /* if (tmp_hal_status == HAL_OK) */ + } /* Return function status */ return tmp_hal_status; - } /* if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */ + } } /** @@ -428,7 +433,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). - * @param hadc: ADC handle. + * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) @@ -456,16 +461,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } @@ -479,23 +485,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /** * @brief Wait for injected group conversion to be completed. - * @param hadc: ADC handle - * @param Timeout: Timeout value in millisecond. + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is * checked and cleared depending on AUTDLY bit status. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart; - uint32_t tmp_Flag_End = 0x00; - ADC_TypeDef *tmpADC_Master; - uint32_t tmp_cfgr = 0x00; - uint32_t tmp_cfgr_jqm_autdly = 0x00; - uint32_t tmp_jeos_raised = 0x01; /* by default, assume that JEOS is set, - tmp_jeos_raised will be corrected - accordingly during API execution */ - + uint32_t tickstart = 0U; + uint32_t tmp_Flag_End = 0U; + uint32_t tmp_cfgr = 0U; + ADC_TypeDef *tmpADC_Master; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -531,47 +533,51 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u } } - /* Next, to clear the polled flag as well as to update the handle State, - JEOS is checked and the relevant configuration registers are retrieved. - JQM, JAUTO and CONT bits will have to be read for the State update, - AUTDLY for JEOS clearing. */ - /* 1. Check whether or not JEOS is set */ - if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS)) + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ + if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == SET) { - tmp_jeos_raised = 0; - } - /* 2. Check whether or not hadc is the handle of a Slave ADC with dual - injected conversions enabled. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET) - { - /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: - check JQM and AUTDLY bits directly in ADC CFGR register */ - tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR); - } - else - { - /* hadc is the handle of a Slave ADC with dual injected conversions enabled: - need to check JQM and AUTDLY bits of Master ADC CFGR register */ - tmpADC_Master = ADC_MASTER_REGISTER(hadc); - tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR); - } - /* 3. Check whether or not hadc is the handle of a Slave ADC with dual - regular conversions enabled. */ - if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) - { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits directly in ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { - /* hadc is not the handle of a Slave ADC with dual regular conversions enabled: - check JAUTO and CONT bits of Master ADC CFGR register */ tmpADC_Master = ADC_MASTER_REGISTER(hadc); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger or by automatic injected conversion */ + /* from group regular. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || + ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) + { + /* Check whether end of sequence is reached */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) ) + { + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + } + } /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_JEOS) @@ -580,46 +586,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ /* For injected groups, no new conversion will start before JEOS is */ /* cleared. */ - /* Note that 1. reading ADCx_JDRy clears JEOC. */ - /* 2. in multimode with dual injected conversions enabled (when */ - /* multimode feature is available), Master AUTDLY bit is */ - /* checked. */ - if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET) + if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); } } else { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); } - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - /* Are injected conversions over ? This is the case if JEOS is set AND - - injected conversions are software-triggered when injected queue management is disabled - OR - - auto-injection is enabled, continuous mode is disabled, - and regular conversions are software-triggered */ - - if (tmp_jeos_raised) - { - if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM)) - && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc))) )) - { - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - } - - /* Return API HAL status */ return HAL_OK; } @@ -633,7 +609,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. - * @param hadc: ADC handle. + * @param hadc ADC handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) @@ -649,7 +625,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) } else { - /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error @@ -684,8 +659,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY); + + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - by default if ADC is Master or Independent or if multimode feature is not available @@ -694,11 +674,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - - /* Clear injected group conversion flag */ + + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET) @@ -738,8 +723,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: set ADSTART only if JAUTO is cleared */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) { SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; @@ -750,8 +733,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* hadc is the handle of a Slave ADC with dual injected conversions enabled: ADSTART is not set */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* Process unlocked */ - __HAL_UNLOCK(hadc); } } else @@ -762,7 +743,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Return function status */ return tmp_hal_status; -} + } } /** @@ -781,7 +762,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) @@ -805,7 +786,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); - if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); @@ -813,17 +794,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { - /* Clear HAL_ADC_STATE_INJ_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } @@ -834,8 +816,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) return tmp_hal_status; } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. * @note Multimode must have been previously configured using @@ -846,9 +827,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) * @note State field of Slave ADC handle is not updated in this configuration: * user should not rely on it for information related to Slave regular * conversions. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) - * @param pData: Destination Buffer address. - * @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes). + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) + * @param pData Destination Buffer address. + * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -877,7 +858,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t if (tmphadcSlave.Instance == NULL) { - /* Update ADC state machine to error */ + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ @@ -886,7 +867,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t return HAL_ERROR; } - /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); @@ -898,15 +878,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Start multimode conversion of ADCs pair */ if (tmp_hal_status == HAL_OK) { - /* Update Master State */ - /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - - + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), + HAL_ADC_STATE_REG_BUSY); + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; @@ -917,8 +896,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ @@ -927,20 +905,23 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); - + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); } else { @@ -963,7 +944,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) @@ -1053,10 +1034,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) ADC_Disable(hadc); ADC_Disable(&tmphadcSlave); } - /* Change ADC state (ADC master) */ - /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); + /* Set ADC state (ADC master) */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } /* Process unlocked */ @@ -1068,7 +1050,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. - * @param hadc: ADC handle of ADC Master (handle of ADC Slave must not be used) + * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) @@ -1079,12 +1061,12 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Return the multi mode conversion value */ return tmpADC_Common->CDR; } -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Get ADC injected group conversion result. @@ -1105,8 +1087,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). - * @param hadc: ADC handle - * @param InjectedRank: the converted ADC injected rank. + * @param hadc ADC handle + * @param InjectedRank the converted ADC injected rank. * This parameter can be one of the following values: * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2 @@ -1146,7 +1128,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa /** * @brief Injected conversion complete callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) @@ -1165,7 +1147,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts). - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) @@ -1180,7 +1162,7 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog 2 callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) @@ -1195,7 +1177,7 @@ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog 3 callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) @@ -1211,7 +1193,7 @@ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) /** * @brief End Of Sampling callback in non-blocking mode. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) @@ -1224,13 +1206,11 @@ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) */ } - - /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral if no * conversion is on going on injected group. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) @@ -1261,9 +1241,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ @@ -1287,7 +1268,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) * disable interrution of end-of-conversion, * disable ADC peripheral if no conversion is on going * on injected group. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) @@ -1320,9 +1301,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) /* if no issue reported */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } else @@ -1346,7 +1328,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. * For multimode (when multimode feature is available), * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) @@ -1403,9 +1385,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } } else @@ -1421,8 +1404,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) return tmp_hal_status; } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. * @note Multimode is kept enabled after this function. Multimode DMA bits @@ -1433,7 +1415,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) * @note In case of DMA configured in circular mode, function * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. - * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) @@ -1547,7 +1529,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* Return function status */ return tmp_hal_status; } -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -1600,19 +1582,18 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) * for each context (3 channels x 2 contexts = 6 calls). Conversion can * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. - * @param hadc: ADC handle - * @param sConfigInjected: Structure of ADC injected group and ADC channel for + * @param hadc ADC handle + * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - ADC_Common_TypeDef *tmpADC_Common; uint32_t tmpOffsetShifted; - uint32_t wait_loop_index = 0; + uint32_t wait_loop_index = 0U; - uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0; + uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1621,7 +1602,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); @@ -1677,9 +1658,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ - + if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1) ) + (sConfigInjected->InjectedNbrOfConversion == 1U) ) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -1695,19 +1676,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) | - sConfigInjected->ExternalTrigInjecConv | - sConfigInjected->ExternalTrigInjecConvEdge ); + tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); + tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); } - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; @@ -1726,7 +1706,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ /* call of the context under setting */ - if (hadc->InjectionConfig.ChannelCount == 0) + if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ @@ -1734,7 +1714,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ - hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000; + hadc->InjectionConfig.ContextQueue = 0x00000000U; /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ @@ -1746,21 +1726,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ - if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) | - sConfigInjected->ExternalTrigInjecConv | - sConfigInjected->ExternalTrigInjecConvEdge ); + tmp_JSQR_ContextQueueBeingBuilt = ( (sConfigInjected->InjectedNbrOfConversion - 1U) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) ); } - } /* if (hadc->InjectionConfig.ChannelCount == 0) */ + } - /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ @@ -1768,7 +1747,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Set the JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); - + /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; @@ -1779,7 +1758,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ - if (hadc->InjectionConfig.ChannelCount == 0) + if (hadc->InjectionConfig.ChannelCount == 0U) { MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); } @@ -1801,7 +1780,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) | ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) ); } - /* If auto-injected mode is enabled: Injected discontinuous setting is */ + /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { @@ -1864,11 +1843,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* - Right bit shift */ /* Enable OverSampling mode */ - - MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS, - ADC_CFGR2_JOVSE | - sConfigInjected->InjecOversampling.Ratio | - sConfigInjected->InjecOversampling.RightBitShift ); + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + sConfigInjected->InjecOversampling.Ratio | + sConfigInjected->InjecOversampling.RightBitShift + ); } else { @@ -1876,18 +1858,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); } - /* Sampling time configuration of the selected channel */ - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) - { - /* Clear the old sample time and set the new one */ - ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } - else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */ - { - /* Clear the old sample time and set the new one */ - ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } +#if defined(ADC_SMPR1_SMPPLUS) + /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ + if(sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); + } + else + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); + } +#else + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); +#endif /* Configure the offset: offset enable/disable, channel, offset value */ @@ -1895,75 +1887,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); - switch (sConfigInjected->InjectedOffsetNumber) + if(sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { - case ADC_OFFSET_1: - /* Configure offset register 1: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR1, - ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN, - ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_2: - /* Configure offset register 2: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR2, - ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2_EN, - ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_3: - /* Configure offset register 3: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR3, - ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3_EN, - ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - case ADC_OFFSET_4: - /* Configure offset register 1: */ - /* - Enable offset */ - /* - Set channel number */ - /* - Set offset value */ - MODIFY_REG(hadc->Instance->OFR4, - ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4_EN, - ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted); - break; - - /* Case ADC_OFFSET_NONE */ - default : - /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */ - if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + /* Set ADC selected offset number */ + LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted); + + } + else + { + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is disabled. */ + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR1*/ - CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR2*/ - CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR3*/ - CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } - if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) + if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - /* Disable offset OFR4*/ - CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } - break; } - } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ + } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ @@ -1971,32 +1923,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { + /* Set mode single-ended or differential input of the selected ADC channel */ + LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); + /* Configuration of differential mode */ - if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) + if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Disable differential mode (default mode: single-ended) */ - CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel)); - } - else - { - /* Enable differential mode */ - SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel)); - - /* Sampling time configuration of channel ADC_IN+1 (negative input). - Starting from channel 9, SMPR2 register must be configured. */ - if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9) - { - /* Clear the old sample time and set the new one */ - ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1); - } - else /* For channels 0 to 8 */ - { - /* Clear the old sample time and set the new one */ - ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1); - } + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime); } - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ @@ -2004,18 +1940,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* HAL_ADC_DeInit(). */ /* Configuration of common ADC parameters */ - - tmpADC_Common = ADC_COMMON_REGISTER(hadc); - /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || - ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && - (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) - ) + if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || + ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || + ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) + ) { /* Configuration of common ADC parameters (continuation) */ /* Software is allowed to change common parameters only when all ADCs */ @@ -2027,11 +1960,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000)); while(wait_loop_index != 0) { wait_loop_index--; @@ -2042,16 +1975,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); } } else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) { if (ADC_VREFINT_INSTANCE(hadc)) { - SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); - } - } + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + } + } } /* If the requested internal measurement path has already been enabled */ /* and other ADC of the common group are enabled, internal */ @@ -2065,7 +1998,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I } } - } /* if (ADC_IS_ENABLE(hadc) == RESET) */ + } /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -2074,7 +2007,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I return tmp_hal_status; } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: @@ -2087,8 +2020,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I * "ADC_MultiModeTypeDef". * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). - * @param hadc: Master ADC handle - * @param multimode : Structure of ADC multimode configuration + * @param hadc Master ADC handle + * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) @@ -2131,7 +2064,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) ) { /* Pointer to the common control register */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* If multimode is selected, configure all multimode paramaters. */ /* Otherwise, reset multimode parameters (can be used in case of */ @@ -2155,8 +2088,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) { - MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, - multimode->Mode | multimode->TwoSamplingDelay ); + MODIFY_REG(tmpADC_Common->CCR, + ADC_CCR_DUAL | + ADC_CCR_DELAY, + multimode->Mode | + multimode->TwoSamplingDelay + ); } } else /* ADC_MODE_INDEPENDENT */ @@ -2183,14 +2120,13 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Enable Injected Queue @@ -2198,7 +2134,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) @@ -2225,7 +2161,7 @@ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) @@ -2248,7 +2184,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) * be carried out only when ADC is disabled. * @note To enable again the voltage regulator, the user is expected to * resort to HAL_ADC_Init() API. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) @@ -2278,7 +2214,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously * saved calibration factor. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h index 7dc27f8cdb..042c3b7548 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of ADC HAL extended module. ****************************************************************************** * @attention @@ -45,7 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" - + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -59,48 +57,16 @@ * @{ */ -/** - * @brief ADC group injected contexts queue configuration - */ -typedef struct -{ - uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each - HAL_ADCEx_InjectedConfigChannel() call to finally initialize - JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ - - uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ -}ADC_InjectionConfigTypeDef; - /** - * @brief ADC handle Structure definition - */ -typedef struct -{ - ADC_TypeDef *Instance; /*!< Register base address */ - - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - - HAL_LockTypeDef Lock; /*!< ADC locking object */ - - __IO uint32_t State; /*!< ADC communication state (bit-map of ADC states) */ - - __IO uint32_t ErrorCode; /*!< ADC Error code */ - - ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ -}ADC_HandleTypeDef; - -/** - * @brief ADC Injected Conversion Oversampling structure definition + * @brief ADC Injected Conversion Oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADCEx_Oversampling_Ratio */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. - This parameter can be a value of @ref ADCEx_Right_Bit_Shift */ + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ }ADC_InjOversamplingTypeDef; /** @@ -122,11 +88,11 @@ typedef struct typedef struct { uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. - This parameter can be a value of @ref ADC_channels + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. - This parameter must be a value of @ref ADCEx_injected_rank. + This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ @@ -134,7 +100,7 @@ typedef struct Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), @@ -144,7 +110,7 @@ typedef struct uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. - This parameter must be a value of @ref ADCEx_SingleDifferential. + This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. @@ -154,7 +120,7 @@ typedef struct of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. - This parameter can be a value of @ref ADCEx_OffsetNumber. + This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. @@ -186,7 +152,7 @@ typedef struct Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. @@ -203,7 +169,7 @@ typedef struct uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_injected_external_trigger_source. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. @@ -211,18 +177,17 @@ typedef struct If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ - - uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ - - ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. - Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + + uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ + + ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. + Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. + Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ }ADC_InjectionConfTypeDef; - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). @@ -231,19 +196,19 @@ typedef struct typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. - This parameter can be a value of @ref ADCEx_Common_mode. */ + This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) - This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */ + This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases. + This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ }ADC_MultiModeTypeDef; -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -251,7 +216,7 @@ typedef struct /* Exported constants --------------------------------------------------------*/ - /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants +/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants * @{ */ @@ -259,23 +224,23 @@ typedef struct * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /*!< Event 0 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /*!< Event 1 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /*!< Event 2 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 3 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /*!< Event 4 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 5 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 6 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /*!< Event 8 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) /*!< Event 9 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) /*!< Event 10 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) /*!< Event 12 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */ -#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /*!< Event 15 triggers injected group conversion start */ -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers injected group conversion start */ +#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -283,288 +248,107 @@ typedef struct /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /*!< Injected conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /*!< Injected conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ -/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode +/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ -#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /*!< ADC channel set in single-ended input mode */ -#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /*!< ADC channel set in differential mode */ +#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ +#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ /** * @} */ -/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number +/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number * @{ */ -#define ADC_OFFSET_NONE ((uint32_t)0x00) /*!< No offset correction */ -#define ADC_OFFSET_1 ((uint32_t)0x01) /*!< Offset correction to apply to a first channel */ -#define ADC_OFFSET_2 ((uint32_t)0x02) /*!< Offset correction to apply to a second channel */ -#define ADC_OFFSET_3 ((uint32_t)0x03) /*!< Offset correction to apply to a third channel */ -#define ADC_OFFSET_4 ((uint32_t)0x04) /*!< Offset correction to apply to a fourth channel */ +#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ +#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ +#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ /** * @} */ -/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */ -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */ -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */ -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */ +#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ +#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ +#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ +#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ /** * @} */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/** @defgroup ADCEx_Common_mode ADC Extended multimode dual mode +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */ -#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /*!< Combined regular simultaneous + injected simultaneous mode */ -#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /*!< Combined regular simultaneous + alternate trigger mode */ -#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Combined Interleaved mode + injected simultaneous mode */ -#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)) /*!< Injected simultaneous mode only */ -#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)) /*!< Regular simultaneous mode only */ -#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only */ -#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)) /*!< Alternate trigger mode only */ -/** - * @} - */ +#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ +#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ +#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ +#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ +#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ -/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA mode for multimode +/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution * @{ */ -#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ -#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ -#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ +#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ +#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ +#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** * @} */ -/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended delay between 2 sampling phases +/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /*!< 1 ADC clock cycle delay */ -#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /*!< 2 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /*!< 3 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 4 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /*!< 5 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) /*!< 6 ADC clock cycles delay */ -#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */ -#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */ +#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ +#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ /** * @} */ -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -/** @defgroup ADCEx_Common_mode ADC Extended Independent ADC Mode + +/** + * @} + */ +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups * @{ */ -#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ +#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ +#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ /** * @} */ -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ - -/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection - * @{ - */ -#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /*!< Analog watchdog 1 selection */ -#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /*!< Analog watchdog 2 selection */ -#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /*!< Analog watchdog 3 selection */ -/** - * @} - */ - -/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode - * @{ - */ -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /*!< No analog watchdog selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) /*!< Analog watchdog applied to a regular group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to an injected group single channel */ -#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ -#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to regular and injected groups all channels */ -/** - * @} - */ - -/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group - * @{ - */ -#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) /*!< ADC regular group selection */ -#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC injected group selection */ -#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */ -/** - * @} - */ - -/** @defgroup ADCEx_Event_type ADC Extended Event Type - * @{ - */ -#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ -#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ -#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ -#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ -#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ -/** - * @} - */ -#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ - -/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition - * @{ - */ -#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready (ADRDY) interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ -#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ -#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ -#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ - -#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ - -/** - * @} - */ - -/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition - * @{ - */ -#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */ -#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ -#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ -#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ -#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ -#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ -#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ -#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ - -#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ - -#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ - ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ - ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ - -/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ - ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ - ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ - -/** - * @} - */ - - -/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank - * @{ - */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */ -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */ -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */ -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */ -/** - * @} - */ - - - -/** @defgroup ADCEx_Oversampling_Ratio ADC Extended Oversampling Ratio - * @{ - */ - -#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */ -#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /*!< ADC Oversampling ratio 4x */ -#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /*!< ADC Oversampling ratio 8x */ -#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 16x */ -#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /*!< ADC Oversampling ratio 32x */ -#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 64x */ -#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!< ADC Oversampling ratio 128x */ -#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR)) /*!< ADC Oversampling ratio 256x */ -/** - * @} - */ - -/** @defgroup ADCEx_Right_Bit_Shift ADC Extended Oversampling Right Shift - * @{ - */ -#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */ -#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /*!< ADC 1 bit shift for oversampling */ -#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /*!< ADC 2 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 3 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /*!< ADC 4 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)) /*!< ADC 5 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)) /*!< ADC 6 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 7 bits shift for oversampling */ -#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /*!< ADC 8 bits shift for oversampling */ -/** - * @} - */ - -/** @defgroup ADCEx_Triggered_Oversampling_Mode ADC Extended Triggered Regular Oversampling - * @{ - */ -#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< A single trigger for all channel oversampled conversions */ -#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /*!< A trigger for each oversampled conversion */ -/** - * @} - */ - -/** @defgroup ADCEx_Regular_Oversampling_Mode ADC Extended Regular Oversampling Continued or Resumed Mode - * @{ - */ -#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /*!< Oversampling buffer maintained during injection sequence */ -#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /*!< Oversampling buffer zeroed during injection sequence */ -/** - * @} - */ - -/** @defgroup ADC_sampling_times ADC Sampling Times - * @{ - */ -#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000) /*!< Sampling time 2.5 ADC clock cycle */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR1_SMPPLUS) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time - replaces all sampling time 2.5 ADC clock cycles. These 2 sampling - times cannot be used simultaneously. */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ -#define ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ -#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */ -#define ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles */ -#define ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */ -#define ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles */ -#define ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */ -#define ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 640.5 ADC clock cycles */ -/** - * @} - */ - /** @defgroup ADC_CFGR_fields ADCx CFGR fields * @{ */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ @@ -578,15 +362,15 @@ typedef struct ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /** * @} - */ + */ /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields * @{ */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_SMPR1_SMPPLUS) #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ @@ -595,44 +379,44 @@ typedef struct #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ - ADC_SMPR1_SMP0) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ + ADC_SMPR1_SMP0) +#endif /** * @} - */ - + */ + /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields * @{ */ /* ADC_CFGR fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) + (neither regular nor injected) is on-going */ +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) +#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) #else -#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) +#endif /** * @} - */ - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/** @defgroup ADCEx_DFSDM_Mode_Configuration ADC Extended DFSDM mode configuration + */ + +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) +/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define ADC_DFSDM_MODE_DISABLE ((uint32_t)0x00000000) /*!< DFSDM mode configuration disabled */ -#define ADC_DFSDM_MODE_ENABLE ((uint32_t)ADC_CFGR_DFSDMCFG) /*!< DFSDM mode configuration enabled */ +#define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} - */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ - + */ +#endif + /** * @} */ /* Exported macros -----------------------------------------------------------*/ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros * @{ */ @@ -648,300 +432,179 @@ typedef struct * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases * mentionned above. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ - CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_DUAL) + LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) /** * @} */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ -/* Private macros -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros * @{ */ - +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + /** * @brief Test if conversion trigger of injected group is software start * or external trigger. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (software start) or RESET (external trigger). */ -#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) /** * @brief Check if conversion is on going on regular or injected groups. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (conversion is on going) or RESET (no conversion is on going). */ #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ ) ? RESET : SET) - + /** * @brief Check if conversion is on going on injected group. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (conversion is on going) or RESET (no conversion is on going). */ -#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \ - ) ? RESET : SET) - +#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ + (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) + /** * @brief Check whether or not ADC is independent. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC3) \ )? \ SET \ : \ RESET \ - ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + ) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) #endif - -/** - * @brief Set the sample time for Channels numbers between 0 and 9. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__: Channel number. - * @retval None - */ -#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__))) - -/** - * @brief Set the sample time for Channels numbers between 10 and 18. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__: Channel number. - * @retval None - */ -#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10)))) - -/** - * @brief Write SMPR1 register. - * @param __HANDLE__ : ADC handle. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__ : Channel number. - * @retval None - */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - do { \ - if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \ - { \ - SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \ - { \ - CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - MODIFY_REG((__HANDLE__)->Instance->SMPR1, \ - ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \ - ADC_SMPR1((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \ - } while(0) -#else -#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - MODIFY_REG((__HANDLE__)->Instance->SMPR1, \ - ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \ - ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__))) -#endif - -/** - * @brief Write SMPR2 register. - * @param __HANDLE__ : ADC handle. - * @param __SAMPLETIME__: Sample time parameter. - * @param __CHANNELNB__ : Channel number. - * @retval None - */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - do { \ - if((__SAMPLETIME__) == ADC_SAMPLETIME_3CYCLES_5) \ - { \ - SET_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - else if ((__SAMPLETIME__) == ADC_SAMPLETIME_2CYCLES_5) \ - { \ - CLEAR_BIT((__HANDLE__)->Instance->SMPR1, ADC_SMPR1_SMPPLUS); \ - } \ - MODIFY_REG((__HANDLE__)->Instance->SMPR2, \ - ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \ - ADC_SMPR2((__SAMPLETIME__) & 0x7FFFFFFF, (__CHANNELNB__))); \ - } while(0) -#else -#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ - MODIFY_REG((__HANDLE__)->Instance->SMPR2, \ - ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \ - ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__))) -#endif - - -/** - * @brief Set the selected regular Channel rank for rank between 1 and 4. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__))) - -/** - * @brief Set the selected regular Channel rank for rank between 5 and 9. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5))) - -/** - * @brief Set the selected regular Channel rank for rank between 10 and 14. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10))) - -/** - * @brief Set the selected regular Channel rank for rank between 15 and 16. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. - * @retval None - */ -#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15))) /** * @brief Set the selected injected Channel rank. - * @param __CHANNELNB__: Channel number. - * @param __RANKNB__: Rank number. + * @param __CHANNELNB__ Channel number. + * @param __RANKNB__ Rank number. * @retval None */ -#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2)) - - -/** - * @brief Set the Analog Watchdog 1 channel. - * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1. - * @retval None - */ -#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH)) - -/** - * @brief Configure the channel number in Analog Watchdog 2 or 3. - * @param __CHANNEL__: ADC Channel - * @retval None - */ -#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__)) +#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue - * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode. + * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. * @retval None - */ -#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM)) + */ +#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) /** * @brief Configure ADC discontinuous conversion mode for injected group - * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode. + * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. * @retval None */ -#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN)) +#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) /** * @brief Configure ADC discontinuous conversion mode for regular group - * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode. - * @retval None - */ -#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN)) -/** - * @brief Configure the number of discontinuous conversions for regular group. - * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions. + * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. * @retval None */ -#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM)) +#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) + +/** + * @brief Configure the number of discontinuous conversions for regular group. + * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. + * @retval None + */ +#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << ADC_CFGR_DISCNUM_Pos) /** * @brief Configure the ADC auto delay mode. - * @param __AUTOWAIT__: Auto delay bit enable or disable. + * @param __AUTOWAIT__ Auto delay bit enable or disable. * @retval None */ -#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY)) +#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) /** * @brief Configure ADC continuous conversion mode. - * @param __CONTINUOUS_MODE__: Continuous mode. + * @param __CONTINUOUS_MODE__ Continuous mode. * @retval None */ -#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT)) - +#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) + /** * @brief Configure the ADC DMA continuous request. - * @param __DMACONTREQ_MODE__: DMA continuous request mode. + * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None - */ -#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG)) - + */ +#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) /** * @brief Configure the channel number into offset OFRx register. - * @param __CHANNEL__: ADC Channel. + * @param __CHANNEL__ ADC Channel. * @retval None */ -#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH)) +#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) /** * @brief Configure the channel number into differential mode selection register. - * @param __CHANNEL__: ADC Channel. + * @param __CHANNEL__ ADC Channel. * @retval None */ #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) /** * @brief Configure calibration factor in differential mode to be set into calibration register. - * @param __CALIBRATION_FACTOR__: Calibration factor value. + * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval None */ -#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) +#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) + /** * @brief Calibration factor in differential mode to be retrieved from calibration register. - * @param __CALIBRATION_FACTOR__: Calibration factor value. + * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval None - */ -#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) - + */ +#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) + /** * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. - * @param __THRESHOLD__: Threshold value. + * @param __THRESHOLD__ Threshold value. * @retval None */ #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Configure the ADC DMA continuous request for ADC multimode. - * @param __DMACONTREQ_MODE__: DMA continuous request mode. + * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None - */ -#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG)) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ - + */ +#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Enable the ADC peripheral. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) /** * @brief Verification of hardware constraints before ADC can be enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) */ #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ @@ -950,10 +613,10 @@ typedef struct ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ ) == RESET \ ) ? SET : RESET) - + /** * @brief Disable the ADC peripheral. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_DISABLE(__HANDLE__) \ @@ -961,17 +624,17 @@ typedef struct (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ } while(0) - + /** * @brief Verification of hardware constraints before ADC can be disabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) */ #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ (( ( ((__HANDLE__)->Instance->CR) & \ (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ ) ? SET : RESET) - + /** * @brief Shift the offset with respect to the selected ADC resolution. * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. @@ -980,8 +643,8 @@ typedef struct * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). - * @param __HANDLE__: ADC handle - * @param __OFFSET__: Value to be shifted + * @param __HANDLE__ ADC handle + * @param __OFFSET__ Value to be shifted * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ @@ -996,8 +659,8 @@ typedef struct * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). - * @param __HANDLE__: ADC handle - * @param __THRESHOLD__: Value to be shifted + * @param __HANDLE__ ADC handle + * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ @@ -1010,8 +673,8 @@ typedef struct * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). * If resolution 8 bits, no shift. * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). - * @param __HANDLE__: ADC handle - * @param __THRESHOLD__: Value to be shifted + * @param __HANDLE__ ADC handle + * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ @@ -1019,20 +682,9 @@ typedef struct ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \ (__THRESHOLD__) << 2 ) -/** - * @brief Report ADC common register. - * @param __HANDLE__: ADC handle. - * @retval Common control register - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define ADC_COMMON_REGISTER(__HANDLE__) (ADC1_COMMON) -#endif - /** * @brief Report Master Instance. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return same instance if ADC of input handle is independent ADC or if * multimode feature is not available. * @retval Master Instance @@ -1045,17 +697,17 @@ typedef struct : \ (ADC1) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance) #endif - + /** * @brief Clear Common Control Register. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval None */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \ +#if defined(ADC_MULTIMODE_SUPPORT) +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATEN | \ ADC_CCR_TSEN | \ @@ -1064,22 +716,22 @@ typedef struct ADC_CCR_DMACFG | \ ADC_CCR_DELAY | \ ADC_CCR_DUAL ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \ +#else +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATEN | \ ADC_CCR_TSEN | \ ADC_CCR_VREFEN ) -#endif - - -/** + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** * @brief Check whether or not dual conversions are enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ )? \ @@ -1087,38 +739,37 @@ typedef struct : \ RESET \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#else #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET) -#endif - +#endif + /** * @brief Check whether or not dual regular conversions are enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ )? \ - ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ - (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ - (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ + ( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ + (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ + (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ : \ RESET \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#else #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET) #endif - /** * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return SET if multimode feature is not available. * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ )? \ @@ -1126,17 +777,17 @@ typedef struct : \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET) -#endif - +#endif + /** * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return SET if multimode feature is not available. * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ )? \ @@ -1144,18 +795,18 @@ typedef struct : \ ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ - ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined( STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET) -#endif +#endif /** * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note Return SET if multimode feature is not available. * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ )? \ @@ -1164,26 +815,26 @@ typedef struct ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET) -#endif - +#endif + /** * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter. - * @param __INSTANCE__: ADC instance. + * @param __INSTANCE__ ADC instance. * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \ (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ ) ? SET : RESET) - + /** * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define ADC_ANY_OTHER_ENABLED(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) \ )? \ @@ -1195,99 +846,94 @@ typedef struct : \ ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \ ) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET) -#endif - +#endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. - * @param __HANDLE_MASTER__: ADC master handle. - * @param __HANDLE_SLAVE__: ADC slave handle. - * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL. + * @param __HANDLE_MASTER__ ADC master handle. + * @param __HANDLE_SLAVE__ ADC slave handle. + * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ +#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ - /** * @brief Check whether or not multimode is configured in DMA mode. + * @param __HANDLE__ ADC handle. * @note Return RESET if multimode feature is not available. * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled) - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -#define ADC_MULTIMODE_DMA_ENABLED() \ + */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) \ ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \ || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS)) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define ADC_MULTIMODE_DMA_ENABLED() (RESET) -#endif - +#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) (RESET) +#endif /** * @brief Verify the ADC instance connected to the temperature sensor. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -/* The temperature sensor measurement path (channel 17) is available on ADC1 */ + */ +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/* The temperature sensor measurement path (channel 17) is available on ADC1 */ #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ +/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) #endif /** * @brief Verify the ADC instance connected to the battery voltage VBAT. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -/* The battery voltage measurement path (channel 18) is available on ADC1 */ + */ +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/* The battery voltage measurement path (channel 18) is available on ADC1 */ #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) -/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ +/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) #endif /** * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) - */ -/* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ + */ +/* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) - /** * @brief Verify the length of scheduled injected conversions group. - * @param __LENGTH__: number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) - */ -#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) - - + */ +#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) + /** * @brief Calibration factor size verification (7 bits maximum). - * @param __CALIBRATION_FACTOR__: Calibration factor value. + * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) */ -#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F)) +#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) + - /** * @brief Verify the ADC channel setting. - * @param __HANDLE__: ADC handle. - * @param __CHANNEL__: programmed ADC channel. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == ADC_CHANNEL_1) || \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ @@ -1305,12 +951,14 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_18) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT))) + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ - (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == ADC_CHANNEL_1) || \ + (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ @@ -1326,6 +974,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ @@ -1346,7 +995,9 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_15) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ - ((__CHANNEL__) == ADC_CHANNEL_18))) || \ + ((__CHANNEL__) == ADC_CHANNEL_18) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ @@ -1363,16 +1014,18 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) ))) + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \ + ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) ))) #endif - + /** * @brief Verify the ADC channel setting in differential mode. - * @param __HANDLE__: ADC handle. - * @param __CHANNEL__: programmed ADC channel. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) - */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + */ +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -1390,9 +1043,9 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_15) ) #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, - channels 0, 16 to 18 can be only used in single-ended mode. + channels 0, 16 to 18 can be only used in single-ended mode. For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, - channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ + channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ (((__HANDLE__)->Instance) == ADC2)) && \ (((__CHANNEL__) == ADC_CHANNEL_1) || \ @@ -1421,21 +1074,21 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) ))) -#endif - -/** +#endif + +/** * @brief Verify the ADC single-ended input or differential mode setting. - * @param __SING_DIFF__: programmed channel setting. + * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) - */ + */ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) - + /** * @brief Verify the ADC offset management setting. - * @param __OFFSET_NUMBER__: ADC offset management. + * @param __OFFSET_NUMBER__ ADC offset management. * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) - */ + */ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ @@ -1444,7 +1097,7 @@ typedef struct /** * @brief Verify the ADC injected channel setting. - * @param __CHANNEL__: programmed ADC injected channel. + * @param __CHANNEL__ programmed ADC injected channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ @@ -1454,31 +1107,31 @@ typedef struct /** * @brief Verify the ADC injected conversions external trigger. - * @param __INJTRIG__: programmed ADC injected conversions external trigger. + * @param __HANDLE__ ADC handle. + * @param __INJTRIG__ programmed ADC injected conversions external trigger. * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) - */ -#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ - \ - ((__INJTRIG__) == ADC_SOFTWARE_START) ) + */ +#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) /** * @brief Verify the ADC edge trigger setting for injected group. - * @param __EDGE__: programmed ADC edge trigger setting. + * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) */ #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ @@ -1486,10 +1139,10 @@ typedef struct ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Verify the ADC multimode setting. - * @param __MODE__: programmed ADC multimode setting. + * @param __MODE__ programmed ADC multimode setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ @@ -1499,11 +1152,11 @@ typedef struct ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ ((__MODE__) == ADC_DUALMODE_INTERL) || \ - ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) + ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) /** * @brief Verify the ADC multimode DMA access setting. - * @param __MODE__: programmed ADC multimode DMA access setting. + * @param __MODE__ programmed ADC multimode DMA access setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ @@ -1512,7 +1165,7 @@ typedef struct /** * @brief Verify the ADC multimode delay setting. - * @param __DELAY__: programmed ADC multimode delay setting. + * @param __DELAY__ programmed ADC multimode delay setting. * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) */ #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ @@ -1527,11 +1180,11 @@ typedef struct ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Verify the ADC analog watchdog setting. - * @param __WATCHDOG__: programmed ADC analog watchdog setting. + * @param __WATCHDOG__ programmed ADC analog watchdog setting. * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ @@ -1540,7 +1193,7 @@ typedef struct /** * @brief Verify the ADC analog watchdog mode setting. - * @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting. + * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ @@ -1553,7 +1206,7 @@ typedef struct /** * @brief Verify the ADC conversion (regular or injected or both). - * @param __CONVERSION__: ADC conversion group. + * @param __CONVERSION__ ADC conversion group. * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) */ #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ @@ -1562,7 +1215,7 @@ typedef struct /** * @brief Verify the ADC event type. - * @param __EVENT__: ADC event. + * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ @@ -1574,9 +1227,9 @@ typedef struct /** * @brief Verify the ADC oversampling ratio. - * @param __RATIO__: programmed ADC oversampling ratio. + * @param __RATIO__ programmed ADC oversampling ratio. * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) - */ + */ #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ @@ -1588,9 +1241,9 @@ typedef struct /** * @brief Verify the ADC oversampling shift. - * @param __SHIFT__: programmed ADC oversampling shift. + * @param __SHIFT__ programmed ADC oversampling shift. * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) - */ + */ #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ @@ -1603,63 +1256,62 @@ typedef struct /** * @brief Verify the ADC oversampling triggered mode. - * @param __MODE__: programmed ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) /** * @brief Verify the ADC oversampling regular conversion resumed or continued mode. - * @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode. + * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ + */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) - /** * @brief Verify the DFSDM mode configuration. - * @param __HANDLE__: ADC handle. + * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) #else #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /** - * @brief Return the DFSDM configuration mode. - * @param __HANDLE__: ADC handle. + * @brief Return the DFSDM configuration mode. + * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * For this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval DFSDM configuration mode */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) #else #define ADC_CFGR_DFSDM(__HANDLE__) (0x0) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ - +#endif + /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ - */ - + */ + /** @addtogroup ADCEx_Exported_Functions_Group1 * @{ - */ + */ /* IO operation functions *****************************************************/ /* ADC calibration */ @@ -1675,13 +1327,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* h /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + +#if defined(ADC_MULTIMODE_SUPPORT) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); @@ -1693,26 +1345,26 @@ void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* h void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); -/* ADC Regular conversions stop */ +/* ADC group regular conversions stop */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ - + /** @addtogroup ADCEx_Exported_Functions_Group2 * @{ - */ + */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); -#endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ +#endif /* ADC_MULTIMODE_SUPPORT */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); @@ -1725,10 +1377,10 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* h /** * @} */ - + /** * @} - */ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c index 9dfd4d0bec..a78181d858 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.c @@ -2,74 +2,131 @@ ****************************************************************************** * @file stm32l4xx_hal_can.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim - ============================================================================== + ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (++) Connect and configure the involved CAN pins using the - following function HAL_GPIO_Init(); - - (#) Initialize and configure the CAN using HAL_CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or - HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function. + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - @endverbatim - ****************************************************************************** * @attention * @@ -107,553 +164,594 @@ * @{ */ +#if defined(CAN1) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10 +#define CAN_TIMEOUT_VALUE 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** - * @brief Initialize the CAN peripheral according to the specified parameters - * in the CAN_InitStruct structure and initialize the associated handle. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - if(hcan->State == HAL_CAN_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } } - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1); - - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - status = CAN_INITSTATUS_SUCCESS; + return HAL_ERROR; } } - - if(status == CAN_INITSTATUS_SUCCESS) + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Stop the CAN module */ + HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspDeInit(hcan); + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip = hcan->Instance; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + +#if defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (1U) << sFilterConfig->FilterBank; + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + /* Return function status */ return HAL_OK; } else { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Return function status */ return HAL_ERROR; } } -/** - * @brief Configure the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; - -#if defined(CAN2) - /* Select the start slave bank */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); -#endif - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filternbrbitpos; - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); - } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filternbrbitpos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); - } - - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filternbrbitpos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filternbrbitpos; - } - - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; - } - - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filternbrbitpos; - } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) - { - CAN1->FA1R |= filternbrbitpos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitialize the CAN peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) -{ - /* Check CAN handle */ - if(hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_CAN_MspDeInit(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_MspDeInit could be implemented in the user file - */ -} - /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + @endverbatim * @{ */ /** - * @brief Initiate and transmit a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout: Timeout duration. + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + if (hcan->State == HAL_CAN_STATE_READY) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; - if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) - { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get tick */ tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart = 0U; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; /* Return function status */ return HAL_ERROR; @@ -661,545 +759,1084 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) } /** - * @brief Initiate and transmit a CAN frame message in Interrupt mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Check if timeout is reached */ + if (++count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t transmitmailbox; /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) { - /* Process Locked */ - __HAL_LOCK(hcan); - - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) { + /* Select an empty transmit mailbox */ + transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = 1U << transmitmailbox; + /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) + if (pHeader->IDE == CAN_ID_STD) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); } else { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); } - + /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME ); - + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; } } else { - return HAL_BUSY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; } - - return HAL_OK; } /** - * @brief Receive a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. - * @param Timeout: Timeout duration. + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; } } - } - - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) - { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - } - else /* FIFONumber == CAN_FIFO1 */ - { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - /* Return function status */ - return HAL_OK; + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; + aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; + aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; + aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; + aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; + aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; + aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; + aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } } /** - * @brief Receive a correct CAN frame in Interrupt mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) { - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) - { - /* Enable FIFO 0 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); - } - else - { - /* Enable FIFO 1 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); - } - + /* Return function status */ + return HAL_OK; } else { - return HAL_BUSY; - } - - /* Return function status */ - return HAL_OK; -} + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; -/** - * @brief Enter the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) -{ - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ return HAL_ERROR; } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; } /** - * @brief Wake up the CAN peripheral from sleep mode (after that the CAN peripheral - * is in the normal mode). - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) { - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + return HAL_ERROR; } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; } /** - * @brief Handle CAN interrupt request. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) { - if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != RESET) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); - } - } - - /* Check End of reception flag for FIFO0 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); - } - - /* Check End of reception flag for FIFO1 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); - } - - /* Check Error Warning Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - /* No need for clear of Error Warning Flag as read-only */ - } - - /* Check Error Passive Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* No need for clear of Error Passive Flag as read-only */ - } - - /* Check Bus-Off Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - /* No need for clear of Bus-Off Flag as read-only */ - } - - /* Check Last error code Flag */ - if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) - { - switch(hcan->Instance->ESR & CAN_ESR_LEC) - { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != RESET) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } } - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != RESET) + { + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != RESET) + { + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) + { + if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + { + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) + { + if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) + { + if ((msrflags & CAN_MSR_SLAKI) != RESET) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != RESET) + { + if ((msrflags & CAN_MSR_WKUI) != RESET) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != RESET) + { + if ((msrflags & CAN_MSR_ERRI) != RESET) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && + ((esrflags & CAN_ESR_EWGF) != RESET)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && + ((esrflags & CAN_ESR_EPVF) != RESET)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != RESET) && + ((esrflags & CAN_ESR_BOFF) != RESET)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && + ((esrflags & CAN_ESR_LEC) != RESET)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); } /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + if (errorcode != HAL_CAN_ERROR_NONE) { - /* Clear ERRI bit */ - SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); - /* Set the CAN state ready to be able to start again the process */ - hcan->State = HAL_CAN_STATE_READY; + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + /* Call Error callback function */ + /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); - } + } } /** - * @brief Transmission complete callback in non-blocking mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file */ } /** - * @brief Reception complete callback in non-blocking mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1208,7 +1845,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } @@ -1217,45 +1854,94 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process. - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief Return the CAN handle state. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { - /* Return CAN handle state */ - return hcan->State; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + } + + /* Return CAN state */ + return state; } /** * @brief Return the CAN error code. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } +/** + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Reset CAN error code */ + hcan->ErrorCode = 0U; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; + } + + /* Return the status */ + return status; +} + /** * @} */ @@ -1264,145 +1950,14 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ -/** - * @brief Initiate and transmit a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; -} - -/** - * @brief Receive a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - #endif /* HAL_CAN_MODULE_ENABLED */ + /** * @} */ +#endif /* CAN1 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h index f71bf09454..87a0fb0ba8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_can.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -36,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_CAN_H -#define __STM32L4xx_CAN_H +#ifndef STM32L4xx_HAL_CAN_H +#define STM32L4xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,6 +48,7 @@ * @{ */ +#if defined (CAN1) /** @addtogroup CAN * @{ */ @@ -58,63 +57,60 @@ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ - /** * @brief HAL State structures definition */ typedef enum { - HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ -}HAL_CAN_StateTypeDef; +} HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE */ -}CAN_InitTypeDef; + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition @@ -123,27 +119,30 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -152,23 +151,27 @@ typedef struct This parameter can be a value of @ref CAN_filter_scale */ uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ -}CAN_FilterConfTypeDef; +} CAN_FilterTypeDef; /** - * @brief CAN Tx message structure definition + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ @@ -177,70 +180,67 @@ typedef struct This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -}CanTxMsgTypeDef; +} CAN_TxHeaderTypeDef; /** - * @brief CAN Rx message structure definition + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ - -}CanRxMsgTypeDef; +} CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ -typedef struct +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ + CAN_TypeDef *Instance; /*!< Register base address */ - CAN_InitTypeDef Init; /*!< CAN required parameters */ + CAN_InitTypeDef Init; /*!< CAN required parameters */ - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - - HAL_LockTypeDef Lock; /*!< CAN locking object */ - - __IO uint32_t ErrorCode; /*!< CAN Error code */ - -}CAN_HandleTypeDef; +} CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -248,25 +248,39 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */ -#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */ -#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + /** * @} */ -/** @defgroup CAN_InitStatus CAN initialization Status +/** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -274,7 +288,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -286,7 +300,7 @@ typedef struct /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -297,7 +311,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -320,7 +334,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -335,8 +349,8 @@ typedef struct /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -344,8 +358,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ @@ -353,8 +367,8 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ @@ -362,8 +376,8 @@ typedef struct /** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -371,17 +385,27 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ /** * @} */ @@ -389,314 +413,301 @@ typedef struct /** @defgroup CAN_flags CAN Flags * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - /* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ -/** @defgroup CAN_interrupts CAN Interrupts + +/** @defgroup CAN_Interrupts CAN Interrupts * @{ */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ - +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - /** * @} */ /* Exported macros -----------------------------------------------------------*/ -/** @defgroup CAN_Exported_Macro CAN Exported Macros +/** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ -/** @brief Reset CAN handle state. - * @param __HANDLE__: CAN handle. +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** - * @brief Enable the specified CAN interrupt. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt. + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** - * @brief Disable the specified CAN interrupt. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt. + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) - - -/** @brief Check whether the specified CAN interrupt source is enabled or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) - - - -/** - * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) - -/** - * @brief Cancel a transmit request. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) - -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__: specifies the CAN Handle. - * @param __NEWSTATE__: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFO can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** * @} - */ - -/* Exported functions --------------------------------------------------------*/ + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup CAN_Exported_Functions CAN Exported Functions * @{ */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @{ */ -/* addtogroup and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions * @{ */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * @{ */ /* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); -/** - * @} - */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); /** * @} - */ + */ + +/** + * @} + */ /* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + /* Private constants ---------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -/** @defgroup CAN_transmit_constants CAN Transmit Constants - * @{ - */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -/** - * @} - */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) - - +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ @@ -705,64 +716,69 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) - +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) - #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) - #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) - -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) - -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) - -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) - -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) - #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ /** * @} */ -/* Private functions ---------------------------------------------------------*/ +#endif /* CAN1 */ /** * @} */ -/** - * @} - */ - - #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_CAN_H */ +#endif /* STM32L4xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h new file mode 100644 index 0000000000..08fd1017dc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.h @@ -0,0 +1,769 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_can_legacy.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_CAN_LEGACY_H +#define __STM32L4xx_CAN_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(CAN1) +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t BankNumber; /*!< Select the start slave bank filter. + This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO uint32_t ErrorCode; /*!< CAN Error code */ + +}CAN_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */ +#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */ +#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */ +#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */ +#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 ((uint32_t)0x00000200) /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 ((uint32_t)0x00000400) /*!< FIFO1 overrun error */ +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN initialization Status + * @{ + */ +#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +/** + * @} + */ + +/** @defgroup CAN_interrupts CAN Interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ + +/** + * @} + */ + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macro CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state. + * @param __HANDLE__: CAN handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupt. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt. + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupt. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt. + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + + +/** @brief Check whether the specified CAN interrupt source is enabled or not. + * @param __HANDLE__: specifies the CAN Handle. + * @param __INTERRUPT__: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__: specifies the CAN Handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + + + +/** + * @brief Release the specified receive FIFO. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__: specifies the CAN Handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disable the DBG Freeze for CAN. + * @param __HANDLE__: specifies the CAN Handle. + * @param __NEWSTATE__: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFO can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* addtogroup and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +/** @defgroup CAN_transmit_constants CAN Transmit Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +/** + * @} + */ +#define CAN_FLAG_MASK ((uint32_t)0x000000FF) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) + +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) + +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) + +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) + +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) + +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) + +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* CAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CAN_LEGACY_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c index aea11067d4..a6d00340ee 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_comp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief COMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: @@ -17,36 +15,34 @@ ================================================================================ ##### COMP Peripheral features ##### ================================================================================ - - [..] - The STM32L4xx device family integrates two analog comparators instances - COMP1 and COMP2: - (#) The COMP input minus (inverting input) and input plus (non inverting input) + + [..] + The STM32L4xx device family integrates two analog comparators instances: + COMP1, COMP2. + (#) Comparators input minus (inverting input) and input plus (non inverting input) can be set to internal references or to GPIO pins (refer to GPIO list in reference manual). - - (#) The COMP output level is available using HAL_COMP_GetOutputLevel() + + (#) Comparators output level is available using HAL_COMP_GetOutputLevel() and can be redirected to other peripherals: GPIO pins (in mode alternate functions for comparator), timers. (refer to GPIO list in reference manual). - + + (#) The comparators have interrupt capability through the EXTI controller + with wake-up from sleep and stop modes. + (#) Pairs of comparators instances can be combined in window mode (2 consecutive instances odd and even COMP and COMP). - - (#) The comparators have interrupt capability through the EXTI controller - with wake-up from sleep and stop modes: - (++) COMP1 is internally connected to EXTI Line 21 - (++) COMP2 is internally connected to EXTI Line 22 - + From the corresponding IRQ handler, the right interrupt source can be retrieved - using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG(). + using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). ##### How to use this driver ##### ================================================================================ [..] This driver provides functions to configure and program the comparator instances of STM32L4xx devices. - + To use the comparator, perform the following steps: (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): @@ -63,7 +59,7 @@ (++) Select the input plus (non-inverting input) (++) Select the hysteresis (++) Select the blanking source - (++) Select the output polarity + (++) Select the output polarity (++) Select the power mode (++) Select the window mode @@ -153,6 +149,10 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" +#ifdef HAL_COMP_MODULE_ENABLED + +#if defined (COMP1) || defined (COMP2) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -162,8 +162,6 @@ * @{ */ -#ifdef HAL_COMP_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup COMP_Private_Constants @@ -175,15 +173,15 @@ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define COMP_DELAY_STARTUP_US ((uint32_t) 80U) /*!< Delay for COMP startup time */ +#define COMP_DELAY_STARTUP_US (80U) /*!< Delay for COMP startup time */ /* Delay for COMP voltage scaler stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART_SCALER"). */ /* Unit: us */ -#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */ +#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200U) /*!< Delay for COMP voltage scaler stabilization time */ -#define COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t) 30U) +#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /** * @} @@ -221,10 +219,10 @@ */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { - uint32_t tmp_csr = 0; - uint32_t exti_line = 0; - uint32_t comp_voltage_scaler_not_initialized = 0; - __IO uint32_t wait_loop_index = 0; + uint32_t tmp_csr = 0U; + uint32_t exti_line = 0U; + uint32_t comp_voltage_scaler_not_initialized = 0U; + __IO uint32_t wait_loop_index = 0U; HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ @@ -269,15 +267,16 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) comp_voltage_scaler_not_initialized = (READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) == 0); /* Set COMP parameters */ - tmp_csr = (hcomp->Init.InvertingInput | - hcomp->Init.NonInvertingInput | - hcomp->Init.BlankingSrce | - hcomp->Init.Hysteresis | - hcomp->Init.OutputPol | - hcomp->Init.Mode ); + tmp_csr = ( hcomp->Init.NonInvertingInput + | hcomp->Init.InvertingInput + | hcomp->Init.BlankingSrce + | hcomp->Init.Hysteresis + | hcomp->Init.OutputPol + | hcomp->Init.Mode + ); /* Set parameters in COMP register */ - /* Note: Update all bits except read-only, lock and enable bits */ + /* Note: Update all bits except read-only, lock and enable bits */ #if defined (COMP_CSR_INMESEL) MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | @@ -309,14 +308,14 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ - if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0) && - (comp_voltage_scaler_not_initialized != 0) ) + if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0U) && + (comp_voltage_scaler_not_initialized != 0U) ) { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000 * 2U))); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -331,53 +330,53 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET) { - SET_BIT(EXTI->RTSR1, exti_line); + LL_EXTI_EnableRisingTrig_0_31(exti_line); } else { - CLEAR_BIT(EXTI->RTSR1, exti_line); + LL_EXTI_DisableRisingTrig_0_31(exti_line); } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET) { - SET_BIT(EXTI->FTSR1, exti_line); + LL_EXTI_EnableFallingTrig_0_31(exti_line); } else { - CLEAR_BIT(EXTI->FTSR1, exti_line); + LL_EXTI_DisableFallingTrig_0_31(exti_line); } /* Clear COMP EXTI pending bit (if any) */ - WRITE_REG(EXTI->PR1, exti_line); + LL_EXTI_ClearFlag_0_31(exti_line); /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET) { - SET_BIT(EXTI->EMR1, exti_line); + LL_EXTI_EnableEvent_0_31(exti_line); } else { - CLEAR_BIT(EXTI->EMR1, exti_line); + LL_EXTI_DisableEvent_0_31(exti_line); } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET) { - SET_BIT(EXTI->IMR1, exti_line); + LL_EXTI_EnableIT_0_31(exti_line); } else { - CLEAR_BIT(EXTI->IMR1, exti_line); + LL_EXTI_DisableIT_0_31(exti_line); } } else { /* Disable EXTI event mode */ - CLEAR_BIT(EXTI->EMR1, exti_line); + LL_EXTI_DisableEvent_0_31(exti_line); /* Disable EXTI interrupt mode */ - CLEAR_BIT(EXTI->IMR1, exti_line); + LL_EXTI_DisableIT_0_31(exti_line); } /* Set HAL COMP handle state */ @@ -414,7 +413,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); /* Set COMP_CSR register to reset value */ - WRITE_REG(hcomp->Instance->CSR, 0x00000000); + WRITE_REG(hcomp->Instance->CSR, 0x00000000U); /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ HAL_COMP_MspDeInit(hcomp); @@ -485,7 +484,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ @@ -510,8 +509,8 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) + wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000U * 2U))); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -573,7 +572,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); /* Check COMP EXTI flag */ - if(READ_BIT(EXTI->PR1, exti_line) != RESET) + if(LL_EXTI_IsActiveFlag_0_31(exti_line) != RESET) { /* Check whether comparator is in independent or window mode */ if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != RESET) @@ -585,12 +584,12 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) /* (low or high ) to the other "out of window" area (high or low).*/ /* Both flags must be cleared to call comparator trigger */ /* callback is called once. */ - WRITE_REG(EXTI->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); + LL_EXTI_ClearFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); } else { /* Clear COMP EXTI line pending bit */ - WRITE_REG(EXTI->PR1, exti_line); + LL_EXTI_ClearFlag_0_31(exti_line); } /* COMP trigger user callback */ @@ -666,8 +665,8 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * voltage than the input minus * @param hcomp COMP handle * @retval Returns the selected comparator output level: - * @arg @ref COMP_OUTPUT_LEVEL_LOW - * @arg @ref COMP_OUTPUT_LEVEL_HIGH + * @arg COMP_OUTPUT_LEVEL_LOW + * @arg COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) @@ -741,7 +740,6 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @} */ -#endif /* HAL_COMP_MODULE_ENABLED */ /** * @} */ @@ -750,4 +748,8 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @} */ +#endif /* COMP1 || COMP2 */ + +#endif /* HAL_COMP_MODULE_ENABLED */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h index 2787ba4572..142639e679 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_comp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention @@ -43,8 +41,11 @@ extern "C" { #endif +#if defined (COMP1) || defined (COMP2) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#include "stm32l4xx_ll_exti.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -98,14 +99,14 @@ typedef struct /** * @brief HAL COMP state machine: HAL COMP states definition */ -#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10) +#define COMP_STATE_BITFIELD_LOCK (0x10U) typedef enum { - HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized */ + HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */ HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */ - HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */ HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ - HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ + HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ }HAL_COMP_StateTypeDef; @@ -132,9 +133,8 @@ typedef struct /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ +#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ #define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ - /** * @} */ @@ -145,7 +145,7 @@ typedef struct /* Note: For the characteritics of comparator power modes */ /* (propagation delay and power consumption), */ /* refer to device datasheet. */ -#define COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< High Speed */ #define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ #define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE) /*!< Ultra-low power mode */ /** @@ -155,7 +155,7 @@ typedef struct /** @defgroup COMP_InputPlus COMP input plus (non-inverting input) * @{ */ -#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -175,7 +175,7 @@ typedef struct #if defined(DAC_CHANNEL2_SUPPORT) #define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ #endif -#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ +#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ #define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ #if defined(COMP_CSR_INMESEL_1) #define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */ @@ -189,10 +189,10 @@ typedef struct /** @defgroup COMP_Hysteresis COMP hysteresis * @{ */ -#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */ -#define COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0) /*!< Hysteresis level low */ -#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1) /*!< Hysteresis level medium */ -#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST) /*!< Hysteresis level high */ +#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ +#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ +#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ +#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ /** * @} */ @@ -200,7 +200,7 @@ typedef struct /** @defgroup COMP_OutputPolarity COMP output Polarity * @{ */ -#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ #define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ /** * @} @@ -209,35 +209,13 @@ typedef struct /** @defgroup COMP_BlankingSrce COMP blanking source * @{ */ -/* Note: Some blanking sources are not available depending on timer */ -/* availability or devices specificities */ -/* (STM32L43xx, STM32L44xx, STM32L45xx, STM32L46xx) */ -#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */ -/* Blanking sources for COMP instance: COMP1 */ -#define COMP_BLANKINGSRC_TIM1_OC5_COMP1 (COMP_CSR_BLANKING_0) /*!< Blanking source for COMP1: TIM1 OC5 selected as blanking source for comparator */ -#define COMP_BLANKINGSRC_TIM2_OC3_COMP1 (COMP_CSR_BLANKING_1) /*!< Blanking source for COMP1: TIM2 OC3 selected as blanking source for comparator */ -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) -#define COMP_BLANKINGSRC_TIM3_OC3_COMP1 (COMP_CSR_BLANKING_2) /*!< Blanking source for COMP1: TIM3 OC3 selected as blanking source for comparator */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - -/* Blanking sources for COMP instance: COMP2 */ -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) -#define COMP_BLANKINGSRC_TIM3_OC4_COMP2 (COMP_CSR_BLANKING_0) /*!< Blanking source for COMP2: TIM3 OC4 selected as blanking source for comparator */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) -#define COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_1) /*!< Blanking source for COMP2: TIM8 OC5 selected as blanking source for comparator */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ -#define COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2) /*!< Blanking source for COMP2: TIM15 OC1 selected as blanking source for comparator */ +#define COMP_BLANKINGSRC_NONE (0x00000000U) /*!RTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line rising edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** @@ -370,135 +348,135 @@ typedef struct * @retval None */ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** * @brief Enable the COMP1 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Generate a software interrupt on the COMP1 EXTI line. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP1 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Disable the COMP1 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Check whether the COMP1 EXTI line flag is set. * @retval RESET or SET */ -#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Clear the COMP1 EXTI flag. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1) /** * @brief Enable the COMP2 EXTI line rising edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line rising edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line falling edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line falling edge trigger. * @retval None - */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2) + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None - */ + */ #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Enable the COMP2 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line in interrupt mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Generate a software interrupt on the COMP2 EXTI line. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP2 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP2 EXTI line in event mode. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Check whether the COMP2 EXTI line flag is set. * @retval RESET or SET */ -#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2) /** * @brief Clear the COMP2 EXTI flag. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, COMP_EXTI_LINE_COMP2) +#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2) /** * @} @@ -514,11 +492,12 @@ typedef struct /** @defgroup COMP_Private_Constants COMP Private Constants * @{ */ + /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ -#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM21) /*!< EXTI line 21 connected to COMP1 output */ -#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM22) /*!< EXTI line 22 connected to COMP2 output */ +#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output */ +#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output */ /** * @} */ @@ -526,10 +505,10 @@ typedef struct /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ -#define COMP_EXTI_IT ((uint32_t) 0x01) /*!< EXTI line event with interruption */ -#define COMP_EXTI_EVENT ((uint32_t) 0x02) /*!< EXTI line event only (without interruption) */ -#define COMP_EXTI_RISING ((uint32_t) 0x10) /*!< EXTI line event on rising edge */ -#define COMP_EXTI_FALLING ((uint32_t) 0x20) /*!< EXTI line event on falling edge */ +#define COMP_EXTI_IT (0x01U) /*!< EXTI line event with interruption */ +#define COMP_EXTI_EVENT (0x02U) /*!< EXTI line event only (without interruption) */ +#define COMP_EXTI_RISING (0x10U) /*!< EXTI line event on rising edge */ +#define COMP_EXTI_FALLING (0x20U) /*!< EXTI line event on falling edge */ /** * @} */ @@ -551,8 +530,8 @@ typedef struct * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ -#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? \ - COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + : COMP_EXTI_LINE_COMP2) /** * @} */ @@ -576,7 +555,7 @@ typedef struct ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)) #endif -/* Note: On this STM32 family, comparator input minus parameters are */ +/* Note: On this STM32 serie, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ @@ -630,74 +609,29 @@ typedef struct #define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \ ((__POL__) == COMP_OUTPUTPOL_INVERTED)) -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) +#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ + ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ + ) -#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)) +#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) -#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) - -#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)) - -#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) - -#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ - ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)) - -#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __BLANKINGSRCE__) \ - ((((__INSTANCE__) == COMP1) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ - (((__BLANKINGSRCE__) == COMP_BLANKINGSRC_NONE) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) || \ - ((__BLANKINGSRCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)))) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ @@ -785,6 +719,8 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); } #endif +#endif /* COMP1 || COMP2 */ + #endif /* __STM32L4xx_HAL_COMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h index d0a45d7df2..cb4789fe3c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32l4xx_hal_conf.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 - * @brief HAL configuration file. + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l4xx_hal_conf.h. ****************************************************************************** * @attention * @@ -53,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ #define HAL_COMP_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -62,8 +63,10 @@ #define HAL_DFSDM_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_DMA2D_MODULE_ENABLED +#define HAL_DSI_MODULE_ENABLED #define HAL_FIREWALL_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED +#define HAL_GFXMMU_MODULE_ENABLED #define HAL_HASH_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED #define HAL_NAND_MODULE_ENABLED @@ -75,7 +78,9 @@ #define HAL_IWDG_MODULE_ENABLED #define HAL_LCD_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED #define HAL_OPAMP_MODULE_ENABLED +#define HAL_OSPI_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_QSPI_MODULE_ENABLED @@ -239,6 +244,10 @@ #include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ @@ -263,6 +272,10 @@ #include "stm32l4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ @@ -303,10 +316,18 @@ #include "stm32l4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ @@ -379,6 +400,10 @@ #include "stm32l4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /* ALL MBED targets use same stm32_assert.h */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c index c39d7c6d14..99afff61e4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cortex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -337,6 +335,9 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPre */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } @@ -352,6 +353,9 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } @@ -365,6 +369,9 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } @@ -426,6 +433,46 @@ __weak void HAL_SYSTICK_Callback(void) } #if (__MPU_PRESENT == 1) +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} + /** * @brief Initialize and configure the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h index 037c29e472..f3eea8a70c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cortex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention @@ -289,40 +287,6 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -#if (__MPU_PRESENT == 1) -/** - * @brief Disable the MPU. - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Disable(void) -{ - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** - * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -} -#endif /* __MPU_PRESENT */ /** * @} */ @@ -343,6 +307,8 @@ void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c index 5e1d25a24a..ffa5acb034 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.c @@ -2,15 +2,13 @@ ****************************************************************************** * @file stm32l4xx_hal_crc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 - * @brief CRC HAL module driver. - * This file provides firmware functions to manage the following + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the CRC peripheral: * + Initialization and de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim =============================================================================== ##### How to use this driver ##### @@ -22,11 +20,11 @@ (++) specify initialization value (IP default or non-default one) (++) specify input data format (++) specify input or output data inversion mode if any - (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the - input data buffer starting with the previously computed CRC as + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as initialization value - (+) Use HAL_CRC_Calculate() function to compute the CRC value of the - input data buffer starting with the defined initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value (default or non-default) to initiate CRC calculation @endverbatim @@ -94,20 +92,20 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 * @{ */ -/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the CRC according to the specified parameters + (+) Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle (+) DeInitialize the CRC peripheral (+) Initialize the CRC MSP (MCU Specific Package) (+) DeInitialize the CRC MSP - + @endverbatim * @{ */ @@ -125,28 +123,28 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if(hcrc->State == HAL_CRC_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } - - hcrc->State = HAL_CRC_STATE_BUSY; - - /* check whether or not non-default generating polynomial has been + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been * picked up by user */ - assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) { /* initialize IP with default generating polynomial */ - WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); } else @@ -157,67 +155,67 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) return HAL_ERROR; } } - - /* check whether or not non-default CRC initial value has been + + /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) { - WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); } - + /* set input data inversion mode */ - assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); - + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + /* set output data inversion mode */ - assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); - + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CRC peripheral. + * @brief DeInitialize the CRC peripheral. * @param hcrc: CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) -{ +{ /* Check the CRC handle allocation */ if(hcrc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - + /* Check the CRC peripheral state */ if(hcrc->State == HAL_CRC_STATE_BUSY) { return HAL_BUSY; } - + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - + /* Reset CRC calculation unit */ __HAL_CRC_DR_RESET(hcrc); - + /* Reset IDR register content */ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; @@ -268,19 +266,19 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * @} */ -/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer using the combination of the previous CRC value and the new one - + [..] or - + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer independently of the previous CRC value. @@ -288,35 +286,35 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * @{ */ -/** +/** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. + * provided by hcrc->InputDataFormat. * @param BufferLength: input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; /* CRC input data buffer index */ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - + /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - + switch (hcrc->InputDataFormat) { - case CRC_INPUTDATA_FORMAT_WORDS: + case CRC_INPUTDATA_FORMAT_WORDS: /* Enter Data to the CRC calculator */ for(index = 0; index < BufferLength; index++) { @@ -324,63 +322,63 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ } temp = hcrc->Instance->DR; break; - - case CRC_INPUTDATA_FORMAT_BYTES: + + case CRC_INPUTDATA_FORMAT_BYTES: temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: + + case CRC_INPUTDATA_FORMAT_HALFWORDS: temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + /* Process unlocked */ __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return temp; } -/** +/** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. + * provided by hcrc->InputDataFormat. * @param BufferLength: input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ + */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; /* CRC input data buffer index */ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - + /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); - + switch (hcrc->InputDataFormat) { - case CRC_INPUTDATA_FORMAT_WORDS: + case CRC_INPUTDATA_FORMAT_WORDS: /* Enter 32-bit input data to the CRC calculator */ for(index = 0; index < BufferLength; index++) { @@ -388,28 +386,28 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t } temp = hcrc->Instance->DR; break; - - case CRC_INPUTDATA_FORMAT_BYTES: + + case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: + + case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + /* Process unlocked */ __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return temp; } @@ -418,12 +416,12 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. + * @brief Peripheral State functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -454,9 +452,9 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) * @{ */ -/** +/** * @brief Enter 8-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. + * Specific data handling to optimize processing time. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer * @param BufferLength: input data buffer length @@ -465,63 +463,72 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { uint32_t i = 0; /* input data buffer index */ - + uint16_t data; + __IO uint16_t *pReg; + /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the IP */ for(i = 0; i < (BufferLength/4); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; + hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; } /* last bytes specific handling */ if ((BufferLength%4) != 0) { if (BufferLength%4 == 1) { - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i]; } if (BufferLength%4 == 2) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; + data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; } if (BufferLength%4 == 3) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i+2]; } } - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return hcrc->Instance->DR; } -/** +/** * @brief Enter 16-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. + * Specific data handling to optimize processing time. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer * @param BufferLength: input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ + */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { uint32_t i = 0; /* input data buffer index */ - + __IO uint16_t *pReg; + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, - * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ for(i = 0; i < (BufferLength/2); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; } if ((BufferLength%2) != 0) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = pBuffer[2*i]; } - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return hcrc->Instance->DR; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h index 6bbae9f187..035242c9dc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_crc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -156,7 +154,7 @@ typedef struct /** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial * @{ */ -#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ +#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ /** * @} */ @@ -164,7 +162,7 @@ typedef struct /** @defgroup CRC_Default_InitValue Default CRC computation initialization value * @{ */ -#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF /*!< Initial CRC default value */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */ /** * @} */ @@ -172,8 +170,8 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) /*!< Enable default generating polynomial 0x04C11DB7 */ -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) /*!< Disable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ /** * @} */ @@ -181,8 +179,8 @@ typedef struct /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ */ -#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) /*!< Enable initial CRC default value */ -#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) /*!< Disable initial CRC default value */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ /** * @} */ @@ -190,10 +188,10 @@ typedef struct /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP * @{ */ -#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) /*!< Resort to a 32-bit long generating polynomial */ -#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ -#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ -#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ +#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B (CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B (CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ /** * @} */ @@ -201,10 +199,10 @@ typedef struct /** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions * @{ */ -#define HAL_CRC_LENGTH_32B 32 /*!< 32-bit long CRC */ -#define HAL_CRC_LENGTH_16B 16 /*!< 16-bit long CRC */ -#define HAL_CRC_LENGTH_8B 8 /*!< 8-bit long CRC */ -#define HAL_CRC_LENGTH_7B 7 /*!< 7-bit long CRC */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ /** * @} */ @@ -216,10 +214,10 @@ typedef struct * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) /*!< Undefined input data format */ -#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) /*!< Input data in byte format */ -#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) /*!< Input data in half-word format */ -#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) /*!< Input data in word format */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ /** * @} */ @@ -265,17 +263,19 @@ typedef struct #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** - * @brief Store a 8-bit data in the Independent Data(ID) register. + * @brief Store data in the Independent Data (ID) register. * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __VALUE__: Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits * @retval None */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) /** - * @brief Return the 8-bit data stored in the Independent Data(ID) register. + * @brief Return the data stored in the Independent Data (ID) register. * @param __HANDLE__: CRC handle - * @retval 8-bit value of the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c index e1ce5df19e..cc30ffe074 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the CRC peripheral. @@ -144,7 +142,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* no polynomial definition vs. polynomial length issue possible */ break; default: - break; + return HAL_ERROR; } /* set generating polynomial */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h index 7f6907df65..4e20acf7f8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_crc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRC HAL extended module. ****************************************************************************** * @attention @@ -63,10 +61,10 @@ /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes * @{ */ -#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) /*!< No input data inversion */ -#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE (CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD (CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD (CRC_CR_REV_IN) /*!< Word-wise input data inversion */ /** * @} */ @@ -74,8 +72,8 @@ /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) /*!< No output data inversion */ -#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE (CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c index 833873cbdc..0be7c96a57 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -92,7 +90,7 @@ #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -1450,7 +1448,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* HAL_CRYP_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h index 315f76c8bb..dcb2f5d66a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -457,7 +455,7 @@ typedef struct /** - * @brief Enable the CRYP interrupt. + * @brief Enable the CRYP interrupt. * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. * This parameter can be one of the following values: @@ -687,7 +685,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c index 11340c0826..586dd48ed2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CRYPEx HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the Cryptography (CRYP) peripheral. @@ -43,7 +41,7 @@ #ifdef HAL_CRYP_MODULE_ENABLED -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -484,7 +482,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { - if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0)) + if (((pInputData == NULL) && (Size != 0)) || \ + ((pInputData != NULL) && (Size == 0)) || \ + ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL))) { return HAL_ERROR; } @@ -950,7 +950,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ + {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; if (hcryp->State == HAL_CRYP_STATE_READY) @@ -1141,7 +1145,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -1230,7 +1234,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /* If required, manage input data size not multiple of 32 bits */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Wrap-up in padding with zero-words if applicable */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -1404,15 +1408,22 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI } #if defined(AES_CR_NPBLB) if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM) + { + /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */ + if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0))) + { + return HAL_ERROR; + } + } #else - if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) -#endif + if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) { if ((pInputData == NULL) || (Size == 0)) { return HAL_ERROR; } - } + } +#endif } else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE) { @@ -2186,7 +2197,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) uint32_t addhoc_process = 0; uint32_t difflength = 0; uint32_t difflengthmod4 = 0; - uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ + {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; uint32_t intermediate_data[4] = {0}; if(hcryp->State == HAL_CRYP_STATE_BUSY) @@ -2249,7 +2264,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - /* Mark that the header phase is over */ + /* Mark that the header phase is suspended */ hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; /* Process Unlocked */ @@ -2318,7 +2333,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -2372,7 +2387,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) applied to the last block of payload */ if (difflengthmod4 != 0) { - intermediate_data[difflength/4] &= mask[difflengthmod4-1]; + intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; } @@ -2484,8 +2499,8 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_SUSPENDED; - /* Mark that the header phase is over */ - hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED; + /* Mark that the payload phase is suspended */ + hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_SUSPENDED; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -2539,7 +2554,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) /* If required, manage input data size not multiple of 32 bits */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Wrap-up in padding with zero-words if applicable */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -2964,7 +2979,12 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ uint32_t difflengthmod4 = difflength%4; uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF}; + uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */ + {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */ + {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */ + uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos; + uint32_t intermediate_data[4] = {0}; #if defined(AES_CR_NPBLB) @@ -3004,7 +3024,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ (case of header length not a multiple of 32-bits) */ if (difflengthmod4 != 0) { - hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]); + hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]); } /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */ for(index=0; index < (4 - ((difflength+3)/4)); index ++) @@ -3047,7 +3067,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ applied to the last block of payload */ if (difflengthmod4 != 0) { - intermediate_data[difflength/4] &= mask[difflengthmod4-1]; + intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1]; *(uint32_t*)(outputaddr) = intermediate_data[difflength/4]; } @@ -3109,7 +3129,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* HAL_CRYP_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h index d82497ae06..19f83a6519 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cryp_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRYPEx HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) +#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ @@ -137,7 +135,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) */ +#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c index fe5e15f5ef..e9b7187443 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -26,6 +24,7 @@ 1 channel : STM32L451xx STM32L452xx STM32L462xx 2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx + STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx When 2 channels are available, the 2 converters (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode): @@ -474,6 +473,28 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + if(Channel == DAC_CHANNEL_1) + { + /* Check if software trigger enabled */ + if(((DAC_CR_TEN1 & ~(DAC_CR_TSEL1)) == (hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)))) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + } + else + { + /* Check if software trigger enabled */ + if(((DAC_CR_TEN2 & ~(DAC_CR_TSEL2)) == (hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)))) + { + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); + } + } + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) if(Channel == DAC_CHANNEL_1) @@ -622,7 +643,8 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u #endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** * @brief Enables DAC and starts conversion of channel. @@ -751,6 +773,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @brief Disables DAC and stop conversion of channel. @@ -777,7 +800,8 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Disable the DMA channel */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { @@ -797,8 +821,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); @@ -858,7 +883,8 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) } } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { /* Check underrun flag of DAC channel 1 */ @@ -882,6 +908,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ } /** @@ -1025,12 +1052,13 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) assert_param(IS_DAC_CHANNEL(Channel)); /* Returns the DAC channel data output register value */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) return hdac->Instance->DOR1; #endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(Channel == DAC_CHANNEL_1) { return hdac->Instance->DOR1; @@ -1041,6 +1069,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ } /** @@ -1058,9 +1087,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf { uint32_t tmpreg1 = 0, tmpreg2 = 0; uint32_t tickstart = 0; +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hclkfreq = 0; +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ - /* Check the DAC parameters */ - + /* Check the DAC parameters */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); @@ -1181,6 +1215,34 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf tmpreg2 = (sConfig->DAC_Trigger); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + if(DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ == sConfig->DAC_HighFrequency) + { + tmpreg1 |= DAC_CR_HFSEL; + } + else + { + if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE == sConfig->DAC_HighFrequency) + { + tmpreg1 &= ~(DAC_CR_HFSEL); + } + else /* Automatic selection */ + { + hclkfreq = HAL_RCC_GetHCLKFreq(); + if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) + { + /* High frequency enable when HCLK frequency higher than 80 */ + tmpreg1 |= DAC_CR_HFSEL; + } + else + { + /* High frequency disable when HCLK frequency higher than 80 */ + tmpreg1 &= ~(DAC_CR_HFSEL); + } + } + } + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h index 8ea78f220b..f19d72be8e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac.h @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32l4xx_hal_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -117,6 +115,11 @@ DAC_SampleAndHoldConfTypeDef; */ typedef struct { +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode + This parameter can be a value of @ref DAC_HighFrequency */ +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. This parameter can be a value of @ref DAC_SampleAndHold */ @@ -176,15 +179,15 @@ typedef struct #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) + +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ -#endif /* STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) #define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register @@ -200,7 +203,25 @@ typedef struct #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T1_TRGO ((uint32_t) (DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO ((uint32_t) (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ((uint32_t) (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM2_OUT ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t) (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t) (DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + + /** * @} */ @@ -220,10 +241,12 @@ typedef struct */ #define DAC_CHANNEL_1 ((uint32_t)0x00000000) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define DAC_CHANNEL_2 ((uint32_t)0x00000010) #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} @@ -290,6 +313,18 @@ typedef struct /** * @} */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup DAC_HighFrequency DAC high frequency interface mode + * @{ + */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE ((uint32_t)0x00000000) /*!< High frequency interface mode disabled */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ ((uint32_t)DAC_CR_HFSEL) /*!< High frequency interface mode enabled */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC ((uint32_t)0x00000002) /*!< High frequency interface mode automatic */ + +/** + * @} + */ +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} @@ -404,13 +439,15 @@ typedef struct ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) #endif /* STM32L451xx STM32L452xx STM32L462xx */ @@ -420,7 +457,7 @@ typedef struct #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x0000000FF) +#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c index 49abcae0bf..d139620350 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. @@ -199,7 +197,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** * @brief Set the specified data holding register value for dual DAC channel. @@ -310,6 +309,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @brief Run the self calibration of one DAC channel. @@ -363,7 +363,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC tmp = (uint32_t)hdac->Instance; #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) if(Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); @@ -374,6 +375,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelC } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); #endif /* STM32L451xx STM32L452xx STM32L462xx */ @@ -524,7 +526,8 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel) */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions @@ -563,15 +566,17 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) * @} */ -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions @@ -630,6 +635,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #endif /* HAL_DAC_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h index 4b0cbb12c8..f9c82155ee 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dac_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DAC HAL Extended module. ****************************************************************************** * @attention @@ -139,9 +137,30 @@ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ -#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) -#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x0000003FF) +#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ + ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ + ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC)) + +#endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ + +#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FF) + +#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FF) #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) @@ -204,18 +223,22 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue); @@ -230,10 +253,12 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe /* Peripheral Control functions ***********************************************/ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel); @@ -246,7 +271,8 @@ uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel); */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup DACEx_Private_Functions * @{ @@ -263,6 +289,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c index f62ffe45d4..caa181294f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dcmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -51,12 +49,10 @@ be large enough to ensure the capture of a frame. (#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535), - (++) resort to a user-defined work buffer and associate it to the DCMI handle with - the function HAL_DCMIEx_WorkBuffer_Associate(), (++) the DMA must be configured in circular mode, either for snapshot or continuous capture mode, (++) during capture, the driver copies the image data samples from DCMI DR register - to the work buffer, + at the end of the final destination buffer used as a work buffer, (++) at each DMA half (respectively complete) transfer interrupt, the first (resp. second) half of the work buffer is copied to the final destination thru a second DMA channel. @@ -134,7 +130,8 @@ #ifdef HAL_DCMI_MODULE_ENABLED -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -417,9 +414,8 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) * @param pData: The destination memory buffer address. * @param Length: The length of capture to be transferred (in 32-bit words). * @note In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length), - * user must beforehand associate a work buffer to the DCMI handle thru the API - * HAL_DCMIEx_WorkBuffer_Associate(). Then, HAL_DCMI_Start_DMA() - * initiates a circular DMA transfer from DCMI DR to the work buffer and each + * the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA() + * initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each * half and complete transfer interrupt triggers a copy from the work buffer to * the final destination pData thru a second DMA channel. * @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end, @@ -1264,7 +1260,8 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize) * @} */ -#endif /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* HAL_DCMI_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h index 7243fc837a..278566e144 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dcmi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dcmi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -43,7 +41,9 @@ extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -645,7 +645,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); * @} */ -#endif /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h index 9dde4bccd2..28d8e4f906 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_def.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -147,7 +145,7 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) } while (__STREXW(newValue, ptr)); } -#if defined ( __GNUC__ ) && !defined ( __CC_ARM ) +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -158,7 +156,7 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c index 8cd6cc6534..3de4618edc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals: @@ -198,7 +196,9 @@ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /** @defgroup DFSDM DFSDM * @brief DFSDM HAL driver module * @{ @@ -209,30 +209,10 @@ /** @defgroup DFSDM_Private_Define DFSDM Private Define * @{ */ -#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV) -#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD) -#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR) -#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET) -#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS) -#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR) #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8 -#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH) -#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH) -#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF) -#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF) -#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF) -#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF) -#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA) -#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA) -#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT) -#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT) -#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX) -#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN) -#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT) -#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF) -#define DFSDM_MSB_MASK 0xFFFF0000U -#define DFSDM_LSB_MASK 0x0000FFFFU -#define DFSDM_CKAB_TIMEOUT 5000U +#define DFSDM_MSB_MASK 0xFFFF0000U +#define DFSDM_LSB_MASK 0x0000FFFFU +#define DFSDM_CKAB_TIMEOUT 5000U #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) #define DFSDM1_CHANNEL_NUMBER 4U #else /* STM32L451xx || STM32L452xx || STM32L462xx */ @@ -294,7 +274,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DFSDM channel according to the specified parameters * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -345,7 +325,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << - DFSDM_CHCFGR1_CLK_DIV_OFFSET); + DFSDM_CHCFGR1_CKOUTDIV_Pos); } /* enable the DFSDM global interface */ @@ -367,12 +347,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET)); + ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | - (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET)); + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; @@ -388,7 +368,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /** * @brief De-initialize the DFSDM channel. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -434,7 +414,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief Initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -449,7 +429,7 @@ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief De-initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -488,7 +468,7 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -515,9 +495,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -540,8 +520,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm /** * @brief This function allows to poll for the clock absence detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -568,7 +548,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs tickstart = HAL_GetTick(); /* Wait clock absence detection */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) == 0) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -582,7 +562,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs } /* Clear clock absence detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Return function status */ return HAL_OK; @@ -591,7 +571,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to stop clock absence detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -615,7 +595,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); } /* Return function status */ return status; @@ -627,7 +607,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -654,9 +634,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -682,7 +662,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /** * @brief Clock absence detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -698,7 +678,7 @@ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief This function allows to stop clock absence detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -722,7 +702,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Disable clock absence detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); @@ -734,10 +714,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to start short circuit detection in polling mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -762,7 +742,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ { /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); /* Start short circuit detection */ @@ -774,8 +754,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ /** * @brief This function allows to poll for the short circuit detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -802,7 +782,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd tickstart = HAL_GetTick(); /* Wait short circuit detection */ - while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0) + while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -816,7 +796,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd } /* Clear short circuit detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Return function status */ return HAL_OK; @@ -825,7 +805,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to stop short circuit detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -849,7 +829,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); } /* Return function status */ return status; @@ -858,10 +838,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /** * @brief This function allows to start short circuit detection in interrupt mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -889,7 +869,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); /* Start short circuit detection */ @@ -901,7 +881,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief Short circuit detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -917,7 +897,7 @@ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_cha /** * @brief This function allows to stop short circuit detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -941,7 +921,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Disable short circuit detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); @@ -952,7 +932,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to get channel analog watchdog value. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -962,8 +942,8 @@ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief This function allows to modify channel offset value. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Offset : DFSDM channel offset. + * @param hdfsdm_channel DFSDM channel handle. + * @param Offset DFSDM channel offset. * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. * @retval HAL status. */ @@ -986,7 +966,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf { /* Modify channel offset */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET); - hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET); + hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos); } /* Return function status */ return status; @@ -1011,7 +991,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf /** * @brief This function allows to get the current DFSDM channel handle state. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1041,7 +1021,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp /** * @brief Initialize the DFSDM filter according to the specified parameters * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1131,7 +1111,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Set filter parameters */ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | - ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) | + ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_Pos) | (hdfsdm_filter->Init.FilterParam.IntOversampling - 1)); /* Store regular and injected triggers and injected scan mode*/ @@ -1151,7 +1131,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief De-initializes the DFSDM filter. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1179,7 +1159,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief Initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1194,7 +1174,7 @@ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief De-initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1228,10 +1208,10 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief This function allows to select channel and to enable/disable * continuous mode for regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channel for regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channel for regular conversion. * This parameter can be a value of @ref DFSDM_Channel_Selection. - * @param ContinuousMode : Enable/disable continuous mode for regular conversion. + * @param ContinuousMode Enable/disable continuous mode for regular conversion. * This parameter can be a value of @ref DFSDM_ContinuousMode. * @retval HAL status */ @@ -1275,8 +1255,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to select channels for injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels for injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels for injected conversion. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -1347,7 +1327,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h * @brief This function allows to start regular conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1375,8 +1355,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsd /** * @brief This function allows to poll for the end of regular conversion. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1437,7 +1417,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop regular conversion in polling mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1467,7 +1447,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm * @brief This function allows to start regular conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1498,7 +1478,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to stop regular conversion in interrupt mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1534,9 +1514,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf * Please note that data on buffer will contain signed regular conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1611,9 +1591,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1684,7 +1664,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef /** * @brief This function allows to stop regular conversion in DMA mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1722,8 +1702,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to get regular conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1741,7 +1721,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /* Extract channel and regular conversion value */ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); - value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); /* return regular conversion value */ return value; @@ -1751,7 +1731,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte * @brief This function allows to start injected conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1779,8 +1759,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to poll for the end of injected conversion. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1851,7 +1831,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in polling mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1881,7 +1861,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd * @brief This function allows to start injected conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1912,7 +1892,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to stop injected conversion in interrupt mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1948,9 +1928,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd * Please note that data on buffer will contain signed injected conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2023,9 +2003,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2094,7 +2074,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in DMA mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2132,8 +2112,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to get injected conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2151,7 +2131,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /* Extract channel and injected conversion value */ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); - value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); /* return regular conversion value */ return value; @@ -2159,8 +2139,8 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief This function allows to start filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. - * @param awdParam : DFSDM filter analog watchdog parameters. + * @param hdfsdm_filter DFSDM filter handle. + * @param awdParam DFSDM filter analog watchdog parameters. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2192,15 +2172,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /* Set thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); - hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \ + hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \ awdParam->HighBreakSignal); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); - hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \ + hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \ awdParam->LowBreakSignal); /* Set channels and interrupt for analog watchdog */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); - hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \ + hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \ DFSDM_FLTCR2_AWDIE); } /* Return function status */ @@ -2209,7 +2189,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to stop filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2247,8 +2227,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /** * @brief This function allows to start extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels where extreme detector is enabled. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels where extreme detector is enabled. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -2272,7 +2252,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi { /* Set channels for extreme detector */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET); + hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); } /* Return function status */ return status; @@ -2280,7 +2260,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi /** * @brief This function allows to stop extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2316,8 +2296,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get extreme detector maximum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2336,7 +2316,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Extract channel and extreme detector maximum value */ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); - value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); /* return extreme detector maximum value */ return value; @@ -2344,8 +2324,8 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get extreme detector minimum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2364,7 +2344,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Extract channel and extreme detector minimum value */ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); - value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); /* return extreme detector minimum value */ return value; @@ -2372,7 +2352,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get conversion time value. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ @@ -2388,7 +2368,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil reg = hdfsdm_filter->Instance->FLTCNVTIMR; /* Extract conversion time value */ - value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET); + value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); /* return extreme detector minimum value */ return value; @@ -2396,7 +2376,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function handles the DFSDM interrupts. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2485,7 +2465,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; if(threshold == DFSDM_AWD_HIGH_THRESHOLD) { - reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET; + reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos; } while((reg & 1) == 0) { @@ -2494,7 +2474,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* Clear analog watchdog flag */ hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ - (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \ + (1 << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ (1 << channel); /* Call analog watchdog callback */ @@ -2508,7 +2488,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t reg = 0; uint32_t channel = 0; - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); while(channel < DFSDM1_CHANNEL_NUMBER) { @@ -2519,7 +2499,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0) { /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Call clock absence callback */ HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); @@ -2538,7 +2518,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t channel = 0; /* Get channel */ - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); while((reg & 1) == 0) { channel++; @@ -2546,7 +2526,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Call short circuit detection callback */ HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); @@ -2557,7 +2537,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) * @brief Regular conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetRegularValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2572,7 +2552,7 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half regular conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2589,7 +2569,7 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * * @brief Injected conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetInjectedValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2604,7 +2584,7 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half injected conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2619,9 +2599,9 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * /** * @brief Filter analog watchdog callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. - * @param Threshold : Low or high threshold has been reached. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. + * @param Threshold Low or high threshold has been reached. * @retval None */ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2639,7 +2619,7 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /** * @brief Error callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2672,7 +2652,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get the current DFSDM filter handle state. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2683,7 +2663,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to get the current DFSDM filter error. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2707,7 +2687,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief DMA half transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2721,7 +2701,7 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) @@ -2735,7 +2715,7 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2749,7 +2729,7 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) @@ -2763,7 +2743,7 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) @@ -2780,7 +2760,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function allows to get the number of injected channels. - * @param Channels : bitfield of injected channels. + * @param Channels bitfield of injected channels. * @retval Number of injected channels. */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) @@ -2803,7 +2783,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) /** * @brief This function allows to get the channel number from channel instance. - * @param Instance : DFSDM channel instance. + * @param Instance DFSDM channel instance. * @retval Channel number. */ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) @@ -2828,7 +2808,8 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) channel = 3; } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) else if(Instance == DFSDM1_Channel4) { channel = 4; @@ -2845,14 +2826,14 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) { channel = 7; } -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return channel; } /** * @brief This function allows to really start regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2893,7 +2874,7 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2929,7 +2910,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really start injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2973,7 +2954,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -3019,7 +3000,9 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @} */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ + +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* HAL_DFSDM_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h index 7af5ae4675..17de1fc91e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention @@ -45,7 +43,9 @@ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -91,7 +91,8 @@ typedef struct { uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, - STM32L496xx, STM32L4A6xx products. + STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx, + STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products. This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. This parameter can be a value of @ref DFSDM_Channel_DataPacking */ @@ -271,9 +272,10 @@ typedef struct */ #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ /** * @} @@ -352,6 +354,22 @@ typedef struct #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ +#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ + DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ + DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ +#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ + DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ #else #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ @@ -440,7 +458,7 @@ typedef struct #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) -#else /* STM32L451xx || STM32L452xx || STM32L462xx */ +#else #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) @@ -483,13 +501,13 @@ typedef struct */ /** @brief Reset DFSDM channel handle state. - * @param __HANDLE__: DFSDM channel handle. + * @param __HANDLE__ DFSDM channel handle. * @retval None */ #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) /** @brief Reset DFSDM filter handle state. - * @param __HANDLE__: DFSDM filter handle. + * @param __HANDLE__ DFSDM filter handle. * @retval None */ #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) @@ -499,6 +517,11 @@ typedef struct */ /* End of exported macros ----------------------------------------------------*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* Include DFSDM HAL Extension module */ +#include "stm32l4xx_hal_dfsdm_ex.h" +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions * @{ @@ -644,14 +667,17 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) #else #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) @@ -686,6 +712,19 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) +#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ + ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) #else #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ @@ -720,7 +759,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe ((CHANNEL) == DFSDM_CHANNEL_2) || \ ((CHANNEL) == DFSDM_CHANNEL_3)) #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU)) -#else /* STM32L451xx || STM32L452xx || STM32L462xx */ +#else #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ ((CHANNEL) == DFSDM_CHANNEL_1) || \ ((CHANNEL) == DFSDM_CHANNEL_2) || \ @@ -745,7 +784,11 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe /** * @} */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c new file mode 100644 index 0000000000..2304f97304 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dfsdm_ex.c + * @author MCD Application Team + * @brief DFSDM Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the DFSDM Peripheral Controller: + * + Set and get pulses skipping on channel. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @defgroup DFSDMEx DFSDMEx + * @brief DFSDM Extended HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions + * @{ + */ + +/** @defgroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions + * @brief DFSDM extended channel operation functions + * +@verbatim + =============================================================================== + ##### Extended channel operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Set and get value of pulses skipping on channel + +@endverbatim + * @{ + */ + +/** + * @brief Set value of pulses skipping. + * @param hdfsdm_channel DFSDM channel handle. + * @param PulsesValue Value of pulses to be skipped. + * This parameter must be a number between Min_Data = 0 and Max_Data = 63. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check pulses value */ + assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue)); + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Set new value of pulses skipping */ + hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP); + } + else + { + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Get value of pulses skipping. + * @param hdfsdm_channel DFSDM channel handle. + * @param PulsesValue Value of pulses to be skipped. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check DFSDM channel state */ + if(hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY) + { + /* Get value of remaining pulses to be skipped */ + *PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP); + } + else + { + status = HAL_ERROR; + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h new file mode 100644 index 0000000000..ec26719449 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dfsdm_ex.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dfsdm_ex.h + * @author MCD Application Team + * @brief Header file of DFSDM HAL extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_DFSDM_EX_H +#define __STM32L4xx_HAL_DFSDM_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DFSDMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions + * @{ + */ + +/** @addtogroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions + * @{ + */ + +HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue); +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t* PulsesValue); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup DFSDMEx_Private_Macros DFSDM Extended Private Macros + * @{ + */ + +#define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE) ((VALUE) < 64U) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_DFSDM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c index 78da7a3a3d..9963ae866e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: @@ -16,7 +14,7 @@ ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is + (except for internal SRAM / FLASH memories: no initialization is necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. @@ -25,15 +23,18 @@ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. - Prior to HAL_DMA_Init the CLK shall be enabled for both DMA thanks to: - __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() + Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX + thanks to: + (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; + (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. - + (#) Use HAL_DMA_Abort() function to abort the current transfer - + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** ================================= [..] @@ -52,13 +53,12 @@ In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e. a member of DMA handle structure). + add his own function to register callbacks with HAL_DMA_RegisterCallback(). *** DMA HAL driver macros list *** - ============================================= + ============================================= [..] - Below the list of most used macros in DMA HAL driver. + Below the list of macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. @@ -66,10 +66,10 @@ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim ****************************************************************************** @@ -125,6 +125,11 @@ * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +#if defined(DMAMUX1) +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); +#endif /* DMAMUX1 */ + /** * @} */ @@ -136,7 +141,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions + * @brief Initialization and de-initialization functions * @verbatim =============================================================================== @@ -144,11 +149,11 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, + and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. + reference manual. @endverbatim * @{ @@ -181,19 +186,16 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) - { - assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); - } - - /* calculation of the channel index */ + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } - else + else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; @@ -206,10 +208,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Get the CR register value */ tmp = hdma->Instance->CCR; - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ - DMA_CCR_DIR)); + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | @@ -220,6 +222,48 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; + +#if defined(DMAMUX1) + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } +#endif /* DMAMUX1 */ + +#if !defined (DMAMUX1) + /* Set request selection */ if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) { @@ -230,18 +274,22 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); /* Configure request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); } else /* DMA2 */ { /* Reset request selection for DMA2 Channelx */ DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); - + /* Configure request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); } } +#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ + /* STM32L496xx || STM32L4A6xx */ + /* Clean callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; @@ -256,7 +304,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; - + return HAL_OK; } @@ -268,52 +316,91 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { + /* Check the DMA handle allocation */ - if(hdma == NULL) + if (NULL == hdma ) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; - - /* Calculation of the channel index */ + /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } - else + else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } - + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0; /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + +#if !defined (DMAMUX1) /* Reset DMA channel selection register */ if (DMA1 == hdma->DmaBaseAddress) { /* DMA1 */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); } - else + else { /* DMA2 */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); + DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); } +#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ + /* STM32L496xx || STM32L4A6xx */ - /* Initialize the error code */ +#if defined(DMAMUX1) + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Reset Request generator parameters if any */ + if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + +#endif /* DMAMUX1 */ + + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ @@ -372,22 +459,22 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - status = HAL_BUSY; - } + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } return status; } @@ -409,19 +496,19 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback ) @@ -434,17 +521,36 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); } + +#ifdef DMAMUX1 + + /* Check if DMAMUX Synchronization is enabled*/ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + +#endif /* DMAMUX1 */ + /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else - { + { /* Process Unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; - } + } return status; } @@ -458,31 +564,49 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; - if(HAL_DMA_STATE_BUSY != hdma->State) + /* Check the DMA peripheral handle */ + if(NULL == hdma) { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; + return HAL_ERROR; } - else + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + +#if defined(DMAMUX1) + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; +#endif /* DMAMUX1 */ + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + +#if defined(DMAMUX1) + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } - return status; + +#endif /* DMAMUX1 */ + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return status; } /** @@ -492,38 +616,60 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - + status = HAL_ERROR; } else - { + { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - + /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - + +#if defined(DMAMUX1) + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + +#else + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); +#endif /* DMAMUX1 */ + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ + + /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); - } + } } return status; } @@ -536,7 +682,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param Timeout: Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart = 0; @@ -545,7 +691,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - + __HAL_UNLOCK(hdma); return HAL_ERROR; } @@ -555,7 +701,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } - + /* Get the level transfer complete flag */ if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { @@ -571,9 +717,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Get tick */ tickstart = HAL_GetTick(); - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + while(RESET == (hdma->DmaBaseAddress->ISR & temp)) { - if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) + if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ @@ -601,7 +747,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); @@ -610,6 +756,35 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp } } +#if defined(DMAMUX1) + /*Check for DMAMUX Request generator (if used) overrun status */ + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } +#endif /* DMAMUX1 */ + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ @@ -624,9 +799,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); } - + /* Process unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); return HAL_OK; } @@ -641,7 +816,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t source_it = hdma->Instance->CCR; - + /* Half Transfer Complete Interrupt management ******************************/ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) { @@ -663,14 +838,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->XferHalfCpltCallback(hdma); } } - + /* Transfer Complete Interrupt management ***********************************/ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) { /* Disable the transfer complete and error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; @@ -723,17 +898,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Channel. * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback: pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) { HAL_StatusTypeDef status = HAL_OK; - + /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) @@ -741,32 +916,32 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = pCallback; break; - + case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = pCallback; - break; + break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = pCallback; - break; - + break; + case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = pCallback; - break; - + break; + default: status = HAL_ERROR; - break; + break; } } else { status = HAL_ERROR; - } - + } + /* Release Lock */ __HAL_UNLOCK(hdma); - + return status; } @@ -777,14 +952,14 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) @@ -792,42 +967,42 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; - + case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; - break; + break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; - break; - + break; + case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; - break; - + break; + case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; - break; - + break; + default: status = HAL_ERROR; - break; + break; } } else { status = HAL_ERROR; - } - + } + /* Release Lock */ __HAL_UNLOCK(hdma); - + return status; } - + /** * @} */ @@ -840,7 +1015,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state @@ -896,9 +1071,20 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { +#if defined(DMAMUX1) + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } +#endif + /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - + /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; @@ -922,6 +1108,57 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t } } +#if defined(DMAMUX1) + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t channel_number = 0; + DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; + + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + { + /* DMA1 */ + DMAMUX1_ChannelBase = DMAMUX1_Channel0; + } + else + { + /* DMA2 */ + DMAMUX1_ChannelBase = DMAMUX1_Channel7; + } + channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)); + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1U << channel_number; +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + + hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U); +} + +#endif /* DMAMUX1 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h index eedd7f6750..c11a47ccae 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -55,7 +53,6 @@ */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ @@ -114,17 +111,17 @@ typedef enum }HAL_DMA_LevelCompleteTypeDef; -/** +/** * @brief HAL DMA Callback ID structure definition */ typedef enum { HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ - + HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ + }HAL_DMA_CallbackIDTypeDef; /** @@ -133,13 +130,13 @@ typedef enum typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ - + DMA_InitTypeDef Init; /*!< DMA communication parameters */ - + HAL_LockTypeDef Lock; /*!< DMA locking object */ - + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - + void *Parent; /*!< Parent object state */ void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ @@ -148,13 +145,29 @@ typedef struct __DMA_HandleTypeDef void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + __IO uint32_t ErrorCode; /*!< DMA Error code */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + +#if defined(DMAMUX1) + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ + +#endif /* DMAMUX1 */ + }DMA_HandleTypeDef; /** * @} @@ -169,11 +182,14 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */ + /** * @} */ @@ -181,6 +197,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_request DMA request * @{ */ +#if !defined (DMAMUX1) + #define DMA_REQUEST_0 ((uint32_t)0x00000000) #define DMA_REQUEST_1 ((uint32_t)0x00000001) #define DMA_REQUEST_2 ((uint32_t)0x00000002) @@ -189,6 +207,131 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_5 ((uint32_t)0x00000005) #define DMA_REQUEST_6 ((uint32_t)0x00000006) #define DMA_REQUEST_7 ((uint32_t)0x00000007) + +#endif + +#if defined(DMAMUX1) + +#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ + +#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ + +#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ + +#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ +#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ + +#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ +#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ + +#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ +#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ +#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ + +#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ +#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ +#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ +#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ + +#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ +#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ +#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ +#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ +#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ +#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ + +#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ +#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ +#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ +#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ + +#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ +#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ + +#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ +#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ +#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ +#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ + +#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ +#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ + +#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ +#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ +#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ + +#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ +#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ +#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ +#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ +#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ +#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ +#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ + +#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ + +#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ +#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ + +#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ +#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ +#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ +#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ +#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ + +#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ +#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ +#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ +#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ +#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ +#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ + +#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ +#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ +#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ + +#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ +#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ + +#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ +#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ +#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ +#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ + +#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ + +#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ +#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ + +#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ + +#endif /* DMAMUX1 */ + /** * @} */ @@ -497,6 +640,11 @@ typedef struct __DMA_HandleTypeDef * @} */ +#if defined(DMAMUX1) +/* Include DMA HAL Extension module */ +#include "stm32l4xx_hal_dma_ex.h" +#endif /* DMAMUX1 */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions @@ -521,7 +669,7 @@ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, u HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); @@ -561,6 +709,8 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ ((STATE) == DMA_MINC_DISABLE)) +#if !defined (DMAMUX1) + #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ ((REQUEST) == DMA_REQUEST_1) || \ ((REQUEST) == DMA_REQUEST_2) || \ @@ -569,6 +719,13 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((REQUEST) == DMA_REQUEST_5) || \ ((REQUEST) == DMA_REQUEST_6) || \ ((REQUEST) == DMA_REQUEST_7)) +#endif + +#if defined(DMAMUX1) + +#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) + +#endif /* DMAMUX1 */ #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ @@ -588,7 +745,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c index 78d3776442..d5088c5e7b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma2d.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: @@ -130,7 +128,8 @@ #ifdef HAL_DMA2D_MODULE_ENABLED -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -243,6 +242,10 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode)); + assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(hdma2d->State == HAL_DMA2D_STATE_RESET) { @@ -256,13 +259,21 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) hdma2d->State = HAL_DMA2D_STATE_BUSY; /* DMA2D CR register configuration -------------------------------------------*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode); +#else MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap); +#else MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* DMA2D OOR register configuration ------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); /* DMA2D OPFCCR RBS and AI fields setting */ MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), \ @@ -585,7 +596,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) /* Abort the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); @@ -634,7 +645,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /* Suspend the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); @@ -689,7 +700,7 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /* Resume the DMA2D transfer */ /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing ‘0’ has no + between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); @@ -1761,7 +1772,8 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ * @} */ -#endif /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* HAL_DMA2D_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h index 90f62da76d..cb389d6659 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma2d.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -43,7 +41,8 @@ extern "C" { #endif -#if defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -112,6 +111,16 @@ typedef struct uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) for the output pixel format converter. This parameter can be one value of @ref DMA2D_RB_Swap. */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). + This parameter can be one value of @ref DMA2D_Bytes_Swap. */ + + uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. + This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + } DMA2D_InitTypeDef; @@ -143,7 +152,6 @@ typedef struct uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). This parameter can be one value of @ref DMA2D_RB_Swap. */ - } DMA2D_LayerCfgTypeDef; /** @@ -204,10 +212,14 @@ typedef struct __DMA2D_HandleTypeDef /** @defgroup DMA2D_Mode DMA2D Mode * @{ */ -#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ -#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ -#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ -#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ +#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ +#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ +#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -271,6 +283,27 @@ typedef struct __DMA2D_HandleTypeDef * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode + * @{ + */ +#define DMA2D_LOM_PIXELS ((uint32_t)0x00000000U) /*!< Line offsets expressed in pixels */ +#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ +/** + * @} + */ + +/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap + * @{ + */ +#define DMA2D_BYTES_REGULAR ((uint32_t)0x00000000U) /*!< Bytes in regular order in output FIFO */ +#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode * @{ */ @@ -280,7 +313,6 @@ typedef struct __DMA2D_HandleTypeDef * @} */ - /** @defgroup DMA2D_Interrupts DMA2D Interrupts * @{ */ @@ -562,8 +594,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); * @{ */ #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ + ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ + ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) +#else #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) @@ -587,6 +627,15 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ ((RB_Swap) == DMA2D_RB_SWAP)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ + ((LOM) == DMA2D_LOM_BYTES)) + +#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ + ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) @@ -609,6 +658,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); */ #endif /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c new file mode 100644 index 0000000000..50b09d5908 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.c @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#if defined(DMAMUX1) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + +@endverbatim + * @{ + */ + + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + /*Check if the DMA state is ready */ + if(hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG( hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID) , \ + ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + pSyncConfig->SyncPolarity | (pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + (pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /*DMA State not Ready*/ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters*/ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ))| \ + pRequestGeneratorConfig->Polarity; + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if(hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h new file mode 100644 index 0000000000..0ce4b2ae20 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dma_ex.h @@ -0,0 +1,298 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_DMA_EX_H +#define __STM32L4xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(DMAMUX1) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @{ + */ + +/** + * @brief HAL DMA Synchro definition + */ + + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE*/ + + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + + +}HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +}HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ + +/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ +#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ +#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ +#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ +#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ +#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ +#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ +#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ +#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ +#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ +#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ +#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ +#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ +#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ +#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */ +#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */ +#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */ +#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection + * @{ + */ + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT 0U /*!< block request generator events */ +#define HAL_DMAMUX_REQUEST_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQUEST_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup DMAEx_Exported_Functions_Group1 + * @{ + */ + +/* ------------------------- REQUEST -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); +/* -------------------------------------------------------------------------- */ + +/* ------------------------- SYNCHRO -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +/* -------------------------------------------------------------------------- */ + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_LTDC_IT) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING)) + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c new file mode 100644 index 0000000000..570bef2b50 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.c @@ -0,0 +1,2379 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dsi.c + * @author MCD Application Team + * @brief DSI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DSI peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DSI_MODULE_ENABLED + +#if defined(DSI) + +/** @addtogroup DSI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup DSI_Private_Constants + * @{ + */ +#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ + +#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ + DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ + DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ + DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) +#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) +#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX +#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX +#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) +#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE +#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE +#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE +#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE +#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Generic DSI packet header configuration + * @param DSIx: Pointer to DSI register base + * @param ChannelID: Virtual channel ID of the header packet + * @param DataType: Packet data type of the header packet + * This parameter can be any value of : + * @ref DSI_SHORT_WRITE_PKT_Data_Type + * or @ref DSI_LONG_WRITE_PKT_Data_Type + * or @ref DSI_SHORT_READ_PKT_Data_Type + * or DSI_MAX_RETURN_PKT_SIZE + * @param Data0: Word count LSB + * @param Data1: Word count MSB + * @retval None + */ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, + uint32_t ChannelID, + uint32_t DataType, + uint32_t Data0, + uint32_t Data1) +{ + /* Update the DSI packet header with new information */ + DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U)); +} + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DSI_Exported_Functions + * @{ + */ + +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DSI + (+) De-initialize the DSI + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DSI according to the specified + * parameters in the DSI_InitTypeDef and create the associated handle. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) +{ + uint32_t tickstart; + uint32_t unitIntervalx4; + uint32_t tempIDF; + + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); + assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); + assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); + assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); + assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); + + if(hdsi->State == HAL_DSI_STATE_RESET) + { + /* Initialize the low level hardware */ + HAL_DSI_MspInit(hdsi); + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /**************** Turn on the regulator and enable the DSI PLL ****************/ + + /* Enable the regulator */ + __HAL_DSI_REG_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the regulator is ready */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the PLL division factors */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U)); + + /* Enable the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /*************************** Set the PHY parameters ***************************/ + + /* D-PHY clock and digital enable*/ + hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + + /* Configure the number of active data lanes */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; + hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; + + /************************ Set the DSI clock parameters ************************/ + + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + + /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ + /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ + /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ + tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; + unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); + + /* Set the bit period in high-speed mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; + hdsi->Instance->WPCR[0U] |= unitIntervalx4; + + /****************************** Error management *****************************/ + + /* Disable all error interrupts and reset the Error Mask */ + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + hdsi->ErrorMsk = 0U; + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initializes the DSI peripheral registers to their default reset + * values. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) +{ + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* D-PHY clock and digital disable */ + hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Disable the regulator */ + __HAL_DSI_REG_DISABLE(hdsi); + + /* DeInit the low level hardware */ + HAL_DSI_MspDeInit(hdsi); + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable the error monitor flags + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ActiveErrors: indicates which error interrupts will be enabled. + * This parameter can be any combination of @ref DSI_Error_Data_Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + + /* Store active errors to the handle */ + hdsi->ErrorMsk = ActiveErrors; + + if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; + } + + if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle DSI interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handles DSI interrupt request. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) +{ + uint32_t ErrorStatus0, ErrorStatus1; + + /* Tearing Effect Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) + { + /* Clear the Tearing Effect Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); + + /* Tearing Effect Callback */ + HAL_DSI_TearingEffectCallback(hdsi); + } + } + + /* End of Refresh Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) + { + /* Clear the End of Refresh Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); + + /* End of Refresh Callback */ + HAL_DSI_EndOfRefreshCallback(hdsi); + } + } + + /* Error Interrupts management ***********************************************/ + if(hdsi->ErrorMsk != 0U) + { + ErrorStatus0 = hdsi->Instance->ISR[0U]; + ErrorStatus0 &= hdsi->Instance->IER[0U]; + ErrorStatus1 = hdsi->Instance->ISR[1U]; + ErrorStatus1 &= hdsi->Instance->IER[1U]; + + if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; + } + + if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; + } + + if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_TX; + } + + if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_RX; + } + + if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; + } + + if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; + } + + if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; + } + + if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; + } + + if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; + } + + if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; + } + + /* Check only selected errors */ + if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) + { + /* DSI error interrupt user callback */ + HAL_DSI_ErrorCallback(hdsi); + } + } +} + +/** + * @brief Tearing Effect DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_TearingEffectCallback could be implemented in the user file + */ +} + +/** + * @brief End of Refresh DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_EndOfRefreshCallback could be implemented in the user file + */ +} + +/** + * @brief Operation Error DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the Generic interface read-back Virtual Channel ID + (+) Select video mode and configure the corresponding parameters + (+) Configure command transmission mode: High-speed or Low-power + (+) Configure the flow control + (+) Configure the DSI PHY timer + (+) Configure the DSI HOST timeout + (+) Configure the DSI HOST timeout + (+) Start/Stop the DSI module + (+) Refresh the display in command mode + (+) Controls the display color mode in Video mode + (+) Control the display shutdown in Video mode + (+) write short DCS or short Generic command + (+) write long DCS or long Generic command + (+) Read command (DCS or generic) + (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) + (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) + (+) Start/Stop test pattern generation + (+) Slew-Rate And Delay Tuning + (+) Low-Power Reception Filter Tuning + (+) Activate an additional current path on all lanes to meet the SDDTx parameter + (+) Custom lane pins configuration + (+) Set custom timing for the PHY + (+) Force the Clock/Data Lane in TX Stop Mode + (+) Force LP Receiver in Low-Power Mode + (+) Force Data Lanes in RX Mode after a BTA + (+) Enable a pull-down on the lanes to prevent from floating states when unused + (+) Switch off the contention detection on data lanes + +@endverbatim + * @{ + */ + +/** + * @brief Configure the Generic interface read-back Virtual Channel ID. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelID: Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCID register */ + hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; + hdsi->Instance->GVCIDR |= VirtualChannelID; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select video mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); + assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); + assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); + assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); + assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); + assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); + assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); + assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); + assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); + assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); + assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); + /* Check the LooselyPacked variant only in 18-bit mode */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); + } + + /* Select video mode by resetting CMDM and DSIM bits */ + hdsi->Instance->MCR &= ~DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + + /* Configure the video mode transmission type */ + hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; + hdsi->Instance->VMCR |= VidCfg->Mode; + + /* Configure the video packet size */ + hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; + hdsi->Instance->VPCR |= VidCfg->PacketSize; + + /* Set the chunks number to be transmitted through the DSI link */ + hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; + hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; + + /* Set the size of the null packet */ + hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; + hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U); + + /* Enable/disable the loosely packed variant to 18-bit configuration */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; + hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; + } + + /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ + hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; + hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; + + /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ + hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; + hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; + + /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ + hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; + hdsi->Instance->VLCR |= VidCfg->HorizontalLine; + + /* Set the Vertical Synchronization Active (VSA) */ + hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; + hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; + + /* Set the Vertical Back Porch (VBP)*/ + hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; + hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; + + /* Set the Vertical Front Porch (VFP)*/ + hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; + hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; + + /* Set the Vertical Active period*/ + hdsi->Instance->VVACR &= ~DSI_VVACR_VA; + hdsi->Instance->VVACR |= VidCfg->VerticalActive; + + /* Configure the command transmission mode */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; + hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; + + /* Low power largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; + hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U); + + /* Low power VACT largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; + hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; + + /* Enable LP transition in HFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; + + /* Enable LP transition in HBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; + + /* Enable LP transition in VACT period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; + + /* Enable LP transition in VFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; + + /* Enable LP transition in VBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; + + /* Enable LP transition in vertical sync period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; + + /* Enable the request for an acknowledge response at the end of a frame */ + hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; + hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select adapted command mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); + assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); + assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); + assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); + assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); + assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); + assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); + + /* Select command mode by setting CMDM and DSIM bits */ + hdsi->Instance->MCR |= DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U); + + /* Configure the maximum allowed size for write memory command */ + hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; + hdsi->Instance->LCCR |= CmdCfg->CommandSize; + + /* Configure the tearing effect source and polarity and select the refresh mode */ + hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); + hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); + + /* Configure the tearing effect acknowledge request */ + hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; + hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; + + /* Enable the Tearing Effect interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); + + /* Enable the End of Refresh interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure command transmission mode: High-speed or Low-power + * and enable/disable acknowledge request after packet transmission + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * the DSI command transmission mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); + assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); + assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); + assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); + assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); + assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); + assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); + assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); + assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); + assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); + assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); + assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); + assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); + + /* Select High-speed or Low-power for command transmission */ + hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ + DSI_CMCR_GSW1TX |\ + DSI_CMCR_GSW2TX |\ + DSI_CMCR_GSR0TX |\ + DSI_CMCR_GSR1TX |\ + DSI_CMCR_GSR2TX |\ + DSI_CMCR_GLWTX |\ + DSI_CMCR_DSW0TX |\ + DSI_CMCR_DSW1TX |\ + DSI_CMCR_DSR0TX |\ + DSI_CMCR_DLWTX |\ + DSI_CMCR_MRDPS); + hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ + LPCmd->LPGenShortWriteOneP |\ + LPCmd->LPGenShortWriteTwoP |\ + LPCmd->LPGenShortReadNoP |\ + LPCmd->LPGenShortReadOneP |\ + LPCmd->LPGenShortReadTwoP |\ + LPCmd->LPGenLongWrite |\ + LPCmd->LPDcsShortWriteNoP |\ + LPCmd->LPDcsShortWriteOneP |\ + LPCmd->LPDcsShortReadNoP |\ + LPCmd->LPDcsLongWrite |\ + LPCmd->LPMaxReadPacket); + + /* Configure the acknowledge request after each packet transmission */ + hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; + hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the flow control parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param FlowControl: flow control feature(s) to be enabled. + * This parameter can be any combination of @ref DSI_FlowControl. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); + + /* Set the DSI Host Protocol Configuration Register */ + hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; + hdsi->Instance->PCR |= FlowControl; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI PHY timer parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * the DSI PHY timing parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) +{ + uint32_t maxTime; + /* Process locked */ + __HAL_LOCK(hdsi); + + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; + + /* Clock lane timer configuration */ + + /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two + High-Speed transmission. + To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed + to Low-Power and from Low-Power to High-Speed. + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. + + Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. + */ + hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); + hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U)); + + /* Data lane timer configuration */ + hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); + hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U)); + + /* Configure the wait period to request HS transmission after a stop state */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; + hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI HOST timeout parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * the DSI host timeout parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Set the timeout clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; + hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U); + + /* High-speed transmission timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; + hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U); + + /* Low-power reception timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; + hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; + + /* High-speed read timeout */ + hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; + hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; + + /* Low-power read timeout */ + hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; + hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; + + /* High-speed write timeout */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; + + /* High-speed write presp mode */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; + + /* Low-speed write timeout */ + hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; + hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; + + /* BTA timeout */ + hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; + hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Enable the DSI host */ + __HAL_DSI_ENABLE(hdsi); + + /* Enable the DSI wrapper */ + __HAL_DSI_WRAPPER_ENABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Refresh the display in command mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the display */ + hdsi->Instance->WCR |= DSI_WCR_LTDCEN; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Controls the display color mode in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ColorMode: Color mode (full or 8-colors). + * This parameter can be any value of @ref DSI_Color_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_MODE(ColorMode)); + + /* Update the display color mode */ + hdsi->Instance->WCR &= ~DSI_WCR_COLM; + hdsi->Instance->WCR |= ColorMode; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Control the display shutdown in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * This parameter can be any value of @ref DSI_ShutDown + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHUT_DOWN(Shutdown)); + + /* Update the display Shutdown */ + hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; + hdsi->Instance->WCR |= Shutdown; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief write short DCS or short Generic command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI short packet data type. + * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code. + * @param Param2: DSC parameter or second generic parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + Param1, + Param2); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief write long DCS or long Generic command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI long packet data type. + * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. + * @param NbParams: Number of parameters. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t* ParametersTable) +{ + uint32_t uicounter, nbBytes, count; + uint32_t tickstart; + uint32_t fifoword; + uint8_t* pparams = ParametersTable; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ + fifoword = Param1; + nbBytes = (NbParams < 3U) ? NbParams : 3U; + + for(count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count))); + } + hdsi->Instance->GPDR = fifoword; + + uicounter = NbParams - nbBytes; + pparams += nbBytes; + /* Set the Next parameters on the write FIFO command*/ + while(uicounter != 0U) + { + nbBytes = (uicounter < 4U) ? uicounter : 4U; + fifoword = 0U; + for(count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count)); + } + hdsi->Instance->GPDR = fifoword; + + uicounter -= nbBytes; + pparams += nbBytes; + } + + /* Configure the packet to send a long DCS command */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + ((NbParams+1U)&0x00FFU), + (((NbParams+1U)&0xFF00U)>>8U)); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Read command (DCS or generic) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelNbr: Virtual channel ID + * @param Array: pointer to a buffer to store the payload of a read back operation. + * @param Size: Data size to be read (in byte). + * @param Mode: DSI read packet data type. + * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. + * @param DCSCmd: DCS get/read command. + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable) +{ + uint32_t tickstart; + uint8_t* pdata = Array; + uint32_t datasize = Size; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); + + if(datasize > 2U) + { + /* set max return packet size */ + if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + + /* Configure the packet to read command */ + if (Mode == DSI_DCS_SHORT_PKT_READ) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check that the payload read FIFO is not empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Get the first byte */ + *((uint32_t *)pdata) = (hdsi->Instance->GPDR); + if (datasize > 4U) + { + datasize -= 4U; + pdata += 4U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Get the remaining bytes if any */ + while(((int)(datasize)) > 0U) + { + if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) + { + *((uint32_t *)pdata) = (hdsi->Instance->GPDR); + datasize -= 4U; + pdata += 4U; + } + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* ULPS Request on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_URDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the D-PHY active lanes enter into ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Exit ULPS on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_UEDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms*/ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Clock lane configuration: no more HS request */ + hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; + + /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLSAI2); + + /* ULPS Request on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Exit ULPS on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms */ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); + + /* Restore clock lane configuration to HS */ + hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Mode: Pattern generator mode + * This parameter can be one of the following values: + * 0 : Color bars (horizontal or vertical) + * 1 : BER pattern (vertical only) + * @param Orientation: Pattern generator orientation + * This parameter can be one of the following values: + * 0 : Vertical color bars + * 1 : Horizontal color bars + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Configure pattern generator mode and orientation */ + hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); + hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U)); + + /* Enable pattern generator by setting PGE bit */ + hdsi->Instance->VMCR |= DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable pattern generator by clearing PGE bit */ + hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set Slew-Rate And Delay Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CommDelay: Communication delay to be adjusted. + * This parameter can be any value of @ref DSI_Communication_Delay + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param Value: Custom value of the slew-rate or delay + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); + assert_param(IS_DSI_LANE_GROUP(Lane)); + + switch(CommDelay) + { + case DSI_SLEW_RATE_HSTX: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Slew Rate Control on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; + hdsi->Instance->WPCR[1U] |= Value<<16U; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Slew Rate Control on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; + hdsi->Instance->WPCR[1U] |= Value<<18U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_SLEW_RATE_LPTX: + if(Lane == DSI_CLOCK_LANE) + { + /* Low-Power transmission Slew Rate Compensation on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; + hdsi->Instance->WPCR[1U] |= Value<<6U; + } + else if(Lane == DSI_DATA_LANES) + { + /* Low-Power transmission Slew Rate Compensation on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; + hdsi->Instance->WPCR[1U] |= Value<<8U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_HS_DELAY: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Delay on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; + hdsi->Instance->WPCR[1U] |= Value; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Delay on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; + hdsi->Instance->WPCR[1U] |= Value<<2U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Low-Power Reception Filter Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Low-Power RX low-pass Filtering Tuning */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; + hdsi->Instance->WPCR[1U] |= Frequency<<25U; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Activate an additional current path on all lanes to meet the SDDTx parameter + * defined in the MIPI D-PHY specification + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Activate/Disactivate additional current path on all lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC; + hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Custom lane pins configuration + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CustomLane: Function to be applyed on selected lane. + * This parameter can be any value of @ref DSI_CustomLane + * @param Lane: select between clock or data lane 0 or data lane 1. + * This parameter can be any value of @ref DSI_Lane_Select + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); + assert_param(IS_DSI_LANE(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(CustomLane) + { + case DSI_SWAP_LANE_PINS: + if(Lane == DSI_CLK_LANE) + { + /* Swap pins on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Swap pins on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Swap pins on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_INVERT_HS_SIGNAL: + if(Lane == DSI_CLK_LANE) + { + /* Invert HS signal on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Invert HS signal on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Invert HS signal on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set custom timing for the PHY + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Timing: PHY timing to be adjusted. + * This parameter can be any value of @ref DSI_PHY_Timing + * @param State: ENABLE or DISABLE + * @param Value: Custom value of the timing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_PHY_TIMING(Timing)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(Timing) + { + case DSI_TCLK_POST: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; + hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; + } + + break; + case DSI_TLPX_CLK: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; + hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; + } + + break; + case DSI_THS_EXIT: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; + hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; + } + + break; + case DSI_TLPX_DATA: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; + hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; + } + + break; + case DSI_THS_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; + hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; + } + + break; + case DSI_THS_TRAIL: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; + hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; + } + + break; + case DSI_THS_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; + hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; + } + + break; + case DSI_TCLK_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; + hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; + } + + break; + case DSI_TCLK_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); + + if(State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; + hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; + } + + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force the Clock/Data Lane in TX Stop Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_LANE_GROUP(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + if(Lane == DSI_CLOCK_LANE) + { + /* Force/Unforce the Clock Lane in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); + } + else if(Lane == DSI_DATA_LANES) + { + /* Force/Unforce the Data Lanes in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force LP Receiver in Low-Power Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force/Unforce LP Receiver in Low-Power Mode */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM; + hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force Data Lanes in RX Mode after a BTA + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force Data Lanes in RX Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable a pull-down on the lanes to prevent from floating states when unused + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Enable/Disable pull-down on lanes */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Switch off the contention detection on data lanes + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Contention Detection on Data Lanes OFF */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DSI state. + (+) Get error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DSI state + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL state + */ +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +{ + return hdsi->State; +} + +/** + * @brief Return the DSI error code + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval DSI Error Code + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +{ + /* Get the error code */ + return hdsi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DSI */ + +#endif /* HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h new file mode 100644 index 0000000000..5baeb926e3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_dsi.h @@ -0,0 +1,1296 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_dsi.h + * @author MCD Application Team + * @brief Header file of DSI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_DSI_H +#define __STM32L4xx_HAL_DSI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(DSI) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup DSI DSI + * @brief DSI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DSI Init Structure definition + */ +typedef struct +{ + uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control + This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ + + uint32_t TXEscapeCkdiv; /*!< TX Escape clock division + The values 0 and 1 stop the TX_ESC clock generation */ + + uint32_t NumberOfLanes; /*!< Number of lanes + This parameter can be any value of @ref DSI_Number_Of_Lanes */ + +}DSI_InitTypeDef; + +/** + * @brief DSI PLL Clock structure definition + */ +typedef struct +{ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ + + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ + + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ + +}DSI_PLLInitTypeDef; + +/** + * @brief DSI Video mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using + 18-bit configuration). + This parameter can be any value of @ref DSI_LooselyPacked */ + + uint32_t Mode; /*!< Video mode type + This parameter can be any value of @ref DSI_Video_Mode_Type */ + + uint32_t PacketSize; /*!< Video packet size */ + + uint32_t NumberOfChunks; /*!< Number of chunks */ + + uint32_t NullPacketSize; /*!< Null packet size */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ + + uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ + + uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ + + uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ + + uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ + + uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ + + uint32_t VerticalActive; /*!< Vertical active duration */ + + uint32_t LPCommandEnable; /*!< Low-power command enable + This parameter can be any value of @ref DSI_LP_Command */ + + uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VSA, VBP and VFP regions */ + + uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VACT region */ + + uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable + This parameter can be any value of @ref DSI_LP_HFP */ + + uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable + This parameter can be any value of @ref DSI_LP_HBP */ + + uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable + This parameter can be any value of @ref DSI_LP_VACT */ + + uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable + This parameter can be any value of @ref DSI_LP_VFP */ + + uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable + This parameter can be any value of @ref DSI_LP_VBP */ + + uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable + This parameter can be any value of @ref DSI_LP_VSYNC */ + + uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable + This parameter can be any value of @ref DSI_FBTA_acknowledge */ + +}DSI_VidCfgTypeDef; + +/** + * @brief DSI Adapted command mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in + pixels. This parameter can be any value between 0x00 and 0xFFFFU */ + + uint32_t TearingEffectSource; /*!< Tearing effect source + This parameter can be any value of @ref DSI_TearingEffectSource */ + + uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity + This parameter can be any value of @ref DSI_TearingEffectPolarity */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted + This parameter can be any value of @ref DSI_Vsync_Polarity */ + + uint32_t AutomaticRefresh; /*!< Automatic refresh mode + This parameter can be any value of @ref DSI_AutomaticRefresh */ + + uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable + This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ + +}DSI_CmdCfgTypeDef; + +/** + * @brief DSI command transmission mode configuration + */ +typedef struct +{ + uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ + + uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ + + uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ + + uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ + + uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ + + uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ + + uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ + + uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ + + uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ + + uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ + + uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ + + uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission + This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ + + uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable + This parameter can be any value of @ref DSI_AcknowledgeRequest */ + +}DSI_LPCmdTypeDef; + +/** + * @brief DSI PHY Timings definition + */ +typedef struct +{ + uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed + to low-power transmission */ + + uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed + to low-power transmission */ + + uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ + + uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the + Stop state */ + +}DSI_PHY_TimerTypeDef; + +/** + * @brief DSI HOST Timeouts definition + */ +typedef struct +{ + uint32_t TimeoutCkdiv; /*!< Time-out clock division */ + + uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ + + uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ + + uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ + + uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ + + uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ + + uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode + This parameter can be any value of @ref DSI_HS_PrespMode */ + + uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ + + uint32_t BTATimeout; /*!< BTA time-out */ + +}DSI_HOST_TimeoutTypeDef; + +/** + * @brief DSI States Structure definition + */ +typedef enum +{ + HAL_DSI_STATE_RESET = 0x00U, + HAL_DSI_STATE_READY = 0x01U, + HAL_DSI_STATE_ERROR = 0x02U, + HAL_DSI_STATE_BUSY = 0x03U, + HAL_DSI_STATE_TIMEOUT = 0x04U +}HAL_DSI_StateTypeDef; + +/** + * @brief DSI Handle Structure definition + */ +typedef struct +{ + DSI_TypeDef *Instance; /*!< Register base address */ + DSI_InitTypeDef Init; /*!< DSI required parameters */ + HAL_LockTypeDef Lock; /*!< DSI peripheral status */ + __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ + __IO uint32_t ErrorCode; /*!< DSI Error code */ + uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ +}DSI_HandleTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_DCS_Command DSI DCS Command + * @{ + */ +#define DSI_ENTER_IDLE_MODE 0x39U +#define DSI_ENTER_INVERT_MODE 0x21U +#define DSI_ENTER_NORMAL_MODE 0x13U +#define DSI_ENTER_PARTIAL_MODE 0x12U +#define DSI_ENTER_SLEEP_MODE 0x10U +#define DSI_EXIT_IDLE_MODE 0x38U +#define DSI_EXIT_INVERT_MODE 0x20U +#define DSI_EXIT_SLEEP_MODE 0x11U +#define DSI_GET_3D_CONTROL 0x3FU +#define DSI_GET_ADDRESS_MODE 0x0BU +#define DSI_GET_BLUE_CHANNEL 0x08U +#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU +#define DSI_GET_DISPLAY_MODE 0x0DU +#define DSI_GET_GREEN_CHANNEL 0x07U +#define DSI_GET_PIXEL_FORMAT 0x0CU +#define DSI_GET_POWER_MODE 0x0AU +#define DSI_GET_RED_CHANNEL 0x06U +#define DSI_GET_SCANLINE 0x45U +#define DSI_GET_SIGNAL_MODE 0x0EU +#define DSI_NOP 0x00U +#define DSI_READ_DDB_CONTINUE 0xA8U +#define DSI_READ_DDB_START 0xA1U +#define DSI_READ_MEMORY_CONTINUE 0x3EU +#define DSI_READ_MEMORY_START 0x2EU +#define DSI_SET_3D_CONTROL 0x3DU +#define DSI_SET_ADDRESS_MODE 0x36U +#define DSI_SET_COLUMN_ADDRESS 0x2AU +#define DSI_SET_DISPLAY_OFF 0x28U +#define DSI_SET_DISPLAY_ON 0x29U +#define DSI_SET_GAMMA_CURVE 0x26U +#define DSI_SET_PAGE_ADDRESS 0x2BU +#define DSI_SET_PARTIAL_COLUMNS 0x31U +#define DSI_SET_PARTIAL_ROWS 0x30U +#define DSI_SET_PIXEL_FORMAT 0x3AU +#define DSI_SET_SCROLL_AREA 0x33U +#define DSI_SET_SCROLL_START 0x37U +#define DSI_SET_TEAR_OFF 0x34U +#define DSI_SET_TEAR_ON 0x35U +#define DSI_SET_TEAR_SCANLINE 0x44U +#define DSI_SET_VSYNC_TIMING 0x40U +#define DSI_SOFT_RESET 0x01U +#define DSI_WRITE_LUT 0x2DU +#define DSI_WRITE_MEMORY_CONTINUE 0x3CU +#define DSI_WRITE_MEMORY_START 0x2CU +/** + * @} + */ + +/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type + * @{ + */ +#define DSI_VID_MODE_NB_PULSES 0U +#define DSI_VID_MODE_NB_EVENTS 1U +#define DSI_VID_MODE_BURST 2U +/** + * @} + */ + +/** @defgroup DSI_Color_Mode DSI Color Mode + * @{ + */ +#define DSI_COLOR_MODE_FULL 0x00000000U +#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM +/** + * @} + */ + +/** @defgroup DSI_ShutDown DSI ShutDown + * @{ + */ +#define DSI_DISPLAY_ON 0x00000000U +#define DSI_DISPLAY_OFF DSI_WCR_SHTDN +/** + * @} + */ + +/** @defgroup DSI_LP_Command DSI LP Command + * @{ + */ +#define DSI_LP_COMMAND_DISABLE 0x00000000U +#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE +/** + * @} + */ + +/** @defgroup DSI_LP_HFP DSI LP HFP + * @{ + */ +#define DSI_LP_HFP_DISABLE 0x00000000U +#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE +/** + * @} + */ + +/** @defgroup DSI_LP_HBP DSI LP HBP + * @{ + */ +#define DSI_LP_HBP_DISABLE 0x00000000U +#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VACT DSI LP VACT + * @{ + */ +#define DSI_LP_VACT_DISABLE 0x00000000U +#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE +/** + * @} + */ + +/** @defgroup DSI_LP_VFP DSI LP VFP + * @{ + */ +#define DSI_LP_VFP_DISABLE 0x00000000U +#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE +/** + * @} + */ + +/** @defgroup DSI_LP_VBP DSI LP VBP + * @{ + */ +#define DSI_LP_VBP_DISABLE 0x00000000U +#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VSYNC DSI LP VSYNC + * @{ + */ +#define DSI_LP_VSYNC_DISABLE 0x00000000U +#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE +/** + * @} + */ + +/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge + * @{ + */ +#define DSI_FBTAA_DISABLE 0x00000000U +#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE +/** + * @} + */ + +/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source + * @{ + */ +#define DSI_TE_DSILINK 0x00000000U +#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC +/** + * @} + */ + +/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity + * @{ + */ +#define DSI_TE_RISING_EDGE 0x00000000U +#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL +/** + * @} + */ + +/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity + * @{ + */ +#define DSI_VSYNC_FALLING 0x00000000U +#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL +/** + * @} + */ + +/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh + * @{ + */ +#define DSI_AR_DISABLE 0x00000000U +#define DSI_AR_ENABLE DSI_WCFGR_AR +/** + * @} + */ + +/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request + * @{ + */ +#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE +/** + * @} + */ + +/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request + * @{ + */ +#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP + * @{ + */ +#define DSI_LP_GSW0P_DISABLE 0x00000000U +#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP + * @{ + */ +#define DSI_LP_GSW1P_DISABLE 0x00000000U +#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP + * @{ + */ +#define DSI_LP_GSW2P_DISABLE 0x00000000U +#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP + * @{ + */ +#define DSI_LP_GSR0P_DISABLE 0x00000000U +#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP + * @{ + */ +#define DSI_LP_GSR1P_DISABLE 0x00000000U +#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP + * @{ + */ +#define DSI_LP_GSR2P_DISABLE 0x00000000U +#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite + * @{ + */ +#define DSI_LP_GLW_DISABLE 0x00000000U +#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP + * @{ + */ +#define DSI_LP_DSW0P_DISABLE 0x00000000U +#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP + * @{ + */ +#define DSI_LP_DSW1P_DISABLE 0x00000000U +#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP + * @{ + */ +#define DSI_LP_DSR0P_DISABLE 0x00000000U +#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write + * @{ + */ +#define DSI_LP_DLW_DISABLE 0x00000000U +#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet + * @{ + */ +#define DSI_LP_MRDP_DISABLE 0x00000000U +#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS +/** + * @} + */ + +/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode + * @{ + */ +#define DSI_HS_PM_DISABLE 0x00000000U +#define DSI_HS_PM_ENABLE DSI_TCCR3_PM +/** + * @} + */ + + +/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control + * @{ + */ +#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U +#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR +/** + * @} + */ + +/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes + * @{ + */ +#define DSI_ONE_DATA_LANE 0U +#define DSI_TWO_DATA_LANES 1U +/** + * @} + */ + +/** @defgroup DSI_FlowControl DSI Flow Control + * @{ + */ +#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE +#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE +#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE +#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE +#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ + DSI_FLOW_CONTROL_EOTP_TX) +/** + * @} + */ + +/** @defgroup DSI_Color_Coding DSI Color Coding + * @{ + */ +#define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ +#define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ +#define DSI_RGB888 0x00000005U +/** + * @} + */ + +/** @defgroup DSI_LooselyPacked DSI Loosely Packed + * @{ + */ +#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE +#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity + * @{ + */ +#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP +/** + * @} + */ + +/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity + * @{ + */ +#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP +/** + * @} + */ + +/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity + * @{ + */ +#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U +#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP +/** + * @} + */ + +/** @defgroup DSI_PLL_IDF DSI PLL IDF + * @{ + */ +#define DSI_PLL_IN_DIV1 0x00000001U +#define DSI_PLL_IN_DIV2 0x00000002U +#define DSI_PLL_IN_DIV3 0x00000003U +#define DSI_PLL_IN_DIV4 0x00000004U +#define DSI_PLL_IN_DIV5 0x00000005U +#define DSI_PLL_IN_DIV6 0x00000006U +#define DSI_PLL_IN_DIV7 0x00000007U +/** + * @} + */ + +/** @defgroup DSI_PLL_ODF DSI PLL ODF + * @{ + */ +#define DSI_PLL_OUT_DIV1 0x00000000U +#define DSI_PLL_OUT_DIV2 0x00000001U +#define DSI_PLL_OUT_DIV4 0x00000002U +#define DSI_PLL_OUT_DIV8 0x00000003U +/** + * @} + */ + +/** @defgroup DSI_Flags DSI Flags + * @{ + */ +#define DSI_FLAG_TE DSI_WISR_TEIF +#define DSI_FLAG_ER DSI_WISR_ERIF +#define DSI_FLAG_BUSY DSI_WISR_BUSY +#define DSI_FLAG_PLLLS DSI_WISR_PLLLS +#define DSI_FLAG_PLLL DSI_WISR_PLLLIF +#define DSI_FLAG_PLLU DSI_WISR_PLLUIF +#define DSI_FLAG_RRS DSI_WISR_RRS +#define DSI_FLAG_RR DSI_WISR_RRIF +/** + * @} + */ + +/** @defgroup DSI_Interrupts DSI Interrupts + * @{ + */ +#define DSI_IT_TE DSI_WIER_TEIE +#define DSI_IT_ER DSI_WIER_ERIE +#define DSI_IT_PLLL DSI_WIER_PLLLIE +#define DSI_IT_PLLU DSI_WIER_PLLUIE +#define DSI_IT_RR DSI_WIER_RRIE +/** + * @} + */ + +/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ +#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ +#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ +#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ +/** + * @} + */ + +/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ +#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ +#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ +#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_Error_Data_Type DSI Error Data Type + * @{ + */ +#define HAL_DSI_ERROR_NONE 0U +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +/** + * @} + */ + +/** @defgroup DSI_Lane_Group DSI Lane Group + * @{ + */ +#define DSI_CLOCK_LANE 0x00000000U +#define DSI_DATA_LANES 0x00000001U +/** + * @} + */ + +/** @defgroup DSI_Communication_Delay DSI Communication Delay + * @{ + */ +#define DSI_SLEW_RATE_HSTX 0x00000000U +#define DSI_SLEW_RATE_LPTX 0x00000001U +#define DSI_HS_DELAY 0x00000002U +/** + * @} + */ + +/** @defgroup DSI_CustomLane DSI CustomLane + * @{ + */ +#define DSI_SWAP_LANE_PINS 0x00000000U +#define DSI_INVERT_HS_SIGNAL 0x00000001U +/** + * @} + */ + +/** @defgroup DSI_Lane_Select DSI Lane Select + * @{ + */ +#define DSI_CLK_LANE 0x00000000U +#define DSI_DATA_LANE0 0x00000001U +#define DSI_DATA_LANE1 0x00000002U +/** + * @} + */ + +/** @defgroup DSI_PHY_Timing DSI PHY Timing + * @{ + */ +#define DSI_TCLK_POST 0x00000000U +#define DSI_TLPX_CLK 0x00000001U +#define DSI_THS_EXIT 0x00000002U +#define DSI_TLPX_DATA 0x00000003U +#define DSI_THS_ZERO 0x00000004U +#define DSI_THS_TRAIL 0x00000005U +#define DSI_THS_PREPARE 0x00000006U +#define DSI_TCLK_ZERO 0x00000007U +#define DSI_TCLK_PREPARE 0x00000008U +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @brief Reset DSI handle state. + * @param __HANDLE__: DSI handle + * @retval None + */ +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) + +/** + * @brief Enables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Enables the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disable the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Enables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Enables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Disables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + }while(0U) + +/** + * @brief Get the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_BUSY : Busy Flag + * @arg DSI_FLAG_PLLLS: PLL Lock Status + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RRS : Regulator Ready Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) + +/** + * @brief Clears the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval None + */ +#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) + +/** + * @brief Enables the specified DSI interrupts. + * @param __HANDLE__: DSI handle. + * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DSI interrupts. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DSI interrupt source is enabled or not. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * This parameter can be one of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Functions DSI Exported Functions + * @{ + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); + +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); + +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DSI_Private_Types DSI Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup DSI_Private_Defines DSI Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Variables DSI Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Constants DSI Private Constants + * @{ + */ +#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DSI_Private_Macros DSI Private Macros + * @{ + */ +#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) +#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ + ((IDF) == DSI_PLL_IN_DIV2) || \ + ((IDF) == DSI_PLL_IN_DIV3) || \ + ((IDF) == DSI_PLL_IN_DIV4) || \ + ((IDF) == DSI_PLL_IN_DIV5) || \ + ((IDF) == DSI_PLL_IN_DIV6) || \ + ((IDF) == DSI_PLL_IN_DIV7)) +#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ + ((ODF) == DSI_PLL_OUT_DIV2) || \ + ((ODF) == DSI_PLL_OUT_DIV4) || \ + ((ODF) == DSI_PLL_OUT_DIV8)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) +#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ + ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ + ((VideoModeType) == DSI_VID_MODE_BURST)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) +#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) +#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) +#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ + ((MODE) == DSI_GEN_LONG_PKT_WRITE)) +#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ + ((Timing) == DSI_TLPX_CLK ) || \ + ((Timing) == DSI_THS_EXIT ) || \ + ((Timing) == DSI_TLPX_DATA ) || \ + ((Timing) == DSI_THS_ZERO ) || \ + ((Timing) == DSI_THS_TRAIL ) || \ + ((Timing) == DSI_THS_PREPARE ) || \ + ((Timing) == DSI_TCLK_ZERO ) || \ + ((Timing) == DSI_TCLK_PREPARE)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_DSI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c index 7f385889cc..f3fd43776a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_firewall.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FIREWALL HAL module driver. * This file provides firmware functions to manage the Firewall * Peripheral initialization and enabling. @@ -11,19 +9,19 @@ * @verbatim =============================================================================== - ##### How to use this driver ##### + ##### How to use this driver ##### =============================================================================== [..] The FIREWALL HAL driver can be used as follows: - + (#) Declare a FIREWALL_InitTypeDef initialization structure. - + (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API - + (#) To ensure that any code executed outside the protected segment closes the - FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling + FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment or HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment @@ -58,7 +56,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -68,12 +66,12 @@ * @{ */ -/** @defgroup FIREWALL FIREWALL +/** @defgroup FIREWALL FIREWALL * @brief HAL FIREWALL module driver * @{ */ #ifdef HAL_FIREWALL_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -86,27 +84,27 @@ * @{ */ -/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions - * @brief Initialization and Configuration Functions +/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions + * @brief Initialization and Configuration Functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This subsection provides the functions allowing to initialize the Firewall. - Initialization is done by HAL_FIREWALL_Config(): + Initialization is done by HAL_FIREWALL_Config(): (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro. - + (+) Set the protected code segment address start and length. - - (+) Set the protected non-volatile and/or volatile data segments - address starts and lengths if applicable. - + + (+) Set the protected non-volatile and/or volatile data segments + address starts and lengths if applicable. + (+) Set the volatile data segment execution and sharing status. - - (+) Length must be set to 0 for an unprotected segment. + + (+) Length must be set to 0 for an unprotected segment. @endverbatim * @{ @@ -115,7 +113,7 @@ /** * @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters. * @param fw_init: Firewall initialization structure - * @note The API returns HAL_ERROR if the Firewall is already enabled. + * @note The API returns HAL_ERROR if the Firewall is already enabled. * @retval HAL status */ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) @@ -125,7 +123,7 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) { return HAL_ERROR; } - + /* Enable Firewall clock */ __HAL_RCC_FIREWALL_CLK_ENABLE(); @@ -134,53 +132,58 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) { return HAL_ERROR; } - + /* Check Firewall configuration addresses and lengths when segment is protected */ /* Code segment */ if (fw_init->CodeSegmentLength != 0) { assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress)); - assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); + assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); + /* Make sure that NonVDataSegmentLength is properly set to prevent code segment access */ + if (fw_init->NonVDataSegmentLength < 0x100) + { + return HAL_ERROR; + } } /* Non volatile data segment */ if (fw_init->NonVDataSegmentLength != 0) { assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress)); - assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); + assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); } /* Volatile data segment */ if (fw_init->VDataSegmentLength != 0) { assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress)); - assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); + assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); } - + /* Check Firewall Configuration Register parameters */ assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution)); assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared)); - - + + /* Configuration */ - + /* Protected code segment start address configuration */ WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress)); /* Protected code segment length configuration */ WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength)); - + /* Protected non volatile data segment start address configuration */ WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress)); /* Protected non volatile data segment length configuration */ WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength)); - + /* Protected volatile data segment start address configuration */ WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress)); /* Protected volatile data segment length configuration */ - WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength)); - + WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength)); + /* Set Firewall Configuration Register VDE and VDS bits - (volatile data execution and shared configuration) */ + (volatile data execution and shared configuration) */ MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared); - + return HAL_OK; } @@ -189,71 +192,71 @@ HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) * @param fw_config: Firewall configuration, type is same as initialization structure * @note This API can't be executed inside a code area protected by the Firewall * when the Firewall is enabled - * @note If NVDSL register is different from 0, that is, if the non volatile data segment - * is defined, this API can't be executed when the Firewall is enabled. - * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status + * @note If NVDSL register is different from 0, that is, if the non volatile data segment + * is defined, this API can't be executed when the Firewall is enabled. + * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status * @retval None */ void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config) { - /* Enable Firewall clock, in case no Firewall configuration has been carried + /* Enable Firewall clock, in case no Firewall configuration has been carried out up to this point */ __HAL_RCC_FIREWALL_CLK_ENABLE(); /* Retrieve code segment protection setting */ fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD); fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG); - + /* Retrieve non volatile data segment protection setting */ fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD); fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG); - + /* Retrieve volatile data segment protection setting */ fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD); - fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG); - + fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG); + /* Retrieve volatile data execution setting */ fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE); - + /* Retrieve volatile data shared setting */ fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS); - + return; } /** - * @brief Enable FIREWALL. + * @brief Enable FIREWALL. * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register. - * Once enabled, the Firewall cannot be disabled by software. Only a - * system reset can set again FWDIS bit. + * Once enabled, the Firewall cannot be disabled by software. Only a + * system reset can set again FWDIS bit. * @retval None */ void HAL_FIREWALL_EnableFirewall(void) { /* Clears FWDIS bit of SYSCFG CFGR1 register */ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS); - + } /** - * @brief Enable FIREWALL pre arm. - * @note When FPA bit is set, any code executed outside the protected segment - * will close the Firewall. + * @brief Enable FIREWALL pre arm. + * @note When FPA bit is set, any code executed outside the protected segment + * will close the Firewall. * @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro - * but can't be executed inside a code area protected by the Firewall. - * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. - * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, + * but can't be executed inside a code area protected by the Firewall. + * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. + * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, * when the non volatile data segment is not defined), * ** this API can be executed when the Firewall is closed - * ** when the Firewall is opened, user should resort to + * ** when the Firewall is opened, user should resort to * __HAL_FIREWALL_PREARM_ENABLE() macro instead * @note When the Firewall is enabled and NVDSL register is different from 0 * (that is, when the non volatile data segment is defined) - * ** FW_CR register can be accessed only when the Firewall is opened: - * user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead. + * ** FW_CR register can be accessed only when the Firewall is opened: + * user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead. * @retval None */ void HAL_FIREWALL_EnablePreArmFlag(void) @@ -265,21 +268,21 @@ void HAL_FIREWALL_EnablePreArmFlag(void) /** * @brief Disable FIREWALL pre arm. - * @note When FPA bit is reset, any code executed outside the protected segment + * @note When FPA bit is reset, any code executed outside the protected segment * when the Firewall is opened will generate a system reset. * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro * but can't be executed inside a code area protected by the Firewall. - * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. - * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, + * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time. + * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, * when the non volatile data segment is not defined), * ** this API can be executed when the Firewall is closed - * ** when the Firewall is opened, user should resort to + * ** when the Firewall is opened, user should resort to * __HAL_FIREWALL_PREARM_DISABLE() macro instead * @note When the Firewall is enabled and NVDSL register is different from 0 * (that is, when the non volatile data segment is defined) - * ** FW_CR register can be accessed only when the Firewall is opened: - * user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead. - + * ** FW_CR register can be accessed only when the Firewall is opened: + * user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead. + * @retval None */ void HAL_FIREWALL_DisablePreArmFlag(void) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h index 77add8b1dc..00954474b9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_firewall.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_firewall.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FIREWALL HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c index d95af67b92..ec118ec837 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -120,7 +118,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 +#else #define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 +#endif /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables @@ -320,7 +322,8 @@ void HAL_FLASH_IRQHandler(void) /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); #endif @@ -337,7 +340,8 @@ void HAL_FLASH_IRQHandler(void) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) #else (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) @@ -500,18 +504,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { + HAL_StatusTypeDef status = HAL_OK; + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); - } - else - { - return HAL_ERROR; + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } } - return HAL_OK; + return status; } /** @@ -642,13 +650,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t tickstart = HAL_GetTick(); while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if((HAL_GetTick() - tickstart) >= Timeout) { return HAL_TIMEOUT; } @@ -661,7 +669,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) #else (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) @@ -746,7 +755,8 @@ static void FLASH_SetErrorCode(void) } #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)) { pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h index b74c513b77..e05c897baa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -176,7 +174,8 @@ typedef struct #define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) #define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) #endif /** @@ -197,7 +196,8 @@ typedef struct */ #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ #else @@ -237,7 +237,8 @@ typedef struct #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ #endif @@ -267,20 +268,29 @@ typedef struct #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ +#else #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ #endif +#endif #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ +#endif /** * @} */ @@ -361,7 +371,8 @@ typedef struct */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode * @{ */ @@ -370,6 +381,16 @@ typedef struct /** * @} */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type + * @{ + */ +#define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ +#define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ +/** + * @} + */ +#else /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type * @{ */ @@ -379,7 +400,18 @@ typedef struct * @} */ #endif +#endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type + * @{ + */ +#define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ +#define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ +#endif +/** + * @} + */ /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type * @{ */ @@ -409,7 +441,8 @@ typedef struct #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 * @{ */ @@ -448,6 +481,19 @@ typedef struct #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ +#endif /** * @} */ @@ -455,16 +501,16 @@ typedef struct /** @defgroup FLASH_Keys FLASH Keys * @{ */ -#define FLASH_KEY1 ((uint32_t)0x45670123U) /*!< Flash key1 */ -#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash key2: used with FLASH_KEY1 +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 to unlock the FLASH registers access */ -#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */ -#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 +#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ +#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR */ -#define FLASH_OPTKEY1 ((uint32_t)0x08192A3BU) /*!< Flash option byte key1 */ -#define FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7FU) /*!< Flash option byte key2: used with FLASH_OPTKEY1 +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 to allow option bytes operations */ /** * @} @@ -486,7 +532,8 @@ typedef struct #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ #endif #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ @@ -512,10 +559,6 @@ typedef struct * @} */ -/** - * @} - */ - /* Exported macros -----------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @brief macros to control FLASH features @@ -779,7 +822,10 @@ uint32_t HAL_FLASH_GetError(void); */ #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) +#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) #else @@ -788,13 +834,19 @@ uint32_t HAL_FLASH_GetError(void); #endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) #else #define FLASH_BANK_SIZE (FLASH_SIZE) #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define FLASH_PAGE_SIZE ((uint32_t)0x1000) +#define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) +#else #define FLASH_PAGE_SIZE ((uint32_t)0x800) +#endif #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ /** @@ -810,7 +862,8 @@ uint32_t HAL_FLASH_GetError(void); ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ ((BANK) == FLASH_BANK_2) || \ ((BANK) == FLASH_BANK_BOTH)) @@ -827,17 +880,23 @@ uint32_t HAL_FLASH_GetError(void); ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) +#else #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) +#endif #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) +#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ @@ -855,7 +914,8 @@ uint32_t HAL_FLASH_GetError(void); #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) #else @@ -866,7 +926,9 @@ uint32_t HAL_FLASH_GetError(void); ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ ((LEVEL) == OB_RDP_LEVEL_2)*/) -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) +#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) #else #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) @@ -891,12 +953,17 @@ uint32_t HAL_FLASH_GetError(void); #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) +#endif + #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) @@ -905,7 +972,8 @@ uint32_t HAL_FLASH_GetError(void); #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) @@ -913,11 +981,26 @@ uint32_t HAL_FLASH_GetError(void); #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) +#else #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ ((LATENCY) == FLASH_LATENCY_1) || \ ((LATENCY) == FLASH_LATENCY_2) || \ ((LATENCY) == FLASH_LATENCY_3) || \ ((LATENCY) == FLASH_LATENCY_4)) +#endif +/** + * @} + */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c index bd6efe7288..1ba98a0c1b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extended peripheral: @@ -85,7 +83,7 @@ */ /** @defgroup FLASHEx FLASHEx - * @brief FALSH Extended HAL module driver + * @brief FLASH Extended HAL module driver * @{ */ @@ -124,7 +122,7 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PC */ /* Exported functions -------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ @@ -208,7 +206,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* If the erase operation is completed, disable the MER1 and MER2 Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); #else @@ -405,7 +404,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) #else @@ -424,7 +424,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->USERConfig = FLASH_OB_GetUser(); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) #else if(pOBInit->PCROPConfig == FLASH_BANK_1) @@ -440,9 +441,83 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) * @} */ +#if defined (FLASH_CFGR_LVEN) +/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions + * @brief Extended specific configuration functions + * +@verbatim + =============================================================================== + ##### Extended specific configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + specific configurations. + +@endverbatim + * @{ + */ + +/** + * @brief Configuration of the LVE pin of the Flash (managed by power controller + * or forced to low in order to use an external SMPS) + * @param ConfigLVE: Configuration of the LVE pin, + * This parameter can be one of the following values: + * @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller + * @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used) + * + * @note Before enforcing the LVE pin to low, the SOC should be in low voltage + * range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_LVE_PIN(ConfigLVE)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Check that the voltage scaling is range 2 */ + if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Configure the LVEN bit */ + MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); + + /* Check that the bit has been correctly configured */ + if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) + { + status = HAL_ERROR; + } + } + else + { + /* Not allow to force Flash LVE pin if not in voltage range 2 */ + status = HAL_ERROR; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + /** * @} - */ + */ +#endif /* FLASH_CFGR_LVEN */ + +/** + * @} + */ /* Private functions ---------------------------------------------------------*/ @@ -460,6 +535,9 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) */ static void FLASH_MassErase(uint32_t Banks) { +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != RESET) +#endif { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); @@ -471,7 +549,8 @@ static void FLASH_MassErase(uint32_t Banks) } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Set the Mass Erase Bit for the bank 2 if requested */ if((Banks & FLASH_BANK_2) != RESET) { @@ -479,6 +558,12 @@ static void FLASH_MassErase(uint32_t Banks) } #endif } +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + else + { + SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); + } +#endif /* Proceed to erase all sectors */ SET_BIT(FLASH->CR, FLASH_CR_STRT); @@ -500,7 +585,15 @@ void FLASH_PageErase(uint32_t Page, uint32_t Banks) assert_param(IS_FLASH_PAGE(Page)); #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + { + CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); + } + else +#endif { assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); @@ -604,7 +697,8 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartO (WRPStartOffset | (WRDPEndOffset << 16))); } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if(WRPArea == OB_WRPAREA_BANK2_AREAA) { MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), @@ -787,7 +881,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((UserType & OB_USER_BFB2) != RESET) { /* BFB2 option byte should be modified */ @@ -800,12 +895,21 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon if((UserType & OB_USER_DUALBANK) != RESET) { +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + /* DUALBANK option byte should be modified */ + assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M)); + + /* Set value and mask for DUALBANK option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M); + optr_reg_mask |= FLASH_OPTR_DB1M; +#else /* DUALBANK option byte should be modified */ assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); /* Set value and mask for DUALBANK option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); optr_reg_mask |= FLASH_OPTR_DUALBANK; +#endif } #endif @@ -841,7 +945,8 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if((UserType & OB_USER_nSWBOOT0) != RESET) { /* nSWBOOT0 option byte should be modified */ @@ -905,7 +1010,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR uint32_t reg_value = 0; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) uint32_t bank2_addr; #endif @@ -921,7 +1027,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR if(status == HAL_OK) { #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) { @@ -937,6 +1044,29 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR bank1_addr = FLASH_BASE; #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + { + /* Configure the Proprietary code readout protection */ + if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) + { + reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); + + reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); + } + else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) + { + reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); + + reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); + MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); + } + } + else +#endif { /* Configure the Proprietary code readout protection */ if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) @@ -948,7 +1078,8 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCR MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = ((PCROPStartAddr - bank2_addr) >> 3); @@ -1007,7 +1138,8 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_ *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16); } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if(WRPArea == OB_WRPAREA_BANK2_AREAA) { *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); @@ -1082,12 +1214,14 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t reg_value = 0; uint32_t bank1_addr; #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) uint32_t bank2_addr; #endif #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) { @@ -1103,6 +1237,28 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, bank1_addr = FLASH_BASE; #endif +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) + { + if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) + { + reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); + *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; + + reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); + *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; + } + else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) + { + reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); + *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; + + reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); + *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; + } + } + else +#endif { if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { @@ -1113,7 +1269,8 @@ static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, *PCROPEndAddr = (reg_value << 3) + bank1_addr; } #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h index 80e85f1720..63d5c9fcd1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FLASH HAL Extended module. ****************************************************************************** * @attention @@ -52,15 +50,32 @@ /** @addtogroup FLASHEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +#if defined (FLASH_CFGR_LVEN) +/** @addtogroup FLASHEx_Exported_Constants + * @{ + */ +/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration + * @{ + */ +#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */ +#define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */ +/** + * @} + */ + +/** + * @} + */ +#endif /* FLASH_CFGR_LVEN */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ */ @@ -75,19 +90,40 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); /** * @} - */ + */ + +#if defined (FLASH_CFGR_LVEN) +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE); +/** + * @} + */ +#endif /* FLASH_CFGR_LVEN */ /** * @} - */ + */ + +/* Private macros ------------------------------------------------------------*/ +/** + @cond 0 + */ +#if defined (FLASH_CFGR_LVEN) +#define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED)) +#endif /* FLASH_CFGR_LVEN */ +/** + @endcond + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c index 6382464fc4..fbd9462a1a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FLASH RAMFUNC driver. * This file provides a Flash firmware functions which should be * executed from internal SRAM @@ -132,6 +130,122 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) return HAL_OK; } +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/** + * @brief Program the FLASH DBANK User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To modify the DBANK option byte, no PCROP region should be defined. + * To deactivate PCROP, user should perform RDP changing + * + * @param DBankConfig: The FLASH DBANK User Option Byte value. + * This parameter can be one of the following values: + * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data + * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data + * + * @retval HAL status + */ +__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) +{ + register uint32_t count, reg; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check if the PCROP is disabled */ + reg = FLASH->PCROP1SR; + if (reg > FLASH->PCROP1ER) + { + reg = FLASH->PCROP2SR; + if (reg > FLASH->PCROP2ER) + { + /* Disable Flash prefetch */ + __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); + + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + { + /* Disable Flash instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + + /* Flush Flash instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + } + + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + { + /* Disable Flash data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + + /* Flush Flash data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + } + + /* Disable WRP zone 1 of 1st bank if needed */ + reg = FLASH->WRP1AR; + if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_STRT)) <= + ((reg & FLASH_WRP1AR_WRP1A_END) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_END))) + { + MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); + } + + /* Disable WRP zone 2 of 1st bank if needed */ + reg = FLASH->WRP1BR; + if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_STRT)) <= + ((reg & FLASH_WRP1BR_WRP1B_END) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_END))) + { + MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); + } + + /* Disable WRP zone 1 of 2nd bank if needed */ + reg = FLASH->WRP2AR; + if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_STRT)) <= + ((reg & FLASH_WRP2AR_WRP2A_END) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_END))) + { + MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); + } + + /* Disable WRP zone 2 of 2nd bank if needed */ + reg = FLASH->WRP2BR; + if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_STRT)) <= + ((reg & FLASH_WRP2BR_WRP2B_END) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_END))) + { + MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); + } + + /* Modify the DBANK user option byte */ + MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); + + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Wait for last operation to be completed */ + /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ + count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8 / 1000); + do + { + if (count-- == 0) + { + break; + } + } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); + + /* If the option byte program operation is completed, disable the OPTSTRT Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h index a09dd20d66..b0988b0278 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash_ramfunc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention @@ -100,6 +98,9 @@ /* Peripheral Control functions ************************************************/ __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); +#endif /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c new file mode 100644 index 0000000000..1a8dd03657 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.c @@ -0,0 +1,567 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_gfxmmu.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Graphic MMU (GFXMMU) peripheral: + * + Initialization and De-initialization. + * + LUT configuration. + * + Modify physical buffer adresses. + * + Error management. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Initialization *** + ====================== + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspInit() : + (++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts are used, enable and configure GFXMMU global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the number of blocks per line, default value, physical + buffer addresses and interrupts using the HAL_GFXMMU_Init() function. + + *** LUT configuration *** + ========================= + [..] + (#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a + range of lines). + (#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM. + (#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT. + + *** Modify physical buffer adresses *** + ======================================= + [..] + (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses. + + *** Error management *** + ======================== + [..] + (#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when + an error occurs. This function will call HAL_GFXMMU_ErrorCallback(). + Use HAL_GFXMMU_GetError() to get the error code. + + *** De-initialization *** + ========================= + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() : + (++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts has been used, disable GFXMMU global interrupt with + HAL_NVIC_DisableIRQ(). + (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ +#ifdef HAL_GFXMMU_MODULE_ENABLED +#if defined(GFXMMU) +/** @defgroup GFXMMU GFXMMU + * @brief GFXMMU HAL driver module + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define GFXMMU_LUTXL_FVB_OFFSET 8U +#define GFXMMU_LUTXL_LVB_OFFSET 16U +#define GFXMMU_CR_ITS_MASK 0x1FU +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the GFXMMU. + (+) De-initialize the GFXMMU. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GFXMMU according to the specified parameters in the + * GFXMMU_InitTypeDef structure and initialize the associated handle. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if(hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address)); + assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation)); + + /* Call GFXMMU MSP init function */ + HAL_GFXMMU_MspInit(hgfxmmu); + + /* Configure blocks per line and interrupts parameters on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | + GFXMMU_CR_AMEIE | GFXMMU_CR_192BM); + hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine); + if(hgfxmmu->Init.Interrupts.Activation == ENABLE) + { + assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts)); + hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts; + } + + /* Configure default value on GFXMMU_DVR register */ + hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue; + + /* Configure physical buffer adresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address; + hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address; + hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address; + hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address; + + /* Reset GFXMMU error code */ + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Set GFXMMU to ready state */ + hgfxmmu->State = HAL_GFXMMU_STATE_READY; + } + /* Return function status */ + return status; +} + +/** + * @brief De-initialize the GFXMMU. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if(hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + + /* Disable all interrupts on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | + GFXMMU_CR_AMEIE); + + /* Call GFXMMU MSP de-init function */ + HAL_GFXMMU_MspDeInit(hgfxmmu); + + /* Set GFXMMU to reset state */ + hgfxmmu->State = HAL_GFXMMU_STATE_RESET; + } + /* Return function status */ + return status; +} + +/** + * @brief Initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspInit could be implemented in the user file. + */ +} + +/** + * @brief De-initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspDeInit could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions + * @brief GFXMMU operation functions + * +@verbatim + ============================================================================== + ##### Operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure LUT. + (+) Modify physical buffer adresses. + (+) Manage error. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to copy LUT from flash to look up RAM. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line enabled on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines enabled on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @param Address Start address of LUT in flash. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + else + { + uint32_t current_address, current_line, lutxl_address, lutxh_address; + + /* Initialize local variables */ + current_address = Address; + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Copy LUT from flash to look up RAM */ + while(current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = *((uint32_t *)current_address); + current_address += 4U; + *((uint32_t *)lutxh_address) = *((uint32_t *)current_address); + current_address += 4U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to disable a range of LUT lines. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line to disable on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines to disable on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + else + { + uint32_t current_line, lutxl_address, lutxh_address; + + /* Initialize local variables */ + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Disable LUT lines */ + while(current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to configure one line of LUT. + * @param hgfxmmu GFXMMU handle. + * @param lutLine LUT line parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber)); + assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock)); + assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset)); + + /* Check GFXMMU state */ + if(hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + uint32_t lutxl_address, lutxh_address; + + /* Initialize local variables */ + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]); + + /* Configure LUT line */ + if(lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE) + { + /* Enable and configure LUT line */ + *((uint32_t *)lutxl_address) = (lutLine->LineStatus | + (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) | + (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET)); + *((uint32_t *)lutxh_address) = lutLine->LineOffset; + } + else + { + /* Disable LUT line */ + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to modify physical buffer addresses. + * @param hgfxmmu GFXMMU handle. + * @param Buffers Buffers parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address)); + + /* Check GFXMMU state */ + if(hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + /* Modify physical buffer adresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = Buffers->Buf0Address; + hgfxmmu->Instance->B1CR = Buffers->Buf1Address; + hgfxmmu->Instance->B2CR = Buffers->Buf2Address; + hgfxmmu->Instance->B3CR = Buffers->Buf3Address; + } + /* Return function status */ + return status; +} + +/** + * @brief This function handles the GFXMMU interrupts. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t flags, interrupts, error; + + /* Read current flags and interrupts and determine which error occurs */ + flags = hgfxmmu->Instance->SR; + interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK); + error = (flags & interrupts); + + if(error != 0U) + { + /* Clear flags on GFXMMU_FCR register */ + hgfxmmu->Instance->FCR = error; + + /* Update GFXMMU error code */ + hgfxmmu->ErrorCode |= error; + + /* Call GFXMMU error callback */ + HAL_GFXMMU_ErrorCallback(hgfxmmu); + } +} + +/** + * @brief Error callback. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_GFXMMU_ErrorCallback could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @brief GFXMMU state functions + * +@verbatim + ============================================================================== + ##### State functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Get GFXMMU handle state. + (+) Get GFXMMU error code. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to get the current GFXMMU handle state. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU state. + */ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Return GFXMMU handle state */ + return hgfxmmu->State; +} + +/** + * @brief This function allows to get the current GFXMMU error code. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU error code. + */ +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t error_code; + + /* Enter in critical section */ + __disable_irq(); + + /* Store and reset GFXMMU error code */ + error_code = hgfxmmu->ErrorCode; + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Exit from critical section */ + __enable_irq(); + + /* Return GFXMMU error code */ + return error_code; +} + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ +#endif /* GFXMMU */ +#endif /* HAL_GFXMMU_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h new file mode 100644 index 0000000000..7c8e6622b3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gfxmmu.h @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_gfxmmu.h + * @author MCD Application Team + * @brief Header file of GFXMMU HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_GFXMMU_H +#define __STM32L4xx_HAL_GFXMMU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(GFXMMU) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup GFXMMU + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types + * @{ + */ + +/** + * @brief HAL GFXMMU states definition + */ +typedef enum +{ + HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */ + HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */ +}HAL_GFXMMU_StateTypeDef; + +/** + * @brief GFXMMU buffers structure definition + */ +typedef struct +{ + uint32_t Buf0Address; /*!< Physical address of buffer 0. */ + uint32_t Buf1Address; /*!< Physical address of buffer 1. */ + uint32_t Buf2Address; /*!< Physical address of buffer 2. */ + uint32_t Buf3Address; /*!< Physical address of buffer 3. */ +}GFXMMU_BuffersTypeDef; + +/** + * @brief GFXMMU interrupts structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Interrupts enable/disable */ + uint32_t UsedInterrupts; /*!< Interrupts used. + This parameter can be a values combination of @ref GFXMMU_Interrupts. + @note: Usefull only when interrupts are enabled. */ +}GFXMMU_InterruptsTypeDef; + +/** + * @brief GFXMMU init structure definition + */ +typedef struct +{ + uint32_t BlocksPerLine; /*!< Number of blocks of 16 bytes per line. + This parameter can be a value of @ref GFXMMU_BlocksPerLine. */ + uint32_t DefaultValue; /*!< Value returned when virtual memory location not physically mapped. */ + GFXMMU_BuffersTypeDef Buffers; /*!< Physical buffers addresses. */ + GFXMMU_InterruptsTypeDef Interrupts; /*!< Interrupts parameters. */ +}GFXMMU_InitTypeDef; + +/** + * @brief GFXMMU handle structure definition + */ +typedef struct +{ + GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */ + GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */ + HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */ + __IO uint32_t ErrorCode; /*!< GFXMMU error code */ +}GFXMMU_HandleTypeDef; + +/** + * @brief GFXMMU LUT line structure definition + */ +typedef struct +{ + uint32_t LineNumber; /*!< LUT line number. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */ + uint32_t LineStatus; /*!< LUT line enable/disable. + This parameter can be a value of @ref GFXMMU_LutLineStatus. */ + uint32_t FirstVisibleBlock; /*!< First visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + uint32_t LastVisibleBlock; /*!< Last visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + int32_t LineOffset; /*!< Offset of block 0 of the current line in physical buffer. + This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208. + @note: Line offset has to be computed with the following formula: + LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */ +}GFXMMU_LutLineTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants + * @{ + */ + +/** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line + * @{ + */ +#define GFXMMU_256BLOCKS 0x00000000U /*!< 256 blocks of 16 bytes per line */ +#define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */ +/** + * @} + */ + +/** @defgroup GFXMMU_Interrupts GFXMMU interrupts + * @{ + */ +#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */ +#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */ +#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */ +#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */ +#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */ +/** + * @} + */ + +/** @defgroup GFXMMU_Error_Code GFXMMU Error Code + * @{ + */ +#define GFXMMU_ERROR_NONE 0x00000000U /*!< No error */ +#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */ +#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */ +#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */ +#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */ +#define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */ +/** + * @} + */ + +/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status + * @{ + */ +#define GFXMMU_LUT_LINE_DISABLE 0x00000000U /*!< LUT line disabled */ +#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN /*!< LUT line enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros + * @{ + */ + +/** @brief Reset GFXMMU handle state. + * @param __HANDLE__ GFXMMU handle. + * @retval None + */ +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions + * @{ + */ +/* Operation functions ********************************************************/ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address); + +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber); + +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); + +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers); + +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu); + +void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @{ + */ +/* State function *************************************************************/ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); + +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros +* @{ +*/ +#define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \ + ((VALUE) == GFXMMU_192BLOCKS)) + +#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U) + +#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U) + +#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U) + +#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U)) + +#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \ + ((VALUE) == GFXMMU_LUT_LINE_ENABLE)) + +#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U) + +#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208)) +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* GFXMMU */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_GFXMMU_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c index 7b52c96902..280eb31cfc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h index d386421f53..9f4bbac544 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h index b58d43c787..63c69cb9e0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_gpio_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of GPIO HAL Extended module. ****************************************************************************** * @attention @@ -572,6 +570,150 @@ #endif /* STM32L496xx || STM32L4A6xx */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +/*---STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx--*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ +#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OctoSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ +#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ +#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ +#define GPIO_AF5_OCTOSPIM_P1 ((uint8_t)0x05) /* OctoSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF5_OCTOSPIM_P2 ((uint8_t)0x05) /* OctoSPI Manager Port 2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ +#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF10_OCTOSPIM_P2 ((uint8_t)0x0A) /* OctoSPI Manager Port 2 Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#define GPIO_AF12_DSI ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ +#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ +#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @} */ @@ -641,6 +783,18 @@ #endif /* STM32L496xx || STM32L4A6xx */ +#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c index 2b84bd69cc..7fbd5f94f0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: @@ -140,7 +138,7 @@ #ifdef HAL_HASH_MODULE_ENABLED -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -182,6 +180,14 @@ * @} */ +/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit + * @{ + */ +#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20 /*!< Number of words below which DMA suspension is aborted */ +/** + * @} + */ + /** * @} */ @@ -1083,9 +1089,32 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) } else { - /* Set State as suspended (it may be required to update it if suspension failed). - The context saving operations must be carried out to be able to resume later on. */ - hhash->State = HAL_HASH_STATE_SUSPENDED; + + /* Make sure there is enough time to suspend the processing */ + tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; + if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) + { + /* No suspension attempted since almost to the end of the transferred data. */ + /* Best option for user code is to wrap up low priority message hashing */ + return HAL_ERROR; + } + + /* Wait for DMAS to be reset */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) + { + return HAL_ERROR; + } + + /* Wait for DMAS to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } /* Disable DMA channel */ HAL_DMA_Abort(hhash->hdmain); @@ -1093,6 +1122,16 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* Clear DMAE bit */ CLEAR_BIT(HASH->CR,HASH_CR_DMAE); + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) + { + return HAL_ERROR; + } + /* At this point, DMA interface is disabled and no transfer is on-going */ /* Retrieve from the DMA handle how many words remain to be written */ tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR; @@ -1108,7 +1147,6 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) priority block processing (HASH case) - re-attempt a new suspension (HMAC case) */ - hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; } else @@ -1126,6 +1164,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } + /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */ hhash->pHashInBuffPtr += 4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; @@ -1134,6 +1173,9 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) } + /* Set State as suspended */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + return HAL_OK; } @@ -2250,6 +2292,7 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, processing was suspended */ inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */ inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */ + } /* Set the HASH DMA transfert complete callback */ @@ -2668,7 +2711,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #endif /* HAL_HASH_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h index 17682fa6af..be9bb69822 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -570,7 +568,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c index ffa5eecfca..0b5fe23b97 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral for SHA-224 and SHA-256 @@ -99,7 +97,7 @@ #ifdef HAL_HASH_MODULE_ENABLED -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -927,7 +925,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #endif /* HAL_HASH_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h index 3e930ed5ac..8a0011e62c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined (STM32L4A6xx) +#if defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -170,7 +168,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ -#endif /* defined (STM32L4A6xx) */ +#endif /* defined (STM32L4A6xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c index e909779e37..a1b683449b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -73,7 +71,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -1279,6 +1278,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) */ #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h index 2c34736126..d79b1e531e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_hcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" @@ -252,7 +251,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); */ #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c index 7b6fb65d98..f46bff66fa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -238,7 +236,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -303,8 +301,8 @@ /* Private macro -------------------------------------------------------------*/ #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) + ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ + ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -366,7 +364,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -406,7 +404,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -421,7 +419,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - if(hi2c->State == HAL_I2C_STATE_RESET) + if (hi2c->State == HAL_I2C_STATE_RESET) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; @@ -444,7 +442,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); } @@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { hi2c->Instance->CR2 = (I2C_CR2_ADD10); } @@ -493,7 +491,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -557,7 +555,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * @verbatim =============================================================================== @@ -569,7 +567,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function + The status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. @@ -630,7 +628,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -638,7 +636,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -646,7 +644,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -654,7 +652,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -665,12 +663,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -684,15 +682,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -707,9 +705,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -754,7 +752,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -762,7 +760,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -778,7 +776,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -789,12 +787,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -809,15 +807,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -832,9 +830,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -865,7 +863,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /** - * @brief Transmits in slave mode an amount of data in blocking mode. + * @brief Transmits in slave mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -877,9 +875,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -902,7 +900,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -910,13 +908,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -924,26 +922,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -959,12 +957,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Normal use case for Transmitter mode */ /* A NACK is generated to confirm the end of transfer */ @@ -977,10 +975,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1017,9 +1015,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1042,7 +1040,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1050,33 +1048,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferCount--; } - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; } @@ -1092,12 +1090,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1108,10 +1106,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1149,9 +1147,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1168,8 +1166,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1185,7 +1183,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current @@ -1218,9 +1216,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1237,8 +1235,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1252,7 +1250,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1283,7 +1281,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1323,7 +1321,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -1332,7 +1330,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1385,9 +1383,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1404,8 +1402,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1416,7 +1414,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; @@ -1454,7 +1452,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); @@ -1493,9 +1491,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1512,8 +1510,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1524,7 +1522,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; @@ -1541,7 +1539,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1562,7 +1560,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); @@ -1596,12 +1594,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); @@ -1642,7 +1640,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; return HAL_OK; } @@ -1662,9 +1660,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1737,9 +1735,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1750,7 +1748,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1765,9 +1763,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1782,7 +1780,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1796,9 +1794,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1813,15 +1811,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1833,13 +1831,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1889,9 +1888,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1902,7 +1901,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1917,9 +1916,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1935,7 +1934,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -1949,7 +1948,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, do { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1959,15 +1958,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1978,13 +1977,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -2033,14 +2033,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2060,8 +2060,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2073,9 +2073,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2090,12 +2090,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ @@ -2132,14 +2132,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2159,8 +2159,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2172,9 +2172,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2230,14 +2230,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2257,8 +2257,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2270,9 +2270,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2346,14 +2346,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2374,7 +2374,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2386,9 +2386,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2416,7 +2416,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2458,9 +2458,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2474,16 +2474,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd do { /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2491,14 +2491,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } - } + } } /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2517,7 +2517,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2535,8 +2535,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2544,7 +2544,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - }while(I2C_Trials < Trials); + } + while (I2C_Trials < Trials); hi2c->State = HAL_I2C_STATE_READY; @@ -2579,7 +2580,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2595,7 +2596,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If size > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2606,6 +2607,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } + /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2645,7 +2653,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2661,7 +2669,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2672,8 +2680,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; + } + /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2706,9 +2721,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2718,10 +2733,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); @@ -2741,11 +2756,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2780,9 +2795,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2792,15 +2807,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); } - + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2815,11 +2830,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2847,7 +2862,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->XferISR = I2C_Slave_ISR_IT; @@ -2875,7 +2890,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) uint32_t tmp; /* Disable Address listen mode only if a transfer is not ongoing */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); @@ -2904,7 +2919,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if(hi2c->Mode == HAL_I2C_MODE_MASTER) + if (hi2c->Mode == HAL_I2C_MODE_MASTER) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2923,7 +2938,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -2944,7 +2959,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief This function handles I2C event interrupt request. @@ -2959,7 +2974,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C events treatment -------------------------------------*/ - if(hi2c->XferISR != NULL) + if (hi2c->XferISR != NULL) { hi2c->XferISR(hi2c, itflags, itsources); } @@ -2977,7 +2992,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C Bus error interrupt occurred ------------------------------------*/ - if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -2986,7 +3001,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -2995,7 +3010,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -3004,7 +3019,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -3077,8 +3092,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -3228,7 +3243,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @} - */ + */ /** * @} @@ -3246,14 +3261,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3266,27 +3281,27 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -3294,7 +3309,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { hi2c->XferSize = hi2c->XferCount; - if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } @@ -3307,7 +3322,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { /* Call TxCpltCallback() if no stop mode is set */ - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSequentialCplt(hi2c); @@ -3320,14 +3335,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Generate a stop condition in case of no transfer option */ - if(hi2c->XferOptions == I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -3347,7 +3362,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3367,26 +3382,26 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } - else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3414,9 +3429,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; @@ -3424,24 +3439,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->XferCount--; } - if((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + if ((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); - } + } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); @@ -3450,7 +3465,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } else { - if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ @@ -3460,7 +3475,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } /* Check if STOPF is set */ - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3480,7 +3495,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; uint32_t xfermode = 0U; @@ -3488,14 +3503,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - + /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ @@ -3504,18 +3519,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if(hi2c->XferCount != 0U) + + if (hi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - + /* Prepare the new XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -3533,7 +3548,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui hi2c->XferCount -= hi2c->XferSize; /* Enable DMA Request */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } @@ -3549,7 +3564,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3569,18 +3584,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3590,17 +3605,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3626,12 +3641,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3642,7 +3657,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3654,9 +3669,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3665,18 +3680,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } -return HAL_OK; + return HAL_OK; } /** @@ -3693,12 +3708,12 @@ return HAL_OK; */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3709,7 +3724,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3721,9 +3736,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3732,17 +3747,17 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -3763,7 +3778,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); @@ -3771,19 +3786,19 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; - if(hi2c->AddrEventCount == 2U) + if (hi2c->AddrEventCount == 2U) { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3885,7 +3900,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3901,7 +3916,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) HAL_I2C_SlaveTxCpltCallback(hi2c); } - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3937,7 +3952,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if((ITFlags & I2C_FLAG_AF) != RESET) + if ((ITFlags & I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3950,16 +3965,16 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); /* Call the corresponding callback to inform upper layer of End of Transfer */ - if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; @@ -3985,7 +4000,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4022,7 +4037,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); @@ -4037,26 +4052,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ - if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); } /* All data are not transferred, so set error code accordingly */ - if(hi2c->XferCount != 0U) + if (hi2c->XferCount != 0U) { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4070,19 +4085,19 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } } - else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; @@ -4094,7 +4109,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) HAL_I2C_ListenCpltCallback(hi2c); } /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4132,12 +4147,12 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4177,9 +4192,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); @@ -4193,10 +4208,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ - if(hi2c->State != HAL_I2C_STATE_ABORT) + if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; @@ -4206,7 +4221,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } /* Abort DMA TX transfer if any */ - if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4218,14 +4233,14 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } /* Abort DMA RX transfer if any */ - else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -4237,16 +4252,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } - else if(hi2c->State == HAL_I2C_STATE_ABORT) + else if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4272,13 +4287,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) { - hi2c->Instance->TXDR = 0x00U; + hi2c->Instance->TXDR = 0x00U; } /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); } @@ -4291,13 +4306,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4309,7 +4324,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4348,13 +4363,13 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4366,7 +4381,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4405,7 +4420,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4417,12 +4432,12 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4432,10 +4447,10 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->hdmarx->XferAbortCallback = NULL; /* Check if come from abort from user */ - if(hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_AbortCpltCallback(hi2c); } @@ -4458,14 +4473,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4487,21 +4502,21 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4524,19 +4539,19 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4558,38 +4573,49 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check if a STOPF is detected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4610,18 +4636,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4644,7 +4670,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4676,25 +4702,14 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); - /* Get the CR2 register value */ - tmpreg = hi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; + MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -4708,28 +4723,28 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr { uint32_t tmpisr = 0U; - if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -4737,31 +4752,31 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr } else { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } } - + /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ @@ -4781,49 +4796,49 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter { uint32_t tmpisr = 0U; - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h index 93bbd5eaf3..7a8f85f292 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32L4xx_HAL_I2C_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" +#include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -52,7 +50,7 @@ /** @addtogroup I2C * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types @@ -60,13 +58,13 @@ */ /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition + * @brief I2C Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization + This parameter calculated by referring to I2C initialization section in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. @@ -90,9 +88,9 @@ typedef struct uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ -}I2C_InitTypeDef; +} I2C_InitTypeDef; -/** +/** * @} */ @@ -122,7 +120,7 @@ typedef struct * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ - */ + */ typedef enum { HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ @@ -139,7 +137,7 @@ typedef enum HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -}HAL_I2C_StateTypeDef; +} HAL_I2C_StateTypeDef; /** * @} @@ -170,9 +168,9 @@ typedef enum HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -}HAL_I2C_ModeTypeDef; +} HAL_I2C_ModeTypeDef; -/** +/** * @} */ @@ -213,7 +211,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -228,7 +226,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -}I2C_HandleTypeDef; +} I2C_HandleTypeDef; /** * @} */ @@ -313,7 +311,7 @@ typedef struct __I2C_HandleTypeDef /** * @} */ - + /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ @@ -337,9 +335,9 @@ typedef struct __I2C_HandleTypeDef * @{ */ #define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ @@ -431,7 +429,7 @@ typedef struct __I2C_HandleTypeDef * @retval None */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified I2C interrupt source is enabled or not. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the I2C interrupt source to check. @@ -506,7 +504,7 @@ typedef struct __I2C_HandleTypeDef #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) @@ -527,7 +525,7 @@ typedef struct __I2C_HandleTypeDef */ /* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** @@ -538,7 +536,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); * @{ */ /* IO operation functions ****************************************************/ - /******* Blocking mode: Polling */ +/******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -547,7 +545,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - /******* Non-Blocking mode: Interrupt */ +/******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -563,7 +561,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - /******* Non-Blocking mode: DMA */ +/******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -604,11 +602,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants @@ -617,7 +615,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros @@ -681,7 +679,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions @@ -690,15 +688,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /* Private functions are defined in stm32l4xx_hal_i2c.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c index 2602734c8d..bd4e329dd2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.c @@ -2,10 +2,8 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: * + Extended features functions * @@ -19,7 +17,8 @@ (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop modes + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus ##### How to use this driver ##### ============================================================================== @@ -96,8 +95,9 @@ ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Noise Filters + (+) Configure Noise Filters (+) Configure Wake Up Feature + (+) Configure Fast Mode Plus @endverbatim * @{ @@ -116,7 +116,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -162,7 +162,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -200,17 +200,17 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ } /** - * @brief Enable I2C wakeup from stop mode. + * @brief Enable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -239,17 +239,17 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) } /** - * @brief Disable I2C wakeup from stop mode. + * @brief Disable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -262,7 +262,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) /* Enable wakeup from stop mode */ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - __HAL_I2C_ENABLE(hi2c); + __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h index e6d115a1ba..726a83fba8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention @@ -40,7 +38,7 @@ #define __STM32L4xx_HAL_I2C_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,7 +50,7 @@ /** @addtogroup I2CEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -101,7 +99,7 @@ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -152,7 +150,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c index 99d4049298..ecefca38d5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_irda.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -158,14 +156,41 @@ * @{ */ #define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */ + #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ /* Private macros ------------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ IRDA clock source. + * @param __BAUD__ Baud rate set by the user. + * @param __PRESCALER__ IRDA clock prescaler value. + * @retval Division result + */ +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) +#else +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ IRDA clock source. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) +#endif + /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +static const uint16_t IRDAPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; +#else +#endif + /* Private function prototypes -----------------------------------------------*/ /** @addtogroup IRDA_Private_Functions * @{ @@ -186,7 +211,7 @@ static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @} @@ -248,9 +273,9 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); */ /** - * @brief Initialize the IRDA mode according to the specified - * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Initialize the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and initialize the associated handle. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -302,8 +327,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) } /** - * @brief DeInitialize the IRDA peripheral. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief DeInitialize the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -336,8 +361,8 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) } /** - * @brief Initialize the IRDA MSP. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Initialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -352,8 +377,8 @@ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) } /** - * @brief DeInitialize the IRDA MSP. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief DeInitialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -376,7 +401,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) * @verbatim =============================================================================== - ##### IO operation functions ##### + ##### IO operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the IRDA data transfers. @@ -388,7 +413,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. - (#) There are two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode: the communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. @@ -453,11 +478,11 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) */ /** - * @brief Send an amount of data in blocking mode. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Send an amount of data in blocking mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -525,11 +550,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u } /** - * @brief Receive an amount of data in blocking mode. + * @brief Receive an amount of data in blocking mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -600,11 +625,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui } /** - * @brief Send an amount of data in interrupt mode. + * @brief Send an amount of data in interrupt mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -631,8 +656,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData __HAL_UNLOCK(hirda); /* Enable the IRDA Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); - +#endif + return HAL_OK; } else @@ -642,11 +671,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData } /** - * @brief Receive an amount of data in interrupt mode. + * @brief Receive an amount of data in interrupt mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -677,7 +706,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, __HAL_UNLOCK(hirda); /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); +#else SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); +#endif /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -691,11 +724,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, } /** - * @brief Send an amount of data in DMA mode. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Send an amount of data in DMA mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -752,11 +785,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat } /** - * @brief Receive an amount of data in DMA mode. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Receive an amount of data in DMA mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @note When the IRDA parity is enabled (PCE = 1), the received data contains * the parity bit (MSB position). * @retval HAL status @@ -818,9 +851,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /** - * @brief Pause the DMA Transfer. + * @brief Pause the DMA Transfer. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) @@ -852,9 +885,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) } /** - * @brief Resume the DMA Transfer. + * @brief Resume the DMA Transfer. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) @@ -887,9 +920,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) } /** - * @brief Stop the DMA Transfer. + * @brief Stop the DMA Transfer. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) @@ -950,7 +983,11 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Tx request if enabled */ @@ -1018,7 +1055,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) @@ -1061,7 +1102,11 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Rx request if enabled */ @@ -1112,7 +1157,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) uint32_t abortcplt = 1; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised @@ -1236,7 +1285,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the IRDA DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) @@ -1302,7 +1355,11 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Rx request if enabled */ @@ -1358,8 +1415,8 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) } /** - * @brief Handle IRDA interrupt request. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Handle IRDA interrupt request. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1375,7 +1432,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) if (errorflags == RESET) { /* IRDA in mode Receiver ---------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) +#else if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { IRDA_Receive_IT(hirda); return; @@ -1386,7 +1447,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) cr3its = READ_REG(hirda->Instance->CR3); if( (errorflags != RESET) && ( ((cr3its & USART_CR3_EIE) != RESET) +#if defined(USART_CR1_FIFOEN) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)) ) +#else || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) +#endif { /* IRDA parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) @@ -1414,7 +1479,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA Over-Run interrupt occurred -----------------------------------------*/ if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#else + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#endif { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); @@ -1425,7 +1494,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) { /* IRDA in mode Receiver ---------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET)) +#else if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { IRDA_Receive_IT(hirda); } @@ -1484,7 +1557,11 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) } /* End if some error occurs */ /* IRDA in mode Transmitter ------------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET)) +#else if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif { IRDA_Transmit_IT(hirda); return; @@ -1549,7 +1626,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1651,9 +1728,9 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) */ /** - * @brief Return the IRDA handle state. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @brief Return the IRDA handle state. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL state */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) @@ -1667,8 +1744,8 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) } /** - * @brief Return the IRDA handle error code. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Return the IRDA handle error code. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ @@ -1690,8 +1767,8 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) */ /** - * @brief Configure the IRDA peripheral. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Configure the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -1708,6 +1785,9 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler)); +#endif /*-------------------------- USART CR1 Configuration -----------------------*/ /* Configure the IRDA Word Length, Parity and transfer Mode: @@ -1721,27 +1801,55 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /*-------------------------- USART CR3 Configuration -----------------------*/ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); +#if defined(USART_PRESC_PRESCALER) + /*--------------------- USART clock PRESC Configuration ----------------*/ + /* Configure + * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */ + MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); +#endif + /*-------------------------- USART GTPR Configuration ----------------------*/ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); + tmpreg = 0; switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_PCLK2: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); +#else + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(LSE_VALUE, hirda->Init.BaudRate)); +#endif break; case IRDA_CLOCKSOURCE_UNDEFINED: default: @@ -1749,12 +1857,22 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) break; } + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hirda->Instance->BRR = tmpreg; + } + else + { + ret = HAL_ERROR; + } + return ret; } /** - * @brief Check the IRDA Idle State. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Check the IRDA Idle State. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -1820,7 +1938,11 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); hirda->gState = HAL_IRDA_STATE_READY; @@ -1845,7 +1967,11 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* At end of Tx process, restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; @@ -1861,7 +1987,11 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore hirda->RxState to Ready */ @@ -1914,7 +2044,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1944,7 +2074,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1956,8 +2086,8 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA IRDA communication error callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA IRDA communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2147,7 +2277,11 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) if(hirda->TxXferCount == 0) { /* Disable the IRDA Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); +#endif /* Enable the IRDA Transmit Complete Interrupt */ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); @@ -2181,9 +2315,9 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) * @brief Wrap up transmission in non-blocking mode. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable the IRDA Transmit Complete Interrupt */ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); @@ -2192,8 +2326,6 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) hirda->gState = HAL_IRDA_STATE_READY; HAL_IRDA_TxCpltCallback(hirda); - - return HAL_OK; } /** @@ -2228,7 +2360,11 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) if(--hirda->RxXferCount == 0) { /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h index 4fced53ab0..148d4e78d6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_irda.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -66,7 +64,8 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. The baud rate register is computed using the following formula: - Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */ + Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) + where usart_ker_ckpres is the IRDA input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref IRDA_Word_Length */ @@ -87,6 +86,12 @@ typedef struct uint16_t PowerMode; /*!< Specifies the IRDA power mode. This parameter can be a value of @ref IRDA_Low_Power */ + +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source. + This parameter can be a value of @ref IRDA_ClockPrescaler. */ +#endif + }IRDA_InitTypeDef; /** @@ -154,13 +159,13 @@ typedef enum */ typedef enum { - HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */ - HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */ - HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */ - HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */ - HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_IRDA_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_IRDA_ERROR_BUSY = 0x20 /*!< Busy Error */ + HAL_IRDA_ERROR_NONE = 0x00U, /*!< No error */ + HAL_IRDA_ERROR_PE = 0x01U, /*!< Parity error */ + HAL_IRDA_ERROR_NE = 0x02U, /*!< Noise error */ + HAL_IRDA_ERROR_FE = 0x04U, /*!< frame error */ + HAL_IRDA_ERROR_ORE = 0x08U, /*!< Overrun error */ + HAL_IRDA_ERROR_DMA = 0x10U, /*!< DMA transfer error */ + HAL_IRDA_ERROR_BUSY = 0x20U /*!< Busy Error */ }HAL_IRDA_ErrorTypeDef; /** @@ -168,12 +173,12 @@ typedef enum */ typedef enum { - IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }IRDA_ClockSourceTypeDef; /** @@ -181,7 +186,7 @@ typedef enum */ typedef struct { - USART_TypeDef *Instance; /*!< IRDA registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ @@ -189,7 +194,7 @@ typedef struct uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ - __IO uint16_t TxXferCount; /* !Instance->ICR = (__FLAG__)) /** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) /** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) /** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) /** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) /** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) /** @brief Check whether the specified IRDA flag is set or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag @@ -493,8 +537,8 @@ typedef enum /** @brief Enable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -509,8 +553,8 @@ typedef enum ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -526,8 +570,8 @@ typedef enum /** @brief Check whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -537,13 +581,13 @@ typedef enum * @arg @ref IRDA_IT_NE Noise Error interrupt * @arg @ref IRDA_IT_FE Framing Error interrupt * @arg @ref IRDA_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08))) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt * @arg @ref IRDA_IT_TC Transmission complete interrupt @@ -551,15 +595,15 @@ typedef enum * @arg @ref IRDA_IT_IDLE Idle line detection interrupt * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt * @arg @ref IRDA_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) - +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag @@ -573,8 +617,8 @@ typedef enum /** @brief Set a specific IRDA request flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the IRDA Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request @@ -585,25 +629,25 @@ typedef enum #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None - */ + */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the IRDA one bit sample method. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None - */ + */ #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART/USART associated to IRDA Handle. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -619,7 +663,7 @@ typedef enum /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. */ #define IRDA_MASK_COMPUTATION(__HANDLE__) \ @@ -660,20 +704,20 @@ typedef enum } while(0) /** @brief Ensure that IRDA Baud rate is less or equal to maximum value. - * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False */ #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) /** @brief Ensure that IRDA prescaler value is strictly larger than 0. - * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. + * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. * @retval True or False */ #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) /** * @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__: IRDA frame length. + * @param __LENGTH__ IRDA frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ @@ -682,7 +726,7 @@ typedef enum /** * @brief Ensure that IRDA frame parity is valid. - * @param __PARITY__: IRDA frame parity. + * @param __PARITY__ IRDA frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ @@ -691,22 +735,42 @@ typedef enum /** * @brief Ensure that IRDA communication mode is valid. - * @param __MODE__: IRDA communication mode. + * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) /** * @brief Ensure that IRDA power mode is valid. - * @param __MODE__: IRDA power mode. + * @param __MODE__ IRDA power mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ ((__MODE__) == IRDA_POWERMODE_NORMAL)) +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Ensure that IRDA clock Prescaler is valid. + * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) +#endif + /** * @brief Ensure that IRDA state is valid. - * @param __STATE__: IRDA state mode. + * @param __STATE__ IRDA state mode. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ @@ -722,7 +786,7 @@ typedef enum /** * @brief Ensure that IRDA sampling rate is valid. - * @param __ONEBIT__: IRDA sampling rate. + * @param __ONEBIT__ IRDA sampling rate. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ @@ -730,7 +794,7 @@ typedef enum /** * @brief Ensure that IRDA DMA TX mode is valid. - * @param __DMATX__: IRDA DMA TX mode. + * @param __DMATX__ IRDA DMA TX mode. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ @@ -738,7 +802,7 @@ typedef enum /** * @brief Ensure that IRDA DMA RX mode is valid. - * @param __DMARX__: IRDA DMA RX mode. + * @param __DMARX__ IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ @@ -746,7 +810,7 @@ typedef enum /** * @brief Ensure that IRDA request is valid. - * @param __PARAM__: IRDA request. + * @param __PARAM__ IRDA request. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h index 5a19356577..487795de3d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_irda_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IRDA HAL Extended module. ****************************************************************************** * @attention @@ -66,11 +64,13 @@ */ /** @brief Report the IRDA clock source. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c index 9917a4f678..e5080c41b1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_iwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h index bead6ad7a7..b11dc2119f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c index 0bd57fdbcd..9c6bdc857f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LCD Controller HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LCD Controller (LCD) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h index dc7f4bf57b..754cf5615a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LCD Controller HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c index 362dfa5fe0..01b100fb10 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lptim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LPTIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Low Power Timer (LPTIM) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h index d5426a7b68..ee1a6b3d65 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_lptim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_lptim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c new file mode 100644 index 0000000000..885043f72a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.c @@ -0,0 +1,1896 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc.c + * @author MCD Application Team + * @brief LTDC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the LTDC peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Program the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, + the pixel clock polarity, Data Enable polarity and the LTDC background color value + using HAL_LTDC_Init() function + + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size + and the image size using HAL_LTDC_ConfigLayer() function for foreground + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + HAL_LTDC_EnableCLUT functions. + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() + and HAL_LTDC_EnableColorKeying functions. + + (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() + function + + (#) If needed, reconfigure and change the pixel format value, the alpha value + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following + functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), + HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). + + (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). + + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + an immediate reload is required. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if + the reload should be done in the next vertical blanking period, + this option allows to avoid display flicker by applying the new settings during the vertical blanking period. + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + *** LTDC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in LTDC HAL driver. + + (+) __HAL_LTDC_ENABLE: Enable the LTDC. + (+) __HAL_LTDC_DISABLE: Disable the LTDC. + (+) __HAL_LTDC_LAYER_ENABLE: Enable a LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable a LTDC Layer. + (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. + + [..] + (@) You can refer to the LTDC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +#ifdef HAL_LTDC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Functions LTDC Exported Functions + * @{ + */ + +/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) De-initialize the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tmp = 0, tmp1 = 0; + + /* Check the LTDC peripheral state */ + if(hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); + assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); + assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); + assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); + assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); + assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); + assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); + assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); + assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); + + if(hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + } + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + tmp = (hltdc->Init.HorizontalSync << 16); + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + tmp = (hltdc->Init.AccumulatedHBP << 16); + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + tmp = (hltdc->Init.AccumulatedActiveW << 16); + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + tmp = (hltdc->Init.TotalWidth << 16); + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16); + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initialize the LTDC peripheral. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ + +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) +{ + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle LTDC interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handle LTDC interrupt request. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + uint32_t isrflags = READ_REG(hltdc->Instance->ISR); + uint32_t itsources = READ_REG(hltdc->Instance->IER); + + /* Transfer Error Interrupt management ***************************************/ + if(((isrflags & LTDC_ISR_TERRIF) != RESET) && ((itsources & LTDC_IER_TERRIE) != RESET)) + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ + HAL_LTDC_ErrorCallback(hltdc); + } + + /* FIFO underrun Interrupt management ***************************************/ + if(((isrflags & LTDC_ISR_FUIF) != RESET) && ((itsources & LTDC_IER_FUIE) != RESET)) + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ + HAL_LTDC_ErrorCallback(hltdc); + } + + /* Line Interrupt management ************************************************/ + if(((isrflags & LTDC_ISR_LIF) != RESET) && ((itsources & LTDC_IER_LIE) != RESET)) + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Line interrupt Callback */ + HAL_LTDC_LineEventCallback(hltdc); + } + + /* Register reload Interrupt management ***************************************/ + if(((isrflags & LTDC_ISR_RRIF) != RESET) && ((itsources & LTDC_IER_RRIE) != RESET)) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Register reload interrupt Callback */ + HAL_LTDC_ReloadEventCallback(hltdc); + } +} + +/** + * @brief Error LTDC callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief Reload Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the LTDC foreground or/and background parameters. + (+) Set the active layer. + (+) Configure the color keying. + (+) Configure the C-LUT. + (+) Enable / Disable the color keying. + (+) Enable / Disable the C-LUT. + (+) Update the layer position. + (+) Update the layer size. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the LTDC Layer according to the specified + * parameters in the LTDC_InitTypeDef and create the associated handle. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Load the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t counter = 0; + uint32_t pcounter = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + for(counter = 0; (counter < CLUTSize); counter++) + { + if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + { + tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + } + else + { + tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + } + pcounter = (uint32_t)pCLUT + sizeof(*pCLUT); + pCLUT = (uint32_t *)pcounter; + + /* Specifies the C-LUT address and RGB value */ + LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; + } + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable Dither by setting DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} +/** + * @brief Reconfigure the frame buffer Address. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(Line)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Set the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)Line; + + /* Enable the Line interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reload LTDC Layers configuration. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the LTDC handle state. + (+) Get the LTDC handle error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LTDC handle state. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->State; +} + +/** + * @brief Return the LTDC handle error code. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. +* @retval LTDC Error Code +*/ +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @brief Configure the LTDC peripheral + * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp); + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp); + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16); + tmp2 = (pLayerCfg->Alpha0 << 24); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + + if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3)); + + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; +} + +/** + * @} + */ + +#endif /* HAL_LTDC_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4S7xx || STM32L4S9xx */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h new file mode 100644 index 0000000000..b5f308980a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc.h @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc.h + * @author MCD Application Team + * @brief Header file of LTDC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_LTDC_H +#define __STM32L4xx_HAL_LTDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Types LTDC Exported Types + * @{ + */ +#define MAX_LAYER 2U + +/** + * @brief LTDC color structure definition + */ +typedef struct +{ + uint8_t Blue; /*!< Configures the blue value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Green; /*!< Configures the green value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Red; /*!< Configures the red value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + +/** + * @brief LTDC Init structure definition + */ +typedef struct +{ + uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HS_POLARITY */ + + uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VS_POLARITY */ + + uint32_t DEPolarity; /*!< configures the data enable polarity. + This parameter can be one of value of @ref LTDC_DE_POLARITY */ + + uint32_t PCPolarity; /*!< configures the pixel clock polarity. + This parameter can be one of value of @ref LTDC_PC_POLARITY */ + + uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + + uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. + This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. + This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + + uint32_t TotalWidth; /*!< configures the total width. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + + uint32_t TotalHeigh; /*!< configures the total height. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ +typedef struct +{ + uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ + + uint32_t PixelFormat; /*!< Specifies the pixel format. + This parameter can be one of value of @ref LTDC_Pixelformat */ + + uint32_t Alpha; /*!< Specifies the constant alpha used for blending. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t Alpha0; /*!< Configures the default alpha value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t BlendingFactor1; /*!< Select the blending factor 1. + This parameter can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t BlendingFactor2; /*!< Select the blending factor 2. + This parameter can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ +} LTDC_LayerCfgTypeDef; + +/** + * @brief HAL LTDC State structures definition + */ +typedef enum +{ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ +}HAL_LTDC_StateTypeDef; + +/** + * @brief LTDC handle Structure definition + */ +typedef struct +{ + LTDC_TypeDef *Instance; /*!< LTDC Register base address */ + + LTDC_InitTypeDef Init; /*!< LTDC parameters */ + + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ + + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +} LTDC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Constants LTDC Exported Constants + * @{ + */ + +/** @defgroup LTDC_Error_Code LTDC Error Code + * @{ + */ +#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */ +/** + * @} + */ + +/** @defgroup LTDC_Layer LTDC Layer + * @{ + */ +#define LTDC_LAYER_1 ((uint32_t)0x00000000U) /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 ((uint32_t)0x00000001U) /*!< LTDC Layer 2 */ +/** + * @} + */ + +/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY + * @{ + */ +#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY + * @{ + */ +#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY + * @{ + */ +#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY + * @{ + */ +#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ +/** + * @} + */ + +/** @defgroup LTDC_SYNC LTDC SYNC + * @{ + */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ +/** + * @} + */ + +/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR + * @{ + */ +#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 + * @{ + */ +#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 + * @{ + */ +#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat LTDC Pixel format + * @{ + */ +#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */ +/** + * @} + */ + +/** @defgroup LTDC_Alpha LTDC Alpha + * @{ + */ +#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ +/** + * @} + */ + +/** @defgroup LTDC_LAYER_Config LTDC LAYER Config + * @{ + */ +#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ +#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ + +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ +/** + * @} + */ + +/** @defgroup LTDC_Interrupts LTDC Interrupts + * @{ + */ +#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ +#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ +#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ +#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ +/** + * @} + */ + +/** @defgroup LTDC_Flags LTDC Flags + * @{ + */ +#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ +#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ +#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ +#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ +/** + * @} + */ + +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** @brief Reset LTDC handle state. + * @param __HANDLE__ LTDC handle + * @retval None + */ +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) + +/** + * @brief Enable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) + +/** + * @brief Disable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) + +/** + * @brief Enable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Disable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Reload immediately all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) + +/** + * @brief Reload during vertical blanking period all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) + +/* Interrupt & Flag management */ +/** + * @brief Get the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clears the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Specify the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified LTDC interrupt has occurred or not. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt source to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) +/** + * @} + */ + +/* Include LTDC HAL Extension module */ +#include "stm32l4xx_hal_ltdc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDC_Exported_Functions + * @{ + */ +/** @addtogroup LTDC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Macros LTDC Private Macros + * @{ + */ +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))) +#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) +#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) +#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) +#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) +#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) +#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) +#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4R7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_LTDC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c new file mode 100644 index 0000000000..bc0eab10fe --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.c @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc_ex.c + * @author MCD Application Team + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#if defined (STM32L4R9xx) || defined (STM32L4S9xx) + +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* STM32L4R9xx || STM32L4S9xx */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h new file mode 100644 index 0000000000..ff827cb2f9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ltdc_ex.h @@ -0,0 +1,101 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ltdc_ex.h + * @author MCD Application Team + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_LTDC_EX_H +#define __STM32L4xx_HAL_LTDC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (STM32L4R9xx) || defined (STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" +#include "stm32l4xx_hal_dsi.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDCEx_Exported_Functions + * @{ + */ + +/** @addtogroup LTDCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R9xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_LTDC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c index bce42d5748..d66dda6cef 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nand.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -86,7 +84,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -1128,5 +1127,6 @@ static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTyp #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h index f0395451e1..1292ae8727 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nand.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nand.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -297,6 +296,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c index 1ab593b170..585ffaa0ef 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nor.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -86,7 +84,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -1063,5 +1062,6 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h index 9749c3a068..d302ee479d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_nor.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_nor.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -293,6 +292,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c index 330f51901a..3aa42edc21 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief OPAMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the operational amplifier(s) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h index 0a664ccdd7..a9dca5c23e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of OPAMP HAL module. ****************************************************************************** * @attention @@ -300,29 +298,40 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; ((INPUT) == OPAMP_PGA_MODE) || \ ((INPUT) == OPAMP_FOLLOWER_MODE)) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) - +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_INVERTINGINPUT_IO1)) -#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ +#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) ((INPUT) == OPAMP_INVERTINGINPUT_IO0) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH)) -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ - ((INPUT) == OPAMP_INVERTINGINPUT_IO1)|| \ + ((INPUT) == OPAMP_INVERTINGINPUT_IO1) || \ ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO)) -#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ +#endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */ + /* STM32L496xx STM32L4A6xx */ + /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) +#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ + defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define IS_OPAMP_INVERTING_INPUT_PGA(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ ((INPUT) == OPAMP_INVERTINGINPUT_CONNECT_NO)) -#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx STM32L451xx STM32L452xx STM32L462xx */ +#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ + /* STM32L451xx STM32L452xx STM32L462xx */ #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \ ((GAIN) == OPAMP_PGA_GAIN_4) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c index 1c5d0bff6e..8a0f250e93 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended OPAMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) @@ -68,7 +66,8 @@ */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) /** @addtogroup OPAMPEx_Exported_Functions_Group1 * @brief Extended operation functions diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h index 904fb4fa6f..ac507d8879 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_opamp_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_opamp_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of OPAMP HAL Extended module. ****************************************************************************** * @attention @@ -62,7 +60,9 @@ */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + /* I/O operation functions *****************************************************/ /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c new file mode 100644 index 0000000000..5c87b74618 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.c @@ -0,0 +1,2564 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ospi.c + * @author MCD Application Team + * @brief OSPI HAL module driver. + This file provides firmware functions to manage the following + functionalities of the OctoSPI interface (OSPI). + + Initialization and de-initialization functions + + Hyperbus configuration + + Indirect functional mode management + + Memory-mapped functional mode management + + Auto-polling functional mode management + + Interrupts and flags management + + DMA channel configuration for indirect functional mode + + Errors management and abort functionality + + IO manager configuration + + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + *** Initialization *** + ====================== + [..] + (#) As prerequisite, fill in the HAL_OSPI_MspInit() : + (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE(). + (++) Reset OctoSPI IP with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET(). + (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init(). + (++) If interrupt or DMA mode is used, enable and configure OctoSPI global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure + DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the fifo threshold, the dual-quad mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay + and the CS boundary using the HAL_OSPI_Init() function. + (#) When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() + function. + + *** Indirect functional mode *** + ================================ + [..] + (#) In regular mode, configure the command sequence using the HAL_OSPI_Command() + or HAL_OSPI_Command_IT() functions : + (++) Instruction phase : the mode used and if present the size, the instruction + opcode and the DTR mode. + (++) Address phase : the mode used and if present the size, the address + value and the DTR mode. + (++) Alternate-bytes phase : the mode used and if present the size, the + alternate bytes values and the DTR mode. + (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (++) Data phase : the mode used and if present the number of bytes and the DTR mode. + (++) Data strobe (DQS) mode : the activation (or not) of this mode + (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + (++) Flash identifier : in dual-quad mode, indicates which flash is concerned + (++) Operation type : always common configuration + (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() + function : + (++) Address space : indicate if the access will be done in register or memory + (++) Address size + (++) Number of data + (++) Data strobe (DQS) mode : the activation (or not) of this mode + (#) If no data is required for the command (only for regular mode, not for + Hyperbus mode), it is sent directly to the memory : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete. + (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or + HAL_OSPI_Transmit_IT() after the command configuration : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and + HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. + (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or + HAL_OSPI_Receive_IT() after the command configuration : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and + HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. + + *** Auto-polling functional mode *** + ==================================== + [..] + (#) Configure the command sequence by the same way than the indirect mode + (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() + or HAL_OSPI_AutoPolling_IT() functions : + (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), + the polling interval and the automatic stop activation. + (#) After the configuration : + (++) In polling mode, the output of the function is done when the status match is reached. The + automatic stop is activated to avoid an infinite loop. + (++) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached. + + *** Memory-mapped functional mode *** + ===================================== + [..] + (#) Configure the command sequence by the same way than the indirect mode except + for the operation type in regular mode : + (++) Operation type equals to read configuration : the command configuration + applies to read access in memory-mapped mode + (++) Operation type equals to write configuration : the command configuration + applies to write access in memory-mapped mode + (++) Both read and write configuration should be performed before activating + memory-mapped mode + (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() + functions : + (++) The timeout activation and the timeout period. + (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on + the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. + + *** Errors management and abort functionality *** + ================================================= + [..] + (#) HAL_OSPI_GetError() function gives the error raised during the last operation. + (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and + flushes the fifo : + (++) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. + + *** Control functions *** + ========================= + [..] + (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver. + (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver. + (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI IP. + (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + + *** IO manager configuration functions *** + ========================================== + [..] + (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup OSPI OSPI + * @brief OSPI HAL module driver + * @{ + */ + +#ifdef HAL_OSPI_MODULE_ENABLED + +/** + @cond 0 + */ +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +#define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */ +#define OSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)OCTOSPI_CR_FMODE_0) /*!< Indirect read mode */ +#define OSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)OCTOSPI_CR_FMODE_1) /*!< Automatic polling mode */ +#define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)OCTOSPI_CR_FMODE) /*!< Memory-mapped mode */ + +#define OSPI_CFG_STATE_MASK 0x00000004U +#define OSPI_BUSY_STATE_MASK 0x00000008U + +#define OSPI_NB_INSTANCE 2 +#define OSPI_IOM_NB_PORTS 2 + +/* Private macro -------------------------------------------------------------*/ +#define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ + ((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \ + ((MODE) == OSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \ + ((MODE) == OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +static void OSPI_DMACplt (DMA_HandleTypeDef *hdma); +static void OSPI_DMAHalfCplt (DMA_HandleTypeDef *hdma); +static void OSPI_DMAError (DMA_HandleTypeDef *hdma); +static void OSPI_DMAAbortCplt (DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg); +/** + @endcond + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup OSPI_Exported_Functions OSPI Exported Functions + * @{ + */ + +/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Initialize the OctoSPI. + (+) De-initialize the OctoSPI. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the OSPI mode according to the specified parameters + * in the OSPI_InitTypeDef and initialize the associated handle. + * @param hospi : OSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the OSPI handle allocation */ + if (hospi == NULL) + { + status = HAL_ERROR; + /* No error code can be set set as the handler is null */ + } + else + { + /* Check the parameters of the initialization structure */ + assert_param(IS_OSPI_FIFO_THRESHOLD (hospi->Init.FifoThreshold)); + assert_param(IS_OSPI_DUALQUAD_MODE (hospi->Init.DualQuad)); + assert_param(IS_OSPI_MEMORY_TYPE (hospi->Init.MemoryType)); + assert_param(IS_OSPI_DEVICE_SIZE (hospi->Init.DeviceSize)); + assert_param(IS_OSPI_CS_HIGH_TIME (hospi->Init.ChipSelectHighTime)); + assert_param(IS_OSPI_FREE_RUN_CLK (hospi->Init.FreeRunningClock)); + assert_param(IS_OSPI_CLOCK_MODE (hospi->Init.ClockMode)); + assert_param(IS_OSPI_WRAP_SIZE (hospi->Init.WrapSize)); + assert_param(IS_OSPI_CLK_PRESCALER (hospi->Init.ClockPrescaler)); + assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting)); + assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle)); + assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary)); + + /* Initialize error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_NONE; + + /* Check if the state is the reset state */ + if (hospi->State == HAL_OSPI_STATE_RESET) + { + /* Initialization of the low level hardware */ + HAL_OSPI_MspInit(hospi); + + /* Configure the default timeout for the OSPI memory access */ + status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); + } + + if (status == HAL_OK) + { + /* Configure memory type, device size, chip select high time, free running clock, clock mode */ + MODIFY_REG(hospi->Instance->DCR1, (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE), + (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1) << OCTOSPI_DCR1_DEVSIZE_Pos) | + ((hospi->Init.ChipSelectHighTime - 1) << OCTOSPI_DCR1_CSHT_Pos) | hospi->Init.FreeRunningClock | + hospi->Init.ClockMode)); + + /* Configure wrap size */ + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize); + + /* Configure chip select boundary */ + hospi->Instance->DCR3 = (hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos); + + + /* Configure FIFO threshold */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1) << OCTOSPI_CR_FTHRES_Pos)); + + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Configure clock prescaler */ + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1) << OCTOSPI_DCR2_PRESCALER_Pos)); + + /* Configure Dual Quad mode */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); + + /* Configure sample shifting and delay hold quarter cycle */ + MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); + + /* Enable OctoSPI */ + __HAL_OSPI_ENABLE(hospi); + + /* Initialize the OSPI state */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT; + } + else + { + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Initialize the OSPI MSP. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_MspInit can be implemented in the user file + */ +} + +/** + * @brief De-Initialize the OSPI peripheral. + * @param hospi : OSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the OSPI handle allocation */ + if (hospi == NULL) + { + status = HAL_ERROR; + /* No error code can be set set as the handler is null */ + } + else + { + /* Disable OctoSPI */ + __HAL_OSPI_DISABLE(hospi); + + /* De-initialize the low-level hardware */ + HAL_OSPI_MspDeInit(hospi); + + /* Reset the driver state */ + hospi->State = HAL_OSPI_STATE_RESET; + } + + return status; +} + +/** + * @brief DeInitialize the OSPI MSP. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief OSPI Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Handle the interrupts. + (+) Handle the command sequence (regular and Hyperbus). + (+) Handle the Hyperbus configuration. + (+) Transmit data in blocking, interrupt or DMA mode. + (+) Receive data in blocking, interrupt or DMA mode. + (+) Manage the auto-polling functional mode. + (+) Manage the memory-mapped functional mode. + +@endverbatim + * @{ + */ + +/** + * @brief Handle OSPI interrupt request. + * @param hospi : OSPI handle + * @retval None + */ +void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) +{ + __IO uint32_t *data_reg = &hospi->Instance->DR; + uint32_t flag = hospi->Instance->SR; + uint32_t itsource = hospi->Instance->CR; + uint32_t currentstate = hospi->State; + + /* OctoSPI fifo threshold interrupt occurred -------------------------------*/ + if (((flag & HAL_OSPI_FLAG_FT) != 0) && ((itsource & HAL_OSPI_IT_FT) != 0)) + { + if (currentstate == HAL_OSPI_STATE_BUSY_TX) + { + /* Write a data in the fifo */ + *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + hospi->XferCount--; + } + else if (currentstate == HAL_OSPI_STATE_BUSY_RX) + { + /* Read a data from the fifo */ + *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + hospi->XferCount--; + } + + if (hospi->XferCount == 0) + { + /* All data have been received or transmitted for the transfer */ + /* Disable fifo threshold interrupt */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_FT); + } + + /* Fifo threshold callback */ + HAL_OSPI_FifoThresholdCallback(hospi); + } + /* OctoSPI transfer complete interrupt occurred ----------------------------*/ + else if (((flag & HAL_OSPI_FLAG_TC) != 0) && ((itsource & HAL_OSPI_IT_TC) != 0)) + { + if (currentstate == HAL_OSPI_STATE_BUSY_RX) + { + if (((flag & OCTOSPI_SR_FLEVEL) != 0) && (hospi->XferCount > 0)) + { + /* Read the last data received in the fifo */ + *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void*)data_reg); + hospi->XferCount--; + } + else if(hospi->XferCount == 0) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TC; + + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* RX complete callback */ + HAL_OSPI_RxCpltCallback(hospi); + } + } + else + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TC; + + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + if (currentstate == HAL_OSPI_STATE_BUSY_TX) + { + /* TX complete callback */ + HAL_OSPI_TxCpltCallback(hospi); + } + else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) + { + /* Command complete callback */ + HAL_OSPI_CmdCpltCallback(hospi); + } + else if (currentstate == HAL_OSPI_STATE_ABORT) + { + if (hospi->ErrorCode == HAL_OSPI_ERROR_NONE) + { + /* Abort called by the user */ + /* Abort complete callback */ + HAL_OSPI_AbortCpltCallback(hospi); + } + else + { + /* Abort due to an error (eg : DMA error) */ + /* Error callback */ + HAL_OSPI_ErrorCallback(hospi); + } + } + } + } + /* OctoSPI status match interrupt occurred ---------------------------------*/ + else if (((flag & HAL_OSPI_FLAG_SM) != 0) && ((itsource & HAL_OSPI_IT_SM) != 0)) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_SM; + + /* Check if automatic poll mode stop is activated */ + if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0) + { + /* Disable the interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + + /* Status match callback */ + HAL_OSPI_StatusMatchCallback(hospi); + } + /* OctoSPI transfer error interrupt occurred -------------------------------*/ + else if (((flag & HAL_OSPI_FLAG_TE) != 0) && ((itsource & HAL_OSPI_IT_TE) != 0)) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TE; + + /* Disable all interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); + + /* Set error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER; + + /* Check if the DMA is enabled */ + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + { + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA transfer on the DMA side */ + hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; + HAL_DMA_Abort_IT(hospi->hdma); + } + else + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ + HAL_OSPI_ErrorCallback(hospi); + } + } + /* OctoSPI timeout interrupt occurred --------------------------------------*/ + else if (((flag & HAL_OSPI_FLAG_TO) != 0) && ((itsource & HAL_OSPI_IT_TO) != 0)) + { + /* Clear flag */ + hospi->Instance->FCR = HAL_OSPI_FLAG_TO; + + /* Timeout callback */ + HAL_OSPI_TimeOutCallback(hospi); + } +} + +/** + * @brief Set the command configuration. + * @param hospi : OSPI handle + * @param cmd : structure that contains the command configuration information + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); + + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) + { + assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); + } + + assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) + { + assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); + assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); + } + + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize)); + assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode)); + } + + assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode)); + if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize)); + assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode)); + } + + assert_param(IS_OSPI_DATA_MODE(cmd->DataMode)); + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + { + assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData)); + } + assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode)); + assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles)); + } + + assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); + assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); + + /* Check the state of the driver */ + if (((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || + ((hospi->State == HAL_OSPI_STATE_READ_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)) || + ((hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG) && (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG))) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_NONE; + + /* Configure the registers */ + status = OSPI_ConfigCmd(hospi, cmd); + + if (status == HAL_OK) + { + if (cmd->DataMode == HAL_OSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so wait until TC flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); + + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + } + else + { + /* Update the state */ + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + { + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + else if (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) + { + if (hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG) + { + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + else + { + hospi->State = HAL_OSPI_STATE_READ_CMD_CFG; + } + } + else + { + if (hospi->State == HAL_OSPI_STATE_READ_CMD_CFG) + { + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + else + { + hospi->State = HAL_OSPI_STATE_WRITE_CMD_CFG; + } + } + } + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Set the command configuration in interrupt mode. + * @param hospi : OSPI handle + * @param cmd : structure that contains the command configuration information + * @note This function is used only in Indirect Read or Write Modes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); + + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) + { + assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); + } + + assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) + { + assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize)); + assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); + } + + assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize)); + assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode)); + } + + assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode)); + if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize)); + assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode)); + } + + assert_param(IS_OSPI_DATA_MODE(cmd->DataMode)); + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData)); + assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode)); + assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles)); + } + + assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); + assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); + + /* Check the state of the driver */ + if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) && + (cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hospi->ErrorCode = HAL_OSPI_ERROR_NONE; + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Configure the registers */ + status = OSPI_ConfigCmd(hospi, cmd); + + if (status == HAL_OK) + { + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_CMD; + + /* Enable the transfer complete and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE); + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the Hyperbus parameters. + * @param hospi : OSPI handle + * @param cfg : Structure containing the Hyperbus configuration + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus configuration structure */ + assert_param(IS_OSPI_RW_RECOVERY_TIME (cfg->RWRecoveryTime)); + assert_param(IS_OSPI_ACCESS_TIME (cfg->AccessTime)); + assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency)); + assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode)); + + /* Check the state of the driver */ + if ((hospi->State == HAL_OSPI_STATE_HYPERBUS_INIT) || (hospi->State == HAL_OSPI_STATE_READY)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure Hyperbus configuration Latency register */ + WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | + (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) | + cfg->WriteZeroLatency | cfg->LatencyMode)); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Set the Hyperbus command configuration. + * @param hospi : OSPI handle + * @param cmd : Structure containing the Hyperbus command + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus command structure */ + assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace)); + assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize)); + assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData)); + assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode)); + + /* Check the state of the driver */ + if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); + + /* Configure the address space in the DCR1 register */ + MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace); + + /* Configure the CCR and WCCR registers with the address size and the following configuration : + - DQS signal enabled (used as RWDS) + - DTR mode enabled on address and data + - address and data on 8 lines */ + WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | + cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2)); + WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 | + cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2)); + + /* Configure the DLR register with the number of data */ + WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1)); + + /* Configure the AR register with the address value */ + WRITE_REG(hospi->Instance->AR, cmd->Address); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_CMD_CFG; + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hospi->Instance->DR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + do + { + /* Wait till fifo threshold flag is set to send data */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *(__IO uint8_t *)((__IO void *)data_reg) = *hospi->pBuffPtr++; + hospi->XferCount--; + } while (hospi->XferCount > 0); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hospi->Instance->DR; + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + + do + { + /* Wait till fifo threshold or transfer complete flags are set to read received data */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *hospi->pBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); + hospi->XferCount--; + } while(hospi->XferCount > 0); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_TX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1; + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_RX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp; + uint32_t data_size = hospi->Instance->DLR + 1; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + hospi->XferCount = data_size; + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) + { + if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 1); + } + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) + { + if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 2); + } + } + + if (status == HAL_OK) + { + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_TX; + + /* Set the DMA transfer complete callback */ + hospi->hdma->XferCpltCallback = OSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hospi->hdma->XferErrorCallback = OSPI_DMAError; + + /* Clear the DMA abort callback */ + hospi->hdma->XferAbortCallback = NULL; + + /* Configure the direction of the DMA */ + hospi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); + + /* Enable the transmit DMA Channel */ + tmp = (uint32_t*)((void*)&pData); + HAL_DMA_Start_IT(hospi->hdma, *(uint32_t*)tmp, (uint32_t)&hospi->Instance->DR, hospi->XferSize); + + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hospi : OSPI handle + * @param pData : pointer to data buffer. + * @note This function is used only in Indirect Read Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp; + uint32_t data_size = hospi->Instance->DLR + 1; + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + { + hospi->XferCount = data_size; + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) + { + if (((data_size % 2) != 0) || ((hospi->Init.FifoThreshold % 2) != 0)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 1); + } + } + else if (hospi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) + { + if (((data_size % 4) != 0) || ((hospi->Init.FifoThreshold % 4) != 0)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hospi->XferCount = (data_size >> 2); + } + } + + if (status == HAL_OK) + { + hospi->XferSize = hospi->XferCount; + hospi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); + + /* Update the state */ + hospi->State = HAL_OSPI_STATE_BUSY_RX; + + /* Set the DMA transfer complete callback */ + hospi->hdma->XferCpltCallback = OSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hospi->hdma->XferErrorCallback = OSPI_DMAError; + + /* Clear the DMA abort callback */ + hospi->hdma->XferAbortCallback = NULL; + + /* Configure the direction of the DMA */ + hospi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); + + /* Enable the transmit DMA Channel */ + tmp = (uint32_t*)((void *)&pData); + HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, *(uint32_t*)tmp, hospi->XferSize); + + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the OSPI Automatic Polling Mode in blocking mode. + * @param hospi : OSPI handle + * @param cfg : structure that contains the polling configuration information. + * @param Timeout : Timeout duration + * @note This function is used only in Automatic Polling Mode + * @note This function should not be used when the memory is in octal mode (see Errata Sheet) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); + assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); + assert_param(IS_OSPI_INTERVAL (cfg->Interval)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + + /* Check the state */ + if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE)) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG (hospi->Instance->PSMAR, cfg->Match); + WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); + WRITE_REG (hospi->Instance->PIR, cfg->Interval); + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + + /* Wait till status match flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear status match flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode. + * @param hospi : OSPI handle + * @param cfg : structure that contains the polling configuration information. + * @note This function is used only in Automatic Polling Mode + * @note This function should not be used when the memory is in octal mode (see Errata Sheet) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hospi->Instance->AR; + uint32_t ir_reg = hospi->Instance->IR; + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); + assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop)); + assert_param(IS_OSPI_INTERVAL (cfg->Interval)); + assert_param(IS_OSPI_STATUS_BYTES_SIZE(hospi->Instance->DLR+1)); + + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG (hospi->Instance->PSMAR, cfg->Match); + WRITE_REG (hospi->Instance->PSMKR, cfg->Mask); + WRITE_REG (hospi->Instance->PIR, cfg->Interval); + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), + (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_SM); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING; + + /* Enable the status match and transfer error interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the Memory Mapped mode. + * @param hospi : OSPI handle + * @param cfg : structure that contains the memory mapped configuration information. + * @note This function is used only in Memory mapped Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the memory-mapped configuration structure */ + assert_param(IS_OSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); + + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED; + + if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE) + { + assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); + + /* Configure register */ + WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod); + + /* Clear flags related to interrupt */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TO); + + /* Enable the timeout interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TO); + } + + /* Configure CR register with functional mode as memory-mapped */ + MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE), + (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** + * @brief Transfer Error callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Abort completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief FIFO Threshold callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_FIFOThresholdCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_CmdCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ + __weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Status Match callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_StatusMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout callback. + * @param hospi : OSPI handle + * @retval None + */ +__weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_OSPI_TimeOutCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief OSPI control and State functions + * +@verbatim + =============================================================================== + ##### Peripheral Control and State functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Check in run-time the state of the driver. + (+) Check the error code set during last operation. + (+) Abort any operation. + (+) Manage the Fifo threshold. + (+) Configure the timeout duration used in the driver. + +@endverbatim + * @{ + */ + +/** +* @brief Abort the current transmission. +* @param hospi : OSPI handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check if the state is in one of the busy or configured states */ + if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + { + /* Check if the DMA is enabled */ + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + { + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA transfer on the DMA side */ + status = HAL_DMA_Abort(hospi->hdma); + if (status != HAL_OK) + { + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + } + } + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state */ + status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); + + if (status == HAL_OK) + { + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** +* @brief Abort the current transmission (non-blocking function) +* @param hospi : OSPI handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check if the state is in one of the busy or configured states */ + if (((hospi->State & OSPI_BUSY_STATE_MASK) != 0) || ((hospi->State & OSPI_CFG_STATE_MASK) != 0)) + { + /* Disable all interrupts */ + __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); + + /* Update state */ + hospi->State = HAL_OSPI_STATE_ABORT; + + /* Check if the DMA is enabled */ + if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0) + { + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA transfer on the DMA side */ + hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; + HAL_DMA_Abort_IT(hospi->hdma); + } + else + { + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** @brief Set OSPI Fifo threshold. + * @param hospi : OSPI handle. + * @param Threshold : Threshold of the Fifo. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the state */ + if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0) + { + /* Synchronize initialization structure with the new fifo threshold value */ + hospi->Init.FifoThreshold = Threshold; + + /* Configure new fifo threshold */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1) << OCTOSPI_CR_FTHRES_Pos)); + + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; + } + + /* Return function status */ + return status; +} + +/** @brief Get OSPI Fifo threshold. + * @param hospi : OSPI handle. + * @retval Fifo threshold + */ +uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi) +{ + return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1); +} + +/** @brief Set OSPI timeout. + * @param hospi : OSPI handle. + * @param Timeout : Timeout for the memory access. + * @retval None + */ +HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout) +{ + hospi->Timeout = Timeout; + return HAL_OK; +} + +/** +* @brief Return the OSPI error code. +* @param hospi : OSPI handle +* @retval OSPI Error Code +*/ +uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi) +{ + return hospi->ErrorCode; +} + +/** + * @brief Return the OSPI handle state. + * @param hospi : OSPI handle + * @retval HAL state + */ +uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi) +{ + /* Return OSPI handle state */ + return hospi->State; +} + +/** + * @} + */ + +/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function + * @brief OSPI IO Manager configuration function + * +@verbatim + =============================================================================== + ##### IO Manager configuration function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Configure the IO manager. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the OctoSPI IO manager. + * @param hospi : OSPI handle + * @param cfg : Configuration of the IO Manager for the instance + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t instance = 0; + uint8_t index = 0, ospi_enabled = 0, other_instance = 0; + OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; + + /* Check the parameters of the OctoSPI IO Manager configuration structure */ + assert_param(IS_OSPIM_PORT(cfg->ClkPort)); + assert_param(IS_OSPIM_PORT(cfg->DQSPort)); + assert_param(IS_OSPIM_PORT(cfg->NCSPort)); + assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); + assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); + + if (hospi->Instance == OCTOSPI1) + { + instance = 0; + other_instance = 1; + } + else + { + instance = 1; + other_instance = 0; + } + + /**************** Get current configuration of the instances ****************/ + for (index = 0; index < OSPI_NB_INSTANCE; index++) + { + if (OSPIM_GetConfig(index+1, &(IOM_cfg[index])) != HAL_OK) + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + } + + if (status == HAL_OK) + { + /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/ + if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0) + { + CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); + ospi_enabled |= 0x1; + } + if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0) + { + CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); + ospi_enabled |= 0x2; + } + + /***************** Deactivation of previous configuration *****************/ + if (IOM_cfg[instance].ClkPort != 0) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + } + + /********************* Deactivation of other instance *********************/ + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || + (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1)], OCTOSPIM_PCR_CLKEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1)], OCTOSPIM_PCR_DQSEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1)], OCTOSPIM_PCR_NCSEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort&0xF)-1)], OCTOSPIM_PCR_IOLEN); + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort&0xF)-1)], OCTOSPIM_PCR_IOHEN); + } + + /******************** Activation of new configuration *********************/ + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); + + if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + } + if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOLSRC_1)))); + } + else + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort&0xF)-1)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << POSITION_VAL(OCTOSPIM_PCR_IOHSRC_1)))); + } + + /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ + if ((ospi_enabled & 0x1) != 0) + { + SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); + } + if ((ospi_enabled & 0x2) != 0) + { + SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); + } + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** + @cond 0 + */ +/** + * @brief DMA OSPI process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = 0; + + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Enable the OSPI transfer complete Interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); +} + +/** + * @brief DMA OSPI process half complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = (hospi->XferCount >> 1); + + if (hospi->State == HAL_OSPI_STATE_BUSY_RX) + { + HAL_OSPI_RxHalfCpltCallback(hospi); + } + else + { + HAL_OSPI_TxHalfCpltCallback(hospi); + } +} + +/** + * @brief DMA OSPI communication error callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMAError(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = 0; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + + /* Disable the DMA transfer on the OctoSPI side */ + CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); + + /* Abort the OctoSPI */ + HAL_OSPI_Abort_IT(hospi); +} + +/** + * @brief DMA OSPI abort complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +{ + OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hospi->XferCount = 0; + + /* Check the state */ + if (hospi->State == HAL_OSPI_STATE_ABORT) + { + /* DMA abort called by OctoSPI abort */ + /* Clear transfer complete flag */ + __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); + + /* Perform an abort of the OctoSPI */ + SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); + } + else + { + /* DMA abort called due to a transfer error interrupt */ + /* Update state */ + hospi->State = HAL_OSPI_STATE_READY; + + /* Error callback */ + HAL_OSPI_ErrorCallback(hospi); + } +} + +/** + * @brief Wait for a flag state until timeout. + * @param hospi : OSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout + * @param Tickstart : Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is in expected state */ + while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - Tickstart) > Timeout)) + { + hospi->State = HAL_OSPI_STATE_ERROR; + hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the registers for the regular command mode. + * @param hospi : OSPI handle + * @param cmd : structure that contains the command configuration information + * @retval HAL status + */ +static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg; + + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0); + + /* Configure the flash ID */ + if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) + { + MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FSEL, cmd->FlashId); + } + + if (cmd->OperationType != HAL_OSPI_OPTYPE_WRITE_CFG) + { + ccr_reg = &(hospi->Instance->CCR); + tcr_reg = &(hospi->Instance->TCR); + ir_reg = &(hospi->Instance->IR); + abr_reg = &(hospi->Instance->ABR); + } + else + { + ccr_reg = &(hospi->Instance->WCCR); + tcr_reg = &(hospi->Instance->WTCR); + ir_reg = &(hospi->Instance->WIR); + abr_reg = &(hospi->Instance->WABR); + } + + /* Configure the CCR register with DQS and SIOO modes */ + *ccr_reg = (cmd->DQSMode | cmd->SIOOMode); + + if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) + { + /* Configure the ABR register with alternate bytes value */ + *abr_reg = cmd->AlternateBytes; + + /* Configure the CCR register with alternate bytes communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE), + (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize)); + } + + /* Configure the TCR register with the number of dummy cycles */ + MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles); + + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hospi->Instance->DLR = (cmd->NbData - 1); + } + } + + if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) + { + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + /* ---- Command with instruction, address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | + OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | + OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | + cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | + cmd->DataMode | cmd->DataDtrMode)); + } + else + { + /* ---- Command with instruction and address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | + OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | + cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); + } + } + + /* Configure the IR register with the instruction value */ + *ir_reg = cmd->Instruction; + + /* Configure the AR register with the address value */ + hospi->Instance->AR = cmd->Address; + } + else + { + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + /* ---- Command with instruction and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | + OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | + cmd->DataMode | cmd->DataDtrMode)); + } + else + { + /* ---- Command with only instruction ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE), + (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && + (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); + } + } + + /* Configure the IR register with the instruction value */ + *ir_reg = cmd->Instruction; + + } + } + else + { + if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) + { + if (cmd->DataMode != HAL_OSPI_DATA_NONE) + { + /* ---- Command with address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | + OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), + (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | + cmd->DataMode | cmd->DataDtrMode)); + } + else + { + /* ---- Command with only address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), + (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); + } + + /* Configure the AR register with the instruction value */ + hospi->Instance->AR = cmd->Address; + } + else + { + /* ---- Invalid command configuration (no instruction, no address) ---- */ + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Get the current IOM configuration for an OctoSPI instance. + * @param instance_nb : number of the instance + * @param cfg : configuration of the IO Manager for the instance + * @retval HAL status + */ +static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t reg = 0, value = 0; + uint32_t index = 0; + + if ((instance_nb == 0) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) + { + /* Invalid parameter -> error returned */ + status = HAL_ERROR; + } + else + { + /* Initialize the structure */ + cfg->ClkPort = cfg->DQSPort = cfg->NCSPort = cfg->IOLowPort = cfg->IOHighPort = 0; + + if (instance_nb == 1) + { + value = 0; + } + else if (instance_nb == 2) + { + value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); + } + + /* Get the information about the instance */ + for (index = 0; index < OSPI_IOM_NB_PORTS; index ++) + { + reg = OCTOSPIM->PCR[index]; + + if ((reg & OCTOSPIM_PCR_CLKEN) != 0) + { + /* The clock is enabled on this port */ + if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC)) + { + /* The clock correspond to the instance passed as parameter */ + cfg->ClkPort = index+1; + } + } + + if ((reg & OCTOSPIM_PCR_DQSEN) != 0) + { + /* The DQS is enabled on this port */ + if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC)) + { + /* The DQS correspond to the instance passed as parameter */ + cfg->DQSPort = index+1; + } + } + + if ((reg & OCTOSPIM_PCR_NCSEN) != 0) + { + /* The nCS is enabled on this port */ + if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC)) + { + /* The nCS correspond to the instance passed as parameter */ + cfg->NCSPort = index+1; + } + } + + if ((reg & OCTOSPIM_PCR_IOLEN) != 0) + { + /* The IO Low is enabled on this port */ + if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1)) + { + /* The IO Low correspond to the instance passed as parameter */ + if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0) + { + cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + } + else + { + cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + } + } + } + + if ((reg & OCTOSPIM_PCR_IOHEN) != 0) + { + /* The IO High is enabled on this port */ + if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1)) + { + /* The IO High correspond to the instance passed as parameter */ + if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0) + { + cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1)); + } + else + { + cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1)); + } + } + } + } + } + + /* Return function status */ + return status; +} + +/** + @endcond + */ + +/** + * @} + */ + +#endif /* HAL_OSPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h new file mode 100644 index 0000000000..82eb12e4b2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_ospi.h @@ -0,0 +1,968 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_ospi.h + * @author MCD Application Team + * @brief Header file of OSPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_OSPI_H +#define __STM32L4xx_HAL_OSPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup OSPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup OSPI_Exported_Types OSPI Exported Types + * @{ + */ + +/** + * @brief OSPI Init structure definition + */ +typedef struct +{ + uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the interrupt + indicating that data are available in reception or free place + is available in transmission. + This parameter can be a value between 1 and 32 */ + uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to + quad mode on two different devices to increase the throughput. + This parameter can be a value of @ref OSPI_DualQuad */ + uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. + This parameter can be a value of @ref OSPI_MemoryType */ + uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, + it corresponds to the number of address bits required to access + the external device. + This parameter can be a value between 1 and 32 */ + uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select + must remain high between commands. + This parameter can be a value between 1 and 8 */ + uint32_t FreeRunningClock; /* It enables or not the free running clock. + This parameter can be a value of @ref OSPI_FreeRunningClock */ + uint32_t ClockMode; /* It indicates the level of clock when the chip select is released. + This parameter can be a value of @ref OSPI_ClockMode */ + uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. + This parameter can be a value of @ref OSPI_WrapSize */ + uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating + the external clock based on the AHB clock. + This parameter can be a value between 1 and 256 */ + uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order + to take in account external signal delays. + This parameter can be a value of @ref OSPI_SampleShifting */ + uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. + This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ + uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select. + This parameter can be a value between 0 and 31 */ +}OSPI_InitTypeDef; + +/** + * @brief HAL OSPI Handle Structure definition + */ +typedef struct +{ + OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ + OSPI_InitTypeDef Init; /* OSPI initialization parameters */ + uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */ + __IO uint32_t XferSize; /* Number of data to transfer */ + __IO uint32_t XferCount; /* Counter of data transferred */ + DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */ + __IO uint32_t State; /* Internal state of the OSPI HAL driver */ + __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ + uint32_t Timeout; /* Timeout used for the OSPI external device access */ +}OSPI_HandleTypeDef; + +/** + * @brief HAL OSPI Regular Command Structure definition + */ +typedef struct +{ + uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or + to the registers for the write operation (these registers are only + used for memory-mapped mode). + This parameter can be a value of @ref OSPI_OperationType */ + uint32_t FlashId; /* It indicates which external device is selected for this command (it + applies only if Dualquad is disabled in the initialization structure). + This parameter can be a value of @ref OSPI_FlashId */ + uint32_t Instruction; /* It contains the instruction to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t InstructionMode; /* It indicates the mode of the instruction. + This parameter can be a value of @ref OSPI_InstructionMode */ + uint32_t InstructionSize; /* It indicates the size of the instruction. + This parameter can be a value of @ref OSPI_InstructionSize */ + uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase. + This parameter can be a value of @ref OSPI_InstructionDtrMode */ + uint32_t Address; /* It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressMode; /* It indicates the mode of the address. + This parameter can be a value of @ref OSPI_AddressMode */ + uint32_t AddressSize; /* It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase. + This parameter can be a value of @ref OSPI_AddressDtrMode */ + uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesMode */ + uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesSize */ + uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase. + This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ + uint32_t DataMode; /* It indicates the mode of the data. + This parameter can be a value of @ref OSPI_DataMode */ + uint32_t NbData; /* It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF */ + uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. + This parameter can be a value of @ref OSPI_DataDtrMode */ + uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase. + This parameter can be a value between 0 and 31 */ + uint32_t DQSMode; /* It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ + uint32_t SIOOMode; /* It enables or not the SIOO mode. + This parameter can be a value of @ref OSPI_SIOOMode */ +}OSPI_RegularCmdTypeDef; + +/** + * @brief HAL OSPI Hyperbus Configuration Structure definition + */ +typedef struct +{ + uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. + This parameter can be a value between 0 and 255 */ + uint32_t AccessTime; /* It indicates the number of cycles for the device acces time. + This parameter can be a value between 0 and 255 */ + uint32_t WriteZeroLatency; /* It enables or not the latency for the write access. + This parameter can be a value of @ref OSPI_WriteZeroLatency */ + uint32_t LatencyMode; /* It configures the latency mode. + This parameter can be a value of @ref OSPI_LatencyMode */ +}OSPI_HyperbusCfgTypeDef; + +/** + * @brief HAL OSPI Hyperbus Command Structure definition + */ +typedef struct +{ + uint32_t AddressSpace; /* It indicates the address space accessed by the command. + This parameter can be a value of @ref OSPI_AddressSpace */ + uint32_t Address; /* It contains the address to be sent tot he device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressSize; /* It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t NbData; /* It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF + In case of autopolling mode, this parameter can be any value between 1 and 4 */ + uint32_t DQSMode; /* It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ +}OSPI_HyperbusCmdTypeDef; + +/** + * @brief HAL OSPI Auto Polling mode configuration structure definition + */ +typedef struct +{ + uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t MatchMode; /* Specifies the method used for determining a match. + This parameter can be a value of @ref OSPI_MatchMode */ + uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref OSPI_AutomaticStop */ + uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. + This parameter can be any value between 0 and 0xFFFF */ +}OSPI_AutoPollingTypeDef; + +/** + * @brief HAL OSPI Memory Mapped mode configuration structure definition + */ +typedef struct +{ + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref OSPI_TimeOutActivation */ + uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. + This parameter can be any value between 0 and 0xFFFF */ +}OSPI_MemoryMappedTypeDef; + +/** + * @brief HAL OSPI IO Manager Configuration structure definition + */ +typedef struct +{ + uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins. + This parameter can be a value between 1 and 8 */ + uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin. + This parameter can be a value between 1 and 8 */ + uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin. + This parameter can be a value between 1 and 8 */ + uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. + This parameter can be a value of @ref OSPIM_IOPort */ + uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. + This parameter can be a value of @ref OSPIM_IOPort */ +}OSPIM_CfgTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup OSPI_Exported_Constants OSPI Exported Constants + * @{ + */ + +/** @defgroup OSPI_State OSPI State + * @{ + */ +#define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ +#define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ +#define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ +#define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ +#define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ +#define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ +#define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ +#define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ +#define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ +#define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ +#define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ +#define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ +#define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ +/** + * @} + */ + +/** @defgroup OSPI_ErrorCode OSPI Error Code + * @{ + */ +#define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ +#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ +#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ +#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ +/** + * @} + */ + +/** @defgroup OSPI_DualQuad OSPI Dual-Quad + * @{ + */ +#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ +#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ +/** + * @} + */ + +/** @defgroup OSPI_MemoryType OSPI Memory Type + * @{ + */ +#define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ +#define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ +#define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ +#define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ +/** + * @} + */ + +/** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock + * @{ + */ +#define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ +#define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ +/** + * @} + */ + +/** @defgroup OSPI_ClockMode OSPI Clock Mode + * @{ + */ +#define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ +#define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ +/** + * @} + */ + +/** @defgroup OSPI_WrapSize OSPI Wrap-Size + * @{ + */ +#define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ +#define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ +#define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ +#define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ +#define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ +/** + * @} + */ + +/** @defgroup OSPI_SampleShifting OSPI Sample Shifting + * @{ + */ +#define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ +#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ +/** + * @} + */ + +/** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle + * @{ + */ +#define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ +#define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ +/** + * @} + */ + +/** @defgroup OSPI_OperationType OSPI Operation Type + * @{ + */ +#define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ +#define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ +#define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ +/** + * @} + */ + +/** @defgroup OSPI_FlashID OSPI Flash Id + * @{ + */ +#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ +#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ +/** + * @} + */ + +/** @defgroup OSPI_InstructionMode OSPI Instruction Mode + * @{ + */ +#define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ +#define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ +#define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ +#define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ +#define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_InstructionSize OSPI Instruction Size + * @{ + */ +#define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ +#define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ +#define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ +#define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ +/** + * @} + */ + +/** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode + * @{ + */ +#define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ +#define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ +/** + * @} + */ + +/** @defgroup OSPI_AddressMode OSPI Address Mode + * @{ + */ +#define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ +#define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ +#define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ +#define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ +#define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_AddressSize OSPI Address Size + * @{ + */ +#define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ +#define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ +#define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ +#define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ +/** + * @} + */ + +/** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode + * @{ + */ +#define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ +#define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ +/** + * @} + */ + +/** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode + * @{ + */ +#define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ +#define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ +#define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ +#define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size + * @{ + */ +#define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ +#define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ +/** + * @} + */ + +/** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode + * @{ + */ +#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ +#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ +/** + * @} + */ + +/** @defgroup OSPI_DataMode OSPI Data Mode + * @{ + */ +#define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ +#define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ +#define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ +#define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ +#define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ +/** + * @} + */ + +/** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode + * @{ + */ +#define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ +#define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ +/** + * @} + */ + +/** @defgroup OSPI_DQSMode OSPI DQS Mode + * @{ + */ +#define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ +#define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ +/** + * @} + */ + +/** @defgroup OSPI_SIOOMode OSPI SIOO Mode + * @{ + */ +#define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ +#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ +/** + * @} + */ + +/** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation + * @{ + */ +#define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ +#define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ +/** + * @} + */ + +/** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode + * @{ + */ +#define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ +#define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ +/** + * @} + */ + +/** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space + * @{ + */ +#define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ +#define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ +/** + * @} + */ + +/** @defgroup OSPI_MatchMode OSPI Match Mode + * @{ + */ +#define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ +#define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ +/** + * @} + */ + +/** @defgroup OSPI_AutomaticStop OSPI Automatic Stop + * @{ + */ +#define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ +#define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ +/** + * @} + */ + +/** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation + * @{ + */ +#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ +#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ +/** + * @} + */ + +/** @defgroup OSPI_Flags OSPI Flags + * @{ + */ +#define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ +#define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ +#define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ +#define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ +#define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ +#define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ +/** + * @} + */ + +/** @defgroup OSPI_Interrupts OSPI Interrupts + * @{ + */ +#define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ +#define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ +#define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ +#define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ +#define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ +/** + * @} + */ + +/** @defgroup OSPI_Timeout_definition OSPI Timeout definition + * @{ + */ +#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ +/** + * @} + */ + +/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port + * @{ + */ +#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1)) /*!< Port 1 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */ +#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */ +#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup OSPI_Exported_Macros OSPI Exported Macros + * @{ + */ +/** @brief Reset OSPI handle state. + * @param __HANDLE__: OSPI handle. + * @retval None + */ +#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) + +/** @brief Enable the OSPI peripheral. + * @param __HANDLE__: specifies the OSPI Handle. + * @retval None + */ +#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) + +/** @brief Disable the OSPI peripheral. + * @param __HANDLE__: specifies the OSPI Handle. + * @retval None + */ +#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) + +/** @brief Enable the specified OSPI interrupt. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __INTERRUPT__: specifies the OSPI interrupt source to enable. + * This parameter can be one of the following values: + * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt + * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt + * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt + * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt + * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt + * @retval None + */ +#define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + + +/** @brief Disable the specified OSPI interrupt. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __INTERRUPT__: specifies the OSPI interrupt source to disable. + * This parameter can be one of the following values: + * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt + * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt + * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt + * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt + * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt + * @retval None + */ +#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Check whether the specified OSPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __INTERRUPT__: specifies the OSPI interrupt source to check. + * This parameter can be one of the following values: + * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt + * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt + * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt + * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt + * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Check whether the selected OSPI flag is set or not. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __FLAG__: specifies the OSPI flag to check. + * This parameter can be one of the following values: + * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag + * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag + * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag + * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag + * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag + * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag + * @retval None + */ +#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) + +/** @brief Clears the specified OSPI's flag status. + * @param __HANDLE__: specifies the OSPI Handle. + * @param __FLAG__: specifies the OSPI clear register flag that needs to be set + * This parameter can be one of the following values: + * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag + * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag + * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag + * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag + * @retval None + */ +#define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup OSPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup OSPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup OSPI_Exported_Functions_Group2 + * @{ + */ +/* OSPI IRQ handler function */ +void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); + +/* OSPI command configuration functions */ +HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); + +/* OSPI indirect mode functions */ +HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); + +/* OSPI status flag polling mode functions */ +HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); + +/* OSPI memory-mapped mode functions */ +HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); + +/* Callback functions in non-blocking modes ***********************************/ +void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); + +/* OSPI indirect mode functions */ +void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); +void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); + +/* OSPI status flag polling mode functions */ +void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); + +/* OSPI memory-mapped mode functions */ +void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); + +/** + * @} + */ + +/* Peripheral Control and State functions ************************************/ +/** @addtogroup OSPI_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); +uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); +HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); +uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); +uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); + +/** + * @} + */ + +/* OSPI IO Manager configuration function ************************************/ +/** @addtogroup OSPI_Exported_Functions_Group4 + * @{ + */ +HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** + @cond 0 + */ +#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1) && ((THRESHOLD) <= 32)) + +#define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ + ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) + +#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) + +#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 32)) + +#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1) && ((TIME) <= 8)) + +#define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ + ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) + +#define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ + ((MODE) == HAL_OSPI_CLOCK_MODE_3)) + +#define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ + ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ + ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ + ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ + ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) + +#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 256)) + +#define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ + ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) + +#define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ + ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) + +#define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ + ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ + ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)) + +#define IS_OSPI_FLASH_ID(FLASH) (((FLASH) == HAL_OSPI_FLASH_ID_1) || \ + ((FLASH) == HAL_OSPI_FLASH_ID_2)) + +#define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) + +#define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ + ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ + ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ + ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) + +#define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) + +#define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ + ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ + ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ + ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ + ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) + +#define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ + ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ + ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ + ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) + +#define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) + +#define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) + +#define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ + ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ + ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ + ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) + +#define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) + +#define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ + ((MODE) == HAL_OSPI_DATA_1_LINE) || \ + ((MODE) == HAL_OSPI_DATA_2_LINES) || \ + ((MODE) == HAL_OSPI_DATA_4_LINES) || \ + ((MODE) == HAL_OSPI_DATA_8_LINES)) + +#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1) + +#define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ + ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) + +#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31) + +#define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ + ((MODE) == HAL_OSPI_DQS_ENABLE)) + +#define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ + ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) + +#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255) + +#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255) + +#define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ + ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) + +#define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ + ((MODE) == HAL_OSPI_FIXED_LATENCY)) + +#define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ + ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) + +#define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ + ((MODE) == HAL_OSPI_MATCH_MODE_OR)) + +#define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ + ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) + +#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFF) + +#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) + +#define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) + +#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) + +#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31) + +#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 2)) + +#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ + ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ + ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ + ((PORT) == HAL_OSPIM_IOPORT_2_HIGH)) +/** + @endcond + */ + +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_OSPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c index 34cf7ec987..0d8687fa8e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -87,7 +85,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -1667,7 +1666,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* HAL_PCD_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h index 01be38c5fd..6db33ba463 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -46,7 +44,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_usb.h" @@ -867,7 +866,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c index d90cf064cb..8a3cc9a345 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PCD Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -45,18 +43,20 @@ /** @addtogroup STM32L4xx_HAL_Driver * @{ */ -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) /** @defgroup PCDEx PCDEx * @brief PCD Extended HAL module driver * @{ */ +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ + defined(STM32L452xx) || defined(STM32L462xx) || \ + defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -500,13 +500,6 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m * @} */ -/** - * @} - */ -/** - * @} - */ - /** * @} */ @@ -514,8 +507,17 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h index 45054ab320..f27c8b6a4a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -46,7 +44,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -124,7 +123,8 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c index 0ba3d39d61..3f5877b4d9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h index 7a2b6ae546..f33df34e85 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c index 9280365e54..1c08c0feff 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -63,11 +61,11 @@ #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */ -#elif defined (STM32L496xx) || defined (STM32L4A6xx) +#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */ #endif -#if defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */ #endif @@ -127,11 +125,28 @@ /** * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 + * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) */ uint32_t HAL_PWREx_GetVoltageRange(void) { +#if defined(PWR_CR5_R1MODE) + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + return PWR_REGULATOR_VOLTAGE_SCALE2; + } + else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) + { + /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ + return PWR_REGULATOR_VOLTAGE_SCALE1; + } + else + { + return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; + } +#else return (PWR->CR1 & PWR_CR1_VOS); +#endif } @@ -141,6 +156,11 @@ uint32_t HAL_PWREx_GetVoltageRange(void) * @param VoltageScaling: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: + @if STM32L4S9xx + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, + * typical output voltage at 1.2 V, + * system frequency up to 120 MHz. + @endif * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, * typical output voltage at 1.2 V, * system frequency up to 80 MHz. @@ -150,7 +170,8 @@ uint32_t HAL_PWREx_GetVoltageRange(void) * @note When moving from Range 1 to Range 2, the system frequency must be decreased to * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 2 to Range 1, the system frequency can be increased to - * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For + * some devices, the system frequency can be increased up to 120 MHz. * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. @@ -161,7 +182,76 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) uint32_t wait_loop_index = 0; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + +#if defined(PWR_CR5_R1MODE) + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) + { + /* If current range is range 2 */ + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Make sure Range 1 Boost is enabled */ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); + + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Wait until VOSF is cleared */ + wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); + while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + return HAL_TIMEOUT; + } + } + /* If current range is range 1 normal or boost mode */ + else + { + /* Enable Range 1 Boost (no issue if bit already reset) */ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); + } + } + else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + { + /* If current range is range 2 */ + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) + { + /* Make sure Range 1 Boost is disabled */ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); + + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Wait until VOSF is cleared */ + wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); + while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) + { + wait_loop_index--; + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + return HAL_TIMEOUT; + } + } + /* If current range is range 1 normal or boost mode */ + else + { + /* Disable Range 1 Boost (no issue if bit already set) */ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); + } + } + else + { + /* Set Range 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); + /* No need to wait for VOSF to be cleared for this transition */ + /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ + } +#else + /* If Set Range 1 */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) { @@ -191,6 +281,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* No need to wait for VOSF to be cleared for this transition */ } } +#endif return HAL_OK; } @@ -658,8 +749,52 @@ void HAL_PWREx_DisableSRAM2ContentRetention(void) } +#if defined(PWR_CR1_RRSTP) +/** + * @brief Enable SRAM3 content retention in Stop 2 mode. + * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in + * Stop 2 mode and its content is kept. + * @retval None + */ +void HAL_PWREx_EnableSRAM3ContentRetention(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_RRSTP); +} +/** + * @brief Disable SRAM3 content retention in Stop 2 mode. + * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode + * and its content is lost. + * @retval None + */ +void HAL_PWREx_DisableSRAM3ContentRetention(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); +} +#endif /* PWR_CR1_RRSTP */ + +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins. + * @retval None + */ +void HAL_PWREx_EnableDSIPinsPDActivation(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + + +/** + * @brief Disable pull-down activation on DSI pins. + * @retval None + */ +void HAL_PWREx_DisableDSIPinsPDActivation(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} +#endif /* PWR_CR3_DSIPDEN */ + #if defined(PWR_CR2_PVME1) /** * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h index 8d044036c2..2830478169 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PWR HAL Extended module. ****************************************************************************** * @attention @@ -155,8 +153,11 @@ typedef struct /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale * @{ */ -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ +#if defined(PWR_CR5_R1MODE) +#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */ +#endif +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ /** * @} */ @@ -717,7 +718,8 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN5_LOW)) #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ ((TYPE) == PWR_PVM_2) ||\ ((TYPE) == PWR_PVM_3) ||\ @@ -745,8 +747,15 @@ typedef struct ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) +#if defined(PWR_CR5_R1MODE) +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#else #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#endif + #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) @@ -779,7 +788,8 @@ typedef struct ((GPIO) == PWR_GPIO_F) ||\ ((GPIO) == PWR_GPIO_G) ||\ ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L496xx) || defined (STM32L4A6xx) +#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ ((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_C) ||\ @@ -829,6 +839,14 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void); void HAL_PWREx_DisablePullUpPullDownConfig(void); void HAL_PWREx_EnableSRAM2ContentRetention(void); void HAL_PWREx_DisableSRAM2ContentRetention(void); +#if defined(PWR_CR1_RRSTP) +void HAL_PWREx_EnableSRAM3ContentRetention(void); +void HAL_PWREx_DisableSRAM3ContentRetention(void); +#endif /* PWR_CR1_RRSTP */ +#if defined(PWR_CR3_DSIPDEN) +void HAL_PWREx_EnableDSIPinsPDActivation(void); +void HAL_PWREx_DisableDSIPinsPDActivation(void); +#endif /* PWR_CR3_DSIPDEN */ #if defined(PWR_CR2_PVME1) void HAL_PWREx_EnablePVM1(void); void HAL_PWREx_DisablePVM1(void); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c index 1beb35b41d..27ae77c567 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_qspi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief QSPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI). @@ -168,6 +166,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" +#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -241,7 +241,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -263,9 +263,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) @@ -291,7 +289,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /* Configure QSPI FIFO Threshold */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES))); + ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); @@ -299,21 +297,19 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) if(status == HAL_OK) { /* Configure QSPI Clock Prescaler and Sample Shift */ -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), - ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) | + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); #else MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), - ((hqspi->Init.ClockPrescaler << POSITION_VAL(QUADSPI_CR_PRESCALER)) | + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | hqspi->Init.SampleShifting)); #endif /* Configure QSPI Flash Size, CS High Time and Clock Mode */ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << POSITION_VAL(QUADSPI_DCR_FSIZE)) | + ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); /* Enable the QSPI peripheral */ @@ -335,7 +331,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -369,10 +365,10 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ -__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) + __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -384,10 +380,10 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ -__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) + __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -423,7 +419,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -433,7 +429,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if((flag & QSPI_FLAG_FT) && (itsource & QSPI_IT_FT)) + if(((flag & QSPI_FLAG_FT) != 0) && ((itsource & QSPI_IT_FT) !=0 )) { data_reg = &hqspi->Instance->DR; @@ -445,7 +441,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->TxXferCount > 0) { /* Fill the FIFO until the threshold is reached */ - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } else @@ -465,7 +461,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0) { /* Read the FIFO until the threshold is reached */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); hqspi->RxXferCount--; } else @@ -483,7 +479,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if((flag & QSPI_FLAG_TC) && (itsource & QSPI_IT_TC)) + else if(((flag & QSPI_FLAG_TC) != 0) && ((itsource & QSPI_IT_TC) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); @@ -494,7 +490,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -516,7 +512,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -532,7 +528,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); hqspi->RxXferCount--; } else @@ -547,7 +543,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ HAL_QSPI_Abort_IT(hqspi); #endif - + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -585,7 +581,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if((flag & QSPI_FLAG_SM) && (itsource & QSPI_IT_SM)) + else if(((flag & QSPI_FLAG_SM) != 0) && ((itsource & QSPI_IT_SM) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); @@ -605,7 +601,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if((flag & QSPI_FLAG_TE) && (itsource & QSPI_IT_TE)) + else if(((flag & QSPI_FLAG_TE) != 0) && ((itsource & QSPI_IT_TE) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); @@ -616,7 +612,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -629,14 +625,14 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; - + /* Error callback */ HAL_QSPI_ErrorCallback(hqspi); } } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if((flag & QSPI_FLAG_TO) && (itsource & QSPI_IT_TO)) + else if(((flag & QSPI_FLAG_TO) != 0) && ((itsource & QSPI_IT_TO) != 0)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); @@ -648,7 +644,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration * @note This function is used only in Indirect Read or Write Modes @@ -738,7 +734,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status @@ -826,19 +822,19 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp else { status = HAL_BUSY; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } - + /* Return function status */ return status; } /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status @@ -855,7 +851,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - + if(pData != NULL ) { /* Update state */ @@ -879,7 +875,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u break; } - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + *(__IO uint8_t *)((__IO void *)data_reg) = *hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -923,8 +919,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status @@ -969,7 +965,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui break; } - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)((__IO void *)data_reg); hqspi->RxXferCount--; } @@ -979,7 +975,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); if (status == HAL_OK) - { + { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); @@ -1012,8 +1008,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1072,8 +1068,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1136,8 +1132,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1174,7 +1170,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1205,43 +1201,43 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - + /* Configure size and pointer of the handle */ hqspi->TxXferSize = hqspi->TxXferCount; hqspi->pTxBuffPtr = pData; - + /* Configure QSPI: CCR register with functional mode as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - + /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); - + /* Enable the QSPI transmit DMA Channel */ - tmp = (uint32_t*)&pData; + tmp = (uint32_t*)((void*)&pData); HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } @@ -1250,7 +1246,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat { hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1258,18 +1254,18 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat else { status = HAL_BUSY; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } - + return status; } /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1292,7 +1288,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - if(pData != NULL) + if(pData != NULL ) { /* Configure counters of the handle */ if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) @@ -1324,7 +1320,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1338,46 +1334,46 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - + /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - + /* Configure size and pointer of the handle */ hqspi->RxXferSize = hqspi->RxXferCount; hqspi->pRxBuffPtr = pData; - + /* Set the QSPI DMA transfer complete callback */ hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; - + /* Set the QSPI DMA Half transfer complete callback */ hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; - + /* Set the DMA error callback */ hqspi->hdma->XferErrorCallback = QSPI_DMAError; - + /* Clear the DMA abort callback */ hqspi->hdma->XferAbortCallback = NULL; - + /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); - + /* Enable the DMA Channel */ - tmp = (uint32_t*)&pData; + tmp = (uint32_t*)((void*)&pData); HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); - + /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - + /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - + /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } @@ -1404,9 +1400,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @param Timeout : Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status @@ -1505,9 +1501,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1598,7 +1594,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman else { status = HAL_BUSY; - + /* Process unlocked */ __HAL_UNLOCK(hqspi); } @@ -1609,9 +1605,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the memory mapped configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1664,9 +1660,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT if (status == HAL_OK) { /* Configure QSPI: CR register with timeout counter enable */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) + if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); @@ -1698,7 +1694,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1713,7 +1709,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1728,7 +1724,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1743,7 +1739,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1758,7 +1754,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1773,7 +1769,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1788,10 +1784,10 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ -__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) + __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -1803,7 +1799,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1818,7 +1814,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1833,7 +1829,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1870,7 +1866,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI handle state. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -1881,7 +1877,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -1891,7 +1887,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -1905,11 +1901,11 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Process unlocked */ __HAL_UNLOCK(hqspi); - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Abort DMA channel */ status = HAL_DMA_Abort(hqspi->hdma); if(status != HAL_OK) @@ -1917,21 +1913,21 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; } } - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - + /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if(status == HAL_OK) - { + if (status == HAL_OK) + { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Wait until BUSY flag is reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); } - + if (status == HAL_OK) { /* Update state */ @@ -1944,7 +1940,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -1956,18 +1952,18 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Update QSPI state */ hqspi->State = HAL_QSPI_STATE_ABORT; - + /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - - if (hqspi->Instance->CR & QUADSPI_CR_DMAEN) + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - + /* Abort DMA channel */ hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; HAL_DMA_Abort_IT(hqspi->hdma); @@ -1976,10 +1972,10 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) { /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - + /* Enable the QSPI Transfer Complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - + /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } @@ -1988,8 +1984,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } /** @brief Set QSPI timeout. - * @param hqspi: QSPI handle. - * @param Timeout: Timeout for the QSPI memory access. + * @param hqspi : QSPI handle. + * @param Timeout : Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -1998,8 +1994,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @param Threshold: Threshold of the Fifo (value between 1 and 16). + * @param hqspi : QSPI handle. + * @param Threshold : Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2016,7 +2012,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t /* Configure QSPI FIFO Threshold */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES))); + ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); } else { @@ -2031,12 +2027,12 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi: QSPI handle. + * @param hqspi : QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) { - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1); + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1); } /** @@ -2045,7 +2041,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) /** * @brief DMA QSPI receive process complete callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2059,7 +2055,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2097,7 +2093,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2117,7 +2113,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma: DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2144,25 +2140,26 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /* DMA Abort called due to a transfer error interrupt */ /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; - + /* Error callback */ HAL_QSPI_ErrorCallback(hqspi); } } + /** * @brief Wait for a flag state until timeout. - * @param hqspi: QSPI handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param hqspi : QSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is in expected state */ - while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) + while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) @@ -2181,9 +2178,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information - * @param FunctionalMode: functional mode to configured + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param FunctionalMode : functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2213,7 +2210,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction, address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); @@ -2229,7 +2226,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); @@ -2242,7 +2239,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); @@ -2257,7 +2254,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only instruction ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } @@ -2275,7 +2272,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); @@ -2291,7 +2288,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } @@ -2303,7 +2300,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); @@ -2320,7 +2317,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << POSITION_VAL(QUADSPI_CCR_DCYC)) | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } @@ -2342,4 +2339,6 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h index 9b2e82197d..cef4014d75 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_qspi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -46,6 +44,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) + /** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -81,9 +81,7 @@ typedef struct This parameter can be a value of @ref QSPI_ChipSelectHighTime */ uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ uint32_t DualFlash; /* Specifies the Dual Flash Mode State @@ -206,10 +204,10 @@ typedef struct /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */ /** * @} @@ -248,9 +246,7 @@ typedef struct * @} */ -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) /** @defgroup QSPI_Flash_Select QSPI Flash Select * @{ */ @@ -328,7 +324,7 @@ typedef struct /** @defgroup QSPI_DataMode QSPI Data Mode * @{ */ -#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!State = HAL_QSPI_STATE_RESET) /** @brief Enable the QSPI peripheral. - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) @@ -507,7 +501,7 @@ typedef struct * @arg QSPI_FLAG_TE: QSPI Transfer error flag * @retval None */ -#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) +#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. * @param __HANDLE__: specifies the QSPI Handle. @@ -611,9 +605,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ ((CLKMODE) == QSPI_CLOCK_MODE_3)) -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CR_DFM) #define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \ ((FLASH) == QSPI_FLASH_ID_2)) @@ -658,9 +650,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \ - defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) +#if defined(QUADSPI_CCR_DHHC) #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) #else @@ -696,7 +686,9 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); /** * @} */ - + +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c index 4835c433d3..50e2470772 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -87,12 +85,12 @@ * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */ +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /** * @} */ @@ -106,25 +104,21 @@ #define MCO1_PIN GPIO_PIN_8 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ - (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) /** * @} */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ - -/** - * @} - */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCC_Private_Functions RCC Private Functions * @{ */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +static uint32_t RCC_GetSysClockFreqFromPLLSource(void); +#endif /** * @} */ @@ -150,11 +144,11 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); [..] Internal/external clock and PLL configuration (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. - + (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. It can be used to generate the clock for the USB OTG FS (48 MHz). - The number of flash wait states is automatically adjusted when MSI range is updated with - HAL_RCC_OscConfig() and the MSI is used as System clock source. + The number of flash wait states is automatically adjusted when MSI range is updated with + HAL_RCC_OscConfig() and the MSI is used as System clock source. (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC clock source. @@ -212,21 +206,41 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz - to work correctly, while the SDMMC1 and RNG peripherals require a frequency + to work correctly, while the SDMMC1 and RNG peripherals require a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1 - through PLLQ divider. You have to enable the peripheral clock and use + through PLLQ divider. You have to enable the peripheral clock and use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) IWDG clock which is always the LSI clock. - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. The clock source frequency should be adapted depending on the device voltage range as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. @endverbatim - - Table 1. HCLK clock frequency. - +-------------------------------------------------------+ + + Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices + +--------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |--------------------------------------| + | | voltage range 1 | voltage range 2 | + | | 1.2 V | 1.0 V | + |-----------------|-------------------|------------------| + |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | + |-----------------|-------------------|------------------| + |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | + |-----------------|-------------------|------------------| + |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | + |-----------------|-------------------|------------------| + |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | + |-----------------|-------------------|------------------| + |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | + |-----------------|-------------------|------------------| + |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | + +--------------------------------------------------------+ + + Table 2. HCLK clock frequency for other STM32L4 devices + +-------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |-------------------------------------| | | voltage range 1 | voltage range 2 | @@ -253,28 +267,63 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 OFF * - All interrupts disabled + * - All interrupt and reset flags cleared * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks - * @retval None + * @retval HAL status */ -void HAL_RCC_DeInit(void) +HAL_StatusTypeDef HAL_RCC_DeInit(void) { + uint32_t tickstart = 0; + /* Set MSION bit */ SET_BIT(RCC->CR, RCC_CR_MSION); /* Insure MSIRDY bit is set before writing default MSIRANGE value */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); } - + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Set MSIRANGE default value */ MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6); - + /* Reset CFGR register (MSI is selected as system clock source) */ CLEAR_REG(RCC->CFGR); + /* Update the SystemCoreClock global variable for MSI as system clock source */ + SystemCoreClock = MSI_VALUE; + + /* Configure the source of time base considering new system clock settings */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Insure MSI selected as system clock source */ + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till system clock source is ready */ + while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */ #if defined(RCC_PLLSAI2_SUPPORT) - + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); #else @@ -282,7 +331,27 @@ void HAL_RCC_DeInit(void) CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); #endif /* RCC_PLLSAI2_SUPPORT */ - + + /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ + /* Get start tick */ + tickstart = HAL_GetTick(); + +#if defined(RCC_PLLSAI2_SUPPORT) + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + +#else + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) + +#endif + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset PLLCFGR register */ CLEAR_REG(RCC->PLLCFGR); SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 ); @@ -292,11 +361,11 @@ void HAL_RCC_DeInit(void) SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 ); #if defined(RCC_PLLSAI2_SUPPORT) - + /* Reset PLLSAI2CFGR register */ CLEAR_REG(RCC->PLLSAI2CFGR); SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 ); - + #endif /* RCC_PLLSAI2_SUPPORT */ /* Reset HSEBYP bit */ @@ -305,8 +374,13 @@ void HAL_RCC_DeInit(void) /* Disable all interrupts */ CLEAR_REG(RCC->CIER); - /* Update the SystemCoreClock global variable */ - SystemCoreClock = MSI_VALUE; + /* Clear all interrupt flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Clear all reset flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + return HAL_OK; } /** @@ -378,12 +452,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) { return HAL_ERROR; - } + } } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; - + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); } @@ -439,7 +513,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) @@ -490,7 +564,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) { @@ -594,7 +668,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { FlagStatus pwrclkchanged = RESET; - + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); @@ -605,12 +679,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } - + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); @@ -774,14 +848,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable all PLL outputs to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) #endif /* RCC_PLLSAI2_SUPPORT */ ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); #else @@ -845,6 +919,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles + @if STM32L4S9xx + * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles + * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles + * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles + * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles + * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles + * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles + * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles + * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles + * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles + * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles + * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles + @endif * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function @@ -854,7 +941,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * the MSI frequency is set to its default value 4 MHz. * * @note The HSI can be selected as system clock source after - * from STOP modes or in case of failure of the HSE used directly or indirectly + * from STOP modes or in case of failure of the HSE used directly or indirectly * as system clock (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target @@ -873,6 +960,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t pllfreq = 0; + uint32_t hpre = RCC_SYSCLK_DIV1; +#endif /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); @@ -884,83 +975,97 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency > READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } } - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) - { - return HAL_ERROR; - } - } /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) { return HAL_ERROR; } - } - /* MSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - /* Check the MSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ + /* Compute target PLL output frequency */ + pllfreq = RCC_GetSysClockFreqFromPLLSource(); + + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ + if((pllfreq > 80000000U) && + (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) + || + ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) { - return HAL_ERROR; + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; } +#endif } - /* HSI is selected as System Clock Source */ else { - /* Check the HSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - return HAL_ERROR; + /* Check the HSE ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) + { + return HAL_ERROR; + } } + /* MSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + { + /* Check the MSI ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ + pllfreq = HAL_RCC_GetSysClockFreq(); + + /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ + if(pllfreq > 80000000U) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); + hpre = RCC_SYSCLK_DIV2; + } +#endif + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick*/ tickstart = HAL_GetTick(); - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) { @@ -970,42 +1075,72 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } } } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } else { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } } } - + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else + { + /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ + if(hpre == RCC_SYSCLK_DIV2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); + } + } +#endif + /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency < READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } } - + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { @@ -1021,7 +1156,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -1033,7 +1168,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim @@ -1042,7 +1177,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui =============================================================================== [..] This subsection provides a set of functions allowing to: - + (+) Ouput clock to MCO pin. (+) Retrieve current clock frequencies. (+) Enable the Clock Security System. @@ -1147,11 +1282,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* Get SYSCLK source */ if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE); + msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } else { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE); + msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; @@ -1180,25 +1315,25 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ; + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: - pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); + pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U; + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; } @@ -1227,7 +1362,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); } /** @@ -1239,7 +1374,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); } /** @@ -1264,11 +1399,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #endif /* RCC_HSI48_SUPPORT */ /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } - else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -1278,7 +1413,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the MSI configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION) + if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION) { RCC_OscInitStruct->MSIState = RCC_MSI_ON; } @@ -1287,11 +1422,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->MSIState = RCC_MSI_OFF; } - RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM)); - RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) ); + RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos; + RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } @@ -1300,14 +1435,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM)); + RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } - else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } @@ -1317,7 +1452,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } @@ -1328,7 +1463,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #if defined(RCC_HSI48_SUPPORT) /* Get the HSI48 configuration ---------------------------------------------*/ - if((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) + if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) { RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; } @@ -1341,7 +1476,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #endif /* RCC_HSI48_SUPPORT */ /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -1349,15 +1484,15 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U); - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); #if defined(RCC_PLLP_DIV_2_31_SUPPORT) - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV)); + RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; #else - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET) + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) { RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17; } @@ -1386,19 +1521,19 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + *pFLatency = READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY); } /** @@ -1458,7 +1593,7 @@ __weak void HAL_RCC_CSSCallback(void) * @{ */ /** - * @brief Update number of Flash wait states in line with MSI range and current + * @brief Update number of Flash wait states in line with MSI range and current voltage range. * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 * @retval HAL status @@ -1467,7 +1602,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) { uint32_t vos = 0; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) { vos = HAL_PWREx_GetVoltageRange(); @@ -1478,7 +1613,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) vos = HAL_PWREx_GetVoltageRange(); __HAL_RCC_PWR_CLK_DISABLE(); } - + if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) { if(msirange > RCC_MSIRANGE_8) @@ -1499,6 +1634,22 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) } else { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(msirange >= RCC_MSIRANGE_8) + { + /* MSI >= 16Mhz */ + latency = FLASH_LATENCY_2; /* 2WS */ + } + else + { + if(msirange == RCC_MSIRANGE_7) + { + /* MSI 8Mhz */ + latency = FLASH_LATENCY_1; /* 1WS */ + } + /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ + } +#else if(msirange > RCC_MSIRANGE_8) { /* MSI > 16Mhz */ @@ -1511,27 +1662,82 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) /* MSI 16Mhz */ latency = FLASH_LATENCY_2; /* 2WS */ } - else if(msirange == RCC_MSIRANGE_7) + else if(msirange == RCC_MSIRANGE_7) { /* MSI 8Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ } /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ } +#endif } - + __HAL_FLASH_SET_LATENCY(latency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != latency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != latency) { return HAL_ERROR; } - + return HAL_OK; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Compute SYSCLK frequency based on PLL SYSCLK source. + * @retval SYSCLK frequency + */ +static uint32_t RCC_GetSysClockFreqFromPLLSource(void) +{ + uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; + uint32_t sysclockfreq = 0U; + + if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) + { + /* Get MSI range source */ + if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) + { /* MSISRANGE from RCC_CSR applies */ + msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + } + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + } + + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; + sysclockfreq = pllvco/pllr; + + return sysclockfreq; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h index 709970c95b..9c8014cdef 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -71,7 +69,8 @@ typedef struct This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. + This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ @@ -121,7 +120,7 @@ typedef struct uint32_t MSIClockRange; /*!< The MSI frequency range. This parameter can be a value of @ref RCC_MSI_Clock_Range */ - uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L45x/STM32L46x/STM32L49x/STM32L4Ax devices). + uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). This parameter can be a value of @ref RCC_HSI48_Config */ RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ @@ -162,7 +161,7 @@ typedef struct /** @defgroup RCC_Timeout_Value Timeout Values * @{ */ -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /** * @} @@ -171,14 +170,14 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */ -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */ -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */ -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */ -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */ -#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */ +#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -187,9 +186,9 @@ typedef struct /** @defgroup RCC_HSE_Config HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */ -#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ /** * @} */ @@ -197,9 +196,9 @@ typedef struct /** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ /** * @} */ @@ -207,14 +206,14 @@ typedef struct /** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ #else -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /** @@ -224,8 +223,8 @@ typedef struct /** @defgroup RCC_LSI_Config LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ @@ -233,10 +232,10 @@ typedef struct /** @defgroup RCC_MSI_Config MSI Config * @{ */ -#define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */ -#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ +#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ +#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ -#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */ +#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ /** * @} */ @@ -245,8 +244,8 @@ typedef struct /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ -#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ -#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ /** * @} */ @@ -254,7 +253,7 @@ typedef struct /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ -#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ /** * @} */ @@ -263,9 +262,9 @@ typedef struct /** @defgroup RCC_PLL_Config PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */ -#define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */ -#define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} */ @@ -274,39 +273,39 @@ typedef struct * @{ */ #if defined(RCC_PLLP_DIV_2_31_SUPPORT) -#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */ -#define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */ -#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */ -#define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */ -#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */ -#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */ -#define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */ -#define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */ -#define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */ -#define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */ -#define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */ -#define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */ -#define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */ -#define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */ -#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ -#define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */ -#define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */ -#define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */ -#define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */ -#define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */ -#define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */ -#define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */ -#define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */ -#define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */ -#define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */ -#define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */ -#define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */ -#define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */ -#define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */ +#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ +#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ +#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ +#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ +#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ +#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ +#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ +#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ +#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ +#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ +#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ +#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ +#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ +#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ +#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ +#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ +#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ +#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ +#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ +#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ +#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ +#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ +#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ +#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ +#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ +#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ +#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ +#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ #else -#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ /** * @} @@ -315,10 +314,10 @@ typedef struct /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider * @{ */ -#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */ -#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */ -#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */ -#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */ +#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ +#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ +#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ +#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ /** * @} */ @@ -326,10 +325,10 @@ typedef struct /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider * @{ */ -#define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */ -#define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */ -#define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */ -#define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */ +#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ +#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ +#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ +#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ /** * @} */ @@ -337,7 +336,7 @@ typedef struct /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ -#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ @@ -375,7 +374,14 @@ typedef struct * @{ */ #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +#define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ +#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ +#else +#define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ /** * @} */ @@ -404,10 +410,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} */ @@ -465,10 +471,10 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} */ @@ -476,8 +482,8 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000U) -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ @@ -485,7 +491,7 @@ typedef struct /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source * @{ */ -#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ @@ -503,7 +509,7 @@ typedef struct /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler * @{ */ -#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ +#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ @@ -545,34 +551,34 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */ -#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */ -#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */ +#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ #if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */ +#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ #endif /* RCC_PLLSAI2_SUPPORT */ /* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */ -#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */ -#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */ -#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */ -#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */ -#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ -#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */ -#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ +#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ +#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ #if defined(RCC_HSI48_SUPPORT) /* Flags in the CRRCR register */ -#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */ +#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -581,19 +587,19 @@ typedef struct /** @defgroup RCC_LSEDrive_Config LSE Drive Config * @{ */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ /** * @} */ -/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock +/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock * @{ */ -#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */ -#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ /** * @} */ @@ -632,6 +638,16 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ @@ -655,7 +671,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ UNUSED(tmpreg); \ } while(0) - + #if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -664,13 +680,27 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ UNUSED(tmpreg); \ } while(0) -#endif /* DMA2D */ +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) @@ -679,7 +709,11 @@ typedef struct #if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) -#endif /* DMA2D */ +#endif /* DMA2D */ + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) +#endif /* GFXMMU */ /** * @} @@ -800,7 +834,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* DCMI */ #if defined(AES) @@ -820,7 +854,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* HASH */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ @@ -831,6 +865,26 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ + #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) @@ -880,6 +934,14 @@ typedef struct #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) +#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ + /** * @} */ @@ -912,6 +974,26 @@ typedef struct } while(0) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) #endif /* FMC_BANK1 */ @@ -920,6 +1002,14 @@ typedef struct #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) +#endif /* OCTOSPI2 */ + /** * @} */ @@ -1123,7 +1213,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ UNUSED(tmpreg); \ } while(0) - + #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1319,7 +1409,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ @@ -1327,7 +1417,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ UNUSED(tmpreg); \ } while(0) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1418,12 +1508,32 @@ typedef struct } while(0) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1453,6 +1563,14 @@ typedef struct #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) +#endif /* DSI */ + /** * @} */ @@ -1469,6 +1587,10 @@ typedef struct #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) @@ -1479,11 +1601,19 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) +#endif /* GFXMMU */ + #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) @@ -1494,6 +1624,10 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) +#endif /* GFXMMU */ + /** * @} */ @@ -1508,7 +1642,7 @@ typedef struct #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) @@ -1840,9 +1974,9 @@ typedef struct #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) @@ -1872,12 +2006,20 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) @@ -1907,6 +2049,14 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) +#endif /* DSI */ + /** * @} */ @@ -1921,6 +2071,10 @@ typedef struct #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) @@ -1931,6 +2085,10 @@ typedef struct #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) @@ -1938,6 +2096,10 @@ typedef struct #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) @@ -1948,6 +2110,10 @@ typedef struct #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) +#endif /* GFXMMU */ + /** * @} */ @@ -2006,6 +2172,14 @@ typedef struct #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) +#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ + #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) @@ -2057,6 +2231,14 @@ typedef struct #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) +#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ + /** * @} */ @@ -2075,6 +2257,14 @@ typedef struct #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) +#endif /* OCTOSPI2 */ + #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) #if defined(FMC_BANK1) @@ -2085,6 +2275,14 @@ typedef struct #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) +#endif /* OCTOSPI2 */ + /** * @} */ @@ -2278,9 +2476,9 @@ typedef struct #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) @@ -2310,14 +2508,22 @@ typedef struct #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) +#endif /* DSI */ + #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) @@ -2347,6 +2553,14 @@ typedef struct #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) +#endif /* DSI */ + /** * @} */ @@ -2364,6 +2578,10 @@ typedef struct #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) @@ -2376,11 +2594,19 @@ typedef struct #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) @@ -2393,6 +2619,10 @@ typedef struct #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) +#endif /* GFXMMU */ + /** * @} */ @@ -2436,6 +2666,10 @@ typedef struct #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) #endif /* USB_OTG_FS */ @@ -2456,6 +2690,14 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) @@ -2487,6 +2729,10 @@ typedef struct #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) #endif /* USB_OTG_FS */ @@ -2507,6 +2753,14 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + /** * @} */ @@ -2524,6 +2778,14 @@ typedef struct #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ @@ -2532,6 +2794,14 @@ typedef struct #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ @@ -2745,9 +3015,9 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) @@ -2777,12 +3047,20 @@ typedef struct #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) @@ -2812,6 +3090,14 @@ typedef struct #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) +#endif /* DSI */ + /** * @} */ @@ -2829,6 +3115,10 @@ typedef struct #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) @@ -2841,11 +3131,19 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) +#endif /* GFXMMU */ + #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) +#if defined(DMAMUX1) +#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) +#endif /* DMAMUX1 */ + #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) @@ -2858,6 +3156,10 @@ typedef struct #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) #endif /* DMA2D */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) +#endif /* GFXMMU */ + /** * @} */ @@ -2901,6 +3203,10 @@ typedef struct #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) #endif /* USB_OTG_FS */ @@ -2921,6 +3227,14 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) @@ -2952,6 +3266,10 @@ typedef struct #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) +#if defined(SRAM3) +#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) +#endif /* SRAM3 */ + #if defined(USB_OTG_FS) #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) #endif /* USB_OTG_FS */ @@ -2972,6 +3290,14 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) +#if defined(OCTOSPIM) +#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) +#endif /* OCTOSPIM */ + +#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) +#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ + /** * @} */ @@ -2989,14 +3315,31 @@ typedef struct #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) #endif /* FMC_BANK1 */ + #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) #endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) +#endif /* OCTOSPI1 */ + +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) +#endif /* OCTOSPI2 */ + #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) #endif /* FMC_BANK1 */ @@ -3210,9 +3553,9 @@ typedef struct #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) @@ -3242,12 +3585,20 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) +#endif /* DSI */ + #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) @@ -3277,13 +3628,21 @@ typedef struct #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) +#endif /* DSI */ + /** * @} */ /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset - * @{ - */ + * @{ + */ /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) @@ -3300,8 +3659,8 @@ typedef struct */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable or disable the RTC clock. * @note As the RTC is in the Backup domain and write access is denied to @@ -3342,13 +3701,13 @@ typedef struct /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). * @retval None */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM)) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) /** * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) @@ -3400,13 +3759,13 @@ typedef struct * and temperature that influence the frequency of the internal MSI RC. * Refer to the Application Note AN3300 for more details on how to * calibrate the MSI. - * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value + * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_MSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 255. * @retval None */ #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode @@ -3418,7 +3777,7 @@ typedef struct * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready * (MSIRDY=1). * @note The MSI clock range after reset can be modified on the fly. - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * @param __MSIRANGEVALUE__ specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz @@ -3443,7 +3802,7 @@ typedef struct /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * @param __MSIRANGEVALUE__ specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz @@ -3472,8 +3831,8 @@ typedef struct */ #define __HAL_RCC_GET_MSI_RANGE() \ ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ - (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ - (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) + READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ + READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on @@ -3503,7 +3862,7 @@ typedef struct * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. - * @param __STATE__: specifies the new state of the HSE. + * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. @@ -3532,8 +3891,8 @@ typedef struct /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE @@ -3541,7 +3900,7 @@ typedef struct * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. + * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. @@ -3591,9 +3950,9 @@ typedef struct * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * - * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected @@ -3612,12 +3971,12 @@ typedef struct /** @brief Macro to get the RTC clock source. * @retval The returned value can be one of the following: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected */ -#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macros to enable or disable the main PLL. * @note After enabling the main PLL, the application software should wait on @@ -3633,7 +3992,7 @@ typedef struct /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry @@ -3641,20 +4000,21 @@ typedef struct * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). * @retval None - * + * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL source division factor M. * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 1 and Max_Data = 8. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. + * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. * @retval None - * + * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) @@ -3663,7 +4023,7 @@ typedef struct * @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry @@ -3671,28 +4031,29 @@ typedef struct * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). * - * @param __PLLM__: specifies the division factor for PLL VCO input clock. - * This parameter must be a number between 1 and 8. + * @param __PLLM__ specifies the division factor for PLL VCO input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. + * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. * - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. * This parameter must be a number between 8 and 86. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 64 and 344 MHz. * - * @param __PLLP__: specifies the division factor for SAI clock. + * @param __PLLP__ specifies the division factor for SAI clock. * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x * else (2 to 31). * - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. * This parameter must be in the range (2, 4, 6 or 8). * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work * correctly. - * @param __PLLR__: specifies the division factor for the main system clock. + * @param __PLLR__ specifies the division factor for the main system clock. * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. * This parameter must be in the range (2, 4, 6 or 8). * @retval None @@ -3701,14 +4062,14 @@ typedef struct #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ - (uint32_t)((__PLLP__) << 27U)) - + (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ + ((uint32_t)(__PLLP__) << 27U)) #else - + #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ - (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) + (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ + (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ + (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ @@ -3720,14 +4081,14 @@ typedef struct * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) /** * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime - * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot + * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot * be stopped if used as System Clock. - * @param __PLLCLOCKOUT__: specifies the PLL clock to be output. + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. * This parameter can be one or a combination of the following values: * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * high-quality audio performance on SAI interface in case. @@ -3742,7 +4103,7 @@ typedef struct /** * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked. + * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. * This parameter can be one of the following values: * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * high-quality audio performance on SAI interface in case. @@ -3755,7 +4116,7 @@ typedef struct /** * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__: specifies the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. @@ -3774,7 +4135,7 @@ typedef struct * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) +#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) /** * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. @@ -3782,7 +4143,7 @@ typedef struct * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). - * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. @@ -3791,11 +4152,11 @@ typedef struct * @retval None */ #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) /** * @brief Macro to configure the wake up from stop clock. - * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. + * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. * This parameter can be one of the following values: * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source @@ -3819,9 +4180,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 @endif @@ -3841,9 +4199,8 @@ typedef struct * @{ */ -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. +/** @brief Enable RCC interrupt(s). + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3857,9 +4214,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif @@ -3867,9 +4221,8 @@ typedef struct */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. +/** @brief Disable RCC interrupt(s). + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3883,9 +4236,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif @@ -3893,9 +4243,8 @@ typedef struct */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) -/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3910,18 +4259,15 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif * @retval None */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) /** @brief Check whether the RCC interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -3936,25 +4282,22 @@ typedef struct @if STM32L443xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 @endif * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. * @retval None */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) +#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) /** @brief Check whether the selected RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready @@ -3965,9 +4308,6 @@ typedef struct @if STM32L443xx * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 @endif - @if STM32L462xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 - @endif @if STM32L4A6xx * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 @endif @@ -3986,18 +4326,16 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #if defined(RCC_HSI48_SUPPORT) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ - ? 1U : 0U) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #else #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ - ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ - ? 1U : 0U) + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #endif /* RCC_HSI48_SUPPORT */ /** @@ -4007,20 +4345,20 @@ typedef struct /** * @} */ - + /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ /* Defines used for Flags */ -#define CR_REG_INDEX ((uint32_t)1U) -#define BDCR_REG_INDEX ((uint32_t)2U) -#define CSR_REG_INDEX ((uint32_t)3U) +#define CR_REG_INDEX 1U +#define BDCR_REG_INDEX 2U +#define CSR_REG_INDEX 3U #if defined(RCC_HSI48_SUPPORT) -#define CRRCR_REG_INDEX ((uint32_t)4U) +#define CRRCR_REG_INDEX 4U #endif /* RCC_HSI48_SUPPORT */ -#define RCC_FLAG_MASK ((uint32_t)0x1FU) +#define RCC_FLAG_MASK 0x1FU /** * @} */ @@ -4055,13 +4393,13 @@ typedef struct #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM))) +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) -#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) +#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) #if defined(RCC_HSI48_SUPPORT) #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) @@ -4075,7 +4413,11 @@ typedef struct ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#if defined(RCC_PLLM_DIV_1_16_SUPPORT) +#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) +#else #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) +#endif /*RCC_PLLM_DIV_1_16_SUPPORT */ #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -4097,9 +4439,16 @@ typedef struct (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) + (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) +#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ + (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ + (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ + (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ #endif /* RCC_PLLSAI2_SUPPORT */ #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ @@ -4137,7 +4486,7 @@ typedef struct ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) @@ -4194,7 +4543,7 @@ typedef struct */ /* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c index e3f89b1de6..7c31e73fb5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extended peripheral: @@ -60,9 +58,9 @@ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ -#define PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define DIVIDER_P_UPDATE 0U #define DIVIDER_Q_UPDATE 1U @@ -99,7 +97,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim @@ -143,6 +141,9 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) + @endif * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock @@ -154,6 +155,9 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) + @endif * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock @if STM32L443xx * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) @@ -173,12 +177,23 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u @if STM32L486xx * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) @endif @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - @endif * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) + * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) + * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) + * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) + @endif * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. @@ -230,6 +245,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /* RCC_PLLSAI2_SUPPORT */ case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI1 clock source config set later after clock selection check */ break; @@ -279,6 +297,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk break; case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI2 clock source config set later after clock selection check */ break; @@ -304,7 +325,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) { FlagStatus pwrclkchanged = RESET; - + /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); @@ -314,14 +335,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } - + /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while((PWR->CR1 & PWR_CR1_DBP) == RESET) + while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { @@ -331,11 +352,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } if(ret == HAL_OK) - { + { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - - if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection)) + + if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); @@ -362,7 +383,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - + if(ret == HAL_OK) { /* Apply new RTC clock source selection */ @@ -483,7 +504,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } -#if defined(I2C2) +#if defined(I2C2) /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) @@ -507,7 +528,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } -#if defined(I2C4) +#if defined(I2C4) /*-------------------------- I2C4 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) @@ -540,7 +561,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -559,17 +580,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - - if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) + + if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } +#if defined(RCC_CCIPR2_SDMMCSEL) + else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */ + { + /* Enable PLLSAI3CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); + } +#endif else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -595,7 +623,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -612,7 +640,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - + if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) { /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ @@ -631,7 +659,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); - + if(ret != HAL_OK) { /* set overall return value */ @@ -669,8 +697,109 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /*-------------------------- DFSDM1 audio clock source configuration -------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM1 interface audio clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + + /*-------------------------- LTDC clock source configuration --------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + /* Check the parameters */ + assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection)); + + /* Disable the PLLSAI2 */ + __HAL_RCC_PLLSAI2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI2 is ready */ + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if(ret == HAL_OK) + { + /* Configure the LTDC clock source */ + __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); + + /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ + ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); + } + + if(ret != HAL_OK) + { + /* set overall return value */ + status = ret; + } + } + +#endif /* LTDC */ + +#if defined(DSI) + + /*-------------------------- DSI clock source configuration ---------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + /* Check the parameters */ + assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection)); + + /* Configure the DSI clock source */ + __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); + + if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2) + { + /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */ + ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); + + if(ret != HAL_OK) + { + /* set overall return value */ + status = ret; + } + } + } + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + + /*-------------------------- OctoSPIx clock source configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + /* Check the parameters */ + assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection)); + + /* Configure the OctoSPI clock source */ + __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + + if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL) + { + /* Enable PLL48M1CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); + } + } + +#endif /* OCTOSPI1 || OCTOSPI2 */ + return status; } @@ -733,7 +862,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ RCC_PERIPHCLK_RTC ; - + #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ @@ -750,26 +879,61 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ RCC_PERIPHCLK_RTC ; +#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI; + +#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC; + +#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI; + #endif /* STM32L431xx */ /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ - - PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC)); - PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U; - PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)); - PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4U) + 7U; - PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1U) * 2U; - PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1U) * 2U; + + PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; +#else + PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; + PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; + PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; #if defined(RCC_PLLSAI2_SUPPORT) /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; +#else PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M; - PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)); - PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4U) + 7U; - PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1U) * 2U; +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; + PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U; +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U; #endif /* RCC_PLLSAI2_SUPPORT */ @@ -792,7 +956,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the UART5 clock source ----------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); #endif /* UART5 */ - + /* Get the LPUART1 clock source --------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); @@ -853,11 +1017,31 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) #if defined(DFSDM1_Filter0) /* Get the DFSDM1 clock source ---------------------------------------------*/ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Get the DFSDM1 audio clock source ---------------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ + +#if defined(LTDC) + /* Get the LTDC clock source -----------------------------------------------*/ + PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); +#endif /* LTDC */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /* Get the OctoSPIclock source --------------------------------------------*/ + PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 || OCTOSPI2 */ } /** - * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs + * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs * @note Return 0 if peripheral clock identifier not managed by this API * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: @@ -881,6 +1065,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) + @endif * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock @@ -892,6 +1079,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) + @endif * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock @if STM32L443xx * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) @@ -907,16 +1097,28 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock @if STM32L462xx * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - @endif + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + @endif @if STM32L486xx * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) @endif @if STM32L4A6xx * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) - @endif * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + @endif + @if STM32L4S9xx + * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) + * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) + * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) + * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) + * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) + * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) + @endif * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) @@ -946,7 +1148,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { - frequency = HSE_VALUE / 32; + frequency = HSE_VALUE / 32U; } /* Clock not enabled for RTC*/ else @@ -957,7 +1159,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else { /* Other external peripheral clock source than RTC */ - + /* Compute PLL clock input */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ { @@ -998,8 +1200,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllvco = 0U; } +#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U)); + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif switch(PeriphClk) { @@ -1011,7 +1215,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(PeriphClk == RCC_PERIPHCLK_SAI1) { srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - + if(srcclk == RCC_SAI1CLKSOURCE_PIN) { frequency = EXTERNAL_SAI1_CLOCK_VALUE; @@ -1021,14 +1225,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) else /* RCC_PERIPHCLK_SAI2 */ { srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - + if(srcclk == RCC_SAI2CLKSOURCE_PIN) { frequency = EXTERNAL_SAI2_CLOCK_VALUE; } /* Else, PLL clock output to check below */ } - + #else case RCC_PERIPHCLK_SAI1: @@ -1036,14 +1240,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(PeriphClk == RCC_PERIPHCLK_SAI1) { srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); - + if(srcclk == RCC_SAI1CLKSOURCE_PIN) { frequency = EXTERNAL_SAI1_CLOCK_VALUE; } /* Else, PLL clock output to check below */ } - + #endif /* SAI2 */ if(frequency == 0U) @@ -1054,10 +1258,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) { /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN); + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV); -#endif + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) @@ -1076,11 +1280,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV); -#endif + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) @@ -1095,16 +1303,26 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = (pllvco * plln) / pllp; } } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #else if(srcclk == RCC_SAI1CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) { /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN); + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; #if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV); -#endif + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) @@ -1116,7 +1334,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllp = 7U; } } - + frequency = (pllvco * plln) / pllp; } else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) @@ -1128,17 +1346,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* No clock source */ frequency = 0U; - } + } } else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) { if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV); -#endif + pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) @@ -1150,7 +1372,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) pllp = 7U; } } - + frequency = (pllvco * plln) / pllp; } else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) @@ -1162,7 +1384,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* No clock source */ frequency = 0U; - } + } } #endif /* SAI2 */ @@ -1172,8 +1394,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLLSAI2 Source) / PLLSAI2M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#endif /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N); + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; +#endif if(pllp == 0U) { if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) @@ -1198,23 +1427,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } } break; - + #if defined(USB_OTG_FS) || defined(USB) - + case RCC_PERIPHCLK_USB: #endif /* USB_OTG_FS || USB */ case RCC_PERIPHCLK_RNG: -#if defined(SDMMC1) +#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) case RCC_PERIPHCLK_SDMMC1: -#endif /* SDMMC1 */ +#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - + if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) @@ -1231,9 +1460,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else { @@ -1244,9 +1477,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); } else { @@ -1269,11 +1506,109 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } #endif /* RCC_HSI48_SUPPORT */ break; - + +#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) + + case RCC_PERIPHCLK_SDMMC1: + + if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; +#endif + if(pllp == 0U) + { + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) + { + pllp = 17U; + } + else + { + pllp = 7U; + } + } + frequency = (pllvco * plln) / pllp; + } + else + { + frequency = 0U; + } + } + else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ + { + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); + + if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + else + { + frequency = 0U; + } + } + else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); +#endif + /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + } + else + { + frequency = 0U; + } + } + else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) + { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif + /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); + } + else + { + frequency = 0U; + } + } + else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ + { + frequency = HSI48_VALUE; + } + else /* No clock source */ + { + frequency = 0U; + } + } + break; + +#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ + case RCC_PERIPHCLK_USART1: /* Get the current USART1 source */ srcclk = __HAL_RCC_GET_USART1_SOURCE(); - + if(srcclk == RCC_USART1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); @@ -1300,7 +1635,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_USART2: /* Get the current USART2 source */ srcclk = __HAL_RCC_GET_USART2_SOURCE(); - + if(srcclk == RCC_USART2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1329,7 +1664,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_USART3: /* Get the current USART3 source */ srcclk = __HAL_RCC_GET_USART3_SOURCE(); - + if(srcclk == RCC_USART3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1360,7 +1695,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_UART4: /* Get the current UART4 source */ srcclk = __HAL_RCC_GET_UART4_SOURCE(); - + if(srcclk == RCC_UART4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1391,7 +1726,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_UART5: /* Get the current UART5 source */ srcclk = __HAL_RCC_GET_UART5_SOURCE(); - + if(srcclk == RCC_UART5CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1416,11 +1751,11 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; #endif /* UART5 */ - + case RCC_PERIPHCLK_LPUART1: /* Get the current LPUART1 source */ srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - + if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1445,9 +1780,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; case RCC_PERIPHCLK_ADC: - + srcclk = __HAL_RCC_GET_ADC_SOURCE(); - + if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); @@ -1456,9 +1791,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* f(PLLSAI1 Source) / PLLSAI1M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); +#endif /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); } } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) @@ -1466,9 +1805,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* f(PLLSAI2 Source) / PLLSAI2M */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); +#endif /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N); - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U); + plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); } } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ @@ -1484,7 +1827,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_DFSDM1: /* Get the current DFSDM1 source */ srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - + if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); @@ -1495,12 +1838,40 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } break; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + + case RCC_PERIPHCLK_DFSDM1AUDIO: + /* Get the current DFSDM1 audio source */ + srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + + if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) + { + frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); + } + else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for DFSDM1 audio source */ + else + { + frequency = 0U; + } + break; + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ case RCC_PERIPHCLK_I2C1: /* Get the current I2C1 source */ srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - + if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1525,7 +1896,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C2: /* Get the current I2C2 source */ srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - + if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1550,7 +1921,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C3: /* Get the current I2C3 source */ srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - + if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1575,7 +1946,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_I2C4: /* Get the current I2C4 source */ srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - + if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1600,7 +1971,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_LPTIM1: /* Get the current LPTIM1 source */ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - + if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1627,7 +1998,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_LPTIM2: /* Get the current LPTIM2 source */ srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); - + if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1656,7 +2027,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) case RCC_PERIPHCLK_SWPMI1: /* Get the current SWPMI1 source */ srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); - + if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); @@ -1674,6 +2045,45 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) #endif /* SWPMI1 */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + + case RCC_PERIPHCLK_OSPI: + /* Get the current OctoSPI clock source */ + srcclk = __HAL_RCC_GET_OSPI_SOURCE(); + + if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if((srcclk == RCC_OSPICLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) + { + /*MSI frequency range in HZ*/ + frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; + } + else if(srcclk == RCC_OSPICLKSOURCE_PLL) + { + if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) + { + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + } + else + { + frequency = 0U; + } + } + /* Clock not enabled for OctoSPI */ + else + { + frequency = 0U; + } + break; + +#endif /* OCTOSPI1 || OCTOSPI2 */ + default: break; } @@ -1689,12 +2099,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions * -@verbatim +@verbatim =============================================================================== ##### Extended clock management functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the + This subsection provides a set of functions allowing to control the activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS, Low speed clock output and clock after wake-up from STOP mode. @endverbatim @@ -1737,12 +2147,18 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) } } - if(status == HAL_OK) + if(status == HAL_OK) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI1 Multiplication factor N */ + /* Configure the PLLSAI1 Division factors M, P, Q and R */ + __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); +#else /* Configure the PLLSAI1 Multiplication factor N */ /* Configure the PLLSAI1 Division factors P, Q and R */ __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); - /* Configure the PLLSAI1 Clock output(s) */ +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut); /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ @@ -1761,7 +2177,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) } } } - + return status; } @@ -1789,21 +2205,21 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) break; } } - - /* Disable the PLLSAI1 Clock outputs */ + + /* Disable the PLLSAI1 Clock outputs */ __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); /* Reset PLL source to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) #endif /* RCC_PLLSAI2_SUPPORT */ ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + return status; } @@ -1825,6 +2241,9 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M)); assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N)); assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P)); +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q)); +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R)); assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut)); @@ -1844,12 +2263,26 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) } } - if(status == HAL_OK) + if(status == HAL_OK) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) + /* Configure the PLLSAI2 Multiplication factor N */ + /* Configure the PLLSAI2 Division factors M, P, Q and R */ + __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); +#elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI2 Multiplication factor N */ + /* Configure the PLLSAI2 Division factors M, P and R */ + __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); +#elif defined(RCC_PLLSAI2Q_DIV_SUPPORT) + /* Configure the PLLSAI2 Multiplication factor N */ + /* Configure the PLLSAI2 Division factors P, Q and R */ + __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); +#else /* Configure the PLLSAI2 Multiplication factor N */ /* Configure the PLLSAI2 Division factors P and R */ __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); - /* Configure the PLLSAI2 Clock output(s) */ +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ + /* Configure the PLLSAI2 Clock output(s) */ __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut); /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ @@ -1868,7 +2301,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) } } } - + return status; } @@ -1896,19 +2329,23 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) break; } } - - /* Disable the PLLSAI2 Clock outputs */ + + /* Disable the PLLSAI2 Clock outputs */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN); +#else __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN); +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ /* Reset PLL source to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + return status; } @@ -1916,7 +2353,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) /** * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. - * @param WakeUpClk Wakeup clock + * @param WakeUpClk Wakeup clock * This parameter can be one of the following values: * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection @@ -1927,14 +2364,14 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) { assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); - + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); } /** * @brief Configure the MSI range after standby mode. * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param MSIRange MSI range + * @param MSIRange MSI range * This parameter can be one of the following values: * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz @@ -1945,7 +2382,7 @@ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) { assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); - + __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); } @@ -1969,7 +2406,7 @@ void HAL_RCCEx_EnableLSECSS(void) void HAL_RCCEx_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - + /* Disable LSE CSS IT if any */ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } @@ -1986,7 +2423,7 @@ void HAL_RCCEx_EnableLSECSS_IT(void) /* Enable LSE CSS IT */ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); - + /* Enable IT on EXTI Line 19 */ __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); @@ -2007,7 +2444,7 @@ void HAL_RCCEx_LSECSS_IRQHandler(void) /* Clear RCC LSE CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); } -} +} /** * @brief RCCEx LSE Clock Security System interrupt callback. @@ -2033,7 +2470,7 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) GPIO_InitTypeDef GPIO_InitStruct; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; - + /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); @@ -2058,9 +2495,9 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } - + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); - + if(backupchanged == SET) { HAL_PWR_DisableBkUpAccess(); @@ -2079,7 +2516,7 @@ void HAL_RCCEx_DisableLSCO(void) { FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; - + /* Update LSCOEN bit in Backup Domain control register */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { @@ -2092,9 +2529,9 @@ void HAL_RCCEx_DisableLSCO(void) HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } - + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); - + /* Restore previous configuration */ if(backupchanged == SET) { @@ -2134,7 +2571,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) #if defined(CRS) -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions * @verbatim @@ -2152,11 +2589,11 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (##) Prepare synchronization configuration necessary for HSI48 calibration (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. - (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate directly reload value with target and sychronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. - (+++) Configures CRS registers with synchronization configuration + (+++) Configures CRS registers with synchronization configuration (+++) Enables automatic calibration and frequency error counter feature Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be @@ -2168,23 +2605,23 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (+++) Call function HAL_RCCEx_CRSWaitSynchronization() (+++) According to CRS status, user can decide to adjust again the calibration or continue application if synchronization is OK - + (#) User can retrieve information related to synchronization in calling function HAL_RCCEx_CRSGetSynchronizationInfo() (#) Regarding synchronization status and synchronization information, user can try a new calibration in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency is higher (and that the TRIM value should be decremented). - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler (CRS_IRQn/CRS_IRQHandler) (++) Call function HAL_RCCEx_CRSConfig() (++) Enable CRS_IRQn (thanks to NVIC functions) (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from + (++) Implement CRS status management in the following user callbacks called from HAL_RCCEx_CRS_IRQHandler(): (+++) HAL_RCCEx_CRS_SyncOkCallback() (+++) HAL_RCCEx_CRS_SyncWarnCallback() @@ -2193,7 +2630,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) - + @endverbatim * @{ */ @@ -2206,7 +2643,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { uint32_t value = 0; - + /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); @@ -2228,15 +2665,15 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) /* Set the RELOAD[15:0] bits according to ReloadValue value */ value |= pInit->ReloadValue; /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM)); + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); WRITE_REG(CRS->CFGR, value); /* Adjust HSI48 oscillator smooth trimming */ /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM))); - + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + /* START AUTOMATIC SYNCHRONIZATION*/ - + /* Enable Automatic trimming & Frequency error counter */ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); } @@ -2251,7 +2688,7 @@ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) } /** - * @brief Return synchronization info + * @brief Return synchronization info * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure * @retval None */ @@ -2259,18 +2696,18 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo { /* Check the parameter */ assert_param(pSynchroInfo != NULL); - + /* Get the reload value */ - pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - + pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM)); + pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP)); + pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); + pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); } /** @@ -2292,10 +2729,10 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; uint32_t tickstart = 0U; - + /* Get timeout */ tickstart = HAL_GetTick(); - + /* Wait for CRS flag or timeout detection */ do { @@ -2311,51 +2748,51 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { /* CRS SYNC event OK */ crsstatus |= RCC_CRS_SYNCOK; - + /* Clear CRS SYNC event OK bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); } - + /* Check CRS SYNCWARN flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ crsstatus |= RCC_CRS_SYNCWARN; - + /* Clear CRS SYNCWARN bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); } - + /* Check CRS TRIM overflow flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_TRIMOVF; - + /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); } - + /* Check CRS Error flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_SYNCERR; - + /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); } - + /* Check CRS SYNC Missed flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) { /* CRS SYNC Missed */ crsstatus |= RCC_CRS_SYNCMISS; - + /* Clear CRS SYNC Missed bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); } - + /* Check CRS Expected SYNC flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) { @@ -2425,7 +2862,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) /* Clear CRS Error flags */ WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - + /* user error callback */ HAL_RCCEx_CRS_ErrorCallback(crserror); } @@ -2467,7 +2904,7 @@ __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) /** * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. + * @param Error Combination of Error status. * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS @@ -2487,7 +2924,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) /** * @} */ - + #endif /* CRS */ /** @@ -2519,16 +2956,18 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); - + /* Check that PLLSAI1 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) { - /* PLL clock source and divider M already set, check that no request for change */ + /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) - || + || (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M) +#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + || + (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) +#endif ) { status = HAL_ERROR; @@ -2561,14 +3000,19 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u status = HAL_ERROR; break; } - + if(status == HAL_OK) { +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Set PLLSAI1 clock source */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); +#else /* Set PLLSAI1 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM)); + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); +#endif } } - + if(status == HAL_OK) { /* Disable the PLLSAI1 */ @@ -2587,41 +3031,79 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } } - if(status == HAL_OK) + if(status == HAL_OK) { if(Divider == DIVIDER_P_UPDATE) { assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P)); +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + + /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/ +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#else /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - (PllSai1->PLLSAI1P << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); #else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - ((PllSai1->PLLSAI1P >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } else if(Divider == DIVIDER_Q_UPDATE) { assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - (((PllSai1->PLLSAI1Q >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)); +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } else { assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, - (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | - (((PllSai1->PLLSAI1R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))); + MODIFY_REG(RCC->PLLSAI1CFGR, + RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ @@ -2640,14 +3122,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u } } - if(status == HAL_OK) + if(status == HAL_OK) { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); } } } - + return status; } @@ -2674,16 +3156,18 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); - + /* Check that PLLSAI2 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) { - /* PLL clock source and divider M already set, check that no request for change */ + /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) - || + || (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai2->PLLSAI2M) +#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + || + (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) +#endif ) { status = HAL_ERROR; @@ -2716,14 +3200,19 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u status = HAL_ERROR; break; } - + if(status == HAL_OK) { +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Set PLLSAI2 clock source */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source); +#else /* Set PLLSAI2 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM)); + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos); +#endif } } - + if(status == HAL_OK) { /* Disable the PLLSAI2 */ @@ -2742,25 +3231,81 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } } - if(status == HAL_OK) + if(status == HAL_OK) { if(Divider == DIVIDER_P_UPDATE) { assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P)); +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + + /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/ +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#else + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#else /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, - (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | - ((PllSai2->PLLSAI2P >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))); +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); +#else + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)); +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ } +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + else if(Divider == DIVIDER_Q_UPDATE) + { + assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q)); +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#else + /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)); +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + } +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ else { assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R)); +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | + ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); +#else /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, - (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | - (((PllSai2->PLLSAI2R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))); + MODIFY_REG(RCC->PLLSAI2CFGR, + RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, + (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | + (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ } /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ @@ -2779,14 +3324,14 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u } } - if(status == HAL_OK) + if(status == HAL_OK) { /* Configure the PLLSAI2 Clock output(s) */ __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); } } } - + return status; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h index deb2b1c929..b0000a7abe 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RCC HAL Extended module. ****************************************************************************** * @attention @@ -54,7 +52,7 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ @@ -69,8 +67,13 @@ typedef struct uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ +#else uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ +#endif uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86 or 127 depending on devices. */ @@ -99,8 +102,13 @@ typedef struct uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ +#else uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ +#endif uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. This parameter must be a number between 8 and 86 or 127 depending on devices. */ @@ -108,6 +116,11 @@ typedef struct uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. + This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ +#endif + uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ @@ -177,7 +190,7 @@ typedef struct uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - + #if defined(I2C4) uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. @@ -233,16 +246,43 @@ typedef struct uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. + This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + + uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. + This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ + +#endif /* LTDC */ + +#if defined(DSI) + + uint32_t DsiClockSelection; /*!< Specifies DSI clock source. + This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + + uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. + This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ + +#endif + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #if defined(CRS) -/** - * @brief RCC_CRS Init structure definition +/** + * @brief RCC_CRS Init structure definition */ typedef struct { @@ -267,8 +307,8 @@ typedef struct }RCC_CRSInitTypeDef; -/** - * @brief RCC_CRS Synchronization structure definition +/** + * @brief RCC_CRS Synchronization structure definition */ typedef struct { @@ -278,12 +318,12 @@ typedef struct uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x3F */ - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF */ - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ @@ -302,8 +342,8 @@ typedef struct /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source * @{ */ -#define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */ -#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ /** * @} */ @@ -311,46 +351,58 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U) +#define RCC_PERIPHCLK_USART1 0x00000001U +#define RCC_PERIPHCLK_USART2 0x00000002U #if defined(USART3) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U) +#define RCC_PERIPHCLK_USART3 0x00000004U #endif #if defined(UART4) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U) +#define RCC_PERIPHCLK_UART4 0x00000008U #endif #if defined(UART5) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_UART5 0x00000010U #endif -#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_LPUART1 0x00000020U +#define RCC_PERIPHCLK_I2C1 0x00000040U #if defined(I2C2) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_I2C2 0x00000080U #endif -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U) -#define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_I2C3 0x00000100U +#define RCC_PERIPHCLK_LPTIM1 0x00000200U +#define RCC_PERIPHCLK_LPTIM2 0x00000400U +#define RCC_PERIPHCLK_SAI1 0x00000800U #if defined(SAI2) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_SAI2 0x00001000U #endif #if defined(USB_OTG_FS) || defined(USB) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_USB 0x00002000U #endif -#define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_ADC 0x00004000U #if defined(SWPMI1) -#define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_SWPMI1 0x00008000U #endif #if defined(DFSDM1_Filter0) -#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_DFSDM1 0x00010000U +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U) -#define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_RTC 0x00020000U +#define RCC_PERIPHCLK_RNG 0x00040000U #if defined(SDMMC1) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SDMMC1 0x00080000U #endif #if defined(I2C4) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_I2C4 0x00100000U +#endif +#if defined(LTDC) +#define RCC_PERIPHCLK_LTDC 0x00400000U +#endif +#if defined(DSI) +#define RCC_PERIPHCLK_DSI 0x00800000U +#endif +#if defined(OCTOSPI1) || defined(OCTOSPI2) +#define RCC_PERIPHCLK_OSPI 0x01000000U #endif /** * @} @@ -360,7 +412,7 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) @@ -371,7 +423,7 @@ typedef struct /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source * @{ */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) @@ -383,7 +435,7 @@ typedef struct /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source * @{ */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) @@ -396,7 +448,7 @@ typedef struct /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source * @{ */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) @@ -409,7 +461,7 @@ typedef struct /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source * @{ */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) @@ -421,7 +473,7 @@ typedef struct /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source * @{ */ -#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) @@ -432,7 +484,7 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source * @{ */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /** @@ -443,7 +495,7 @@ typedef struct /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source * @{ */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /** @@ -454,34 +506,44 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source * @{ */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 /** * @} */ - + #if defined(I2C4) /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source * @{ */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 /** * @} */ -#endif /* I2C4 */ +#endif /* I2C4 */ /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ -#define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) +#define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 +#else #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* RCC_PLLSAI2_SUPPORT */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 +#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) +#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 +#else #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -490,10 +552,17 @@ typedef struct /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source * @{ */ -#define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) +#define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 +#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 +#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) +#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 +#else #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -502,7 +571,7 @@ typedef struct /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL @@ -513,7 +582,7 @@ typedef struct /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source * @{ */ -#define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL @@ -526,13 +595,16 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ #else -#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ #endif /* RCC_HSI48_SUPPORT */ -#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 -#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 -#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL +#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ +#if defined(RCC_CCIPR2_SDMMCSEL) +#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ +#endif /* RCC_CCIPR2_SDMMCSEL */ /** * @} */ @@ -542,9 +614,9 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_RNGCLKSOURCE_HSI48 0x00000000U #else -#define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_RNGCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 @@ -558,9 +630,9 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_USBCLKSOURCE_HSI48 0x00000000U #else -#define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_USBCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 @@ -573,7 +645,7 @@ typedef struct /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ -#define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_ADCCLKSOURCE_NONE 0x00000000U #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 @@ -587,7 +659,7 @@ typedef struct /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source * @{ */ -#define RCC_SWPMI1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /** * @} @@ -598,13 +670,65 @@ typedef struct /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source * @{ */ -#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL +#else #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U +#define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 +#define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) +/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source + * @{ + */ +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR +/** + * @} + */ +#endif /* LTDC */ + +#if defined(DSI) +/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U +#define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL +/** + * @} + */ +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source + * @{ + */ +#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U +#define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 +#define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 +/** + * @} + */ +#endif /* OCTOSPI1 || OCTOSPI2 */ + /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ */ @@ -618,13 +742,13 @@ typedef struct /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ -#define RCC_CRS_NONE ((uint32_t)0x00000000U) -#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U) -#define RCC_CRS_SYNCOK ((uint32_t)0x00000002U) -#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U) -#define RCC_CRS_SYNCERR ((uint32_t)0x00000008U) -#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U) -#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U) +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U /** * @} */ @@ -632,7 +756,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** @@ -642,7 +766,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -657,8 +781,8 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} */ @@ -666,16 +790,16 @@ typedef struct /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} */ - + /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault * @{ */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ /** * @} */ @@ -683,9 +807,9 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ + corresponds to a higher output frequency */ /** * @} */ @@ -693,8 +817,8 @@ typedef struct /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ /** * @} */ @@ -713,7 +837,7 @@ typedef struct /** * @} */ - + /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags * @{ */ @@ -748,6 +872,11 @@ typedef struct * @note PLLSAI1 clock source is common with the main PLL (configured through * __HAL_RCC_PLL_CONFIG() macro) * + @if STM32L4S9xx + * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + @endif * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. * This parameter must be a number between 8 and 86. * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO @@ -769,24 +898,50 @@ typedef struct * * @retval None */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + +#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ + (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) + +#else + +#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) + +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#else + #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \ - ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))) + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) #else #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \ - (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))) - + WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) + #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /** * @brief Macro to configure the PLLSAI1 clock multiplication factor N. * @@ -803,7 +958,26 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + +/** @brief Macro to configure the PLLSAI1 input clock division factor M. + * + * @note This function must be used only when the PLLSAI1 is disabled. + * @note PLLSAI1 clock source is common with the main PLL (configured through + * __HAL_RCC_PLL_CONFIG() macro) + * + * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + * @retval None + */ + +#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ /** @brief Macro to configure the PLLSAI1 clock division factor P. * @@ -821,12 +995,12 @@ typedef struct #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)) - + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) + #else #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ @@ -843,7 +1017,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /** @brief Macro to configure the PLLSAI1 clock division factor R. * @@ -858,7 +1032,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /** * @brief Macros to enable or disable the PLLSAI1. @@ -910,6 +1084,11 @@ typedef struct * @note PLLSAI2 clock source is common with the main PLL (configured through * __HAL_RCC_PLL_CONFIG() macro) * + @if STM32L4S9xx + * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + @endif * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. * This parameter must be a number between 8 and 86. * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO @@ -920,27 +1099,74 @@ typedef struct * else (2 to 31). * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P * + @if STM32L4S9xx + * @param __PLLSAI2Q__ specifies the division factor for DSI clock. + * This parameter must be in the range (2, 4, 6 or 8). + * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q + * + @endif * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. * This parameter must be in the range (2, 4, 6 or 8). * * @retval None */ -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \ - ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV))) +# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ + (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + +# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ + (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + +# else + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) + +# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ #else +# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) + #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \ - (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))) - -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +# else + +#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ + WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ + ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) + +# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ + +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ /** @@ -959,7 +1185,26 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) + +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + +/** @brief Macro to configure the PLLSAI2 input clock division factor M. + * + * @note This function must be used only when the PLLSAI2 is disabled. + * @note PLLSAI2 clock source is common with the main PLL (configured through + * __HAL_RCC_PLL_CONFIG() macro) + * + * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. + * This parameter must be a number between Min_Data = 1 and Max_Data = 16. + * + * @retval None + */ + +#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ /** @brief Macro to configure the PLLSAI2 clock division factor P. * @@ -974,7 +1219,26 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) + +/** @brief Macro to configure the PLLSAI2 clock division factor Q. + * + * @note This function must be used only when the PLLSAI2 is disabled. + * @note PLLSAI2 clock source is common with the main PLL (configured through + * __HAL_RCC_PLL_CONFIG() macro) + * + * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. + * This parameter must be in the range (2, 4, 6 or 8). + * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q + * + * @retval None + */ +#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ /** @brief Macro to configure the PLLSAI2 clock division factor R. * @@ -989,7 +1253,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /** * @brief Macros to enable or disable the PLLSAI2. @@ -1002,14 +1266,26 @@ typedef struct #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) /** - * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2). + * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). * @note Enabling and disabling those clocks can be done without the need to stop the PLL. * This is mainly used to save Power. * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. * This parameter can be one or a combination of the following values: + @if STM32L486xx * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. + * high-quality audio performance on SAI interface in case. * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4A6xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4S9xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. + @endif * @retval None */ @@ -1018,12 +1294,24 @@ typedef struct #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) /** - * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2). + * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. * This parameter can be one of the following values: + @if STM32L486xx * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. + * high-quality audio performance on SAI interface in case. * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4A6xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. + @endif + @if STM32L4S9xx + * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve + * high-quality audio performance on SAI interface in case. + * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. + @endif * @retval SET / RESET */ #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) @@ -1039,23 +1327,25 @@ typedef struct @if STM32L486xx * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 @endif - @if STM32L4A6xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) + @if STM32L4S9xx + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 + @endif * @if STM32L443xx * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. @endif - @if STM32L462xx - * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. - @endif * * @retval None */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) +#else +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: @@ -1063,17 +1353,18 @@ typedef struct @if STM32L486xx * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 @endif - @if STM32L4A6xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) * - * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 + * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 * clock source when PLLs are disabled for devices without PLLSAI2. * */ -#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) +#else +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined(SAI2) @@ -1086,11 +1377,19 @@ typedef struct * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) + @if STM32L4S9xx + * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 + @endif * * @retval None */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) +#else +#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the SAI2 clock source. * @retval The clock source can be one of the following values: @@ -1099,7 +1398,11 @@ typedef struct * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) */ -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) +#else +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* SAI2 */ @@ -1113,7 +1416,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: @@ -1121,7 +1424,7 @@ typedef struct * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) +#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) #if defined(I2C2) @@ -1135,7 +1438,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: @@ -1143,7 +1446,7 @@ typedef struct * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ -#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) +#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) #endif /* I2C2 */ @@ -1157,7 +1460,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: @@ -1165,7 +1468,7 @@ typedef struct * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ -#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) +#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) #if defined(I2C4) @@ -1179,7 +1482,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) /** @brief Macro to get the I2C4 clock source. * @retval The clock source can be one of the following values: @@ -1187,7 +1490,7 @@ typedef struct * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock */ -#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))) +#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) #endif /* I2C4 */ @@ -1203,7 +1506,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: @@ -1212,7 +1515,7 @@ typedef struct * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) +#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) /** @brief Macro to configure the USART2 clock (USART2CLK). * @@ -1225,7 +1528,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: @@ -1234,7 +1537,7 @@ typedef struct * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) +#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) #if defined(USART3) @@ -1249,7 +1552,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: @@ -1258,7 +1561,7 @@ typedef struct * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) +#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) #endif /* USART3 */ @@ -1275,7 +1578,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) /** @brief Macro to get the UART4 clock source. * @retval The clock source can be one of the following values: @@ -1284,7 +1587,7 @@ typedef struct * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock */ -#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))) +#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) #endif /* UART4 */ @@ -1301,7 +1604,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) /** @brief Macro to get the UART5 clock source. * @retval The clock source can be one of the following values: @@ -1310,7 +1613,7 @@ typedef struct * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock */ -#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))) +#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) #endif /* UART5 */ @@ -1325,7 +1628,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) /** @brief Macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: @@ -1334,7 +1637,7 @@ typedef struct * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) +#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * @@ -1347,7 +1650,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) /** @brief Macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: @@ -1356,7 +1659,7 @@ typedef struct * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). * @@ -1369,7 +1672,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) /** @brief Macro to get the LPTIM2 clock source. * @retval The clock source can be one of the following values: @@ -1378,84 +1681,87 @@ typedef struct * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) +#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) #if defined(SDMMC1) /** @brief Macro to configure the SDMMC1 clock. * - @if STM32L443xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif - @if STM32L462xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif @if STM32L486xx * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. @endif - @if STM32L4A6xx + * + @if STM32L443xx * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. @endif * * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. * This parameter can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock - @endif - @if STM32L462xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock - @endif @if STM32L486xx * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock @endif + @if STM32L4S9xx + * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 + * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock + @endif + * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock * @retval None */ +#if defined(RCC_CCIPR2_SDMMCSEL) #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) + do \ + { \ + if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ + { \ + SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ + } \ + } while(0) +#else +#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) +#endif /* RCC_CCIPR2_SDMMCSEL */ /** @brief Macro to get the SDMMC1 clock. * @retval The clock source can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock - @endif - @if STM32L462xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock - @endif @if STM32L486xx * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock @endif + @if STM32L4S9xx + * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 + * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock + * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock + @endif + * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock */ -#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#if defined(RCC_CCIPR2_SDMMCSEL) +#define __HAL_RCC_GET_SDMMC1_SOURCE() \ + ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#else +#define __HAL_RCC_GET_SDMMC1_SOURCE() \ + (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) +#endif /* RCC_CCIPR2_SDMMCSEL */ #endif /* SDMMC1 */ @@ -1465,16 +1771,10 @@ typedef struct * * @param __RNG_CLKSOURCE__ specifies the RNG clock source. * This parameter can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 @endif * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock @@ -1483,27 +1783,21 @@ typedef struct * @retval None */ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) /** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 @endif * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock */ -#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #if defined(USB_OTG_FS) || defined(USB) @@ -1513,16 +1807,10 @@ typedef struct * * @param __USB_CLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 @endif * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock @@ -1531,27 +1819,21 @@ typedef struct * @retval None */ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - @if STM32L462xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif @if STM32L486xx * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 @endif - @if STM32L4A6xx + @if STM32L443xx * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 @endif * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ -#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #endif /* USB_OTG_FS || USB */ @@ -1563,14 +1845,11 @@ typedef struct @if STM32L486xx * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices @endif - @if STM32L4A6xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock * @retval None */ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: @@ -1579,12 +1858,9 @@ typedef struct @if STM32L486xx * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices @endif - @if STM32L4A6xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock */ -#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) +#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) #if defined(SWPMI1) @@ -1596,14 +1872,14 @@ typedef struct * @retval None */ #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) /** @brief Macro to get the SWPMI1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock */ -#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))) +#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) #endif /* SWPMI1 */ @@ -1615,18 +1891,119 @@ typedef struct * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock * @retval None */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) +#else +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the DFSDM1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock */ -#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) +#else +#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @brief Macro to configure the DFSDM1 audio clock. + * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock + * @retval None + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 audio clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock + * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + +/** @brief Macro to configure the LTDC clock. + * @param __LTDC_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock + * @retval None + */ +#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock + * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock + */ +#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) + +#endif /* LTDC */ + +#if defined(DSI) + +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock + * @retval None + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) + +/** @brief Macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock + * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + +/** @brief Macro to configure the OctoSPI clock. + * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock + * @retval None + */ +#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) + +/** @brief Macro to get the OctoSPI clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock + * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock + */ +#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) + +#endif /* OCTOSPI1 || OCTOSPI2 */ + /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ @@ -1746,8 +2123,8 @@ typedef struct do { \ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - + } while(0) + /** * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. * @retval None. @@ -1756,7 +2133,7 @@ typedef struct do { \ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0) /** * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. @@ -1826,7 +2203,7 @@ typedef struct * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt */ /* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) +#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ @@ -1870,7 +2247,7 @@ typedef struct */ /* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) +#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ @@ -1893,7 +2270,7 @@ typedef struct /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features * @{ - */ + */ /** * @brief Enable the oscillator clock for frequency error counter. * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. @@ -1922,8 +2299,8 @@ typedef struct /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to * reach the expected synchronization on the zero value. The formula is the following: * RELOAD = (fTARGET / fSYNC) -1 * @param __FTARGET__ Target frequency (value in Hz) @@ -2170,6 +2547,87 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) +#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)) + +#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) + +#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)) + #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ @@ -2262,7 +2720,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) - + #if defined(I2C4) #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ @@ -2274,11 +2732,20 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_RCC_SAI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) +#else #define IS_RCC_SAI1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #else @@ -2291,35 +2758,52 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_RCC_SAI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) +#else #define IS_RCC_SAI2CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* RCC_PLLSAI2_SUPPORT */ #define IS_RCC_LPTIM1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) #define IS_RCC_LPTIM2CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) #if defined(SDMMC1) -#if defined(RCC_HSI48_SUPPORT) +#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) + +#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) + +#elif defined(RCC_HSI48_SUPPORT) #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) - #else #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ @@ -2400,11 +2884,51 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #endif /* DFSDM1_Filter0 */ +#if defined(LTDC) + +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) + +#endif /* LTDC */ + +#if defined(DSI) + +#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) + +#endif /* DSI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + +#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) + +#endif /* OCTOSPI1 || OCTOSPI2 */ + #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) +#else #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -2424,7 +2948,11 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) +#else #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -2434,6 +2962,11 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ + ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) @@ -2452,7 +2985,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) - + #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c index 9d94bf1480..469c6af21d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rng.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -122,11 +120,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { return HAL_ERROR; } - - assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); - - __HAL_LOCK(hrng); - + + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); +#if defined(RNG_CR_CED) + assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); +#endif /* defined(RNG_CR_CED) */ + if(hrng->State == HAL_RNG_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -135,18 +134,21 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Init the low level hardware */ HAL_RNG_MspInit(hrng); } - + /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; +#if defined(RNG_CR_CED) + /* Clock Error Detection configuration */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); +#endif /* defined(RNG_CR_CED) */ + /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; - __HAL_UNLOCK(hrng); - /* Return function status */ return HAL_OK; } @@ -163,21 +165,27 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) { return HAL_ERROR; } + +#if defined(RNG_CR_CED) + /* Clear Clock Error Detection bit */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED); +#endif /* defined(RNG_CR_CED) */ + /* Disable the RNG Peripheral */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); - + /* Clear RNG interrupt status flags */ CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); - + /* DeInit the low level hardware */ HAL_RNG_MspDeInit(hrng); - + /* Update the RNG state */ hrng->State = HAL_RNG_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hrng); - + /* Return the function status */ return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h index 53fcd334e0..4eedd1bb24 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rng.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rng.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -59,6 +57,16 @@ * @{ */ +#if defined(RNG_CR_CED) +/** + * @brief RNG Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< Clock error detection */ +}RNG_InitTypeDef; +#endif /* defined(RNG_CR_CED) */ + /** * @brief RNG HAL State Structure definition */ @@ -69,7 +77,7 @@ typedef enum HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */ HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */ - + }HAL_RNG_StateTypeDef; /** @@ -77,14 +85,18 @@ typedef enum */ typedef struct { - RNG_TypeDef *Instance; /*!< Register base address */ - - HAL_LockTypeDef Lock; /*!< RNG locking object */ - - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - + RNG_TypeDef *Instance; /*!< Register base address */ + +#if defined(RNG_CR_CED) + RNG_InitTypeDef Init; /*!< RNG configuration parameters */ +#endif /* defined(RNG_CR_CED) */ + + HAL_LockTypeDef Lock; /*!< RNG locking object */ + + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + uint32_t RandomNumber; /*!< Last Generated RNG Data */ - + }RNG_HandleTypeDef; /** @@ -116,6 +128,17 @@ typedef struct * @} */ +#if defined(RNG_CR_CED) +/** @defgroup RNG_Clock_Error_Detection RNG Clock Error Detection + * @{ + */ +#define RNG_CED_ENABLE ((uint32_t)0x00000000) /*!< Clock error detection enabled */ +#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +#endif /* defined(RNG_CR_CED) */ + /** * @} */ @@ -176,7 +199,7 @@ typedef struct * @retval None */ #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) - + /** * @brief Disable the RNG interrupt. * @param __HANDLE__: RNG Handle @@ -266,6 +289,23 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/** @addtogroup RNG_Private_Macros RNG Private Macros + * @{ + */ + +#if defined(RNG_CR_CED) +/** + * @brief Verify the RNG Clock Error Detection mode. + * @param __MODE__: RNG Clock Error Detection mode + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \ + ((__MODE__) == RNG_CED_DISABLE)) +#endif /* defined(RNG_CR_CED) */ + +/** + * @} + */ /* Private functions prototypes ----------------------------------------------*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c index 636adf2692..73ffaf2f11 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h index be41b872af..ed269a98ca 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -268,8 +266,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x000000000) -#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN ((uint32_t)0x00000000) +#define RTC_FORMAT_BCD ((uint32_t)0x00000001) /** * @} */ @@ -718,10 +716,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_TR_RESERVED_MASK 0x007F7F7FU +#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU #define RTC_TIMEOUT_VALUE 1000 diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c index 0f334cd37c..31a6fe7de1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h index df4c98ce7c..102703f1e9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c index 160fd53c8c..02f941c970 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sai.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: @@ -73,6 +71,11 @@ (+@) Number of SLOT x SLOT size = Frame length (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. + [..] + (@) For STM32L4Rx/STM32L4Sx devices, PDM interface can be activated through HAL_SAI_Init function. + Please note that PDM interface is only available for SAI1 sub-block A. + PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function. + [..] Three operation modes are available within this driver : @@ -200,7 +203,6 @@ typedef enum { #define SAI_FIFO_SIZE 8 #define SAI_DEFAULT_TIMEOUT 4 #define SAI_LONG_TIMEOUT 1000 -#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT) /** * @} @@ -265,6 +267,7 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); (++) FIFO Threshold (++) Frame Config (++) Slot Config + (++) PDM Config (only for STM32L4Rx/STM32L4Sx devices) (+) Call the function HAL_SAI_DeInit() to restore the default configuration of the selected SAI peripheral. @@ -277,12 +280,12 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); * @brief Initialize the structure FrameInit, SlotInit and the low part of * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol @ref SAI_Protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol @ref SAI_Protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: Number of slot. + * @param nbslot Number of slot. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -320,7 +323,7 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco /** * @brief Initialize the SAI according to the specified parameters. * in the SAI_InitTypeDef structure and initialize the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -354,6 +357,9 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode)); assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState)); assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Check the SAI Block Frame parameters */ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); @@ -368,6 +374,23 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Check the SAI PDM parameters */ + assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation)); + if(hsai->Init.PdmInit.Activation == ENABLE) + { + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr)); + assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable)); + /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */ + if((hsai->Instance != SAI1_Block_A) || + (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || + (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) + { + return HAL_ERROR; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + if(hsai->State == HAL_SAI_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -423,7 +446,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) } #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { @@ -439,7 +463,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) SAI1->GCR = tmpregisterGCR; #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { @@ -448,7 +473,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /* In this case, the MCKDIV value is calculated to get AudioFrequency */ #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B )) { @@ -464,8 +490,35 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure Master Clock Divider using the following formula : + - If NOMCK = 1 : + MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1)) + - If NOMCK = 0 : + MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */ + if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) + { /* NOMCK = 1 */ + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); + } + else + { /* NOMCK = 0 */ + uint32_t tmposr; + tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2 : 1; + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10) / (hsai->Init.AudioFrequency * tmposr * 256); + } + hsai->Init.Mckdiv = tmpval / 10; + + /* Round result to the nearest integer */ + if((tmpval % 10) > 8) + { + hsai->Init.Mckdiv+= 1; + } +#else /* Configure Master Clock using the following formula : MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 @@ -479,6 +532,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { hsai->Init.Mckdiv+= 1; } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ @@ -493,6 +547,19 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /* SAI Block Configuration -------------------------------------------------*/ /* SAI CR1 Configuration */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV | SAI_xCR1_OSR); + + hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ + hsai->Init.MckOverSampling); +#else hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ @@ -503,6 +570,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) ckstr_bits | syncen_bits | \ hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* SAI CR2 Configuration */ hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); @@ -525,6 +593,22 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* SAI PDM Configuration ---------------------------------------------------*/ + if(hsai->Instance == SAI1_Block_A) + { + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + if(hsai->Init.PdmInit.Activation == ENABLE) + { + /* Configure and enable PDM interface */ + SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | + ((hsai->Init.PdmInit.MicPairsNbr - 1) << SAI_PDMCR_MICNBR_Pos)); + SAI1->PDMCR |= SAI_PDMCR_PDMEN; + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; @@ -539,7 +623,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI peripheral. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -563,6 +647,18 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Disable SAI PDM interface */ + if(hsai->Instance == SAI1_Block_A) + { + /* Reset PDM delays */ + SAI1->PDMDLY = 0U; + + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_SAI_MspDeInit(hsai); @@ -580,7 +676,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -596,7 +692,7 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -638,17 +734,14 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) (+) Blocking mode functions are : (++) HAL_SAI_Transmit() (++) HAL_SAI_Receive() - (++) HAL_SAI_TransmitReceive() (+) Non Blocking mode functions with Interrupt are : (++) HAL_SAI_Transmit_IT() (++) HAL_SAI_Receive_IT() - (++) HAL_SAI_TransmitReceive_IT() (+) Non Blocking mode functions with DMA are : (++) HAL_SAI_Transmit_DMA() (++) HAL_SAI_Receive_DMA() - (++) HAL_SAI_TransmitReceive_DMA() (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SAI_TxCpltCallback() @@ -661,11 +754,11 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) @@ -761,11 +854,11 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -859,10 +952,10 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -921,10 +1014,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -981,7 +1074,7 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui /** * @brief Pause the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1001,7 +1094,7 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) /** * @brief Resume the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1028,7 +1121,7 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) /** * @brief Stop the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1060,6 +1153,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Disable SAI peripheral */ SAI_Disable(hsai); + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + hsai->State = HAL_SAI_STATE_READY; /* Process Unlocked */ @@ -1070,7 +1166,7 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /** * @brief Abort the current transfer and disable the SAI. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1123,10 +1219,10 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1210,10 +1306,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1280,9 +1376,9 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Enable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param val: value sent during the mute @ref SAI_Block_Mute_Value + * @param val value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) @@ -1300,7 +1396,7 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val /** * @brief Disable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1316,10 +1412,10 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Enable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param callback: function called when the mute is detected. - * @param counter: number a data before mute detection max 63. + * @param callback function called when the mute is detected. + * @param counter number a data before mute detection max 63. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) @@ -1330,7 +1426,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback { /* set the mute counter */ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); - SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET)); + SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos)); hsai->mutecallback = callback; /* enable the IT interrupt */ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET); @@ -1341,7 +1437,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback /** * @brief Disable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1360,7 +1456,7 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Handle SAI interrupt request. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1536,7 +1632,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1552,7 +1648,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1568,7 +1664,7 @@ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1584,7 +1680,7 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1600,7 +1696,7 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1636,7 +1732,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI handle state. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL state */ @@ -1647,7 +1743,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI error code. -* @param hsai: pointer to a SAI_HandleTypeDef structure that contains +* @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. * @retval SAI Error Code */ @@ -1671,12 +1767,12 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol. - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: number of slot minimum value is 2 and max is 16. + * @param nbslot number of slot minimum value is 2 and max is 16. * the value must be a multiple of 2. * @retval HAL status */ @@ -1766,11 +1862,11 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot: number of slot minimum value is 1 and the max is 16. + * @param protocol one of the supported protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot number of slot minimum value is 1 and the max is 16. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -1836,7 +1932,7 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Fill the fifo. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1865,9 +1961,9 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) /** * @brief Return the interrupt flag to set according the SAI setup. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param mode: SAI_MODE_DMA or SAI_MODE_IT + * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) @@ -1899,7 +1995,7 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) /** * @brief Disable the SAI and wait for the disabling. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1925,7 +2021,7 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1949,7 +2045,7 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1974,7 +2070,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1999,7 +2095,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2025,7 +2121,7 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2051,7 +2147,7 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) } /** * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2078,7 +2174,7 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief DMA SAI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2103,7 +2199,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI transmit process half complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2116,7 +2212,7 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2139,7 +2235,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2151,7 +2247,7 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) } /** * @brief DMA SAI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2180,7 +2276,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI Abort callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h index 383d35fadf..1c956e7348 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sai.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention @@ -76,6 +74,20 @@ typedef enum */ typedef void (*SAIcallback)(void); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief SAI PDM Init structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Enable/disable PDM interface */ + uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + uint32_t ClockEnable; /*!< Specifies which clock must be enabled. + This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ +}SAI_PdmInitTypeDef; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition * @brief SAI Init Structure definition * @{ @@ -101,7 +113,14 @@ typedef struct uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. This parameter can be a value of @ref SAI_Block_NoDivider - @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length + @note: For STM32L4Rx/STM32L4Sx devices : + If bit NOMCK in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NOMCK in the SAI_xCR1 register is set, the frame length can + take any of the values without constraint. There is no MCLK_x clock + which can be output. + For other devices : + If bit NODIV in the SAI_xCR1 register is cleared, the frame length should be aligned to a number equal to a power of 2, from 8 to 256. If bit NODIV in the SAI_xCR1 register is set, the frame length can take any of the values without constraint since the input clock of @@ -116,7 +135,13 @@ typedef struct uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for AudioFrequency the user choice - This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 63 on STM32L4Rx/STM32L4Sx devices. + This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. */ + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. + This parameter can be a value of @ref SAI_Block_Mck_OverSampling */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ @@ -127,6 +152,10 @@ typedef struct uint32_t TriState; /*!< Specifies the companding mode type. This parameter can be a value of @ref SAI_TRIState_Management */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* This part of the structure is automatically filled if your are using the high level initialisation function HAL_SAI_InitProtocol */ @@ -314,6 +343,26 @@ typedef struct __SAI_HandleTypeDef * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling + * @{ + */ +#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U) +#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR) +/** + * @} + */ + +/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable + * @{ + */ +#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1) +#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2) +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup SAI_Block_Mode SAI Block Mode * @{ */ @@ -391,7 +440,11 @@ typedef struct __SAI_HandleTypeDef * @{ */ #define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK) +#else #define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -564,14 +617,14 @@ typedef struct __SAI_HandleTypeDef */ /** @brief Reset SAI handle state. - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -586,8 +639,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check whether the specified SAI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the SAI interrupt source to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -601,8 +654,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag. @@ -616,8 +669,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SAI pending flag. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_MUTEDET: Clear Mute detection @@ -638,6 +691,11 @@ typedef struct __SAI_HandleTypeDef * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* Include SAI HAL Extension module */ +#include "stm32l4xx_hal_sai_ex.h" +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SAI_Exported_Functions @@ -738,6 +796,16 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ + ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) + +#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) + +#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ + (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ ((MODE) == SAI_MODEMASTER_RX) || \ ((MODE) == SAI_MODESLAVE_TX) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c new file mode 100644 index 0000000000..44bd907dc5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.c @@ -0,0 +1,142 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sai_ex.c + * @author MCD Application Team + * @brief SAI Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the SAI Peripheral Controller: + * + Modify PDM microphone delays. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ +#ifdef HAL_SAI_MODULE_ENABLED +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @defgroup SAIEx SAIEx + * @brief SAI Extended HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_OFFSET 8U +#define SAI_PDM_RIGHT_DELAY_OFFSET 4U + +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @brief SAIEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Modify PDM microphone delays + +@endverbatim + * @{ + */ + +/** + * @brief Configure PDM microphone delays. + * @param hsai SAI handle. + * @param pdmMicDelay Microphone delays configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that SAI sub-block is SAI1 sub-block A */ + if(hsai->Instance != SAI1_Block_A) + { + status = HAL_ERROR; + } + else + { + /* Check microphone delay parameters */ + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay)); + + /* Check SAI state */ + if(hsai->State != HAL_SAI_STATE_RESET) + { + /* Reset current delays for specified microphone */ + SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); + + /* Apply new microphone delays */ + SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \ + (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1))); + } + else + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#endif /* HAL_SAI_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h new file mode 100644 index 0000000000..3a3828dad1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai_ex.h @@ -0,0 +1,132 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sai_ex.h + * @author MCD Application Team + * @brief Header file of SAI HAL extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_SAI_EX_H +#define __STM32L4xx_HAL_SAI_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SAIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup SAIEx_Exported_Types SAIEx Exported Types + * @{ + */ + +/** + * @brief PDM microphone delay structure definition + */ +typedef struct +{ + uint32_t MicPair; /*!< Specifies which pair of microphones is selected. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + + uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ + + uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ +}SAIEx_PdmMicDelayParamTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ + +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros + * @{ + */ + +#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_SAI_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c index 5ea713557e..d76c7386a1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sd.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -37,7 +35,8 @@ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() and according to your pin assignment; - (##) Perform DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() + (##) On STM32L4Rx/STM32L4Sxx devices, no DMA configuration is need, an internal DMA for SDMMC IP is used. + (##) On other devices, perform DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() and HAL_SD_WriteBlocks_DMA() APIs). (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. @@ -233,9 +232,10 @@ * @{ */ -/** @addtogroup SD +/** @defgroup SD SD + * @brief SD HAL module driver * @{ - */ + */ #ifdef HAL_SD_MODULE_ENABLED @@ -266,11 +266,13 @@ static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSC static HAL_StatusTypeDef SD_PowerOFF (SD_HandleTypeDef *hsd); static HAL_StatusTypeDef SD_Write_IT (SD_HandleTypeDef *hsd); static HAL_StatusTypeDef SD_Read_IT (SD_HandleTypeDef *hsd); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SD_DMAReceiveCplt (DMA_HandleTypeDef *hdma); static void SD_DMAError (DMA_HandleTypeDef *hdma); static void SD_DMATxAbort (DMA_HandleTypeDef *hdma); static void SD_DMARxAbort (DMA_HandleTypeDef *hdma); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @} */ @@ -312,7 +314,9 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) /* Check the parameters */ assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass)); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); @@ -334,6 +338,28 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) return HAL_ERROR; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the bus wide */ + if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + hsd->Instance->CLKCR |= 0x00100000; + /* Enable High Speed */ + if(HAL_SDEx_HighSpeed(hsd) != HAL_OK) + { + return HAL_ERROR; + } + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Initialize the error code */ hsd->ErrorCode = HAL_SD_ERROR_NONE; @@ -361,12 +387,22 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; Init.BusWide = SDMMC_BUS_WIDE_1B; Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; Init.ClockDiv = SDMMC_INIT_CLK_DIV; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + /* Set Transceiver polarity */ + hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Initialize SDMMC peripheral interface with default configuration */ status = SDMMC_Init(hsd->Instance, Init); if(status != HAL_OK) @@ -374,8 +410,10 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Disable SDMMC Clock */ __HAL_SD_DISABLE(hsd); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* Set Power State to ON */ status = SDMMC_PowerState_ON(hsd->Instance); @@ -384,9 +422,11 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Enable SDMMC Clock */ __HAL_SD_ENABLE(hsd); - +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + /* Required power up waiting time before starting the SD initialization sequence */ HAL_Delay(2U); @@ -553,8 +593,15 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ SDMMC_ConfigData(hsd->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Read block(s) in polling mode */ if(NumberOfBlocks > 1) @@ -602,6 +649,9 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 return HAL_TIMEOUT; } } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Send stop transmission command in case of multiblock read */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) @@ -647,6 +697,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Empty FIFO if there is still any data */ while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) { @@ -662,9 +713,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 return HAL_ERROR; } } +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -734,6 +786,22 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else + config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + SDMMC_ConfigData(hsd->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -758,15 +826,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_ERROR; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * BLOCKSIZE; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Write block(s) in polling mode */ while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { @@ -789,7 +848,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_TIMEOUT; } } - +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Send stop transmission command in case of multiblock write */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { @@ -835,7 +897,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -897,15 +959,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui BlockAdd *= 512U; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) @@ -917,6 +970,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else + config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + SDMMC_ConfigData(hsd->Instance, &config); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Read Blocks in IT mode */ if(NumberOfBlocks > 1U) { @@ -1010,6 +1079,19 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u return HAL_ERROR; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -1034,6 +1116,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -1042,6 +1125,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; SDMMC_ConfigData(hsd->Instance, &config); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ return HAL_OK; } @@ -1090,6 +1174,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Initialize data control register */ hsd->Instance->DCTRL = 0U; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); /* Set the DMA transfer complete callback */ @@ -1106,21 +1191,16 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Enable SD DMA transfer */ __HAL_SD_DMA_ENABLE(hsd); +#else + hsd->pRxBuffPtr = (uint32_t*)pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { BlockAdd *= 512U; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) @@ -1131,6 +1211,28 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + config.DPSM = SDMMC_DPSM_DISABLE; +#else + config.DPSM = SDMMC_DPSM_ENABLE; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + SDMMC_ConfigData(hsd->Instance, &config); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsd->Instance->IDMABASE0 = (uint32_t) pData ; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Read Blocks in DMA mode */ if(NumberOfBlocks > 1U) @@ -1151,6 +1253,9 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; @@ -1203,6 +1308,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, /* Initialize data control register */ hsd->Instance->DCTRL = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->pTxBuffPtr = (uint32_t*)pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; +#else /* Enable SD Error interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); @@ -1214,6 +1323,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, /* Set the DMA Abort callback */ hsd->hdmatx->XferAbortCallback = NULL; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { @@ -1230,6 +1340,24 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsd->Instance->IDMABASE0 = (uint32_t) pData ; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) @@ -1250,11 +1378,15 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Enable SDMMC DMA transfer */ __HAL_SD_DMA_ENABLE(hsd); @@ -1269,6 +1401,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; SDMMC_ConfigData(hsd->Instance, &config); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ return HAL_OK; } @@ -1396,8 +1529,14 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE( hsd->Instance); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if((hsd->Context & SD_CONTEXT_IT) != RESET) { @@ -1412,7 +1551,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) @@ -1426,6 +1565,32 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } else if((hsd->Context & SD_CONTEXT_DMA) != RESET) { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + hsd->Instance->DLEN = 0; + hsd->Instance->DCTRL = 0; + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Stop Transfer for Write Single/Multi blocks or Read Multi blocks */ + if((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } + } + + hsd->State = HAL_SD_STATE_READY; + if(((hsd->Context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + { + HAL_SD_TxCpltCallback(hsd); + } + if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + { + HAL_SD_RxCpltCallback(hsd); + } +#else if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); @@ -1445,20 +1610,17 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SD_TxCpltCallback(hsd); } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE); - SD_Write_IT(hsd); } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF); - SD_Read_IT(hsd); } @@ -1483,15 +1645,33 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - if((hsd->Context & SD_CONTEXT_DMA) != RESET) + if((hsd->Context & SD_CONTEXT_IT) != RESET) { - /* Abort the SD DMA Streams */ + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + HAL_SD_ErrorCallback(hsd); + } + else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Disable Internal DMA */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + HAL_SD_ErrorCallback(hsd); + } +#else + /* Abort the SD DMA channel */ if(hsd->hdmatx != NULL) { /* Set the DMA Tx abort callback */ @@ -1518,14 +1698,40 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; HAL_SD_AbortCallback(hsd); } - } - else if((hsd->Context & SD_CONTEXT_IT) != RESET) - { - /* Set the SD state to ready to be able to start again the process */ - hsd->State = HAL_SD_STATE_READY; - HAL_SD_ErrorCallback(hsd); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } } + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET) + { + if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == SD_DMA_BUFFER0) + { + /* Current buffer is buffer0, Transfer complete for buffer1 */ + if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(hsd); + } + else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ + { + HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(hsd); + } + } + else /* SD_DMA_BUFFER1 */ + { + /* Current buffer is buffer1, Transfer complete for buffer0 */ + if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(hsd); + } + else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ + { + HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(hsd); + } + } + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ } /** @@ -1650,7 +1856,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef pCID->OEM_AppliID = tmp << 8; /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); + tmp = (uint8_t)((hsd->CID[0] & 0x0000FF00) >> 8); pCID->OEM_AppliID |= tmp; /* Byte 3 */ @@ -2030,11 +2236,39 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { /* Configure the SDMMC peripheral */ Init.ClockEdge = hsd->Init.ClockEdge; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) Init.ClockBypass = hsd->Init.ClockBypass; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ Init.ClockPowerSave = hsd->Init.ClockPowerSave; Init.BusWide = WideMode; Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if 0 + /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ + // if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV) + if(hsd->Init.ClockDiv >= SDMMC_TRANSFER_CLK_DIV) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + else + { + if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + else + { + /* No High speed SD card */ + // Init.ClockDiv = SDMMC_NSpeed_CLK_DIV; + Init.ClockDiv = SDMMC_TRANSFER_CLK_DIV; + } + } +#else Init.ClockDiv = hsd->Init.ClockDiv; +#endif +#else + Init.ClockDiv = hsd->Init.ClockDiv; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ SDMMC_Init(hsd->Instance, Init); } @@ -2084,22 +2318,27 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; +#else if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - /* Abort the SD DMA Tx Stream */ + /* Abort the SD DMA Tx channel */ if(hsd->hdmatx != NULL) { HAL_DMA_Abort(hsd->hdmatx); } - /* Abort the SD DMA Rx Stream */ + /* Abort the SD DMA Rx channel */ if(hsd->hdmarx != NULL) { HAL_DMA_Abort(hsd->hdmarx); } } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ hsd->State = HAL_SD_STATE_READY; CardState = HAL_SD_GetCardState(hsd); @@ -2124,19 +2363,40 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { HAL_SD_CardStateTypedef CardState; - /* DIsable All interrupts */ + /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + HAL_SD_AbortCallback(hsd); + } +#else if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - /* Abort the SD DMA Tx Stream */ + /* Abort the SD DMA Tx channel */ if(hsd->hdmatx != NULL) { hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; @@ -2145,7 +2405,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) hsd->hdmatx = NULL; } } - /* Abort the SD DMA Rx Stream */ + /* Abort the SD DMA Rx channel */ if(hsd->hdmarx != NULL) { hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; @@ -2159,6 +2419,9 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) /* No transfer ongoing on both DMA channels*/ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) @@ -2174,6 +2437,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) HAL_SD_AbortCallback(hsd); } } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } @@ -2191,6 +2455,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) * @{ */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief DMA SD transmit process complete callback * @param hdma: DMA handle @@ -2230,7 +2495,7 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -2287,14 +2552,16 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) /* All DMA channels are aborted */ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { HAL_SD_AbortCallback(hsd); } @@ -2324,14 +2591,16 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) /* All DMA channels are aborted */ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { HAL_SD_AbortCallback(hsd); } @@ -2342,6 +2611,7 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) } } } +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Initializes the sd card. @@ -2423,8 +2693,10 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) return errorstate; } +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Configure SDMMC peripheral interface */ SDMMC_Init(hsd->Instance, hsd->Init); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /* All cards are initialized */ return HAL_SD_ERROR_NONE; @@ -2456,6 +2728,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { hsd->SdCard.CardVersion = CARD_V1_X; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ while(validvoltage == 0) { @@ -2486,11 +2759,13 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) } /* Card type is SDSC */ hsd->SdCard.CardType = CARD_SDSC; +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ } else { hsd->SdCard.CardVersion = CARD_V2_X; +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ while(validvoltage == 0) { @@ -2528,8 +2803,115 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { hsd->SdCard.CardType = CARD_SDSC; } +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((!validvoltage) && (count < SDMMC_MAX_VOLT_TRIAL)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31) == 1) ? 1 : 0); + + count++; + } + + if(count >= SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + + if(hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE) + { + if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + { + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + + /* Start switching procedue */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN; + + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Check to CKSTOP */ + while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP); + + /* Clear CKSTOP Flag */ + hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; + + /* Check to BusyD0 */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) + { + /* Error when activate Voltage Switch in SDMMC IP */ + return SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Enable Transceiver Switch PIN */ + HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); + + /* Switch ready */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; + + /* Check VSWEND Flag */ + while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND); + + /* Clear VSWEND Flag */ + hsd->Instance->ICR = SDMMC_FLAG_VSWEND; + + /* Check BusyD0 status */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) + { + /* Error when enabling 1.8V mode */ + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + /* Switch to 1.8V OK */ + + /* Disable VSWITCH FLAG from SDMMC IP */ + hsd->Instance->POWER = 0x13; + /* Clean Status flags */ + hsd->Instance->ICR = 0xFFFFFFFF; + } + } + } + } + } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + return HAL_SD_ERROR_NONE; } @@ -2600,7 +2982,11 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Get status data */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) +#else while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { @@ -2631,7 +3017,11 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) return HAL_SD_ERROR_RX_OVERRUN; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) +#else while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); pSDstatus++; @@ -2643,7 +3033,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Clear all the static status flags*/ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); return HAL_SD_ERROR_NONE; } @@ -2815,6 +3205,23 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) return errorstate; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) + { + if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0)) + { + tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); + tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); + index++; + } + + + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } +#else while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) @@ -2828,6 +3235,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) return HAL_SD_ERROR_TIMEOUT; } } +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { @@ -2851,8 +3259,8 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { /* No error flag set */ /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h index da41cd6551..b1748fe7a8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sd.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -52,10 +50,9 @@ * @{ */ -/** @defgroup SD SD - * @brief SD HAL module driver +/** @addtogroup SD * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup SD_Exported_Types SD Exported Types @@ -126,6 +123,11 @@ typedef struct uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + + uint32_t CardSpeed; /*!< Specifies the card Speed */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ }HAL_SD_CardInfoTypeDef; /** @@ -153,10 +155,13 @@ typedef struct __IO uint32_t ErrorCode; /*!< SD Card Error codes */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ uint32_t CSD[4]; /*!< SD card specific data table */ @@ -332,6 +337,13 @@ typedef struct /** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards * @{ */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */ +#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */ +#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards + and <104Mo/s for SDR104, Spec version 3.01 */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + #define CARD_SDSC ((uint32_t)0x00000000U) #define CARD_SDHC_SDXC ((uint32_t)0x00000001U) #define CARD_SECURED ((uint32_t)0x00000003U) @@ -359,6 +371,7 @@ typedef struct * @{ */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief Enable the SD device. * @retval None @@ -382,6 +395,7 @@ typedef struct * @retval None */ #define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Enable the SD device interrupt. @@ -615,6 +629,10 @@ typedef struct * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* Include SD HAL Extension module */ +#include "stm32l4xx_hal_sd_ex.h" +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* Exported functions --------------------------------------------------------*/ /** @defgroup SD_Exported_Functions SD Exported Functions * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c new file mode 100644 index 0000000000..4ee5298889 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.c @@ -0,0 +1,550 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sd_ex.c + * @author MCD Application Team + * @brief SD card Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (SD) peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SD Extension HAL driver can be used as follows: + (+) Set card in High Speed mode using HAL_SDEx_HighSpeed() function. + (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. + (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup SDEx SDEx + * @brief SD HAL extended module driver + * @{ + */ + +#ifdef HAL_SD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDEx_Exported_Functions + * @{ + */ + +/** @addtogroup SDEx_Exported_Functions_Group1 + * @brief High Speed function + * +@verbatim + ============================================================================== + ##### High Speed function ##### + ============================================================================== + [..] + This section provides function allowing to configure the card in High Speed mode. + +@endverbatim + * @{ + */ + +/** + * @brief Switches the SD card to High Speed mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock between 50 and 120 MHz + * @param hsd: SD handle + * @retval SD Card error state + */ +uint32_t HAL_SDEx_HighSpeed(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_OK; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint8_t SD_hs[64] = {0}; + uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; + uint32_t Timeout = HAL_GetTick(); + + if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) && + (hsd->Init.Transceiver == SDMMC_TRANSCEIVER_ENABLE)) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + + if (errorstate != HAL_OK) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); + + errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); + if(errorstate != HAL_OK) + { + return errorstate; + } + + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0; count < 8; count++) + { + *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); + } + + tempbuff += 8; + } + + if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + errorstate = 0; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode HS is ok */ + if ((SD_hs[13]& 2) != 2) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + HAL_SDEx_DriveTransceiver_1_8V_Callback(SET); + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + } + + return errorstate; +} + +/** + * @brief Enable/Disable the SD Transciver 1.8V Mode Callback. + * @param status: Voltage Switch State + * @retval None + */ +__weak void HAL_SDEx_DriveTransceiver_1_8V_Callback(FlagStatus status) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(status); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SD_EnableTransciver could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup SDEx_Exported_Functions_Group2 + * @brief Multibuffer functions + * +@verbatim + ============================================================================== + ##### Multibuffer functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure the multibuffer mode and start read and write + multibuffer mode for SD HAL driver. + +@endverbatim + * @{ + */ + +/** + * @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA. + * @param hsd: SD handle + * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data + * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data + * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize) +{ + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0; + hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1; + hsd->Instance->IDMABSIZE = (uint32_t) (BLOCKSIZE * BufferSize); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * @param hsd: SD handle + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + + if(hsd->State == HAL_SD_STATE_READY) + { + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + { + hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_BUSY; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + + hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + +// /* Set Block Size for Card */ +// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); +// if(errorstate != HAL_SD_ERROR_NONE) +// { +// hsd->State = HAL_SD_STATE_READY; +// hsd->ErrorCode |= errorstate; +// return HAL_ERROR; +// } + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + + /* Read Blocks in DMA mode */ + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + +} + +/** + * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * @param hsd: SD handle + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + + if(hsd->State == HAL_SD_STATE_READY) + { + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + if ((hsd->Instance->IDMABASE0 == 0) || (hsd->Instance->IDMABASE1 == 0) || (hsd->Instance->IDMABSIZE == 0)) + { + hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + hsd->State = HAL_SD_STATE_BUSY; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + SDMMC_ConfigData(hsd->Instance, &config); + +// /* Set Block Size for Card */ +// errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); +// if(errorstate != HAL_SD_ERROR_NONE) +// { +// hsd->State = HAL_SD_STATE_READY; +// hsd->ErrorCode |= errorstate; +// return HAL_ERROR; +// } + + __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + + /* Write Blocks in DMA mode */ + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Change the DMA Buffer0 or Buffer1 address on the fly. + * @param hsd: pointer to a SD_HandleTypeDef structure. + * @param Buffer: the buffer to be changed, This parameter can be one of + * the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1 + * @param pDataBuffer: The new address + * @note The BUFFER0 address can be changed only when the current transfer use + * BUFFER1 and the BUFFER1 address can be changed only when the current + * transfer use BUFFER0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer) +{ + if(Buffer == SD_DMA_BUFFER0) + { + /* change the buffer0 address */ + hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer; + } + else + { + /* change the memory1 address */ + hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer; + } + + return HAL_OK; +} + +/** + * @brief Read DMA Buffer 0 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Read_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Read DMA Buffer 1 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Read_DMADoubleBuffer1CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Write DMA Buffer 0 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @brief Write DMA Buffer 1 Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Write_DMADoubleBuffer0CpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h new file mode 100644 index 0000000000..a187e6143b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sd_ex.h @@ -0,0 +1,144 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_sd_ex.h + * @author MCD Application Team + * @brief Header file of SD HAL extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_SD_EX_H +#define __STM32L4xx_HAL_SD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDEx_Exported_Types SDEx Exported Types + * @{ + */ + +/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure + * @{ + */ +typedef enum +{ + SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */ + SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */ + +}HAL_SDEx_DMABuffer_MemoryTypeDef; + + +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDEx_Exported_Functions SDEx Exported Functions + * @{ + */ + +/** @defgroup SDEx_Exported_Functions_Group1 HighSpeed functions + * @{ + */ +uint32_t HAL_SDEx_HighSpeed (SD_HandleTypeDef *hsd); + +void HAL_SDEx_DriveTransceiver_1_8V_Callback(FlagStatus status); + +/** + * @} + */ + +/** @defgroup SDEx_Exported_Functions_Group2 MultiBuffer functions + * @{ + */ +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer); + +void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd); +void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); +void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd); +void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L4xx_HAL_SDEx_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c index 13b4a081dc..af7665a3d5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -24,20 +22,20 @@ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: (++) Enable the USARTx interface clock. (++) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Enable the clock for the USART GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() and HAL_SMARTCARD_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -153,17 +151,46 @@ */ #define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#if defined(USART_CR1_FIFOEN) +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#else +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#endif + +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ + USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ + +#if defined(USART_CR1_FIFOEN) +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#else +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#endif + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup SMARTCARD_Private_Variables SMARTCARD Private Variables + * @{ + */ +static const uint16_t SMARTCARDPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; +/** + * @} + */ +#endif + /* Private function prototypes -----------------------------------------------*/ /** @addtogroup SMARTCARD_Private_Functions * @{ @@ -182,9 +209,15 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(USART_CR1_FIFOEN) +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +#endif +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(USART_CR1_FIFOEN) +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /** * @} */ @@ -244,10 +277,10 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar */ /** - * @brief Initialize the SMARTCARD mode according to the specified + * @brief Initialize the SMARTCARD mode according to the specified * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) @@ -306,9 +339,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief DeInitialize the SMARTCARD peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) @@ -347,32 +380,32 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief Initialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) + __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspInit can be implemented in the user file */ } /** - * @brief DeInitialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) + __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspDeInit can be implemented in the user file */ @@ -461,9 +494,13 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) */ /** - * @brief Send an amount of data in blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in blocking mode. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @param Timeout Timeout duration. @@ -488,7 +525,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -542,9 +579,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui } /** - * @brief Receive an amount of data in blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in blocking mode. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @param Timeout Timeout duration. @@ -601,9 +642,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin } /** - * @brief Send an amount of data in interrupt mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -617,20 +665,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - hsmartcard->pTxBuffPtr = pData; - hsmartcard->TxXferSize = Size; + + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - + hsmartcard->TxISR = NULL; + /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - + /* Disable Rx, enable Tx */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); @@ -638,16 +687,43 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Enable the SMARTCARD Error Interrupt: (Frame error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); - + +#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the TX FIFO threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + } + else +#endif + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); +#endif + } + return HAL_OK; } else @@ -657,9 +733,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Receive an amount of data in interrupt mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @retval HAL status @@ -684,12 +767,37 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* Configure Rx interrupt processing */ +#if defined(USART_CR1_FIFOEN) + if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN; - /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + } + else +#endif + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE_RXFNEIE); +#else + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); +#endif + } + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -702,9 +810,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Send an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be sent. * @retval HAL status @@ -774,9 +882,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard } /** - * @brief Receive an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param pData pointer to data buffer. * @param Size amount of data to be received. * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), @@ -838,7 +946,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, /** * @brief Abort ongoing transfers (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) @@ -847,12 +955,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) @@ -906,7 +1019,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) @@ -915,11 +1028,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); +#else /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Check if a receive process is ongoing or not. If not disable ERR IT */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) @@ -959,7 +1078,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /** * @brief Abort ongoing Receive transfer (blocking mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) @@ -968,11 +1087,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); +#else /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -1012,7 +1138,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Abort ongoing transfers (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx and Rx) @@ -1023,14 +1149,20 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t abortcplt = 1; +#if defined(USART_CR1_FIFOEN) + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ @@ -1062,7 +1194,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->hdmarx->XferAbortCallback = NULL; } } - + /* Disable the SMARTCARD DMA Tx request if enabled */ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { @@ -1118,6 +1250,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->TxXferCount = 0; hsmartcard->RxXferCount = 0; + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; + /* Reset errorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; @@ -1138,7 +1274,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Abort ongoing Transmit transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Tx) @@ -1149,11 +1285,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); +#else /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Check if a receive process is ongoing or not. If not disable ERR IT */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) @@ -1186,6 +1328,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /* Reset Tx transfer counter */ hsmartcard->TxXferCount = 0; + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1197,10 +1342,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart { /* Reset Tx transfer counter */ hsmartcard->TxXferCount = 0; - + + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); - + /* Restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1214,7 +1362,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /** * @brief Abort ongoing Receive transfer (Interrupt mode). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. * This procedure performs following operations : * - Disable SMARTCARD Interrupts (Rx) @@ -1228,28 +1376,35 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { +#if defined(USART_CR1_FIFOEN) + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); +#else /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); - + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#endif + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if(hsmartcard->hdmarx != NULL) { /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { @@ -1261,13 +1416,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc { /* Reset Rx transfer counter */ hsmartcard->RxXferCount = 0; - + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); } @@ -1276,127 +1434,156 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc { /* Reset Rx transfer counter */ hsmartcard->RxXferCount = 0; - + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); } - + return HAL_OK; } /** * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR); uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); - uint32_t cr3its; + uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); uint32_t errorflags; - + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == RESET) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - SMARTCARD_Receive_IT(hsmartcard); - /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */ + if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} return; } } - + /* If some errors occur */ - cr3its = READ_REG(hsmartcard->Instance->CR3); - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) ) +#if defined(USART_CR1_FIFOEN) + if( (errorflags != RESET) + && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) +#else + if( (errorflags != RESET) + && ( ((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) +#endif { /* SMARTCARD parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; } - + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; } - + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; } - + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + if( ((isrflags & USART_ISR_ORE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET)) ) +#else + if( ((isrflags & USART_ISR_ORE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET)) ) +#endif { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } - + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); - + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; } - + /* Call SMARTCARD Error Call back function if need be --------------------------*/ if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET) ) +#endif { - SMARTCARD_Receive_IT(hsmartcard); + if (hsmartcard->RxISR != NULL) {hsmartcard->RxISR(hsmartcard);} } - + /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception */ if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET) || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))) { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ SMARTCARD_EndRxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - + /* Abort the SMARTCARD DMA Rx channel */ if(hsmartcard->hdmarx != NULL) { /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { @@ -1417,27 +1604,28 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) } } /* other error type to be considered as blocking : - - Frame error in Transmission + - Frame error in Transmission */ - else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) + else if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) { /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ SMARTCARD_EndTxTransfer(hsmartcard); - + /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - + /* Abort the SMARTCARD DMA Tx channel */ if(hsmartcard->hdmatx != NULL) { /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - + /* Abort DMA TX */ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) { @@ -1460,15 +1648,15 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) else { /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + Error is notified to user through user error callback */ HAL_SMARTCARD_ErrorCallback(hsmartcard); hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET)) { @@ -1476,69 +1664,93 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) __HAL_UNLOCK(hsmartcard); HAL_SMARTCARD_RxCpltCallback(hsmartcard); /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information - * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); return; } - + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif { - SMARTCARD_Transmit_IT(hsmartcard); + if (hsmartcard->TxISR != NULL) {hsmartcard->TxISR(hsmartcard);} return; } - + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)) + if( (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)) { SMARTCARD_EndTransmit_IT(hsmartcard); return; } + +#if defined(USART_CR1_FIFOEN) + /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + { + HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard); + return; + } + + /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + { + HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard); + return; + } +#endif } /** - * @brief Tx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Tx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) + __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. */ } /** - * @brief Rx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Rx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. */ } /** - * @brief SMARTCARD error callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief SMARTCARD error callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. */ @@ -1547,7 +1759,7 @@ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) @@ -1563,7 +1775,7 @@ __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard /** * @brief SMARTCARD Abort Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) @@ -1579,7 +1791,7 @@ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hs /** * @brief SMARTCARD Abort Receive Complete callback. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) @@ -1597,7 +1809,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm */ /** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions + * @brief SMARTCARD State and Errors functions * @verbatim ============================================================================== @@ -1617,8 +1829,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsm /** * @brief Return the SMARTCARD handle state. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1627,15 +1839,15 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar uint32_t temp1= 0x00, temp2 = 0x00; temp1 = hsmartcard->gState; temp2 = hsmartcard->RxState; - + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); } /** * @brief Return the SMARTCARD handle error code. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD handle Error Code + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. +* @retval SMARTCARD handle Error Code */ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) { @@ -1650,14 +1862,14 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions * @{ */ /** * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1680,6 +1892,9 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable)); assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable)); assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler)); +#endif /*-------------------------- USART CR1 Configuration -----------------------*/ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). @@ -1687,8 +1902,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - tmpreg |= (uint32_t) hsmartcard->Init.WordLength; + tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -1707,15 +1921,22 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * to hsmartcard->Init.NACKEnable * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; - tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS); - MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg); + tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg); + +#if defined(USART_PRESC_PRESCALER) + /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/ + /* Configure + * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */ + MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler); +#endif /*-------------------------- USART GTPR Configuration ----------------------*/ - tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS)); + tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); /*-------------------------- USART RTOR Configuration ----------------------*/ - tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); @@ -1725,28 +1946,69 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); + tmpreg = 0; switch (clocksource) { - case SMARTCARD_CLOCKSOURCE_PCLK1: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_PCLK2: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_HSI: - hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_LSE: - hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + case SMARTCARD_CLOCKSOURCE_PCLK1: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_PCLK2: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_HSI: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HSI_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_SYSCLK: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq()/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_LSE: +#if defined(USART_PRESC_PRESCALER) + tmpreg = (uint16_t)((LSE_VALUE/SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler] + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#else + tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); +#endif + break; + case SMARTCARD_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hsmartcard->Instance->BRR = tmpreg; + } + else + { + ret = HAL_ERROR; + } + +#if defined(USART_CR1_FIFOEN) + /* Initialize the number of data to process during RX/TX ISR execution */ + hsmartcard->NbTxDataToProcess = 1; + hsmartcard->NbRxDataToProcess = 1; +#endif + + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; return ret; } @@ -1754,8 +2016,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1816,8 +2078,8 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Check the SMARTCARD Idle State. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1864,7 +2126,7 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar /** * @brief Handle SMARTCARD Communication Timeout. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @param Flag Specifies the SMARTCARD flag to check. * @param Status The new Flag status (SET or RESET). * @param Tickstart Tick start value @@ -1882,12 +2144,16 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); +#endif CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); return HAL_TIMEOUT; @@ -1901,13 +2167,17 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* At end of Tx process, restore hsmartcard->gState to Ready */ @@ -1918,13 +2188,17 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore hsmartcard->RxState to Ready */ @@ -1933,7 +2207,7 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) /** - * @brief DMA SMARTCARD transmit process complete callback. + * @brief DMA SMARTCARD transmit process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1952,7 +2226,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SMARTCARD receive process complete callback. + * @brief DMA SMARTCARD receive process complete callback. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -2074,7 +2348,7 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); - + hsmartcard->hdmarx->XferAbortCallback = NULL; /* Check if an Abort process is still ongoing */ @@ -2085,7 +2359,7 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) return; } } - + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ hsmartcard->TxXferCount = 0; hsmartcard->RxXferCount = 0; @@ -2155,13 +2429,14 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Send an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once + * @note Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() - * @retval HAL status + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check that a Tx process is ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) @@ -2169,34 +2444,67 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartca if(hsmartcard->TxXferCount == 0) { /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); +#endif /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); - - return HAL_OK; } else { hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); hsmartcard->TxXferCount--; - - return HAL_OK; } } - else - { - return HAL_BUSY; - } } +#if defined(USART_CR1_FIFOEN) +/** + * @brief Send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + for(nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(hsmartcard->TxXferCount == 0) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + } + else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + { + hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->TxXferCount--; + } + } + } +} +#endif + /** * @brief Wrap up transmission in non-blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); @@ -2217,62 +2525,133 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); } - + /* Tx process is ended, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - HAL_SMARTCARD_TxCpltCallback(hsmartcard); + /* Clear TxISR function pointer */ + hsmartcard->TxISR = NULL; - return HAL_OK; + HAL_SMARTCARD_TxCpltCallback(hsmartcard); } /** * @brief Receive an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). - * @retval HAL status + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) { /* Check that a Rx process is ongoing */ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - + if(--hsmartcard->RxXferCount == 0) { +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); +#else CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE); - +#endif + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - + /* Disable the SMARTCARD Parity Error Interrupt */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + HAL_SMARTCARD_RxCpltCallback(hsmartcard); - - return HAL_OK; } - - return HAL_OK; } else { /* Clear RXNE interrupt flag */ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); - - return HAL_BUSY; } } +#if defined(USART_CR1_FIFOEN) +/** + * @brief Receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + for(nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + + if(--hsmartcard->RxXferCount == 0) + { + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + + HAL_SMARTCARD_RxCpltCallback(hsmartcard); + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((hsmartcard->RxXferCount != 0U)) && (hsmartcard->RxXferCount < hsmartcard->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + } +} +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h index ad6d966b73..b6fe5b0436 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -66,7 +64,8 @@ typedef struct { uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: - Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */ + Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) + where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ @@ -97,7 +96,9 @@ typedef struct Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ - uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */ + uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. + This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied + by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -120,6 +121,11 @@ typedef struct disabled. Otherwise, its maximum value is 7 (before signalling an error) */ +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */ +#endif + }SMARTCARD_InitTypeDef; /** @@ -235,40 +241,53 @@ typedef enum /** * @brief SMARTCARD handle Structure definition */ -typedef struct +typedef struct __SMARTCARD_HandleTypeDef { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ - SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ + SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ - SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ + SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ - uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ + uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ - __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ - uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ + uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ - __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ +#if defined(USART_CR1_FIFOEN) + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - HAL_LockTypeDef Lock; /*!< Locking object */ + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ +#endif - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - uint32_t ErrorCode; /*!< SmartCard Error code */ + DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + uint32_t ErrorCode; /*!< SmartCard Error code */ }SMARTCARD_HandleTypeDef; @@ -297,7 +316,7 @@ typedef enum /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ -#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */ +#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */ /** * @} */ @@ -305,17 +324,17 @@ typedef enum /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits * @{ */ -#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */ -#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */ +#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */ +#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ /** * @} - */ - + */ + /** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ */ -#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */ -#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */ +#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */ +#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */ /** * @} */ @@ -323,9 +342,9 @@ typedef enum /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode * @{ */ -#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */ -#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */ -#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */ +#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */ +#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */ +#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */ /** * @} */ @@ -333,8 +352,8 @@ typedef enum /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity * @{ */ -#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) /*!< SMARTCARD frame low polarity */ -#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */ +#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */ +#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */ /** * @} */ @@ -342,8 +361,8 @@ typedef enum /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ -#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SMARTCARD frame phase on first clock transition */ -#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */ +#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */ +#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */ /** * @} */ @@ -351,8 +370,8 @@ typedef enum /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ -#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ -#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ +#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ +#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ /** * @} */ @@ -360,8 +379,8 @@ typedef enum /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method * @{ */ -#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame one-bit sample disabled */ -#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */ /** * @} */ @@ -370,8 +389,8 @@ typedef enum /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable * @{ */ -#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */ -#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD NACK transmission enabled */ +#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */ +#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */ /** * @} */ @@ -379,17 +398,39 @@ typedef enum /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable * @{ */ -#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD receiver timeout disabled */ -#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */ +#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */ +#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */ /** * @} */ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler + * @{ + */ +#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define SMARTCARD_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define SMARTCARD_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define SMARTCARD_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define SMARTCARD_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define SMARTCARD_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define SMARTCARD_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + +/** + * @} + */ +#endif + /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ -#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ /** * @} */ @@ -397,8 +438,8 @@ typedef enum /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ -#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ /** * @} */ @@ -406,8 +447,8 @@ typedef enum /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion * @{ */ -#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ -#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ /** * @} */ @@ -415,8 +456,8 @@ typedef enum /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap * @{ */ -#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ -#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ /** * @} */ @@ -424,8 +465,8 @@ typedef enum /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable * @{ */ -#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ -#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ /** * @} */ @@ -433,8 +474,8 @@ typedef enum /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error * @{ */ -#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ -#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ /** * @} */ @@ -442,8 +483,8 @@ typedef enum /** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first * @{ */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ /** * @} */ @@ -451,32 +492,8 @@ typedef enum /** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters * @{ */ -#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive data flush request */ -#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */ -/** - * @} - */ - -/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register - * @{ - */ -#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */ -/** - * @} - */ - -/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register - * @{ - */ -#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */ -/** - * @} - */ - -/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register - * @{ - */ -#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */ +#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */ +#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */ /** * @} */ @@ -484,7 +501,7 @@ typedef enum /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask * @{ */ -#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ /** * @} */ @@ -499,7 +516,7 @@ typedef enum */ /** @brief Reset SMARTCARD handle states. - * @param __HANDLE__: SMARTCARD handle. + * @param __HANDLE__ SMARTCARD handle. * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -508,7 +525,7 @@ typedef enum } while(0) /** @brief Flush the Smartcard Data registers. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ @@ -518,8 +535,8 @@ typedef enum } while(0) /** @brief Clear the specified SMARTCARD pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag @@ -527,86 +544,92 @@ typedef enum * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - @if STM32L443xx - * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) - @endif + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag * @retval None */ #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) /** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) /** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) /** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) /** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) /** @brief Check whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - @if STM32L443xx * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) - @endif * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref SMARTCARD_FLAG_BUSY Busy flag * @arg @ref SMARTCARD_FLAG_EOBF End of block flag * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag + * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag + * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag * @arg @ref SMARTCARD_FLAG_NE Noise error flag * @arg @ref SMARTCARD_FLAG_FE Framing error flag * @arg @ref SMARTCARD_FLAG_PE Parity error flag + * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag + * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag + * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag + * @arg @ref SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - /** @brief Enable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ @@ -614,20 +637,24 @@ typedef enum ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ @@ -636,51 +663,57 @@ typedef enum /** @brief Check whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt - * @arg @ref SMARTCARD_IT_NE Noise error interrupt - * @arg @ref SMARTCARD_IT_FE Framing error interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << ((__INTERRUPT__)>> 0x08U))) != RESET) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT__: specifies the SMARTCARD interrupt source to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - @if STM32L443xx - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) - @endif - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag @@ -688,19 +721,18 @@ typedef enum * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - @if STM32L443xx * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) - @endif * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag * @retval None */ -#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) +#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific SMARTCARD request flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request @@ -710,25 +742,25 @@ typedef enum #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the SMARTCARD one bit sample method. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -745,42 +777,42 @@ typedef enum /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz) * divided by the oversampling used on the SMARTCARD (i.e. 16). - * @param __BAUDRATE__: Baud rate set by the configuration function. + * @param __BAUDRATE__ Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001) /** @brief Check the block length range. * @note The maximum SMARTCARD block length is 0xFF. - * @param __LENGTH__: block length. + * @param __LENGTH__ block length. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) /** @brief Check the receiver timeout value. * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__: receiver timeout value. + * @param __TIMEOUTVALUE__ receiver timeout value. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** @brief Check the SMARTCARD autoretry counter value. * @note The maximum number of retransmissions is 0x7. - * @param __COUNT__: number of retransmissions. + * @param __COUNT__ number of retransmissions. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) /** * @brief Ensure that SMARTCARD frame length is valid. - * @param __LENGTH__: SMARTCARD frame length. + * @param __LENGTH__ SMARTCARD frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) /** * @brief Ensure that SMARTCARD frame number of stop bits is valid. - * @param __STOPBITS__: SMARTCARD frame number of stop bits. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ @@ -788,7 +820,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame parity is valid. - * @param __PARITY__: SMARTCARD frame parity. + * @param __PARITY__ SMARTCARD frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ @@ -796,28 +828,28 @@ typedef enum /** * @brief Ensure that SMARTCARD communication mode is valid. - * @param __MODE__: SMARTCARD communication mode. + * @param __MODE__ SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00)) +#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that SMARTCARD frame polarity is valid. - * @param __CPOL__: SMARTCARD frame polarity. + * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** * @brief Ensure that SMARTCARD frame phase is valid. - * @param __CPHA__: SMARTCARD frame phase. + * @param __CPHA__ SMARTCARD frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) /** * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. - * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ @@ -825,7 +857,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame sampling is valid. - * @param __ONEBIT__: SMARTCARD frame sampling. + * @param __ONEBIT__ SMARTCARD frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ @@ -833,7 +865,7 @@ typedef enum /** * @brief Ensure that SMARTCARD NACK transmission setting is valid. - * @param __NACK__: SMARTCARD NACK transmission setting. + * @param __NACK__ SMARTCARD NACK transmission setting. * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) */ #define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ @@ -841,15 +873,65 @@ typedef enum /** * @brief Ensure that SMARTCARD receiver timeout setting is valid. - * @param __TIMEOUT__: SMARTCARD receiver timeout setting. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) +/** + * @brief Ensure that SMARTCARD clock Prescaler is valid. + * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) + +/** + * @brief Ensure that SMARTCARD FIFO mode is valid. + * @param __STATE__ SMARTCARD FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that SMARTCARD TXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that SMARTCARD RXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + /** * @brief Ensure that SMARTCARD advanced features initialization is valid. - * @param __INIT__: SMARTCARD advanced features initialization. + * @param __INIT__ SMARTCARD advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ @@ -863,7 +945,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame TX inversion setting is valid. - * @param __TXINV__: SMARTCARD frame TX inversion setting. + * @param __TXINV__ SMARTCARD frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ @@ -871,7 +953,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame RX inversion setting is valid. - * @param __RXINV__: SMARTCARD frame RX inversion setting. + * @param __RXINV__ SMARTCARD frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ @@ -879,7 +961,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame data inversion setting is valid. - * @param __DATAINV__: SMARTCARD frame data inversion setting. + * @param __DATAINV__ SMARTCARD frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ @@ -887,7 +969,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. - * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ @@ -895,7 +977,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame overrun setting is valid. - * @param __OVERRUN__: SMARTCARD frame overrun setting. + * @param __OVERRUN__ SMARTCARD frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -903,7 +985,7 @@ typedef enum /** * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. - * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -911,7 +993,7 @@ typedef enum /** * @brief Ensure that SMARTCARD frame MSB first setting is valid. - * @param __MSBFIRST__: SMARTCARD frame MSB first setting. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -919,7 +1001,7 @@ typedef enum /** * @brief Ensure that SMARTCARD request parameter is valid. - * @param __PARAM__: SMARTCARD request parameter. + * @param __PARAM__ SMARTCARD request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c index a73b80ec74..6f17643d67 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SMARTCARD HAL module driver. * This file provides extended firmware functions to manage the following * functionalities of the SmartCard. @@ -73,13 +71,69 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /* Exported functions --------------------------------------------------------*/ /** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions * @{ */ -/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions +/** @defgroup SMARTCARDEx_Exported_Functions_Group2 IO operation functions + * @brief Extended SMARTCARD Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_SMARTCARDEx_RxFifoFullCallback() + (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief SMARTCARD RX Fifo full callback. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +__weak void HAL_SMARTCARDEx_RxFifoFullCallback (SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD TX Fifo empty callback. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback (SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} +#endif + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral Control functions * @brief Extended control functions * @verbatim @@ -92,6 +146,10 @@ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature + (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold @endverbatim * @{ @@ -99,21 +157,21 @@ /** * @brief Update on the fly the SMARTCARD block length in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @param BlockLength SMARTCARD block length (8-bit long at most) * @retval None */ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) { - MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS)); + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos)); } /** * @brief Update on the fly the receiver timeout value in RTOR register. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout * value must be less or equal to 0x0FFFFFFFF. * @retval None */ @@ -125,7 +183,7 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ /** * @brief Enable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -157,7 +215,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @brief Disable the SMARTCARD receiver timeout feature. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -187,6 +245,184 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef } } +#if defined(USART_CR1_FIFOEN) +/** + * @brief Enable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update TX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update RX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} +#endif /** * @} */ @@ -195,6 +431,47 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ +/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; + uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) + { + hsmartcard->NbTxDataToProcess = 1; + hsmartcard->NbRxDataToProcess = 1; + } + else + { + rx_fifo_depth = 8; /* RX Fifo size */ + tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + hsmartcard->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + } +} +#endif +/** + * @} + */ + #endif /* HAL_SMARTCARD_MODULE_ENABLED */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h index e2b7cbe68f..e59ba1112c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smartcard_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention @@ -70,50 +68,93 @@ #define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ /** * @} - */ - + */ + /** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ -#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ -#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ -#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ -#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ -#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ -#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ +#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */ -#endif /* USART_TCBGT_SUPPORT */ +#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */ +#endif /* USART_TCBGT_SUPPORT */ /** * @} */ +#if defined(USART_CR1_FIFOEN) +/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level + * @brief SMARTCARD TXFIFO level + * @{ + */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level + * @brief SMARTCARD RXFIFO level + * @{ + */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ +#endif - - /** @defgroup SMARTCARDEx_Flags SMARTCARD Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ -#endif /* USART_TCBGT_SUPPORT */ -#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ -#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ -#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ -#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ -#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ +#endif /* USART_TCBGT_SUPPORT */ +#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ +#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ +#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ +#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ +#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */ +#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */ +#else #define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ -#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#endif +#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */ +#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */ +#else #define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ -#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ -#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ -#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ -#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ -#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ +#endif +#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ +#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ +#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ +#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ +#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */ +#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */ +#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */ +#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */ +#endif /** * @} */ @@ -128,23 +169,35 @@ * - ZZZZZ : Flag position in the ISR register(5 bits) * @{ */ -#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */ -#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */ -#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */ -#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */ -#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */ +#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ +#endif +#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ +#endif +#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */ -#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */ -#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */ -#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */ -#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */ - -#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */ -#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */ +#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */ +#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */ -#endif /* USART_TCBGT_SUPPORT */ +#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ +#endif + +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */ +#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */ +#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */ +#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */ +#endif /** * @} */ @@ -154,13 +207,16 @@ */ #define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ #define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ -#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise detected clear flag */ #define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ #define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ +#if defined(USART_CR1_FIFOEN) +#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */ +#endif #define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ #if defined(USART_TCBGT_SUPPORT) #define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ -#endif /* USART_TCBGT_SUPPORT */ +#endif #define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ #define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ /** @@ -170,7 +226,27 @@ /** * @} */ + /* Exported macros -----------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Constants SMARTCARDEx Private Constants + * @{ + */ +#if defined(USART_CR1_FIFOEN) +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode + * @{ + */ +#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ +#endif +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros * @{ @@ -297,24 +373,24 @@ #endif /* STM32L432xx || STM32L442xx */ /** @brief Set the Transmission Completion flag - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). * @retval None */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ - do { \ - if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ - { \ +#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ + do { \ + if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ + { \ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } \ - else \ - { \ + } \ + else \ + { \ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ - } \ - } while(0) + } \ + } while(0) #else #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ do { \ @@ -323,22 +399,23 @@ #endif /** @brief Return the transmission completion flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is * reported. * @retval Transmission completion flag */ #if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) #else #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC) #endif - + + /** * @brief Ensure that SMARTCARD frame transmission completion used flag is valid. - * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag. + * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) */ #if defined(USART_TCBGT_SUPPORT) @@ -350,7 +427,7 @@ /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMARTCARDEx_Exported_Functions @@ -358,9 +435,22 @@ */ /* Initialization and de-initialization functions ****************************/ -/* IO operation methods *******************************************************/ +/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 + * @{ + */ -/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 +/* IO operation functions *****************************************************/ +#if defined(USART_CR1_FIFOEN) +void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard); +#endif + +/** + * @} + */ + + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 * @{ */ @@ -370,6 +460,13 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(USART_CR1_FIFOEN) +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); +#endif + /** * @} */ @@ -378,6 +475,9 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ + +/* Private functions ---------------------------------------------------------*/ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c index fdbd04224d..8aeaa1b497 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.c @@ -2,25 +2,23 @@ ****************************************************************************** * @file stm32l4xx_hal_smbus.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SMBUS HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, * based on I2C principles of operation : * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The SMBUS HAL driver can be used as follows: - + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: - SMBUS_HandleTypeDef hsmbus; + SMBUS_HandleTypeDef hsmbus; (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock @@ -28,7 +26,7 @@ (+++) Enable the clock for the SMBUS GPIOs (+++) Configure SMBUS pins as alternate function open-drain (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SMBUSx interrupt priority + (+++) Configure the SMBUSx interrupt priority (+++) Enable the NVIC SMBUS IRQ Channel (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, @@ -92,7 +90,7 @@ [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros - + @endverbatim ****************************************************************************** * @attention @@ -121,8 +119,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal.h" @@ -156,7 +154,7 @@ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -172,6 +170,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); + static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} @@ -184,19 +184,19 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and + [..] This subsection provides a set of functions allowing to initialize and deinitialize the SMBUSx peripheral: - (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, IT and NVIC ). - (+) Call the function HAL_SMBUS_Init() to configure the selected device with + (+) Call the function HAL_SMBUS_Init() to configure the selected device with the selected configuration: (++) Clock Timing (++) Bus Timeout @@ -212,31 +212,31 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre (++) Peripheral mode - (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration - of the selected SMBUSx peripheral. + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx peripheral. (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and - HAL_SMBUS_ConfigDigitalFilter(). + HAL_SMBUS_ConfigDigitalFilter(). @endverbatim * @{ */ /** - * @brief Initialize the SMBUS according to the specified parameters + * @brief Initialize the SMBUS according to the specified parameters * in the SMBUS_InitTypeDef and initialize the associated handle. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) -{ +{ /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); @@ -250,7 +250,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); - if(hsmbus->State == HAL_SMBUS_STATE_RESET) + if (hsmbus->State == HAL_SMBUS_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; @@ -258,17 +258,17 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); } - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); - - /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ /* Configure SMBUSx: Frequency range */ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ /* Configure SMBUSx: Bus Timeout */ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; @@ -277,10 +277,10 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - if(hsmbus->Init.OwnAddress1 != 0U) + + if (hsmbus->Init.OwnAddress1 != 0U) { - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); } @@ -292,41 +292,41 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ /* Configure SMBUSx: Addressing Master mode */ - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) { hsmbus->Instance->CR2 = (I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ /* AUTOEND and NACK bit will be manage during Transfer process */ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); - + /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) + && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } /* Enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitialize the SMBUS peripheral. + * @brief DeInitialize the SMBUS peripheral. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -334,29 +334,29 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; - + /* Disable the SMBUS Peripheral Clock */ __HAL_SMBUS_DISABLE(hsmbus); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_SMBUS_MspDeInit(hsmbus); - + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; hsmbus->State = HAL_SMBUS_STATE_RESET; - - /* Release Lock */ + + /* Release Lock */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } @@ -373,7 +373,7 @@ __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspInit could be implemented in the user file - */ + */ } /** @@ -389,7 +389,7 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspDeInit could be implemented in the user file - */ + */ } /** @@ -407,7 +407,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); @@ -453,7 +453,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); @@ -490,20 +490,19 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin } } - /** * @} */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the SMBUS data + This subsection provides a set of functions allowing to manage the SMBUS data transfers. (#) Blocking mode function to check if device is ready for usage is : @@ -512,7 +511,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin (#) There is only one mode of transfer: (++) Non-Blocking mode : The communication is performed using Interrupts. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the + The end of the data processing will be indicated through the dedicated SMBUS IRQ when using Interrupt mode. (#) Non-Blocking mode functions with Interrupt are : @@ -550,15 +549,15 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ +{ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; /* Prepare transfer parameters */ @@ -568,12 +567,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -584,17 +583,17 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -603,32 +602,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); - + return HAL_OK; } else { return HAL_BUSY; - } + } } /** @@ -647,27 +646,27 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Prepare transfer parameters */ hsmbus->pBuffPtr = pData; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; - + /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - - if(Size > MAX_NBYTE_SIZE) + + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -675,20 +674,20 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 { hsmbus->XferSize = Size; } - + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -697,24 +696,24 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -728,18 +727,18 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) { - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); - + /* Keep the same state as previous */ /* to perform as well the call of the corresponding end of transfer callback */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; } - else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; } @@ -750,32 +749,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ return HAL_ERROR; } hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); } - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -792,11 +791,11 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ @@ -804,10 +803,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -822,7 +821,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Convert OTHER_xxx XferOptions if any */ SMBUS_ConvertOtherXferOptions(hsmbus); - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -832,32 +831,32 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } - + /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -867,8 +866,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } else { - return HAL_ERROR; - } + return HAL_ERROR; + } } /** @@ -885,22 +884,22 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + /* Set SBC bit to manage Acknowledge at each bit */ hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -921,7 +920,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -932,12 +931,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + __HAL_UNLOCK(hsmbus); - /* Note : The SMBUS interrupts must be enabled after unlocking current process + /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ @@ -947,7 +946,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ } else { - return HAL_ERROR; + return HAL_ERROR; } } @@ -960,10 +959,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) { hsmbus->State = HAL_SMBUS_STATE_LISTEN; - + /* Enable the Address Match interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } @@ -976,13 +975,13 @@ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) { /* Disable Address listen mode only if a transfer is not ongoing */ - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Disable the Address Match interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); - + return HAL_OK; } else @@ -1000,7 +999,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; /* Clear ALERT flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); @@ -1008,7 +1007,7 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) /* Enable Alert Interrupt */ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** * @brief Disable the SMBUS alert mode with Interrupt. @@ -1019,16 +1018,16 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) { /* Enable SMBus alert */ - hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; - + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + /* Disable Alert Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); - return HAL_OK; + return HAL_OK; } /** - * @brief Check if target device is ready for communication. + * @brief Check if target device is ready for communication. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress Target device address: The device 7 bits address value @@ -1038,72 +1037,72 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ +{ uint32_t tickstart = 0U; - + __IO uint32_t SMBUS_Trials = 0U; - - if(hsmbus->State == HAL_SMBUS_STATE_READY) + + if (hsmbus->State == HAL_SMBUS_STATE_READY) { - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hsmbus); - + hsmbus->State = HAL_SMBUS_STATE_BUSY; hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - + do { /* Generate Start */ - hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); - + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); return HAL_TIMEOUT; } - } + } } - + /* Check if the NACKF flag has not been set */ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_OK; } else { - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -1114,31 +1113,32 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Clear STOP Flag, auto generated with autoend*/ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - + /* Check if the maximum allowed number of trials has been reached */ if (SMBUS_Trials++ == Trials) { /* Generate Stop */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - }while(SMBUS_Trials < Trials); + } + } + while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; - } + } else { return HAL_BUSY; @@ -1161,28 +1161,28 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t tmpisrvalue = 0U; - + /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); - + /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) - { + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Master_ISR(hsmbus); } } - + /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1190,15 +1190,15 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Master_ISR(hsmbus); } - } - - /* SMBUS in mode Listener Only --------------------------------------------------*/ + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) - && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { @@ -1215,79 +1215,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) */ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); - } - - /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); - } - - /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); - } - - /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; - - /* Clear TIMEOUT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); - } - - /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; - - /* Clear ALERT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); - } - - /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; - - /* Clear PEC error flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); - } - - /* Call the Error Callback in case of Error detected */ - if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) - { - /* Do not Reset the HAL state in case of ALERT error */ - if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) - { - if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) - { - /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ - /* keep HAL_SMBUS_STATE_LISTEN if set */ - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_LISTEN; - } - } - - /* Call the Error callback to prevent upper layer */ - HAL_SMBUS_ErrorCallback(hsmbus); - } + SMBUS_ITErrorHandler(hsmbus); } /** @@ -1303,7 +1231,7 @@ __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1334,7 +1262,7 @@ __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file - */ + */ } /** @@ -1357,8 +1285,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @brief Slave Address Match callback. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param TransferDirection: Master request Transfer Direction (Write/Read) - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -1402,22 +1330,22 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_ErrorCallback() could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1449,14 +1377,14 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) /** * @} - */ + */ /** * @} - */ + */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1466,42 +1394,45 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) { uint16_t DevAddress; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - + /* Set corresponding Error Code */ /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ /* Disable the selected SMBUS peripheral */ __HAL_SMBUS_DISABLE(hsmbus); @@ -1511,21 +1442,21 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + /* REenable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1537,64 +1468,64 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - + /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) - { + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferSize--; - hsmbus->XferCount--; + hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); - - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } } - else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U)) + else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ - if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1603,10 +1534,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1614,30 +1545,30 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Specific use case for Quick command */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { /* Generate a Stop command */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; } /* Call TxCpltCallback() if no stop mode is set */ - else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ - + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1646,10 +1577,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1657,39 +1588,39 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } } } - + /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { uint8_t TransferDirection = 0U; uint16_t SlaveAddrCode = 0U; /* Process Locked */ __HAL_LOCK(hsmbus); - - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Check that SMBUS transfer finished */ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1711,58 +1642,58 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to prevent upper layer */ + + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) { TransferDirection = SMBUS_GET_DIR(hsmbus); SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); - + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ /* Other ADDRInterrupt will be treat in next Listen usecase */ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); /* Call Slave Addr callback */ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); } - else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) { - if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; - if(hsmbus->XferCount == 1U) + if (hsmbus->XferCount == 1U) { /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } - else if(hsmbus->XferCount == 0U) + else if (hsmbus->XferCount == 0U) { /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ hsmbus->PreviousState = hsmbus->State; hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1777,13 +1708,13 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; } - } - else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + } + else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { - if(hsmbus->XferCount > MAX_NBYTE_SIZE) - { + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -1793,7 +1724,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1802,21 +1733,21 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hsmbus->XferCount > 0U) + if (hsmbus->XferCount > 0U) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferCount--; hsmbus->XferSize--; } - - if(hsmbus->XferCount == 0U) + + if (hsmbus->XferCount == 0U) { /* Last Byte is Transmitted */ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ @@ -1833,17 +1764,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } /* Check if STOPF is set */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1861,30 +1792,30 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear Configuration Register 2 */ SMBUS_RESET_CR2(hsmbus); - + /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Clear ADDR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); hsmbus->XferOptions = 0U; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ HAL_SMBUS_ListenCpltCallback(hsmbus); } } /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} + + return HAL_OK; +} /** * @brief Manage the enabling of Interrupts. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -1892,40 +1823,40 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { /* Enable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Enable ERR, TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Enable ERR, TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; } - + /* Enable interrupts only at the end */ /* to avoid the risk of SMBUS interrupt handle execution before */ /* all interrupts requested done */ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); - return HAL_OK; + return HAL_OK; } /** * @brief Manage the disabling of Interrupts. @@ -1934,60 +1865,60 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) +static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) + if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Disable TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) - { - /* Disable ERR interrupt */ - tmpisr |= SMBUS_IT_ERRI; - } - - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) - { - /* Disable STOPI, NACKI */ - tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; - } - } - - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) - { - /* Disable TC, STOP, NACK, RXI interrupt */ - tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Disable TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOPI, NACKI */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1998,9 +1929,95 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); - + return HAL_OK; } + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t itflags = READ_REG(hsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Call the Error Callback in case of Error detected */ + if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } +} + /** * @brief Handle SMBUS Communication Timeout. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -2010,26 +2027,26 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ uint32_t tickstart = HAL_GetTick(); - + /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + if (Status == RESET) + { + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } @@ -2037,25 +2054,25 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu } else { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; - + hsmbus->State = HAL_SMBUS_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - + return HAL_TIMEOUT; } } } } - return HAL_OK; + return HAL_OK; } /** @@ -2080,26 +2097,15 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); - - /* Get the CR2 register value */ - tmpreg = hsmbus->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - + /* update CR2 register */ - hsmbus->Instance->CR2 = tmpreg; -} + MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); +} /** * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. @@ -2111,14 +2117,14 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ /* set XferOptions to SMBUS_FIRST_FRAME */ - if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) { hsmbus->XferOptions = SMBUS_FIRST_FRAME; } /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ /* it request implicitly to generate a restart condition */ /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ - else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) { hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; } @@ -2126,7 +2132,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* it request implicitly to generate a restart condition */ /* then generate a stop condition at the end of transfer */ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ - else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; } @@ -2134,7 +2140,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* it request implicitly to generate a restart condition */ /* then generate a stop condition at the end of transfer */ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ - else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h index 9582dc5188..bc7dba982d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_smbus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_smbus.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention @@ -40,11 +38,11 @@ #define __STM32L4xx_HAL_SMBUS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" +#include "stm32l4xx_hal_def.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -52,25 +50,25 @@ /** @addtogroup SMBUS * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Types SMBUS Exported Types * @{ - */ - + */ + /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition - * @brief SMBUS Configuration Structure definition + * @brief SMBUS Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization + This parameter calculated by referring to SMBUS initialization section in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. This parameter can be a value of @ref SMBUS_Analog_Filter */ - + uint32_t OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ @@ -99,51 +97,51 @@ typedef struct This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section in Reference manual */ } SMBUS_InitTypeDef; -/** +/** * @} */ /** @defgroup HAL_state_definition HAL state definition - * @brief HAL State definition + * @brief HAL State definition * @{ - */ + */ #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ -/** +/** * @} */ /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition - * @brief SMBUS Error Code definition + * @brief SMBUS Error Code definition * @{ - */ + */ #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ -/** +/** * @} */ -/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition - * @brief SMBUS handle Structure definition +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition + * @brief SMBUS handle Structure definition * @{ */ typedef struct @@ -168,11 +166,11 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ -}SMBUS_HandleTypeDef; +} SMBUS_HandleTypeDef; /** * @} */ - + /** * @} */ @@ -281,9 +279,9 @@ typedef struct */ #define SMBUS_NO_STARTSTOP (0x00000000U) -#define SMBUS_GENERATE_STOP I2C_CR2_STOP -#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define SMBUS_GENERATE_START_WRITE I2C_CR2_START +#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ @@ -298,7 +296,7 @@ typedef struct */ #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) -#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) @@ -340,7 +338,7 @@ typedef struct * Elements values convention: 0xXXXXYYYY * - XXXXXXXX : Flag mask * @{ - */ + */ #define SMBUS_FLAG_TXE I2C_ISR_TXE #define SMBUS_FLAG_TXIS I2C_ISR_TXIS @@ -369,8 +367,8 @@ typedef struct /* Exported macros ------------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros * @{ - */ - + */ + /** @brief Reset SMBUS handle state. * @param __HANDLE__ specifies the SMBUS Handle. * @retval None @@ -388,7 +386,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) @@ -404,11 +402,11 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified SMBUS interrupt source is enabled or not. * @param __HANDLE__ specifies the SMBUS Handle. * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. @@ -420,7 +418,7 @@ typedef struct * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable * @arg @ref SMBUS_IT_RXI RX interrupt enable * @arg @ref SMBUS_IT_TXI TX interrupt enable - * + * * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) @@ -429,69 +427,69 @@ typedef struct * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag - * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) - * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert * @arg @ref SMBUS_FLAG_BUSY Bus busy * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) - * + * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) - + /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert - * + * * @retval None */ #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - + /** @brief Enable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. - * @param __HANDLE__ specifies the SMBUS Handle. + * @param __HANDLE__ specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} - */ - - + */ + + /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -517,7 +515,7 @@ typedef struct ((MASK) == SMBUS_OA2_MASK04) || \ ((MASK) == SMBUS_OA2_MASK05) || \ ((MASK) == SMBUS_OA2_MASK06) || \ - ((MASK) == SMBUS_OA2_MASK07)) + ((MASK) == SMBUS_OA2_MASK07)) #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ ((CALL) == SMBUS_GENERALCALL_ENABLE)) @@ -540,8 +538,8 @@ typedef struct ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) - - + + #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ ((REQUEST) == SMBUS_GENERATE_START_READ) || \ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ @@ -581,7 +579,7 @@ typedef struct /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions @@ -591,13 +589,13 @@ typedef struct /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - + /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); /** @@ -607,7 +605,7 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions * @{ */ - + /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling * @{ @@ -654,7 +652,7 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); * @} */ -/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions * @{ */ @@ -668,7 +666,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup SMBUS_Private_Functions SMBUS Private Functions @@ -677,19 +675,19 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /* Private functions are defined in stm32l4xx_hal_smbus.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c index 95068ef614..46029adbbb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -35,7 +33,7 @@ (+++) Enable the DMAx clock (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel - (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS @@ -54,17 +52,15 @@ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks [..] Master Receive mode restriction: - (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI does not initiate a new transfer the following procedure has to be respected: (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() [..] - The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI - modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the - maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on - the APBx peripheral clock frequency (fPCLK) used by the SPI instance. - + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. @endverbatim @@ -267,7 +263,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -366,7 +362,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } #endif /* USE_SPI_CRC */ - /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */ + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); @@ -392,7 +388,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -426,7 +422,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -442,7 +438,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -495,11 +491,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -507,7 +503,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -679,11 +674,11 @@ error: /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -693,7 +688,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 #endif /* USE_SPI_CRC */ uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { @@ -747,12 +741,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Set the Rx Fifo threshold */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -910,12 +904,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, @@ -929,7 +923,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -986,12 +979,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Set the Rx Fifo threshold */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) { - /* set fiforxthreshold according the reception data length: 16bit */ + /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthreshold according the reception data length: 8bit */ + /* Set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1071,7 +1064,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { - /* check TXE flag */ + /* Check TXE flag */ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { if (hspi->TxXferCount > 1U) @@ -1112,7 +1105,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->RxXferCount -= 2U; if (hspi->RxXferCount <= 1U) { - /* set fiforxthresold before to switch on 8 bit data size */ + /* Set RX Fifo threshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } @@ -1186,13 +1179,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } error : @@ -1203,16 +1192,15 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1287,16 +1275,15 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { @@ -1336,13 +1323,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Set fiforxthresold according the reception data length: 16 bit */ + /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { - /* Set fiforxthresold according the reception data length: 8 bit */ + /* Set RX Fifo threshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } @@ -1392,18 +1379,17 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1474,12 +1460,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check if packing mode is enabled and if there is more than 2 data to receive */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) { - /* Set fiforxthresold according the reception data length: 16 bit */ + /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* Set fiforxthresold according the reception data length: 8 bit */ + /* Set RX Fifo threshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1501,17 +1487,17 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - - /* check tx dma handle */ + + /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); /* Check Direction parameter */ @@ -1614,25 +1600,25 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - - /* check rx dma handle */ + + /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; - - /* check tx dma handle */ + + /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ @@ -1685,17 +1671,17 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* Set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -1747,12 +1733,12 @@ error: /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, @@ -1760,8 +1746,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - - /* check rx & tx dma handles */ + + /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1813,8 +1799,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } #endif /* USE_SPI_CRC */ - - /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); @@ -1826,7 +1810,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } else { - /* Set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) @@ -1845,7 +1829,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* Set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -2268,7 +2252,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2288,7 +2272,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2307,8 +2291,8 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) } /** - * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2339,7 +2323,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2434,8 +2418,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /** - * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2450,8 +2434,8 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2466,8 +2450,8 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2482,8 +2466,8 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2498,8 +2482,8 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2514,8 +2498,8 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2530,8 +2514,8 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2584,7 +2568,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2596,7 +2580,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2620,8 +2604,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ /** - * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2667,8 +2651,8 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2759,7 +2743,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2844,7 +2828,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2857,7 +2841,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2870,7 +2854,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2883,7 +2867,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -3041,7 +3025,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3055,7 +3039,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount -= 2U; if (hspi->RxXferCount == 1U) { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } @@ -3066,7 +3050,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount--; } - /* check end of the reception */ + /* Check end of the reception */ if (hspi->RxXferCount == 0U) { #if (USE_SPI_CRC != 0U) @@ -3091,7 +3075,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3107,7 +3091,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) hspi->CRCSize--; - /* check end of the reception */ + /* Check end of the reception */ if (hspi->CRCSize == 0U) { /* Disable RXNE and ERR interrupt */ @@ -3123,7 +3107,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3143,7 +3127,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->TxXferCount--; } - /* check the end of the transmission */ + /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) { #if (USE_SPI_CRC != 0U) @@ -3169,7 +3153,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3203,7 +3187,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3227,7 +3211,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3265,7 +3249,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3290,7 +3274,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3323,7 +3307,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3346,7 +3330,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3379,7 +3363,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3403,7 +3387,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3428,13 +3412,13 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, @@ -3480,13 +3464,13 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, } /** - * @brief Handle SPI FIFO Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Fifo: Fifo to check - * @param State: Fifo state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, @@ -3542,10 +3526,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle the check of the RX transaction complete. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3579,9 +3563,9 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t /** * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3592,6 +3576,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { @@ -3605,12 +3590,13 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + return HAL_OK; } /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3667,7 +3653,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3709,7 +3695,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3748,22 +3734,22 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { __IO uint32_t count; - + /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); - + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - + /* Check RXNEIE is disabled */ do { @@ -3792,19 +3778,19 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx/Tx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) { __IO uint32_t count; - + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - + /* Check TXEIE is disabled */ do { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h index 0be73f9243..3aa540374e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -398,16 +396,16 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -417,9 +415,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI handle. + * @param __HANDLE__ specifies the SPI handle. * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to disable. + * @param __INTERRUPT__ specifies the interrupt source to disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -429,9 +427,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -441,9 +439,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -459,14 +457,14 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -479,7 +477,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -492,7 +490,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -504,14 +502,14 @@ typedef struct __SPI_HandleTypeDef }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -527,92 +525,168 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ - ((MODE) == SPI_MODE_MASTER)) +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) -#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((MODE) == SPI_DIRECTION_1LINE)) +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) -#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_1LINE)) +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_15BIT) || \ - ((DATASIZE) == SPI_DATASIZE_14BIT) || \ - ((DATASIZE) == SPI_DATASIZE_13BIT) || \ - ((DATASIZE) == SPI_DATASIZE_12BIT) || \ - ((DATASIZE) == SPI_DATASIZE_11BIT) || \ - ((DATASIZE) == SPI_DATASIZE_10BIT) || \ - ((DATASIZE) == SPI_DATASIZE_9BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT) || \ - ((DATASIZE) == SPI_DATASIZE_7BIT) || \ - ((DATASIZE) == SPI_DATASIZE_6BIT) || \ - ((DATASIZE) == SPI_DATASIZE_5BIT) || \ - ((DATASIZE) == SPI_DATASIZE_4BIT)) +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_4BIT)) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ - ((CPOL) == SPI_POLARITY_HIGH)) +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ - ((CPHA) == SPI_PHASE_2EDGE)) +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ - ((NSS) == SPI_NSS_HARD_INPUT) || \ - ((NSS) == SPI_NSS_HARD_OUTPUT)) +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) -#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ - ((NSSP) == SPI_NSS_PULSE_DISABLE)) +/** @brief Checks if SPI NSS Pulse parameter is in allowed range. + * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. + * This parameter can be a value of @ref SPI_NSSP_Mode + * @retval None + */ +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ - ((BIT) == SPI_FIRSTBIT_LSB)) +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ - ((MODE) == SPI_TIMODE_ENABLE)) +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_16BIT)) +/** @brief Checks if SPI CRC length is in allowed range. + * @param __LENGTH__ specifies the SPI CRC length. + * This parameter can be a value of @ref SPI_CRC_length + * @retval None + */ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) - -#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL) +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c index 543a289eb7..813a8ff429 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended SPI HAL module driver. * This file provides firmware functions to manage the following * SPI peripheral extended functionalities : @@ -65,7 +63,7 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions * @{ @@ -90,8 +88,8 @@ */ /** - * @brief Flush the RX fifo. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Flush the RX fifo. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h index 1835b59de3..99261d60be 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_spi_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SPI HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c index caec73775b..69aa39213e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sram.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -95,7 +93,8 @@ #include "stm32l4xx_hal.h" #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_HAL_Driver * @{ @@ -695,5 +694,6 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h index 4c3cb948f3..9eea5ab71b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sram.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_sram.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -44,7 +42,8 @@ #endif #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_ll_fmc.h" @@ -192,6 +191,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c index 19e029ec23..68b1309688 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_swpmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SWPMI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Single Wire Protocol Master Interface (SWPMI). diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h index 1f78f9d82e..2df60ff9ac 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_swpmi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_swpmi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SWPMI HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c index 3b2fd25ce5..f60505f99c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -192,7 +190,11 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Base handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) @@ -207,6 +209,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -231,7 +234,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM Base peripheral - * @param htim: TIM Base handle + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) @@ -258,7 +261,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -273,7 +276,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Base MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -289,7 +292,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) @@ -312,7 +315,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) @@ -335,7 +338,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) @@ -355,7 +358,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) @@ -374,9 +377,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim : TIM handle - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. + * @param htim TIM handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -420,7 +423,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) @@ -469,7 +472,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Output Compare handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) @@ -484,6 +491,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -508,7 +516,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM Output Compare handle + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) @@ -535,7 +543,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -550,7 +558,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -565,8 +573,8 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -599,8 +607,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -633,8 +641,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -701,8 +709,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -769,8 +777,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -778,8 +786,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -890,8 +898,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -987,7 +995,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) @@ -1002,6 +1014,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1026,7 +1039,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1053,7 +1066,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1068,7 +1081,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM PWM MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1083,8 +1096,8 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1117,8 +1130,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1154,8 +1167,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1220,8 +1233,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1286,15 +1299,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1405,8 +1418,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1500,7 +1513,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Input Capture handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) @@ -1515,6 +1532,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1539,7 +1557,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM Input Capture handle + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) @@ -1566,7 +1584,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1581,7 +1599,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Input Capture MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) @@ -1596,8 +1614,8 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1622,8 +1640,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1648,8 +1666,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1707,8 +1725,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1767,15 +1785,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1881,9 +1899,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /** - * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be disabled + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1971,8 +1989,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM OnePulse handle - * @param OnePulseMode: Select the One pulse mode. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM OnePulse handle + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. @@ -1991,6 +2013,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -2021,7 +2044,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitialize the TIM One Pulse - * @param htim: TIM One Pulse handle + * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) @@ -2048,7 +2071,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2063,7 +2086,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2078,8 +2101,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2114,8 +2137,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be disable + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2150,8 +2173,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2192,8 +2215,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2258,8 +2281,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Encoder Interface configuration structure + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2276,6 +2303,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2349,7 +2379,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitialize the TIM Encoder interface - * @param htim: TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2376,7 +2406,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2391,7 +2421,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2406,8 +2436,8 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2433,7 +2463,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); } break; - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2450,8 +2480,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2461,9 +2491,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Disable the Input Capture channels 1 and 2 + /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { @@ -2472,13 +2502,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); } break; - + case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); } break; - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -2496,8 +2526,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2519,14 +2549,14 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -2546,8 +2576,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2597,15 +2627,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2717,8 +2747,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2784,7 +2814,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) @@ -2940,9 +2970,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle - * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to configure + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2973,7 +3003,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 1 in Output Compare */ + /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); } break; @@ -2991,7 +3021,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, case TIM_CHANNEL_3: { /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); @@ -3042,9 +3072,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: TIM IC handle - * @param sConfig: TIM Input Capture configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3139,9 +3169,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM PWM handle - * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be configured + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3284,13 +3314,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: TIM One Pulse handle - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel : TIM Channels to be enabled + * @param InputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3306,89 +3336,90 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O if(OutputChannel != InputChannel) { - /* Process Locked */ - __HAL_LOCK(htim); + /* Process Locked */ + __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; + htim->State = HAL_TIM_STATE_BUSY; - /* Extract the Ouput compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; + /* Extract the Ouput compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; switch (OutputChannel) - { - case TIM_CHANNEL_1: { + case TIM_CHANNEL_1: + { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { + TIM_OC1_SetConfig(htim->Instance, &temp1); + } + break; + case TIM_CHANNEL_2: + { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - TIM_OC2_SetConfig(htim->Instance, &temp1); + TIM_OC2_SetConfig(htim->Instance, &temp1); + } + break; + default: + break; } - break; - default: - break; - } + switch (InputChannel) - { - case TIM_CHANNEL_1: { + case TIM_CHANNEL_1: + { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Select the Trigger source */ + /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; + htim->Instance->SMCR |= TIM_TS_TI1FP1; - /* Select the Slave Mode */ + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + case TIM_CHANNEL_2: + { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC2PSC Bits */ + /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - /* Select the Trigger source */ + /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; + htim->Instance->SMCR |= TIM_TS_TI2FP2; - /* Select the Slave Mode */ + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + } + break; + + default: + break; } - break; - default: - break; + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} else { return HAL_ERROR; @@ -3397,8 +3428,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3419,7 +3450,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3428,8 +3459,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ @@ -3560,8 +3591,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3620,8 +3651,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3642,7 +3673,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3651,8 +3682,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ @@ -3784,8 +3815,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3844,8 +3875,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim: TIM handle - * @param EventSource: specifies the event source. + * @param htim TIM handle + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3856,7 +3887,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) @@ -3885,10 +3916,10 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 @@ -3917,7 +3948,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - + /* Clear the OCREF clear selection bit */ tmpsmcr &= ~TIM_SMCR_OCCS; @@ -3952,7 +3983,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, htim->Instance->SMCR |= TIM_SMCR_OCCS; } break; - + default: break; } @@ -4054,8 +4085,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /** * @brief Configures the clock source to be used - * @param htim: TIM handle - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4096,7 +4127,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -4122,7 +4153,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, @@ -4141,20 +4172,20 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); } break; - + case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - /* Check TI2 input conditioning related parameters */ + /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); @@ -4180,7 +4211,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); } break; - + case TIM_CLOCKSOURCE_ITR0: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4189,7 +4220,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); } break; - + case TIM_CLOCKSOURCE_ITR1: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4198,7 +4229,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); } break; - + case TIM_CLOCKSOURCE_ITR2: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4207,7 +4238,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); } break; - + case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ @@ -4230,8 +4261,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: TIM handle. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4264,8 +4295,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4283,7 +4314,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI htim->State = HAL_TIM_STATE_BUSY; TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - + /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); @@ -4292,28 +4323,28 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); + __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - + __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; @@ -4328,15 +4359,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); + __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Read the captured value from Capture Compare unit - * @param htim: TIM handle. - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4428,7 +4459,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) @@ -4443,7 +4474,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non-blocking mode - * @param htim : TIM OC handle + * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) @@ -4457,7 +4488,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Input Capture callback in non-blocking mode - * @param htim : TIM IC handle + * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) @@ -4472,7 +4503,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) @@ -4487,7 +4518,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) @@ -4502,7 +4533,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) @@ -4536,7 +4567,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base handle state. - * @param htim: TIM Base handle + * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) @@ -4546,7 +4577,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC handle state. - * @param htim: TIM Ouput Compare handle + * @param htim TIM Ouput Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4556,7 +4587,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM handle state. - * @param htim: TIM handle + * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) @@ -4566,7 +4597,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture handle state. - * @param htim: TIM IC handle + * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) @@ -4576,7 +4607,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode handle state. - * @param htim: TIM OPM handle + * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) @@ -4586,7 +4617,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode handle state. - * @param htim: TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4600,7 +4631,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA error callback - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) @@ -4614,7 +4645,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) @@ -4646,7 +4677,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) } /** * @brief TIM DMA Capture complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) @@ -4679,7 +4710,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) @@ -4693,7 +4724,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) @@ -4707,8 +4738,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: TIM Base configuration structure + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4731,6 +4762,10 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= (uint32_t)Structure->ClockDivision; } + /* Set the auto-reload preload */ + tmpcr1 &= ~TIM_CR1_ARPE; + tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; + TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ @@ -4753,7 +4788,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Time Ouput Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4827,7 +4862,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4903,7 +4938,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4977,7 +5012,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -5035,7 +5070,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Ouput Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -5088,7 +5123,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Ouput Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -5161,7 +5196,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - + /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { @@ -5173,91 +5208,91 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - + tmpccmr1 = htim->Instance->CCMR1; + /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - + /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - + htim->Instance->CCER = tmpccer; + } break; - + case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_ITR0: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR1: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR2: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + default: break; } @@ -5266,17 +5301,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 @@ -5321,12 +5356,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5356,17 +5391,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 @@ -5404,12 +5439,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5439,17 +5474,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 @@ -5487,17 +5522,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be @@ -5535,7 +5570,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param InputTriggerSource: The Input Trigger source. + * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 @@ -5563,17 +5598,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ @@ -5597,7 +5632,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h index 368389fdd2..bfc0194b00 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -85,6 +83,9 @@ typedef struct - the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** @@ -463,6 +464,15 @@ typedef struct * @} */ +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ +/** + * @} + */ + /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ @@ -472,15 +482,6 @@ typedef struct * @} */ -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) -/** - * @} - */ - /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ @@ -490,6 +491,15 @@ typedef struct * @} */ +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) +/** + * @} + */ + /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ @@ -593,9 +603,9 @@ typedef struct * @} */ -/** @defgroup TIM_Commutation_Source TIM Commutation Source +/** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ - */ + */ #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) /** @@ -656,16 +666,16 @@ typedef struct /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) /** * @} */ @@ -781,7 +791,7 @@ typedef struct * @{ */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) /** * @} */ @@ -800,14 +810,14 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) /** * @} */ @@ -815,22 +825,22 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) -#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) -#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) -#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_RESET ((uint32_t)0x00000000) +#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) +#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) +#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) +#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) /** * @} */ @@ -999,28 +1009,28 @@ typedef struct */ /** @brief Reset TIM handle state. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -1036,7 +1046,7 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ @@ -1053,15 +1063,15 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1077,8 +1087,8 @@ typedef struct /** @brief Disable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1093,8 +1103,8 @@ typedef struct #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1103,14 +1113,13 @@ typedef struct * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @arg TIM_DMA_BREAK: Break DMA request * @retval None */ #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1119,14 +1128,13 @@ typedef struct * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @arg TIM_DMA_BREAK: Break DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to check. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1134,11 +1142,11 @@ typedef struct * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1149,8 +1157,8 @@ typedef struct #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to clear. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1158,11 +1166,11 @@ typedef struct * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1174,8 +1182,8 @@ typedef struct /** * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1190,8 +1198,8 @@ typedef struct #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1207,7 +1215,7 @@ typedef struct /** * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. @@ -1217,32 +1225,32 @@ mode. /** * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __PRESC__: specifies the Prescaler new value. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ @@ -1253,20 +1261,20 @@ mode. /** * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1 - * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ @@ -1278,22 +1286,25 @@ mode. /** * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__: TIM handle. - * @retval None + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1309,14 +1320,18 @@ mode. /** * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ @@ -1326,8 +1341,8 @@ mode. /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1335,7 +1350,7 @@ mode. * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -1348,8 +1363,8 @@ mode. /** * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value @@ -1357,7 +1372,7 @@ mode. * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @arg TIM_CHANNEL_5: get capture/compare 5 register value * @arg TIM_CHANNEL_6: get capture/compare 6 register value - * @retval None + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ @@ -1367,10 +1382,52 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__: TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None @@ -1380,9 +1437,9 @@ mode. /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__: TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if + * @param __HANDLE__ TIM handle. + * @note When the USR bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit @@ -1391,17 +1448,17 @@ mode. */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) - + /** * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge @@ -1412,7 +1469,7 @@ mode. TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) - + /** * @} */ @@ -1430,7 +1487,7 @@ mode. * @} */ /* End of private constants --------------------------------------------------*/ - + /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ @@ -1466,7 +1523,7 @@ mode. ((__BASE__) == TIM_DMABASE_OR3)) -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ @@ -1479,6 +1536,9 @@ mode. ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ ((__STATE__) == TIM_OCFAST_ENABLE)) @@ -1514,7 +1574,7 @@ mode. ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12)) -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1963,7 +2023,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); /** * @} -*/ +*/ /* End of private functions --------------------------------------------------*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c index 39039e4c42..754c1a7116 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -113,7 +111,7 @@ /* Private define ------------------------------------------------------------*/ #define BDTR_BKF_SHIFT (16) #define BDTR_BK2F_SHIFT (20) -#define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000) +#define TIMx_ETRSEL_MASK ((uint32_t)0x0003C000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -150,8 +148,8 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Hall Sensor configuration structure + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -164,9 +162,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen return HAL_ERROR; } - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -229,7 +228,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitialize the TIM Hall Sensor interface - * @param htim: TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -256,7 +255,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -271,7 +270,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -286,16 +285,16 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral */ @@ -307,16 +306,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ @@ -328,19 +327,19 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral */ @@ -352,16 +351,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -376,15 +375,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM Hall Sensor handle - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param htim TIM Hall Sensor handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); if((htim->State == HAL_TIM_STATE_BUSY)) { @@ -401,8 +400,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 htim->State = HAL_TIM_STATE_BUSY; } } - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callback */ @@ -425,16 +424,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -475,13 +474,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -505,13 +503,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -535,13 +532,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -585,7 +581,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -602,13 +598,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -675,15 +670,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -792,13 +786,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -892,13 +885,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -921,13 +913,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -951,13 +942,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1018,13 +1008,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1071,7 +1060,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) @@ -1092,15 +1081,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1209,13 +1197,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1298,8 +1285,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1323,8 +1310,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1352,8 +1339,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1383,8 +1370,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1447,15 +1434,15 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1496,15 +1483,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1549,15 +1536,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1601,8 +1588,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim: TIM handle. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1663,8 +1650,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: TIM handle - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1672,7 +1659,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) { uint32_t tmpbdtr = 0; - + /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); @@ -1683,13 +1670,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - + /* Check input state */ __HAL_LOCK(htim); - + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); @@ -1700,22 +1687,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); - + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { + /* Check the parameters */ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - + /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } - + /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; - + __HAL_UNLOCK(htim); return HAL_OK; @@ -1723,12 +1711,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the break input source. - * @param htim: TIM handle. - * @param BreakInput: Break input to configure + * @param htim TIM handle. + * @param BreakInput Break input to configure * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig: Break input source configuration + * @param sBreakInputConfig Break input source configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, @@ -1748,22 +1736,24 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) { assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); } #else assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* Check input state */ __HAL_LOCK(htim); - + switch(sBreakInputConfig->Source) { case TIM_BREAKINPUTSOURCE_BKIN: @@ -1791,81 +1781,87 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, } break; -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) case TIM_BREAKINPUTSOURCE_DFSDM1: { bkin_enable_mask = TIM1_OR2_BKDF1BK0E; bkin_enable_bitpos = 8; } - break; -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ + break; +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ default: break; } - + switch(BreakInput) { case TIM_BREAKINPUT_BRK: { /* Get the TIMx_OR2 register value */ tmporx = htim->Instance->OR2; - + /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - + /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; } - + /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmporx; + htim->Instance->OR2 = tmporx; } break; case TIM_BREAKINPUT_BRK2: { /* Get the TIMx_OR3 register value */ tmporx = htim->Instance->OR3; - + /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - + /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \ - defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ + defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ +#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ + /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ { tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; } - + /* Set TIMx_OR3 */ - htim->Instance->OR3 = tmporx; + htim->Instance->OR3 = tmporx; } - break; + break; default: break; } - + __HAL_UNLOCK(htim); return HAL_OK; @@ -1873,7 +1869,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /** * @brief Configures the TIMx Remapping input capabilities. - * @param htim: TIM handle. + * @param htim TIM handle. * @param Remap: specifies the TIM remapping source. * @if STM32L486xx @@ -1898,7 +1894,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * field4 can have the following values: * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant + * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant @endif @if STM32L443xx * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3): @@ -1917,7 +1913,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output * - * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant + * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant * @endif @if STM32L486xx @@ -1995,7 +1991,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * field4 can have the following values: * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant + * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant * @endif * For TIM15, the parameter is a combination of 3 fields (field1 | field2): @@ -2005,7 +2001,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE * * field2 can have the following values: - * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection + * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively @@ -2042,34 +2038,31 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { uint32_t tmpor1 = 0; uint32_t tmpor2 = 0; - + __HAL_LOCK(htim); /* Check parameters */ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); assert_param(IS_TIM_REMAP(Remap)); - + /* Set ETR_SEL bit field (if required) */ if (IS_TIM_ETRSEL_INSTANCE(htim->Instance)) { tmpor2 = htim->Instance->OR2; tmpor2 &= ~TIMx_ETRSEL_MASK; tmpor2 |= (Remap & TIMx_ETRSEL_MASK); - + /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmpor2; + htim->Instance->OR2 = tmpor2; } - + /* Set other remapping capabilities */ tmpor1 = Remap; tmpor1 &= ~TIMx_ETRSEL_MASK; /* Set TIMx_OR1 */ - htim->Instance->OR1 = Remap; - - /* Set TIMx_OR1 */ - htim->Instance->OR1 = tmpor1; - + htim->Instance->OR1 = tmpor1; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); @@ -2079,8 +2072,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim: TIM handle. - * @param Channels: specifies the reference signal(s) the OC5REF is combined with. + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. * This parameter can be any combination of the following values: * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF @@ -2134,7 +2127,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Hall commutation changed callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) @@ -2149,7 +2142,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) @@ -2183,7 +2176,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Hall Sensor interface handle state. - * @param htim: TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) @@ -2197,7 +2190,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) @@ -2212,12 +2205,12 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h index 61df2f10dd..eae1c9a328 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tim_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention @@ -59,28 +57,28 @@ * @{ */ -/** - * @brief TIM Hall sensor Configuration Structure definition +/** + * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; -/** - * @brief TIM Break/Break2 input configuration +/** + * @brief TIM Break/Break2 input configuration */ typedef struct { uint32_t Source; /*!< Specifies the source of the timer break input. @@ -119,15 +117,18 @@ typedef struct { /* STM32L496xx || STM32L4A6xx */ #define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ +#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ #define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ @@ -145,7 +146,8 @@ typedef struct { #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ #define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ @@ -154,7 +156,8 @@ typedef struct { #define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) @@ -166,12 +169,19 @@ typedef struct { #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ -#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ -#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ -#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ /* STM32L496xx || STM32L4A6xx */ +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) +#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ +#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ +#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ #define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ @@ -179,16 +189,20 @@ typedef struct { #define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ #define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ @@ -205,13 +219,15 @@ typedef struct { /* STM32L496xx || STM32L4A6xx */ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ #define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ #define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -233,11 +249,13 @@ typedef struct { #define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -259,7 +277,7 @@ typedef struct { /** * @} */ - + /** * @} */ @@ -286,7 +304,8 @@ typedef struct { #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ @@ -295,7 +314,9 @@ typedef struct { #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ +#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) @@ -312,7 +333,7 @@ typedef struct { * @{ */ -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ @@ -409,7 +430,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ @@ -420,7 +441,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ @@ -452,7 +473,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c index d0aad5aba1..ffb54c8bb1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tsc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and De-initialization diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h index f1c3386132..32f5bb622b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_tsc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_tsc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TSC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c index 206c426c90..8aa955c859 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -31,8 +29,9 @@ (+++) Enable the NVIC USART IRQ handle. (++) UART interrupts handling: -@@- The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) are managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes. + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() and HAL_UART_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. @@ -42,7 +41,7 @@ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) @@ -118,11 +117,28 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#if defined(USART_CR1_FIFOEN) +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#else +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#endif + +#if defined(USART_CR1_FIFOEN) +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#else +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#endif + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ -#define UART_LPUART_BRR_MIN ((uint32_t)0x00000300) /* LPUART BRR minimum authorized value */ -#define UART_LPUART_BRR_MAX ((uint32_t)0x000FFFFF) /* LPUART BRR maximum authorized value */ /** * @} */ @@ -145,9 +161,20 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +#if defined(USART_CR1_FIFOEN) +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +#endif +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +#if defined(USART_CR1_FIFOEN) +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +#endif + /** * @} */ @@ -220,8 +247,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); /** * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -231,7 +258,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { /* Check the parameters */ @@ -242,49 +269,49 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } /** * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -294,47 +321,47 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check UART instance */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -342,9 +369,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle. - * @param BreakDetectLength: specifies the LIN break detection length. + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. * This parameter can be one of the following values: * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection @@ -357,12 +384,12 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe { return HAL_ERROR; } - + /* Check the LIN UART instance */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - + /* LIN mode limited to 16-bit oversampling only */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) { @@ -373,47 +400,47 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe { return HAL_ERROR; } - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - + /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -421,10 +448,10 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. - * @param Address: UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod: specifies the UART wakeup method. + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. * This parameter can be one of the following values: * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark @@ -444,53 +471,53 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add { return HAL_ERROR; } - + /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { /* If address mark wake up method is chosen, set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); } - + /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } @@ -498,7 +525,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief DeInitialize the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -508,42 +535,42 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0; - huart->Instance->CR2 = 0x0; - huart->Instance->CR3 = 0x0; - + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + /* Process Unlock */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Initialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspInit can be implemented in the user file */ @@ -551,14 +578,14 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) /** * @brief DeInitialize the UART MSP. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspDeInit can be implemented in the user file */ @@ -647,39 +674,43 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Send an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; + + huart->TxXferSize = Size; huart->TxXferCount = Size; - while(huart->TxXferCount > 0) + + while(huart->TxXferCount > 0U) { - huart->TxXferCount--; if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; @@ -687,25 +718,27 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pData += 2U; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } + huart->TxXferCount--; } + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -716,10 +749,14 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout: Timeout duration. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -727,35 +764,34 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uint16_t* tmp; uint16_t uhMask; uint32_t tickstart = 0; - + /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; + + huart->RxXferSize = Size; huart->RxXferCount = Size; - + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; - + /* as long as data have to be received */ - while(huart->RxXferCount > 0) + while(huart->RxXferCount > 0U) { - huart->RxXferCount--; if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; @@ -764,20 +800,21 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); } + huart->RxXferCount--; } - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -788,9 +825,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -798,27 +835,66 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->TxISR = NULL; + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Transmit Data Register Empty Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - + +#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the TX FIFO threshold interrupt */ + SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else +#endif + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the Transmit Data Register Empty interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +#endif + } + return HAL_OK; } else @@ -829,9 +905,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -839,33 +915,73 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; huart->RxXferCount = Size; - + huart->RxISR = NULL; + /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART Parity Error and Data Register not empty Interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - + +#if defined(USART_CR1_FIFOEN) + /* Configure Rx interrupt processing*/ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else +#endif + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); +#else + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif + } + return HAL_OK; } else @@ -876,9 +992,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -886,46 +1002,46 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - + /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - + /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; - + /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; - + /* Enable the UART transmit DMA channel */ HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); - + /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ + in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + return HAL_OK; } else @@ -936,9 +1052,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @retval HAL status @@ -948,48 +1064,48 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - + /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - + /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; - + /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; - + /* Enable the DMA channel */ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the UART Parity Error Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ + in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + return HAL_OK; } else @@ -1000,14 +1116,14 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pause the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { @@ -1020,27 +1136,27 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the UART DMA Rx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Resume the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ @@ -1050,65 +1166,65 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Enable the UART DMA Rx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Stop the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + /* Stop UART DMA Tx request if ongoing */ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel */ if(huart->hdmatx != NULL) { HAL_DMA_Abort(huart->hdmatx); } - + UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ if(huart->hdmarx != NULL) { HAL_DMA_Abort(huart->hdmarx); } - + UART_EndRxTransfer(huart); } - + return HAL_OK; } @@ -1127,55 +1243,70 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmatx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmatx); } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmarx); } } - + /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + return HAL_OK; } @@ -1194,30 +1325,42 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmatx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmatx); } } - + /* Reset Tx transfer counter */ - huart->TxXferCount = 0; - + huart->TxXferCount = 0U; + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + return HAL_OK; } @@ -1236,34 +1379,41 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - + HAL_DMA_Abort(huart->hdmarx); } } - + /* Reset Rx transfer counter */ - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + return HAL_OK; } @@ -1283,10 +1433,14 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { - uint32_t abortcplt = 1; + uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -1325,7 +1479,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { /* Disable DMA Tx at UART level */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmatx != NULL) { @@ -1339,16 +1493,16 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } else { - abortcplt = 0; + abortcplt = 0U; } } } - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmarx != NULL) { @@ -1359,36 +1513,51 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { huart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1; + abortcplt = 1U; } else { - abortcplt = 0; + abortcplt = 0U; } } } - + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1) + if (abortcplt == 1U) { /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortCpltCallback(huart); } - + return HAL_OK; } @@ -1409,20 +1578,24 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmatx != NULL) { /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - + /* Abort DMA TX */ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) { @@ -1433,11 +1606,14 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0; - + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortTransmitCpltCallback(huart); } @@ -1445,15 +1621,26 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else { /* Reset Tx transfer counter */ - huart->TxXferCount = 0; + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortTransmitCpltCallback(huart); } - + return HAL_OK; } @@ -1474,21 +1661,25 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback : will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { @@ -1499,14 +1690,20 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else { /* Reset Rx transfer counter */ - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortReceiveCpltCallback(huart); } @@ -1514,115 +1711,144 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else { /* Reset Rx transfer counter */ - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* As no DMA to be aborted, call directly user Abort complete callback */ HAL_UART_AbortReceiveCpltCallback(huart); } - + return HAL_OK; } /** * @brief Handle UART interrupt request. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { uint32_t isrflags = READ_REG(huart->Instance->ISR); uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its; + uint32_t cr3its = READ_REG(huart->Instance->CR3); uint32_t errorflags; - + /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); if (errorflags == RESET) { /* UART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - UART_Receive_IT(huart); + if (huart->RxISR != NULL) {huart->RxISR(huart);} return; } } - + /* If some errors occur */ - cr3its = READ_REG(huart->Instance->CR3); +#if defined(USART_CR1_FIFOEN) + if( (errorflags != RESET) + && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) +#else if( (errorflags != RESET) && ( ((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) +#endif { /* UART parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + huart->ErrorCode |= HAL_UART_ERROR_PE; } - + /* UART frame error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + huart->ErrorCode |= HAL_UART_ERROR_FE; } - + /* UART noise error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + huart->ErrorCode |= HAL_UART_ERROR_NE; } /* UART Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) +#else + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || + ((cr3its & USART_CR3_EIE) != RESET))) +#endif { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + huart->ErrorCode |= HAL_UART_ERROR_ORE; } - + /* Call UART Error Call back function if need be --------------------------*/ if(huart->ErrorCode != HAL_UART_ERROR_NONE) { /* UART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - UART_Receive_IT(huart); + if (huart->RxISR != NULL) {huart->RxISR(huart);} } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + consider error as blocking */ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { + { /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* Abort the UART DMA Rx channel */ if(huart->hdmarx != NULL) { /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) { @@ -1645,46 +1871,67 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) else { /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + Error is notified to user through user error callback */ HAL_UART_ErrorCallback(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - cr3its = READ_REG(huart->Instance->CR3); if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); /* Set the UART state ready to be able to start again the process */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; HAL_UARTEx_WakeupCallback(huart); return; } - + /* UART in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif { - UART_Transmit_IT(huart); + if (huart->TxISR != NULL) {huart->TxISR(huart);} return; } - + /* UART in mode Transmitter (transmission end) -----------------------------*/ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { UART_EndTransmit_IT(huart); return; } - + +#if defined(USART_CR1_FIFOEN) + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + { + HAL_UARTEx_TxFifoEmptyCallback(huart); + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + { + HAL_UARTEx_RxFifoFullCallback(huart); + return; + } +#endif } /** * @brief Tx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) @@ -1699,14 +1946,14 @@ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback can be implemented in the user file. */ @@ -1714,14 +1961,14 @@ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file. */ @@ -1729,14 +1976,14 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ @@ -1744,7 +1991,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callback. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -1818,9 +2065,11 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) UART_SetConfig() API configures the UART peripheral (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver (+) HAL_LIN_SendBreak() API transmits the break characters @@ -1831,49 +2080,49 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Enable USART mute mode by setting the MME bit in the CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } /** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart: UART handle. + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - + huart->gState = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } /** * @brief Enter UART mute mode (means UART actually enters mute mode). * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) @@ -1883,7 +2132,7 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) @@ -1891,23 +2140,24 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) @@ -1915,47 +2165,48 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - + huart->gState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Transmit break characters. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) { /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Send break characters */ - huart->Instance->RQR |= UART_SENDBREAK_REQUEST; - + SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } - /** * @} */ @@ -1977,25 +2228,25 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ /** - * @brief Return the UART handle state. + * @brief Return the UART handle state. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. + * the configuration information for the specified UART. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1= 0x00, temp2 = 0x00; + uint32_t temp1= 0x00U, temp2 = 0x00U; temp1 = huart->gState; temp2 = huart->RxState; - + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** - * @brief Return the UART handle error code. +* @brief Return the UART handle error code. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval UART Error Code + * the configuration information for the specified UART. +* @retval UART Error Code */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { @@ -2015,99 +2266,126 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg = 0x00000000U; UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint16_t brrtemp = 0x0000U; + uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; - + uint32_t lpuart_ker_ck_pres = 0x00000000U; + /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); if(UART_INSTANCE_LOWPOWER(huart)) { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); } else { assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); } - + assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); +#endif + /*-------------------------- USART CR1 Configuration -----------------------*/ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); - + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ + * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - + /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) */ + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) + * - set TXFTCFG bit according to huart->Init.TxFifoThreshold value + * - set RXFTCFG bit according to huart->Init.RxFifoThreshold value */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; + if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; } - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); - + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + +#if defined(USART_PRESC_PRESCALER) + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); +#endif + /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - + /* Check LPUART instance */ if(UART_INSTANCE_LOWPOWER(huart)) { /* Retrieve frequency clock */ - tmpreg = 0; - switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - tmpreg = HAL_RCC_GetPCLK1Freq(); +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq()/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); +#endif break; case UART_CLOCKSOURCE_HSI: - tmpreg = (uint32_t) HSI_VALUE; +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; +#endif break; case UART_CLOCKSOURCE_SYSCLK: - tmpreg = HAL_RCC_GetSysClockFreq(); +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq()/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); +#endif break; case UART_CLOCKSOURCE_LSE: - tmpreg = (uint32_t) LSE_VALUE; +#if defined(USART_PRESC_PRESCALER) + lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); +#else + lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } - + /* if proper clock source reported */ - if (tmpreg != 0) + if (lpuart_ker_ck_pres != 0U) { /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ( (tmpreg < (3 * huart->Init.BaudRate) ) || - (tmpreg > (4096 * huart->Init.BaudRate) )) + if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) { ret = HAL_ERROR; } @@ -2116,26 +2394,43 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_HSI: - tmpreg = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_SYSCLK: - tmpreg = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_LSE: - tmpreg = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; } - - if ((tmpreg >= UART_LPUART_BRR_MIN) && (tmpreg <= UART_LPUART_BRR_MAX)) + + /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { - huart->Instance->BRR = tmpreg; + huart->Instance->BRR = usartdiv; } else { @@ -2150,112 +2445,179 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_PCLK2: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_HSI: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_SYSCLK: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_LSE: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } - - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); - huart->Instance->BRR = brrtemp; + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } } else { switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_PCLK2: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_HSI: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_SYSCLK: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_LSE: - huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); +#endif break; case UART_CLOCKSOURCE_UNDEFINED: default: - ret = HAL_ERROR; + ret = HAL_ERROR; break; } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } } - + +#if defined(USART_CR1_FIFOEN) + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; +#endif + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + return ret; - } /** * @brief Configure the UART peripheral advanced features. - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - + /* if required, configure TX pin active level inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); } - + /* if required, configure RX pin active level inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); } - + /* if required, configure data inversion */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - + /* if required, configure RX/TX pins swap */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); } - + /* if required, configure RX overrun detection disabling */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } - + /* if required, configure DMA disabling on reception error */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } - + /* if required, configure auto Baud rate detection scheme */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) { @@ -2269,7 +2631,7 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); } } - + /* if required, configure MSB first on communication line */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) { @@ -2285,14 +2647,14 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Check if the Transmitter is enabled */ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { @@ -2313,24 +2675,24 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) return HAL_TIMEOUT; } } - + /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Handle UART Communication Timeout. - * @param huart UART handle. - * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) @@ -2341,17 +2703,22 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; + + huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); + return HAL_TIMEOUT; } } @@ -2362,13 +2729,17 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +#endif /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -2377,17 +2748,24 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; } @@ -2402,13 +2780,13 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - huart->TxXferCount = 0; - + { + huart->TxXferCount = 0U; + /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ + in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } @@ -2417,7 +2795,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { HAL_UART_TxCpltCallback(huart); } - } /** @@ -2428,7 +2805,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + HAL_UART_TxHalfCpltCallback(huart); } @@ -2440,24 +2817,24 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - huart->RxXferCount = 0; - + huart->RxXferCount = 0U; + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; } - + HAL_UART_RxCpltCallback(huart); } @@ -2469,7 +2846,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + HAL_UART_RxHalfCpltCallback(huart); } @@ -2481,23 +2858,23 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - + /* Stop UART DMA Tx request if ongoing */ if ( (huart->gState == HAL_UART_STATE_BUSY_TX) &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) { - huart->TxXferCount = 0; + huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } - + /* Stop UART DMA Rx request if ongoing */ if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) { - huart->RxXferCount = 0; + huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } - + huart->ErrorCode |= HAL_UART_ERROR_DMA; HAL_UART_ErrorCallback(huart); } @@ -2505,15 +2882,15 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA UART communication abort callback, when initiated by HAL services on Error * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - huart->RxXferCount = 0; - huart->TxXferCount = 0; - + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + HAL_UART_ErrorCallback(huart); } @@ -2530,7 +2907,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); huart->hdmatx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ if(huart->hdmarx != NULL) { @@ -2541,19 +2918,27 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortCpltCallback(huart); } @@ -2572,7 +2957,7 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); huart->hdmarx->XferAbortCallback = NULL; - + /* Check if an Abort process is still ongoing */ if(huart->hdmatx != NULL) { @@ -2583,19 +2968,22 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0; - huart->RxXferCount = 0; - + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortCpltCallback(huart); } @@ -2612,12 +3000,20 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - huart->TxXferCount = 0; - + + huart->TxXferCount = 0U; + +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } +#endif + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortTransmitCpltCallback(huart); } @@ -2633,140 +3029,409 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - huart->RxXferCount = 0; - + + huart->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + /* Call user Abort complete callback */ HAL_UART_AbortReceiveCpltCallback(huart); } /** - * @brief Send an amount of data in interrupt mode. + * @brief TX interrrupt handler for 7 or 8 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval HAL status + * @param huart UART handle. + * @retval None */ -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { - uint16_t* tmp; - /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { if(huart->TxXferCount == 0) { /* Disable the UART Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - +#endif + /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - return HAL_OK; } else { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); - } + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); huart->TxXferCount--; - - return HAL_OK; } } - else +} + +/** + * @brief TX interrrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) { - return HAL_BUSY; + if(huart->TxXferCount == 0) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +#endif + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + huart->pTxBuffPtr += 2; + huart->TxXferCount--; + } } } +#if defined(USART_CR1_FIFOEN) +/** + * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->TxXferCount--; + } + } + } +} + +/** + * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + { + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } + } +} +#endif + /** * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - + /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + HAL_UART_TxCpltCallback(huart); - - return HAL_OK; } /** - * @brief Receive an amount of data in interrupt mode. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval HAL status + * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None */ -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { - uint16_t* tmp; - uint16_t uhMask = huart->Mask; + uint16_t uhMask = huart->Mask; uint16_t uhdata; - + /* Check that a Rx process is ongoing */ if(huart->RxState == HAL_UART_STATE_BUSY_RX) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - } - else - { - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - } - + *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + if(--huart->RxXferCount == 0) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - +#endif + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - + /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + HAL_UART_RxCpltCallback(huart); - - return HAL_OK; } - - return HAL_OK; } else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - return HAL_BUSY; } } +/** + * @brief RX interrrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t*) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr +=2; + + if(--huart->RxXferCount == 0) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + HAL_UART_RxCpltCallback(huart); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +#if defined(USART_CR1_FIFOEN) +/** + * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) + { + for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->RxXferCount--; + + if(huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + HAL_UART_RxCpltCallback(huart); + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) + { + for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t*) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr +=2; + huart->RxXferCount--; + + if(huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + HAL_UART_RxCpltCallback(huart); + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h index d4b5cfa2b5..34e100955f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -66,12 +64,19 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: + UART: + ===== - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + + where (uart/lpuart)_ker_ck_pres is the UART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref UARTEx_Word_Length. */ @@ -99,6 +104,12 @@ typedef struct uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ +#endif + }UART_InitTypeDef; /** @@ -207,13 +218,12 @@ typedef enum */ typedef enum { - HAL_UART_ERROR_NONE = 0x00, /*!< No error */ - HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_UART_ERROR_BUSY = 0x20 /*!< Busy Error */ + HAL_UART_ERROR_NONE = 0x00U, /*!< No error */ + HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */ + HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */ + HAL_UART_ERROR_FE = 0x04U, /*!< frame error */ + HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */ + HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */ }HAL_UART_ErrorTypeDef; /** @@ -221,53 +231,71 @@ typedef enum */ typedef enum { - UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }UART_ClockSourceTypeDef; /** * @brief UART handle Structure definition */ -typedef struct +typedef struct __UART_HandleTypeDef { - USART_TypeDef *Instance; /*!< UART registers base address */ + USART_TypeDef *Instance; /*!< UART registers base address */ - UART_InitTypeDef Init; /*!< UART communication parameters */ + UART_InitTypeDef Init; /*!< UART communication parameters */ - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - uint16_t TxXferSize; /*!< UART Tx Transfer size */ + uint16_t TxXferSize; /*!< UART Tx Transfer size */ - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - uint16_t RxXferSize; /*!< UART Rx Transfer size */ + uint16_t RxXferSize; /*!< UART Rx Transfer size */ - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - uint16_t Mask; /*!< UART Rx RDR register mask */ + uint16_t Mask; /*!< UART Rx RDR register mask */ - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ +#if defined(USART_CR1_FIFOEN) + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - HAL_LockTypeDef Lock; /*!< Locking object */ + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ +#endif - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ +#if defined(USART_CR2_SLVEN) + uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. + This parameter can be a value of @ref UARTEx_Slave_Mode. */ +#endif - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - __IO uint32_t ErrorCode; /*!< UART Error code */ + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ }UART_HandleTypeDef; @@ -284,7 +312,7 @@ typedef struct * @{ */ #define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 ((uint32_t)0x00000000) /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ #define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ #define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ /** @@ -294,9 +322,9 @@ typedef struct /** @defgroup UART_Parity UART Parity * @{ */ -#define UART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ -#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ -#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ /** * @} */ @@ -304,10 +332,10 @@ typedef struct /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /*!< No hardware control */ -#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */ -#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */ -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ /** * @} */ @@ -315,9 +343,9 @@ typedef struct /** @defgroup UART_Mode UART Transfer Mode * @{ */ -#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ -#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ -#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} */ @@ -325,8 +353,8 @@ typedef struct /** @defgroup UART_State UART State * @{ */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000) /*!< UART disabled */ -#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ /** * @} */ @@ -334,8 +362,8 @@ typedef struct /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */ -#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ /** * @} */ @@ -343,19 +371,40 @@ typedef struct /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disable */ -#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ /** * @} */ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ +#endif + /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ /** * @} */ @@ -363,8 +412,8 @@ typedef struct /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ /** * @} */ @@ -372,8 +421,8 @@ typedef struct /** @defgroup UART_LIN UART Local Interconnection Network mode * @{ */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000) /*!< Local Interconnect Network disable */ -#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ /** * @} */ @@ -381,8 +430,8 @@ typedef struct /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /*!< LIN 10-bit break detection length */ -#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ /** * @} */ @@ -390,8 +439,8 @@ typedef struct /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA TX disabled */ -#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ /** * @} */ @@ -399,8 +448,8 @@ typedef struct /** @defgroup UART_DMA_Rx UART DMA Rx * @{ */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA RX disabled */ -#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ /** * @} */ @@ -408,8 +457,8 @@ typedef struct /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /*!< UART half-duplex disabled */ -#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ /** * @} */ @@ -417,8 +466,8 @@ typedef struct /** @defgroup UART_WakeUp_Methods UART WakeUp Methods * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /*!< UART wake-up on idle line */ -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ /** * @} */ @@ -426,11 +475,11 @@ typedef struct /** @defgroup UART_Request_Parameters UART Request Parameters * @{ */ -#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ /** * @} */ @@ -438,15 +487,15 @@ typedef struct /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type * @{ */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ /** * @} */ @@ -454,8 +503,8 @@ typedef struct /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ -#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ /** * @} */ @@ -463,8 +512,8 @@ typedef struct /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ /** * @} */ @@ -472,8 +521,8 @@ typedef struct /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion * @{ */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ -#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ /** * @} */ @@ -481,8 +530,8 @@ typedef struct /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap * @{ */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ -#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ /** * @} */ @@ -490,8 +539,8 @@ typedef struct /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ /** * @} */ @@ -499,8 +548,8 @@ typedef struct /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ /** * @} */ @@ -508,8 +557,8 @@ typedef struct /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ /** * @} */ @@ -517,8 +566,8 @@ typedef struct /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ /** * @} */ @@ -526,8 +575,8 @@ typedef struct /** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable * @{ */ -#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /*!< UART stop mode disable */ -#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ /** * @} */ @@ -535,8 +584,8 @@ typedef struct /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /*!< UART mute mode disable */ -#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ /** * @} */ @@ -544,7 +593,7 @@ typedef struct /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) /*!< UART address-matching LSB position in CR2 register */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -552,9 +601,9 @@ typedef struct /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000) /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ /** * @} */ @@ -562,8 +611,8 @@ typedef struct /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /*!< Driver enable signal is active high */ -#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ /** * @} */ @@ -571,7 +620,7 @@ typedef struct /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ /** * @} */ @@ -579,7 +628,7 @@ typedef struct /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ /** * @} */ @@ -587,7 +636,7 @@ typedef struct /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask * @{ */ -#define UART_IT_MASK ((uint32_t)0x001F) /*!< UART interruptions flags mask */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ /** * @} */ @@ -595,7 +644,7 @@ typedef struct /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value * @{ */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /*!< UART polling-based communications time-out value */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ /** * @} */ @@ -605,28 +654,40 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define UART_FLAG_REACK ((uint32_t)0x00400000) /*!< UART receive enable acknowledge flag */ -#define UART_FLAG_TEACK ((uint32_t)0x00200000) /*!< UART transmit enable acknowledge flag */ -#define UART_FLAG_WUF ((uint32_t)0x00100000) /*!< UART wake-up from stop mode flag */ -#define UART_FLAG_RWU ((uint32_t)0x00080000) /*!< UART receiver wake-up from mute mode flag */ -#define UART_FLAG_SBKF ((uint32_t)0x00040000) /*!< UART send break flag */ -#define UART_FLAG_CMF ((uint32_t)0x00020000) /*!< UART character match flag */ -#define UART_FLAG_BUSY ((uint32_t)0x00010000) /*!< UART busy flag */ -#define UART_FLAG_ABRF ((uint32_t)0x00008000) /*!< UART auto Baud rate flag */ -#define UART_FLAG_ABRE ((uint32_t)0x00004000) /*!< UART auto Baud rate error */ -#define UART_FLAG_EOBF ((uint32_t)0x00001000) /*!< UART end of block flag */ -#define UART_FLAG_RTOF ((uint32_t)0x00000800) /*!< UART receiver timeout flag */ -#define UART_FLAG_CTS ((uint32_t)0x00000400) /*!< UART clear to send flag */ -#define UART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< UART clear to send interrupt flag */ -#define UART_FLAG_LBDF ((uint32_t)0x00000100) /*!< UART LIN break detection flag */ -#define UART_FLAG_TXE ((uint32_t)0x00000080) /*!< UART transmit data register empty */ -#define UART_FLAG_TC ((uint32_t)0x00000040) /*!< UART transmission complete */ -#define UART_FLAG_RXNE ((uint32_t)0x00000020) /*!< UART read data register not empty */ -#define UART_FLAG_IDLE ((uint32_t)0x00000010) /*!< UART idle flag */ -#define UART_FLAG_ORE ((uint32_t)0x00000008) /*!< UART overrun error */ -#define UART_FLAG_NE ((uint32_t)0x00000004) /*!< UART noise error */ -#define UART_FLAG_FE ((uint32_t)0x00000002) /*!< UART frame error */ -#define UART_FLAG_PE ((uint32_t)0x00000001) /*!< UART parity error */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#if defined(USART_CR1_FIFOEN) +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#else +#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ +#endif +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#if defined(USART_CR1_FIFOEN) +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#else +#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ +#endif +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ /** * @} */ @@ -641,19 +702,41 @@ typedef struct * - ZZZZZ : Flag position in the ISR register(5bits) * @{ */ -#define UART_IT_PE ((uint32_t)0x0028) /*!< UART parity error interruption */ -#define UART_IT_TXE ((uint32_t)0x0727) /*!< UART transmit data register empty interruption */ -#define UART_IT_TC ((uint32_t)0x0626) /*!< UART transmission complete interruption */ -#define UART_IT_RXNE ((uint32_t)0x0525) /*!< UART read data register not empty interruption */ -#define UART_IT_IDLE ((uint32_t)0x0424) /*!< UART idle interruption */ -#define UART_IT_LBD ((uint32_t)0x0846) /*!< UART LIN break detection interruption */ -#define UART_IT_CTS ((uint32_t)0x096A) /*!< UART CTS interruption */ -#define UART_IT_CM ((uint32_t)0x112E) /*!< UART character match interruption */ -#define UART_IT_WUF ((uint32_t)0x1476) /*!< UART wake-up from stop mode interruption */ -#define UART_IT_ERR ((uint32_t)0x0060) /*!< UART error interruption */ -#define UART_IT_ORE ((uint32_t)0x0300) /*!< UART overrun error interruption */ -#define UART_IT_NE ((uint32_t)0x0200) /*!< UART noise error interruption */ -#define UART_IT_FE ((uint32_t)0x0100) /*!< UART frame error interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#endif +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#if defined(USART_CR1_FIFOEN) +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#endif +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#if defined(USART_CR1_FIFOEN) +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#endif + +/* Elements values convention: 000000000XXYYYYYb + - YYYYY : Interrupt source position in the XX register (5bits) + - XX : Interrupt source register (2bits) + - 01: CR1 register + - 10: CR2 register + - 11: CR3 register */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +/* Elements values convention: 0000ZZZZ00000000b + - ZZZZ : Flag position in the ISR register(4bits) */ +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -666,11 +749,12 @@ typedef struct #define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#if defined(USART_CR1_FIFOEN) +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#endif #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ -#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ /** @@ -688,7 +772,7 @@ typedef struct */ /** @brief Reset UART handle states. - * @param __HANDLE__: UART handle. + * @param __HANDLE__ UART handle. * @retval None */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -696,8 +780,8 @@ typedef struct (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ } while(0) /** @brief Flush the UART Data registers. - * @param __HANDLE__: specifies the UART Handle. - * @retval None + * @param __HANDLE__ specifies the UART Handle. + * @retval None */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ @@ -706,19 +790,18 @@ typedef struct } while(0) /** @brief Clear the specified UART pending flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag - * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None @@ -726,39 +809,51 @@ typedef struct #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) /** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) /** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) /** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) +#if defined(USART_CR1_FIFOEN) +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) +#endif + /** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref UART_FLAG_WUF Wake up from stop mode flag @@ -768,13 +863,13 @@ typedef struct * @arg @ref UART_FLAG_BUSY Busy flag * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref UART_FLAG_EOBF End of block flag - * @arg @ref UART_FLAG_RTOF Receiver timeout flag * @arg @ref UART_FLAG_CTS CTS Change flag * @arg @ref UART_FLAG_LBDF LIN Break detection flag * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -785,109 +880,131 @@ typedef struct #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_ORE Overrun Error interrupt - * @arg @ref UART_IT_NE Noise Error interrupt - * @arg @ref UART_IT_FE Framing Error interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt source to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @arg @ref UART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag - * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None */ #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific UART request flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request * @arg @ref UART_SENDBREAK_REQUEST Send Break Request @@ -896,31 +1013,31 @@ typedef struct * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request * @retval None */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the UART one bit sample method. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** @brief Enable CTS flow control. * @note This macro allows to enable CTS hardware flow control for a given UART instance, @@ -931,7 +1048,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ @@ -949,7 +1066,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ @@ -967,7 +1084,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ @@ -985,7 +1102,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ @@ -993,65 +1110,105 @@ typedef struct CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0) - /** * @} */ +/* Private variables -----------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup UART_Private_Variables UART Private Variables + * @{ + */ +static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; +/** + * @} + */ +#endif + /* Private macros --------------------------------------------------------*/ /** @defgroup UART_Private_Macros UART Private Macros * @{ */ +#if defined(USART_PRESC_PRESCALER) + /** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__: LPUART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__) ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) + +#else + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256)) + ((__BAUD__)/2)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__: UART clock. - * @param __BAUD__: Baud rate set by the user. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. * @retval Division result */ #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) +#endif /* USART_PRESC_PRESCALER */ + /** @brief Check whether or not UART instance is Low Power UART. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET ) +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE(__HANDLE__->Instance)) /** @brief Check UART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz) + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 52 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6500001U) /** @brief Check UART assertion time. - * @param __TIME__: 5-bit value assertion time. + * @param __TIME__ 5-bit value assertion time. * @retval Test result (TRUE or FALSE). */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** @brief Check UART deassertion time. - * @param __TIME__: 5-bit value deassertion time. + * @param __TIME__ 5-bit value deassertion time. * @retval Test result (TRUE or FALSE). */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__: UART frame number of stop bits. + * @param __STOPBITS__ UART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ @@ -1061,7 +1218,7 @@ typedef struct /** * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__: LPUART frame number of stop bits. + * @param __STOPBITS__ LPUART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ @@ -1069,7 +1226,7 @@ typedef struct /** * @brief Ensure that UART frame parity is valid. - * @param __PARITY__: UART frame parity. + * @param __PARITY__ UART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ @@ -1078,7 +1235,7 @@ typedef struct /** * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__: UART hardware flow control. + * @param __CONTROL__ UART hardware flow control. * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ @@ -1089,14 +1246,14 @@ typedef struct /** * @brief Ensure that UART communication mode is valid. - * @param __MODE__: UART communication mode. + * @param __MODE__ UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. - * @param __STATE__: UART state. + * @param __STATE__ UART state. * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ @@ -1104,7 +1261,7 @@ typedef struct /** * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__: UART oversampling. + * @param __SAMPLING__ UART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) */ #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ @@ -1112,7 +1269,7 @@ typedef struct /** * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__: UART frame sampling. + * @param __ONEBIT__ UART frame sampling. * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) */ #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ @@ -1120,7 +1277,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__: UART auto Baud rate detection mode. + * @param __MODE__ UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ @@ -1130,7 +1287,7 @@ typedef struct /** * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__: UART receiver timeout setting. + * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ @@ -1138,7 +1295,7 @@ typedef struct /** * @brief Ensure that UART LIN state is valid. - * @param __LIN__: UART LIN state. + * @param __LIN__ UART LIN state. * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) */ #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ @@ -1146,7 +1303,7 @@ typedef struct /** * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__: UART LIN break detection length. + * @param __LENGTH__ UART LIN break detection length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ @@ -1154,7 +1311,7 @@ typedef struct /** * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__: UART DMA TX state. + * @param __DMATX__ UART DMA TX state. * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) */ #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ @@ -1162,7 +1319,7 @@ typedef struct /** * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__: UART DMA RX state. + * @param __DMARX__ UART DMA RX state. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ @@ -1170,7 +1327,7 @@ typedef struct /** * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__: UART half-duplex state. + * @param __HDSEL__ UART half-duplex state. * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) */ #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ @@ -1178,7 +1335,7 @@ typedef struct /** * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__: UART wake-up method . + * @param __WAKEUP__ UART wake-up method . * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) */ #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ @@ -1186,7 +1343,7 @@ typedef struct /** * @brief Ensure that UART request parameter is valid. - * @param __PARAM__: UART request parameter. + * @param __PARAM__ UART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ @@ -1197,7 +1354,7 @@ typedef struct /** * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__: UART advanced features initialization. + * @param __INIT__ UART advanced features initialization. * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) */ #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ @@ -1212,7 +1369,7 @@ typedef struct /** * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__: UART frame TX inversion setting. + * @param __TXINV__ UART frame TX inversion setting. * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) */ #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ @@ -1220,7 +1377,7 @@ typedef struct /** * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__: UART frame RX inversion setting. + * @param __RXINV__ UART frame RX inversion setting. * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) */ #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ @@ -1228,7 +1385,7 @@ typedef struct /** * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__: UART frame data inversion setting. + * @param __DATAINV__ UART frame data inversion setting. * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) */ #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ @@ -1236,7 +1393,7 @@ typedef struct /** * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__: UART frame RX/TX pins swap setting. + * @param __SWAP__ UART frame RX/TX pins swap setting. * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) */ #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ @@ -1244,7 +1401,7 @@ typedef struct /** * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__: UART frame overrun setting. + * @param __OVERRUN__ UART frame overrun setting. * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) */ #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ @@ -1252,7 +1409,7 @@ typedef struct /** * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__: UART auto Baud rate state. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ @@ -1260,7 +1417,7 @@ typedef struct /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__: UART DMA enabling or disabling on error setting. + * @param __DMA__ UART DMA enabling or disabling on error setting. * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) */ #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ @@ -1268,7 +1425,7 @@ typedef struct /** * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__: UART frame MSB first setting. + * @param __MSBFIRST__ UART frame MSB first setting. * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) */ #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ @@ -1276,7 +1433,7 @@ typedef struct /** * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__: UART stop mode state. + * @param __STOPMODE__ UART stop mode state. * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) */ #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ @@ -1284,7 +1441,7 @@ typedef struct /** * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__: UART mute mode state. + * @param __MUTE__ UART mute mode state. * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ @@ -1292,21 +1449,67 @@ typedef struct /** * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__: UART wake-up selection. + * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) /** * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__: UART driver enable polarity. + * @param __POLARITY__ UART driver enable polarity. * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) */ #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ ((__POLARITY__) == UART_DE_POLARITY_LOW)) +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c index 49a416e5a1..363a37943e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -21,6 +19,16 @@ (#) For the UART RS485 Driver Enable mode, initialize the UART registers by calling the HAL_RS485Ex_Init() API. + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. @endverbatim ****************************************************************************** @@ -76,6 +84,9 @@ * @{ */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +#if defined(USART_CR1_FIFOEN) +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +#endif /** * @} */ @@ -147,26 +158,26 @@ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTy /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. - * @param Polarity: select the driver enable polarity. - * This parameter can be one of the following values: + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime: Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime: Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). * @retval HAL status */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { uint32_t temp = 0x0; - + /* Check the UART handle allocation */ if(huart == NULL) { @@ -174,60 +185,131 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, } /* Check the Driver Enable UART instance */ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - + /* Check the Driver Enable polarity */ assert_param(IS_UART_DE_POLARITY(Polarity)); - + /* Check the Driver Enable assertion time */ assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - + /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); } - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; } - + if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - + /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - + /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); } +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of Wakeup and FIFO mode related callback functions. + + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + + (#) TX/RX Fifos Callbacks: + (+) HAL_UARTEx_RxFifoFullCallback() + (+) HAL_UARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ + __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +#if defined(USART_CR1_FIFOEN) +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} +#endif + /** * @} */ @@ -249,7 +331,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode (+) HAL_UARTEx_DisableStopMode() API disables the above functionality (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt - + (+) HAL_UARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_UARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_UARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold @endverbatim * @{ @@ -265,8 +353,8 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * long). * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart: UART handle. - * @param AddressLength: this parameter can be one of the following values: + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status @@ -278,21 +366,21 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua { return HAL_ERROR; } - + /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->gState to Ready */ return (UART_CheckIdleState(huart)); } @@ -300,46 +388,48 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /** * @brief Set Wakeup from Stop mode interrupt flag selection. - * @param huart: UART handle. - * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUP_ON_ADDRESS - * @arg @ref UART_WAKEUP_ON_STARTBIT - * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart = 0; - + /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) { UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); } - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + /* Wait until REACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { @@ -350,76 +440,386 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return status; } /** * @brief Enable UART Stop Mode. - * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart: UART handle. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Set UESM bit */ SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - + huart->gState = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Disable UART Stop Mode. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + huart->gState = HAL_UART_STATE_BUSY; - + /* Clear UESM bit */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} +#if defined(USART_CR2_SLVEN) +/** + * @brief Enable the SPI slave mode. + * @note When the UART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the UART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the UART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(huart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->SlaveMode = UART_SLAVEMODE_ENABLE; + + huart->gState = HAL_UART_STATE_READY; + + /* Enable UART */ + __HAL_UART_ENABLE(huart); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable SPI slave mode */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->SlaveMode = UART_SLAVEMODE_ENABLE; + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param huart UART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref UART_NSS_HARD + * @arg @ref UART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); + assert_param(IS_UART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; } +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} /** - * @brief UART wakeup from Stop mode callback. - * @param huart: UART handle. - * @retval None + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status */ -__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); + uint32_t tmpcr1 = 0; - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_WakeupCallback can be implemented in the user file. - */ + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; } +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} +#endif + /** * @} */ @@ -434,21 +834,55 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) /** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart: UART handle. - * @param WakeUpSelection: UART wake up from stop mode parameters. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. * @retval None */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - + /* Set the USART address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - + /* Set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); } +#if defined(USART_CR1_FIFOEN) +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; + uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + } + else + { + rx_fifo_depth = 8; /* RX Fifo size */ + tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + } +} +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h index 8977d53da8..926662f36b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of UART HAL Extended module. ****************************************************************************** * @attention @@ -84,25 +82,66 @@ typedef struct * @{ */ -/** @defgroup UARTEx_Word_Length UART Word Length +/** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ -/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ +#if defined(USART_CR2_SLVEN) +/** @defgroup UARTEx_Slave_Select_management UARTEx Slave Select Management + * @{ + */ +#define UART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define UART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +/** + * @} + */ +#endif + +#if defined(USART_CR1_FIFOEN) +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ +#endif + /** * @} */ @@ -124,7 +163,21 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @} */ +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + /* IO operation functions *****************************************************/ +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#if defined(USART_CR1_FIFOEN) +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); +#endif + +/** + * @} + */ /** @addtogroup UARTEx_Exported_Functions_Group3 * @{ @@ -135,7 +188,20 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#if defined(USART_CR2_SLVEN) +HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig); +#endif + +#if defined(USART_CR1_FIFOEN) +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +#endif + /** * @} @@ -145,17 +211,48 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); * @} */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Constants UARTEx Private Constants + * @{ + */ +#if defined(USART_CR2_SLVEN) +/** @defgroup UARTEx_Slave_Mode UARTEx Synchronous Slave mode + * @{ + */ +#define UART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define UART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ +#endif + +#if defined(USART_CR1_FIFOEN) +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ +#endif +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup UARTEx_Private_Macros UARTEx Private Macros * @{ */ /** @brief Report the UART clock source. - * @param __HANDLE__: specifies the UART Handle. - * @param __CLOCKSOURCE__: output variable. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ + defined (STM32L496xx) || defined (STM32L4A6xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -242,7 +339,7 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); break; \ } \ } \ - else if ((__HANDLE__)->Instance == UART5) \ + else if((__HANDLE__)->Instance == UART5) \ { \ switch(__HAL_RCC_GET_UART5_SOURCE()) \ { \ @@ -600,7 +697,7 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); /** * @brief Ensure that UART frame length is valid. - * @param __LENGTH__: UART frame length. + * @param __LENGTH__ UART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ @@ -609,12 +706,48 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); /** * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__: UART wake-up address length. + * @param __ADDRESS__ UART wake-up address length. * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) */ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) +#if defined(USART_CR2_SLVEN) +/** + * @brief Ensure that UART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ UART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_UART_NSS(__NSS__) (((__NSS__) == UART_NSS_HARD) || \ + ((__NSS__) == UART_NSS_SOFT)) +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c index d6502a6a87..af1c56627f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_usart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter @@ -43,8 +41,8 @@ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode (Receiver/Transmitter) in the husart handle Init structure. + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode + (Receiver/Transmitter) in the husart handle Init structure. (#) Initialize the USART registers by calling the HAL_USART_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) @@ -107,10 +105,25 @@ */ #define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ #define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */ + +#if defined(USART_CR1_FIFOEN) +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ + USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \ + USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */ +#else #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ #define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ +#endif + +#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ /** * @} */ @@ -133,10 +146,21 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); +#if defined(USART_CR1_FIFOEN) +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +#endif +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); +#if defined(USART_CR1_FIFOEN) +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +#endif + + /** * @} */ @@ -249,13 +273,13 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) } /** - * @brief DeInitialize the USART peripheral. + * @brief DeInitialize the USART peripheral. * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { - /* Check the USART handle allocation */ + /* Check the USART handle allocation */ if(husart == NULL) { return HAL_ERROR; @@ -284,14 +308,14 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief Initialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ -__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) + __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspInit can be implemented in the user file */ @@ -299,14 +323,14 @@ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) /** * @brief DeInitialize the USART MSP. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ -__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) + __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspDeInit can be implemented in the user file */ @@ -317,7 +341,7 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) */ /** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions + * @brief USART Transmit and Receive functions * @verbatim =============================================================================== @@ -410,24 +434,23 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->TxXferSize = Size; husart->TxXferCount = Size; - + /* Check the remaining data to be sent */ while(husart->TxXferCount > 0) { - husart->TxXferCount--; - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -441,19 +464,29 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa { husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); } + + husart->TxXferCount--; } - + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + + /* Clear Transmission Complete Flag */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + /* At end of Tx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -464,7 +497,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. * @param husart USART handle. * @param pRxData Pointer to data buffer. * @param Size Amount of data to be received. @@ -476,51 +509,54 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat uint16_t* tmp; uint16_t uhMask; uint32_t tickstart = 0; - + if(husart->State == HAL_USART_STATE_READY) { if((pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - + /* Init tickstart for timeout managment*/ tickstart = HAL_GetTick(); - + husart->RxXferSize = Size; husart->RxXferCount = Size; - + /* Computation of USART mask to apply to RDR register */ USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; - + /* as long as data have to be received */ while(husart->RxXferCount > 0) { - husart->RxXferCount--; - - /* Wait until TC flag is set to send dummy byte in order to generate the - * clock for the slave to send data. - * Whatever the frame length (7, 8 or 9-bit long), the same dummy value - * can be written for all the cases. */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) +#if defined(USART_CR2_SLVEN) + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) +#endif { - return HAL_TIMEOUT; + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); } - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); - + /* Wait for RXNE Flag */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pRxData ; @@ -531,14 +567,26 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat { *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } + + husart->RxXferCount--; + } - + +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + /* At end of Rx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else @@ -548,7 +596,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat } /** - * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. @@ -568,6 +616,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -586,14 +635,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; - /* Check the remain data to be sent */ - while(husart->TxXferCount > 0) +#if defined(USART_CR2_SLVEN) + if ((husart->SlaveMode == USART_SLAVEMODE_ENABLE) || (husart->TxXferCount == 0x01U)) +#else + if (husart->TxXferCount == 0x01U) +#endif { - husart->TxXferCount--; - husart->RxXferCount--; - - /* Wait until TC flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + /* Wait until TXE flag is set to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -601,28 +650,60 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { tmp = (uint16_t*) pTxData; husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2; + pTxData += 2U; } else - { + { husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); } - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + husart->TxXferCount--; + } + + /* Check the remain data to be sent */ + while ((husart->TxXferCount > 0) || (husart->RxXferCount > 0)) + { + if (husart->TxXferCount > 0) { - return HAL_TIMEOUT; + /* Wait until TXE flag is set to send data */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pTxData; + husart->Instance->TDR = (*tmp & uhMask); + pTxData += 2; + } + else + { + husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + } + + husart->TxXferCount--; } - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + + if (husart->RxXferCount > 0) { - tmp = (uint16_t*) pRxData ; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; - } - else - { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) pRxData ; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + pRxData +=2; + } + else + { + *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } + + husart->RxXferCount--; } } @@ -659,12 +740,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /* Process Locked */ __HAL_LOCK(husart); - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; husart->TxXferCount = Size; + husart->TxISR = NULL; husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; + husart->State = HAL_USART_STATE_BUSY_TX; /* The USART Error Interrupts: (Frame error, noise error, overrun error) are not managed by the USART Transmit Process to avoid the overrun interrupt @@ -672,11 +754,45 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT to benefit for the frame error and noise interrupts the usart mode should be configured only for transmit "USART_MODE_TX" */ - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); +#if defined(USART_CR1_FIFOEN) + /* Configure Tx interrupt processing */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the TX FIFO threshold interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); + } + else +#endif + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + } return HAL_OK; } @@ -687,8 +803,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT } /** - * @brief Receive an amount of data in interrupt mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. * @param husart USART handle. * @param pRxData pointer to data buffer. * @param Size amount of data to be received. @@ -696,6 +812,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { +#if defined(USART_CR1_FIFOEN) + uint8_t nb_dummy_data; +#endif + if(husart->State == HAL_USART_STATE_READY) { if((pRxData == NULL ) || (Size == 0)) @@ -706,34 +826,87 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Process Locked */ __HAL_LOCK(husart); - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; husart->RxXferCount = Size; + husart->RxISR = NULL; USART_MASK_COMPUTATION(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Send dummy byte in order to generate the clock for the Slave to send the next data */ - if(husart->Init.WordLength == USART_WORDLENGTH_9B) +#if defined(USART_CR1_FIFOEN) + /* Configure Rx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) { - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF); + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } else +#endif { - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error and Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); +#else + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +#endif } +#if defined(USART_CR2_SLVEN) + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) +#endif + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + When FIFO mode is disabled only one data must be transferred. + When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold. + */ +#if defined(USART_CR1_FIFOEN) + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0 ; nb_dummy_data--) + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + else +#endif + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + return HAL_OK; } else @@ -743,7 +916,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx } /** - * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. @@ -774,18 +947,69 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; + +#if defined(USART_CR1_FIFOEN) + /* Configure TxRx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Process Unlocked */ - __HAL_UNLOCK(husart); + /* Enable the TX and RX FIFO Threshold interrupts */ + SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); + } + else +#endif + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + husart->RxISR = USART_RxISR_8BIT; + } - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); +#else SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); +#endif + + /* Enable the USART Transmit Data Register Empty Interrupt */ +#if defined(USART_CR1_FIFOEN) + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +#else + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); +#endif + } return HAL_OK; } @@ -796,7 +1020,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint } /** - * @brief Send an amount of data in DMA mode. + * @brief Send an amount of data in DMA mode. * @param husart USART handle. * @param pTxData pointer to data buffer. * @param Size amount of data to be sent. @@ -854,13 +1078,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p } /** - * @brief Receive an amount of data in DMA mode. + * @brief Receive an amount of data in DMA mode. * @param husart USART handle. * @param pRxData pointer to data buffer. * @param Size amount of data to be received. * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -899,15 +1123,21 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); - /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, - this mode isn't a simplex receive mode but a full-duplex receive mode */ - /* Set the USART DMA Tx Complete and Error callback to Null */ - husart->hdmatx->XferErrorCallback = NULL; - husart->hdmatx->XferHalfCpltCallback = NULL; - husart->hdmatx->XferCpltCallback = NULL; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - +#if defined(USART_CR2_SLVEN) + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + tmp = (uint32_t*)&pRxData; + /* Set the USART DMA Tx Complete and Error callback to Null */ + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + } +#endif + /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -934,7 +1164,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR } /** - * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @param husart USART handle. * @param pTxData pointer to TX data buffer. * @param pRxData pointer to RX data buffer. @@ -1018,7 +1248,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin } /** - * @brief Pause the DMA Transfer. + * @brief Pause the DMA Transfer. * @param husart USART handle. * @retval HAL status */ @@ -1040,14 +1270,14 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) { /* Disable the USART DMA Tx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } + } if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { + { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Disable the USART DMA Rx request */ + /* Disable the USART DMA Rx request */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); } } @@ -1059,7 +1289,7 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) } /** - * @brief Resume the DMA Transfer. + * @brief Resume the DMA Transfer. * @param husart USART handle. * @retval HAL status */ @@ -1077,7 +1307,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) { /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); @@ -1097,7 +1327,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) } /** - * @brief Stop the DMA Transfer. + * @brief Stop the DMA Transfer. * @param husart USART handle. * @retval HAL status */ @@ -1108,7 +1338,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ + the stream and the corresponding call back is executed. */ /* Disable the USART Tx/Rx DMA requests */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); @@ -1145,9 +1375,14 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#endif /* Disable the USART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) @@ -1188,6 +1423,17 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) /* Clear the Error flags in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + /* Restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; @@ -1215,9 +1461,14 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { uint32_t abortcplt = 1; - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +#if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#endif /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ @@ -1311,6 +1562,17 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) /* Clear the Error flags in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); +#if defined(USART_CR1_FIFOEN) + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + +#endif + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + /* Restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; @@ -1330,116 +1592,151 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { uint32_t isrflags = READ_REG(husart->Instance->ISR); uint32_t cr1its = READ_REG(husart->Instance->CR1); - uint32_t cr3its; - uint32_t errorflags; + uint32_t cr3its = READ_REG(husart->Instance->CR3); + uint32_t errorflags; + /* If no error occurs */ +#if defined(USART_CR2_SLVEN) + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); +#else errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); +#endif if (errorflags == RESET) { /* USART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - USART_Receive_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } + if (husart->RxISR != NULL) {husart->RxISR(husart);} return; } } - + /* If some errors occur */ - cr3its = READ_REG(husart->Instance->CR3); +#if defined(USART_CR1_FIFOEN) + if( (errorflags != RESET) + && ( ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) +#else if( (errorflags != RESET) && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) +#endif { /* USART parity error interrupt occurred -------------------------------------*/ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - + husart->ErrorCode |= HAL_USART_ERROR_PE; } - + /* USART frame error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - + husart->ErrorCode |= HAL_USART_ERROR_FE; } - + /* USART noise error interrupt occurred --------------------------------------*/ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - + husart->ErrorCode |= HAL_USART_ERROR_NE; } - + /* USART Over-Run interrupt occurred -----------------------------------------*/ - if(((isrflags & USART_ISR_ORE) != RESET) && - (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) +#if defined(USART_CR1_FIFOEN) + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) +#else + if( ((isrflags & USART_ISR_ORE) != RESET) + &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || + ((cr3its & USART_CR3_EIE) != RESET))) +#endif { __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - + husart->ErrorCode |= HAL_USART_ERROR_ORE; } - + +#if defined(USART_CR2_SLVEN) + /* USART SPI slave underrun error interrupt occurred -------------------------*/ + if(((isrflags & USART_ISR_UDR) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + /* Ignore SPI slave underrun errors when reception is going on */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + return; + } + else + { + __HAL_USART_CLEAR_UDRFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_UDR; + } + } +#endif + /* Call USART Error Call back function if need be --------------------------*/ if(husart->ErrorCode != HAL_USART_ERROR_NONE) { /* USART in mode Receiver ---------------------------------------------------*/ - if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) + && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) + || ((cr3its & USART_CR3_RXFTIE) != RESET))) +#else + if(((isrflags & USART_ISR_RXNE) != RESET) + && ((cr1its & USART_CR1_RXNEIE) != RESET)) +#endif { - if(husart->State == HAL_USART_STATE_BUSY_RX) - { - USART_Receive_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } + if (husart->RxISR != NULL) {husart->RxISR(husart);} } - + /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + consider error as blocking */ if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) { /* Blocking error : transfer is aborted - Set the USART state ready to be able to start again the process, - Disable Interrupts, and disable DMA requests, if ongoing */ + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - + /* Disable the USART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); - + /* Abort the USART DMA Tx channel */ if(husart->hdmatx != NULL) { /* Set the USART Tx DMA Abort callback to NULL : no callback - executed at end of DMA abort procedure */ + executed at end of DMA abort procedure */ husart->hdmatx->XferAbortCallback = NULL; /* Abort DMA TX */ HAL_DMA_Abort_IT(husart->hdmatx); } - + /* Abort the USART DMA Rx channel */ if(husart->hdmarx != NULL) { /* Set the USART Rx DMA Abort callback : - will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; - + /* Abort DMA RX */ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) { @@ -1462,49 +1759,64 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) else { /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ + Error is notified to user through user error callback */ HAL_USART_ErrorCallback(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; } } return; - + } /* End if some error occurs */ - - + + /* USART in mode Transmitter ------------------------------------------------*/ - if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) +#if defined(USART_CR1_FIFOEN) + if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) + && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) + || ((cr3its & USART_CR3_TXFTIE) != RESET))) +#else + if(((isrflags & USART_ISR_TXE) != RESET) + && ((cr1its & USART_CR1_TXEIE) != RESET)) +#endif { - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - USART_Transmit_IT(husart); - } - else - { - USART_TransmitReceive_IT(husart); - } + if (husart->TxISR != NULL) {husart->TxISR(husart);} return; } - + /* USART in mode Transmitter (transmission end) -----------------------------*/ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { USART_EndTransmit_IT(husart); return; } - + +#if defined(USART_CR1_FIFOEN) + /* USART TX Fifo Empty occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + { + HAL_USARTEx_TxFifoEmptyCallback(husart); + return; + } + + /* USART RX Fifo Full occurred ----------------------------------------------*/ + if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + { + HAL_USARTEx_RxFifoFullCallback(husart); + return; + } +#endif } /** * @brief Tx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxCpltCallback can be implemented in the user file. */ @@ -1512,14 +1824,14 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ -__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) + __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_TxHalfCpltCallback can be implemented in the user file. */ @@ -1527,14 +1839,14 @@ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE: This function should not be modified, when the callback is needed, the HAL_USART_RxCpltCallback can be implemented in the user file. */ @@ -1542,14 +1854,14 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Half Transfer completed callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_RxHalfCpltCallback can be implemented in the user file */ @@ -1557,14 +1869,14 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_TxRxCpltCallback can be implemented in the user file */ @@ -1572,14 +1884,14 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief USART error callback. - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_ErrorCallback can be implemented in the user file. */ @@ -1623,7 +1935,7 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) /** * @brief Return the USART handle state. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle state */ @@ -1634,7 +1946,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) /** * @brief Return the USART error code. - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART handle Error Code */ @@ -1662,17 +1974,22 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) */ static void USART_EndTransfer(USART_HandleTypeDef *husart) { - /* Disable TXEIE and TCIE interrupts */ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE)); +#if defined(USART_CR1_FIFOEN) + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +#else + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); +#endif /* At end of process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; } /** - * @brief DMA USART transmit process complete callback. + * @brief DMA USART transmit process complete callback. * @param hdma DMA handle. * @retval None */ @@ -1682,7 +1999,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { + { husart->TxXferCount = 0; if(husart->State == HAL_USART_STATE_BUSY_TX) @@ -1706,7 +2023,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART transmit process half complete callback. + * @brief DMA USART transmit process half complete callback. * @param hdma DMA handle. * @retval None */ @@ -1718,30 +2035,30 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART receive process complete callback. + * @brief DMA USART receive process complete callback. * @param hdma DMA handle. * @retval None */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); - + /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { husart->RxXferCount = 0; - + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ + in USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ + clock to the slave device */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - + if(husart->State == HAL_USART_STATE_BUSY_RX) { HAL_USART_RxCpltCallback(husart); @@ -1765,12 +2082,11 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { HAL_USART_TxRxCpltCallback(husart); } - } - + } } /** - * @brief DMA USART receive process half complete callback. + * @brief DMA USART receive process half complete callback. * @param hdma DMA handle. * @retval None */ @@ -1783,7 +2099,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMAError(DMA_HandleTypeDef *hdma) @@ -1849,7 +2165,7 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); /* Restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; + husart->State = HAL_USART_STATE_READY; /* Call user Abort complete callback */ HAL_USART_AbortCpltCallback(husart); @@ -1916,15 +2232,11 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar { if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - husart->State= HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_TIMEOUT; } } @@ -1934,7 +2246,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief Configure the USART peripheral. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) @@ -1954,62 +2266,109 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); assert_param(IS_USART_PARITY(husart->Init.Parity)); assert_param(IS_USART_MODE(husart->Init.Mode)); - - +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); +#endif + /*-------------------------- USART CR1 Configuration -----------------------*/ /* Clear M, PCE, PS, TE and RE bits and configure * the USART Word Length, Parity and Mode: * set the M bits according to husart->Init.WordLength value * set PCE and PS bits according to husart->Init.Parity value * set TE and RE bits according to husart->Init.Mode value - * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*---------------------------- USART CR2 Configuration ---------------------*/ - /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value + * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = 0; tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= (uint32_t)husart->Init.CLKLastBit; tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); - tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits); + tmpreg |= (uint32_t)husart->Init.StopBits; MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* no CR3 register configuration */ +#if defined(USART_PRESC_PRESCALER) + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ + MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); +#endif /*-------------------------- USART BRR Configuration -----------------------*/ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ USART_GETCLOCKSOURCE(husart, clocksource); + switch (clocksource) { - case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + case USART_CLOCKSOURCE_PCLK1: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_PCLK2: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_HSI: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_SYSCLK: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_LSE: +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); +#else + usartdiv = (uint16_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); +#endif + break; + case USART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); - husart->Instance->BRR = brrtemp; - + /* USARTDIV must be greater than or equal to 0d16 */ + if (usartdiv >= USART_BRR_MIN) + { + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + +#if defined(USART_CR1_FIFOEN) + /* Initialize the number of data to process during RX/TX ISR execution */ + husart->NbTxDataToProcess = 1; + husart->NbRxDataToProcess = 1; +#endif + + /* Clear ISR function pointers */ + husart->RxISR = NULL; + husart->TxISR = NULL; + return ret; } @@ -2063,59 +2422,158 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_Transmit_IT(). * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. * @param husart USART handle. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; - /* Check that a Tx process is ongoing */ - if(husart->State == HAL_USART_STATE_BUSY_TX) + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - if(husart->TxXferCount == 0) { /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - - return HAL_OK; } else { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) +{ + uint16_t* tmp; + + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + if(husart->TxXferCount == 0) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + tmp = (uint16_t*) husart->pTxBuffPtr; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->pTxBuffPtr += 2; + husart->TxXferCount--; + } + } +} + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + uint8_t nb_tx_data; + /* Check that a Tx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(husart->TxXferCount == 0) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->TxXferCount--; + } + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + uint16_t* tmp; + uint8_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_TX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + for(nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + { + if(husart->TxXferCount == 0) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { tmp = (uint16_t*) husart->pTxBuffPtr; husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2; + husart->TxXferCount--; } - else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); - } - - husart->TxXferCount--; - - return HAL_OK; } } - else - { - return HAL_BUSY; - } } +#endif /** * @brief Wraps up transmission in non-blocking mode. * @param husart Pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) { /* Disable the USART Transmit Complete Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TC); @@ -2123,12 +2581,27 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - /* Tx process is ended, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxCpltCallback(husart); - - return HAL_OK; + /* Clear TxISR function pointer */ + husart->TxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Tx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxCpltCallback(husart); + } + else if (husart->RxXferCount == 0) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } } @@ -2136,136 +2609,370 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) * @brief Simplex receive an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. * @param husart USART handle - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) { - uint16_t* tmp; uint16_t uhMask = husart->Mask; - - if(husart->State == HAL_USART_STATE_BUSY_RX) + + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pRxBuffPtr; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; - } - else - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } - /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); - + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + if(--husart->RxXferCount == 0) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - +#endif + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Rx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_RxCpltCallback(husart); - - return HAL_OK; + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } } - - return HAL_OK; - } - else - { - return HAL_BUSY; +#if defined(USART_CR2_SLVEN) + else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } } } /** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @brief Simplex receive an amount of data in non-blocking mode. * @note Function called under interruption only, once - * interruptions have been enabled by HAL_USART_TransmitReceive_IT(). - * @param husart: USART handle. - * @retval HAL status + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None */ -static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) { uint16_t* tmp; uint16_t uhMask = husart->Mask; - if(husart->State == HAL_USART_STATE_BUSY_TX_RX) + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) { - - if(husart->TxXferCount != 0x00) - { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) - { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (uint16_t)(*tmp & uhMask); - husart->pTxBuffPtr += 2; - } - else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask); - } - husart->TxXferCount--; - - /* Check the latest data transmitted */ - if(husart->TxXferCount == 0) - { - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - } - } - } - - if(husart->RxXferCount != 0x00) - { - if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) - { - if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pRxBuffPtr; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; - } - else - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } - husart->RxXferCount--; - } - } - - /* Check the latest data received */ - if(husart->RxXferCount == 0) + tmp = (uint16_t*) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2; + + if(--husart->RxXferCount == 0) { /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ +#if defined(USART_CR1_FIFOEN) + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +#else CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +#endif /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Rx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxRxCpltCallback(husart); - - return HAL_OK; + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } } +#if defined(USART_CR2_SLVEN) + else if ( (husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } +} - return HAL_OK; +#if defined(USART_CR1_FIFOEN) +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @retval None + * @retval HAL status + */ +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + uint16_t uhMask = husart->Mask; + uint8_t nb_rx_data; + + /* Check that a Rx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + + if(--husart->RxXferCount == 0) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } + } +#if defined(USART_CR2_SLVEN) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_8BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + +#if defined(USART_CR2_SLVEN) + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && + (husart->TxXferCount == 0U)) +#else + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->TxXferCount == 0U)) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } } else { - return HAL_BUSY; + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); } } +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + uint16_t* tmp; + uint16_t uhMask = husart->Mask; + uint8_t nb_rx_data; + + /* Check that a Tx process is ongoing */ + if ((husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX)) + { + for(nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + tmp = (uint16_t*) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2; + + if(--husart->RxXferCount == 0) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { +#if defined(USART_CR2_SLVEN) + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } +#endif + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_RxCpltCallback(husart); + } + else if ((husart->TxXferCount == 0) && + (READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxRxCpltCallback(husart); + } + } +#if defined(USART_CR2_SLVEN) + else if ((husart->State == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) +#else + else if (husart->State == HAL_USART_STATE_BUSY_RX) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + if (((husart->RxXferCount != 0U)) && (husart->RxXferCount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_16BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + +#if defined(USART_CR2_SLVEN) + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE) && + (husart->TxXferCount == 0U)) +#else + if ( (husart->State == HAL_USART_STATE_BUSY_TX_RX) && + (husart->TxXferCount == 0U)) +#endif + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} +#endif + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h index a7ed6ebb47..baea5261ee 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_usart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -66,7 +64,11 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */ + Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. + @note Oversampling by 8 is systematically applied to achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -93,6 +95,12 @@ typedef struct uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_Last_Bit. */ + +#if defined(USART_PRESC_PRESCALER) + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref USART_ClockPrescaler. */ +#endif + }USART_InitTypeDef; /** @@ -100,14 +108,14 @@ typedef struct */ typedef enum { - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ }HAL_USART_StateTypeDef; /** @@ -115,12 +123,13 @@ typedef enum */ typedef enum { - HAL_USART_ERROR_NONE = 0x00, /*!< No error */ - HAL_USART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_USART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_USART_ERROR_FE = 0x04, /*!< frame error */ - HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */ + HAL_USART_ERROR_NONE = 0x00U, /*!< No error */ + HAL_USART_ERROR_PE = 0x01U, /*!< Parity error */ + HAL_USART_ERROR_NE = 0x02U, /*!< Noise error */ + HAL_USART_ERROR_FE = 0x04U, /*!< frame error */ + HAL_USART_ERROR_ORE = 0x08U, /*!< Overrun error */ + HAL_USART_ERROR_DMA = 0x10U, /*!< DMA transfer error */ + HAL_USART_ERROR_UDR = 0x20U /*!< SPI slave underrun error */ }HAL_USART_ErrorTypeDef; /** @@ -128,47 +137,65 @@ typedef enum */ typedef enum { - USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }USART_ClockSourceTypeDef; /** * @brief USART handle Structure definition */ -typedef struct +typedef struct __USART_HandleTypeDef { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< USART registers base address */ - USART_InitTypeDef Init; /*!< USART communication parameters */ + USART_InitTypeDef Init; /*!< USART communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ - uint16_t TxXferSize; /*!< USART Tx Transfer size */ + uint16_t TxXferSize; /*!< USART Tx Transfer size */ - __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ - uint16_t RxXferSize; /*!< USART Rx Transfer size */ + uint16_t RxXferSize; /*!< USART Rx Transfer size */ - __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ - uint16_t Mask; /*!< USART Rx RDR register mask */ + uint16_t Mask; /*!< USART Rx RDR register mask */ - DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ +#if defined(USART_CR1_FIFOEN) + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - HAL_LockTypeDef Lock; /*!< Locking object */ + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref USARTEx_FIFO_mode. */ +#endif - __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ +#if defined(USART_CR2_SLVEN) + uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. + This parameter can be a value of @ref USARTEx_Slave_Mode. */ +#endif - __IO uint32_t ErrorCode; /*!< USART Error code */ + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ }USART_HandleTypeDef; @@ -184,10 +211,10 @@ typedef struct /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ -#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ -#define USART_STOPBITS_1 ((uint32_t)0x00000000) /*!< USART frame with 1 stop bit */ -#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ /** * @} */ @@ -195,19 +222,19 @@ typedef struct /** @defgroup USART_Parity USART Parity * @{ */ -#define USART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ -#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ -#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ +#define USART_PARITY_NONE 0x00000000U /*!< No parity */ +#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ /** * @} */ /** @defgroup USART_Mode USART Mode * @{ - */ -#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ -#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ -#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ /** * @} */ @@ -215,8 +242,8 @@ typedef struct /** @defgroup USART_Over_Sampling USART Over Sampling * @{ */ -#define USART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */ +#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ /** * @} */ @@ -224,8 +251,8 @@ typedef struct /** @defgroup USART_Clock USART Clock * @{ */ -#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< USART clock disable */ -#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */ +#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ +#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ /** * @} */ @@ -233,8 +260,8 @@ typedef struct /** @defgroup USART_Clock_Polarity USART Clock Polarity * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< USART Clock signal is steady Low */ -#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */ +#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ +#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ /** * @} */ @@ -242,8 +269,8 @@ typedef struct /** @defgroup USART_Clock_Phase USART Clock Phase * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x00000000) /*!< USART frame phase on first clock transition */ -#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */ +#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ /** * @} */ @@ -251,17 +278,38 @@ typedef struct /** @defgroup USART_Last_Bit USART Last Bit * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< USART frame last data bit clock pulse not output to SCLK pin */ -#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */ +#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ /** * @} */ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_ClockPrescaler USART Clock Prescaler + * @{ + */ +#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ +#endif + /** @defgroup USART_Request_Parameters USART Request Parameters * @{ */ -#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ /** * @} */ @@ -271,20 +319,31 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define USART_FLAG_REACK ((uint32_t)0x00400000) /*!< USART receive enable acknowledge flag */ -#define USART_FLAG_TEACK ((uint32_t)0x00200000) /*!< USART transmit enable acknowledge flag */ -#define USART_FLAG_BUSY ((uint32_t)0x00010000) /*!< USART busy flag */ -#define USART_FLAG_CTS ((uint32_t)0x00000400) /*!< USART clear to send flag */ -#define USART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< USART clear to send interrupt flag */ -#define USART_FLAG_LBDF ((uint32_t)0x00000100) /*!< USART LIN break detection flag */ -#define USART_FLAG_TXE ((uint32_t)0x00000080) /*!< USART transmit data register empty */ -#define USART_FLAG_TC ((uint32_t)0x00000040) /*!< USART transmission complete */ -#define USART_FLAG_RXNE ((uint32_t)0x00000020) /*!< USART read data register not empty */ -#define USART_FLAG_IDLE ((uint32_t)0x00000010) /*!< USART idle flag */ -#define USART_FLAG_ORE ((uint32_t)0x00000008) /*!< USART overrun error */ -#define USART_FLAG_NE ((uint32_t)0x00000004) /*!< USART noise error */ -#define USART_FLAG_FE ((uint32_t)0x00000002) /*!< USART frame error */ -#define USART_FLAG_PE ((uint32_t)0x00000001) /*!< USART parity error */ +#if defined(USART_CR1_FIFOEN) +#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */ +#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ +#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ +#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ +#else +#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ +#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ +#endif +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +#if defined(USART_CR2_SLVEN) +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#endif /** * @} */ @@ -300,15 +359,24 @@ typedef struct * @{ */ -#define USART_IT_PE ((uint16_t)0x0028) /*!< USART parity error interruption */ -#define USART_IT_TXE ((uint16_t)0x0727) /*!< USART transmit data register empty interruption */ -#define USART_IT_TC ((uint16_t)0x0626) /*!< USART transmission complete interruption */ -#define USART_IT_RXNE ((uint16_t)0x0525) /*!< USART read data register not empty interruption */ -#define USART_IT_IDLE ((uint16_t)0x0424) /*!< USART idle interruption */ -#define USART_IT_ERR ((uint16_t)0x0060) /*!< USART error interruption */ -#define USART_IT_ORE ((uint16_t)0x0300) /*!< USART overrun error interruption */ -#define USART_IT_NE ((uint16_t)0x0200) /*!< USART noise error interruption */ -#define USART_IT_FE ((uint16_t)0x0100) /*!< USART frame error interruption */ +#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#if defined(USART_CR1_FIFOEN) +#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ +#endif +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ +#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ +#define USART_IT_ERR 0x0060U /*!< USART error interruption */ +#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ +#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ +#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ + /** * @} */ @@ -316,21 +384,26 @@ typedef struct /** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags * @{ */ -#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#if defined(USART_CR1_FIFOEN) +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#endif +#if defined(USART_CR2_SLVEN) +#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ +#endif /** * @} */ /** @defgroup USART_Interruption_Mask USART Interruption Flags Mask * @{ - */ -#define USART_IT_MASK ((uint16_t)0x001F) /*!< USART interruptions flags mask */ + */ +#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ /** * @} */ @@ -345,22 +418,28 @@ typedef struct */ /** @brief Reset USART handle state. - * @param __HANDLE__: USART handle. + * @param __HANDLE__ USART handle. * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) /** @brief Check whether the specified USART flag is set or not. - * @param __HANDLE__: specifies the USART Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: + * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref USART_FLAG_RXFF RXFIFO Full flag + * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref USART_FLAG_BUSY Busy flag - * @arg @ref USART_FLAG_CTS CTS Change flag + * @arg @ref USART_FLAG_UDR SPI slave underrun error flag * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -371,137 +450,178 @@ typedef struct #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified USART pending flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: - * @arg @ref USART_CLEAR_PEF - * @arg @ref USART_CLEAR_FEF - * @arg @ref USART_CLEAR_NEF - * @arg @ref USART_CLEAR_OREF - * @arg @ref USART_CLEAR_IDLEF - * @arg @ref USART_CLEAR_TCF - * @arg @ref USART_CLEAR_CTSF + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the USART PE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) /** @brief Clear the USART FE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) /** @brief Clear the USART NE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) /** @brief Clear the USART ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) /** @brief Clear the USART IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) -/** @brief Enable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) +#if defined(USART_CR1_FIFOEN) +/** @brief Clear the USART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF) +#endif + +#if defined(USART_CR2_SLVEN) +/** @brief Clear SPI slave underrun error flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) +#endif + +/** @brief Enable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to disable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & 0xFF) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_ORE OverRun Error interrupt - * @arg @ref USART_IT_NE Noise Error interrupt - * @arg @ref USART_IT_FE Framing Error interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__INTERRUPT__)>> 0x08))) != RESET) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_ORE OverRun Error interrupt - * @arg @ref USART_IT_NE Noise Error interrupt - * @arg @ref USART_IT_FE Framing Error interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \ - (((uint16_t)(__IT__)) & USART_IT_MASK))) +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None */ #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific USART request flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __REQ__: specifies the request flag to set. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. * This parameter can be one of the following values: * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request @@ -511,49 +631,81 @@ typedef struct #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) /** @brief Enable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ + */ #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the USART one bit sample method. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None - */ -#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) /** @brief Enable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ -#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable USART. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ -#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** * @} */ +/* Private variables -----------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_Private_Variables USART Private Variables + * @{ + */ +static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; +/** + * @} + */ +#endif + /* Private macros --------------------------------------------------------*/ /** @defgroup USART_Private_Macros USART Private Macros * @{ */ -/** @brief Check USART Baud rate. - * @param __BAUDRATE__: Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8). - * @retval Test result (TRUE or FALSE). +#if defined(USART_PRESC_PRESCALER) +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result */ -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) +#else +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) +#endif + +/** @brief Check USART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on L4 + * divided by the smallest oversampling used on the USART (i.e. 8) + * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) +#else +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) +#endif /** * @brief Ensure that USART frame number of stop bits is valid. - * @param __STOPBITS__: USART frame number of stop bits. + * @param __STOPBITS__ USART frame number of stop bits. * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) */ #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ @@ -563,23 +715,23 @@ typedef struct /** * @brief Ensure that USART frame parity is valid. - * @param __PARITY__: USART frame parity. + * @param __PARITY__ USART frame parity. * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) */ #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ ((__PARITY__) == USART_PARITY_EVEN) || \ - ((__PARITY__) == USART_PARITY_ODD)) + ((__PARITY__) == USART_PARITY_ODD)) /** * @brief Ensure that USART communication mode is valid. - * @param __MODE__: USART communication mode. + * @param __MODE__ USART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U)) /** * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__: USART oversampling. + * @param __SAMPLING__ USART oversampling. * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) */ #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ @@ -587,7 +739,7 @@ typedef struct /** * @brief Ensure that USART clock state is valid. - * @param __CLOCK__: USART clock state. + * @param __CLOCK__ USART clock state. * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) */ #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ @@ -595,21 +747,21 @@ typedef struct /** * @brief Ensure that USART frame polarity is valid. - * @param __CPOL__: USART frame polarity. + * @param __CPOL__ USART frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) /** * @brief Ensure that USART frame phase is valid. - * @param __CPHA__: USART frame phase. + * @param __CPHA__ USART frame phase. * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) */ #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) /** * @brief Ensure that USART frame last bit clock pulse setting is valid. - * @param __LASTBIT__: USART frame last bit clock pulse setting. + * @param __LASTBIT__ USART frame last bit clock pulse setting. * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) */ #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ @@ -617,12 +769,32 @@ typedef struct /** * @brief Ensure that USART request parameter is valid. - * @param __PARAM__: USART request parameter. + * @param __PARAM__ USART request parameter. * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) */ #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Ensure that USART Prescaler is valid. + * @param __CLOCKPRESCALER__ USART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256)) + +#endif /** * @} */ @@ -671,20 +843,18 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); -void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); -void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); /** * @} */ -/* Peripheral Control functions ***********************************************/ - /** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c new file mode 100644 index 0000000000..d2b1b3d70f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.c @@ -0,0 +1,551 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_usart_ex.c + * @author MCD Application Team + * @brief Extended USART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + * + Peripheral Control functions + * + * + @verbatim + ============================================================================== + ##### USART peripheral extended features ##### + ============================================================================== + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup USARTEx USARTEx + * @brief USART Extended HAL module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_Private_Functions USARTEx Private Functions + * @{ + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); +/** + * @} + */ +#endif + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions + * @{ + */ + +/** @defgroup USARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended USART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_USARTEx_RxFifoFullCallback() + (+) HAL_USARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief USART RX Fifo full callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_RxFifoFullCallback (USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief USART TX Fifo empty callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_TxFifoEmptyCallback (USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} +#endif + +/** + * @} + */ + +/** @defgroup USARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + +@endverbatim + * @{ + */ + +#if defined(USART_CR2_SLVEN) +/** + * @brief Enable the SPI slave mode. + * @note When the USART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the USART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the USART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable SPI slave mode */ + CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param husart USART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref USART_NSS_HARD + * @arg @ref USART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + assert_param(IS_USART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Enable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_ENABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_DISABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param husart USART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_TXFIFO_THRESHOLD_1_8 + * @arg @ref USART_TXFIFO_THRESHOLD_1_4 + * @arg @ref USART_TXFIFO_THRESHOLD_1_2 + * @arg @ref USART_TXFIFO_THRESHOLD_3_4 + * @arg @ref USART_TXFIFO_THRESHOLD_7_8 + * @arg @ref USART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update TX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param husart USART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_RXFIFO_THRESHOLD_1_8 + * @arg @ref USART_RXFIFO_THRESHOLD_1_4 + * @arg @ref USART_RXFIFO_THRESHOLD_1_2 + * @arg @ref USART_RXFIFO_THRESHOLD_3_4 + * @arg @ref USART_RXFIFO_THRESHOLD_7_8 + * @arg @ref USART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update RX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USARTEx_Private_Functions + * @{ + */ + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param husart USART handle. + * @retval None + */ +void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; + uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; + + if (husart->FifoMode == USART_FIFOMODE_DISABLE) + { + husart->NbTxDataToProcess = 1; + husart->NbRxDataToProcess = 1; + } + else + { + rx_fifo_depth = 8; /* RX Fifo size */ + tx_fifo_depth = 8; /* TX Fifo size */ + rx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + husart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; + } +} +#endif +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h index cf01f07631..bea5add84f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_usart_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USART HAL Extended module. ****************************************************************************** * @attention @@ -63,18 +61,86 @@ /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ +#if defined(USART_CR2_SLVEN) +/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management + * @{ + */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +/** + * @} + */ +#endif + +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level + * @{ + */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level + * @brief USART RXFIFO level + * @{ + */ +#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ +#endif + /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ +#if defined(USART_CR2_SLVEN) +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode + * @{ + */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ +#endif + +#if defined(USART_CR1_FIFOEN) +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ +#endif +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup USARTEx_Private_Macros USARTEx Private Macros @@ -207,7 +273,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. */ #define USART_MASK_COMPUTATION(__HANDLE__) \ @@ -250,18 +316,96 @@ /** * @brief Ensure that USART frame length is valid. - * @param __LENGTH__: USART frame length. + * @param __LENGTH__ USART frame length. * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ ((__LENGTH__) == USART_WORDLENGTH_8B) || \ ((__LENGTH__) == USART_WORDLENGTH_9B)) +#if defined(USART_CR2_SLVEN) +/** + * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ USART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ + ((__NSS__) == USART_NSS_SOFT)) +#endif + +#if defined(USART_CR1_FIFOEN) +/** + * @brief Ensure that USART TXFIFO threshold level is valid. + * @param __THRESHOLD__ USART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) +#endif /** * @} */ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup USARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup USARTEx_Exported_Functions_Group2 + * @{ + */ + +/* IO operation functions *****************************************************/ +#if defined(USART_CR1_FIFOEN) +void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); +void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); +#endif + +/** + * @} + */ + +/** @addtogroup USARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +#if defined(USART_CR2_SLVEN) +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); +#endif + +#if defined(USART_CR1_FIFOEN) +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +#endif + +/** + * @} + */ + +/** + * @} + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c index 5e8ce3077a..ce4a280195 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_wwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h index 7039355348..75759788f5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c index 1a309d0f68..ead41c287d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief ADC LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h index 52c31cb96f..f859f8783a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -77,6 +75,9 @@ extern "C" { #define ADC_SQR4_REGOFFSET (0x00000300U) #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#if defined(CORE_CM0PLUS) +#define ADC_SQRX_REGOFFSET_POS (8U) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ +#endif #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ @@ -114,6 +115,9 @@ extern "C" { #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) +#if defined(CORE_CM0PLUS) +#define ADC_JDRX_REGOFFSET_POS (8U) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ +#endif /* Definition of ADC group injected sequencer bits information to be inserted */ /* into ADC group injected sequencer ranks literals definition. */ @@ -208,6 +212,9 @@ extern "C" { #define ADC_SMPR1_REGOFFSET (0x00000000U) #define ADC_SMPR2_REGOFFSET (0x02000000U) #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) +#if defined(CORE_CM0PLUS) +#define ADC_SMPRX_REGOFFSET_POS (25U) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ +#endif #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U) #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ @@ -289,7 +296,11 @@ extern "C" { #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ - +#if defined(CORE_CM0PLUS) +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000U) /* Selection of 1 bit to discriminate differential mode: mask of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16U) /* Selection of 1 bit to discriminate differential mode: position of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4U) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ +#endif /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ @@ -316,12 +327,19 @@ extern "C" { #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) +#define ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ + /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) - +#if defined(CORE_CM0PLUS) +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000U) /* Selection of 1 bit to discriminate threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16U) /* Selection of 1 bit to discriminate threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4U) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ +#endif /* Internal mask for ADC offset: */ /* Internal register offset for ADC offset number configuration */ @@ -846,7 +864,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ -#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} @@ -855,23 +873,23 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ -#if defined(ADC_CFGR_DFSDMCFG) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ +#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} */ -#endif /* ADC_CFGR_DFSDMCFG */ +#endif #if defined(ADC_SMPR1_SMPPLUS) /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration @@ -882,12 +900,12 @@ typedef struct /** * @} */ -#endif /* ADC_SMPR1_SMPPLUS */ +#endif /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} @@ -896,7 +914,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ @@ -919,7 +937,7 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ @@ -992,7 +1010,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode * @{ */ -#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** * @} @@ -1001,7 +1019,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode * @{ */ -#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ /** @@ -1011,7 +1029,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length * @{ */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ @@ -1022,7 +1040,7 @@ typedef struct /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode * @{ */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group injected sequencer discontinuous mode disable */ #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} @@ -1077,7 +1095,7 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ @@ -1187,7 +1205,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ -#define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ @@ -1199,7 +1217,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define LL_ADC_OVS_REG_CONT (0x00000000U)/*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_CONT (0x00000000U) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ /** * @} @@ -1208,7 +1226,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ @@ -1223,7 +1241,7 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ @@ -1240,7 +1258,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode * @{ */ -#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ @@ -1255,7 +1273,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer * @{ */ -#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ @@ -1267,7 +1285,7 @@ typedef struct /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ -#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ @@ -1490,7 +1508,7 @@ typedef struct * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (7) @@ -1993,8 +2011,13 @@ typedef struct * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ +#if defined(CORE_CM0PLUS) +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) +#else #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW) +#endif /** * @brief Helper macro to set the ADC calibration value with both single ended @@ -2009,8 +2032,13 @@ typedef struct * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ +#if defined(CORE_CM0PLUS) +#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ + (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) +#else #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__)) +#endif #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -2166,7 +2194,7 @@ typedef struct * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -2559,9 +2587,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx */ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) { +#if defined(CORE_CM0PLUS) + MODIFY_REG(ADCx->CALFACT, + SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, + CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); +#else MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); +#endif } /** @@ -2586,7 +2620,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); +#else return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); +#endif } /** @@ -3204,7 +3242,6 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } - /** * @brief Set ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: @@ -3473,11 +3510,15 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); +#endif MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))); + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** @@ -3578,11 +3619,15 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); +#endif - return (uint32_t) (READ_BIT(*preg, + return (uint32_t) ((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -3702,7 +3747,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); } -#if defined(ADC_CFGR_DFSDMCFG) +#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) /** * @brief Set ADC group regular conversion data transfer to DFSDM. * @note DFSDM transfer cannot be used if DMA transfer is enabled. @@ -3737,7 +3782,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG)); } -#endif /* ADC_CFGR_DFSDMCFG */ +#endif /** * @brief Set ADC group regular behavior in case of overrun: @@ -4020,7 +4065,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, some fast channels are available: fast analog inputs + * @note On STM32L4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -4083,8 +4128,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))); + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); } /** @@ -4157,9 +4202,9 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - return (uint32_t)(READ_BIT(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))) - << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + return (uint32_t)((READ_BIT(ADCx->JSQR, + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -4294,7 +4339,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, some fast channels are available: fast analog inputs + * @note On STM32L4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: @@ -4517,10 +4562,10 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, ADC_JSQR_JL , TriggerSource | (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) | - ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) | - ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) | - ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) | - ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) | + (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | SequencerNbRanks ); } @@ -4638,11 +4683,19 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), + SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); +#endif } /** @@ -4730,12 +4783,21 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) + >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) + ); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) ); +#endif } /** @@ -4753,7 +4815,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. - * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) + * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * are internally fixed to single-ended inputs configuration. * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. @@ -4763,7 +4825,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * ADC must be ADC disabled. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime + * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_1 @@ -4780,6 +4842,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 * @param SingleDiff This parameter can be a combination of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED @@ -4810,15 +4873,14 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. - * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) + * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * are internally fixed to single-ended inputs configuration. * @note One or several values can be selected. In this case, the value * returned is null if all channels are in single ended-mode. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime + * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: - * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 @@ -4833,6 +4895,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 * @retval 0: channel in single-ended mode, else: channel in differential mode */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) @@ -4998,12 +5061,21 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + MODIFY_REG(*preg, + (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), + AWDChannelGroup & AWDy); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); +#endif } /** @@ -5130,51 +5202,59 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */ - /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */ - register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK)); + register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - /* Set variable of AWD1 monitored channel according to AWD1 features */ - /* and ADC channel definition: */ - /* - channel ID with number */ - /* - channel ID with bitfield */ - /* - AWD1 single or all channels */ - /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */ - /* AWD2 or AWD3 selected). */ - register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS); + /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* (parameter value LL_ADC_AWD_DISABLE). */ + /* Else, the selected AWD is enabled and is monitoring a group of channels */ + /* or a single channel. */ + if(AnalogWDMonitChannels != 0) + { + if(AWDy == LL_ADC_AWD1) + { + if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = (( AnalogWDMonitChannels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR_AWD1CH)) + ); + } + else + { + /* AWD monitoring a single channel */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)) + ); + } + } + else + { + if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK + | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) + ); + } + else + { + /* AWD monitoring a single channel */ + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = ( AnalogWDMonitChannels + | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) + ); + } + } + } - register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup - | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle) - | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & 0x00000001U)) - ) - * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS)) - ); - - /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */ - /* features and ADC channel definition: */ - /* - channel ID with number */ - /* - channel ID with bitfield */ - /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */ - /* shift AWD1 equivalent single-all channels out of register) */ - /* - AWD2-3 enable or disable */ - /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */ - /* channel can be read back if only 1 channel monitoring */ - /* is activated, therefore the channel monitoring value channel "3" */ - /* is not not supported by this function, there is no risk of */ - /* conflict. */ - register uint32_t AWD23Enabled = ((0x00000001U >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */ - - register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup - | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - | ((ADC_CFGR_AWD1SGL) >> ((0x00000001U >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U)) - | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) - ) >> AWD23Enabled - ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U)); - - return (AWD1ChannelGroup | AWD23ChannelGroup); + return AnalogWDMonitChannels; + } /** @@ -5232,7 +5312,11 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); +#endif MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -5271,7 +5355,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going - * on either groups regular or injected. + * on either ADC groups regular or injected. * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n @@ -5286,7 +5370,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) @@ -5296,11 +5380,19 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + AWDThresholdsHighLow, + AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow)); +#endif } /** @@ -5333,12 +5425,21 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + + return (uint32_t)(READ_BIT(*preg, + (AWDThresholdsHighLow | ADC_TR1_LT1)) + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) + ); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> POSITION_VAL(AWDThresholdsHighLow) ); +#endif } /** @@ -6284,7 +6385,11 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6311,7 +6416,11 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6338,7 +6447,11 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6365,7 +6478,11 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6392,7 +6509,11 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { +#if defined(CORE_CM0PLUS) + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); +#else register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); +#endif return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h index c4ffe5a34e..a547514fcb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_bus.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of BUS LL module. @verbatim @@ -92,12 +90,18 @@ extern "C" { #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(DMAMUX1) +#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN +#endif /* DMAMUX1 */ #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN #if defined(DMA2D) #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN #endif /* DMA2D */ +#if defined(GFXMMU) +#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN +#endif /* GFXMMU */ #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN /** * @} @@ -140,7 +144,16 @@ extern "C" { #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN #endif /* HASH */ #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#if defined(OCTOSPIM) +#define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN +#endif /* OCTOSPIM */ +#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) +#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN +#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN +#if defined(SRAM3_BASE) +#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN +#endif /* SRAM3_BASE */ /** * @} */ @@ -152,7 +165,15 @@ extern "C" { #if defined(FMC_Bank1_R) #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN #endif /* FMC_Bank1_R */ +#if defined(QUADSPI) #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN +#endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN +#endif /* OCTOSPI2 */ /** * @} */ @@ -240,9 +261,9 @@ extern "C" { #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN -#if defined(SDMMC1) +#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN -#endif /* SDMMC1 */ +#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #if defined(TIM8) @@ -261,6 +282,12 @@ extern "C" { #if defined(DFSDM1_Channel0) #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN #endif /* DFSDM1_Channel0 */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ /** * @} */ @@ -293,17 +320,21 @@ extern "C" { * @brief Enable AHB1 peripherals clock. * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -321,17 +352,21 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * @brief Check if AHB1 peripheral clock is enabled or not * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -345,17 +380,21 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @brief Disable AHB1 peripherals clock. * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -369,18 +408,22 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * @brief Force AHB1 peripherals reset. * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -394,18 +437,22 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * @brief Release AHB1 peripherals reset. * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1ENR DMA2DRST LL_AHB1_GRP1_ReleaseReset + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -419,19 +466,23 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -449,19 +500,23 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep + * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) * * (*) value not defined in all devices. * @retval None @@ -495,7 +550,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -512,6 +569,8 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -541,7 +600,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -558,6 +619,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -583,7 +646,9 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -600,6 +665,8 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -625,7 +692,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -643,6 +712,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -668,7 +739,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA @@ -686,6 +759,8 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -707,12 +782,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -724,12 +802,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) * @arg @ref LL_AHB2_GRP1_PERIPH_ADC * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -755,12 +836,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB @@ -772,12 +856,15 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) * @arg @ref LL_AHB2_GRP1_PERIPH_ADC * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) * * (*) value not defined in all devices. * @retval None @@ -798,10 +885,14 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) /** * @brief Enable AHB3 peripherals clock. * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -818,10 +909,14 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if AHB3 peripheral clock is enabled or not * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -834,10 +929,14 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable AHB3 peripherals clock. * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -850,11 +949,15 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force AHB3 peripherals reset. * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -867,11 +970,15 @@ __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release AHB3 peripherals reset. * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB2_GRP1_PERIPH_ALL * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -884,10 +991,14 @@ __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep + * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n + * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -904,10 +1015,14 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) /** * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep + * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n + * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) * * (*) value not defined in all devices. * @retval None @@ -1547,7 +1662,9 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_FW @@ -1562,6 +1679,8 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1589,7 +1708,9 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_FW @@ -1604,6 +1725,8 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). @@ -1626,7 +1749,9 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) @@ -1640,6 +1765,8 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1662,7 +1789,9 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG @@ -1677,6 +1806,8 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1699,7 +1830,9 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG @@ -1714,6 +1847,8 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1736,7 +1871,9 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep + * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) @@ -1750,6 +1887,8 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None @@ -1776,7 +1915,9 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep + * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) @@ -1790,6 +1931,8 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) * * (*) value not defined in all devices. * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c index 27b494cdc0..9f902eb443 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_comp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief COMP LL module driver ****************************************************************************** * @attention @@ -94,7 +92,7 @@ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ -#if defined(COMP_CSR_INMESEL_1) && defined(DAC_CHANNEL2_SUPPORT) +#if defined(COMP_CSR_INMESEL_1) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ @@ -108,30 +106,6 @@ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5) \ ) -#elif defined(COMP_CSR_INMESEL_1) -#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO5) \ - ) -#elif defined(DAC_CHANNEL2_SUPPORT) -#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ - ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ - || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ - ) #else #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ @@ -139,6 +113,7 @@ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ ) @@ -156,14 +131,25 @@ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ ) -#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \ + ? ( \ + (1U) \ + ) \ + : \ + (((__COMP_INSTANCE__) == COMP1) \ + ? ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + ) \ + : \ + ( \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2) \ + ) \ + ) \ ) /** @@ -241,7 +227,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus)); assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis)); assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); - assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource)); + assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource)); /* Note: Hardware constraint (refer to description of this function) */ /* COMP instance must not be locked. */ @@ -305,8 +291,8 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru /** * @brief Set each @ref LL_COMP_InitTypeDef field to default value. - * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure - * whose fields will be set to default values. + * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure + * whose fields will be set to default values. * @retval None */ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h index 8d5d8f6ff3..8b02ddb71e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_comp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_comp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of COMP LL module. ****************************************************************************** * @attention @@ -64,7 +62,7 @@ extern "C" { */ /* COMP registers bits positions */ -#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ +#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ /** * @} @@ -127,7 +125,7 @@ typedef struct /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ -#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */ +#define LL_COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */ #define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ /** * @} @@ -136,7 +134,7 @@ typedef struct /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ -#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */ +#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000U) /*!< COMP power mode to high speed */ #define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ #define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */ /** @@ -146,7 +144,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection * @{ */ -#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ +#define LL_COMP_INPUT_PLUS_IO1 (0x00000000U) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */ #define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */ #if defined(COMP_CSR_INPSEL_1) #define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */ @@ -163,9 +161,7 @@ typedef struct #define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */ #define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */ #define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ -#if defined(DAC_CHANNEL2_SUPPORT) #define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ -#endif #define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ #define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */ #if defined(COMP_CSR_INMESEL_1) @@ -187,9 +183,7 @@ typedef struct #define LL_COMP_INVERTINGINPUT_3_4VREFINT LL_COMP_INPUT_MINUS_3_4VREFINT #define LL_COMP_INVERTINGINPUT_VREFINT LL_COMP_INPUT_MINUS_VREFINT #define LL_COMP_INVERTINGINPUT_DAC1 LL_COMP_INPUT_MINUS_DAC1_CH1 -#if defined(DAC_CHANNEL2_SUPPORT) #define LL_COMP_INVERTINGINPUT_DAC2 LL_COMP_INPUT_MINUS_DAC1_CH2 -#endif #define LL_COMP_INVERTINGINPUT_IO1 LL_COMP_INPUT_MINUS_IO1 #define LL_COMP_INVERTINGINPUT_IO2 LL_COMP_INPUT_MINUS_IO2 #if defined(COMP_CSR_INMESEL_1) @@ -210,7 +204,7 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis * @{ */ -#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */ +#define LL_COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ #define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ #define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ #define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ @@ -221,7 +215,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity * @{ */ -#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ +#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ #define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */ /** * @} @@ -230,7 +224,7 @@ typedef struct /** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source * @{ */ -#define LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U) /*!__REG__, (__VALUE__)) +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) /** * @brief Read a value in CRC register @@ -354,7 +352,10 @@ __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) */ __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) { - *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData; + __IO uint16_t *pReg; + + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); + *pReg = InData; } /** @@ -418,10 +419,11 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) /** * @brief Return data stored in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. * @rmtoll IDR IDR LL_CRC_Read_IDR * @param CRCx CRC Instance - * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + * @retval Value stored in CRC_IDR register */ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) { @@ -430,15 +432,20 @@ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) /** * @brief Store data in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. * @rmtoll IDR IDR LL_CRC_Write_IDR * @param CRCx CRC Instance - * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF + * @param InData value to be stored in CRC_IDR register * @retval None */ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) { +#if (CRC_IDR_IDR == 0x0FFU) *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +#else + WRITE_REG(CRCx->IDR, InData); +#endif } /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c index a0a8108087..83b775ad36 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_crs.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief CRS LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h index 40267e697e..4eb39e0989 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_crs.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_crs.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of CRS LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c index 79f8ba4867..30a154f970 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DAC LL module driver ****************************************************************************** * @attention @@ -78,6 +76,22 @@ ) #endif /* DAC_CHANNEL2_SUPPORT */ +#if defined (DAC_CR_TSEL1_3) +#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + ) +#else #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ @@ -88,6 +102,7 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) +#endif /* DAC_CR_TSEL1_3 */ #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h index 74c41604b7..e312a599c3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -269,14 +267,29 @@ typedef struct /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source * @{ */ -#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ -#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ -#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#if defined (DAC_CR_TSEL1_3) +#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 OUT TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 OUT TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ +#else +#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#endif /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c index 88ab69fa2e..c60a79c7e2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32l4xx_ll_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA LL module driver. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,8 +81,11 @@ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) -#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) +#if defined(DMAMUX1) +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 93U) +#else #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ ((__VALUE__) == LL_DMA_REQUEST_1) || \ ((__VALUE__) == LL_DMA_REQUEST_2) || \ @@ -93,6 +94,7 @@ ((__VALUE__) == LL_DMA_REQUEST_5) || \ ((__VALUE__) == LL_DMA_REQUEST_6) || \ ((__VALUE__) == LL_DMA_REQUEST_7)) +#endif /* DMAMUX1 */ #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ @@ -226,8 +228,13 @@ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) /* Reset DMAx_Channely memory address register */ LL_DMA_WriteReg(tmp, CMAR, 0U); +#if defined(DMAMUX1) + /* Reset Request register field for DMAx Channel */ + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQUEST_MEM2MEM); +#else /* Reset Request register field for DMAx Channel */ LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); +#endif /* DMAMUX1 */ if (Channel == LL_DMA_CHANNEL_1) { @@ -347,11 +354,19 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM */ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); +#if defined(DMAMUX1) + /*--------------------------- DMAMUXx CCR Configuration ---------------------- + * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter : + * - PeriphRequest: DMA_CxCR[7:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); +#else /*--------------------------- DMAx CSELR Configuration ----------------------- - * Configure the peripheral base address with parameter : + * Configure the DMA request for DMA instance on Channel x with parameter : * - PeriphRequest: DMA_CSELR[31:0] bits */ LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); +#endif /* DMAMUX1 */ return SUCCESS; } @@ -364,16 +379,20 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) { /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; - DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct->NbData = (uint32_t)0x00000000U; + DMA_InitStruct->NbData = 0x00000000U; +#if defined(DMAMUX1) + DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQUEST_MEM2MEM; +#else DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; +#endif /* DMAMUX1 */ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h index 65ac16c405..f6c75b0416 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dma.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA LL module. ****************************************************************************** * @attention @@ -45,6 +43,9 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx.h" +#if defined(DMAMUX1) +#include "stm32l4xx_ll_dmamux.h" +#endif /* DMAMUX1 */ /** @addtogroup STM32L4xx_LL_Driver * @{ @@ -77,6 +78,8 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = */ /* Private constants ---------------------------------------------------------*/ +#if defined(DMAMUX1) +#else /** @defgroup DMA_LL_Private_Constants DMA Private Constants * @{ */ @@ -88,8 +91,27 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = /** * @} */ +#endif /* DMAMUX1 */ /* Private macros ------------------------------------------------------------*/ +#if defined(DMAMUX1) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). + */ +#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) + +/** + * @} + */ +#else #if defined(USE_FULL_LL_DRIVER) /** @defgroup DMA_LL_Private_Macros DMA Private Macros * @{ @@ -98,6 +120,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = * @} */ #endif /*USE_FULL_LL_DRIVER*/ +#endif /* DMAMUX1 */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) @@ -159,11 +182,19 @@ typedef struct This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ +#if defined(DMAMUX1) + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#else uint32_t PeriphRequest; /*!< Specifies the peripheral request. This parameter can be a value of @ref DMA_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ +#endif /* DMAMUX1 */ uint32_t Priority; /*!< Specifies the channel priority level. This parameter can be a value of @ref DMA_LL_EC_PRIORITY @@ -266,15 +297,15 @@ typedef struct /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ -#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */ -#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */ -#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ #if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} @@ -283,7 +314,7 @@ typedef struct /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction * @{ */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** @@ -293,7 +324,7 @@ typedef struct /** @defgroup DMA_LL_EC_MODE Transfer mode * @{ */ -#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ /** * @} @@ -303,7 +334,7 @@ typedef struct * @{ */ #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ @@ -312,7 +343,7 @@ typedef struct * @{ */ #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ @@ -320,7 +351,7 @@ typedef struct /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment * @{ */ -#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** @@ -330,7 +361,7 @@ typedef struct /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment * @{ */ -#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** @@ -340,7 +371,7 @@ typedef struct /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level * @{ */ -#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ @@ -348,20 +379,123 @@ typedef struct * @} */ -/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request +#if defined(DMAMUX1) +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request * @{ */ -#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /*!< DMA peripheral request 0 */ -#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /*!< DMA peripheral request 1 */ -#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /*!< DMA peripheral request 2 */ -#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /*!< DMA peripheral request 3 */ -#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /*!< DMA peripheral request 4 */ -#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /*!< DMA peripheral request 5 */ -#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /*!< DMA peripheral request 6 */ -#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /*!< DMA peripheral request 7 */ +#define LL_DMAMUX_REQUEST_MEM2MEM 0U /*!< Memory to memory transfer */ +#define LL_DMAMUX_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ +#define LL_DMAMUX_REQUEST_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ +#define LL_DMAMUX_REQUEST_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ +#define LL_DMAMUX_REQUEST_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ +#define LL_DMAMUX_REQUEST_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQUEST_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQUEST_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQUEST_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQUEST_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQUEST_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ +#define LL_DMAMUX_REQUEST_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQUEST_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQUEST_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQUEST_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ +#define LL_DMAMUX_REQUEST_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQUEST_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ +#define LL_DMAMUX_REQUEST_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ +#define LL_DMAMUX_REQUEST_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ +#define LL_DMAMUX_REQUEST_USART1_RX 24U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQUEST_USART1_TX 25U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQUEST_USART2_RX 26U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQUEST_USART2_TX 27U /*!< DMAMUX USART2 TX request */ +#define LL_DMAMUX_REQUEST_USART3_RX 28U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQUEST_USART3_TX 29U /*!< DMAMUX USART3 TX request */ +#define LL_DMAMUX_REQUEST_UART4_RX 30U /*!< DMAMUX UART4 RX request */ +#define LL_DMAMUX_REQUEST_UART4_TX 31U /*!< DMAMUX UART4 TX request */ +#define LL_DMAMUX_REQUEST_UART5_RX 32U /*!< DMAMUX UART5 RX request */ +#define LL_DMAMUX_REQUEST_UART5_TX 33U /*!< DMAMUX UART5 TX request */ +#define LL_DMAMUX_REQUEST_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQUEST_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ +#define LL_DMAMUX_REQUEST_SAI1_A 36U /*!< DMAMUX SAI1 A request */ +#define LL_DMAMUX_REQUEST_SAI1_B 37U /*!< DMAMUX SAI1 B request */ +#define LL_DMAMUX_REQUEST_SAI2_A 38U /*!< DMAMUX SAI2 A request */ +#define LL_DMAMUX_REQUEST_SAI2_B 39U /*!< DMAMUX SAI2 B request */ +#define LL_DMAMUX_REQUEST_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ +#define LL_DMAMUX_REQUEST_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ +#define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ +#define LL_DMAMUX_REQUEST_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ +#define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ +#define LL_DMAMUX_REQUEST_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ +#define LL_DMAMUX_REQUEST_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ +#define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ +#define LL_DMAMUX_REQUEST_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ +#define LL_DMAMUX_REQUEST_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ +#define LL_DMAMUX_REQUEST_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ +#define LL_DMAMUX_REQUEST_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ +#define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ +#define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ +#define LL_DMAMUX_REQUEST_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ +#define LL_DMAMUX_REQUEST_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQUEST_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQUEST_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ +#define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ +#define LL_DMAMUX_REQUEST_DCMI 90U /*!< DMAMUX DCMI request */ +#define LL_DMAMUX_REQUEST_AES_IN 91U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQUEST_AES_OUT 92U /*!< DMAMUX AES_OUT request */ +#define LL_DMAMUX_REQUEST_HASH_IN 93U /*!< DMAMUX HASH_IN request */ /** * @} */ +#else +/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request + * @{ + */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +/** + * @} + */ +#endif /* DMAMUX1 */ /** * @} @@ -1198,6 +1332,238 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } +#if defined(DMAMUX1) +/** + * @brief Set DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 + * @arg @ref LL_DMAMUX_REQUEST_ADC1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP + * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX + * @arg @ref LL_DMAMUX_REQUEST_USART1_RX + * @arg @ref LL_DMAMUX_REQUEST_USART1_TX + * @arg @ref LL_DMAMUX_REQUEST_USART2_RX + * @arg @ref LL_DMAMUX_REQUEST_USART2_TX + * @arg @ref LL_DMAMUX_REQUEST_USART3_RX + * @arg @ref LL_DMAMUX_REQUEST_USART3_TX + * @arg @ref LL_DMAMUX_REQUEST_UART4_RX + * @arg @ref LL_DMAMUX_REQUEST_UART4_TX + * @arg @ref LL_DMAMUX_REQUEST_UART5_RX + * @arg @ref LL_DMAMUX_REQUEST_UART5_TX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX + * @arg @ref LL_DMAMUX_REQUEST_SAI1_A + * @arg @ref LL_DMAMUX_REQUEST_SAI1_B + * @arg @ref LL_DMAMUX_REQUEST_SAI2_A + * @arg @ref LL_DMAMUX_REQUEST_SAI2_B + * @arg @ref LL_DMAMUX_REQUEST_OSPI1 + * @arg @ref LL_DMAMUX_REQUEST_OSPI2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQUEST_DCMI + * @arg @ref LL_DMAMUX_REQUEST_AES_IN + * @arg @ref LL_DMAMUX_REQUEST_AES_OUT + * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 + * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 + * @arg @ref LL_DMAMUX_REQUEST_ADC1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP + * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX + * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX + * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX + * @arg @ref LL_DMAMUX_REQUEST_USART1_RX + * @arg @ref LL_DMAMUX_REQUEST_USART1_TX + * @arg @ref LL_DMAMUX_REQUEST_USART2_RX + * @arg @ref LL_DMAMUX_REQUEST_USART2_TX + * @arg @ref LL_DMAMUX_REQUEST_USART3_RX + * @arg @ref LL_DMAMUX_REQUEST_USART3_TX + * @arg @ref LL_DMAMUX_REQUEST_UART4_RX + * @arg @ref LL_DMAMUX_REQUEST_UART4_TX + * @arg @ref LL_DMAMUX_REQUEST_UART5_RX + * @arg @ref LL_DMAMUX_REQUEST_UART5_TX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX + * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX + * @arg @ref LL_DMAMUX_REQUEST_SAI1_A + * @arg @ref LL_DMAMUX_REQUEST_SAI1_B + * @arg @ref LL_DMAMUX_REQUEST_SAI2_A + * @arg @ref LL_DMAMUX_REQUEST_SAI2_B + * @arg @ref LL_DMAMUX_REQUEST_OSPI1 + * @arg @ref LL_DMAMUX_REQUEST_OSPI2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM + * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP + * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQUEST_DCMI + * @arg @ref LL_DMAMUX_REQUEST_AES_IN + * @arg @ref LL_DMAMUX_REQUEST_AES_OUT + * @arg @ref LL_DMAMUX_REQUEST_HASH_IN + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} +#else /** * @brief Set DMA request for DMA instance on Channel x. * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. @@ -1267,6 +1633,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); } +#endif /* DMAMUX1 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c index 2bdd4e5aaa..3f1012ea3e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dma2d.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief DMA2D LL module driver. ****************************************************************************** * @attention @@ -73,10 +71,19 @@ /** @addtogroup DMA2D_LL_Private_Macros * @{ */ +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) +#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \ + ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \ + ((MODE) == LL_DMA2D_MODE_R2M)) +#else #define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \ ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ ((MODE) == LL_DMA2D_MODE_R2M)) +#endif #define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \ ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \ @@ -202,6 +209,12 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed)); assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue)); assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha)); +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + assert_param(IS_LL_DMA2D_SWAP_MODE(DMA2D_InitStruct->OutputSwapMode)); +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + assert_param(IS_LL_DMA2D_OFFSET_MODE(DMA2D_InitStruct->LineOffsetMode)); +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset)); assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode)); assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode)); @@ -213,11 +226,21 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U)) { /* DMA2D CR register configuration -------------------------------------------*/ +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + MODIFY_REG(DMA2Dx->CR, (DMA2D_CR_MODE | DMA2D_CR_LOM), \ + (DMA2D_InitStruct->Mode | DMA2D_InitStruct->LineOffsetMode)); +#else LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode); +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ /* DMA2D OPFCCR register configuration ---------------------------------------*/ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB | DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), \ + (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->OutputSwapMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); +#else MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \ (DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode)); +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ /* DMA2D OOR register configuration ------------------------------------------*/ LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset); @@ -256,12 +279,18 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888; DMA2D_InitStruct->NbrOfLines = 0x0U; DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U; +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + DMA2D_InitStruct->LineOffsetMode = LL_DMA2D_LINE_OFFSET_PIXELS; +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ DMA2D_InitStruct->LineOffset = 0x0U; DMA2D_InitStruct->OutputBlue = 0x0U; DMA2D_InitStruct->OutputGreen = 0x0U; DMA2D_InitStruct->OutputRed = 0x0U; DMA2D_InitStruct->OutputAlpha = 0x0U; DMA2D_InitStruct->OutputMemoryAddress = 0x0U; +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + DMA2D_InitStruct->OutputSwapMode = LL_DMA2D_SWAP_MODE_REGULAR; +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h index d0069d03b4..3cf689e711 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma2d.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of DMA2D LL module. ****************************************************************************** * @attention @@ -135,8 +133,23 @@ typedef struct This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) + uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) + uint32_t LineOffsetMode; /*!< Specifies the output line offset mode. + - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE. + + This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + uint32_t LineOffset; /*!< Specifies the output line offset value. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on STM32L496xx/STM32L4A6xx + else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices. This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ @@ -355,7 +368,11 @@ typedef struct #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ -#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ +#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */ +#if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */ +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */ +#endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ /** * @} */ @@ -401,6 +418,17 @@ typedef struct * @} */ +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) +/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode + * @{ + */ +#define LL_DMA2D_SWAP_MODE_REGULAR ((uint32_t)0x00000000) /*!< Regular order */ +#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ +/** + * @} + */ +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap * @{ */ @@ -419,6 +447,17 @@ typedef struct * @} */ +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) +/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode + * @{ + */ +#define LL_DMA2D_LINE_OFFSET_PIXELS ((uint32_t)0x00000000) /*!< Line offsets are expressed in pixels */ +#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ +/** + * @} + */ +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode * @{ */ @@ -567,6 +606,10 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) * @arg @ref LL_DMA2D_MODE_M2M_PFC * @arg @ref LL_DMA2D_MODE_M2M_BLEND * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*) + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) @@ -583,6 +626,10 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * @arg @ref LL_DMA2D_MODE_M2M_PFC * @arg @ref LL_DMA2D_MODE_M2M_BLEND * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*) + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) { @@ -676,11 +723,73 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } +#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) +/** + * @brief Set DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @param OutputSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode); +} + +/** + * @brief Return DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); +} +#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ + +#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) +/** + * @brief Set DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @param LineOffsetMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode); +} + +/** + * @brief Return DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); +} +#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ + /** * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). * @rmtoll OOR LO LL_DMA2D_SetLineOffset * @param DMA2Dx DMA2D Instance + @if DMA2D_LINE_OFFSET_MODE_SUPPORT + * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF + @else * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF + @endif * @retval None */ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) @@ -692,7 +801,11 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). * @rmtoll OOR LO LL_DMA2D_GetLineOffset * @param DMA2Dx DMA2D Instance + @if DMA2D_LINE_OFFSET_MODE_SUPPORT + * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF + @else * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF + @endif */ __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h new file mode 100644 index 0000000000..66a10c9d19 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dmamux.h @@ -0,0 +1,1795 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_LL_DMAMUX_H +#define __STM32L4xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQ_MEM2MEM 0U /*!< Memory to memory transfer */ +#define LL_DMAMUX_REQ_GENERATOR0 1U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQ_GENERATOR1 2U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQ_GENERATOR2 3U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQ_GENERATOR3 4U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQ_ADC1 5U /*!< DMAMUX ADC1 request */ +#define LL_DMAMUX_REQ_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ +#define LL_DMAMUX_REQ_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ +#define LL_DMAMUX_REQ_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ +#define LL_DMAMUX_REQ_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ +#define LL_DMAMUX_REQ_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQ_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQ_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQ_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ +#define LL_DMAMUX_REQ_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQ_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ +#define LL_DMAMUX_REQ_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQ_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ +#define LL_DMAMUX_REQ_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ +#define LL_DMAMUX_REQ_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ +#define LL_DMAMUX_REQ_USART1_RX 24U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 25U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 26U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 27U /*!< DMAMUX USART2 TX request */ +#define LL_DMAMUX_REQ_USART3_RX 28U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 29U /*!< DMAMUX USART3 TX request */ +#define LL_DMAMUX_REQ_UART4_RX 30U /*!< DMAMUX UART4 RX request */ +#define LL_DMAMUX_REQ_UART4_TX 31U /*!< DMAMUX UART4 TX request */ +#define LL_DMAMUX_REQ_UART5_RX 32U /*!< DMAMUX UART5 RX request */ +#define LL_DMAMUX_REQ_UART5_TX 33U /*!< DMAMUX UART5 TX request */ +#define LL_DMAMUX_REQ_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQ_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ +#define LL_DMAMUX_REQ_SAI1_A 36U /*!< DMAMUX SAI1 A request */ +#define LL_DMAMUX_REQ_SAI1_B 37U /*!< DMAMUX SAI1 B request */ +#define LL_DMAMUX_REQ_SAI2_A 38U /*!< DMAMUX SAI2 A request */ +#define LL_DMAMUX_REQ_SAI2_B 39U /*!< DMAMUX SAI2 B request */ +#define LL_DMAMUX_REQ_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ +#define LL_DMAMUX_REQ_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ +#define LL_DMAMUX_REQ_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ +#define LL_DMAMUX_REQ_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ +#define LL_DMAMUX_REQ_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ +#define LL_DMAMUX_REQ_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ +#define LL_DMAMUX_REQ_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ +#define LL_DMAMUX_REQ_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ +#define LL_DMAMUX_REQ_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ +#define LL_DMAMUX_REQ_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ +#define LL_DMAMUX_REQ_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ +#define LL_DMAMUX_REQ_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ +#define LL_DMAMUX_REQ_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ +#define LL_DMAMUX_REQ_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQ_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQ_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQ_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQ_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ +#define LL_DMAMUX_REQ_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ +#define LL_DMAMUX_REQ_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQ_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQ_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQ_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQ_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ +#define LL_DMAMUX_REQ_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ +#define LL_DMAMUX_REQ_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ +#define LL_DMAMUX_REQ_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ +#define LL_DMAMUX_REQ_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ +#define LL_DMAMUX_REQ_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ +#define LL_DMAMUX_REQ_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ +#define LL_DMAMUX_REQ_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ +#define LL_DMAMUX_REQ_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ +#define LL_DMAMUX_REQ_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ +#define LL_DMAMUX_REQ_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ +#define LL_DMAMUX_REQ_DCMI 90U /*!< DMAMUX DCMI request */ +#define LL_DMAMUX_REQ_AES_IN 91U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQ_AES_OUT 92U /*!< DMAMUX AES_OUT request */ +#define LL_DMAMUX_REQ_HASH_IN 93U /*!< DMAMUX HASH_IN request */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 1U /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 2U /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 3U /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 4U /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 5U /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 6U /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 7U /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 8U /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 9U /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 10U /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 11U /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 12U /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 13U /*!< Synchronization signal from EXTI Line13 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 14U /*!< Synchronization signal from EXTI Line14 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 15U /*!< Synchronization signal from EXTI Line15 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 16U /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 17U /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH2 18U /*!< Synchronization signal from DMAMUX channel2 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH3 19U /*!< Synchronization signal from DMAMUX channel3 Event */ +#define LL_DMAMUX_SYNC_LPTIM1_OUT 20U /*!< Synchronization signal from LPTIM1 Ouput */ +#define LL_DMAMUX_SYNC_LPTIM2_OUT 21U /*!< Synchronization signal from LPTIM2 Ouput */ +#define LL_DMAMUX_SYNC_DSI_TE 22U /*!< Synchronization signal from DSI Tearing Effect */ +#define LL_DMAMUX_SYNC_DSI_REFRESH_END 23U /*!< Synchronization signal from DSI End of Refresh */ +#define LL_DMAMUX_SYNC_DMA2D_TX_END 24U /*!< Synchronization signal from DMA2D End of Transfer */ +#define LL_DMAMUX_SYNC_LTDC_LINE_IT 25U /*!< Synchronization signal from LTDC Line Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 1U /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 2U /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 3U /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 4U /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 5U /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 6U /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 7U /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 8U /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 9U /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 10U /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 11U /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 12U /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 13U /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 14U /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 15U /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 16U /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 17U /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 18U /*!< Request signal generation from DMAMUX channel2 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 19U /*!< Request signal generation from DMAMUX channel3 Event */ +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT 20U /*!< Request signal generation from LPTIM1 Ouput */ +#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT 21U /*!< Request signal generation from LPTIM2 Ouput */ +#define LL_DMAMUX_REQ_GEN_DSI_TE 22U /*!< Request signal generation from DSI Tearing Effect */ +#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END 23U /*!< Request signal generation from DSI End of Refresh */ +#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END 24U /*!< Request signal generation from DMA2D End of Transfer */ +#define LL_DMAMUX_REQ_GEN_LTDC_LINE_IT 25U /*!< Request signal generation from LTDC Line Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_SPI3_RX + * @arg @ref LL_DMAMUX_REQ_SPI3_TX + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_I2C3_RX + * @arg @ref LL_DMAMUX_REQ_I2C3_TX + * @arg @ref LL_DMAMUX_REQ_I2C4_RX + * @arg @ref LL_DMAMUX_REQ_I2C4_TX + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_UART4_RX + * @arg @ref LL_DMAMUX_REQ_UART4_TX + * @arg @ref LL_DMAMUX_REQ_UART5_RX + * @arg @ref LL_DMAMUX_REQ_UART5_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SAI1_A + * @arg @ref LL_DMAMUX_REQ_SAI1_B + * @arg @ref LL_DMAMUX_REQ_SAI2_A + * @arg @ref LL_DMAMUX_REQ_SAI2_B + * @arg @ref LL_DMAMUX_REQ_OSPI1 + * @arg @ref LL_DMAMUX_REQ_OSPI2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM1_COM + * @arg @ref LL_DMAMUX_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM8_UP + * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM8_COM + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM4_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM4_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM5_UP + * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM15_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX_REQ_DCMI + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_HASH_IN + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel-1)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ, RequestNb - 1); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ) + 1); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)); +} + +/** + * @brief Enable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_DSI_TE + * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END + * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_DSI_TE + * @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END + * @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END + * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE + * @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END + * @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END + * @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 12. + * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 13. + * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)); +} + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 12. + * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 13. + * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); +} + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE)); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_LL_DMAMUX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c index e94a1192ba..c97b41c126 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_exti.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief EXTI LL module driver. ****************************************************************************** * @attention @@ -108,11 +106,15 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FTSR1, 0x00000000U); /* Software interrupt event register set to default reset values */ LL_EXTI_WriteReg(SWIER1, 0x00000000U); - /* Pending register set to default reset values */ + /* Pending register clear */ LL_EXTI_WriteReg(PR1, 0x007DFFFFU); /* Interrupt mask register 2 set to default reset values */ +#if defined(LL_EXTI_LINE_40) + LL_EXTI_WriteReg(IMR2, 0x00000187U); +#else LL_EXTI_WriteReg(IMR2, 0x00000087U); +#endif /* Event mask register 2 set to default reset values */ LL_EXTI_WriteReg(EMR2, 0x00000000U); /* Rising Trigger selection register 2 set to default reset values */ @@ -121,7 +123,7 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FTSR2, 0x00000000U); /* Software interrupt event register 2 set to default reset values */ LL_EXTI_WriteReg(SWIER2, 0x00000000U); - /* Pending register 2 set to default reset values */ + /* Pending register 2 clear */ LL_EXTI_WriteReg(PR2, 0x00000078U); return SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h index 8e31cc7a09..9127ab2f91 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_exti.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_exti.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention @@ -187,6 +185,9 @@ typedef struct #if defined(EXTI_IMR2_IM39) #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ #endif +#if defined(EXTI_IMR2_IM40) +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#endif #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ @@ -329,13 +330,15 @@ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) @@ -400,13 +403,15 @@ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) @@ -471,13 +476,15 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) @@ -545,13 +552,15 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) @@ -610,13 +619,15 @@ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) @@ -676,13 +687,15 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 - * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_34(*) * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 - * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_39(*) + * @arg @ref LL_EXTI_LINE_40(*) * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note (*): Available in some devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c index 509f8b2c72..c052ded246 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_fmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -111,7 +109,17 @@ /* --- BCR Register ---*/ /* BCR register clear mask */ -#if defined(FMC_BCR1_WFDIS) +#if defined(FMC_BCRx_NBLSET) +#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ + FMC_BCRx_MTYP | FMC_BCRx_MWID |\ + FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ + FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\ + FMC_BCRx_WREN | FMC_BCRx_WAITEN |\ + FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\ + FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ + FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS |\ + FMC_BCRx_NBLSET)) +#elif defined(FMC_BCR1_WFDIS) #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ FMC_BCRx_MTYP | FMC_BCRx_MWID |\ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ @@ -133,16 +141,29 @@ /* --- BTR Register ---*/ /* BTR register clear mask */ -#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ - FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ - FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ - FMC_BTRx_ACCMOD)) +#if defined(FMC_BTRx_DATAHLD) +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ + FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ + FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ + FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD)) +#else +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ + FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ + FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ + FMC_BTRx_ACCMOD)) +#endif /* FMC_BTRx_DATAHLD */ /* --- BWTR Register ---*/ /* BWTR register clear mask */ -#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD | \ - FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD | \ - FMC_BWTRx_BUSTURN)) +#if defined(FMC_BWTRx_DATAHLD) +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ + FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD)) +#else +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ + FMC_BWTRx_ACCMOD)) +#endif /* FMC_BWTRx_DATAHLD */ /** * @} @@ -234,6 +255,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); #endif /* FMC_BCR1_WFDIS */ +#if defined(FMC_BCRx_NBLSET) + assert_param(IS_FMC_NBLSETUP_TIME(Init->NBLSetupTime)); +#endif /* FMC_BCRx_NBLSET */ assert_param(IS_FMC_PAGESIZE(Init->PageSize)); /* Disable NORSRAM Device */ @@ -258,6 +282,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) | Init->WriteFifo #endif /* FMC_BCR1_WFDIS */ +#if defined(FMC_BCRx_NBLSET) + | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) +#endif /* FMC_BCRx_NBLSET */ | Init->PageSize ) ); @@ -280,6 +307,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini #if defined(FMC_BCR1_WFDIS) | Init->WriteFifo #endif /* FMC_BCR1_WFDIS */ +#if defined(FMC_BCRx_NBLSET) + | Init->NBLSetupTime << POSITION_VAL(FMC_BCRx_NBLSET) +#endif /* FMC_BCRx_NBLSET */ | Init->PageSize ) ); @@ -297,8 +327,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); } - #endif /* FMC_BCR1_WFDIS */ + return HAL_OK; } @@ -356,6 +386,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); +#if defined(FMC_BTRx_DATAHLD) + assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); +#endif /* FMC_BTRx_DATAHLD */ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); @@ -363,14 +396,17 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1], \ - BTR_CLEAR_MASK, \ - (uint32_t)(Timing->AddressSetupTime | \ - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | \ - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | \ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | \ - (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | \ - (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | \ + MODIFY_REG(Device->BTCR[Bank + 1], + BTR_CLEAR_MASK, + (uint32_t)(Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | + ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | +#if defined(FMC_BTRx_DATAHLD) + ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | +#endif /* FMC_BTRx_DATAHLD */ + ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | + (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | + (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | (Timing->AccessMode))); /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ @@ -408,18 +444,24 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); +#if defined(FMC_BTRx_DATAHLD) + assert_param(IS_FMC_DATAHOLD_TIME(Timing->DataHoldTime)); +#endif /* FMC_BTRx_DATAHLD */ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - MODIFY_REG(Device->BWTR[Bank], \ - BWTR_CLEAR_MASK, \ - (uint32_t)(Timing->AddressSetupTime | \ - ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \ - ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | \ - Timing->AccessMode | \ + MODIFY_REG(Device->BWTR[Bank], + BWTR_CLEAR_MASK, + (uint32_t)(Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | + ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | +#if defined(FMC_BTRx_DATAHLD) + ((Timing->DataHoldTime) << POSITION_VAL(FMC_BTRx_DATAHLD)) | +#endif /* FMC_BTRx_DATAHLD */ + Timing->AccessMode | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BWTRx_BUSTURN)))); } else diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h index c6e66f07c7..e22ecd214d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_fmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention @@ -91,8 +89,12 @@ extern "C" { #if defined(FMC_BCR1_WFDIS) #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) - #endif /* FMC_BCR1_WFDIS */ + +#if defined(FMC_BCRx_NBLSET) +#define IS_FMC_NBLSETUP_TIME(__TIME__) ((__TIME__) <= 3) +#endif /* FMC_BCRx_NBLSET */ + #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ ((__MODE__) == FMC_ACCESS_MODE_B) || \ ((__MODE__) == FMC_ACCESS_MODE_C) || \ @@ -247,6 +249,16 @@ extern "C" { * @} */ +#if defined(FMC_BTRx_DATAHLD) +/** @defgroup FMC_Data_Hold_Time + * @{ + */ +#define IS_FMC_DATAHOLD_TIME(__TIME__) ((__TIME__) <= 3) +/** + * @} + */ +#endif /* FMC_BTRx_DATAHLD */ + /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration * @{ */ @@ -333,6 +345,13 @@ typedef struct This parameter can be a value of @ref FMC_Write_FIFO. @note This Parameter is not available for STM32L47x/L48x devices. */ +#if defined(FMC_BCRx_NBLSET) + uint32_t NBLSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the byte lane (NBL) setup time from NBLx low to Chip select NEx low. + This parameter can be a value between Min_Data = 0 and Max_Data = 3. + @note This parameter is used for SRAMs, ROMs and NOR Flash memories. */ +#endif /* FMC_BCRx_NBLSET */ + uint32_t PageSize; /*!< Specifies the memory page size. This parameter can be a value of @ref FMC_Page_Size */ }FMC_NORSRAM_InitTypeDef; @@ -358,6 +377,16 @@ typedef struct @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ +#if defined(FMC_BTRx_DATAHLD) + uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data hold time. + This parameter can be a value between Min_Data = 0 and Max_Data = 3. + @note This parameter value corresponds to x HCLK cycles for read and + x+1 HCLK cycles for write. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ +#endif /* FMC_BTRx_DATAHLD */ + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. @@ -725,9 +754,9 @@ typedef struct * @brief FMC Interrupt definition * @{ */ -#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) -#define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) -#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) +#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) +#define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) +#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c index ea68657a92..0bd742a8d2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief GPIO LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h index 0b0a30722c..ae61d32827 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c index 123155a1b4..8d8105b0de 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_i2c.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief I2C LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h index bcb74180e8..564210d489 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_i2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of I2C LL module. ****************************************************************************** * @attention @@ -283,14 +281,14 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -1099,7 +1097,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) + uint32_t TimeoutB) { MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); @@ -2106,9 +2104,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) * @retval None */ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h index d691da4efa..0ab5630db2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c index 5eef8c67ee..c776c5c67c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lptim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LPTIM LL module driver. ****************************************************************************** * @attention @@ -63,23 +61,23 @@ /** @addtogroup LPTIM_LL_Private_Macros * @{ */ -#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) +#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) -#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) +#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) -#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) +#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) -#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) +#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -169,10 +167,10 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); - assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); - assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); - assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); /* Set CKSEL bitfield according to ClockSource value */ /* Set PRESC bitfield according to Prescaler value */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h index 3edb39542b..fc04402a39 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lptim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LPTIM LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c index 7b1459a329..dc74d16025 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lpuart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief LPUART LL module driver. ****************************************************************************** * @attention @@ -75,6 +73,21 @@ /* Check of parameters for configuration of LPUART registers */ +#if defined(USART_PRESC_PRESCALER) +#define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + +#endif /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ /* value : */ /* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ @@ -172,6 +185,9 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART /* Check the parameters */ assert_param(IS_LPUART_INSTANCE(LPUARTx)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue)); +#endif assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); @@ -211,6 +227,9 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); /* Configure the LPUART Baud Rate : +#if defined(USART_PRESC_PRESCALER) + - prescaler value is required +#endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ @@ -220,11 +239,22 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART status = SUCCESS; LL_LPUART_SetBaudRate(LPUARTx, periphclk, +#if defined(USART_PRESC_PRESCALER) + LPUART_InitStruct->PrescalerValue, +#endif LPUART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 0x300 */ assert_param(IS_LL_LPUART_BRR(LPUARTx->BRR)); } +#if defined(USART_PRESC_PRESCALER) + + /*---------------------------- LPUART PRESC Configuration ----------------------- + * Configure LPUARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. + */ + LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue); +#endif } return (status); @@ -240,6 +270,9 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) { /* Set LPUART_InitStruct fields to default values */ +#if defined(USART_PRESC_PRESCALER) + LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; +#endif LPUART_InitStruct->BaudRate = 9600U; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h index 076c3bd388..d91b729458 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lpuart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_lpuart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of LPUART LL module. ****************************************************************************** * @attention @@ -58,6 +56,30 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256 +}; +/** + * @} + */ +#endif /* Private constants ---------------------------------------------------------*/ /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants @@ -93,6 +115,13 @@ extern "C" { */ typedef struct { +#if defined(USART_PRESC_PRESCALER) + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/ + +#endif uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/ @@ -143,6 +172,9 @@ typedef struct #define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ +#endif #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ @@ -160,9 +192,17 @@ typedef struct #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#else #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ +#endif #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#else #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ +#endif #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ @@ -172,6 +212,12 @@ typedef struct #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#endif /** * @} */ @@ -181,17 +227,48 @@ typedef struct * @{ */ #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#else #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#endif #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#else #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#endif #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#endif #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#endif /** * @} */ +#if defined(USART_CR1_FIFOEN) + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ +#endif /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ @@ -232,6 +309,27 @@ typedef struct /** * @} */ +#if defined(USART_PRESC_PRESCALER) + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +/** + * @} + */ +#endif /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ @@ -376,10 +474,30 @@ typedef struct * @brief Compute LPUARTDIV value according to Peripheral Clock and * expected Baud Rate (20-bit value of LPUARTDIV is returned) * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + @if USART_PRESC_PRESCALER + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __PRESCALER__ Prescaler value + @endif * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ +#if defined(USART_PRESC_PRESCALER) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#else #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#endif /** * @} @@ -439,6 +557,137 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); } +#if defined(USART_CR1_FIFOEN) +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); +} +#endif + /** * @brief LPUART enabled in STOP Mode * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that @@ -677,6 +926,55 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); } +#if defined(USART_PRESC_PRESCALER) +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} +#endif + /** * @brief Set the length of the stop bits * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength @@ -1086,12 +1384,35 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) * @rmtoll BRR BRR LL_LPUART_SetBaudRate * @param LPUARTx LPUART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + @endif * @param BaudRate Baud Rate * @retval None */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) +#else __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate) +#endif { +#if defined(USART_PRESC_PRESCALER) + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); +#else LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); +#endif } /** @@ -1101,18 +1422,44 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri * @rmtoll BRR BRR LL_LPUART_GetBaudRate * @param LPUARTx LPUART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + @endif * @retval Baud Rate */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) +#else __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk) +#endif { register uint32_t lpuartdiv = 0x0U; register uint32_t brrresult = 0x0U; +#if defined(USART_PRESC_PRESCALER) + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[PrescalerValue])); +#endif lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; if (lpuartdiv >= LPUART_BRR_MIN_VALUE) { +#if defined(USART_PRESC_PRESCALER) + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); +#else brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); +#endif } return (brrresult); @@ -1336,6 +1683,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); +} +#else + /** * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE @@ -1346,6 +1710,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); } +#endif /** * @brief Check if the LPUART Transmission Complete Flag is set or not @@ -1358,6 +1723,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); +} +#else + /** * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE @@ -1368,6 +1750,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); } +#endif /** * @brief Check if the LPUART CTS interrupt Flag is set or not @@ -1468,6 +1851,53 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); +} +#endif + /** * @brief Clear Parity Error Flag * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE @@ -1523,6 +1953,20 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Clear TX FIFO Empty Flag + * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF); +} +#endif + /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC @@ -1586,6 +2030,23 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Enable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE @@ -1596,6 +2057,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Enable Transmission Complete Interrupt @@ -1608,6 +2070,23 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Enable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE @@ -1618,6 +2097,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx) { SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Enable Parity Error Interrupt @@ -1641,6 +2121,31 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Enable Error Interrupt * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing @@ -1678,6 +2183,31 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Disable IDLE Interrupt * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE @@ -1689,6 +2219,23 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Disable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE @@ -1699,6 +2246,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Disable Transmission Complete Interrupt @@ -1711,6 +2259,23 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Disable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE @@ -1721,6 +2286,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx) { CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Disable Parity Error Interrupt @@ -1744,6 +2310,31 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Disable Error Interrupt * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing @@ -1781,6 +2372,31 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE @@ -1792,6 +2408,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); +} +#else + /** * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled. * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE @@ -1802,6 +2435,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); } +#endif /** * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. @@ -1814,6 +2448,23 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); +} +#else + /** * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled. * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE @@ -1824,6 +2475,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); } +#endif /** * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. @@ -1846,6 +2498,30 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) { return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); +} +#endif /** * @brief Check if the LPUART Error Interrupt is enabled or disabled. @@ -1880,6 +2556,31 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) +{ + return (READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); +} +#endif + /** * @} */ @@ -2100,7 +2801,13 @@ __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) } /** + @if USART_CR1_FIFOEN + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + @else * @brief Request a Receive Data flush + @endif * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush * @param LPUARTx LPUART Instance * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c index 49be22d1bb..6e0653a383 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_opamp.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief OPAMP LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h index 22ee05d63b..a77c0044e4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_opamp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_opamp.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of OPAMP LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c index 7c6d7b16db..b934799fda 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief PWR LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h index d870a8477d..1d1f4624c3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of PWR LL module. ****************************************************************************** * @attention @@ -185,7 +183,7 @@ extern "C" { /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR * @{ */ -#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000) +#define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U) #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) /** * @} @@ -218,22 +216,22 @@ extern "C" { /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT * @{ */ -#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001) -#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002) -#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004) -#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008) -#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010) -#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020) -#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040) -#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080) -#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100) -#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200) -#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400) -#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800) -#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000) -#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000) -#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000) -#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000) +#define LL_PWR_GPIO_BIT_0 (0x00000001U) +#define LL_PWR_GPIO_BIT_1 (0x00000002U) +#define LL_PWR_GPIO_BIT_2 (0x00000004U) +#define LL_PWR_GPIO_BIT_3 (0x00000008U) +#define LL_PWR_GPIO_BIT_4 (0x00000010U) +#define LL_PWR_GPIO_BIT_5 (0x00000020U) +#define LL_PWR_GPIO_BIT_6 (0x00000040U) +#define LL_PWR_GPIO_BIT_7 (0x00000080U) +#define LL_PWR_GPIO_BIT_8 (0x00000100U) +#define LL_PWR_GPIO_BIT_9 (0x00000200U) +#define LL_PWR_GPIO_BIT_10 (0x00000400U) +#define LL_PWR_GPIO_BIT_11 (0x00000800U) +#define LL_PWR_GPIO_BIT_12 (0x00001000U) +#define LL_PWR_GPIO_BIT_13 (0x00002000U) +#define LL_PWR_GPIO_BIT_14 (0x00004000U) +#define LL_PWR_GPIO_BIT_15 (0x00008000U) /** * @} */ @@ -303,16 +301,6 @@ __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); } -/** - * @brief Check if the regulator is in low-power mode - * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); -} - /** * @brief Switch from run main mode to run low-power mode. * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode @@ -333,8 +321,19 @@ __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) LL_PWR_DisableLowPowerRunMode(); } +/** + * @brief Check if the regulator is in low-power mode + * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); +} + /** * @brief Set the main internal regulator output voltage + * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices. * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling * @param VoltageScaling This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 @@ -358,6 +357,38 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); } +#if defined(PWR_CR5_R1MODE) +/** + * @brief Enable main regulator voltage range 1 boost mode + * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) +{ + CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); +} + +/** + * @brief Disable main regulator voltage range 1 boost mode + * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) +{ + SET_BIT(PWR->CR5, PWR_CR5_R1MODE); +} + +/** + * @brief Check if the main regulator voltage range 1 boost mode is enabled + * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) +{ + return (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == RESET); +} +#endif /* PWR_CR5_R1MODE */ + /** * @brief Enable access to the backup domain * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess @@ -419,6 +450,70 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); } +#if defined(PWR_CR1_RRSTP) +/** + * @brief Enable SRAM3 content retention in Stop mode + * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_RRSTP); +} + +/** + * @brief Disable SRAM3 content retention in Stop mode + * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); +} + +/** + * @brief Check if SRAM3 content retention in Stop mode is enabled + * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)); +} +#endif /* PWR_CR1_RRSTP */ + +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Disable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Check if pull-down activation on DSI pins is enabled + * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) +{ + return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); +} +#endif /* PWR_CR3_DSIPDEN */ + #if defined(PWR_CR2_PVME1) /** * @brief Enable VDDUSB supply @@ -661,7 +756,7 @@ __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) } /** - * @brief Check if pull-up and pull-down configuration is enabled + * @brief Check if pull-up and pull-down configuration is enabled * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg * @retval State of bit (1 or 0). */ @@ -670,6 +765,38 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); } +#if defined(PWR_CR3_DSIPDEN) +/** + * @brief Enable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableDSIPullDown(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Disable pull-down activation on DSI pins + * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); +} + +/** + * @brief Check if pull-down activation on DSI pins is enabled + * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) +{ + return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); +} +#endif /* PWR_CR3_DSIPDEN */ + /** * @brief Enable SRAM2 content retention in Standby mode * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention @@ -691,7 +818,7 @@ __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) } /** - * @brief Check if SRAM2 content retention in Standby mode is enabled + * @brief Check if SRAM2 content retention in Standby mode is enabled * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention * @retval State of bit (1 or 0). */ @@ -1374,7 +1501,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) /** * @brief Indicate whether the regulator is ready in main mode or is in low-power mode - * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. + * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF * @retval State of bit (1 or 0). */ @@ -1407,14 +1534,14 @@ ErrorStatus LL_PWR_DeInit(void); */ #endif /* USE_FULL_LL_DRIVER */ -/** Legacy definitions for compatibility purpose -@cond 0 -*/ +/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name + * @{ + */ /* Old functions name kept for legacy purpose, to be replaced by the */ /* current functions name. */ #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS /** -@endcond + * @} */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c index 5d750e968c..d3c5a0f053 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rcc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RCC LL module driver. ****************************************************************************** * @attention @@ -60,7 +58,7 @@ /** @addtogroup RCC_LL_Private_Macros * @{ */ -#if defined(RCC_CCIPR_USART3SEL) +#if defined(RCC_CCIPR_USART3SEL) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) @@ -80,19 +78,24 @@ #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) -#if defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL) +#if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) +#elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) -#elif !defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL) +#elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) #else #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) -#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL */ +#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */ #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) @@ -103,8 +106,13 @@ #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) #endif /* RCC_CCIPR_SAI2SEL */ +#if defined(RCC_CCIPR2_SDMMCSEL) +#define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE)) +#endif /* RCC_CCIPR2_SDMMCSEL */ + #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) + #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) #if defined(USB_OTG_FS) || defined(USB) @@ -117,10 +125,24 @@ #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE)) #endif /* SWPMI1 */ -#if defined(DFSDM1_Channel0) +#if defined(DFSDM1_Channel0) #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)) +#endif /* RCC_CCIPR2_DFSDM1SEL */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) +#endif /* DSI */ + +#if defined(LTDC) +#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) +#endif /* LTDC */ + +#if defined(OCTOSPI1) +#define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE)) +#endif /* OCTOSPI */ /** * @} @@ -142,7 +164,14 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); #if defined(RCC_PLLSAI2_SUPPORT) uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void); +#if defined(LTDC) +uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void); +#else uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void); +#endif /* LTDC */ +#if defined(DSI) +uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void); +#endif /* DSI */ #endif /*RCC_PLLSAI2_SUPPORT*/ /** * @} @@ -162,7 +191,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void); * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source - * - HSE, HSI, PLL and PLLSAIxSource OFF + * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled @@ -183,11 +212,11 @@ ErrorStatus LL_RCC_DeInit(void) /* Insure MSIRDY bit is set before writing default MSIRANGE value */ while (LL_RCC_MSI_IsReady() == 0U) { - __NOP(); } /* Set MSIRANGE default value */ LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6); + /* Set MSITRIM bits to the reset value*/ LL_RCC_MSI_SetCalibTrimming(0); @@ -199,7 +228,7 @@ ErrorStatus LL_RCC_DeInit(void) vl_mask = 0xFFFFFFFFU; - /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */ + /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */ CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON)); @@ -214,6 +243,18 @@ ErrorStatus LL_RCC_DeInit(void) /* Write new mask in CR register */ LL_RCC_WriteReg(CR, vl_mask); +#if defined(RCC_PLLSAI2_SUPPORT) + /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + { + } +#else + /* Wait for PLLRDY, PLLSAI1RDY bits to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) + { + } +#endif + /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); @@ -231,6 +272,21 @@ ErrorStatus LL_RCC_DeInit(void) /* Disable all interrupts */ LL_RCC_WriteReg(CIER, 0x00000000U); + /* Clear all interrupt flags */ + vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ + RCC_CICR_PLLSAI1RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC; +#if defined(RCC_HSI48_SUPPORT) + vl_mask |= RCC_CICR_HSI48RDYC; +#endif +#if defined(RCC_PLLSAI2_SUPPORT) + vl_mask |= RCC_CICR_PLLSAI2RDYC; +#endif + + LL_RCC_WriteReg(CICR, vl_mask); + + /* Clear reset flags */ + LL_RCC_ClearResetFlags(); + return SUCCESS; } @@ -604,6 +660,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) return i2c_frequency; } + /** * @brief Return LPUARTx clock frequency * @param LPUARTxSource This parameter can be one of the following values: @@ -829,6 +886,45 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) return sai_frequency; } +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Return SDMMCx kernel clock frequency + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE + * @retval SDMMC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource) +{ + uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource)); + + /* SDMMC1CLK kernel clock frequency */ + switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource)) + { + case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */ + sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE); + break; + + case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */ + if (LL_RCC_PLL_IsReady()) + { + sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI(); + } + break; + + default: + sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return sdmmc_frequency; +} +#endif + /** * @brief Return SDMMCx clock frequency * @param SDMMCxSource This parameter can be one of the following values: @@ -847,12 +943,14 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) /* SDMMC1CLK clock frequency */ switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) { +#if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1) case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */ if (LL_RCC_PLLSAI1_IsReady()) { sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); } break; +#endif case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */ if (LL_RCC_PLL_IsReady()) @@ -861,6 +959,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) } break; +#if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI) case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */ if (LL_RCC_MSI_IsReady()) { @@ -870,6 +969,7 @@ uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) LL_RCC_MSI_GetRangeAfterStandby())); } break; +#endif #if defined(RCC_HSI48_SUPPORT) case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */ @@ -1039,14 +1139,14 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) } break; -#if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2) case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */ if (LL_RCC_PLLSAI2_IsReady()) { adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC(); } break; -#endif /* RCC_PLLSAI2_SUPPORT */ +#endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */ case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ adc_frequency = RCC_GetSystemClockFreq(); @@ -1124,8 +1224,161 @@ uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) return dfsdm_frequency; } + +#if defined(RCC_CCIPR2_DFSDM1SEL) +/** + * @brief Return DFSDMx Audio clock frequency + * @param DFSDMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval DFSDM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) +{ + uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource)); + + /* DFSDM1CLK clock frequency */ + switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) + { + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */ + dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE); + break; + + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */ + if (LL_RCC_MSI_IsReady()) + { + dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + } + break; + + case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */ + default: + if (LL_RCC_HSI_IsReady()) + { + dfsdm_frequency = HSI_VALUE; + } + break; + } + + return dfsdm_frequency; +} +#endif /* RCC_CCIPR2_DFSDM1SEL */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** + * @brief Return DSI clock frequency + * @param DSIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval DSI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) +{ + uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource)); + + /* DSICLK clock frequency */ + switch (LL_RCC_GetDSIClockSource(DSIxSource)) + { + case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */ + if (LL_RCC_PLLSAI2_IsReady()) + { + dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI(); + } + break; + + case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */ + default: + dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return dsi_frequency; +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Return LTDC clock frequency + * @param LTDCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval LTDC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready + */ +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) +{ + uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); + + if (LL_RCC_PLLSAI2_IsReady()) + { + ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC(); + } + + return ltdc_frequency; +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Return OCTOSPI clock frequency + * @param OCTOSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE + * @retval OCTOSPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready + */ +uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) +{ + uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource)); + + /* OCTOSPI clock frequency */ + switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource)) + { + case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */ + octospi_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */ + if (LL_RCC_MSI_IsReady()) + { + octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + } + break; + + case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */ + if (LL_RCC_PLL_IsReady()) + { + octospi_frequency = RCC_PLL_GetFreqDomain_48M(); + } + break; + + default: + octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + break; + } + + return octospi_frequency; +} +#endif /* OCTOSPI1 */ + /** * @} */ @@ -1333,6 +1586,48 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); } +#if defined(DSI) +/** + * @brief Return PLL clock frequency used for DSI clock + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ + /* DSICLK = PLLSAI2_VCO / PLLSAI2R */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + } + + return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), + LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR()); +} +#endif /* DSI */ /** * @brief Return PLLSAI1 clock frequency used for SAI domain @@ -1342,7 +1637,11 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ +#else /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ +#endif /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1382,7 +1681,11 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ +#else /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ +#endif /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1422,7 +1725,11 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ +#else /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ +#endif /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1463,7 +1770,11 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ +#else /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */ +#endif /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */ pllsource = LL_RCC_PLL_GetMainSource(); @@ -1491,10 +1802,59 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) LL_RCC_MSI_GetRangeAfterStandby())); break; } +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) + return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), + LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP()); +#else return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP()); +#endif } +#if defined(LTDC) +/** + * @brief Return PLLSAI2 clock frequency used for LTDC domain + * @retval PLLSAI2 clock frequency (in Hz) + */ +uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ + /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + (LL_RCC_MSI_IsEnabledRangeSelect() ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + break; + } + + return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), + LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR()); +} + +#else + /** * @brief Return PLLSAI2 clock frequency used for ADC domain * @retval PLLSAI2 clock frequency (in Hz) @@ -1534,8 +1894,9 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void) return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR()); } -#endif /*RCC_PLLSAI2_SUPPORT*/ +#endif /* LTDC */ +#endif /*RCC_PLLSAI2_SUPPORT*/ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h index e0d119a20a..e1d4b8667b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rcc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RCC LL module. ****************************************************************************** * @attention @@ -62,7 +60,9 @@ extern "C" { * @{ */ -static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16}; +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ /** * @} @@ -90,6 +90,7 @@ static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; * @} */ #endif /*USE_FULL_LL_DRIVER*/ + /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Exported_Types RCC Exported Types @@ -127,7 +128,7 @@ typedef struct /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to + * @note These values could be modified in the user environment according to * HW set-up. * @{ */ @@ -146,8 +147,8 @@ typedef struct #if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ - #if defined(RCC_HSI48_SUPPORT) + #if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #endif /* HSI48_VALUE */ @@ -488,24 +489,50 @@ typedef struct /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection * @{ */ +#if defined(RCC_CCIPR2_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ +#else #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */ #define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */ +#endif /* RCC_CCIPR2_SAI1SEL */ -#if defined(RCC_CCIPR_SAI2SEL) +#if defined(RCC_CCIPR2_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ +#elif defined(RCC_CCIPR_SAI2SEL) #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */ #if defined(RCC_PLLSAI2_SUPPORT) #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */ #define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */ -#endif /* RCC_CCIPR_SAI2SEL *//** +#endif /* RCC_CCIPR2_SAI2SEL */ +/** * @} */ +#if defined(RCC_CCIPR2_SDMMCSEL) +/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection + * @{ + */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */ +/** + * @} + */ +#endif /* RCC_CCIPR2_SDMMCSEL */ + /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection * @{ */ @@ -559,7 +586,7 @@ typedef struct */ #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */ #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */ -#if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC) #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */ #endif /* RCC_PLLSAI2_SUPPORT */ #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */ @@ -579,16 +606,69 @@ typedef struct #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection * @{ */ +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ +#else #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ +#endif /* RCC_CCIPR2_DFSDM1SEL */ /** * @} */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ +#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */ +#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */ +#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */ +/** + * @} + */ +#endif /* OCTOSPI1 */ + /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source * @{ */ @@ -651,14 +731,30 @@ typedef struct /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source * @{ */ +#if defined(RCC_CCIPR2_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ +#else #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */ -#if defined(RCC_CCIPR_SAI2SEL) +#endif /* RCC_CCIPR2_SAI1SEL */ +#if defined(RCC_CCIPR2_SAI2SEL) +#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ +#elif defined(RCC_CCIPR_SAI2SEL) #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */ -#endif /* RCC_CCIPR_SAI2SEL */ +#endif /* RCC_CCIPR2_SAI2SEL */ /** * @} */ +#if defined(RCC_CCIPR2_SDMMCSEL) +/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source + * @{ + */ +#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR2_SDMMCSEL */ + /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source * @{ */ @@ -704,15 +800,60 @@ typedef struct #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CCIPR2_ADFSDM1SEL */ /** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source * @{ */ +#if defined(RCC_CCIPR2_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */ +#else #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */ +#endif /* RCC_CCIPR2_DFSDM1SEL */ /** * @} */ #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source + * @{ + */ +#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */ +/** + * @} + */ +#endif /* OCTOSPI1 */ + + /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ @@ -724,6 +865,7 @@ typedef struct * @} */ + /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source * @{ */ @@ -735,17 +877,27 @@ typedef struct * @} */ -/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor +/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor * @{ */ -#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 1 */ -#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 2 */ -#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 3 */ -#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 4 */ -#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 5 */ -#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 6 */ -#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 7 */ -#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL, PLLSAI1 and PLLSAI2 division factor by 8 */ +#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */ +#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */ +#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */ +#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */ +#if defined(RCC_PLLM_DIV_1_16_SUPPORT) +#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */ +#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */ +#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */ +#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */ +#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */ +#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */ +#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */ +#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */ +#endif /* RCC_PLLM_DIV_1_16_SUPPORT */ /** * @} */ @@ -766,35 +918,35 @@ typedef struct */ #if defined(RCC_PLLP_DIV_2_31_SUPPORT) #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */ -#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */ #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */ -#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 5 */ -#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 6 */ -#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */ #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */ -#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 9 */ -#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 10 */ -#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3)) /*!< Main PLL division factor for PLLP output by 11 */ -#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 12 */ -#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 13 */ -#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 14 */ -#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */ #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */ -#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 17 */ -#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 18 */ -#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_4)) /*!< Main PLL division factor for PLLP output by 19 */ -#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 20 */ -#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 21 */ -#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 22 */ -#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 23 */ -#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 24 */ -#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 25 */ -#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 26 */ -#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 27 */ -#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 28 */ -#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 29 */ -#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 30 */ -#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_0|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 31 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */ +#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */ #else #define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */ #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */ @@ -814,6 +966,31 @@ typedef struct * @} */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M) + * @{ + */ +#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */ +#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */ +#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */ +#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */ +#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */ +#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */ +#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */ +#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */ +#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */ +#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */ +#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */ +#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */ +#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */ +#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */ +#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */ +#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */ +/** + * @} + */ +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) * @{ */ @@ -830,35 +1007,35 @@ typedef struct */ #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */ -#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ +#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */ -#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ -#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ -#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ +#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ +#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ +#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */ -#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ -#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ -#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ -#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ -#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ -#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ -#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ +#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ +#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ +#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ +#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ +#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ +#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ +#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */ -#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ -#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ -#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ -#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ -#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ -#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ -#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ -#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ -#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ -#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ -#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ -#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ -#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ -#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ -#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_0|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ +#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ +#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ +#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ +#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ +#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ +#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ +#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ +#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ +#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ +#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ +#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ +#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ +#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ +#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ +#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ #else #define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ @@ -879,11 +1056,82 @@ typedef struct */ #if defined(RCC_PLLSAI2_SUPPORT) +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M) + * @{ + */ +#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */ +#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */ +#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */ +#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */ +#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */ +#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */ +#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */ +#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */ +#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */ +#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */ +#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */ +#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */ +#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */ +#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */ +#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */ +#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */ +/** + * @} + */ +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q) + * @{ + */ +#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */ +#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */ +#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */ +#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ + /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P) * @{ */ +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */ +#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */ +#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */ +#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */ +#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */ +#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ +#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */ +#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */ +#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */ +#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */ +#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */ +#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */ +#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */ +#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */ +#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */ +#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ +#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */ +#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */ +#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */ +#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */ +#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */ +#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */ +#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */ +#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */ +#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */ +#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */ +#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */ +#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */ +#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */ +#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ +#else #define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ /** * @} */ @@ -898,6 +1146,19 @@ typedef struct /** * @} */ + +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR) + * @{ + */ +#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */ +#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */ +#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */ +#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */ +/** + * @} + */ +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ #endif /* RCC_PLLSAI2_SUPPORT */ /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection @@ -974,6 +1235,16 @@ typedef struct * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param __PLLN__ Between 8 and 86 * @param __PLLR__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 @@ -1000,6 +1271,16 @@ typedef struct * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param __PLLN__ Between 8 and 86 * @param __PLLP__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 @@ -1035,7 +1316,7 @@ typedef struct * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ - ((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos)) + ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos)) #else /** @@ -1062,6 +1343,7 @@ typedef struct (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ + /** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1076,6 +1358,16 @@ typedef struct * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param __PLLN__ Between 8 and 86 * @param __PLLQ__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 @@ -1087,7 +1379,68 @@ typedef struct #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + +#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1138,7 +1491,8 @@ typedef struct */ #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ - ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos)) + ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + #else /** * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain @@ -1163,8 +1517,45 @@ typedef struct #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U)) + #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1Q__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) + +#else /** * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1191,6 +1582,44 @@ typedef struct ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), + * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI1M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param __PLLSAI1N__ Between 8 and 86 + * @param __PLLSAI1R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval PLLSAI1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \ + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) + +#else /** * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1217,6 +1646,123 @@ typedef struct ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ + ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2P__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + +#else /** * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1240,6 +1786,49 @@ typedef struct #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \ (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U)) + +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#if defined(LTDC) +/** + * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @param __PLLSAI2DIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + * @retval PLLSAI2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \ + (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos]))) +#else /** * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), @@ -1266,6 +1855,45 @@ typedef struct ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U)) +#endif /* LTDC */ + +#if defined(DSI) +/** + * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI + * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), + * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) + * @param __PLLSAI2M__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param __PLLSAI2N__ Between 8 and 86 + * @param __PLLSAI2Q__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \ + ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U)) +#endif /* DSI */ + + /** * @brief Helper macro to calculate the HCLK frequency @@ -1295,7 +1923,7 @@ typedef struct * @arg @ref LL_RCC_APB1_DIV_16 * @retval PCLK1 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) /** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) @@ -1308,7 +1936,7 @@ typedef struct * @arg @ref LL_RCC_APB2_DIV_16 * @retval PCLK2 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) /** * @brief Helper macro to calculate the MSI frequency (in Hz) @@ -1452,6 +2080,16 @@ __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); } +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)); +} + /** * @brief Enable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Enable @@ -1579,7 +2217,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) /** * @brief Get HSI48 Calibration value * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF */ __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) { @@ -2284,7 +2922,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) */ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U))); } @@ -2309,7 +2947,11 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) /** * @brief Configure SAIx clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource + @else * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource + @endif * @param SAIxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) @@ -2325,9 +2967,30 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) */ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) { +#if defined(RCC_CCIPR2_SAI1SEL) + MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); +#else MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +#endif /* RCC_CCIPR2_SAI1SEL */ } +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Configure SDMMC1 kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); +} +#endif /* RCC_CCIPR2_SDMMCSEL */ + /** * @brief Configure SDMMC1 clock source * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource @@ -2336,7 +2999,7 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) * * (*) value not defined in all devices. * @retval None @@ -2417,9 +3080,29 @@ __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** + * @brief Configure DFSDM Audio clock source + * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source); +} +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + /** * @brief Configure DFSDM Kernel clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource + @else * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource + @endif * @param DFSDMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK @@ -2427,10 +3110,62 @@ __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) */ __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource) { +#if defined(RCC_CCIPR2_DFSDM1SEL) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource); +#else MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource); +#endif /* RCC_CCIPR2_DFSDM1SEL */ } #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** + * @brief Configure DSI clock source + * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure LTDC Clock Source + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source); +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Configure OCTOSPI clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source); +} +#endif /* OCTOSPI1 */ + /** * @brief Get USARTx clock source * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource @@ -2528,8 +3263,8 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) */ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) { - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); - return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x0000FF0000U) >> 16U)) >> ((I2Cx & 0x0000FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); + return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); } /** @@ -2555,7 +3290,11 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) /** * @brief Get SAIx clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource + @else * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource + @endif * @param SAIx This parameter can be one of the following values: * @arg @ref LL_RCC_SAI1_CLKSOURCE * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) @@ -2575,9 +3314,31 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) */ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) { +#if defined(RCC_CCIPR2_SAI1SEL) + return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); +#else return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx); +#endif /* RCC_CCIPR2_SAI1SEL */ } +#if defined(RCC_CCIPR2_SDMMCSEL) +/** + * @brief Get SDMMCx kernel clock source + * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) + * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); +} +#endif /* RCC_CCIPR2_SDMMCSEL */ + /** * @brief Get SDMMCx clock source * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource @@ -2586,9 +3347,9 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) * * (*) value not defined in all devices. */ @@ -2672,9 +3433,30 @@ __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) +#if defined(RCC_CCIPR2_ADFSDM1SEL) +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); +} +#endif /* RCC_CCIPR2_ADFSDM1SEL */ + /** * @brief Get DFSDMx Kernel clock source + @if STM32L4S9xx + * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource + @else * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource + @endif * @param DFSDMx This parameter can be one of the following values: * @arg @ref LL_RCC_DFSDM1_CLKSOURCE * @retval Returned value can be one of the following values: @@ -2683,10 +3465,64 @@ __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) */ __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) { +#if defined(RCC_CCIPR2_DFSDM1SEL) + return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); +#else return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx)); +#endif /* RCC_CCIPR2_DFSDM1SEL */ } #endif /* DFSDM1_Channel0 */ +#if defined(DSI) +/** + * @brief Get DSI Clock Source + * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Get LTDC Clock Source + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource + * @param LTDCx This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); +} +#endif /* LTDC */ + +#if defined(OCTOSPI1) +/** + * @brief Get OCTOSPI clock source + * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource + * @param OCTOSPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI + * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); +} +#endif /* OCTOSPI1 */ /** * @} */ @@ -2820,8 +3656,8 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) /** * @brief Configure PLL used for SYSCLK Domain * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLR can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLR can be written only when PLL is disabled. * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n @@ -2840,6 +3676,16 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param PLLN Between 8 and 86 * @param PLLR This parameter can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 @@ -2858,8 +3704,8 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, /** * @brief Configure PLL used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLP can be written only when PLL is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n @@ -2879,6 +3725,16 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param PLLN Between 8 and 86 * @param PLLP This parameter can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 @@ -2917,8 +3773,8 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, /** * @brief Configure PLL used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLP can be written only when PLL is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n @@ -2959,8 +3815,8 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, /** * @brief Configure PLL used for 48Mhz domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLQ can be written only when PLL is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLQ can be written only when PLL is disabled. * @note This can be selected for USB, RNG, SDMMC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n @@ -2980,6 +3836,16 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. * @param PLLN Between 8 and 86 * @param PLLQ This parameter can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 @@ -2994,6 +3860,35 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); } +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + /** * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN @@ -3007,7 +3902,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) #if defined(RCC_PLLP_DIV_2_31_SUPPORT) /** * @brief Get Main PLL division factor for PLLP - * @note used for PLLSAI3CLK (SAI1 and SAI2 clock) + * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_2 @@ -3048,7 +3943,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) #else /** * @brief Get Main PLL division factor for PLLP - * @note used for PLLSAI3CLK (SAI1 and SAI2 clock) + * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLP_DIV_7 @@ -3062,7 +3957,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) /** * @brief Get Main PLL division factor for PLLQ - * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) + * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLQ_DIV_2 @@ -3077,7 +3972,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) /** * @brief Get Main PLL division factor for PLLR - * @note used for PLLCLK (system clock) + * @note Used for PLLCLK (system clock) * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLR_DIV_2 @@ -3090,20 +3985,6 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); } -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_NONE - * @arg @ref LL_RCC_PLLSOURCE_MSI - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - /** * @brief Get Division factor for the main PLL and other PLL * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider @@ -3116,6 +3997,16 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 (*) + * @arg @ref LL_RCC_PLLM_DIV_10 (*) + * @arg @ref LL_RCC_PLLM_DIV_11 (*) + * @arg @ref LL_RCC_PLLM_DIV_12 (*) + * @arg @ref LL_RCC_PLLM_DIV_13 (*) + * @arg @ref LL_RCC_PLLM_DIV_14 (*) + * @arg @ref LL_RCC_PLLM_DIV_15 (*) + * @arg @ref LL_RCC_PLLM_DIV_16 (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) { @@ -3232,11 +4123,58 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)); } +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Configure PLLSAI1 used for 48Mhz domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. + * @note This can be selected for USB, RNG, SDMMC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n + * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, + PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); +} +#else /** * @brief Configure PLLSAI1 used for 48Mhz domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. * @note This can be selected for USB, RNG, SDMMC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n @@ -3269,13 +4207,86 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); } +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI1 used for SAI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n + * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1P_DIV_2 + * @arg @ref LL_RCC_PLLSAI1P_DIV_3 + * @arg @ref LL_RCC_PLLSAI1P_DIV_4 + * @arg @ref LL_RCC_PLLSAI1P_DIV_5 + * @arg @ref LL_RCC_PLLSAI1P_DIV_6 + * @arg @ref LL_RCC_PLLSAI1P_DIV_7 + * @arg @ref LL_RCC_PLLSAI1P_DIV_8 + * @arg @ref LL_RCC_PLLSAI1P_DIV_9 + * @arg @ref LL_RCC_PLLSAI1P_DIV_10 + * @arg @ref LL_RCC_PLLSAI1P_DIV_11 + * @arg @ref LL_RCC_PLLSAI1P_DIV_12 + * @arg @ref LL_RCC_PLLSAI1P_DIV_13 + * @arg @ref LL_RCC_PLLSAI1P_DIV_14 + * @arg @ref LL_RCC_PLLSAI1P_DIV_15 + * @arg @ref LL_RCC_PLLSAI1P_DIV_16 + * @arg @ref LL_RCC_PLLSAI1P_DIV_17 + * @arg @ref LL_RCC_PLLSAI1P_DIV_18 + * @arg @ref LL_RCC_PLLSAI1P_DIV_19 + * @arg @ref LL_RCC_PLLSAI1P_DIV_20 + * @arg @ref LL_RCC_PLLSAI1P_DIV_21 + * @arg @ref LL_RCC_PLLSAI1P_DIV_22 + * @arg @ref LL_RCC_PLLSAI1P_DIV_23 + * @arg @ref LL_RCC_PLLSAI1P_DIV_24 + * @arg @ref LL_RCC_PLLSAI1P_DIV_25 + * @arg @ref LL_RCC_PLLSAI1P_DIV_26 + * @arg @ref LL_RCC_PLLSAI1P_DIV_27 + * @arg @ref LL_RCC_PLLSAI1P_DIV_28 + * @arg @ref LL_RCC_PLLSAI1P_DIV_29 + * @arg @ref LL_RCC_PLLSAI1P_DIV_30 + * @arg @ref LL_RCC_PLLSAI1P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); +} +#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Configure PLLSAI1 used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n @@ -3329,12 +4340,18 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P * @arg @ref LL_RCC_PLLSAI1P_DIV_31 * @retval None */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, + PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); +} #else /** * @brief Configure PLLSAI1 used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLP can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled. * @note This can be selected for SAI1 or SAI2 (*) * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n @@ -3360,23 +4377,65 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t P * @arg @ref LL_RCC_PLLSAI1P_DIV_17 * @retval None */ -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); -#else MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ } +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */ +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Configure PLLSAI1 used for ADC domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled. + * @note This can be selected for ADC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n + * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1R_DIV_2 + * @arg @ref LL_RCC_PLLSAI1R_DIV_4 + * @arg @ref LL_RCC_PLLSAI1R_DIV_6 + * @arg @ref LL_RCC_PLLSAI1R_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, + PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); +} +#else /** * @brief Configure PLLSAI1 used for ADC domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI1 and PLLSAI2 (*) are disabled - * @note PLLN/PLLR can be written only when PLLSAI1 is disabled + * PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLN/PLLR can be written only when PLLSAI1 is disabled. * @note This can be selected for ADC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n @@ -3409,6 +4468,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); } +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ /** * @brief Get SAI1PLL multiplication factor for VCO @@ -3423,7 +4483,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) /** * @brief Get SAI1PLL division factor for PLLSAI1P - * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). + * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1P_DIV_2 @@ -3457,28 +4517,28 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) * @arg @ref LL_RCC_PLLSAI1P_DIV_30 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); +} #else /** * @brief Get SAI1PLL division factor for PLLSAI1P - * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). + * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1P_DIV_7 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 */ -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) { -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); -#else return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P)); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ } +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ /** * @brief Get SAI1PLL division factor for PLLSAI1Q - * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) + * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 @@ -3493,7 +4553,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void) /** * @brief Get PLLSAI1 division factor for PLLSAIR - * @note used for PLLADC1CLK (ADC clock) + * @note Used for PLLADC1CLK (ADC clock) * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI1R_DIV_2 @@ -3506,6 +4566,34 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void) return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R)); } +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) +/** + * @brief Get Division factor for the PLLSAI1 + * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI1M_DIV_1 + * @arg @ref LL_RCC_PLLSAI1M_DIV_2 + * @arg @ref LL_RCC_PLLSAI1M_DIV_3 + * @arg @ref LL_RCC_PLLSAI1M_DIV_4 + * @arg @ref LL_RCC_PLLSAI1M_DIV_5 + * @arg @ref LL_RCC_PLLSAI1M_DIV_6 + * @arg @ref LL_RCC_PLLSAI1M_DIV_7 + * @arg @ref LL_RCC_PLLSAI1M_DIV_8 + * @arg @ref LL_RCC_PLLSAI1M_DIV_9 + * @arg @ref LL_RCC_PLLSAI1M_DIV_10 + * @arg @ref LL_RCC_PLLSAI1M_DIV_11 + * @arg @ref LL_RCC_PLLSAI1M_DIV_12 + * @arg @ref LL_RCC_PLLSAI1M_DIV_13 + * @arg @ref LL_RCC_PLLSAI1M_DIV_14 + * @arg @ref LL_RCC_PLLSAI1M_DIV_15 + * @arg @ref LL_RCC_PLLSAI1M_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M)); +} +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + /** * @brief Enable PLLSAI1 output mapped on SAI domain clock * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI @@ -3611,11 +4699,148 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)); } +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) +/** + * @brief Configure PLLSAI2 used for SAI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, + PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); +} +#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) /** * @brief Configure PLLSAI2 used for SAI domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI2 and PLLSAI2 are disabled - * @note PLLN/PLLP can be written only when PLLSAI2 is disabled + * PLLSAI1 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. + * @note This can be selected for SAI1 or SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n + * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); +} +#else +/** + * @brief Configure PLLSAI2 used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLSAI2 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled. * @note This can be selected for SAI1 or SAI2 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n @@ -3646,12 +4871,113 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); } +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */ +#if defined(DSI) +/** + * @brief Configure PLLSAI2 used for DSI domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled. + * @note This can be selected for DSI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n + * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLQ | PLLM); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Configure PLLSAI2 used for LTDC domain clock + * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. + * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. + * @note This can be selected for LTDC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n + * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + * @param PLLN Between 8 and 86 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2R_DIV_2 + * @arg @ref LL_RCC_PLLSAI2R_DIV_4 + * @arg @ref LL_RCC_PLLSAI2R_DIV_6 + * @arg @ref LL_RCC_PLLSAI2R_DIV_8 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR | PLLM); + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR); +} +#else /** * @brief Configure PLLSAI2 used for ADC domain clock * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLSAI2 and PLLSAI2 are disabled - * @note PLLN/PLLR can be written only when PLLSAI2 is disabled + * PLLSAI2 and PLLSAI2 are disabled. + * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. * @note This can be selected for ADC * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n @@ -3684,6 +5010,7 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t P MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR); } +#endif /* LTDC */ /** * @brief Get SAI2PLL multiplication factor for VCO @@ -3695,9 +5022,51 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void) return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos); } +#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) /** * @brief Get SAI2PLL division factor for PLLSAI2P - * @note used for PLLSAI2CLK (SAI1 or SAI2 clock). + * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). + * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2P_DIV_2 + * @arg @ref LL_RCC_PLLSAI2P_DIV_3 + * @arg @ref LL_RCC_PLLSAI2P_DIV_4 + * @arg @ref LL_RCC_PLLSAI2P_DIV_5 + * @arg @ref LL_RCC_PLLSAI2P_DIV_6 + * @arg @ref LL_RCC_PLLSAI2P_DIV_7 + * @arg @ref LL_RCC_PLLSAI2P_DIV_8 + * @arg @ref LL_RCC_PLLSAI2P_DIV_9 + * @arg @ref LL_RCC_PLLSAI2P_DIV_10 + * @arg @ref LL_RCC_PLLSAI2P_DIV_11 + * @arg @ref LL_RCC_PLLSAI2P_DIV_12 + * @arg @ref LL_RCC_PLLSAI2P_DIV_13 + * @arg @ref LL_RCC_PLLSAI2P_DIV_14 + * @arg @ref LL_RCC_PLLSAI2P_DIV_15 + * @arg @ref LL_RCC_PLLSAI2P_DIV_16 + * @arg @ref LL_RCC_PLLSAI2P_DIV_17 + * @arg @ref LL_RCC_PLLSAI2P_DIV_18 + * @arg @ref LL_RCC_PLLSAI2P_DIV_19 + * @arg @ref LL_RCC_PLLSAI2P_DIV_20 + * @arg @ref LL_RCC_PLLSAI2P_DIV_21 + * @arg @ref LL_RCC_PLLSAI2P_DIV_22 + * @arg @ref LL_RCC_PLLSAI2P_DIV_23 + * @arg @ref LL_RCC_PLLSAI2P_DIV_24 + * @arg @ref LL_RCC_PLLSAI2P_DIV_25 + * @arg @ref LL_RCC_PLLSAI2P_DIV_26 + * @arg @ref LL_RCC_PLLSAI2P_DIV_27 + * @arg @ref LL_RCC_PLLSAI2P_DIV_28 + * @arg @ref LL_RCC_PLLSAI2P_DIV_29 + * @arg @ref LL_RCC_PLLSAI2P_DIV_30 + * @arg @ref LL_RCC_PLLSAI2P_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV)); +} +#else +/** + * @brief Get SAI2PLL division factor for PLLSAI2P + * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI2P_DIV_7 @@ -3707,10 +5076,28 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) { return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P)); } +#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ + +#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) +/** + * @brief Get division factor for PLLSAI2Q + * @note Used for PLLDSICLK (DSI clock) + * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 + * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q)); +} +#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ /** * @brief Get SAI2PLL division factor for PLLSAI2R - * @note used for PLLADC2CLK (ADC clock) + * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSAI2R_DIV_2 @@ -3723,6 +5110,51 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void) return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)); } +#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) +/** + * @brief Get Division factor for the PLLSAI2 + * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2M_DIV_1 + * @arg @ref LL_RCC_PLLSAI2M_DIV_2 + * @arg @ref LL_RCC_PLLSAI2M_DIV_3 + * @arg @ref LL_RCC_PLLSAI2M_DIV_4 + * @arg @ref LL_RCC_PLLSAI2M_DIV_5 + * @arg @ref LL_RCC_PLLSAI2M_DIV_6 + * @arg @ref LL_RCC_PLLSAI2M_DIV_7 + * @arg @ref LL_RCC_PLLSAI2M_DIV_8 + * @arg @ref LL_RCC_PLLSAI2M_DIV_9 + * @arg @ref LL_RCC_PLLSAI2M_DIV_10 + * @arg @ref LL_RCC_PLLSAI2M_DIV_11 + * @arg @ref LL_RCC_PLLSAI2M_DIV_12 + * @arg @ref LL_RCC_PLLSAI2M_DIV_13 + * @arg @ref LL_RCC_PLLSAI2M_DIV_14 + * @arg @ref LL_RCC_PLLSAI2M_DIV_15 + * @arg @ref LL_RCC_PLLSAI2M_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M)); +} +#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ + +#if defined(RCC_CCIPR2_PLLSAI2DIVR) +/** + * @brief Get PLLSAI2 division factor for PLLSAI2DIVR + * @note Used for LTDC domain clock + * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)); +} +#endif /* RCC_CCIPR2_PLLSAI2DIVR */ + /** * @brief Enable PLLSAI2 output mapped on SAI domain clock * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI @@ -3745,6 +5177,53 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void) CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); } +#if defined(DSI) +/** + * @brief Enable PLLSAI2 output mapped on DSI domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); +} + +/** + * @brief Disable PLLSAI2 output mapped on DSI domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, Main PLLSAI2 should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); +} +#endif /* DSI */ + +#if defined(LTDC) +/** + * @brief Enable PLLSAI2 output mapped on LTDC domain clock + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void) +{ + SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} + +/** + * @brief Disable PLLSAI2 output mapped on LTDC domain clock + * @note In order to save power, when of the PLLSAI2 is + * not used, Main PLLSAI2 should be 0 + * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void) +{ + CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); +} +#else /** * @brief Enable PLLSAI2 output mapped on ADC domain clock * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC @@ -3766,12 +5245,15 @@ __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void) { CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); } +#endif /* LTDC */ /** * @} */ #endif /* RCC_PLLSAI2_SUPPORT */ + + /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management * @{ */ @@ -4439,6 +5921,9 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#if defined(RCC_CCIPR2_SDMMCSEL) +uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); +#endif uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); #if defined(USB_OTG_FS) || defined(USB) @@ -4450,7 +5935,19 @@ uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource); #endif /* SWPMI1 */ #if defined(DFSDM1_Channel0) uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +#if defined(RCC_CCIPR2_DFSDM1SEL) +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); +#endif /* RCC_CCIPR2_DFSDM1SEL */ #endif /* DFSDM1_Channel0 */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +#if defined(OCTOSPI1) +uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); +#endif /* OCTOSPI1 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c index e1c3b4acee..5ded9ba331 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rng.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RNG LL module driver. ****************************************************************************** * @attention @@ -60,6 +58,18 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/** @addtogroup RNG_LL_Private_Macros + * @{ + */ +#if defined(RNG_CR_CED) +#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ + ((__MODE__) == LL_RNG_CED_DISABLE)) +#endif /* defined(RNG_CR_CED) */ + +/** + * @} + */ + /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -92,6 +102,42 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) return (SUCCESS); } +#if defined(RNG_CR_CED) +/** + * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct. + * @param RNGx RNG Instance + * @param RNG_InitStruct: pointer to a LL_RNG_InitTypeDef structure + * that contains the configuration information for the specified RNG peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content + * - ERROR: not applicable + */ +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection)); + + /* Clock Error Detection configuration */ + MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection); + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_RNG_InitTypeDef field to default value. + * @param RNG_InitStruct: pointer to a @ref LL_RNG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Set RNG_InitStruct fields to default values */ + RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE; + +} +#endif /* defined(RNG_CR_CED) */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h index 94325a4ac4..2c49eac9a1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rng.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RNG LL module. ****************************************************************************** * @attention @@ -62,11 +60,47 @@ extern "C" { /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures + * @{ + */ + + +#if defined(RNG_CR_CED) +/** + * @brief LL RNG Init Structure Definition + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< Clock error detection. + This parameter can be one value of @ref RNG_LL_CED. + + This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */ +}LL_RNG_InitTypeDef; +#endif /* defined(RNG_CR_CED) */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants * @{ */ + +#if defined(RNG_CR_CED) +/** @defgroup RNG_LL_CED Clock Error Detection + * @{ + */ +#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */ +#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +#endif /* defined(RNG_CR_CED) */ + /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_RNG_ReadReg function * @{ @@ -168,6 +202,42 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)); } +#if defined(RNG_CR_CED) +/** + * @brief Enable RNG Clock Error Detection + * @rmtoll CR CED LL_RNG_EnableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_CED); +} + +/** + * @brief Disable RNG Clock Error Detection + * @rmtoll CR CED LL_RNG_DisableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CED); +} + +/** + * @brief Check if RNG Clock Error Detection is enabled + * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) +{ + return (!(READ_BIT(RNGx->CR, RNG_CR_CED) == (RNG_CR_CED))); +} +#endif /* defined(RNG_CR_CED) */ + + /** * @} */ @@ -324,7 +394,10 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ - +#if defined(RNG_CR_CED) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); +#endif /* defined(RNG_CR_CED) */ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c index 6c359de270..1fff8e3f76 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rtc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief RTC LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h index a935f5ab0e..41ace5a83e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of RTC LL module. ****************************************************************************** * @attention @@ -63,8 +61,8 @@ extern "C" { * @{ */ /* Masks Definition */ -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU /* Write protection defines */ #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) @@ -223,8 +221,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ /** * @} */ @@ -614,8 +612,8 @@ typedef struct * @{ */ #define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ -#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */ -#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */ /** * @} */ @@ -1293,7 +1291,12 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); } /** @@ -1627,7 +1630,13 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx)); + register uint32_t temp = 0U; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c index d0434cdcc1..c245cca9cb 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -234,7 +232,9 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) /* Check the parameters */ assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); @@ -242,12 +242,20 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) /* Set SDMMC configuration parameters */ /* Write to SDMMC CLKCR */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ + Init.ClockPowerSave |\ + Init.BusWide |\ + Init.HardwareFlowControl |\ + Init.ClockDiv); +#else MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ Init.ClockBypass |\ Init.ClockPowerSave |\ Init.BusWide |\ Init.HardwareFlowControl |\ Init.ClockDiv); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } @@ -324,11 +332,32 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) { /* Set power state to ON */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + SDMMCx->POWER |= SDMMC_POWER_PWRCTRL; + +#else SDMMCx->POWER = SDMMC_POWER_PWRCTRL; + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Set SDMMC Power state to Power-Cycle. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx) +{ + /* Set power state to Power Cycle*/ + SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1; + + return HAL_OK; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @brief Set SDMMC Power state to OFF. * @param SDMMCx: Pointer to SDMMC register base @@ -337,7 +366,13 @@ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) { /* Set power state to OFF */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL); + +#else SDMMCx->POWER = (uint32_t)0x00000000; + +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ return HAL_OK; } @@ -894,7 +929,11 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate = SDMMC_ERROR_NONE; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + sdmmc_cmdinit.Argument = Argument; +#else sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -1125,6 +1164,32 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) return errorstate; } +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param None + * @retval HAL status + */ +uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = 0x00000000; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT); + + return errorstate; +} +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** * @} @@ -1156,7 +1221,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); return SDMMC_ERROR_NONE; } @@ -1207,7 +1272,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ } /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1330,7 +1395,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { /* No error flag set */ /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1363,10 +1428,9 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else - { /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1417,7 +1481,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ } /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1465,11 +1529,19 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { /* Card is SD V2.0 compliant */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { /* Card is SD V2.0 compliant */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h index 8b1b0183c6..41996af8e0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_sdmmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of low layer SDMMC HAL module. ****************************************************************************** * @attention @@ -69,9 +67,11 @@ typedef struct uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or disabled when the bus is idle. @@ -86,6 +86,11 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Transceiver */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + }SDMMC_InitTypeDef; @@ -200,7 +205,11 @@ typedef struct and asks the card whether card supports voltage. */ #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ +#else #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ +#endif #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ @@ -307,6 +316,11 @@ typedef struct #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) +#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) +#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) @@ -334,8 +348,8 @@ typedef struct */ #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) -#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ -#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ +#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ +#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ /** @defgroup SDMMC_LL_Clock_Edge Clock Edge @@ -350,6 +364,7 @@ typedef struct * @} */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass * @{ */ @@ -361,6 +376,7 @@ typedef struct /** * @} */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving * @{ @@ -403,12 +419,31 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Division Clock Division * @{ */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ +#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400) +#else #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup SDMMC_LL_Transceiver Transceiver + * @{ + */ +#define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U) + +#define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) || \ + ((MODE) == SDMMC_TRANSCEIVER_ENABLE)) +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /** @defgroup SDMMC_LL_Command_Index Command Index * @{ */ @@ -470,6 +505,19 @@ typedef struct ((RESP) == SDMMC_RESP3) || \ ((RESP) == SDMMC_RESP4)) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode + * @{ + */ +#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) +#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) +#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) +#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) + +/** + * @} + */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -536,7 +584,11 @@ typedef struct * @{ */ #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 +#else #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) @@ -571,28 +623,39 @@ typedef struct /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources * @{ */ -#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL -#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL -#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT -#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT -#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR -#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR -#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND -#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT -#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND -#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND -#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE -#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF -#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF -#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF -#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE -#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE -#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT -#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT -#define SDMMC_IT_TXACT SDMMC_STA_TXACT -#define SDMMC_IT_RXACT SDMMC_STA_RXACT -#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL -#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL +#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE +#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE +#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE +#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE +#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE +#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE +#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE +#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE +#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE +#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE +#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE +#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE +#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE +#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE +#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE +#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE +#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE +#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE +#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE +#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE +#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE +#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE +#else +#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE +#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE +#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE +#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE +#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE +#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE +#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} */ @@ -617,16 +680,56 @@ typedef struct #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD +#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT +#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT +#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT +#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 +#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END +#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL +#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT +#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND +#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP +#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE +#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC +#else #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ + SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ + SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ + SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ + SDMMC_FLAG_IDMABTC)) + +#else #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DBCKEND)) + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -648,9 +751,15 @@ typedef struct /* ---------------------- SDMMC registers bit mask --------------------------- */ /* --- CLKCR Register ---*/ /* CLKCR register clear mask */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ + SDMMC_CLKCR_WIDBUS |\ + SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) +#else #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /* --- DCTRL Register ---*/ /* SDMMC DCTRL Clear Mask */ @@ -659,15 +768,29 @@ typedef struct /* --- CMD Register ---*/ /* CMD Register clear mask */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ + SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ + SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) +#else #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* SDMMC Initialization Frequency (400KHz max) */ -#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x3C) /* 48MHz / (SDMMC_INIT_CLK_DIV * 2) < 400KHz */ /* SDMMC Data Transfer Frequency (25MHz max) */ -#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) +#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x1) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV * 2) < 25MHz */ +#else +/* SDMMC Initialization Frequency (400KHz max) */ +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ + +/* SDMMC Data Transfer Frequency (25MHz max) */ +#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} @@ -678,6 +801,7 @@ typedef struct * @{ */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) /** * @brief Enable the SDMMC device. * @param __INSTANCE__: SDMMC Instance @@ -704,6 +828,7 @@ typedef struct * @retval None */ #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Enable the SDMMC device interrupt. @@ -966,15 +1091,23 @@ typedef struct * @param __INSTANCE__: Pointer to SDMMC register base * @retval None */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) +#else +#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ /** * @brief Disable the SD I/O Suspend command sending. * @param __INSTANCE__: Pointer to SDMMC register base * @retval None */ +#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) - +#else +#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ + /** * @brief Enable the CMDTRANS mode. * @param __INSTANCE__ : Pointer to SDMMC register base @@ -1025,6 +1158,9 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); * @{ */ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); +#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); @@ -1067,6 +1203,9 @@ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); +#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c index 4d3e260233..99e28de235 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SPI LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h index 16fc9cdc47..b88bcd537c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SPI LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c index 949bc6d327..083b96f141 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_swpmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief SWPMI LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h index a2452f46a0..4193ed5c22 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_swpmi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_swpmi.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SWPMI LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h index 409db3d0b5..e1ed494005 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_system.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_system.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -77,15 +75,12 @@ extern "C" { * @{ */ -/* Defines used for position in the register */ -#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID) - /** * @brief Power-down in Run mode Flash key */ -#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */ -#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 - to unlock the RUN_PD bit in FLASH_ACR */ +#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ +#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 + to unlock the RUN_PD bit in FLASH_ACR */ /** * @} @@ -377,6 +372,19 @@ extern "C" { #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#if defined(FLASH_ACR_LATENCY_5WS) +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +#endif /** * @} */ @@ -1049,7 +1057,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** @@ -1390,6 +1398,19 @@ __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) * @arg @ref LL_FLASH_LATENCY_2 * @arg @ref LL_FLASH_LATENCY_3 * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 (*) + * @arg @ref LL_FLASH_LATENCY_6 (*) + * @arg @ref LL_FLASH_LATENCY_7 (*) + * @arg @ref LL_FLASH_LATENCY_8 (*) + * @arg @ref LL_FLASH_LATENCY_9 (*) + * @arg @ref LL_FLASH_LATENCY_10 (*) + * @arg @ref LL_FLASH_LATENCY_11 (*) + * @arg @ref LL_FLASH_LATENCY_12 (*) + * @arg @ref LL_FLASH_LATENCY_13 (*) + * @arg @ref LL_FLASH_LATENCY_14 (*) + * @arg @ref LL_FLASH_LATENCY_15 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) @@ -1406,6 +1427,19 @@ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) * @arg @ref LL_FLASH_LATENCY_2 * @arg @ref LL_FLASH_LATENCY_3 * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 (*) + * @arg @ref LL_FLASH_LATENCY_6 (*) + * @arg @ref LL_FLASH_LATENCY_7 (*) + * @arg @ref LL_FLASH_LATENCY_8 (*) + * @arg @ref LL_FLASH_LATENCY_9 (*) + * @arg @ref LL_FLASH_LATENCY_10 (*) + * @arg @ref LL_FLASH_LATENCY_11 (*) + * @arg @ref LL_FLASH_LATENCY_12 (*) + * @arg @ref LL_FLASH_LATENCY_13 (*) + * @arg @ref LL_FLASH_LATENCY_14 (*) + * @arg @ref LL_FLASH_LATENCY_15 (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c index ca7cfed782..4ae0d28f2a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief TIM LL module driver. ****************************************************************************** * @attention @@ -172,24 +170,24 @@ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) @@ -323,11 +321,11 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) { /* Set the default configuration */ - TIM_InitStruct->Prescaler = (uint16_t)0x0000U; + TIM_InitStruct->Prescaler = (uint16_t)0x0000; TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; + TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; } /** @@ -703,7 +701,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; - TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; @@ -716,7 +714,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) /** * @brief Configure the Break and Dead Time feature of the timer instance. * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR - * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it * can be necessary to configure all of them during the first write access to * the TIMx_BDTR register. * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -732,7 +730,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; - + /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); @@ -741,10 +739,10 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); - + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ - + /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); @@ -765,16 +763,16 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); - + /* Set the BREAK2 input related BDTR bit-fields */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); } - + /* Set TIMx_BDTR */ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); - + return SUCCESS; } /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h index 0556e17596..ab0dd4e6d6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_tim.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of TIM LL module. ****************************************************************************** * @attention @@ -159,7 +157,7 @@ static const uint8_t SHIFT_TAB_OISx[] = #endif /* DFSDM1_Channel0 */ #define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /*!< BRK2 BKIN2 input polarity */ #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /*!< BRK2 COMP1 input polarity */ -#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ +#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ /* Remap mask definitions */ #define TIMx_OR1_RMP_SHIFT 16U @@ -171,22 +169,26 @@ static const uint8_t SHIFT_TAB_OISx[] = #endif /* ADC3 */ #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT) #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#if defined(ADC2) && defined(ADC3) #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) +#else +#define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) +#endif /* ADC2 & ADC3 */ #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ -#define DT_DELAY_1 ((uint8_t)0x7FU) -#define DT_DELAY_2 ((uint8_t)0x3FU) -#define DT_DELAY_3 ((uint8_t)0x1FU) -#define DT_DELAY_4 ((uint8_t)0x1FU) +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ -#define DT_RANGE_1 ((uint8_t)0x00U) -#define DT_RANGE_2 ((uint8_t)0x80U) -#define DT_RANGE_3 ((uint8_t)0xC0U) -#define DT_RANGE_4 ((uint8_t)0xE0U) +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) /** Legacy definitions for compatibility purpose @cond 0 @@ -450,8 +452,8 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; -/** - * @brief BDTR (Break and Dead Time) structure definition +/** + * @brief BDTR (Break and Dead Time) structure definition */ typedef struct { @@ -459,31 +461,31 @@ typedef struct This parameter can be a value of @ref TIM_LL_EC_OSSR This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ + has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() - + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ - uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() @@ -494,17 +496,17 @@ typedef struct This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() @@ -515,21 +517,21 @@ typedef struct This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ } LL_TIM_BDTR_InitTypeDef; @@ -593,7 +595,7 @@ typedef struct #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ /** * @} - */ + */ #endif /* USE_FULL_LL_DRIVER */ /** @defgroup TIM_LL_EC_IT IT Defines @@ -825,7 +827,7 @@ typedef struct * @{ */ #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ -#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ +#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ /** * @} @@ -834,9 +836,9 @@ typedef struct /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode * @{ */ -#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ -#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ +#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ +#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ /** * @} */ @@ -894,14 +896,14 @@ typedef struct /** @defgroup TIM_LL_EC_TS Trigger Selection * @{ */ -#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ -#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ -#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ -#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ -#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ -#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ -#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ -#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ +#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ +#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ +#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ +#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ +#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ +#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ +#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ +#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ /** * @} */ @@ -1162,11 +1164,12 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap * @{ */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) +#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ @@ -1335,6 +1338,7 @@ typedef struct /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros * @{ */ + /** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); @@ -1359,9 +1363,9 @@ typedef struct */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ + (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -1482,7 +1486,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) { - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** @@ -1493,18 +1497,18 @@ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) { - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** * @brief Indicates whether update event generation is enabled. * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent * @param TIMx Timer instance - * @retval State of bit (1 or 0). + * @retval Inverted state of bit (0 or 1). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); } /** @@ -1573,6 +1577,9 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * CR1 CMS LL_TIM_SetCounterMode * @param TIMx Timer instance @@ -2515,7 +2522,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -3644,11 +3651,11 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n - * OR2 BKDFBK0E LL_TIM_EnableBreakInputSource\n - * OR3 BKINE LL_TIM_EnableBreakInputSource\n - * OR3 BKCMP1E LL_TIM_EnableBreakInputSource\n - * OR3 BKCMP2E LL_TIM_EnableBreakInputSource\n - * OR3 BKDFBK0E LL_TIM_EnableBreakInputSource + * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n + * OR3 BK2INE LL_TIM_EnableBreakInputSource\n + * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n + * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN @@ -3673,11 +3680,11 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n - * OR2 BKDFBK0E LL_TIM_DisableBreakInputSource\n - * OR3 BKINE LL_TIM_DisableBreakInputSource\n - * OR3 BKCMP1E LL_TIM_DisableBreakInputSource\n - * OR3 BKCMP2E LL_TIM_DisableBreakInputSource\n - * OR3 BKDFBK0E LL_TIM_DisableBreakInputSource + * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n + * OR3 BK2INE LL_TIM_DisableBreakInputSource\n + * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n + * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN @@ -3699,14 +3706,12 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * @brief Set the polarity of the break signal for the timer break input. * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. - * @rmtoll OR2 BKINE LL_TIM_SetBreakInputSourcePolarity\n - * OR2 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n - * OR2 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n - * OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKINE LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n - * OR3 BKINP LL_TIM_SetBreakInputSourcePolarity + * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n + * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n + * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c index 211b7cd943..a49c43007c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usart.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief USART LL module driver. ****************************************************************************** * @attention @@ -73,9 +71,28 @@ * @{ */ +#if defined(USART_PRESC_PRESCALER) +#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + +#endif /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U) +#else #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) +#endif /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \ @@ -222,6 +239,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check the parameters */ assert_param(IS_UART_INSTANCE(USARTx)); +#if defined(USART_PRESC_PRESCALER) + assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue)); +#endif assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); @@ -295,6 +315,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini } /* Configure the USART Baud Rate : +#if defined(USART_PRESC_PRESCALER) + - prescaler value is required +#endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ @@ -304,12 +327,23 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini status = SUCCESS; LL_USART_SetBaudRate(USARTx, periphclk, +#if defined(USART_PRESC_PRESCALER) + USART_InitStruct->PrescalerValue, +#endif USART_InitStruct->OverSampling, USART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR(USARTx->BRR)); } + +#if defined(USART_PRESC_PRESCALER) + /*---------------------------- USART PRESC Configuration ----------------------- + * Configure USARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value. + */ + LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue); +#endif } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -326,6 +360,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) { /* Set USART_InitStruct fields to default values */ +#if defined(USART_PRESC_PRESCALER) + USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; +#endif USART_InitStruct->BaudRate = 9600U; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h index 9fc806da08..da5cd195ff 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usart.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USART LL module. ****************************************************************************** * @attention @@ -58,6 +56,30 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint16_t USART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256 +}; +/** + * @} + */ +#endif /* Private constants ---------------------------------------------------------*/ /** @defgroup USART_LL_Private_Constants USART Private Constants @@ -88,6 +110,13 @@ extern "C" { */ typedef struct { +#if defined(USART_PRESC_PRESCALER) + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ + +#endif uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ @@ -176,6 +205,9 @@ typedef struct #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ +#endif #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ @@ -184,6 +216,9 @@ typedef struct #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ +#if defined(USART_CR2_SLVEN) +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */ +#endif #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ /** @@ -199,14 +234,25 @@ typedef struct #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#else #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ +#endif #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#else #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ +#endif #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#if defined(USART_CR2_SLVEN) +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#endif #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ @@ -216,9 +262,17 @@ typedef struct #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#endif #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ #endif +#if defined(USART_CR1_FIFOEN) +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#endif /** * @} */ @@ -228,24 +282,57 @@ typedef struct * @{ */ #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#else #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#endif #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#else #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#endif #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#endif #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#endif #if defined(USART_TCBGT_SUPPORT) #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ #endif +#if defined(USART_CR1_FIFOEN) +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#endif /** * @} */ +#if defined(USART_CR1_FIFOEN) +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ +#endif + /** @defgroup USART_LL_EC_DIRECTION Communication Direction * @{ */ @@ -334,6 +421,27 @@ typedef struct * @} */ +#if defined(USART_PRESC_PRESCALER) +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +/** + * @} + */ +#endif + /** @defgroup USART_LL_EC_STOPBITS Stop Bits * @{ */ @@ -508,19 +616,59 @@ typedef struct * @brief Compute USARTDIV value according to Peripheral Clock and * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + @if USART_PRESC_PRESCALER + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __PRESCALER__ Prescaler value + @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ +#if defined(USART_PRESC_PRESCALER) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#else #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#endif /** * @brief Compute USARTDIV value according to Peripheral Clock and * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + @if USART_PRESC_PRESCALER + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __PRESCALER__ Prescaler value + @endif * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ +#if defined(USART_PRESC_PRESCALER) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#else #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) +#endif /** * @} @@ -576,6 +724,154 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief FIFO Mode Enable + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); +} +#endif + /** * @brief USART enabled in STOP Mode. * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that @@ -970,6 +1266,60 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); } +#if defined(USART_PRESC_PRESCALER) + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} +#endif + /** * @brief Enable Clock output on SCLK pin * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not @@ -1577,28 +1927,56 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) * @rmtoll BRR BRR LL_USART_SetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + @endif * @param OverSampling This parameter can be one of the following values: * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 * @param BaudRate Baud Rate * @retval None */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, + uint32_t BaudRate) +#else __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate) +#endif { register uint32_t usartdiv = 0x0U; register uint32_t brrtemp = 0x0U; if (OverSampling == LL_USART_OVERSAMPLING_8) { +#if defined(USART_PRESC_PRESCALER) + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, PrescalerValue, BaudRate)); +#else usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); +#endif brrtemp = usartdiv & 0xFFF0U; brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); USARTx->BRR = brrtemp; } else { +#if defined(USART_PRESC_PRESCALER) + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, PrescalerValue, BaudRate)); +#else USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); +#endif } } @@ -1610,15 +1988,37 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @rmtoll BRR BRR LL_USART_GetBaudRate * @param USARTx USART Instance * @param PeriphClk Peripheral Clock + @if USART_PRESC_PRESCALER + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + @endif * @param OverSampling This parameter can be one of the following values: * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ +#if defined(USART_PRESC_PRESCALER) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) +#else __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +#endif { register uint32_t usartdiv = 0x0U; register uint32_t brrresult = 0x0U; +#if defined(USART_PRESC_PRESCALER) + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[PrescalerValue])); +#endif usartdiv = USARTx->BRR; @@ -1627,14 +2027,22 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe if ((usartdiv & 0xFFF7U) != 0U) { usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; +#if defined(USART_PRESC_PRESCALER) + brrresult = (periphclkpresc * 2U) / usartdiv; +#else brrresult = (PeriphClk * 2U) / usartdiv; +#endif } } else { if ((usartdiv & 0xFFFFU) != 0U) { +#if defined(USART_PRESC_PRESCALER) + brrresult = periphclkpresc / usartdiv; +#else brrresult = PeriphClk / usartdiv; +#endif } } return (brrresult); @@ -2020,6 +2428,97 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) * @} */ +#if defined(USART_CR2_SLVEN) + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef* USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef* USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef* USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef* USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef* USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef* USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)); +} + +/** + * @} + */ +#endif + /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature * @{ */ @@ -2566,6 +3065,25 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); +} +#else + /** * @brief Check if the USART Read Data Register Not Empty Flag is set or not * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE @@ -2576,6 +3094,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); } +#endif /** * @brief Check if the USART Transmission Complete Flag is set or not @@ -2588,6 +3107,25 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); +} +#else + /** * @brief Check if the USART Transmit Data Register Empty Flag is set or not * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE @@ -2598,6 +3136,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); } +#endif /** * @brief Check if the USART LIN Break Detection Flag is set or not @@ -2662,6 +3201,22 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)); } +#if defined(USART_CR2_SLVEN) + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)); +} +#endif + /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not @@ -2767,7 +3322,37 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); +} +#endif + #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not @@ -2781,6 +3366,35 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); +} +#endif + /** * @brief Clear Parity Error Flag * @rmtoll ICR PECF LL_USART_ClearFlag_PE @@ -2836,6 +3450,22 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} +#endif + /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_USART_ClearFlag_TC @@ -2848,6 +3478,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) } #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag @@ -2911,6 +3542,22 @@ __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); } +#if defined(USART_CR2_SLVEN) + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} +#endif + /** * @brief Clear Character Match Flag * @rmtoll ICR CMCF LL_USART_ClearFlag_CM @@ -2954,6 +3601,25 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Enable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE @@ -2964,6 +3630,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Enable Transmission Complete Interrupt @@ -2976,6 +3643,25 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) SET_BIT(USARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Enable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE @@ -2986,6 +3672,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Enable Parity Error Interrupt @@ -3033,6 +3720,33 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) SET_BIT(USARTx->CR1, USART_CR1_EOBIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Enable LIN Break Detection Interrupt * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3087,7 +3801,24 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) SET_BIT(USARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} +#endif + #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt @@ -3103,6 +3834,22 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Disable IDLE Interrupt * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE @@ -3114,6 +3861,25 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} +#else + /** * @brief Disable RX Not Empty Interrupt * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE @@ -3124,6 +3890,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); } +#endif /** * @brief Disable Transmission Complete Interrupt @@ -3136,6 +3903,25 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} +#else + /** * @brief Disable TX Empty Interrupt * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE @@ -3146,6 +3932,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); } +#endif /** * @brief Disable Parity Error Interrupt @@ -3193,6 +3980,35 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} +#endif + /** * @brief Disable LIN Break Detection Interrupt * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3247,6 +4063,22 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} +#endif + #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** @@ -3263,6 +4095,22 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} +#endif + /** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE @@ -3274,6 +4122,25 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); +} +#else + /** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE @@ -3284,6 +4151,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); } +#endif /** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. @@ -3296,6 +4164,25 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); } +#if defined(USART_CR1_FIFOEN) + +/* Legacy define */ +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); +} +#else + /** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE @@ -3306,6 +4193,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); } +#endif /** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. @@ -3353,6 +4241,35 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); +} +#endif + /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not @@ -3403,7 +4320,24 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); } +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); +} +#endif + #if defined(USART_TCBGT_SUPPORT) + /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. @@ -3419,6 +4353,22 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) } #endif +#if defined(USART_CR1_FIFOEN) + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); +} +#endif + /** * @} */ @@ -3652,7 +4602,15 @@ __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) } /** + @if USART_CR1_FIFOEN + * @brief Request a Receive Data and FIFO flush + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + @else * @brief Request a Receive Data flush + @endif * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush * @param USARTx USART Instance * @retval None @@ -3663,7 +4621,13 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) } /** + @if USART_CR1_FIFOEN + * @brief Request a Transmit data and FIFO flush + * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + @else * @brief Request a Transmit data flush + @endif * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c index d31a3b1f24..544bc6e826 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usb.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -67,7 +65,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /** @addtogroup STM32L4xx_LL_USB_DRIVER * @{ @@ -2386,7 +2385,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h index 9b30b103fa..d10baf2e60 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_usb.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention @@ -46,7 +44,8 @@ #if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L452xx) || defined(STM32L462xx) || \ defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) + defined(STM32L496xx) || defined(STM32L4A6xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" @@ -605,7 +604,8 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L452xx || STM32L462xx || */ /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ + /* STM32L496xx || STM32L4A6xx || */ + /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c index 57c477b0c9..ab554fc155 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_utils.c * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief UTILS LL module driver. ****************************************************************************** * @attention @@ -54,8 +52,13 @@ /** @addtogroup UTILS_LL_Private_Constants * @{ */ -#define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define UTILS_MAX_FREQUENCY_SCALE1 120000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#else +#define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#endif /* Defines used for PLL range */ #define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */ @@ -68,6 +71,15 @@ #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to HCLK Frequency */ +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#else #define UTILS_SCALE1_LATENCY1_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ #define UTILS_SCALE1_LATENCY2_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ #define UTILS_SCALE1_LATENCY3_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ @@ -75,6 +87,7 @@ #define UTILS_SCALE2_LATENCY1_FREQ 6000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ #define UTILS_SCALE2_LATENCY2_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ #define UTILS_SCALE2_LATENCY3_FREQ 18000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ +#endif /** * @} */ @@ -216,29 +229,51 @@ void LL_mDelay(uint32_t Delay) [..] System, AHB and APB buses clocks configuration - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80000000 Hz. + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is + 120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others. @endverbatim @internal Depending on the device voltage range, the maximum frequency should be adapted accordingly: - (++) Table 1. HCLK clock frequency. - (++) +-------------------------------------------------------+ - (++) | Latency | HCLK clock frequency (MHz) | - (++) | |-------------------------------------| - (++) | | voltage range 1 | voltage range 2 | - (++) | | 1.2 V | 1.0 V | - (++) |-----------------|------------------|------------------| - (++) |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | - (++) |-----------------|------------------|------------------| - (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | - (++) |-----------------|------------------|------------------| - (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | - (++) |-----------------|------------------|------------------| - (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | - (++) |-----------------|------------------|------------------| - (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | - (++) +-------------------------------------------------------+ + (++) Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices + (++) +--------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |--------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.2 V | 1.0 V | + (++) |-----------------|-------------------|------------------| + (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | + (++) |-----------------|-------------------|------------------| + (++) |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | + (++) |-----------------|-------------------|------------------| + (++) |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | + (++) |-----------------|-------------------|------------------| + (++) |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | + (++) |-----------------|-------------------|------------------| + (++) |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | + (++) |-----------------|-------------------|------------------| + (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | + (++) +--------------------------------------------------------+ + + (++) Table 2. HCLK clock frequency for other STM32L4 devices + (++) +-------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |-------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.2 V | 1.0 V | + (++) |-----------------|------------------|------------------| + (++) |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | + (++) |-----------------|------------------|------------------| + (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | + (++) |-----------------|------------------|------------------| + (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | + (++) |-----------------|------------------|------------------| + (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | + (++) |-----------------|------------------|------------------| + (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | + (++) +-------------------------------------------------------+ + @endinternal * @{ */ @@ -262,7 +297,7 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) * - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR) * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM) * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLR: ensure that max frequency at 80000000 Hz is reached (PLLVCO_output / PLLR) + * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR) * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains * the configuration information for the PLL. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains @@ -276,6 +311,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U, msi_range = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = 0U; +#endif /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) @@ -292,7 +330,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS case LL_RCC_MSIRANGE_3: /* MSI = 800 KHz */ case LL_RCC_MSIRANGE_4: /* MSI = 1 MHz */ case LL_RCC_MSIRANGE_5: /* MSI = 2 MHz */ - /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/ + /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/ status = ERROR; break; @@ -345,8 +383,28 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + hpre = UTILS_ClkInitStruct->AHBCLKDivider; + if(hpre == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + } + } +#endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Apply definitive AHB prescaler value if necessary */ + if((status == SUCCESS) && (hpre != 0U)) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + } +#endif } } else @@ -365,7 +423,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR) * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM) * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLR: ensure that max frequency at 80000000 Hz is reach (PLLVCO_output / PLLR) + * - PLLR: ensure that max frequency at 120000000 Hz is reach (PLLVCO_output / PLLR) * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains * the configuration information for the PLL. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains @@ -379,6 +437,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = 0U; +#endif /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) @@ -400,8 +461,28 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + hpre = UTILS_ClkInitStruct->AHBCLKDivider; + if(hpre == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + } + } +#endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Apply definitive AHB prescaler value if necessary */ + if((status == SUCCESS) && (hpre != 0U)) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + } +#endif } else { @@ -419,7 +500,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR) * - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM) * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLR: ensure that max frequency at 80000000 Hz is reached (PLLVCO_output / PLLR) + * - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR) * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 * @param HSEBypass This parameter can be one of the following values: * @arg @ref LL_UTILS_HSEBYPASS_ON @@ -437,6 +518,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U; +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = 0U; +#endif /* Check the parameters */ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); @@ -473,8 +557,28 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + hpre = UTILS_ClkInitStruct->AHBCLKDivider; + if(hpre == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + } + } +#endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + /* Apply definitive AHB prescaler value if necessary */ + if((status == SUCCESS) && (hpre != 0U)) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + } +#endif } else { @@ -519,6 +623,37 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) { if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) + { + /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) { /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */ @@ -541,11 +676,28 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } - /* else HCLK_Frequency < 16MHz default LL_FLASH_LATENCY_0 0WS */ + /* else HCLK_Frequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */ } +#endif } else /* SCALE2 */ { +#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) { /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */ @@ -563,8 +715,9 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } - /* else HCLK_Frequency < 6MHz default LL_FLASH_LATENCY_0 0WS */ + /* else HCLK_Frequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */ } +#endif } LL_FLASH_SetLatency(latency); @@ -604,7 +757,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); - /* - PLLR: ensure that max frequency at 80000000 Hz is reached */ + /* - PLLR: ensure that max frequency at 120000000 Hz is reached */ pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1) * 2); assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); @@ -634,8 +787,8 @@ static ErrorStatus UTILS_PLL_IsBusy(void) /* PLLSAI1 configuration cannot be modified */ status = ERROR; } - #if defined(RCC_PLLSAI2_SUPPORT) + /* Check if PLLSAI2 is busy*/ if(LL_RCC_PLLSAI2_IsReady() != 0U) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h index cc764390b7..01a32c8ab8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_utils.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of UTILS LL module. @verbatim ============================================================================== @@ -189,6 +187,11 @@ typedef struct #define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */ #define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */ #define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000010U /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U /*!< LQFP100 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U /*!< WLCSP144 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U /*!< UFBGA144 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U /*!< UFBGA169 with DSI package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U /*!< LQFP144 with DSI package type */ /** * @} */ @@ -243,7 +246,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void) */ __STATIC_INLINE uint32_t LL_GetFlashSize(void) { - return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); } /** @@ -260,12 +263,17 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*) * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { - return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); } /** @@ -279,7 +287,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) /** * @brief This function configures the Cortex-M SysTick source of the time base. * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param Ticks Number of ticks * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h index 19528d2527..01ba7d0987 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_ll_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 21-April-2017 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention From 6b5302c8f59d19f8715791b9824ba2abd4fea809 Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 5 Jan 2018 22:04:19 +0100 Subject: [PATCH 116/133] Add more comments --- .../TARGET_STM32L4/device/stm32l4xx_hal_def.h | 5 ++- .../TARGET_STM32L4/device/stm32l4xx_hal_hcd.c | 9 ++++- .../TARGET_STM32L4/device/stm32l4xx_hal_i2c.c | 2 ++ .../TARGET_STM32L4/device/stm32l4xx_hal_pcd.c | 36 +++++++++++++++---- .../TARGET_STM32L4/device/stm32l4xx_hal_pcd.h | 3 ++ .../TARGET_STM32L4/device/stm32l4xx_hal_spi.c | 1 + .../TARGET_STM32L4/device/stm32l4xx_ll_usb.c | 3 ++ .../device/stm32l4xx_ll_utils.c | 7 ++++ 8 files changed, 57 insertions(+), 9 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h index 28d8e4f906..fcee1d4eca 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h @@ -122,10 +122,13 @@ typedef enum (__HANDLE__)->Lock = HAL_UNLOCKED; \ }while (0) #endif /* USE_RTOS */ + +// Added for MBED PR #3062 #if defined (__CC_ARM) #pragma diag_suppress 3731 #endif +// Added for MBED PR #3062 static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; @@ -135,7 +138,7 @@ static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) } while (__STREXW(newValue, ptr)); } - +// Added for MBED PR #3062 static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c index a1b683449b..8409955e3b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_hcd.c @@ -206,7 +206,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].ep_num = epnum & 0x7F; hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); hhcd->hc[ch_num].speed = speed; - /* reset to 0 */ + + // Added for MBED PR #3432 + /* reset to 0 */ hhcd->hc[ch_num].toggle_out = 0; hhcd->hc[ch_num].toggle_in = 0; @@ -346,6 +348,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint16_t length, uint8_t do_ping) { + // Added for MBED PR #3432 if ((hhcd->hc[ch_num].ep_is_in != direction)) { if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){ /* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */ @@ -401,6 +404,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].do_ping = do_ping; } } + // Added for MBED PR #3432 else if ((token == 1) && (direction == 1)) { if( hhcd->hc[ch_num].toggle_in == 0) @@ -910,6 +914,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) { + // Added for MBED PR #3432 int reactivate = 0; __HAL_HCD_MASK_HALT_HC_INT(chnum); @@ -939,6 +944,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + // Added for MBED PR #3432 #4231 if ( hhcd->hc[chnum].urb_state != URB_ERROR) { tmpreg |= USB_OTG_HCCHAR_CHENA; reactivate = 1; @@ -946,6 +952,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) USBx_HC(chnum)->HCCHAR = tmpreg; } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + // Added for MBED PR #3432 #4231 if (hhcd->hc[chnum].state == 0) reactivate = 1; if (reactivate == 0) HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c index f46bff66fa..f926f76d79 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c @@ -2592,6 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + // Added for MBED PR #3324 hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); hi2c->XferISR = I2C_Master_ISR_IT; @@ -2665,6 +2666,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + // Added for MBED PR #3324 hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); hi2c->XferISR = I2C_Master_ISR_IT; diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c index 0d8687fa8e..453922e740 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c @@ -162,8 +162,11 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) - hpcd->EPLock[index].Lock = HAL_UNLOCKED; + + // Added for MBED PR #3062 + for (index = 0; index < hpcd->Init.dev_endpoints ; index++) + hpcd->EPLock[index].Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); } @@ -469,6 +472,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { fifoemptymsk = 0x1 << epnum; + + // Added for MBED PR #3062 atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); @@ -1188,6 +1193,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0; ep->num = ep_addr & 0x7F; + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); if ((ep_addr & 0x7F) == 0 ) @@ -1198,6 +1204,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u { USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); } + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1233,7 +1241,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->xfer_count = 0; ep->is_in = 1; ep->num = ep_addr & 0x7F; - + + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); if ((ep_addr & 0x7F) == 0 ) @@ -1244,7 +1253,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); } - + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1272,13 +1282,17 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep->is_stall = 1; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - + + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); + USB_EPSetStall(hpcd->Instance , ep); if((ep_addr & 0x7F) == 0) { USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1306,9 +1320,13 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep->is_stall = 0; ep->num = ep_addr & 0x7F; ep->is_in = ((ep_addr & 0x80) == 0x80); - + + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); + USB_EPClearStall(hpcd->Instance , ep); + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1322,7 +1340,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { + // Added for MBED PR #3062 __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); + if ((ep_addr & 0x80) == 0x80) { USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); @@ -1331,7 +1351,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_FlushRxFifo(hpcd->Instance); } - + + // Added for MBED PR #3062 __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); return HAL_OK; @@ -1444,6 +1465,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t if(len <= 0) { fifoemptymsk = 0x1 << epnum; + // Added for MBED PR #3062 atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h index 6db33ba463..ff07fdfd25 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h @@ -117,6 +117,8 @@ typedef USB_TypeDef PCD_TypeDef; typedef USB_CfgTypeDef PCD_InitTypeDef; typedef USB_EPTypeDef PCD_EPTypeDef; #endif /* USB */ + +// Added for MBED PR #3062 typedef struct { HAL_LockTypeDef Lock; @@ -133,6 +135,7 @@ typedef struct PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ +// Added for MBED PR #3062 PCD_EPLockDef EPLock[15]; __IO PCD_StateTypeDef State; /*!< PCD communication state */ uint32_t Setup[12]; /*!< Setup packet buffer */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c index 46029adbbb..b69650029c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c @@ -650,6 +650,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } + // Added for MBED PR #4975 if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { __HAL_SPI_DISABLE(hspi); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c index 544bc6e826..ce44b68be8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c @@ -570,6 +570,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0) { + // Added for MBED PR #3062 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num); } } @@ -680,6 +681,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0) { + // Added for MBED PR #3062 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num)); } @@ -1406,6 +1408,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /* Write packet into the Tx FIFO. */ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); + // Added for MBED PR #3432 hc->xfer_count = hc->xfer_len; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c index ab554fc155..dff9d0b8ff 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_utils.c @@ -38,6 +38,13 @@ #include "stm32l4xx_ll_system.h" #include "stm32l4xx_ll_pwr.h" +// Removed from MBED PR #3410 +//#ifdef USE_FULL_ASSERT +//#include "stm32_assert.h" +//#else +//#define assert_param(expr) ((void)0U) +//#endif /* USE_FULL_ASSERT */ + /** @addtogroup STM32L4xx_LL_Driver * @{ */ From fb71917adb8bcd8a26f044c0263383916e4f3132 Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 5 Jan 2018 22:04:49 +0100 Subject: [PATCH 117/133] Remove release notes file --- .../device/Release_Notes_stm32l4xx_hal.html | 1016 ----------------- 1 file changed, 1016 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html b/targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html deleted file mode 100644 index 12ece83fdd..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/device/Release_Notes_stm32l4xx_hal.html +++ /dev/null @@ -1,1016 +0,0 @@ - -Release Notes for STM32L4xx HAL Drivers - -
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Back to Release page

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Release -Notes for STM32L4xx HAL Drivers

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Copyright -2017 STMicroelectronics

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Update History

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V1.8.2 -/ 22-December-2017

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Main -Changes

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  • Maintenance Release of HAL and Low Layer drivers
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HAL Drivers changes

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  • HAL CAN driver
    • Rework of HAL CAN driver (compatibility break) 
      • A -new HAL CAN driver has been redesigned with new APIs, to bypass -limitations on CAN Tx/Rx FIFO management present with previous HAL CAN -driver version.
      • The -new HAL CAN driver is the recommended version. It is located as usual -in Drivers/STM32L4xx_HAL_Driver/Src and -Drivers/STM32L4xx_HAL_Driver/Inc folders. It can be enabled through -switch HAL_CAN_MODULE_ENABLED in stm32l4xx_hal_conf.h
      • The -legacy HAL CAN -driver is also present in the release in -Drivers/STM32L4xx_HAL_Driver/Src/Legacy and -Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -folders for software compatibility reasons. Its usage is not -recommended as deprecated. It can however be enabled through -switch HAL_CAN_LEGACY_MODULE_ENABLED in -stm32l4xx_hal_conf.h
      • Short migration guide:
        • Fields of CAN_InitTypeDef structure are renamed : 
          • SJW -to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to -TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to -AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to -TransmitFifoPriority
        • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start()
        • HAL_CAN_Transmit() -is replaced by HAL_CAN_AddTxMessage() to place Tx request, then -HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion
        • HAL_CAN_Transmit_IT() -is replaced by HAL_CAN_ActivateNotification() to enable transmission with interrupt mode, then HAL_CAN_AddTxMessage() to place Tx request
        • HAL_CAN_Receive() -is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message
        • HAL_CAN_Receive_IT() -is replaced by HAL_CAN_ActivateNotification() to enable reception with interrupt mode, then HAL_CAN_GetRxMessage() in the receive callback to get Rx message
        • HAL_CAN_Sleep() is renamed to HAL_CAN_RequestSleep()
        • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback()
        • HAL_CAN_RxCpltCallback() is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback()
      • More complete "how to use the new driver" is detailed in the driver header section itself
  • HAL CORTEX driver
    • HAL_MPU_Enable() and HAL_MPU_Disable() functions moved to stm32l4xx_hal_cortex.c
  • HAL CRC driver
    • Fix GCC warning 
  • HAL FLASH driver
    • HAL_FLASH_Unlock() updated to not return HAL_ERROR if flash is already unlocked 
  • HAL OSPI driver
    • Cleanup IO Manager ports
  • HAL RCC driver
    • RCC_RTCCLKSOURCE_NO_CLK renamed to RCC_RTCCLKSOURCE_NONE
    • HAL_RCC_DeInit() updates
      • Clear of status flags
      • Wait for PLLs disable flags to clear PLLs configuration registers
    • Fix MISRA C-2004 rule 10.6 ('U' suffix)
  • HAL TIM driver
    • Fix MISRA C-2004 rule 10.6 ('U' suffix)

LL Drivers changes

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  • LL CRC driver
    • Fix GCC warning
  • LL RCC driver
    • Add LL_RCC_PLL_SetMainSource() and LL_RCC_HSI_IsEnabledInStopMode() APIs
    • LL_RCC_DeInit() update
      • Clear of status flags
      • Wait for PLLs disable flags to clear PLLs configuration registers
    • Fix IS_LL_RCC_I2C_CLKSOURCE() assert macro

V1.8.1 -/ 13-October-2017

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Main -Changes

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  • Maintenance Release of HAL and Low Layer drivers
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HAL Drivers changes

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  • HAL generic driver
    • Fix compilation issue with ARMCC --gnu option on __packed declaration in stm32l4xx_hal_def.h
  • HAL ADC driver
    • Reuse LL ADC definitions
    • Fix MISRA C-2004 rule 19.10
  • HAL DSI driver
    • Fix -timing issue at highest optimization level on IAR on DSI Host, DSI -Wrapper, DSI PLL and DSI regulator enable/disable macros 
    • Add macro __HAL_DSI_RESET_HANDLE_STATE()
  • HAL FLASH driver
    • HAL_FLASH_Unlock() shall not return an error when Flash already unlocked
  • HAL I2C driver
    • Fix race condition in HAL_I2C_Master_Receive() and HAL_I2C_Slave_Receive()
    • Fix RD_WRN bit management in case of I2C_NO_STARTSTOP request
  • HAL OSPI driver
    • Add note on limitation of HAL_OSPI_AutoPolling() and HAL_OSPI_AutoPolling_IT() usage in octal mode (cf. Errata Sheet)
    • Fix compilation warning in C++
  • HAL QSPI driver
    • Fix MISRA C-2004 rules 10.3, 11.4 and 12.6
  • HAL RCC driver
    • Update -SDMMC1 clock source selection on STM32L4Rx/STM32L4Sx devices to -select PLL divider "P" output instead of internal multiplexor on -MSI, HSI48, PLLSAI1 or PLL "Q" outputs as SDMMC1 kernel clock source
    • Fix __HAL_RCC_GPIOB_IS_CLK_ENABLED() macro definition
  • HAL SDMMC driver
    • Fix management of peripheral flags depending on command or data transfers.
  • HAL SMBUS driver
    • Fix RD_WRN bit management in case of SMBUS_NO_STARTSTOP request

LL Drivers changes

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  • LL DAC driver
    • Add missing definition for external triggers from TIM and LPTIM instances
  • LL DMA2D driver
    • Fix CodeSonar warning in LL_DMA2D_StructInit()
  • LL I2C driver
    • Fix RD_WRN bit management in case of LL_I2C_GENERATE_NOSTARTSTOP request in LL_I2C_HandleTransfer()
  • LL RCC driver
    • Update SDMMC1 clock -source selection on STM32L4Rx/STM32L4Sx devices to select PLL divider -"P" output instead of internal multiplexor on MSI, HSI48, PLLSAI1 or -PLL "Q" outputs as SDMMC1 kernel clock source
      • Add LL_RCC_SetSDMMCKernelClockSource(), LL_RCC_GetSDMMCKernelClockSource() and LL_RCC_GetSDMMCKernelClockFreq() APIs

V1.8.0 -/ 25-August-2017

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Main -Changes

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  • Release of HAL and Low Layer drivers to add support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/ STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
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  • New OctoSPI, DSI, LTDC, GFXMMU peripherals supported in new HAL OSPI, HAL DSI, HAL LTDC and HAL GFXMMU drivers
  • Superset features device STM32L4S9xx API User Manual available (STM32L4S9xx_User_Manual.chm)  
   

HAL Drivers changes

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  • HAL DSI driver (NEW):stm32l4xx_hal_dsi.h/.c files
  • HAL GFXMMU driver (NEW):stm32l4xx_hal_gfxmmu.h/.c files
  • HAL LTDC driver (NEW):stm32l4xx_hal_ltdc.h/.c and extension stm32l4xx_hal_ltdc_ex.h/.c files
  • HAL OSPI driver (NEW):stm32l4xx_hal_ospi.h/.c files
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  • HAL generic driver
    • Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() APIs
    • Default HAL_Delay() implementation updated to insure minimum requested delay
    • Add -__HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE() and -__HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE() macros to set respectively SRAM2 -page protection attribute for page 0 to 31 and page 32 to 63
  • HAL CAN driver
    • Add FIFOs overrun error management (new error codes HAL_CAN_ERROR_FOV0 and HAL_CAN_ERROR_FOV1)
  • HAL CRYP driver
    • Fix zero padding in case of Data type
    • Fix phase setting related to payload suspension
    • Fix to not be too restrictive on input parameters in HAL_CRYPEx_AES_Auth() and  HAL_CRYPEx_AES_Auth_DMA()
  • HAL DAC driver
    • Fix Sample & Hold configuration in case of multi-channel
    • Rename DAC_HIGH_FREQUENCY_INTERFACE_MODE_ENABLE to DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ
  • HAL DMA driver
    • Fix DMAMUX synchronization signal configuration in HAL_DMAEx_ConfigMuxSync()
    • Support of DMAMUX1 peripheral via new DMA Extension APIs
      • HAL_DMAEx_ConfigMuxRequestGenerator()
      • HAL_DMAEx_EnableMuxRequestGenerator(), HAL_DMAEx_DisableMuxRequestGenerator()
      • HAL_DMAEx_ConfigMuxSync()
      • HAL_DMAEx_MUX_IRQHandler()
  • HAL DFSDM driver extension (new stm32l4xx_hal_dfsdm_ex.h/.c)
    • New APIs HAL_DFSDMEx_ChannelSetPulsesSkipping() and HAL_DFSDMEx_ChannelGetPulsesSkipping()
  • HAL DFSDM driver
    • Fix -cast issue to return possible negative value in -HAL_DFSDM_FilterGetRegularValue(), HAL_DFSDM_FilterGetInjectedValue(), -HAL_DFSDM_FilterGetExdMaxValue() and HAL_DFSDM_FilterGetExdMinValue()
  • HAL FLASH driver
    • Add new LVE pin management in HAL_FLASHEx_ConfigLVEPin()
    • Fix timeout issue in private FLASH_WaitForLastOperation() API
    • Fix error status of HAL_FLASHEx_OBProgram(
  • FMC driver
    • New field NBLSetupTime added in FMC_NORSRAM_InitTypeDef structure
    • New field DataHoldTime added in FMC_NORSRAM_TimingTypeDef structure
  • HAL HASH driver
    • Update of context swap mechanism implemented in HAL_HASH_DMAFeed_ProcessSuspend() when input data are fed to the IP by DMA
  • HAL HCD/PCD driver
    • Add support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/ STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
  • HAL IRDA driver
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • IRDA_InitTypeDef structure update to add ClockPrescaler parameter
  • HAL PCD driver
    • Fix USB PCD lock/unlock and flush TX fifo during device reset
  • HAL PWR driver
    • Add PWR_REGULATOR_VOLTAGE_SCALE1_BOOST new parameter value for HAL_PWREx_ControlVoltageScaling() to use higher supply voltage (1.28V) with main regulator voltage in range 1 above 80Mhz (maximum frequency equals to 120Mhz) for STM32L4Rx/STM32L4Sx devices  
    • Add -SRAM3 retention management APIs: HAL_PWREx_EnableSRAM3ContentRetention() and HAL_PWREx_DisableSRAM3ContentRetention()
    • Add DSI pins pull-down management
      • new HAL_PWREx_EnableDSIPinsPDActivation() and HAL_PWREx_DisableDSIPinsPDActivation() APIs
  • HAL RCC driver
    • Add clock management of new peripherals: DSI, GFXMMU, LTDC, OSPI1, OSPI2, OSPIM
    • Add OctoSPI peripherals clock source frequency computation in HAL_RCCEx_GetPeriphCLKFreq()
    • Fix issue with main PLL divider M value to allow 1 to 16 value range on STM32L4Rx/STM32L4Sx devices
    • Fix SDMMC1 clock source selection possibilities in HAL_RCCEx_PeriphCLKConfig(), __HAL_RCC_SDMMC1_CONFIG() and __HAL_RCC_GET_SDMMC1_SOURCE()
    • Fix HAL_RCCEx_GetPeriphCLKFreq() to take into account PLLSAI1 and PLLSAI2 divider M values (1 to 16 range) on STM32L4Rx/STM32L4Sx devices
    • Add undershoot/overshoot management in HAL_RCC_ClockConfig() when switching to/from system clock from main PLL above 80Mhz
  • HAL RNG driver
    • Add support of Clock Error detection and Bypass mode management in new RNG_InitTypeDef and HAL_RNG_Init() API
      • parameters ClockErrorDetection and BypassMode added in new RNG_InitTypeDef
  • HAL RTC driver
    • Fix HAL_RTC_Init() to wait for synchronization and avoid RTC registers access timing issues
  • HAL SAI driver
    • Add FIFO flush in HAL_SAI_DMAStop()
    • Fix HAL_SAI_Transmit_DMA() to follow the slave TX mode sequence described in the Reference Manual
  • HAL SD driver
    • Major rework of HAL SD driver aligned with STM32F7 series
      • BlockSize parameter removed in Read&Write block APIs since 512 byte size is always read&write.
  • HAL SMARTCARD driver
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • SMARTCARD_InitTypeDef structure update to add ClockPrescaler parameter
    • Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only
      • new -HAL_SMARTCARDEx_EnableFifoMode(), HAL_SMARTCARDEx_DisableFifoMode(), -HAL_SMARTCARDEx_SetTxFifoThreshold(), HAL_SMARTCARDEx_SetRxFifoThreshold(), -HAL_SMARTCARDEx_RxFifoFullCallback() and HAL_SMARTCARDEx_TxFifoEmptyCallback() -APIs
  • HAL SMBUS driver
    • Add Analog and digital filter configuration APIs: HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter() 
    • Add error management if occuring during STOP process
  • HAL SPI driver
    • Add control of RXFIFO emty at end of transmissing in Master transmission 2 lines mode
  • HAL SWPMI driver
    • Fix missing clock initialization before register update in HAL_SWPMI_Init()
  • HAL TIM driver
    • Add TIM_TIM1_ETR_GPIO and TIM_TIM8_ETR_GPIO definitions
    • Add TIM_TIM16_TI1_MSI, TIM_TIM16_TI1_HSE_32 and TIM_TIM16_TI1_MCO definitions for STM32L4Rx/STM32L4Sx
    • Add new AutoReloadPreload parameter in TIM_Base_InitTypeDef (user code impacted)
    • Fix wrong MOE disable conditions with new macro __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY()
  • HAL UART driver
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • UART_InitTypeDef structure update to add ClockPrescaler parameter
    • Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only
      • new -HAL_UARTEx_EnableFifoMode(), HAL_UARTEx_DisableFifoMode(), -HAL_UARTEx_SetTxFifoThreshold(), HAL_UARTEx_SetRxFifoThreshold(), -HAL_UARTEx_RxFifoFullCallback() and HAL_UARTEx_TxFifoEmptyCallback() -APIs
    • Add SPI Slave mode management for STM32L4Rx/STM32L4Sx devices only
      • new HAL_UARTEx_EnableSlaveMode(), HAL_UARTEx_DisableSlaveMode() and HAL_UARTEx_ConfigNSS()
  • HAL USART driver (new stm32l4xx_hal_usart_ex.c)
    • Add Clock Prescaler management for STM32L4Rx/STM32L4Sx devices only
      • USART_InitTypeDef structure update to add ClockPrescaler parameter
    • Add FIFO mode management for STM32L4Rx/STM32L4Sx devices only
      • new -HAL_USARTEx_EnableFifoMode(), HAL_USARTEx_DisableFifoMode(), -HAL_USARTEx_SetTxFifoThreshold(), HAL_USARTEx_SetRxFifoThreshold(), -HAL_USARTEx_RxFifoFullCallback() and HAL_USARTEx_TxFifoEmptyCallback() -APIs
    • Add SPI Slave mode management for STM32L4Rx/STM32L4Sx devices only
      • new HAL_USARTEx_EnableSlaveMode(), HAL_USARTEx_DisableSlaveMode() and HAL_USARTEx_ConfigNSS()

-

LL Drivers changes

  • LL DMAMUX driver (NEW):stm32l4xx_ll_dmamux.h
  • All LL drivers update to remove usage of CMSIS POSITION_VAL() macro and resort to xx_Pos position bit definition
  • LL ADC
    • Fix legacy APIs LL_ADC_REG_SetTrigSource() and LL_ADC_INJ_SetTrigSource()
  • LL BUS 
    • Add management of new peripherals: DSI, GFXMMU, LTDC, OSPI1, OSPI2, OSPIM
  • LL DMA
    • Fix simple write register access to clear DMA flags in LL_DMA_ClearFlag_XXX() APIs
  • LL DMA2D
    • Add management of output swapping mode (regular or bytes two by two) and line offset mode (pixel or byte)
  • LL EXTI 
    • Add management of EXTI line 40 (I2C4)
  • LL I2C
    • Fix LL_I2C_Init() to not set OAEN1 bit when Own Address 1 value is 0
  • LL LPUART / LL USART
    • Add management of Rx FIFO and Tx FIFO
  • LL PWR
    • Add -SRAM3 retention management APIs 
      • LL_PWR_EnableSRAM3Retention(), -LL_PWR_DisableSRAM3Retention() and LL_PWR_IsEnabledSRAM3Retention()
    • Add voltage range 1 boost mode APIs
      • LL_PWR_EnableRange1BoostMode(), LL_PWR_DisableRange1BoostMode() and LL_PWR_IsEnabledRange1BoostMode()
    • For compatibility purpose accross STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()
    • Add DSI pins pull-down management
      • new LL_PWR_EnableDSIPinsPDActivation(), LL_PWR_DisableDSIPinsPDActivation() and LL_PWR_IsEnabledDSIPinsPDActivation() APIs
  • LL RCC
    • Add management of new peripheral clock sources for DSI, LTDC, OSPI1, OSPI2 and SDMMC
    • Add -new definitions for main PLL divider M values above LL_RCC_PLLM_DIV_8 -and up to LL_RCC_PLLM_DIV_16 for STM32L4Rx/STM32L4Sx devices
    • Fix -in __LL_RCC_CALC_PLLCLK_SAI_FREQ(), __LL_RCC_CALC_PLLSAI1_SAI_FREQ(), -__LL_RCC_CALC_PLLSAI1_48M_FREQ(), __LL_RCC_CALC_PLLSAI1_ADC_FREQ(), -__LL_RCC_CALC_PLLSAI2_SAI_FREQ()
    • Fix -in LL_RCC_PLLSAI1_ConfigDomain_48M(), -LL_RCC_PLLSAI1_ConfigDomain_SAI(), LL_RCC_PLLSAI1_ConfigDomain_ADC(), -LL_RCC_PLLSAI1_GetP(), LL_RCC_PLLSAI2_ConfigDomain_SAI() and -LL_RCC_PLLSAI2_GetP()
    • Fix LL_RCC_GetSDMMCClockFreq() to take into account all SDMMC1 possible clock sources
    • Add HSI48 oscillator clock source value for RNG and USB: 
      • LL_RCC_RNG_CLKSOURCE_HSI48 and update LL_RCC_GetRNGClockFreq()
      • LL_RCC_USB_CLKSOURCE_HSI48 and update LL_RCC_GetUSBClockFreq()
    • General fixes
      • Renaming of RCC_DFSDM1CLKSOURCE_PCLK to RCC_DFSDM1CLKSOURCE_PCLK2
      • Renaming of RCC_SWPMI1CLKSOURCE_PCLK to RCC_SWPMI1CLKSOURCE_PCLK1
      • Renaming of RCC_LPTIMxCLKSOURCE_PCLK to RCC_LPTIMxCLKSOURCE_PCLK1
  • LL RNG
    • Add Clock Error detection and Bypass mode management in new LL_RNG_InitTypeDef and new LL_RNG_Init() API
      • new LL_RNG_EnableClkErrorDetect(), LL_RNG_DisableClkErrorDetect() and LL_RNG_IsEnableClkErrorDetect()
      • new LL_RNG_EnableBypassMode(), LL_RNG_DisableBypassMode() and LL_RNG_IsEnabledBypassMode
  • LL RTC
    • LL_RTC_TIME_Get() and LL_RTC_DATE_Get() implementations optimization (single register read access)
  • LL SYSTEM
    • Add SRAM2 page write protection APIs: LL_SYSCFG_EnableSRAM2PageWRP_0_31() and LL_SYSCFG_EnableSRAM2PageWRP_32_63()
  • LL TIM
    • Fix definition of TIM break input polarity (inverse values LL_TIM_BKIN_POLARITY_LOW / LL_TIM_BKIN_POLARITY_HIGH)
    • Fix LL_TIM_EnableUpdateEvent(), LL_TIM_DisableUpdateEvent() and LL_TIM_IsEnabledUpdateEvent()
  • LL UTILS
    • Add management of new flash latency ranges in UTILS_SetFlashLatency()
    • Add undershoot management when switching to system clock from main PLL above 80Mhz in LL_PLL_ConfigSystemClock_MSI(), LL_PLL_ConfigSystemClock_HSI() and LL_PLL_ConfigSystemClock_HSE()

V1.7.2 -/ 16-June-2017

-

Main -Changes

-
  • Maintenance Release of HAL and Low Layer drivers

 -

HAL Drivers changes

-
  • HAL CAN driver
    • Add overrun error management by the error callback
  • HAL CRC driver
    • Update of HAL_CRCEx_Polynomial_Set() to return an error when a non-supported polynomial length is passed as parameter
  • HAL CRYP driver
    • Update zero padding management with respect to data type
    • Phase setting and comments correction in case of payload phase suspension
    • Correct input parameters tests in HAL_CRYPEx_AES_Auth() and HAL_CRYPEx_AES_Auth_DMA() APIs
    • Correct interruptions and IP enabling flags setting for key derivation in IT mode
  • HAL DCMI driver
    • Comments correction to describe image size management when larger than maximum authorized DMA transfer size
  • HAL FLASH driver
    • Add software work-around in HAL_FLASH_Unlock() to clear OPTVERR flag on STM32L45x/L46x parts when initially improperly raised
    • Correct timeout issue in FLASH_WaitForLastOperation()
  • HAL HASH driver
    • Update of context swap mechanism implemented in HAL_HASH_DMAFeed_ProcessSuspend() when input data are fed to the IP by DMA

LL Drivers changes

-
  • LL RCC
    • Correct duplication of aRCC_APBAHBPrescTable
  • LL RTC
    • Simplication of implementation of function LL_RTC_DATE_Get()
  • LL TIM
    • Fix LL_TIM_EnableUpdateEvent(), LL_TIM_DisableUpdateEvent() and LL_TIM_IsEnabledUpdateEvent()

V1.7.1 -/ 21-April-2017

-

Main -Changes

-
  • Maintenance Release of HAL and Low Layer drivers
-

   

HAL Drivers changes

-
  • HAL generic driver
    • Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() APIs
  • HAL DAC driver
    • Fix Sample & Hold configuration in case of multi-channel
  • HAL HASH driver
    • Fix to ensure proper DMA-based HASH processing suspension/resumption
  • HAL PCD driver
    • Fix USB PCD lock/unlock and flush TX fifo during device reset
  • HAL RTC driver
    • Add wait for synchronization in HAL_RTC_Init() to insure RTC time initialization 

LL Drivers changes

-
  • LL ADC
    • Fix legacy APIs LL_ADC_REG_SetTrigSource() and LL_ADC_INJ_SetTrigSource()
  • LL DMA 
    • Write only operation on IFCR register

V1.7.0 -/ 17-February-2017

-

Main -Changes

-
  • Release of HAL and Low Layer drivers to add support of STM32L496xx/STM32L4A6xx devices
-
  • New DCMI, DMA2D, HASH peripherals supported in new HAL DCMI, HAL & LL DMA2D and HAL HASH drivers
  • New CAN2 instance supported in HAL CAN
  • Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm) 

   

HAL Drivers changes

-
  • HAL DCMI driver (NEW): stm32l4xx_hal_dcmi.h/.c files
  • HAL DMA2D driver (NEW): stm32l4xx_hal_dma2d.h/.c files
  • HAL HASH driver (NEW): stm32l4xx_hal_hash.h/.c and extension stm32l4xx_hal_hash_ex.h/.c files
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • HAL SD update
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer -to the following examples in STM32CubeL4 firmware package V1.7.0 to -identify the changes: BSP example and USB_Device/MSC_Standalone -application
  • HAL generic update
    • stm32l4xx_hal_conf_template.h updated for new HAL DCMI, HAL DMA2D and HAL HASH
      • #define HAL_DCMI_MODULE_ENABLED
      • #define HAL_DMA2D_MODULE_ENABLED
      • HAL_HASH_MODULE_ENABLED
    • HAL_Delay() updated to guarantee minimum delay
  • HAL CAN driver
    • Add support of CAN2 instance
  • HAL GPIO driver
    • Add support of GPIOI port and STM32L496xx/STM32L4A6xx alternate functions
  • HAL PWR driver
    • Add support of GPIOI port pull-up/pull-down state in Standby and Shutdown modes
  • HAL QSPI driver
    • Fix QSPI_HandleTypeDef structure to handle data size as uint32_t
  • HAL RCC driver
    • Add new macros for new peripherals clock and reset for CAN2, DCMI, DMA2D, GPIOI and HASH
    • Fix HAL_RCCEx_GetPeriphCLKFreq() to compute peripheral frequencies from MSI frequency
    • Fix HAL_RCCEx_GetPeriphCLKFreq() to compute DFSDM1 frequency from PCLK2 frequency
    • Rename some peripheral clock sources to specify the corresponding APB clock:
      • RCC_DFSDM1CLKSOURCE_PCLK to RCC_DFSDM1CLKSOURCE_PCLK2
      • RCC_SWPMI1CLKSOURCE_PCLK to RCC_SWPMI1CLKSOURCE_PCLK1
      • RCC_LPTIMxCLKSOURCE_PCLK to RCC_LPTIMxCLKSOURCE_PCLK1
  • HAL RTC driver
    • Fix wrong clear of time and date registers in HAL_RTCEx_TamperTimeStampIRQHandler()
  • HAL SPI driver
    • Add internal timeout to exit HAL_SPI_Abort() and HAL_SPI_Abort_IT() 
  • HAL TIM driver
    • Fix wrong MOE disable conditions with new macro __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY()
  • HAL SWPMI driver
    • Fix peripheral clock management sequence in HAL_SWPMI_Init()

LL Drivers changes

-
  • LL DMA2D driver (NEW)
  • LL BUS 
    • Add management of new peripherals: CAN2, DCMI, DMA2D, GPIOI and HASH
  • LL PWR
    • For compatibility purpose accross STM32 series, rename LL_PWR_IsActiveFlag_VOSF() to LL_PWR_IsActiveFlag_VOS()
  • LL RCC
    • Fix LL_RCC_GetDFSDMClockFreq() to compute frequency from PCLK2 frequency
  • LL SDMMC
    • Add new internal functions after HAL SD rework
  • LL TIM
    • Fix definition of TIM break input polarity (fix values LL_TIM_BKIN_POLARITY_LOW / LL_TIM_BKIN_POLARITY_HIGH)

V1.6.0 -/ 28-October-2016

-

Main -Changes

-
  • Release of HAL and Low Layer drivers to add support of STM32L451xx/STM32L452xx/STM32L462xx devices
-
  • Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm) 

   

HAL Drivers changes

-
  • HAL CRYP driver
    • HAL CRYP exported macros alignment with other STM32 series to use CRYP handle address as parameter in:
      • __HAL_CRYP_ENABLE(), __HAL_CRYP_DISABLE(), __HAL_CRYP_SET_OPERATINGMODE(), -__HAL_CRYP_SET_CHAININGMODE(), __HAL_CRYP_GET_FLAG(), __HAL_CRYP_CLEAR_FLAG(), -__HAL_CRYP_GET_IT_SOURCE(), __HAL_CRYP_GET_IT(), __HAL_CRYP_CLEAR_IT(), -__HAL_CRYP_ENABLE_IT() and __HAL_CRYP_DISABLE_IT()
  • HAL FLASH driver
    • Temporary data cache deactivation on 
      • Flash programming in HAL_FLASH_Program() and HAL_FLASH_Program_IT()
      • Flash erase in HAL_FLASHEx_Erase() and HAL_FLASHEx_Erase_IT()
    • To insure LSB/MSB address order in C compiler assembly output, split 64-bit programming in 2 double-word write operations
  • HAL I2C driver
    • Fix -to reset HAL I2C handle LISTEN state option in transfer direction -change with HAL_I2C_Slave_Sequential_Transmit_IT() and -HAL_I2C_Slave_Sequential_Receive_IT() 
  • HAL SMBUS driver
    • Add -support of Zone read/write feature thanks to new XferOptions parameter -values SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, -SMBUS_OTHER_AND_LAST_FRAME_NO_PEC and -SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC that may be used in -HAL_SMBUS_Master_Transmit_IT(), HAL_SMBUS_Master_Receive_IT(), -HAL_SMBUS_Slave_Transmit_IT() and HAL_SMBUS_Slave_Receive_IT()
  • HAL RTC driver
    • Fix -race conditions on EXTI flags clearing in HAL_RTC_AlarmIRQHandler(), -HAL_RTCEx_TamperTimeStampIRQHandler() and -HAL_RTCEx_WakeUpTimerIRQHandler()
  • Fix CodeSonar warnings in 
    • HAL ADC, HAL CRC, HAL CRYP, HAL I2C, HAL IRDA, HAL SMARTCARD, HAL SMBUS, HAL OPAMP, HAL RTC, HAL UART, HAL USART

   

-

LL Drivers changes

  • LL I2C driver
    • Add I2C4 management in LL_I2C_DeInit()
  • LL SYSTEM driver
    • Application -shall be responsible to write the correct key sequence in SYSCFG_SKR -register prior to call LL_SYSCFG_EnableSRAM2Erase()
  • LL TIM driver
    • New APIs to insure BDTR register initialization in a single write operation 
      • LL_TIM_BDTR_StructInit()
      • LL_TIM_BDTR_Init()
  • LL UTILS driver
    • Fix LL_RCC_PLLSOURCE_HSE in LL_PLL_ConfigSystemClock_HSE()  

V1.5.2 -/ 12-September-2016

-

HAL Drivers changes

-
  • HAL ADC driver
    • No need to configure number of discontinuous conversions if discontinuous mode is not enabled
    • HAL_ADCEx_MultiModeConfigChannel() returns HAL_ERROR if no Slave instance defined
  • HAL DAC driver
    • Fix calibration with correct handling of DAC_SR_CAL_FLAGx bits in HAL_DACEx_SelfCalibrate()
  • HAL FLASH driver
    • Change in HAL_FLASHEx_OBGetConfig() to not return PCROP and/or WRP data if their respective areas are not defined
    • Fix -error management in HAL_FLASH_IRQHandler() to simply call -HAL_FLASH_OperationErrorCallback() instead of calling both -HAL_FLASH_EndOfOperationCallback() and HAL_FLASH_OperationErrorCallback()
  • HAL I2C driver
    • Fix wrong state check in HAL_I2C_Master_Sequential_Transmit_IT()
    • Add -new option I2C_FIRST_AND_NEXT_FRAME to manage a sequencewith start -condition, address and data to transfer without a final stop condition -allowing successive calls to HAL_I2C_Master_Sequential_Transmit_IT()
  • HAL IRDA driver
    • Add transfer abort functions and associated callbacks in interrupt mode
      • HAL_IRDA_Abort(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortReceive()
      • HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_AbortReceive_IT()
      • HAL_IRDA_AbortCpltCallback(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_AbortReceiveCpltCallback()
    • IRQ Handler + DMA model optimizations
  • HAL RTC driver
    • Fix missing wakeup flag clear in HAL_RTCEx_SetWakeUpTimer_IT()  
  • HAL SMARTCARD driver
    • Add transfer abort functions and associated callbacks in interrupt mode
      • HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortReceive()
      • HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_AbortReceive_IT()
      • HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_AbortReceiveCpltCallback()
    • IRQ Handler + DMA model optimizations
  • HAL SMBUS driver
    • Fix issue on last data reception in host or device modes
  • HAL SPI driver
    • USE_SPI_CRC -compilation define added to provide the mean to optimize the HAL SPI -driver when CRC feature is not used (when CRC is used, application must be changed to set USE_SPI_CRC in stm32l4xx_hal_conf.h (see Inc\stm32l4xx_hal_conf_template.h))
    • Add transfer abort functions and associated callbacks in interrupt mode
      • HAL_SPI_Abort()
      • HAL_SPI_Abort_IT()
      • HAL_SPI_AbortCpltCallback()
  • HAL SWPMI driver
    • Fix SWPMI peripheral errors management in DMA (resort to HAL_DMA_Abort_IT() and DMA XferAbortCallback in HAL_SWPMI_IRQHandler())
  • HAL UART driver
    • New APIs to abort UART tranfer with associated callbacks added 
      • HAL_UART_Abort(), -HAL_UART_AbortTransmit(), HAL_UART_AbortReceive(), HAL_UART_Abort_IT(), -HAL_UART_AbortTransmit_IT(), HAL_UART_AbortReceive_IT(), -HAL_UART_AbortCpltCallback(), HAL_UART_AbortTransmitCpltCallback() and -HAL_UART_AbortReceiveCpltCallback()
  • HAL USART driver
    • New APIs to abort USART tranfer with associated callbacks added
      • HAL_USART_Abort(), HAL_USART_Abort_IT() and HAL_USART_AbortCpltCallback()

LL Drivers -changes

-
  • LL COMP driver
    • Fix LL_COMP_INPUT_PLUS_IO3 definition

V1.5.1 -/ 31-May-2016

-

HAL Drivers changes

-
  • HAL ADC driver
    • Bypass multimode assert_param macro calls depending on configuration
  • HAL CRC driver -
    • HAL_CRC_DeInit() resets CRC_IDR -register to reset value

LL Drivers -changes

-
  • LL BUS driver -
    • LL_APB1_GRP1_PERIPH_USBFS -renamed to LL_APB1_GRP1_PERIPH_USB
    -
  • LL SYSTEM driver -
    • Fix typo on -LL_DBGMCU_APB1_xxx and LL_DBGMCU_APB2_xxx
-

V1.5.0 -/ 29-April-2016

-

Main -Changes

-
  • Maintenance Release of HAL and Low Layer drivers
-

   

HAL Drivers changes

- - -
  • Enhance HAL delay and timebase implementation
    • Add -new driver -stm32l4xx_hal_timebase_tim_template.c which overrides the native HAL -time base functions (defined as weak) to use the TIM peripheral as time -base tick source. For more details about the usage of this driver, please refer to -HAL\HAL_TimeBase example and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0
    • HAL RCC driver
      • To -use PLLSAI1 and PLLSAI2 indidependently from main system PLL, PLLSAI1 -& PLLSAI2 initialization enriched to add PLL entry clock source and -divider M
        • RCC_PLLSAI1InitTypeDef includes PLLSAI1Source and PLLSAI1M new fields
        • RCC_PLLSAI2InitTypeDef includes PLLSAI2Source and PLLSAI2M new fields
      • Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK
      • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
        • All macros __HAL_RCC_DFSDM_xxx() renamed to __HAL_RCC_DFSDM1_xxx()
        • DfsdmClockSelection field of RCC_PeriphCLKInitTypeDef renamed to Dfsdm1ClockSelection
        • RCC_PERIPHCLK_DFSDM renamed to RCC_PERIPHCLK_DFSDM1
        • RCC_DFSDMCLKSOURCE_PCLK renamed to RCC_DFSDM1CLKSOURCE_PCLK
        • RCC_DFSDMCLKSOURCE_SYSCLK renamed to RCC_DFSDM1CLKSOURCE_SYSCLK
        • __HAL_RCC_DFSDM_CONFIG() renamed to __HAL_RCC_DFSDM1_CONFIG()
        • __HAL_RCC_GET_DFSDM_SOURCE() renamed to __HAL_RCC_GET_DFSDM1_SOURCE()
      • Add missing RTC clock source definition RCC_RTCCLKSOURCE_NO_CLK
    • HAL I2C driver
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using -the PPP end of transfer interrupt in the DMA transfer process. This requires the following -updates on user application:
        • Configure and enable the I2Cx IRQ in HAL_I2C_MspInit() function
        • In stm32l4xx_it.c file, I2Cx_IRQHandler() function: add a -call to HAL_I2C_IRQHandler() function
    • HAL UART/USART drivers
      • IRQ Handler global optimization 
      • Add error management in case of DMA transfer through - HAL_DMA_Abort_IT() and DMA XferAbortCallback()
      • Polling management update:
        • The user Timeout value must be estimated for the overall process -duration
    • HAL IRDA/SMARTCARD drivers
      • Polling management update:
        • The user Timeout value must be estimated for the overall process -duration
    • HAL SPI driver
      • Add SPI error management during DMA process: this requires the following updates in the user - application:
        • Configure and enable the SPIx IRQ in - HAL_SPI_MspInit() function
        • In stm32l4xx_it.c file, SPIx_IRQHandler() - function: add a call to HAL_SPI_IRQHandler() function
        • - -Add and customize the -Error Callback API: HAL_SPI_ErrorCallback()
    • HAL QSPI driver
      • Add QSPI error management during DMA process
      • Improve the DMA transmit process by using QSPI TC interrupt instead of -waiting on TC flag under DMA ISR. 
      • These two improvements require the following updates on user -application:
        • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
        • In stm32l4xx_it.c file, QSPI_IRQHandler() function: add a -call to HAL_QSPI_IRQHandler() function
        • Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()
      • Add the management of non-blocking transfer abort -service: HAL_QSPI_Abort_IT(). In this case the user must:
        • Add new callback HAL_QSPI_AbortCpltCallback() - to inform user at the end of abort process
        • A new value of State in -the HAL_QSPI_StateTypeDef provides the current state during the abort phase
- -
      • Polling management update:
        • The user Timeout value must be estimated for the overall process -duration
      • Fix wrong data size management in HAL_QSPI_Receive_DMA()
        • New API HAL_QSPI_SetFifoThreshold() and HAL_QSPI_GetFifoThreshold()
    • HAL IWDG driver
      • New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() -and HAL_IWDG_GetState() APIs
        • API functions are: 
          • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG -counter
          • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
        • Refer to the following example to identify the changes: IWDG_Example
    • HAL WWDG driver
      • New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() -and HAL_WWDG_GetState() APIs
        • Update HAL_WWDG_Refresh() API to remove counter parameter
        • New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt
        • API -functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), -HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()
  • HAL DMA driver
    • Global driver code optimization to reduce memory footprint 
    • New APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() to register/unregister the different possible callbacks identified by enum typedef HAL_DMA_CallbackIDTypeDef
    • New API HAL_DMA_Abort_IT() to abort DMA transfer in non-blocking mode for interrupt context
      • The new registered Abort callback is called when DMA transfer abortion is completed
    • Add new Error Codes: HAL_DMA_ERROR_NO_XFER and -HAL_DMA_ERROR_NOT_SUPPORTED
    • Add __HAL_DMA_GET_COUNTER() macro
  • HAL COMP driver
    • EXTI -configuration done in HAL_COMP_Init() based on TriggerMode field of -COMP_InitTypeDef structure; HAL_COMP_Start()/HAL_COMP_Stop() APIs are sufficient to start and stop comparators (HAL_COMP_Start_IT() and HAL_COMP_Stop_IT() are preserved for -legacy compatibility)
    • Add comparator startup time and scaler bridge stabilization time in HAL_COMP_Init()
    • Fix to call HAL_COMP_TriggerCallback() only once when the 2 comparators are configured in window mode
    • Inverting & Non-inverting inputs renaming (previous definitions preserved for legacy compatibility)
      • COMP_INVERTING_xxx definitions renamed to COMP_INPUT_MINUS_xxx
      • COMP_NONINVERTING_xxx definitions renamed to COMP_INPUT_PLUS_xxx
    • Blanking sources renaming to highlight Comparator & Timer instances connections (previous definitions preserved for legacy compatibility)
      • COMP_BLANKINGSRCE_TIM1OC5 renamed to COMP_BLANKINGSRC_TIM1_OC5_COMP1
      • COMP_BLANKINGSRCE_TIM2OC3 renamed to COMP_BLANKINGSRC_TIM2_OC3_COMP1
      • COMP_BLANKINGSRCE_TIM3OC3 renamed to COMP_BLANKINGSRC_TIM3_OC3_COMP1
      • COMP_BLANKINGSRCE_TIM3OC4 renamed to COMP_BLANKINGSRC_TIM3_OC4_COMP2
      • COMP_BLANKINGSRCE_TIM8OC5 renamed to COMP_BLANKINGSRC_TIM8_OC5_COMP2
      • COMP_BLANKINGSRCE_TIM15OC1 renamed to COMP_BLANKINGSRC_TIM15_OC1_COMP2
      • COMP_BLANKINGSRCE_NONE renamed to COMP_BLANKINGSRC_NONE
  • HAL CRYP driver
    • Software workaround for AES issue on GCM encryption with payload length not a multiple of 128 bits
    • Add support of payload length not multiple of 32 bits
  • HAL GPIO driver
    • Add missing GPIO_AF6_COMP1 for STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx
    • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • GPIO_AF6_DFSDM renamed to GPIO_AF6_DFSDM1
  • HAL HCD driver
    • Clear NACK flag before re-enabling the channel for new IN request
  • HAL PCD driver
    • Host mode
      • Use HCLK frequency to set TRDT value
    • Device mode
      • Force suspend and low-power mode before going to L1 state
      • Unmask Start Of Frame interrupt
  • HAL TIM driver
    • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • TIM_BREAKINPUTSOURCE_DFSDM renamed to TIM_BREAKINPUTSOURCE_DFSDM1
  • HAL SAI driver
    • Update - HAL_SAI_IRQHandler:
      • Add error management in case of DMA transfer through - HAL_DMA_Abort_IT() and DMA XferAbortCallback()
  • HAL SWPMI driver
    • Update initialization sequence in voltage class B

   

-

LL Drivers changes

  • LL ADC driver
    • Fix injected conversion configuration with SW start in LL_ADC_INJ_ConfigQueueContext()
  • LL BUS driver
    • DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • LL_APB2_GRP1_PERIPH_DFSDM renamed to LL_APB2_GRP1_PERIPH_DFSDM1
  • LL COMP driver
    • Window mode renaming to highlight Comparator instances connection (previous definitions preserved for legacy compatibility)
      • LL_COMP_WINDOWMODE_ENABLE renamed to LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
    • Blanking sources renaming to highlight Comparator & Timer instances connections (previous definitions preserved for legacy compatibility)
      • LL_COMP_BLANKINGSRCE_TIM1OC5 renamed to LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
      • LL_COMP_BLANKINGSRCE_TIM2OC3 renamed to LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
      • LL_COMP_BLANKINGSRCE_TIM3OC3 renamed to LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
      • LL_COMP_BLANKINGSRCE_TIM3OC4 renamed to LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2
      • LL_COMP_BLANKINGSRCE_TIM8OC5 renamed to LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
      • LL_COMP_BLANKINGSRCE_TIM15OC1 renamed to LL_COMP_BLANKINGSRC_TIM15_OC1_COMP2
  • LL I2C driver
    •  Add SMBus feature support
      •  LL_I2C_InitTypeDef structure enriched with new PeripheralMode field to indicate I2C or SMBus modes
      • New -APIs LL_I2C_EnableSMBusAlert(), LL_I2C_DisableSMBusAlert(), -LL_I2C_IsEnabledSMBusAlert(), LL_I2C_EnableSMBusPEC(), -LL_I2C_DisableSMBusPEC(), LL_I2C_IsEnabledSMBusPEC(), -LL_I2C_ConfigSMBusTimeout(), LL_I2C_EnableSMBusTimeout(), LL_I2C_DisableSMBusTimeout(), LL_I2C_IsEnabledSMBusTimeout(), LL_I2C_SetSMBusTimeoutA(), LL_I2C_GetSMBusTimeoutA(), LL_I2C_SetSMBusTimeoutAMode(), LL_I2C_GetSMBusTimeoutAMode(), LL_I2C_SetSMBusTimeoutB(), -LL_I2C_GetSMBusTimeoutB(), LL_I2C_SetSMBusTimeoutBMode(), -LL_I2C_GetSMBusTimeoutBMode(), LL_I2C_IsActiveSMBusFlag_PECERR(), LL_I2C_IsActiveSMBusFlag_TIMEOUT(), -LL_I2C_IsActiveSMBusFlag_ALERT(), LL_I2C_ClearSMBusFlag_PECERR(), -LL_I2C_ClearSMBusFlag_TIMEOUT(), LL_I2C_ClearSMBusFlag_ALERT(), -LL_I2C_EnableSMBusPECCompare(), LL_I2C_IsEnabledSMBusPECCompare() and -LL_I2C_GetSMBusPEC()
    • New APIs LL_I2C_SetMode() and LL_I2C_GetMode()
    • New APIs LL_I2C_EnableAutoEndMode(), LL_I2C_DisableAutoEndMode() and LL_I2C_IsEnabledAutoEndMode()
    • New APIs LL_I2C_EnableReloadMode(), LL_I2C_DisableReloadMode() and LL_I2C_IsEnabledReloadMode()
    • New APIs LL_I2C_EnableSlaveByteControl(), LL_I2C_DisableSlaveByteControl() and LL_I2C_IsEnabledSlaveByteControl()
    • New APIs LL_I2C_SetTransferRequest(), LL_I2C_GetTransferRequest(), LL_I2C_SetSlaveAddr() and LL_I2C_GetSlaveAdd()
    • New APIs LL_I2C_SetTransferSize() and LL_I2C_GetTransferSize()
    • New APIs LL_I2C_GenerateStopCondition(), LL_I2C_GenerateStartCondition()
    • New APIs LL_I2C_EnableAuto10BitRead(), LL_I2C_DisableAuto10BitRead() and LL_I2C_IsEnabledAuto10BitRead()
  • LL PWR driver
    •  New APIs LL_PWR_EnterLowPowerRunMode() and LL_PWR_ExitLowPowerRunMode()
  • LL RCC driver
    •  DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • LL_RCC_DFSDM_CLKSOURCE renamed to LL_RCC_DFSDM1_CLKSOURCE
      • LL_RCC_DFSDM_CLKSOURCE_PCLK renamed to LL_RCC_DFSDM1_CLKSOURCE_PCLK
      • LL_RCC_DFSDM_CLKSOURCE_SYSCLK renamed to LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
  • LL SYSTEM driver
    •  New API LL_FLASH_IsPrefetchEnabled()
  • LL TIM driver
    •  DFSDM renaming to DFSDM1 (previous definitions preserved for legacy compatibility)
      • LL_TIM_BKIN_SOURCE_DFBK renamed to LL_TIM_BKIN_SOURCE_DF1BK
    • New OCRef clear input selection definitions LL_TIM_OCREF_CLR_INT_NC and LL_TIM_OCREF_CLR_INT_ETR
    • New OCRef clear API LL_TIM_SetOCRefClearInputSource()

V1.4.0 -/ 26-February-2016

-

Main -Changes

-
  • Release of HAL and Low Layer drivers to add support of STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/ STM32L443xx devices
-
  • Low Layer driver initialization/de-initialization APIs applicable to all STM32L4xx devices
  • CRS peripheral implemented as an extension of HAL RCC (HAL_RCCEx_CRS_xxxx() APIs)
  • Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm) 

   

HAL Drivers changes

-
  • HAL generic update
    • Add default HSI48_VALUE in stm32l4xx_hal_conf_template
  • HAL CRYP update
    • New error code HAL_CRYP_BUSY_ERROR to reject new request while ongoing processing
  • HAL IRDA/SMARTCARD/UART/USART update
    • Improvement of baud rate computation at initialization

   

-

LL Drivers changes

  • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
    • stm32l4xx_ll_crs.c
  • LL BUS update
    •  Add read-back register on clock enable functions to take into account any delay on bus
  • LL ADC update
    •  Trigger sources renaming:
      • LL_ADC_REG_TRIG_SW_START renamed to LL_ADC_REG_TRIG_SOFTWARE
      • LL_ADC_REG_TRIG_EXT_TIMx_CCy renamed to LL_ADC_REG_TRIG_EXT_TIMx_CHy
      • LL_ADC_INJ_TRIG_SW_START renamed to LL_ADC_INJ_TRIG_SOFTWARE
      • LL_ADC_INJ_TRIG_EXT_TIMx_CCy renamed to LL_ADC_INJ_TRIG_EXT_TIMx_CHy
    • Oversamping data shift renaming:
      • LL_ADC_OVS_DATA_SHIFT_NONE renamed to LL_ADC_OVS_SHIFT_NONE
      • LL_ADC_OVS_DATA_SHIFT_xxx renamed to LL_ADC_OVS_SHIFT_xxx
  • LL DAC update
    •  Trigger sources renaming:
      • LL_DAC_TRIGGER_SOFTWARE renamed to LL_DAC_TRIG_SOFTWARE
      • LL_DAC_TRIGGER_TIMx_TRGO renamed to LL_DAC_TRIG_EXT_TIMx_TRGO
      • LL_DAC_TRIGGER_EXT_IT9 renamed to LL_DAC_TRIG_EXT_EXTI_LINE9
  • LL LPUART update
    •  Improvement of LPUARTDIV value in baud rate computation in __LL_LPUART_DIV() macro
  • LL USART update
    •  Improvement of USARTDIV value in baud rate computation in __LL_USART_DIV_SAMPLING8() and __LL_USART_DIV_SAMPLING16() macros

V1.3.0 -/ 29-January-2016

-

Main -Changes

-
  • New Low Layer driver initialization/de-initialization APIs
    • Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() -and more initialization APIs when applicable for peripheral PPP: -ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, -RCC, RNG, RTC, SPI, SWPMI, TIM and USART. 
    • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
      • stm32l4xx_ll_adc.c, stm32l4xx_ll_comp.c, stm32l4xx_ll_crc.c, stm32l4xx_ll_dac.c, stm32l4xx_ll_dma.c, stm32l4xx_ll_exti.c, stm32l4xx_ll_gpio.c, stm32l4xx_ll_i2c.c, stm32l4xx_ll_lptim.c, stm32l4xx_ll_lpuart.c, stm32l4xx_ll_opamp.c, stm32l4xx_ll_pwr.c, stm32l4xx_ll_rcc.c, stm32l4xx_ll_rng.c, stm32l4xx_ll_rtc.c, stm32l4xx_ll_spi.c, stm32l4xx_ll_swpmi.c, stm32l4xx_ll_tim.c and stm32l4xx_ll_usart.c
      • stm32l4xx_ll_utils.c contains some Low Layer utilities for SysTick, Flash latency and clock configuration. 
  • Fix "parameter unused" GCC compilation warnings on __weak functions

HAL Drivers changes

-
  • HAL generic update
    • Declare uwTick as global variable to allow weak HAL_IncTick() API updates in user application 
    • Add new API HAL_SYSCFG_EnableIOAnalogSwitchBooster() and HAL_SYSCFG_DisableIOAnalogSwitchBooster()
  • HAL COMP update
    • Allow comparator lock from the reset state with HAL_COMP_Lock()
  • HAL CRYP update
    • Fix state issue to resume AES calculations
  • HAL DMA update
    • Fix state issue after DMA transfer error 
  • HAL FLASH update
    • Fix __HAL_FLASH_INSTRUCTION_CACHE_RESET() and __HAL_FLASH_DATA_CACHE_RESET() to allow multiple resets
  • HAL I2C update
    • Add support of repeated start feature with the following new APIs
      • HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Sequential_Receive_IT() and  HAL_I2C_Master_Abort_IT(), 
      • HAL_I2C_Slave_Sequential_Transmit_IT() and HAL_I2C_Slave_Sequential_Receive_IT()
      • HAL_I2C_EnableListen_IT() and HAL_I2C_DisableListen_IT()
      • New user callbacks HAL_I2C_ListenCpltCallback() and HAL_I2C_AddrCallback()
    • Fix acknowledge failure error management (STOP being automatically generated)
    • Review -state machine and provide new API  HAL_I2C_GetMode() to return -HAL_I2C_MODE_MASTER, HAL_I2C_MODE_SLAVE or HAL_I2C_MODE_NONE
  • HAL IRDA update
    • Add missing IRDA_CLEAR_IDLEF definition for IDLE flag clear with __HAL_IRDA_CLEAR_FLAG()
  • HAL SD update
    • Fix SD card capacity calculation for cards with capacity over 4GB in HAL_SD_Get_CardInfo()
  • HAL SMARTCARD update
    • Add missing SMARTCARD_STOPBITS_0_5 definition for frame with 0.5 stop bit
    • HAL SMARTCARD guardtime correction to not expect a minimum  of 12 etu
  • HAL UART update
    • Add missing UART_STOPBITS_0_5 definition for frame with 0.5 stop bit
    • RX Buffer flush request should not be called at each RXNE processing
    • Fix wrong macro used in assert_param in HAL_LIN_SendBreak()
  • HAL USART update
    • Add missing USART_STOPBITS_0_5 definition for frame with 0.5 stop bit

LL Drivers changes

-
  • LL UTILS update (user code impacted !)
    • Move the following functions declaration from stm32l4xx_ll_utils.h to stm32l4xx_ll_utils.c file
      • LL_mDelay(), LL_Init1msTick() and LL_SetSystemCoreClock()
  • LL ADC update
    •  FLAG & IT definition name change
  • LL COMP update
    •  Rename InputInverting and InputNonInverting APIs
      • LL_COMP_Set{/Get}InputNonInverting() renamed to LL_COMP_Set{/Get}InputMinus
      • LL_COMP_Set{/Get}InputInverting() renamed to LL_COMP_Set{/Get}InputPlus
    • Remove LL_COMP_SetWindowMode() and LL_COMP_GetWindowMode()
  • LL DMA update
    •  Add helper macro __LL_DMA_GET_CHANNEL_INSTANCE()
  • LL GPIO update
    • Fix definition LL_GPIO_OUTPUT_OPENDRAIN
    • Add -the explicit possible values in the API description of -LL_GPIO_GetPinMode(), LL_GPIO_GetPinOutputType(), -LL_GPIO_GetPinSpeed(), LL_GPIO_GetPinPull(), LL_GPIO_GetAFPin_0_7() and -LL_GPIO_GetAFPin_8_15()
    • Add -GPIO speed definitions LL_GPIO_SPEED_FREQ_LOW, -LL_GPIO_SPEED_FREQ_MEDIUM, LL_GPIO_SPEED_FREQ_HIGH and -LL_GPIO_SPEED_FREQ_VERY_HIGH to align with HAL GPIO
  • LL I2C update
    •  Add missing function LL_I2C_ConfigFilters() to configure noise filters
  • LL LPTIM update
    • Add missing functions
      • LL_LPTIM_IsEnabled()
      • LL_LPTIM_SetWaveform()
      • LL_LPTIM_SetPolarity()
  • LL OPAMP update
    • Rename power range APIs
      • LL_OPAMP_Get{/Set}PowerRange() renamed to LL_OPAMP_Get{/Set}CommonPowerRange()
  • LL SPI update
    • Fix LL_SPI_IsEnabled(), LL_SPI_IsEnabledCRC() and LL_SPI_IsEnabledNSSPulse()
    • Remove -LL_SPI_Set{/Get}HalfDuplexDirection() functions: this is managed with -TransferDirection parameter in LL_SPI_Set{/Get}TransferDirection()
  • LL SWPMI update
    • Add missing function LL_SWPMI_IsActivated()
  • LL TIM update
    • Add missing functions
      • LL_TIM_CC_IsEnabledChannel()
      • LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload() and LL_TIM_OC_IsEnabledClear()
      • LL_TIM_IsEnabledMasterSlaveMode()
      • LL_TIM_EnableExternalClock(), LL_TIM_DisableExternalClock() and LL_TIM_IsEnabledExternalClock()
  • LL USART update
    • Add LL_USART_STOPBITS_0_5 definition for usage in LL_USART_Set{/Get}StopBitsLength() and LL_USART_ConfigCharacter()

V1.2.0 -/ 25-November-2015

-

Main -Changes

-
  • HAL generic update
    • Reduce default HSE startup timeout value to 100ms in Inc\stm32l4xx_hal_conf_template.h file
  • HAL PWR update (User application code impacted)
    • Stop 1 with main regulator renamed into Stop 0, to be aligned with latest version of Reference Manual
    • Change HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry) into HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
      • Application code using HAL_PWREx_EnterSTOP1Mode(PWR_LOWPOWERREGULATOR_ON, STOPEntry) must be updated to use HAL_PWREx_EnterSTOP1Mode(STOPEntry)
    • Add new API HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
      • Application code using HAL_PWREx_EnterSTOP1Mode(PWR_MAINREGULATOR_ON, STOPEntry) must be updated to use HAL_PWREx_EnterSTOP0Mode(STOPEntry)
      •  
  • HAL OPAMP update
    • Provide capability to run calibration despite PGA mode by switching temporary to standalone mode
  • HAL SAI update
    • Update SAI block synchronization selection (User application code impacted)
      • Replace uncomplete SAI_SYNCHRONOUS_EXT value for with SAI_SYNCHRONOUS_EXT_SAI1 and SAI_SYNCHRONOUS_EXT_SAI2
    • Update external synchronization input selection (User application code impacted)
      • Remove useless SAI_SYNCEXT_IN_ENABLE value for SynchroExt field in SAI_InitTypeDef structure
    • Add support of 24bits configuration in PCM protocol
    • Add codec not ready interrupt management
    • Fix computation of data size, frame length, active frame length, slot size and first bit offset in I2S protocol
    • Fix mute counter setting in HAL_SAI_EnableRxMuteMode()
    • Fix -ambiguous clock strobing values: fix HAL_SAI_Init() to set correct -CKSTR bits in SAI_xCR1 according to ClockStrobing and AudioMode -parameters
    • Fill in the Fifo before enable interrupt in HAL_SAI_Transmit_IT()
    • Fix assert on active slot selection in HAL_SAI_Init()
    • Fix companding mode management in HAL_SAI_Init()
  • HAL TSC update
    • Improve IODefault state management
  • HAL NOR/HAL SRAM/FMC update
    • WriteFifo field of FMC_NORSRAM_InitTypeDef structure is not applicable on STM32L47x/STM32L48x devices
  • LL PWR update (User application code impacted)
    • LL PWR API change to add new Stop 0 mode and update Stop 1 mode definition
    • Change LL_PWR_SetPowerMode(uint32_t LowPowerMode) possible LowPowerMode values update 
      • LL_PWR_MODE_STOP1_LP_REGU renamed into LL_PWR_MODE_STOP1
        • Application code using LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1_LP_REGU) must be updated to use LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1)
      • LL_PWR_MODE_STOP1_MAIN_REGU renamed into LL_PWR_MODE_STOP0
        • Application code using LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1_MAIN_REGU) must be updated to use LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0)

V1.1.1 -/ 16-October-2015

-

Main -Changes

-
  • HAL generic update
    • Fine -tuning of Inc\stm32l4xx_hal_conf_template.h file to keep Flash prefetch -off as default system configuration (PREFETCH_ENABLE set to 0)
  • HAL TIM update
    • Removed -useless assert_param() macro check on input parameters in -HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel() and -HAL_TIM_ConfigClockSource(), 
  • LL ADC update
    • Fix LL_ADC_GetAnalogWDMonitChannels() for AWD2 and AWD3
  • LL RCC update
    • Add new API LL_RCC_LSE_DisableCSS()
  • LL UTILS update
    • Fix LL_GetPackageType()

V1.1.0 -/ 16-September-2015

-

Main -Changes

-
  • Add Low Layer drivers allowing performance and footprint optimization 
    • Low -Layer drivers APIs provide register level programming: they require -deep knowledge of peripherals described in STM32L4x6 Reference Manual
    • Low -Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, -EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, -SWPMI, TIM, USART, WWDG peripherals and additionnal Low Level Bus, -System and Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l4xx_ll_ppp.h file must be included in user code.
  • HAL ADC update
    • Channel 5 is not usable for ADC3
  • HAL CAN update
    • Update HAL_CAN_IRQHandler() to clear ERRI bit prior to call HAL_CAN_ErrorCallback()
  • HAL COMP update
    • Update HAL_COMP_Init() for low power optimization in case of COMP_INVERTINGINPUT_VREFINT
  • HAL CRC update
    • Add new API HAL_CRYPEx_ProcessSuspend()
  • HAL DMA update
    • Update HAL_DMA_IRQHandler() to set HAL_DMA_ERROR_TE error bit in handle ErrorCode field
  • HAL FLASH update
    • Add option byte OB_USER_nRST_SHDW to be used with HAL_FLASHEx_OBProgram()
  • HAL GPIO update
    • Rename -GPIO speed definitions to GPIO_SPEED_FREQ_LOW, -GPIO_SPEED_FREQ_MEDIUM, GPIO_SPEED_FREQ_HIGH and -GPIO_SPEED_FREQ_VERY_HIGH
    • Fix macro __HAL_GPIO_EXTI_GENERATE_SWIT()
  • HAL PWR update
    • Fix HAL_PWR_DisableWakeUpPin() to clear only appropriate bits in PWR CR3 register
    • Combination -of GPIO pins possible in HAL_PWREx_EnableGPIOPullUp(), -HAL_PWREx_DisableGPIOPullUp(), HAL_PWREx_EnableGPIOPullDown() and -HAL_PWREx_DisableGPIOPullDown()
  • HAL RCC update
    • Add -LSE Clock Security System (CSS) management with new APIs: -HAL_RCCEx_EnableLSECSS_IT(), HAL_RCCEx_LSECSS_IRQHandler() and -HAL_RCCEx_LSECSS_Callback()
    • Add RCC_MCO1SOURCE_NOCLOCK to provide capability to disable MCO output in HAL_RCC_MCOConfig()
    • Update -HAL_RCC_OscConfig() and HAL_RCCEx_PeriphCLKConfig() to keep backup -domain enabled when configuring respectively LSE and RTC clock -source
    • Update HAL_RCCEx_DisablePLLSAI1() and HAL_RCCEx_DisablePLLSAI2() to disable respectively PLLSAI1 and PLLSAI2 clock outputs
    • Update HAL_RCCEx_GetPeriphCLKFreq() to return the frequency in Hz applied to peripherals via HAL_RCCEx_PeriphCLKConfig()
    • Update HAL_RCC_DeInit() to set default MSI range
    • Remove old workaround on LSE drive medium configuration values
  • HAL SPI update
    • Fix issue to receive CRC in RX 2 lines mode 8-bit dataSize and even buffer size.
  • HAL TIM update
    • Fix macro __HAL_TIM_SET_COMPARE()
  • HAL UART update
    • Remove enable of Error interrupt in HAL_UART_Transmit_IT()

V1.0.0 -/ 26-June-2015

-

Main -Changes

-
  • First official release of STM32L4xx HAL Drivers for STM32L471xx/STM32L475xx/ STM32L476xx/ STM32L485xx and STM32L486xx devices.
-

License

-
-
Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
    -
  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
    2. -
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
    3. -
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived
    -
    4. -
-       -from this software without specific prior written permission.
-
-THIS -SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGE.
-
- -
-
-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file From 9971ad27ca9e12f2758260dde16a4e17b738e995 Mon Sep 17 00:00:00 2001 From: bcostm Date: Fri, 5 Jan 2018 22:05:57 +0100 Subject: [PATCH 118/133] Update system_stm32l4xx.c with latest version --- .../TARGET_STM32L4/device/system_stm32l4xx.c | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c index 4e9cc827c4..f8719f6b4d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32l4xx.c * @author MCD Application Team - * @version V1.3.1 - * @date 21-April-2017 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File * * This file provides two functions and one global variable to be called from @@ -110,15 +108,15 @@ #include "stm32l4xx.h" #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -167,12 +165,12 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ - uint32_t SystemCoreClock = 4000000; + uint32_t SystemCoreClock = 4000000U; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \ - 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; /** * @} */ @@ -189,6 +187,7 @@ * @{ */ +// Removed from MBED PR #4740 /*+ MBED */ #if 0 /*- MBED */ @@ -205,24 +204,25 @@ void SystemInit(void) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ RCC->CR |= RCC_CR_MSION; /* Reset CFGR register */ - RCC->CFGR = 0x00000000; + RCC->CFGR = 0x00000000U; /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; + RCC->CR &= 0xEAF6FFFFU; /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000; + RCC->PLLCFGR = 0x00001000U; /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= 0xFFFBFFFFU; /* Disable all interrupts */ - RCC->CIER = 0x00000000; + RCC->CIER = 0x00000000U; /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM @@ -280,16 +280,16 @@ void SystemInit(void) */ void SystemCoreClockUpdate(void) { - uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2; + uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; /* Get MSI Range frequency--------------------------------------------------*/ if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8; + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; } else { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4; + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; @@ -314,7 +314,7 @@ void SystemCoreClockUpdate(void) SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ; + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; switch (pllsource) { @@ -330,8 +330,8 @@ void SystemCoreClockUpdate(void) pllvco = (msirange / pllm); break; } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2; + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; SystemCoreClock = pllvco/pllr; break; @@ -341,7 +341,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } From 4c7f0e6e5b3451ce5981682837ecea1dc294b218 Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 9 Jan 2018 15:12:06 +0100 Subject: [PATCH 119/133] Update stm32l4xx.h files --- .../TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h | 4 ++-- .../TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l4xx.h | 4 ++-- .../TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h | 4 ++-- .../TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h | 4 ++-- .../TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h index fc2df3cbca..098dcae95d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L4xx device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l4xx.h index 7a1b40b4f0..d0222219ce 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L4xx device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h index 49a5aaca38..ebbb0a21d1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L4xx device used in the target application - * - To use or not the peripheral's drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h index b9fe2a860a..f8eb206aec 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L4xx device used in the target application - * - To use or not the peripheral's drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h index 8a55c79896..cad28cf905 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L4xx device used in the target application - * - To use or not the peripheral's drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * From 5bb6edc9527e6483961af095fabb9dcaa9204fbb Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 9 Jan 2018 15:20:42 +0100 Subject: [PATCH 120/133] Update stm32l4xxxx.h files --- .../TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h | 4 ++-- .../TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h | 2 +- .../TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h | 2 +- .../TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h | 2 +- .../TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h | 4 +++- 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h index 5dc42a0c10..2ed3383594 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention @@ -1063,7 +1063,7 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) +//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h index d19a39436f..a26a4b0e50 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h @@ -1133,7 +1133,7 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) -// #define CAN ((CAN_TypeDef *) CAN1_BASE) +// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h index 738f95e0d2..b5b7968c89 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/stm32l476xx.h @@ -1345,7 +1345,7 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) +//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC1_BASE) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h index a8be1c5319..c4011208aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h @@ -1379,7 +1379,7 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) -//#define CAN ((CAN_TypeDef *) CAN1_BASE) +//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC1_BASE) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h index be0eeca82b..4b717f963e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral�s registers hardware + * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention @@ -1425,6 +1425,7 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) +//#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define I2C4 ((I2C_TypeDef *) I2C4_BASE) @@ -16051,6 +16052,7 @@ typedef struct #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*! Date: Wed, 10 Jan 2018 15:15:08 +0100 Subject: [PATCH 121/133] Use legacy CAN api --- .../device/stm32l4xx_hal_can_legacy.c | 1480 +++++++++++++++++ .../device/stm32l4xx_hal_conf.h | 7 +- 2 files changed, 1484 insertions(+), 3 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c new file mode 100644 index 0000000000..7e93892d6a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_can_legacy.c @@ -0,0 +1,1480 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### User NOTE ##### + ============================================================================== + [..] + (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations. + Another HAL CAN driver version has been designed with new API's, to fix these limitations. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (++) Connect and configure the involved CAN pins using the + following function HAL_GPIO_Init(); + + (#) Initialize and configure the CAN using HAL_CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or + HAL_CAN_Transmit_IT() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN Legacy HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#ifdef HAL_CAN_MODULE_ENABLED +/* Select HAL CAN module in stm32l4xx_hal_conf.h file: + (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations + (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */ +#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32l4xx_hal_conf.h file' +#endif /* HAL_CAN_MODULE_ENABLED */ + +#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' + +#if defined(CAN1) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10 +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CAN peripheral according to the specified parameters + * in the CAN_InitStruct structure and initialize the associated handle. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ + uint32_t tickstart = 0; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + hcan->Instance->MCR |= CAN_MCR_INRQ ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TTCM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_ABOM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_AWUM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_NART; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_RFLM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TXFP; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ + ((uint32_t)hcan->Init.SJW) | \ + ((uint32_t)hcan->Init.BS1) | \ + ((uint32_t)hcan->Init.BS2) | \ + ((uint32_t)hcan->Init.Prescaler - 1); + + /* Request leave initialisation */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + status = CAN_INITSTATUS_SUCCESS; + } + } + + if(status == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); + + filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; + +#if defined(CAN2) + /* Select the start slave bank */ + CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); +#endif + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filternbrbitpos; + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filternbrbitpos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filternbrbitpos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filternbrbitpos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filternbrbitpos; + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; + } + + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filternbrbitpos; + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + CAN1->FA1R |= filternbrbitpos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CAN peripheral registers to their default reset values. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiate and transmit a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiate and transmit a CAN frame message in Interrupt mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + } + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame in Interrupt mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + } + else + { + return HAL_BUSY; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enter the Sleep (low power) mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wake up the CAN peripheral from sleep mode (after that the CAN peripheral + * is in the normal mode). + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handle CAN interrupt request. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + + /* Check Overrun flag for FIFO1 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + } + + /* Check End of reception flag for FIFO0 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + /* Check End of reception flag for FIFO1 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Check Error Warning Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-Off Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + /* No need for clear of Bus-Off Flag as read-only */ + } + + /* Check Last error code Flag */ + if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + switch(hcan->Instance->ESR & CAN_ESR_LEC) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + hcan->Instance->ESR &= ~(CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Clear ERRI bit */ + SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); + + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME ); + + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non-blocking mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Reception complete callback in non-blocking mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN handle state. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN handle state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +/** + * @brief Initiate and transmit a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame. + * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: Specify the FIFO number + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Disable CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* CAN1 */ + +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h index cb4789fe3c..5ad54eb713 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h @@ -52,8 +52,9 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -#define HAL_CAN_MODULE_ENABLED -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +// For MBED we use the CAN legacy for now +//#define HAL_CAN_MODULE_ENABLED +#define HAL_CAN_LEGACY_MODULE_ENABLED #define HAL_COMP_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -245,7 +246,7 @@ #endif /* HAL_CAN_MODULE_ENABLED */ #ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "Legacy/stm32l4xx_hal_can_legacy.h" + #include "stm32l4xx_hal_can_legacy.h" #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ #ifdef HAL_COMP_MODULE_ENABLED From 05bcc9a95376589f7770d74ac78227540b178656 Mon Sep 17 00:00:00 2001 From: chrisyang Date: Wed, 24 Jan 2018 22:51:53 +0800 Subject: [PATCH 122/133] rtl8195am - restructure target files restructure target files to better sync with Ameba sdk base --- .../TARGET_AMEBA/{ => TARGET_RTL8195A}/analogin_api.c | 0 .../TARGET_AMEBA/{ => TARGET_RTL8195A}/analogin_ext.h | 0 .../TARGET_AMEBA/{ => TARGET_RTL8195A}/analogout_api.c | 0 .../TARGET_AMEBA/{sdk => TARGET_RTL8195A/device}/platform_opts.h | 0 .../soc/realtek/8195a/cmsis => TARGET_RTL8195A}/device/strproc.h | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/flash_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/flash_ext.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/flash_ext.h | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/gpio_api.c | 0 .../TARGET_AMEBA/{ => TARGET_RTL8195A}/gpio_irq_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/i2c_api.c | 0 .../TARGET_AMEBA/{ => TARGET_RTL8195A}/log_uart_api.c | 0 .../TARGET_AMEBA/{ => TARGET_RTL8195A}/log_uart_api.h | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/ota_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/ota_api.h | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/port_api.c | 0 .../TARGET_AMEBA/{ => TARGET_RTL8195A}/pwmout_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/rtc_api.c | 0 .../TARGET_AMEBA/{ => TARGET_RTL8195A}/serial_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/spi_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/timer_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/timer_api.h | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/trng_api.c | 0 .../TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/us_ticker.c | 0 .../os/{rtx2/rtx2_service.c => cmsis_rtos/cmsis_rtos_service.c} | 0 .../os/{rtx2/rtx2_service.h => cmsis_rtos/cmsis_rtos_service.h} | 0 .../device => sdk/soc/realtek/8195a/fwlib}/hal_pinmux.h | 0 .../device => sdk/soc/realtek/8195a/fwlib}/hal_platform.h | 0 .../device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_adc.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_dac.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_gdma.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_gpio.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_i2c.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_peri_on.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_pwm.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_sdio.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_spi_flash.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_ssi.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_sys_on.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_timer.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_uart.h | 0 .../soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_wdt.h | 0 43 files changed, 0 insertions(+), 0 deletions(-) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/analogin_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/analogin_ext.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/analogout_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{sdk => TARGET_RTL8195A/device}/platform_opts.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{sdk/soc/realtek/8195a/cmsis => TARGET_RTL8195A}/device/strproc.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/flash_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/flash_ext.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/flash_ext.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/gpio_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/gpio_irq_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/i2c_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/log_uart_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/log_uart_api.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/ota_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/ota_api.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/port_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/pwmout_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/rtc_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/serial_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/spi_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/timer_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/timer_api.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/trng_api.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{ => TARGET_RTL8195A}/us_ticker.c (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/{rtx2/rtx2_service.c => cmsis_rtos/cmsis_rtos_service.c} (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/{rtx2/rtx2_service.h => cmsis_rtos/cmsis_rtos_service.h} (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib}/hal_pinmux.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib}/hal_platform.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_adc.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_dac.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_gdma.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_gpio.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_i2c.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_peri_on.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_pwm.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_sdio.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_spi_flash.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_ssi.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_sys_on.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_timer.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_uart.h (100%) rename targets/TARGET_Realtek/TARGET_AMEBA/{TARGET_RTL8195A/device => sdk/soc/realtek/8195a/fwlib/rtl8195a}/rtl8195a_wdt.h (100%) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/analogin_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/analogin_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/analogin_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_ext.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/analogin_ext.h rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_ext.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/analogout_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogout_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/analogout_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogout_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/platform_opts.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_opts.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/sdk/platform_opts.h rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/platform_opts.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/cmsis/device/strproc.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/strproc.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/cmsis/device/strproc.h rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/strproc.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/flash_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/flash_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/flash_ext.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/flash_ext.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/flash_ext.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/flash_ext.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/gpio_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/gpio_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/gpio_irq_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_irq_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/gpio_irq_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/gpio_irq_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/i2c_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/i2c_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/i2c_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/log_uart_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/log_uart_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/log_uart_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/log_uart_api.h rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/ota_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/ota_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/ota_api.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/ota_api.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/port_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/port_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/port_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/port_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/pwmout_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/pwmout_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/rtc_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/rtc_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/rtc_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/rtc_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/serial_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/serial_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/spi_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/spi_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/timer_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/timer_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/timer_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/timer_api.h rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/timer_api.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/trng_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/trng_api.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/us_ticker.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c rename to targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/us_ticker.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_pinmux.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pinmux.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_pinmux.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_pinmux.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_platform.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_platform.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/hal_platform.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_platform.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_adc.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_adc.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_dac.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_dac.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gdma.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gpio.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_gpio.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_i2c.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_peri_on.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_peri_on.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_pwm.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_pwm.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sdio.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sdio.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_spi_flash.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_spi_flash.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_ssi.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sys_on.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sys_on.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_uart.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_uart.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_wdt.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h similarity index 100% rename from targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_wdt.h rename to targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h From e38489980c49f2c534e4feddabbec88937353ff5 Mon Sep 17 00:00:00 2001 From: chrisyang Date: Fri, 26 Jan 2018 10:58:42 +0800 Subject: [PATCH 123/133] rtl8195am - add missing changes --- mbed-os.IAB | Bin 0 -> 10256384 bytes mbed-os.IAD | Bin 0 -> 100488 bytes mbed-os.IMB | Bin 0 -> 2641920 bytes mbed-os.IMD | Bin 0 -> 26128 bytes mbed-os.PFI | Bin 0 -> 336 bytes mbed-os.PO | Bin 0 -> 776 bytes mbed-os.PR | Bin 0 -> 39512 bytes mbed-os.PRI | Bin 0 -> 253512 bytes mbed-os.PS | Bin 0 -> 2159800 bytes mbed-os.SearchResults | 164 ++++++++++++++++++ mbed-os.WK3 | Bin 0 -> 25994 bytes .../sdk/os/os_dep/include/osdep_service.h | 2 +- 12 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 mbed-os.IAB create mode 100644 mbed-os.IAD create mode 100644 mbed-os.IMB create mode 100644 mbed-os.IMD create mode 100644 mbed-os.PFI create mode 100644 mbed-os.PO create mode 100644 mbed-os.PR create mode 100644 mbed-os.PRI create mode 100644 mbed-os.PS create mode 100644 mbed-os.SearchResults create mode 100644 mbed-os.WK3 diff --git a/mbed-os.IAB b/mbed-os.IAB new file mode 100644 index 0000000000000000000000000000000000000000..2738a4d20ca052a492ebaf6bf6ab03986c81722f GIT binary patch literal 10256384 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(cmsis\target_cortex_m):#if (__FPU_USED == 1) && defined ( __CC_ARM ) +Arm_math.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Arm_math.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Arm_math.h (features\unsupported\dsp\cmsis_dsp):#if defined __CC_ARM +Arm_math.h (features\unsupported\dsp\cmsis_dsp): #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +Arm_math.h (features\unsupported\dsp\cmsis_dsp):#if (__FPU_USED == 1) && defined ( __CC_ARM ) +Arm_math.h (features\unsupported\dsp\cmsis_dsp):#if defined ( __CC_ARM ) +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM +Basic_types.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#elif defined(__CC_ARM) +Basic_types.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#elif defined ( __CC_ARM ) +Basic_types.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#elif defined (__CC_ARM) +Binary.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\source\common):#if defined(__GNUC__) && !defined(__CC_ARM) // keil does not support binary format +Binary.h (features\feature_ble\targets\target_nordic\target_nrf5\source\common):#if defined(__GNUC__) && !defined(__CC_ARM) // keil does not support binary format +Ble_conn_state.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\ble\common):#if defined(__CC_ARM) +Ble_conn_state.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\ble\common):#if defined(__CC_ARM) +Bootloader_util.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\bootloader_dfu):#if defined ( __CC_ARM ) +Cfstore_svm.cpp (features\storage\feature_storage\cfstore\source):#if defined ( __CC_ARM ) +Cfstore_test.c (features\storage\feature_storage\cfstore\source):#if defined ( __CC_ARM ) +Cmsis_compiler.h (cmsis\target_cortex_a):#if defined ( __CC_ARM ) +Cmsis_compiler.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Cmsis_os.h (rtos\target_cortex\rtx4):#if defined(__CC_ARM) +Cmsis_os2.h (rtos\target_cortex\rtx5\include):#if defined(__CC_ARM) +Common_functions.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM +Common_functions.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM +Common_functions.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM +Compiler_abstraction.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\device):#if defined ( __CC_ARM ) +Configuration_store.c (features\storage\feature_storage\cfstore\source):#if defined ( __CC_ARM ) +Core_armv8mbl.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_armv8mml.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_ca.h (cmsis\target_cortex_a):#if defined ( __CC_ARM ) +Core_cm0.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_cm0plus.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_cm23.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_cm3.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_cm33.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_cm4.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_cm7.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) +Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) +Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) +Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) +Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) +Core_sc000.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Core_sc300.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) +Device_manager_peripheral.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\ble\device_manager):#if defined ( __CC_ARM ) +Dlist.h (targets\target_realtek\target_ameba\sdk\common\api\platform):#if defined ( __CC_ARM ) +Em_usb.h (features\unsupported\usbdevice\targets\target_silicon_labs\inc):#ifdef __CC_ARM +Em_usb.h (features\unsupported\usbdevice\targets\target_silicon_labs\inc):#elif defined( __CC_ARM ) /* MDK-ARM compiler */ +Em_usb.h (features\unsupported\usbdevice\targets\target_silicon_labs\inc): #if defined(__ICCARM__) || defined (__CC_ARM) || defined (__CROSSWORKS_ARM) +Hal_soc_ps_monitor.h (targets\target_realtek\target_ameba\sdk\soc\realtek\8195a\fwlib):#if defined (__CC_ARM) +Main.cpp (tests\mbed_hal\flash\functional_tests):#ifdef __CC_ARM +Mbed_application.c (platform):#if defined (__CC_ARM) +Mbed_assert.h (platform):#elif !defined(__cplusplus) && defined(__GNUC__) && !defined(__CC_ARM) \ +Mbed_boot.c (rtos\target_cortex): #elif defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +Mbed_boot.c (rtos\target_cortex):#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +Mbed_critical.c (platform):#if defined (__CC_ARM) +Mbed_retarget.cpp (platform):#elif defined(__CC_ARM) +Mbed_rtx.h (targets\target_realtek):#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +Mbed_rtx_conf.h (rtos\target_cortex):#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +Mbed_sdk_boot.c (platform):#if defined (__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 5010060)) +Mbed_semihost_api.h (platform):#if !defined(__CC_ARM) && !defined(__ARMCC_VERSION) +Mbed_toolchain.h (platform): && !defined(__CC_ARM) /* ARMCC */ \ +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__CC_ARM) +Mbed_toolchain.h (platform):#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM) +Mbed_toolchain.h (platform):#elif defined(__CC_ARM) +Mbed_toolchain.h (platform):#if (defined(__GNUC__) || defined(__clang__)) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) +Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) +Mbed_trace.h (features\feature_common_pal\mbed-trace\mbed-trace):#if defined(__GNUC__) || defined(__CC_ARM) +Mbed_trace.h (features\feature_common_pal\mbed-trace\mbed-trace):#if defined(__GNUC__) || defined(__CC_ARM) +Nrf51.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\device):#if defined(__CC_ARM) +Nrf51.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\device):#if defined(__CC_ARM) +Nrf_delay.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\drivers_nrf\delay):#if defined ( __CC_ARM ) +Nrf_svc.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\softdevice\s130\headers):#if defined (__CC_ARM) +Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#elif defined __CC_ARM +Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#if defined __CC_ARM || defined __TASKING__ +Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#if defined __CC_ARM || defined __GNUC__ +Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):# elif defined __GNUC__ && NS_GCC_VERSION >= 40600 && !defined __CC_ARM +Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#if defined __GNUC__ && NS_GCC_VERSION >= 40600 && !defined __CC_ARM +Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM +Osdep_service.h (targets\target_realtek\target_ameba\sdk\os\os_dep\include):#elif defined ( __CC_ARM ) +Platform_stdlib.h (targets\target_realtek\target_ameba\sdk\common\api\platform):#elif defined (__CC_ARM) +Rtl8195a_compiler.h (targets\target_realtek\target_ameba\target_rtl8195a\device):#elif defined(__CC_ARM) +Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined(__CC_ARM) || \ +Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined (__CC_ARM) || +Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined (__CC_ARM) +Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined (__CC_ARM) +Rtw_debug.h (targets\target_realtek\target_ameba\sdk\common\drivers\wlan\realtek\include):#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) +Rtw_debug.h (targets\target_realtek\target_ameba\sdk\common\drivers\wlan\realtek\include):#endif //#ifdef __CC_ARM +Rtx2_service.c (targets\target_realtek\target_ameba\sdk\os\rtx2):#if defined(__CC_ARM) +Rtx2_service.c (targets\target_realtek\target_ameba\sdk\os\rtx2):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#else // !(defined(__CC_ARM) || defined(__ICCARM__)) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#else // !(defined(__CC_ARM) || defined(__ICCARM__)) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) +Rtx_lib.c (rtos\target_cortex\rtx5\rtx\source): (defined(__GNUC__) && !defined(__CC_ARM)) +Rtx_lib.c (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) || \ +Rtx_lib.c (rtos\target_cortex\rtx5\rtx\source):#if (( defined(__CC_ARM) || \ +Rtx_malloc_wrapper.c (features\feature_uvisor\source\rtx):#elif defined (__CC_ARM) +Section_config.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#if defined (__CC_ARM) +Section_config.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#if defined (__CC_ARM) +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM +Storage_volume.cpp (features\storage\feature_storage\storage-volume-manager\source):#if defined ( __CC_ARM ) +Storage_volume_manager.cpp (features\storage\feature_storage\storage-volume-manager\source):#if defined ( __CC_ARM ) +Utest_shim.h (features\frameworks\utest\utest):# if defined(__CC_ARM) +Uvisor_exports.h (features\feature_uvisor\includes\uvisor\api\inc):#if defined(__CC_ARM) +Uvisor_exports.h (features\feature_uvisor\includes\uvisor\api\inc):#endif /* defined(__CC_ARM) || defined(__GNUC__) */ +Wireless.h (targets\target_realtek\target_ameba\sdk\common\drivers\wlan\realtek\src\osdep):#ifdef __CC_ARM //Fix Keil compile error, must modify sizeof iw_encode_ext - Alex Fang +Wsf_types.h (features\feature_ble\targets\target_cordio\stack\cordio_stack\ws-core\sw\wsf\generic): defined(__CC_ARM) || defined(__IAR_SYSTEMS_ICC__) +Wsf_types.h (features\feature_ble\targets\target_maxim\exactle\wsf\generic): (__ICC8051__ == 0)) || defined(__CC_ARM) || \ diff --git a/mbed-os.WK3 b/mbed-os.WK3 new file mode 100644 index 0000000000000000000000000000000000000000..911a21d7ebad1242bd7cf97dab7afd98ea5a91c6 GIT binary patch literal 25994 zcmeHP3y>Vec^-`pbXY3<;L86Cf1=MO=omoq&?U1&L#;T)~NrT_K@TMIhLast~ADK(Yiv3c~sR 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Jan 2018 11:07:35 +0800 Subject: [PATCH 124/133] rtl8195am - remove irrelevant files --- mbed-os.IAB | Bin 10256384 -> 0 bytes mbed-os.IAD | Bin 100488 -> 0 bytes mbed-os.IMB | Bin 2641920 -> 0 bytes mbed-os.IMD | Bin 26128 -> 0 bytes mbed-os.PFI | Bin 336 -> 0 bytes mbed-os.PO | Bin 776 -> 0 bytes mbed-os.PR | Bin 39512 -> 0 bytes mbed-os.PRI | Bin 253512 -> 0 bytes mbed-os.PS | Bin 2159800 -> 0 bytes mbed-os.SearchResults | 164 ------------------------------------------ mbed-os.WK3 | Bin 25994 -> 0 bytes 11 files changed, 164 deletions(-) delete mode 100644 mbed-os.IAB delete mode 100644 mbed-os.IAD delete mode 100644 mbed-os.IMB delete mode 100644 mbed-os.IMD delete mode 100644 mbed-os.PFI delete mode 100644 mbed-os.PO delete mode 100644 mbed-os.PR delete mode 100644 mbed-os.PRI delete mode 100644 mbed-os.PS delete mode 100644 mbed-os.SearchResults delete mode 100644 mbed-os.WK3 diff --git a/mbed-os.IAB b/mbed-os.IAB deleted file mode 100644 index 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(__FPU_USED == 1) && defined ( __CC_ARM ) -Arm_math.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Arm_math.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Arm_math.h (features\unsupported\dsp\cmsis_dsp):#if defined __CC_ARM -Arm_math.h (features\unsupported\dsp\cmsis_dsp): #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -Arm_math.h (features\unsupported\dsp\cmsis_dsp):#if (__FPU_USED == 1) && defined ( __CC_ARM ) -Arm_math.h (features\unsupported\dsp\cmsis_dsp):#if defined ( __CC_ARM ) -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -basicAPI.cpp (tests\storage_abstraction\basicapi):#ifndef __CC_ARM -Basic_types.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#elif defined(__CC_ARM) -Basic_types.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#elif defined ( __CC_ARM ) -Basic_types.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#elif defined (__CC_ARM) -Binary.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\source\common):#if defined(__GNUC__) && !defined(__CC_ARM) // keil does not support binary format -Binary.h (features\feature_ble\targets\target_nordic\target_nrf5\source\common):#if defined(__GNUC__) && !defined(__CC_ARM) // keil does not support binary format -Ble_conn_state.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\ble\common):#if defined(__CC_ARM) -Ble_conn_state.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\ble\common):#if defined(__CC_ARM) -Bootloader_util.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\bootloader_dfu):#if defined ( __CC_ARM ) -Cfstore_svm.cpp (features\storage\feature_storage\cfstore\source):#if defined ( __CC_ARM ) -Cfstore_test.c (features\storage\feature_storage\cfstore\source):#if defined ( __CC_ARM ) -Cmsis_compiler.h (cmsis\target_cortex_a):#if defined ( __CC_ARM ) -Cmsis_compiler.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Cmsis_os.h (rtos\target_cortex\rtx4):#if defined(__CC_ARM) -Cmsis_os2.h (rtos\target_cortex\rtx5\include):#if defined(__CC_ARM) -Common_functions.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM -Common_functions.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM -Common_functions.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM -Compiler_abstraction.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\device):#if defined ( __CC_ARM ) -Configuration_store.c (features\storage\feature_storage\cfstore\source):#if defined ( __CC_ARM ) -Core_armv8mbl.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_armv8mml.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_ca.h (cmsis\target_cortex_a):#if defined ( __CC_ARM ) -Core_cm0.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_cm0plus.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_cm23.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_cm3.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_cm33.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_cm4.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_cm7.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) -Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) -Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) -Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) -Core_cm7.h (cmsis\target_cortex_m): #if defined ( __CC_ARM ) -Core_sc000.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Core_sc300.h (cmsis\target_cortex_m):#if defined ( __CC_ARM ) -Device_manager_peripheral.c (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\ble\device_manager):#if defined ( __CC_ARM ) -Dlist.h (targets\target_realtek\target_ameba\sdk\common\api\platform):#if defined ( __CC_ARM ) -Em_usb.h (features\unsupported\usbdevice\targets\target_silicon_labs\inc):#ifdef __CC_ARM -Em_usb.h (features\unsupported\usbdevice\targets\target_silicon_labs\inc):#elif defined( __CC_ARM ) /* MDK-ARM compiler */ -Em_usb.h (features\unsupported\usbdevice\targets\target_silicon_labs\inc): #if defined(__ICCARM__) || defined (__CC_ARM) || defined (__CROSSWORKS_ARM) -Hal_soc_ps_monitor.h (targets\target_realtek\target_ameba\sdk\soc\realtek\8195a\fwlib):#if defined (__CC_ARM) -Main.cpp (tests\mbed_hal\flash\functional_tests):#ifdef __CC_ARM -Mbed_application.c (platform):#if defined (__CC_ARM) -Mbed_assert.h (platform):#elif !defined(__cplusplus) && defined(__GNUC__) && !defined(__CC_ARM) \ -Mbed_boot.c (rtos\target_cortex): #elif defined(__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -Mbed_boot.c (rtos\target_cortex):#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -Mbed_critical.c (platform):#if defined (__CC_ARM) -Mbed_retarget.cpp (platform):#elif defined(__CC_ARM) -Mbed_rtx.h (targets\target_realtek):#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -Mbed_rtx_conf.h (rtos\target_cortex):#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -Mbed_sdk_boot.c (platform):#if defined (__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 5010060)) -Mbed_semihost_api.h (platform):#if !defined(__CC_ARM) && !defined(__ARMCC_VERSION) -Mbed_toolchain.h (platform): && !defined(__CC_ARM) /* ARMCC */ \ -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__CC_ARM) -Mbed_toolchain.h (platform):#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM) -Mbed_toolchain.h (platform):#elif defined(__CC_ARM) -Mbed_toolchain.h (platform):#if (defined(__GNUC__) || defined(__clang__)) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) -Mbed_toolchain.h (platform):#if defined(__GNUC__) || defined(__CC_ARM) -Mbed_trace.h (features\feature_common_pal\mbed-trace\mbed-trace):#if defined(__GNUC__) || defined(__CC_ARM) -Mbed_trace.h (features\feature_common_pal\mbed-trace\mbed-trace):#if defined(__GNUC__) || defined(__CC_ARM) -Nrf51.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\device):#if defined(__CC_ARM) -Nrf51.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\device):#if defined(__CC_ARM) -Nrf_delay.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\drivers_nrf\delay):#if defined ( __CC_ARM ) -Nrf_svc.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\softdevice\s130\headers):#if defined (__CC_ARM) -Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#elif defined __CC_ARM -Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#if defined __CC_ARM || defined __TASKING__ -Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#if defined __CC_ARM || defined __GNUC__ -Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):# elif defined __GNUC__ && NS_GCC_VERSION >= 40600 && !defined __CC_ARM -Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#if defined __GNUC__ && NS_GCC_VERSION >= 40600 && !defined __CC_ARM -Ns_types.h (features\feature_common_pal\nanostack-libservice\mbed-client-libservice):#ifdef __CC_ARM -Osdep_service.h (targets\target_realtek\target_ameba\sdk\os\os_dep\include):#elif defined ( __CC_ARM ) -Platform_stdlib.h (targets\target_realtek\target_ameba\sdk\common\api\platform):#elif defined (__CC_ARM) -Rtl8195a_compiler.h (targets\target_realtek\target_ameba\target_rtl8195a\device):#elif defined(__CC_ARM) -Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined(__CC_ARM) || \ -Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined (__CC_ARM) || -Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined (__CC_ARM) -Rtl8195a_init.c (targets\target_realtek\target_ameba\target_rtl8195a\device):#if defined (__CC_ARM) -Rtw_debug.h (targets\target_realtek\target_ameba\sdk\common\drivers\wlan\realtek\include):#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) -Rtw_debug.h (targets\target_realtek\target_ameba\sdk\common\drivers\wlan\realtek\include):#endif //#ifdef __CC_ARM -Rtx2_service.c (targets\target_realtek\target_ameba\sdk\os\rtx2):#if defined(__CC_ARM) -Rtx2_service.c (targets\target_realtek\target_ameba\sdk\os\rtx2):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#else // !(defined(__CC_ARM) || defined(__ICCARM__)) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_ca.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#else // !(defined(__CC_ARM) || defined(__ICCARM__)) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_core_cm.h (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) -Rtx_lib.c (rtos\target_cortex\rtx5\rtx\source): (defined(__GNUC__) && !defined(__CC_ARM)) -Rtx_lib.c (rtos\target_cortex\rtx5\rtx\source):#if defined(__CC_ARM) || \ -Rtx_lib.c (rtos\target_cortex\rtx5\rtx\source):#if (( defined(__CC_ARM) || \ -Rtx_malloc_wrapper.c (features\feature_uvisor\source\rtx):#elif defined (__CC_ARM) -Section_config.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#if defined (__CC_ARM) -Section_config.h (targets\target_realtek\target_ameba\sdk\soc\realtek\common\bsp):#if defined (__CC_ARM) -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Section_vars.h (features\feature_ble\targets\target_nordic\target_mcu_nrf51822\sdk\source\libraries\experimental_section_vars):#if defined __CC_ARM -Storage_volume.cpp (features\storage\feature_storage\storage-volume-manager\source):#if defined ( __CC_ARM ) -Storage_volume_manager.cpp (features\storage\feature_storage\storage-volume-manager\source):#if defined ( __CC_ARM ) -Utest_shim.h (features\frameworks\utest\utest):# if defined(__CC_ARM) -Uvisor_exports.h (features\feature_uvisor\includes\uvisor\api\inc):#if defined(__CC_ARM) -Uvisor_exports.h (features\feature_uvisor\includes\uvisor\api\inc):#endif /* defined(__CC_ARM) || defined(__GNUC__) */ -Wireless.h (targets\target_realtek\target_ameba\sdk\common\drivers\wlan\realtek\src\osdep):#ifdef __CC_ARM //Fix Keil compile error, must modify sizeof iw_encode_ext - Alex Fang -Wsf_types.h (features\feature_ble\targets\target_cordio\stack\cordio_stack\ws-core\sw\wsf\generic): defined(__CC_ARM) || defined(__IAR_SYSTEMS_ICC__) -Wsf_types.h (features\feature_ble\targets\target_maxim\exactle\wsf\generic): (__ICC8051__ == 0)) || defined(__CC_ARM) || \ diff --git a/mbed-os.WK3 b/mbed-os.WK3 deleted file mode 100644 index 911a21d7ebad1242bd7cf97dab7afd98ea5a91c6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 25994 zcmeHP3y>Vec^-`pbXY3<;L86Cf1=MO=omoq&?U1&L#;T)~NrT_K@TMIhLast~ADK(Yiv3c~sR z-tNA+(@I($2S&+x@;}U4UHl1*bx7(KQ zrOmuOWHK)^njULjm$r)eQn6qcdz#jtl0bg0JY5$2yJhnm8R^wT^Kf6}bj5(UNe~YFqfPeHlP0Jvk z2_kFGk-3iV|ML4^?EB?0?j04Q?K*y0N+c(yMPZo9>7- z-SWBc+Vq;$cx-Ok{5k%E=QZKARjKJ!W9yN13DhM}mq1+tbqUlZaE43ZzXHb>z8w&I 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zIvHQglJV5`D=THR%O(u$7fV?f8KdYM-%i?A+4b;#Z%^5`C#LY1rx@P4=`AMH ztC9)2Wgxyr&|g(y>cq?}6PXt?*1Ihpi}Jij{`$M5@-W90xN;Dfw!QZUj`lmo&cT$?gVZHNQJKjE(J)9 zzYR70Bj5?(0bnKYd0+?739JWx7gz+)wdU)$G45LJ7(`x zqop^Nigz%~s7@A77z6QCv`aOH4*iJTwt@9@w=3$2L?Y6k>Pl@-#8{+vyJ{p2C$L;7 zs`_FBef{0-ZQXs*ttyuh?~5Aofk;9%gS9(e6s^Wrh54LTtAf$Tppg5Lsw{4hGhWsl zwN(wCmutFV7?Z*pQ^gqTj`zkGQ%dmat0S3=oe2%?3_-8Z|1d&B_J~thiB2VViQ@9A z5Hy1|8iHXfM8-AD3^n^o?pS3NPDR_4_9I=8f;wa!{k_ptyssDcmE1L8+4U5gm;oA5Vvjt;jN73D8 z7cxb6+ET4*s;n-Rr5Yoy1JY?%%?c(e0$4R**;53{7M4@2F0`)8h2jKjtr|Zhok%TG zEtEit!EgG~lqWzHa<`-ZpnlWWDtdEIBes+nOM4NgEqhPD5zl)d!7G8?*cLAZ^3bdQ zgu<(UN1-3D1Ly^sF9FTKv(Rk}SPDFi8ssg>$7ltdT?<&yPWSQJ7wc9)W&BftkKYPd z5(9rUc|} n?S>GZ`r`jb=)lw4aQT=RFm+qu^bg9^ZG|;{VCVn6t?>T Date: Tue, 9 Jan 2018 16:48:39 +0900 Subject: [PATCH 125/133] Commonize RZ_A1 related folders placed in "FEATURE_LWIP" directory In the below "features/FEATURE_LWIP" folders, same as Cortex-M targets, I changed the folder structure to combine files that can be shared as RZ/A1 related. And I renamed the folder name to "TARGET_RZ_A1XX" in order to make commonality explicit. - "features/FEATURE_LWIP" folder \features\FEATURE_LWIP\lwip-interface\lwip-eth\arch\TARGET_RZ_A1H \features\FEATURE_LWIP\lwip-interface\lwip-eth\arch\TARGET_VK_RZ_A1H \features\FEATURE_LWIP\lwip-interface\lwip-eth\arch\TARGET_RZ_A1XX --- .../lwipopts_conf.h | 0 .../rza1_emac.c | 0 .../arch/TARGET_VK_RZ_A1H/lwipopts_conf.h | 26 --- .../arch/TARGET_VK_RZ_A1H/rza1_emac.c | 210 ------------------ 4 files changed, 236 deletions(-) rename features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/{TARGET_RZ_A1H => TARGET_RZ_A1XX}/lwipopts_conf.h (100%) rename features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/{TARGET_RZ_A1H => TARGET_RZ_A1XX}/rza1_emac.c (100%) delete mode 100644 features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/lwipopts_conf.h delete mode 100644 features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/rza1_emac.c diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/lwipopts_conf.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h similarity index 100% rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/lwipopts_conf.h rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c similarity index 100% rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/lwipopts_conf.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/lwipopts_conf.h deleted file mode 100644 index 1ad186c7a1..0000000000 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/lwipopts_conf.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright (C) 2012 mbed.org, MIT License - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this software - * and associated documentation files (the "Software"), to deal in the Software without restriction, - * including without limitation the rights to use, copy, modify, merge, publish, distribute, - * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING - * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef LWIPOPTS_CONF_H -#define LWIPOPTS_CONF_H - -#define LWIP_TRANSPORT_ETHERNET 1 - -#define MEM_SIZE (1600 * 16) - -#endif diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/rza1_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/rza1_emac.c deleted file mode 100644 index 65515507a0..0000000000 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_VK_RZ_A1H/rza1_emac.c +++ /dev/null @@ -1,210 +0,0 @@ -#include "lwip/opt.h" -#include "lwip/tcpip.h" -#include "netif/etharp.h" -#include "lwip/ethip6.h" -#include "mbed_interface.h" -#include "ethernet_api.h" -#include "ethernetext_api.h" - -#define RECV_TASK_PRI (osPriorityNormal) -#define PHY_TASK_PRI (osPriorityNormal) -#define PHY_TASK_WAIT (200) - -/* memory */ -static sys_sem_t recv_ready_sem; /* receive ready semaphore */ - -/* function */ -static void rza1_recv_task(void *arg); -static void rza1_phy_task(void *arg); -#if LWIP_IPV4 -static err_t rza1_etharp_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr); -#endif -#if LWIP_IPV6 -static err_t rza1_etharp_output_ipv6(struct netif *netif, struct pbuf *q, const ip6_addr_t *ipaddr); -#endif -static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p); -static void rza1_recv_callback(void); - -static void rza1_recv_task(void *arg) { - struct netif *netif = (struct netif*)arg; - u16_t recv_size; - struct pbuf *p; - int cnt; - - while (1) { - sys_arch_sem_wait(&recv_ready_sem, 0); - for (cnt = 0; cnt < 16; cnt++) { - recv_size = ethernet_receive(); - if (recv_size != 0) { - p = pbuf_alloc(PBUF_RAW, recv_size, PBUF_RAM); - if (p != NULL) { - (void)ethernet_read((char *)p->payload, p->len); - /* full packet send to tcpip_thread to process */ - if (netif->input(p, netif) != ERR_OK) { - /* Free buffer */ - pbuf_free(p); - } - } - } else { - break; - } - } - } -} - -static void rza1_phy_task(void *arg) { - struct netif *netif = (struct netif*)arg; - s32_t connect_sts = 0; /* 0: disconnect, 1:connect */ - s32_t link_sts; - s32_t link_mode_new = NEGO_FAIL; - s32_t link_mode_old = NEGO_FAIL; - - while (1) { - link_sts = ethernet_link(); - if (link_sts == 1) { - link_mode_new = ethernetext_chk_link_mode(); - if (link_mode_new != link_mode_old) { - if (connect_sts == 1) { - tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1); - } - if (link_mode_new != NEGO_FAIL) { - ethernetext_set_link_mode(link_mode_new); - tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_up, (void*) netif, 1); - connect_sts = 1; - } - } - } else { - if (connect_sts != 0) { - tcpip_callback_with_block((tcpip_callback_fn)netif_set_link_down, (void*) netif, 1); - link_mode_new = NEGO_FAIL; - connect_sts = 0; - } - } - link_mode_old = link_mode_new; - osDelay(PHY_TASK_WAIT); - } -} - -#if LWIP_IPV4 -static err_t rza1_etharp_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) { - /* Only send packet is link is up */ - if (netif->flags & NETIF_FLAG_LINK_UP) { - return etharp_output(netif, q, ipaddr); - } - - return ERR_CONN; -} -#endif - -#if LWIP_IPV6 -static err_t rza1_etharp_output_ipv6(struct netif *netif, struct pbuf *q, const ip6_addr_t *ipaddr) { - /* Only send packet is link is up */ - if (netif->flags & NETIF_FLAG_LINK_UP) { - return ethip6_output(netif, q, ipaddr); - } - - return ERR_CONN; -} -#endif - -static err_t rza1_low_level_output(struct netif *netif, struct pbuf *p) { - struct pbuf *q; - s32_t cnt; - err_t err = ERR_MEM; - s32_t write_size = 0; - - if ((p->payload != NULL) && (p->len != 0)) { - /* If the first data can't be written, transmit descriptor is full. */ - for (cnt = 0; cnt < 100; cnt++) { - write_size = ethernet_write((char *)p->payload, p->len); - if (write_size != 0) { - break; - } - osDelay(1); - } - if (write_size != 0) { - for (q = p->next; q != NULL; q = q->next) { - (void)ethernet_write((char *)q->payload, q->len); - } - if (ethernet_send() == 1) { - err = ERR_OK; - } - } - } - - return err; -} - -static void rza1_recv_callback(void) { - sys_sem_signal(&recv_ready_sem); -} - -err_t eth_arch_enetif_init(struct netif *netif) -{ - ethernet_cfg_t ethcfg; - - /* set MAC hardware address */ -#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE) - netif->hwaddr[0] = MBED_MAC_ADDR_0; - netif->hwaddr[1] = MBED_MAC_ADDR_1; - netif->hwaddr[2] = MBED_MAC_ADDR_2; - netif->hwaddr[3] = MBED_MAC_ADDR_3; - netif->hwaddr[4] = MBED_MAC_ADDR_4; - netif->hwaddr[5] = MBED_MAC_ADDR_5; -#else - mbed_mac_address((char *)netif->hwaddr); -#endif - netif->hwaddr_len = ETH_HWADDR_LEN; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* device capabilities */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET; -#ifdef LWIP_IGMP - netif->flags |= NETIF_FLAG_IGMP; -#endif -#if LWIP_IPV6_MLD - netif->flags |= NETIF_FLAG_MLD6; -#endif - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwiprza1"; -#endif /* LWIP_NETIF_HOSTNAME */ - - netif->name[0] = 'e'; - netif->name[1] = 'n'; - -#if LWIP_IPV4 - netif->output = rza1_etharp_output_ipv4; -#endif -#if LWIP_IPV6 - netif->output_ip6 = rza1_etharp_output_ipv6; -#endif - - netif->linkoutput = rza1_low_level_output; - - /* Initialize the hardware */ - ethcfg.int_priority = 6; - ethcfg.recv_cb = &rza1_recv_callback; - ethcfg.ether_mac = (char *)netif->hwaddr; - ethernetext_init(ðcfg); - - /* semaphore */ - sys_sem_new(&recv_ready_sem, 0); - - /* task */ - sys_thread_new("rza1_emac_rx_thread", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI); - sys_thread_new("rza1_emac_phy_thread", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI); - - return ERR_OK; -} - -void eth_arch_enable_interrupts(void) { - ethernetext_start_stop(1); -} - -void eth_arch_disable_interrupts(void) { - ethernetext_start_stop(0); -} From 7d270160d0adab0459e6099407c374d58673fffa Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Tue, 9 Jan 2018 17:39:22 +0900 Subject: [PATCH 126/133] Revise the folder structure in "targets/TARGET_RENESAS" directory In "targets/TARGET_RENESAS" folders, same as Cortex-M targets, I changed the folder structure to combine files that can be shared as RZ/A1 related. And I renamed the folder name to "TARGET_RZ_A1XX" in order to make commonality explicit. - "targets/TARGET_RENESAS" folder \targets\TARGET_RENESAS\TARGET_RZ_A1H \targets\TARGET_RENESAS\TARGET_VK_RZ_A1H \targets\TARGET_RENESAS\TARGET_RZ_A1XX --- .../TARGET_RZ_A1H/PeripheralNames.h | 0 .../TARGET_RZ_A1H/PinNames.h | 0 .../TARGET_RZ_A1H/PortNames.h | 0 .../TARGET_MBED_MBRZA1H/reserved_pins.h | 0 .../TARGET_RZ_A1H/analogin_api.c | 0 .../TARGET_RZ_A1H/can_api.c | 0 .../TARGET_RZ_A1H/device.h | 0 .../TARGET_RZ_A1H/device/MBRZA1H.h | 0 .../TARGET_RZ_A1H/device/RZ_A1_Init.c | 0 .../device/TOOLCHAIN_ARM_STD/MBRZA1H.sct | 0 .../device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h | 0 .../device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c | 0 .../device/TOOLCHAIN_ARM_STD/sys.cpp | 0 .../device/TOOLCHAIN_GCC_ARM/RZA1H.ld | 0 .../device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S | 0 .../device/TOOLCHAIN_IAR/MBRZA1H.icf | 0 .../device/TOOLCHAIN_IAR/startup_RZA1H.S | 0 .../TARGET_RZ_A1H/device/cmsis.h | 0 .../TARGET_RZ_A1H/device/cmsis_nvic.c | 0 .../TARGET_RZ_A1H/device/inc/RZ_A1H.h | 0 .../device/inc/iobitmasks/bsc_iobitmask.h | 0 .../device/inc/iobitmasks/cpg_iobitmask.h | 0 .../device/inc/iobitmasks/dmac_iobitmask.h | 0 .../device/inc/iobitmasks/gpio_iobitmask.h | 0 .../device/inc/iobitmasks/intc_iobitmask.h | 0 .../device/inc/iobitmasks/mtu2_iobitmask.h | 0 .../device/inc/iobitmasks/ostm_iobitmask.h | 0 .../device/inc/iobitmasks/riic_iobitmask.h | 0 .../device/inc/iobitmasks/rspi_iobitmask.h | 0 .../device/inc/iobitmasks/scif_iobitmask.h | 0 .../device/inc/iobitmasks/usb_iobitmask.h | 0 .../TARGET_RZ_A1H/device/inc/iodefine.h | 0 .../device/inc/iodefines/adc_iodefine.h | 0 .../device/inc/iodefines/bsc_iodefine.h | 0 .../device/inc/iodefines/ceu_iodefine.h | 0 .../device/inc/iodefines/cpg_iodefine.h | 0 .../device/inc/iodefines/disc_iodefine.h | 0 .../device/inc/iodefines/dmac_iodefine.h | 0 .../device/inc/iodefines/dvdec_iodefine.h | 0 .../device/inc/iodefines/ether_iodefine.h | 0 .../device/inc/iodefines/flctl_iodefine.h | 0 .../device/inc/iodefines/gpio_iodefine.h | 0 .../device/inc/iodefines/ieb_iodefine.h | 0 .../device/inc/iodefines/inb_iodefine.h | 0 .../device/inc/iodefines/intc_iodefine.h | 0 .../device/inc/iodefines/iodefine_typedef.h | 0 .../device/inc/iodefines/irda_iodefine.h | 0 .../device/inc/iodefines/jcu_iodefine.h | 0 .../device/inc/iodefines/l2c_iodefine.h | 0 .../device/inc/iodefines/lin_iodefine.h | 0 .../device/inc/iodefines/lvds_iodefine.h | 0 .../device/inc/iodefines/mlb_iodefine.h | 0 .../device/inc/iodefines/mmc_iodefine.h | 0 .../device/inc/iodefines/mtu2_iodefine.h | 0 .../device/inc/iodefines/ostm_iodefine.h | 0 .../device/inc/iodefines/pfv_iodefine.h | 0 .../device/inc/iodefines/pwm_iodefine.h | 0 .../device/inc/iodefines/riic_iodefine.h | 0 .../device/inc/iodefines/romdec_iodefine.h | 0 .../device/inc/iodefines/rscan0_iodefine.h | 0 .../device/inc/iodefines/rspi_iodefine.h | 0 .../device/inc/iodefines/rtc_iodefine.h | 0 .../device/inc/iodefines/scif_iodefine.h | 0 .../device/inc/iodefines/scim_iodefine.h | 0 .../device/inc/iodefines/scux_iodefine.h | 0 .../device/inc/iodefines/sdg_iodefine.h | 0 .../device/inc/iodefines/spdif_iodefine.h | 0 .../device/inc/iodefines/spibsc_iodefine.h | 0 .../device/inc/iodefines/ssif_iodefine.h | 0 .../device/inc/iodefines/usb20_iodefine.h | 0 .../device/inc/iodefines/vdc5_iodefine.h | 0 .../device/inc/iodefines/wdt_iodefine.h | 0 .../TARGET_RZ_A1H/device/inc/reg32_t.h | 0 .../TARGET_RZ_A1H/device/mbed_sf_boot.c | 0 .../TARGET_RZ_A1H/device/mmu_RZ_A1H.c | 0 .../TARGET_RZ_A1H/device/nvic_wrapper.c | 0 .../TARGET_RZ_A1H/device/os_tick_ostm.c | 0 .../TARGET_RZ_A1H/device/system_RZ_A1H.c | 0 .../TARGET_RZ_A1H/device/system_RZ_A1H.h | 0 .../TARGET_RZ_A1H/ethernet_api.c | 0 .../TARGET_RZ_A1H/gpio_api.c | 0 .../TARGET_RZ_A1H/gpio_irq_api.c | 0 .../TARGET_RZ_A1H/i2c_api.c | 0 .../TARGET_RZ_A1H/objects.h | 0 .../TARGET_RZ_A1H/pinmap.c | 0 .../TARGET_RZ_A1H/port_api.c | 0 .../TARGET_RZ_A1H/pwmout_api.c | 0 .../TARGET_RZ_A1H/rtc_api.c | 0 .../TARGET_RZ_A1H/serial_api.c | 0 .../TARGET_RZ_A1H/spi_api.c | 0 .../TARGET_RZ_A1H/us_ticker.c | 0 .../TARGET_VK_RZ_A1H/PeripheralNames.h | 0 .../TARGET_VK_RZ_A1H/PinNames.h | 0 .../TARGET_VK_RZ_A1H/PortNames.h | 0 .../TARGET_MBED_VKRZA1H/reserved_pins.h | 0 .../TARGET_VK_RZ_A1H/analogin_api.c | 0 .../TARGET_VK_RZ_A1H/can_api.c | 0 .../TARGET_VK_RZ_A1H/device.h | 0 .../TARGET_VK_RZ_A1H/device/RZ_A1_Init.c | 0 .../device/TOOLCHAIN_ARM_STD/VKRZA1H.sct | 0 .../TOOLCHAIN_ARM_STD/startup_VKRZA1H.S | 0 .../device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S | 0 .../device/TOOLCHAIN_IAR/VKRZA1H.icf | 0 .../device/TOOLCHAIN_IAR/startup_VKRZA1H.S | 0 .../TARGET_VK_RZ_A1H/device/VKRZA1H.h | 0 .../TARGET_VK_RZ_A1H/device/cmsis.h | 0 .../TARGET_VK_RZ_A1H/device/cmsis_nvic.c | 0 .../TARGET_VK_RZ_A1H/device/gic.c | 0 .../TARGET_VK_RZ_A1H/device/gic.h | 0 .../device/inc/iobitmasks/bsc_iobitmask.h | 0 .../device/inc/iobitmasks/cpg_iobitmask.h | 0 .../device/inc/iobitmasks/dmac_iobitmask.h | 0 .../device/inc/iobitmasks/gpio_iobitmask.h | 0 .../device/inc/iobitmasks/intc_iobitmask.h | 0 .../device/inc/iobitmasks/mtu2_iobitmask.h | 0 .../device/inc/iobitmasks/ostm_iobitmask.h | 0 .../device/inc/iobitmasks/riic_iobitmask.h | 0 .../device/inc/iobitmasks/rspi_iobitmask.h | 0 .../device/inc/iobitmasks/scif_iobitmask.h | 0 .../device/inc/iobitmasks/usb_iobitmask.h | 0 .../TARGET_VK_RZ_A1H/device/inc/iodefine.h | 0 .../device/inc/iodefines/adc_iodefine.h | 0 .../device/inc/iodefines/bsc_iodefine.h | 0 .../device/inc/iodefines/ceu_iodefine.h | 0 .../device/inc/iodefines/cpg_iodefine.h | 0 .../device/inc/iodefines/disc_iodefine.h | 0 .../device/inc/iodefines/dmac_iodefine.h | 0 .../device/inc/iodefines/dvdec_iodefine.h | 0 .../device/inc/iodefines/ether_iodefine.h | 0 .../device/inc/iodefines/flctl_iodefine.h | 0 .../device/inc/iodefines/gpio_iodefine.h | 0 .../device/inc/iodefines/ieb_iodefine.h | 0 .../device/inc/iodefines/inb_iodefine.h | 0 .../device/inc/iodefines/intc_iodefine.h | 0 .../device/inc/iodefines/irda_iodefine.h | 0 .../device/inc/iodefines/jcu_iodefine.h | 0 .../device/inc/iodefines/l2c_iodefine.h | 0 .../device/inc/iodefines/lin_iodefine.h | 0 .../device/inc/iodefines/lvds_iodefine.h | 0 .../device/inc/iodefines/mlb_iodefine.h | 0 .../device/inc/iodefines/mmc_iodefine.h | 0 .../device/inc/iodefines/mtu2_iodefine.h | 0 .../device/inc/iodefines/ostm_iodefine.h | 0 .../device/inc/iodefines/pfv_iodefine.h | 0 .../device/inc/iodefines/pwm_iodefine.h | 0 .../device/inc/iodefines/riic_iodefine.h | 0 .../device/inc/iodefines/romdec_iodefine.h | 0 .../device/inc/iodefines/rscan0_iodefine.h | 0 .../device/inc/iodefines/rspi_iodefine.h | 0 .../device/inc/iodefines/rtc_iodefine.h | 0 .../device/inc/iodefines/scif_iodefine.h | 0 .../device/inc/iodefines/scim_iodefine.h | 0 .../device/inc/iodefines/scux_iodefine.h | 0 .../device/inc/iodefines/sdg_iodefine.h | 0 .../device/inc/iodefines/spdif_iodefine.h | 0 .../device/inc/iodefines/spibsc_iodefine.h | 0 .../device/inc/iodefines/ssif_iodefine.h | 0 .../device/inc/iodefines/usb20_iodefine.h | 0 .../device/inc/iodefines/vdc5_iodefine.h | 0 .../device/inc/iodefines/wdt_iodefine.h | 0 .../TARGET_VK_RZ_A1H/device/inc/reg32_t.h | 0 .../device/mmu_Renesas_RZ_A1.c | 0 .../TARGET_VK_RZ_A1H/device/nvic_wrapper.c | 0 .../TARGET_VK_RZ_A1H/device/pl310.c | 0 .../TARGET_VK_RZ_A1H/device/pl310.h | 0 .../TARGET_VK_RZ_A1H/device/system_VKRZA1H.c | 0 .../TARGET_VK_RZ_A1H/device/system_VKRZA1H.h | 0 .../TARGET_VK_RZ_A1H/ethernet_api.c | 0 .../TARGET_VK_RZ_A1H/gpio_api.c | 0 .../TARGET_VK_RZ_A1H/gpio_irq_api.c | 0 .../TARGET_VK_RZ_A1H/i2c_api.c | 0 .../TARGET_VK_RZ_A1H/objects.h | 0 .../TARGET_VK_RZ_A1H/pinmap.c | 0 .../TARGET_VK_RZ_A1H/port_api.c | 0 .../TARGET_VK_RZ_A1H/pwmout_api.c | 0 .../TARGET_VK_RZ_A1H/rtc_api.c | 0 .../TARGET_VK_RZ_A1H/serial_api.c | 0 .../TARGET_VK_RZ_A1H/spi_api.c | 0 .../TARGET_VK_RZ_A1H/us_ticker.c | 0 .../common}/RZ_A1_Init.h | 0 .../common}/cmsis_nvic.h | 0 .../common}/dev_drv.h | 0 .../common}/nvic_wrapper.h | 0 .../common}/r_typedefs.h | 16 +- .../common}/rza_io_regrw.c | 0 .../common}/rza_io_regrw.h | 0 .../common}/vfp_neon_push_pop.h | 0 .../ethernetext_api.h | 0 .../gpio_addrdefine.h | 0 .../gpio_object.h | 0 .../TARGET_VK_RZ_A1H/device/RZ_A1_Init.h | 71 ------- .../TARGET_VK_RZ_A1H/device/cmsis_nvic.h | 48 ----- .../TARGET_VK_RZ_A1H/device/dev_drv.h | 85 -------- .../device/inc/rza_io_regrw.h | 83 -------- .../TARGET_VK_RZ_A1H/device/nvic_wrapper.h | 84 -------- .../TARGET_VK_RZ_A1H/device/r_typedefs.h | 61 ------ .../TARGET_VK_RZ_A1H/device/rza_io_regrw.c | 200 ------------------ .../TARGET_VK_RZ_A1H/ethernetext_api.h | 20 -- .../TARGET_VK_RZ_A1H/gpio_addrdefine.h | 22 -- .../TARGET_VK_RZ_A1H/gpio_object.h | 51 ----- 201 files changed, 8 insertions(+), 733 deletions(-) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/PeripheralNames.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/PinNames.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/PortNames.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/analogin_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/can_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/MBRZA1H.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/RZ_A1_Init.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/cmsis.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/cmsis_nvic.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/RZ_A1H.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/inc/reg32_t.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/mbed_sf_boot.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/mmu_RZ_A1H.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/nvic_wrapper.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/os_tick_ostm.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/system_RZ_A1H.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/device/system_RZ_A1H.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/ethernet_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/gpio_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/gpio_irq_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/i2c_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/objects.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/pinmap.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/port_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/pwmout_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/rtc_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/serial_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/spi_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_RZ_A1H/us_ticker.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/PeripheralNames.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/PinNames.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/PortNames.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/analogin_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/can_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/VKRZA1H.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/cmsis.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/cmsis_nvic.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/gic.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/gic.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/inc/reg32_t.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/nvic_wrapper.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/pl310.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/pl310.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/ethernet_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/gpio_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/gpio_irq_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/i2c_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/objects.h (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/pinmap.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/port_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/pwmout_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/rtc_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/serial_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/spi_api.c (100%) rename targets/TARGET_RENESAS/{ => TARGET_RZ_A1XX}/TARGET_VK_RZ_A1H/us_ticker.c (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device => TARGET_RZ_A1XX/common}/RZ_A1_Init.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device => TARGET_RZ_A1XX/common}/cmsis_nvic.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device => TARGET_RZ_A1XX/common}/dev_drv.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device => TARGET_RZ_A1XX/common}/nvic_wrapper.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device => TARGET_RZ_A1XX/common}/r_typedefs.h (98%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device => TARGET_RZ_A1XX/common}/rza_io_regrw.c (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device/inc => TARGET_RZ_A1XX/common}/rza_io_regrw.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H/device => TARGET_RZ_A1XX/common}/vfp_neon_push_pop.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H => TARGET_RZ_A1XX}/ethernetext_api.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H => TARGET_RZ_A1XX}/gpio_addrdefine.h (100%) rename targets/TARGET_RENESAS/{TARGET_RZ_A1H => TARGET_RZ_A1XX}/gpio_object.h (100%) delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/dev_drv.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/rza_io_regrw.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/r_typedefs.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/rza_io_regrw.c delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h delete mode 100644 targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PinNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PinNames.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/analogin_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/analogin_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/can_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/can_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/MBRZA1H.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/MBRZA1H.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/RZ_A1_Init.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/RZ_A1_Init.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/MBRZA1H.icf diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis_nvic.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/cmsis_nvic.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/RZ_A1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/reg32_t.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/reg32_t.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/reg32_t.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/reg32_t.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mbed_sf_boot.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/mmu_RZ_A1H.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/nvic_wrapper.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/nvic_wrapper.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/os_tick_ostm.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_RZ_A1H.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_RZ_A1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/ethernet_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/ethernet_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_irq_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_irq_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/i2c_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/i2c_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/objects.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/objects.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pwmout_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pwmout_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/serial_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/serial_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/spi_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/spi_api.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/us_ticker.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/us_ticker.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PinNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PinNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/PortNames.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/analogin_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/analogin_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/VKRZA1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/gic.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/dmac_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/gpio_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/intc_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/mtu2_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/reg32_t.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/reg32_t.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/pl310.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/ethernet_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/ethernet_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_irq_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_irq_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/objects.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/objects.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/port_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/port_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pwmout_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pwmout_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/rtc_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/rtc_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/serial_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/serial_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/us_ticker.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/us_ticker.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/RZ_A1_Init.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/RZ_A1_Init.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/RZ_A1_Init.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/cmsis_nvic.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis_nvic.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/cmsis_nvic.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/dev_drv.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/dev_drv.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/dev_drv.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/dev_drv.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/nvic_wrapper.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/nvic_wrapper.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/nvic_wrapper.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/r_typedefs.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/r_typedefs.h similarity index 98% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/r_typedefs.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/r_typedefs.h index 188c22218d..158c75cf54 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/r_typedefs.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/r_typedefs.h @@ -35,18 +35,18 @@ Includes , "Project Includes" #include #include #include - #if defined(__ARM_NEON__) - #include - -#else /* __ARM_NEON__ */ - -typedef float float32_t; -typedef double float64_t; - #endif /* __ARM_NEON__ */ +#ifndef float32_t +typedef float float32_t; +#endif +#ifndef float64_t +typedef double float64_t; +#endif + + /****************************************************************************** Typedef definitions ******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/rza_io_regrw.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.c similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/rza_io_regrw.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.c diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/rza_io_regrw.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/rza_io_regrw.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/rza_io_regrw.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/vfp_neon_push_pop.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/common/vfp_neon_push_pop.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernetext_api.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernetext_api.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/ethernetext_api.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernetext_api.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_addrdefine.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_addrdefine.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_object.h similarity index 100% rename from targets/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_object.h diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.h deleted file mode 100644 index 323884e05e..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/RZ_A1_Init.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** -* @file RZ_A1_Init.h -* $Rev: 531 $ -* $Date:: 2013-04-16 13:07:35 +0900#$ -* @brief RZ_A1 Initialize -******************************************************************************/ - -#ifndef RZ_A1_INIT_H -#define RZ_A1_INIT_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include -#include -#include "iodefine.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - -/****************************************************************************** -Macro definitions -******************************************************************************/ - -/****************************************************************************** -Variable Externs -******************************************************************************/ - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ - -void RZ_A1_SetSramWriteEnable(void); -void RZ_A1_InitClock(void); -int RZ_A1_IsClockMode0(void); -void RZ_A1_InitBus(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* RZ_A1_INIT_H */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.h deleted file mode 100644 index aa87423909..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/cmsis_nvic.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2015 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/dev_drv.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/dev_drv.h deleted file mode 100644 index deb2ebbc13..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/dev_drv.h +++ /dev/null @@ -1,85 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/****************************************************************************** -* File Name : dev_drv.h -* $Rev: 809 $ -* $Date:: 2014-04-09 15:06:36 +0900#$ -* Description : Device driver header -******************************************************************************/ -#ifndef DEV_DRV_H -#define DEV_DRV_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ - - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - - -/****************************************************************************** -Macro definitions -******************************************************************************/ -/* ==== Arguments, Return values ==== */ -#define DEVDRV_SUCCESS (0) /* Success */ -#define DEVDRV_ERROR (-1) /* Failure */ - -/* ==== Flags ==== */ -#define DEVDRV_FLAG_OFF (0) /* Flag OFF */ -#define DEVDRV_FLAG_ON (1) /* Flag ON */ - -/* ==== Channels ==== */ -typedef enum devdrv_ch -{ - DEVDRV_CH_0, /* Channel 0 */ - DEVDRV_CH_1, /* Channel 1 */ - DEVDRV_CH_2, /* Channel 2 */ - DEVDRV_CH_3, /* Channel 3 */ - DEVDRV_CH_4, /* Channel 4 */ - DEVDRV_CH_5, /* Channel 5 */ - DEVDRV_CH_6, /* Channel 6 */ - DEVDRV_CH_7, /* Channel 7 */ - DEVDRV_CH_8, /* Channel 8 */ - DEVDRV_CH_9, /* Channel 9 */ - DEVDRV_CH_10, /* Channel 10 */ - DEVDRV_CH_11, /* Channel 11 */ - DEVDRV_CH_12, /* Channel 12 */ - DEVDRV_CH_13, /* Channel 13 */ - DEVDRV_CH_14, /* Channel 14 */ - DEVDRV_CH_15 /* Channel 15 */ -} devdrv_ch_t; - -/****************************************************************************** -Variable Externs -******************************************************************************/ - - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ - -#endif /* DEV_DRV_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/rza_io_regrw.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/rza_io_regrw.h deleted file mode 100644 index 5f0fec64dd..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/inc/rza_io_regrw.h +++ /dev/null @@ -1,83 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rza_io_regrw.h -* $Rev: 1135 $ -* $Date:: 2014-08-08 10:11:30 +0900#$ -* Description : Low level register read/write header -*******************************************************************************/ -#ifndef RZA_IO_REGRW_H -#define RZA_IO_REGRW_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -/* ==== includes each bit mask header ==== */ -#include "cpg_iobitmask.h" -#include "intc_iobitmask.h" -#include "bsc_iobitmask.h" -#include "dmac_iobitmask.h" -#include "mtu2_iobitmask.h" -#include "ostm_iobitmask.h" -#include "scif_iobitmask.h" -#include "rspi_iobitmask.h" -#include "riic_iobitmask.h" -#include "usb_iobitmask.h" -#include "gpio_iobitmask.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - - -/****************************************************************************** -Macro definitions -******************************************************************************/ - - -/****************************************************************************** -Variable Externs -******************************************************************************/ - - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ -void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask); -void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask); -void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask); -uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint8_t mask); -uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask); -uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask); - -#ifdef __cplusplus -} -#endif - -#endif /* RZA_IO_REGRW_H */ - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.h deleted file mode 100644 index fcdf554bb8..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/nvic_wrapper.h +++ /dev/null @@ -1,84 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** -* @file nvic_wrapper.h -* $Rev: $ -* $Date:: $ -* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) -******************************************************************************/ - -#ifndef NVIC_WRAPPER_H -#define NVIC_WRAPPER_H - - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - -/****************************************************************************** -Macro definitions -******************************************************************************/ - -/****************************************************************************** -Variable Externs -******************************************************************************/ - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ - -/* NVIC functions */ -void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -uint32_t NVIC_GetPriorityGrouping(void); -void NVIC_EnableIRQ(IRQn_Type IRQn); -void NVIC_DisableIRQ(IRQn_Type IRQn); -uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); -void NVIC_SetPendingIRQ(IRQn_Type IRQn); -void NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t NVIC_GetActive(IRQn_Type IRQn); -void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); -uint32_t NVIC_GetPriority(IRQn_Type IRQn); -uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); -void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -void NVIC_SystemReset(void); -/* SysTick function */ -uint32_t SysTick_Config(uint32_t ticks); -/* Debug In/Output function */ -uint32_t ITM_SendChar (uint32_t ch); -int32_t ITM_ReceiveChar (void); -int32_t ITM_CheckChar (void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* NVIC_WRAPPER_H */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/r_typedefs.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/r_typedefs.h deleted file mode 100644 index 188c22218d..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/r_typedefs.h +++ /dev/null @@ -1,61 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : r_typedefs.h -* $Rev: 788 $ -* $Date:: 2014-04-07 18:57:13 +0900#$ -* Description : basic type definition -******************************************************************************/ -#ifndef R_TYPEDEFS_H -#define R_TYPEDEFS_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include -#include -#include - -#if defined(__ARM_NEON__) - -#include - -#else /* __ARM_NEON__ */ - -typedef float float32_t; -typedef double float64_t; - -#endif /* __ARM_NEON__ */ - -/****************************************************************************** -Typedef definitions -******************************************************************************/ -typedef char char_t; -typedef int bool_t; -typedef int int_t; -typedef long double float128_t; -typedef signed long long_t; -typedef unsigned long ulong_t; - -#endif /* R_TYPEDEFS_H */ - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/rza_io_regrw.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/rza_io_regrw.c deleted file mode 100644 index f919fa8c8b..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/rza_io_regrw.c +++ /dev/null @@ -1,200 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* File Name : rza_io_regrw.c -* $Rev: 1121 $ -* $Date:: 2014-08-06 17:09:53 +0900#$ -* Description : Low level register read/write -*******************************************************************************/ - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ -#include "r_typedefs.h" - -#ifdef __CC_ARM -#pragma arm section code = "CODE_IO_REGRW" -#pragma arm section rodata = "CONST_IO_REGRW" -#pragma arm section rwdata = "DATA_IO_REGRW" -#pragma arm section zidata = "BSS_IO_REGRW" -#endif - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - - -/****************************************************************************** -Macro definitions -******************************************************************************/ - - -/****************************************************************************** -Imported global variables and functions (from other files) -******************************************************************************/ - - -/****************************************************************************** -Exported global variables and functions (to be accessed by other files) -******************************************************************************/ - - -/****************************************************************************** -Private global variables and functions -******************************************************************************/ - - -/****************************************************************************** -* Function Name: RZA_IO_RegWrite_8 -* Description : IO register 8-bit write -* Arguments : volatile uint8_t * ioreg : IO register for writing -* : : Use register definition name of the -* : : iodefine.h -* : uint8_t write_value : Write value for the IO register -* : uint8_t shift : The number of left shifts to the -* : : target bit -* : uint8_t mask : Mask value for the IO register -* : : (Target bit : "1") -* Return Value : None -******************************************************************************/ -void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask) -{ - uint8_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ - *ioreg = reg_value; /* Write to register */ -} - -/****************************************************************************** -* Function Name: RZA_IO_RegWrite_16 -* Description : IO register 16-bit write -* Arguments : volatile uint16_t * ioreg : IO register for writing -* : : Use register definition name of the -* : : iodefine.h -* : uint16_t write_value : Write value for the IO register -* : uint16_t shift : The number of left shifts to the -* : : target bit -* : uint16_t mask : Mask value for the IO register -* : : (Target bit : "1") -* Return Value : None -******************************************************************************/ -void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask) -{ - uint16_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ - *ioreg = reg_value; /* Write to register */ -} - -/****************************************************************************** -* Function Name: RZA_IO_RegWrite_32 -* Description : IO register 32-bit write -* Arguments : volatile uint32_t * ioreg : IO register for writing -* : : Use register definition name of the -* : : iodefine.h -* : uint32_t write_value : Write value for the IO register -* : uint32_t shift : The number of left shifts to the -* : : target bit -* : uint32_t mask : Mask value for the IO register -* : : (Target bit : "1") -* Return Value : None -******************************************************************************/ -void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) -{ - uint32_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ - *ioreg = reg_value; /* Write to register */ -} - -/****************************************************************************** -* Function Name: RZA_IO_RegRead_8 -* Description : IO register 8-bit read -* Arguments : volatile uint8_t * ioreg : IO register for reading -* : : Use register definition name of the -* : : iodefine.h -* : uint8_t shift : The number of right shifts to the -* : : target bit -* : uint8_t mask : Mask bit for the IO register -* : : (Target bit: "1") -* Return Value : uint8_t : Value of the obtained target bit -******************************************************************************/ -uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask) -{ - uint8_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ - - return reg_value; -} - -/****************************************************************************** -* Function Name: RZA_IO_RegRead_16 -* Description : IO register 16-bit read -* Arguments : volatile uint16_t * ioreg : IO register for reading -* : : Use register definition name of the -* : : iodefine.h -* : uint16_t shift : The number of right shifts to the -* : : target bit -* : uint16_t mask : Mask bit for the IO register -* : : (Target bit: "1") -* Return Value : uint16_t : Value of the obtained target bit -******************************************************************************/ -uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask) -{ - uint16_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ - - return reg_value; -} - -/****************************************************************************** -* Function Name: RZA_IO_RegRead_32 -* Description : IO register 32-bit read -* Arguments : volatile uint32_t * ioreg : IO register for reading -* : : Use register definition name of the -* : : iodefine.h -* : uint32_t shift : The number of right shifts to the -* : : target bit -* : uint32_t mask : Mask bit for the IO register -* : : (Target bit: "1") -* Return Value : uint32_t : Value of the obtained target bit -******************************************************************************/ -uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask) -{ - uint32_t reg_value; - - reg_value = *ioreg; /* Read from register */ - reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ - - return reg_value; -} - - -/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h deleted file mode 100644 index 18dfa2109e..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h +++ /dev/null @@ -1,20 +0,0 @@ - -/* PHY link mode */ -#define NEGO_FAIL (0) -#define HALF_10M (1) -#define FULL_10M (2) -#define HALF_TX (3) -#define FULL_TX (4) - -typedef void (ethernetext_cb_fnc)(void); - -typedef struct tag_ethernet_cfg { - int int_priority; - ethernetext_cb_fnc *recv_cb; - char *ether_mac; -} ethernet_cfg_t; - -extern int ethernetext_init(ethernet_cfg_t *p_ethcfg); -extern void ethernetext_start_stop(int32_t mode); -extern int ethernetext_chk_link_mode(void); -extern void ethernetext_set_link_mode(int32_t link); diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h deleted file mode 100644 index 3865c03ec2..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef __GPIO_ADDRDEFINE__ -#define __GPIO_ADDRDEFINE__ - -#define GPIO_BASE ((long)0xFCFE3000uL) /* GPIO */ - -#define PORT(n) (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4)) -#define PSR(n) (volatile unsigned long *)(GPIO_BASE + 0x100 + ((n)*4)) -#define PPR(n) (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4)) -#define PM(n) (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4)) -#define PMC(n) (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4)) -#define PFC(n) (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4)) -#define PFCE(n) (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4)) -#define PNOT(n) (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4)) -#define PMSR(n) (volatile unsigned long *)(GPIO_BASE + 0x800 + ((n)*4)) -#define PMCSR(n) (volatile unsigned long *)(GPIO_BASE + 0x900 + ((n)*4)) -#define PFCAE(n) (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4)) -#define PIBC(n) (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4)) -#define PBDC(n) (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4)) -#define PIPC(n) (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4)) - -#endif/*__GPIO_ADDRDEFINE__*/ - diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h deleted file mode 100644 index 211a4c870d..0000000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h +++ /dev/null @@ -1,51 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __I uint32_t *reg_in; - __IO uint32_t *reg_buf; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0); -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif From 73a5c55010985d1636e9945d957172c076022d34 Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Tue, 9 Jan 2018 18:20:50 +0900 Subject: [PATCH 127/133] Commonalize the files in "targets/TARGET_RENESAS/TARGET_RZ_A1XX" directory I made be available in common whatever the board related to RZ_A1 in the below files. - Since there are the table code of Pinmap differs for each board, I moved the code to "PeripheralPins" file for each board, and changed to include PeripheralPins.h. analogin_api.c, can_api.c, gpio_irq_api.c, i2c_api.c, pinmap.c, port_api.c, pwmout_api.c, serial_api.c, spi_api.c and us_ticker.c - Since there are some board-specific processes, I enclosed the processes with "#ifdef" and rearranged the functions to make be easier to enclose. can_api.c, ethernet_api.c and serial_api.c - Since there are the driver configuration values differs for each board, I added "mbed_drv_cfg.h" file for each board and defined macros for the values, and changed to refer to the macros. can_api.c, gpio_api.c, pwmout_api.c and rtc_api.c --- .../TARGET_RZ_A1XX/PeripheralPins.h | 64 + .../TARGET_RZ_A1H/PeripheralNames.h | 106 +- .../TARGET_RZ_A1H/PeripheralPins.c | 343 ++++++ .../TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h | 9 +- .../TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c | 57 - .../TARGET_RZ_A1H/mbed_drv_cfg.h | 19 + .../TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h | 84 -- .../TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c | 172 --- .../TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c | 65 - .../TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c | 378 ------ .../TARGET_VK_RZ_A1H/PeripheralNames.h | 129 +- .../TARGET_VK_RZ_A1H/PeripheralPins.c | 540 +++++++++ .../TARGET_VK_RZ_A1H/analogin_api.c | 133 --- .../TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c | 1042 ----------------- .../TARGET_VK_RZ_A1H/ethernet_api.c | 695 ----------- .../TARGET_VK_RZ_A1H/gpio_irq_api.c | 223 ---- .../TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c | 760 ------------ .../TARGET_VK_RZ_A1H/mbed_drv_cfg.h | 19 + .../TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c | 192 --- .../TARGET_VK_RZ_A1H/pwmout_api.c | 700 ----------- .../TARGET_VK_RZ_A1H/serial_api.c | 672 ----------- .../TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c | 343 ------ .../TARGET_VK_RZ_A1H/us_ticker.c | 136 --- .../{TARGET_RZ_A1H => }/analogin_api.c | 17 +- .../{TARGET_RZ_A1H => }/can_api.c | 349 +++--- .../{TARGET_RZ_A1H => }/ethernet_api.c | 41 +- .../{TARGET_VK_RZ_A1H => }/gpio_api.c | 3 +- .../{TARGET_RZ_A1H => }/gpio_irq_api.c | 40 +- .../{TARGET_RZ_A1H => }/i2c_api.c | 21 +- .../{TARGET_VK_RZ_A1H => }/objects.h | 2 +- .../TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c | 74 ++ .../{TARGET_VK_RZ_A1H => }/port_api.c | 25 +- .../{TARGET_RZ_A1H => }/pwmout_api.c | 270 ++--- .../{TARGET_VK_RZ_A1H => }/rtc_api.c | 11 +- .../{TARGET_RZ_A1H => }/serial_api.c | 417 +++---- .../{TARGET_RZ_A1H => }/spi_api.c | 131 +-- .../{TARGET_RZ_A1H => }/us_ticker.c | 4 +- 37 files changed, 1699 insertions(+), 6587 deletions(-) create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/analogin_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/ethernet_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_irq_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pwmout_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/serial_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/us_ticker.c rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/analogin_api.c (89%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/can_api.c (95%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/ethernet_api.c (95%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_VK_RZ_A1H => }/gpio_api.c (96%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/gpio_irq_api.c (77%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/i2c_api.c (98%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_VK_RZ_A1H => }/objects.h (98%) create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_VK_RZ_A1H => }/port_api.c (86%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/pwmout_api.c (71%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_VK_RZ_A1H => }/rtc_api.c (98%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/serial_api.c (77%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/spi_api.c (89%) rename targets/TARGET_RENESAS/TARGET_RZ_A1XX/{TARGET_RZ_A1H => }/us_ticker.c (98%) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h new file mode 100644 index 0000000000..e25ceb20e1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +typedef struct { + PinName pin; + int function; + int pm; +} PinFunc; + +/************IRQ***************/ +extern const PinMap PinMap_IRQ[]; + +/************PINMAP***************/ +extern const PinFunc PIPC_0_tbl[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************CAN***************/ +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h index a1a385b36d..58806d5257 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h @@ -34,82 +34,31 @@ typedef enum { UART7, } UARTName; -// PWMType & 1 == 1 then have to use PWDTR[12] == 1 typedef enum { - PWM1A = 0, - PWM1B, - PWM1C, - PWM1D, - PWM1E, - PWM1F, - PWM1G, - PWM1H, - PWM2A = 0x10, - PWM2B, - PWM2C, - PWM2D, - PWM2E, - PWM2F, - PWM2G, - PWM2H, -} PWMType; - -typedef enum { - TIOC0A = 0, - TIOC0B, - TIOC0C, - TIOC0D, - TIOC1A = 0x10, - TIOC1B, - TIOC2A = 0x20, - TIOC2B, - TIOC3A = 0x30, - TIOC3B, - TIOC3C, - TIOC3D, - TIOC4A = 0x40, - TIOC4B, - TIOC4C, - TIOC4D, -} MTU2_PWMType; - -typedef enum { - PWM0_PIN = 0, - PWM1_PIN, - PWM2_PIN, - PWM3_PIN, - PWM4_PIN, - PWM5_PIN, - PWM6_PIN, - PWM7_PIN, - PWM8_PIN, - PWM9_PIN, - PWM10_PIN, - PWM11_PIN, - PWM12_PIN, - PWM13_PIN, - MTU2_PWM0_PIN = 0x20, - MTU2_PWM1_PIN, - MTU2_PWM2_PIN, - MTU2_PWM3_PIN, - MTU2_PWM4_PIN, - MTU2_PWM5_PIN, - MTU2_PWM6_PIN, - MTU2_PWM7_PIN, - MTU2_PWM8_PIN, - MTU2_PWM9_PIN, - MTU2_PWM10_PIN, - MTU2_PWM11_PIN, - MTU2_PWM12_PIN, - MTU2_PWM13_PIN, - MTU2_PWM14_PIN, - MTU2_PWM15_PIN, - MTU2_PWM16_PIN, - MTU2_PWM17_PIN, - MTU2_PWM18_PIN, - MTU2_PWM19_PIN, - MTU2_PWM20_PIN, - MTU2_PWM21_PIN, + PWM_PWM1A = 0, + PWM_PWM1B, + PWM_PWM1C, + PWM_PWM1D, + PWM_PWM1E, + PWM_PWM1F, + PWM_PWM1G, + PWM_PWM1H, + PWM_PWM2A, + PWM_PWM2B, + PWM_PWM2C, + PWM_PWM2D, + PWM_PWM2E, + PWM_PWM2F, + PWM_PWM2G, + PWM_PWM2H, + PWM_TIOC0A = 0x20, + PWM_TIOC0C, + PWM_TIOC1A, + PWM_TIOC2A, + PWM_TIOC3A, + PWM_TIOC3C, + PWM_TIOC4A, + PWM_TIOC4C, } PWMName; typedef enum { @@ -128,21 +77,22 @@ typedef enum { SPI_1, SPI_2, SPI_3, + SPI_4, } SPIName; typedef enum { I2C_0 = 0, I2C_1, I2C_2, - I2C_3 + I2C_3, } I2CName; typedef enum { CAN_0 = 0, CAN_1, CAN_2, - CAN_3, - CAN_4 + CAN_3, + CAN_4, } CANName; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c new file mode 100644 index 0000000000..bfc94f513a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c @@ -0,0 +1,343 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************IRQ***************/ +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, +} IRQNo; +const PinMap PinMap_IRQ[] = { + {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4}, + {P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3}, + {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11 + {P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8}, + {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16 + {P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3}, + {P3_9, IRQ6, 8}, // 20 + {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8}, + {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8}, + {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28 + {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31 + {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4}, + {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8}, + {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8}, + {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8}, + {P6_15, IRQ7, 8}, // 44 + {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8}, + {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8}, + {P7_14, IRQ6, 8}, // 51 + {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4}, + {P9_1, IRQ0, 4}, // 55 + {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57 + {NC, NC, 0} +}; + +/************PINMAP***************/ +const PinFunc PIPC_0_tbl[] = { +// pin func pm + {P4_0 , 2 , -1}, /* TIOC0A */ + {P5_0 , 6 , -1}, /* TIOC0A */ + {P7_0 , 7 , -1}, /* TIOC0A */ + {P10_4 , 2 , -1}, /* TIOC0A */ + {P4_1 , 2 , -1}, /* TIOC0B */ + {P5_1 , 6 , -1}, /* TIOC0B */ + {P7_1 , 7 , -1}, /* TIOC0B */ + {P10_5 , 2 , -1}, /* TIOC0B */ + {P4_2 , 2 , -1}, /* TIOC0C */ + {P5_5 , 6 , -1}, /* TIOC0C */ + {P7_2 , 7 , -1}, /* TIOC0C */ + {P10_6 , 2 , -1}, /* TIOC0C */ + {P4_3 , 2 , -1}, /* TIOC0D */ + {P5_7 , 6 , -1}, /* TIOC0D */ + {P7_3 , 7 , -1}, /* TIOC0D */ + {P10_7 , 2 , -1}, /* TIOC0D */ + {P2_11 , 5 , -1}, /* TIOC1A */ + {P6_0 , 5 , -1}, /* TIOC1A */ + {P7_4 , 7 , -1}, /* TIOC1A */ + {P8_8 , 5 , -1}, /* TIOC1A */ + {P9_7 , 4 , -1}, /* TIOC1A */ + {P10_8 , 2 , -1}, /* TIOC1A */ + {P2_12 , 8 , -1}, /* TIOC1B */ + {P5_2 , 6 , -1}, /* TIOC1B */ + {P6_1 , 5 , -1}, /* TIOC1B */ + {P7_5 , 7 , -1}, /* TIOC1B */ + {P8_9 , 5 , -1}, /* TIOC1B */ + {P10_9 , 2 , -1}, /* TIOC1B */ + {P2_1 , 6 , -1}, /* TIOC2A */ + {P6_2 , 6 , -1}, /* TIOC2A */ + {P7_6 , 7 , -1}, /* TIOC2A */ + {P8_14 , 4 , -1}, /* TIOC2A */ + {P10_10 , 2 , -1}, /* TIOC2A */ + {P2_2 , 6 , -1}, /* TIOC2B */ + {P6_3 , 6 , -1}, /* TIOC2B */ + {P7_7 , 7 , -1}, /* TIOC2B */ + {P8_15 , 4 , -1}, /* TIOC2B */ + {P10_11 , 2 , -1}, /* TIOC2B */ + {P10_11 , 2 , -1}, /* TIOC2B */ + {P3_4 , 6 , -1}, /* TIOC3A */ + {P7_8 , 7 , -1}, /* TIOC3A */ + {P8_10 , 4 , -1}, /* TIOC3A */ + {P3_5 , 6 , -1}, /* TIOC3B */ + {P7_9 , 7 , -1}, /* TIOC3B */ + {P8_11 , 4 , -1}, /* TIOC3B */ + {P3_6 , 6 , -1}, /* TIOC3C */ + {P5_3 , 6 , -1}, /* TIOC3C */ + {P7_10 , 7 , -1}, /* TIOC3C */ + {P8_12 , 4 , -1}, /* TIOC3C */ + {P3_7 , 6 , -1}, /* TIOC3D */ + {P5_4 , 6 , -1}, /* TIOC3D */ + {P7_11 , 7 , -1}, /* TIOC3D */ + {P8_13 , 4 , -1}, /* TIOC3D */ + {P3_8 , 6 , -1}, /* TIOC4A */ + {P4_4 , 3 , -1}, /* TIOC4A */ + {P7_12 , 7 , -1}, /* TIOC4A */ + {P11_0 , 2 , -1}, /* TIOC4A */ + {P3_9 , 6 , -1}, /* TIOC4B */ + {P4_5 , 3 , -1}, /* TIOC4B */ + {P7_13 , 7 , -1}, /* TIOC4B */ + {P11_1 , 2 , -1}, /* TIOC4B */ + {P3_10 , 6 , -1}, /* TIOC4C */ + {P4_6 , 3 , -1}, /* TIOC4C */ + {P7_14 , 7 , -1}, /* TIOC4C */ + {P11_2 , 2 , -1}, /* TIOC4C */ + {P3_11 , 6 , -1}, /* TIOC4D */ + {P4_7 , 3 , -1}, /* TIOC4D */ + {P7_15 , 7 , -1}, /* TIOC4D */ + {P11_3 , 2 , -1}, /* TIOC4D */ + {P5_7 , 1 , 1 }, /* TXOUT0M */ + {P5_6 , 1 , 1 }, /* TXOUT0P */ + {P5_5 , 1 , 1 }, /* TXOUT1M */ + {P5_4 , 1 , 1 }, /* TXOUT1P */ + {P5_3 , 1 , 1 }, /* TXOUT2M */ + {P5_2 , 1 , 1 }, /* TXOUT2P */ + {P5_1 , 1 , 1 }, /* TXCLKOUTM */ + {P5_0 , 1 , 1 }, /* TXCLKOUTP */ + {P2_11 , 4 , 0 }, /* SSITxD0 */ + {P4_7 , 5 , 0 }, /* SSITxD0 */ + {P7_4 , 6 , 0 }, /* SSITxD1 */ + {P10_15 , 2 , 0 }, /* SSITxD1 */ + {P4_15 , 6 , 0 }, /* SSITxD3 */ + {P7_11 , 2 , 0 }, /* SSITxD3 */ + {P2_7 , 4 , 0 }, /* SSITxD5 */ + {P4_11 , 5 , 0 }, /* SSITxD5 */ + {P8_10 , 8 , 0 }, /* SSITxD5 */ + {P3_7 , 8 , 0 }, /* WDTOVF */ + {NC , 0 , -1} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_14, AN6, 1}, + {P1_15, AN7, 1}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P1_1 , I2C_0, 1}, + {P1_3 , I2C_1, 1}, + {P1_7 , I2C_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P1_0 , I2C_0, 1}, + {P1_2 , I2C_1, 1}, + {P1_6 , I2C_3, 1}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P2_14 , UART0, 6}, + {P2_5 , UART1, 6}, + {P4_12 , UART1, 7}, + {P6_3 , UART2, 7}, + {P4_14 , UART2, 7}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P8_14 , UART4, 7}, + {P8_13 , UART5, 5}, + {P11_10, UART5, 3}, + {P6_6 , UART5, 5}, + {P5_6 , UART6, 5}, + {P11_1 , UART6, 4}, + {P7_4 , UART7, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P2_15 , UART0, 6}, + {P2_6 , UART1, 6}, + {P4_13 , UART1, 7}, + {P6_2 , UART2, 7}, + {P4_15 , UART2, 7}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P8_15 , UART4, 7}, + {P8_11 , UART5, 5}, + {P11_11, UART5, 3}, + {P6_7 , UART5, 5}, + {P5_7 , UART6, 5}, + {P11_2 , UART6, 4}, + {P7_5 , UART7, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {P2_3 , UART1, 6}, + {P11_7 , UART5, 3}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {P2_7 , UART1, 6}, + {P11_8 , UART5, 3}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P10_12, SPI_0, 4}, + {P4_4 , SPI_1, 2}, + {P6_4 , SPI_1, 7}, + {P11_12, SPI_1, 2}, + {P8_3 , SPI_2, 3}, + {P5_0 , SPI_3, 8}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P10_14, SPI_0, 4}, + {P4_6 , SPI_1, 2}, + {P6_6 , SPI_1, 7}, + {P11_14, SPI_1, 2}, + {P8_5 , SPI_2, 3}, + {P5_2 , SPI_3, 8}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P10_15, SPI_0, 4}, + {P4_7 , SPI_1, 2}, + {P6_7 , SPI_1, 7}, + {P11_15, SPI_1, 2}, + {P8_6 , SPI_2, 3}, + {P5_3 , SPI_3, 8}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P10_13, SPI_0, 4}, + {P4_5 , SPI_1, 2}, + {P6_5 , SPI_1, 7}, + {P11_13, SPI_1, 2}, + {P8_4 , SPI_2, 3}, + {P5_1 , SPI_3, 8}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P2_1 , PWM_TIOC2A, 6}, + {P2_11 , PWM_TIOC1A, 5}, + {P3_8 , PWM_TIOC4A, 6}, + {P3_10 , PWM_TIOC4C, 6}, + {P4_0 , PWM_TIOC0A, 2}, + {P4_4 , PWM_TIOC4A, 3}, + {P4_6 , PWM_TIOC4C, 3}, + {P5_0 , PWM_TIOC0A, 6}, + {P5_3 , PWM_TIOC3C, 6}, + {P5_5 , PWM_TIOC0C, 6}, + {P7_2 , PWM_TIOC0C, 7}, + {P7_4 , PWM_TIOC1A, 7}, + {P7_6 , PWM_TIOC2A, 7}, + {P7_10 , PWM_TIOC3C, 7}, + {P7_12 , PWM_TIOC4A, 7}, + {P7_14 , PWM_TIOC4C, 7}, + {P8_8 , PWM_TIOC1A, 5}, + {P8_10 , PWM_TIOC3A, 4}, + {P8_12 , PWM_TIOC3C, 4}, + {P8_14 , PWM_TIOC2A, 4}, + {P11_0 , PWM_TIOC4A, 2}, + {P11_2 , PWM_TIOC4C, 2}, + {P4_4 , PWM_PWM2E , 4}, + {P3_2 , PWM_PWM2C , 7}, + {P4_6 , PWM_PWM2G , 4}, + {P4_7 , PWM_PWM2H , 4}, + {P8_14 , PWM_PWM1G , 6}, + {P8_15 , PWM_PWM1H , 6}, + {P8_13 , PWM_PWM1F , 6}, + {P8_11 , PWM_PWM1D , 6}, + {P8_8 , PWM_PWM1A , 6}, + {P10_0 , PWM_PWM2A , 3}, + {P8_12 , PWM_PWM1E , 6}, + {P8_9 , PWM_PWM1B , 6}, + {P8_10 , PWM_PWM1C , 6}, + {P4_5 , PWM_PWM2F , 4}, + {NC , NC , 0} +}; + +/************CAN***************/ +const PinMap PinMap_CAN_RD[] = { + {P7_8 , CAN_0, 4}, + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P7_11 , CAN_1, 4}, + {P11_12, CAN_1, 1}, + {P4_9 , CAN_2, 6}, + {P6_4 , CAN_2, 3}, + {P7_2 , CAN_2, 5}, + {P2_12 , CAN_3, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {P2_14 , CAN_4, 5}, + {NC , NC , 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {P7_9 , CAN_0, 4}, + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P7_10 , CAN_1, 4}, + {P11_13, CAN_1, 1}, + {P4_8 , CAN_2, 6}, + {P6_5 , CAN_2, 3}, + {P7_3 , CAN_2, 5}, + {P2_13 , CAN_3, 5}, + {P4_3 , CAN_3, 4}, + {P4_11 , CAN_4, 6}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +}; + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h index 270cdeecb0..b5c3632705 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h @@ -25,7 +25,14 @@ typedef enum { Port1 = 1, Port2 = 2, Port3 = 3, - Port4 = 4 + Port4 = 4, + Port5 = 5, + Port6 = 6, + Port7 = 7, + Port8 = 8, + Port9 = 9, + Port10 = 10, + Port11 = 11 } PortName; #ifdef __cplusplus diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c deleted file mode 100644 index 19f7876829..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "pinmap.h" -#include "gpio_addrdefine.h" - - -uint32_t gpio_set(PinName pin) { - pin_function(pin, 0); - return (1 << PINNO(pin)); -} - -void gpio_init(gpio_t *obj, PinName pin) { - int group ; - obj->pin = pin; - if(pin == NC) return; - - obj->mask = gpio_set(pin); - - group = PINGROUP(pin); - if (group > 11) return; - - obj->reg_set = (volatile uint32_t *) PSR(group); - obj->reg_in = (volatile uint32_t *) PPR(group); - obj->reg_dir = (volatile uint32_t *)PMSR(group); - obj->reg_buf = (volatile uint32_t *)PIBC(group); -} - -void gpio_mode(gpio_t *obj, PinMode mode) { -/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */ -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - switch (direction) { - case PIN_INPUT : - *obj->reg_dir = (obj->mask << 16) | obj->mask; - *obj->reg_buf |= obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir = (obj->mask << 16) | 0; - *obj->reg_buf &= ~obj->mask; - break; - } -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h new file mode 100644 index 0000000000..1ee094dce6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h @@ -0,0 +1,19 @@ +#ifndef MBED_DRV_CFG_H +#define MBED_DRV_CFG_H + +/* can_api.c */ +#define CAN_TEST_GLOBAL_CH 1 + +/* gpio_api.c */ +#define GPIO_GROUP_MAX 11 + +/* pwmout_api.c */ +#define FUNC_MOTOR_CTL_PWM +#define FUMC_MTU2_PWM + +/* rtc_api.c */ +//#define USE_RTCX1_CLK +#define USE_EXTAL_CLK +//#define USE_RTCX3_CLK + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h deleted file mode 100644 index 3ce9e0d3c7..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "gpio_object.h" -#include "rspi_iodefine.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct i2c_s { - uint32_t i2c; - uint32_t dummy; - uint8_t pclk_bit; - uint8_t width_low; - uint8_t width_hi; - int bbsy_wait_cnt; - int last_stop_flag; -}; - -struct spi_s { - struct st_rspi *spi; - uint32_t bits; - int index; -}; - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; - uint8_t int_enable; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - PortName port; - uint32_t mask; -}; - -struct serial_s { - struct st_scif *uart; - int index; -}; - -struct pwmout_s { - uint32_t ch; - PWMName pwm; -}; - -struct analogin_s { - ADCName adc; -}; - -struct can_s { - uint32_t ch; -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c deleted file mode 100644 index a96727e9b2..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c +++ /dev/null @@ -1,172 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_addrdefine.h" - -PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ - -typedef struct { - PinName pin; - int function; - int pm; -} PinFunc; - -static const PinFunc PIPC_0_tbl[] = { -// pin func pm - {P4_0 , 2 , -1}, /* TIOC0A */ - {P5_0 , 6 , -1}, /* TIOC0A */ - {P7_0 , 7 , -1}, /* TIOC0A */ - {P10_4 , 2 , -1}, /* TIOC0A */ - {P4_1 , 2 , -1}, /* TIOC0B */ - {P5_1 , 6 , -1}, /* TIOC0B */ - {P7_1 , 7 , -1}, /* TIOC0B */ - {P10_5 , 2 , -1}, /* TIOC0B */ - {P4_2 , 2 , -1}, /* TIOC0C */ - {P5_5 , 6 , -1}, /* TIOC0C */ - {P7_2 , 7 , -1}, /* TIOC0C */ - {P10_6 , 2 , -1}, /* TIOC0C */ - {P4_3 , 2 , -1}, /* TIOC0D */ - {P5_7 , 6 , -1}, /* TIOC0D */ - {P7_3 , 7 , -1}, /* TIOC0D */ - {P10_7 , 2 , -1}, /* TIOC0D */ - {P2_11 , 5 , -1}, /* TIOC1A */ - {P6_0 , 5 , -1}, /* TIOC1A */ - {P7_4 , 7 , -1}, /* TIOC1A */ - {P8_8 , 5 , -1}, /* TIOC1A */ - {P9_7 , 4 , -1}, /* TIOC1A */ - {P10_8 , 2 , -1}, /* TIOC1A */ - {P2_12 , 8 , -1}, /* TIOC1B */ - {P5_2 , 6 , -1}, /* TIOC1B */ - {P6_1 , 5 , -1}, /* TIOC1B */ - {P7_5 , 7 , -1}, /* TIOC1B */ - {P8_9 , 5 , -1}, /* TIOC1B */ - {P10_9 , 2 , -1}, /* TIOC1B */ - {P2_1 , 6 , -1}, /* TIOC2A */ - {P6_2 , 6 , -1}, /* TIOC2A */ - {P7_6 , 7 , -1}, /* TIOC2A */ - {P8_14 , 4 , -1}, /* TIOC2A */ - {P10_10 , 2 , -1}, /* TIOC2A */ - {P2_2 , 6 , -1}, /* TIOC2B */ - {P6_3 , 6 , -1}, /* TIOC2B */ - {P7_7 , 7 , -1}, /* TIOC2B */ - {P8_15 , 4 , -1}, /* TIOC2B */ - {P10_11 , 2 , -1}, /* TIOC2B */ - {P10_11 , 2 , -1}, /* TIOC2B */ - {P3_4 , 6 , -1}, /* TIOC3A */ - {P7_8 , 7 , -1}, /* TIOC3A */ - {P8_10 , 4 , -1}, /* TIOC3A */ - {P3_5 , 6 , -1}, /* TIOC3B */ - {P7_9 , 7 , -1}, /* TIOC3B */ - {P8_11 , 4 , -1}, /* TIOC3B */ - {P3_6 , 6 , -1}, /* TIOC3C */ - {P5_3 , 6 , -1}, /* TIOC3C */ - {P7_10 , 7 , -1}, /* TIOC3C */ - {P8_12 , 4 , -1}, /* TIOC3C */ - {P3_7 , 6 , -1}, /* TIOC3D */ - {P5_4 , 6 , -1}, /* TIOC3D */ - {P7_11 , 7 , -1}, /* TIOC3D */ - {P8_13 , 4 , -1}, /* TIOC3D */ - {P3_8 , 6 , -1}, /* TIOC4A */ - {P4_4 , 3 , -1}, /* TIOC4A */ - {P7_12 , 7 , -1}, /* TIOC4A */ - {P11_0 , 2 , -1}, /* TIOC4A */ - {P3_9 , 6 , -1}, /* TIOC4B */ - {P4_5 , 3 , -1}, /* TIOC4B */ - {P7_13 , 7 , -1}, /* TIOC4B */ - {P11_1 , 2 , -1}, /* TIOC4B */ - {P3_10 , 6 , -1}, /* TIOC4C */ - {P4_6 , 3 , -1}, /* TIOC4C */ - {P7_14 , 7 , -1}, /* TIOC4C */ - {P11_2 , 2 , -1}, /* TIOC4C */ - {P3_11 , 6 , -1}, /* TIOC4D */ - {P4_7 , 3 , -1}, /* TIOC4D */ - {P7_15 , 7 , -1}, /* TIOC4D */ - {P11_3 , 2 , -1}, /* TIOC4D */ - {P5_7 , 1 , 1 }, /* TXOUT0M */ - {P5_6 , 1 , 1 }, /* TXOUT0P */ - {P5_5 , 1 , 1 }, /* TXOUT1M */ - {P5_4 , 1 , 1 }, /* TXOUT1P */ - {P5_3 , 1 , 1 }, /* TXOUT2M */ - {P5_2 , 1 , 1 }, /* TXOUT2P */ - {P5_1 , 1 , 1 }, /* TXCLKOUTM */ - {P5_0 , 1 , 1 }, /* TXCLKOUTP */ - {P2_11 , 4 , 0 }, /* SSITxD0 */ - {P4_7 , 5 , 0 }, /* SSITxD0 */ - {P7_4 , 6 , 0 }, /* SSITxD1 */ - {P10_15 , 2 , 0 }, /* SSITxD1 */ - {P4_15 , 6 , 0 }, /* SSITxD3 */ - {P7_11 , 2 , 0 }, /* SSITxD3 */ - {P2_7 , 4 , 0 }, /* SSITxD5 */ - {P4_11 , 5 , 0 }, /* SSITxD5 */ - {P8_10 , 8 , 0 }, /* SSITxD5 */ - {P3_7 , 8 , 0 }, /* WDTOVF */ - {NC , 0 , -1} -}; - -void pin_function(PinName pin, int function) { - if (pin == (PinName)NC) return; - - int n = pin >> 4; - int bitmask = 1<<(pin & 0xf); - const PinFunc * Pipc_0_func = PIPC_0_tbl; - int pipc_data = 1; - - if (gpio_multi_guard != pin) { - if (function == 0) { - // means GPIO mode - *PMC(n) &= ~bitmask; - } else { - // alt-function mode - --function; - - if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} - if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} - if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} - - while (Pipc_0_func->pin != NC) { - if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) { - pipc_data = 0; - if (Pipc_0_func->pm == 0) { - *PMSR(n) = (bitmask << 16) | 0; - } else if (Pipc_0_func->pm == 1) { - *PMSR(n) = (bitmask << 16) | bitmask; - } else { - // Do Nothing - } - break; - } - Pipc_0_func++; - } - if (pipc_data == 1) { - *PIPC(n) |= bitmask; - } else { - *PIPC(n) &= ~bitmask; - } - - if (P1_0 <= pin && pin <= P1_7 && function == 0) { - *PBDC(n) |= bitmask; - } - *PMC(n) |= bitmask; - } - } else { - gpio_multi_guard = (PinName)NC; - } -} - -void pin_mode(PinName pin, PinMode mode) { -// if (pin == (PinName)NC) { return; } -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c deleted file mode 100644 index 5f9f16e4d5..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c +++ /dev/null @@ -1,65 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -PinName port_pin(PortName port, int pin_n) { - return (PinName)(0); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { - obj->port = port; - obj->mask = mask; - - // Do not use masking, because it prevents the use of the unmasked pins - // port_reg->FIOMASK = ~mask; - - uint32_t i; - // The function is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i)); - } - } - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) { - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) { - switch (dir) { - case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; - case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; - } -} - -void port_write(port_t *obj, int value) { - *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask); -} - -int port_read(port_t *obj) { - return (*obj->reg_in & obj->mask); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c deleted file mode 100644 index f526a221c3..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c +++ /dev/null @@ -1,378 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed_assert.h" -#include "device.h" - -#if DEVICE_RTC - -#include "rtc_api.h" -#include "rtc_iodefine.h" -#include "mbed_mktime.h" - - -#define RCR1_VAL_ON (0x08u) // AIE = 1 -#define RCR1_VAL_OFF (0x00u) -#define RCR2_VAL_ALLSTOP (0x00u) -#define RCR2_VAL_START (0x01u) // START = 1 -#define RCR2_VAL_RESET (0x02u) // RESET = 1 -#define RCR3_VAL (0x00u) -#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL -#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL -#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) -#define RFRL_VAL_13333 (0x2DCDu) // -#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF) -#define RFRL_VAL_MAX (0xFFFFu) // - -#define MASK_00_03_POS (0x000Fu) -#define MASK_04_07_POS (0x00F0u) -#define MASK_08_11_POS (0x0F00u) -#define MASK_12_15_POS (0xF000u) -#define MASK_16_20_POS (0x000F0000u) -#define SHIFT_1_HBYTE (4u) -#define SHIFT_2_HBYTE (8u) -#define SHIFT_3_HBYTE (12u) -#define SHIFT_1BYTE (8u) -#define SHIFT_2BYTE (16u) - -#define TIME_ERROR_VAL (0xFFFFFFFFu) - -static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val); -static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val); -static uint8_t rtc_hex8_to_dec(uint8_t hex_val); -static uint16_t rtc_hex16_to_dec(uint16_t hex_val); - - -/* - * Setup the RTC based on a time structure. - * The rtc_init function should be executed first. - * [in] - * None. - * [out] - * None. - */ -void rtc_init(void) { - volatile uint8_t dummy_read; - - // Set control register - RTC.RCR2 = RCR2_VAL_ALLSTOP; - RTC.RCR1 = RCR1_VAL_ON; - RTC.RCR3 = RCR3_VAL; - RTC.RCR5 = RCR5_VAL_EXTAL; - RTC.RFRH = RFRH_VAL_13333; - RTC.RFRL = RFRL_VAL_13333; - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - - RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - - // Set timer and alarm. Default value :01-01-1970 00:00:00 - RTC.RSECCNT = 0; - RTC.RMINCNT = 0; - RTC.RHRCNT = 0; - RTC.RWKCNT = 0; - RTC.RDAYCNT = 1; - RTC.RMONCNT = 1; - RTC.RYRCNT = 0x1970; - RTC.RSECAR = 0; - RTC.RMINAR = 0; - RTC.RHRAR = 0; - RTC.RWKAR = 0; - RTC.RDAYAR = 1; - RTC.RMONAR = 1; - RTC.RYRAR = 0x1970; - - // Dummy read - dummy_read = RTC.RYRCNT; - dummy_read = RTC.RYRCNT; - -} - - -/* - * Release the RTC based on a time structure. - * [in] - * None. - * [out] - * None. - */ -void rtc_free(void) { - volatile uint8_t dummy_read; - - // Set control register - RTC.RCR2 = RCR2_VAL_ALLSTOP; - RTC.RCR1 = RCR1_VAL_OFF; - RTC.RCR3 = RCR3_VAL; - RTC.RCR5 = RCR5_VAL_RTCX1; - RTC.RFRH = RFRH_VAL_MAX; - RTC.RFRL = RFRL_VAL_MAX; - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 - - // Dummy read - dummy_read = RTC.RCR2; - dummy_read = RTC.RCR2; - - // Set timer and alarm. Default value :01-01-1970 00:00:00 - RTC.RSECCNT = 0; - RTC.RMINCNT = 0; - RTC.RHRCNT = 0; - RTC.RWKCNT = 0; - RTC.RDAYCNT = 1; - RTC.RMONCNT = 1; - RTC.RYRCNT = 0x1970; - RTC.RSECAR = 0; - RTC.RMINAR = 0; - RTC.RHRAR = 0; - RTC.RWKAR = 0; - RTC.RDAYAR = 1; - RTC.RMONAR = 1; - RTC.RYRAR = 0x1970; - - // Dummy read - dummy_read = RTC.RYRCNT; - dummy_read = RTC.RYRCNT; - -} - - -/* - * Check the RTC has been enabled. - * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled. - * [in] - * None. - * [out] - * 0:Disabled, 1:Enabled. - */ -int rtc_isenabled(void) { - int ret_val = 0; - - if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ? - ret_val = 1; - } - - return ret_val; -} - - -/* - * RTC read function. - * [in] - * None. - * [out] - * UNIX timestamp value. - */ -time_t rtc_read(void) { - - struct tm timeinfo; - int err = 0; - uint8_t tmp_regdata; - time_t t; - - if (rtc_isenabled() != 0) { - RTC.RCR1 &= ~0x10u; // CIE = 0 - do { - // before reading process - tmp_regdata = RTC.RCR1; - tmp_regdata &= ~0x80u; // CF = 0 - tmp_regdata |= 0x01u; // AF = 1 - RTC.RCR1 = tmp_regdata; - - // Read RTC register - err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec); - err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min); - err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour); - err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday); - err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon); - err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year); - } while ((RTC.RCR1 & 0x80u) != 0); - } else { - err = 1; - } - - if (err == 0) { - // Convert to timestamp - t = _rtc_mktime(&timeinfo); - } else { - // Error - t = TIME_ERROR_VAL; - } - - return t; -} - -/* - * Dec(8bit) to Hex function for RTC. - * [in] - * dec_val:Decimal value (from 0x00 to 0x99). - * offset:Subtract offset from dec_val. - * hex_val:Pointer of output hexadecimal value. - * [out] - * 0:Success - * 1:Error - */ -static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) { - int err = 0; - uint8_t ret_val; - - if (hex_val != NULL) { - if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || - ((dec_val & MASK_00_03_POS) >= 0x0A)) { - err = 1; - } else { - ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 + - (dec_val & MASK_00_03_POS); - if (ret_val < offset) { - err = 1; - } else { - *hex_val = ret_val - offset; - } - } - } else { - err = 1; - } - - return err; -} - -/* - * Dec(16bit) to Hex function for RTC - * [in] - * dec_val:Decimal value (from 0x0000 to 0x9999). - * offset:Subtract offset from dec_val. - * hex_val:Pointer of output hexadecimal value. - * [out] - * 0:Success - * 1:Error - */ -static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) { - int err = 0; - uint16_t ret_val; - - if (hex_val != NULL) { - if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) || - ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) || - ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) || - ((dec_val & MASK_00_03_POS) >= 0x0A)) { - err = 1; - *hex_val = 0; - } else { - ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 + - (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 + - (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 + - (dec_val & MASK_00_03_POS); - if (ret_val < offset) { - err = 1; - } else { - *hex_val = ret_val - offset; - } - } - } else { - err = 1; - } - return err; -} - -/* - * RTC write function - * [in] - * t:UNIX timestamp value - * [out] - * None. - */ -void rtc_write(time_t t) { - - struct tm timeinfo; - if (_rtc_localtime(t, &timeinfo) == false) { - return; - } - volatile uint16_t dummy_read; - - if (rtc_isenabled() != 0) { - RTC.RCR2 = RCR2_VAL_ALLSTOP; - dummy_read = (uint16_t)RTC.RCR2; - dummy_read = (uint16_t)RTC.RCR2; - RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1 - dummy_read = (uint16_t)RTC.RCR2; - dummy_read = (uint16_t)RTC.RCR2; - - RTC.RSECCNT = rtc_hex8_to_dec(timeinfo.tm_sec); - RTC.RMINCNT = rtc_hex8_to_dec(timeinfo.tm_min); - RTC.RHRCNT = rtc_hex8_to_dec(timeinfo.tm_hour); - RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo.tm_mday); - RTC.RMONCNT = rtc_hex8_to_dec(timeinfo.tm_mon + 1); - RTC.RYRCNT = rtc_hex16_to_dec(timeinfo.tm_year + 1900); - dummy_read = (uint16_t)RTC.RYRCNT; - dummy_read = (uint16_t)RTC.RYRCNT; - - RTC.RCR2 = RCR2_VAL_START; // START = 1 - - dummy_read = (uint16_t)RTC.RCR2; - dummy_read = (uint16_t)RTC.RCR2; - } -} - -/* - * HEX to Dec(8bit) function for RTC. - * [in] - * hex_val:Hexadecimal value. - * [out] - * decimal value:From 0x00 to 0x99. - */ -static uint8_t rtc_hex8_to_dec(uint8_t hex_val) { - uint32_t calc_data; - - calc_data = hex_val / 10 * 0x10; - calc_data += hex_val % 10; - - if (calc_data > 0x99) { - calc_data = 0; - } - - return (uint8_t)calc_data; -} - -/* - * HEX to Dec(16bit) function for RTC. - * [in] - * hex_val:Hexadecimal value. - * [out] - * decimal value:From 0x0000 to 0x9999. - */ -static uint16_t rtc_hex16_to_dec(uint16_t hex_val) { - uint32_t calc_data; - calc_data = hex_val / 1000 * 0x1000; - calc_data += ((hex_val / 100) % 10) * 0x100; - calc_data += ((hex_val / 10) % 10) * 0x10; - calc_data += hex_val % 10; - - if (calc_data > 0x9999) { - calc_data = 0; - } - return (uint16_t)calc_data; - -} - -#endif /* DEVICE_RTC */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h index e7db580626..a8c7fb6df0 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h @@ -34,105 +34,31 @@ typedef enum { UART7, } UARTName; -// PWMType & 1 == 1 then have to use PWDTR[12] == 1 typedef enum { - PWM1A = 0, - PWM1B, - PWM1C, - PWM1D, - PWM1E, - PWM1F, - PWM1G, - PWM1H, - PWM2A = 0x10, - PWM2B, - PWM2C, - PWM2D, - PWM2E, - PWM2F, - PWM2G, - PWM2H, -} PWMType; - -typedef enum { - TIOC0A = 0, - TIOC0B, - TIOC0C, - TIOC0D, - TIOC1A = 0x10, - TIOC1B, - TIOC2A = 0x20, - TIOC2B, - TIOC3A = 0x30, - TIOC3B, - TIOC3C, - TIOC3D, - TIOC4A = 0x40, - TIOC4B, - TIOC4C, - TIOC4D, -} MTU2_PWMType; - -typedef enum { - PWM0_PIN = 0, - PWM1_PIN, - PWM2_PIN, - PWM3_PIN, - PWM4_PIN, - PWM5_PIN, - PWM6_PIN, - PWM7_PIN, - PWM8_PIN, - PWM9_PIN, - PWM10_PIN, - PWM11_PIN, - PWM12_PIN, -#ifdef MAX_PERI - PWM13_PIN, - PWM14_PIN, - PWM15_PIN, - MTU2_PWM0_PIN = 0x20, - MTU2_PWM1_PIN, - MTU2_PWM2_PIN, - MTU2_PWM3_PIN, - MTU2_PWM4_PIN, - MTU2_PWM5_PIN, - MTU2_PWM6_PIN, - MTU2_PWM7_PIN, - MTU2_PWM8_PIN, - MTU2_PWM9_PIN, - MTU2_PWM10_PIN, - MTU2_PWM11_PIN, - MTU2_PWM12_PIN, - MTU2_PWM13_PIN, - MTU2_PWM14_PIN, - MTU2_PWM15_PIN, - MTU2_PWM16_PIN, - MTU2_PWM17_PIN, - MTU2_PWM18_PIN, - MTU2_PWM19_PIN, - MTU2_PWM20_PIN, - MTU2_PWM21_PIN, - MTU2_PWM22_PIN, - MTU2_PWM23_PIN, - MTU2_PWM23_PIN, - MTU2_PWM24_PIN, - MTU2_PWM25_PIN, - MTU2_PWM26_PIN, -#else - MTU2_PWM0_PIN = 0x20, - MTU2_PWM1_PIN, - MTU2_PWM2_PIN, - MTU2_PWM3_PIN, - MTU2_PWM4_PIN, - MTU2_PWM5_PIN, - MTU2_PWM6_PIN, - MTU2_PWM7_PIN, - MTU2_PWM8_PIN, - MTU2_PWM9_PIN, - MTU2_PWM10_PIN, - MTU2_PWM11_PIN, -#endif + PWM_PWM1A = 0, + PWM_PWM1B, + PWM_PWM1C, + PWM_PWM1D, + PWM_PWM1E, + PWM_PWM1F, + PWM_PWM1G, + PWM_PWM1H, + PWM_PWM2A, + PWM_PWM2B, + PWM_PWM2C, + PWM_PWM2D, + PWM_PWM2E, + PWM_PWM2F, + PWM_PWM2G, + PWM_PWM2H, + PWM_TIOC0A = 0x20, + PWM_TIOC0C, + PWM_TIOC1A, + PWM_TIOC2A, + PWM_TIOC3A, + PWM_TIOC3C, + PWM_TIOC4A, + PWM_TIOC4C, } PWMName; typedef enum { @@ -147,7 +73,8 @@ typedef enum { } ADCName; typedef enum { - SPI_1 = 1, + SPI_0 = 0, + SPI_1, SPI_2, SPI_3, SPI_4, @@ -157,7 +84,7 @@ typedef enum { I2C_0 = 0, I2C_1, I2C_2, - I2C_3 + I2C_3, } I2CName; typedef enum { @@ -165,7 +92,7 @@ typedef enum { CAN_1, CAN_2, CAN_3, - CAN_4 + CAN_4, } CANName; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c new file mode 100644 index 0000000000..d5fd4b1d92 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c @@ -0,0 +1,540 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************IRQ***************/ +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, +} IRQNo; +const PinMap PinMap_IRQ[] = { +#ifdef MAX_PERI + {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4}, + {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8}, + {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4}, + {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4}, + {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4}, + {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, + {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8}, + {NC, NC, 0} +#else + {P9_1, IRQ0, 4}, + {P7_8, IRQ1, 8}, + {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, + {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3}, + {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3}, + {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3}, + {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, + {NC, NC, 0} +#endif +}; + +/************PINMAP***************/ +const PinFunc PIPC_0_tbl[] = { +#ifdef MAX_PERI +// pin func pm + {P4_0 , 2 , -1}, /* TIOC0A */ + {P5_0 , 6 , -1}, /* TIOC0A */ + {P7_0 , 7 , -1}, /* TIOC0A */ + {P4_1 , 2 , -1}, /* TIOC0B */ + {P5_1 , 6 , -1}, /* TIOC0B */ + {P7_1 , 7 , -1}, /* TIOC0B */ + {P4_2 , 2 , -1}, /* TIOC0C */ + {P5_5 , 6 , -1}, /* TIOC0C */ + {P7_2 , 7 , -1}, /* TIOC0C */ + {P4_3 , 2 , -1}, /* TIOC0D */ + {P5_7 , 6 , -1}, /* TIOC0D */ + {P7_3 , 7 , -1}, /* TIOC0D */ + {P2_11 , 5 , -1}, /* TIOC1A */ + {P6_0 , 5 , -1}, /* TIOC1A */ + {P7_4 , 7 , -1}, /* TIOC1A */ + {P8_8 , 5 , -1}, /* TIOC1A */ + {P9_7 , 4 , -1}, /* TIOC1A */ + {P2_12 , 8 , -1}, /* TIOC1B */ + {P5_2 , 6 , -1}, /* TIOC1B */ + {P6_1 , 5 , -1}, /* TIOC1B */ + {P7_5 , 7 , -1}, /* TIOC1B */ + {P8_9 , 5 , -1}, /* TIOC1B */ + {P2_1 , 6 , -1}, /* TIOC2A */ + {P6_2 , 6 , -1}, /* TIOC2A */ + {P7_6 , 7 , -1}, /* TIOC2A */ + {P8_14 , 4 , -1}, /* TIOC2A */ + {P2_2 , 6 , -1}, /* TIOC2B */ + {P6_3 , 6 , -1}, /* TIOC2B */ + {P7_7 , 7 , -1}, /* TIOC2B */ + {P8_15 , 4 , -1}, /* TIOC2B */ + {P3_4 , 6 , -1}, /* TIOC3A */ + {P7_8 , 7 , -1}, /* TIOC3A */ + {P8_10 , 4 , -1}, /* TIOC3A */ + {P3_5 , 6 , -1}, /* TIOC3B */ + {P7_9 , 7 , -1}, /* TIOC3B */ + {P8_11 , 4 , -1}, /* TIOC3B */ + {P3_6 , 6 , -1}, /* TIOC3C */ + {P5_3 , 6 , -1}, /* TIOC3C */ + {P7_10 , 7 , -1}, /* TIOC3C */ + {P8_12 , 4 , -1}, /* TIOC3C */ + {P3_7 , 6 , -1}, /* TIOC3D */ + {P5_4 , 6 , -1}, /* TIOC3D */ + {P7_11 , 7 , -1}, /* TIOC3D */ + {P8_13 , 4 , -1}, /* TIOC3D */ + {P3_8 , 6 , -1}, /* TIOC4A */ + {P4_4 , 3 , -1}, /* TIOC4A */ + {P7_12 , 7 , -1}, /* TIOC4A */ + {P3_9 , 6 , -1}, /* TIOC4B */ + {P4_5 , 3 , -1}, /* TIOC4B */ + {P7_13 , 7 , -1}, /* TIOC4B */ + {P3_10 , 6 , -1}, /* TIOC4C */ + {P4_6 , 3 , -1}, /* TIOC4C */ + {P7_14 , 7 , -1}, /* TIOC4C */ + {P3_11 , 6 , -1}, /* TIOC4D */ + {P4_7 , 3 , -1}, /* TIOC4D */ + {P7_15 , 7 , -1}, /* TIOC4D */ + {P5_7 , 1 , 1 }, /* TXOUT0M */ + {P5_6 , 1 , 1 }, /* TXOUT0P */ + {P5_5 , 1 , 1 }, /* TXOUT1M */ + {P5_4 , 1 , 1 }, /* TXOUT1P */ + {P5_3 , 1 , 1 }, /* TXOUT2M */ + {P5_2 , 1 , 1 }, /* TXOUT2P */ + {P5_1 , 1 , 1 }, /* TXCLKOUTM */ + {P5_0 , 1 , 1 }, /* TXCLKOUTP */ + {P2_11 , 4 , 0 }, /* SSITxD0 */ + {P4_7 , 5 , 0 }, /* SSITxD0 */ + {P7_4 , 6 , 0 }, /* SSITxD1 */ + {P4_15 , 6 , 0 }, /* SSITxD3 */ + {P7_11 , 2 , 0 }, /* SSITxD3 */ + {P2_7 , 4 , 0 }, /* SSITxD5 */ + {P4_11 , 5 , 0 }, /* SSITxD5 */ + {P8_10 , 8 , 0 }, /* SSITxD5 */ + {P3_7 , 8 , 0 }, /* WDTOVF */ + {NC , 0 , -1} +#else + // pin func pm + {P4_0 , 2 , -1}, // TIOC0A + {P5_0 , 6 , -1}, // TIOC0A + {P4_2 , 2 , -1}, // TIOC0C + {P5_5 , 6 , -1}, // TIOC0C + // + {P8_14 , 4 , -1}, // TIOC2A + // + {P8_10 , 4 , -1}, // TIOC3A + {P5_3 , 6 , -1}, // TIOC3C + {P8_12 , 4 , -1}, // TIOC3C + // + {P3_8 , 6 , -1}, // TIOC4A + {P4_4 , 3 , -1}, // TIOC4A + {P3_10 , 6 , -1}, // TIOC4C + {P4_6 , 3 , -1}, // TIOC4C + // + {P5_7 , 1 , 1 }, // TXOUT0M + {P5_6 , 1 , 1 }, // TXOUT0P + {P5_5 , 1 , 1 }, // TXOUT1M + {P5_4 , 1 , 1 }, // TXOUT1P + {P5_3 , 1 , 1 }, // TXOUT2M + {P5_2 , 1 , 1 }, // TXOUT2P + {P5_1 , 1 , 1 }, // TXCLKOUTM + {P5_0 , 1 , 1 }, // TXCLKOUTP + {P4_7 , 5 , 0 }, // SSITxD0 + {P8_10 , 8 , 0 }, // SSITxD5 + {P3_7 , 8 , 0 }, // WDTOVF + {NC , 0 , -1} +#endif +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { +#ifdef MAX_PERI + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_14, AN6, 1}, + {P1_15, AN7, 1}, + {NC, NC, 0} +#else + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_12, AN4, 1}, + {P1_13, AN5, 1}, + {P1_15, AN7, 1}, + {NC, NC, 0} +#endif +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P1_1 , I2C_0, 1}, + {P1_3 , I2C_1, 1}, + {P1_5 , I2C_2, 1}, + {P1_7 , I2C_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P1_0 , I2C_0, 1}, + {P1_2 , I2C_1, 1}, + {P1_4 , I2C_2, 1}, + {P1_6 , I2C_3, 1}, + {NC , NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { +#ifdef MAX_PERI + {P2_14 , UART0, 6}, + {P4_9 , UART0, 7}, + {P6_9 , UART0, 5}, + {P2_5 , UART1, 6}, + {P4_12 , UART1, 7}, + {P6_12 , UART1, 5}, + {P9_3 , UART1, 4}, + {P3_0 , UART2, 6}, + {P3_1 , UART2, 4}, + {P4_2 , UART2, 5}, + {P4_14 , UART2, 7}, + {P6_3 , UART2, 7}, + {P8_6 , UART2, 7}, + {P3_5 , UART3, 7}, + {P5_3 , UART3, 5}, + {P6_1 , UART3, 7}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P7_1 , UART4, 4}, + {P8_14 , UART4, 7}, + {P6_6 , UART5, 5}, + {P8_1 , UART5, 4}, + {P8_13 , UART5, 5}, + {P5_6 , UART6, 5}, + {P6_14 , UART6, 4}, + {P7_4 , UART7, 4}, + {NC , NC , 0} +#else + {P3_0 , UART2, 6}, + {P3_1 , UART2, 4}, + {P4_2 , UART2, 5}, + {P5_3 , UART3, 5}, + {P8_8 , UART3, 7}, + {P5_0 , UART4, 5}, + {P8_14 , UART4, 7}, + {P8_13 , UART5, 5}, + {P5_6 , UART6, 5}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_UART_RX[] = { +#ifdef MAX_PERI + {P2_15 , UART0, 6}, + {P4_10 , UART0, 7}, + {P6_10 , UART0, 5}, + {P2_6 , UART1, 6}, + {P4_13 , UART1, 7}, + {P6_13 , UART1, 5}, + {P9_4 , UART1, 4}, + {P3_2 , UART2, 4}, + {P4_3 , UART2, 5}, + {P4_15 , UART2, 7}, + {P6_2 , UART2, 7}, + {P8_4 , UART2, 7}, + {P3_6 , UART3, 7}, + {P5_4 , UART3, 5}, + {P6_0 , UART3, 7}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P7_2 , UART4, 4}, + {P8_15 , UART4, 7}, + {P6_7 , UART5, 5}, + {P8_2 , UART5, 4}, + {P8_11 , UART5, 5}, + {P5_7 , UART6, 5}, + {P6_15 , UART6, 4}, + {P7_5 , UART7, 4}, + {NC , NC , 0} +#else + {P3_2 , UART2, 4}, + {P4_3 , UART2, 5}, + {P5_4 , UART3, 5}, + {P8_9 , UART3, 7}, + {P5_1 , UART4, 5}, + {P8_15 , UART4, 7}, + {P8_11 , UART5, 5}, + {P5_7 , UART6, 5}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_UART_CTS[] = { +#ifdef MAX_PERI + {P2_3 , UART1, 6}, + {P9_5 , UART1, 4}, + {P6_3 , UART5, 5}, + {P7_15 , UART5, 4}, + {P7_6 , UART7, 4}, + {NC , NC , 0} +#else + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_UART_RTS[] = { +#ifdef MAX_PERI + {P2_7 , UART1, 6}, + {P9_6 , UART1, 4}, + {P6_4 , UART5, 5}, + {P8_3 , UART5, 4}, + {P7_7 , UART7, 4}, + {NC , NC , 0} +#else + {NC , NC , 0} +#endif +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { +#ifdef MAX_PERI + {P2_12 , SPI_0, 2}, + {P7_15 , SPI_0, 2}, + {P4_4 , SPI_1, 2}, + {P6_4 , SPI_1, 7}, + {P8_3 , SPI_2, 3}, + {P8_14 , SPI_2, 5}, + {P3_0 , SPI_3, 8}, + {P5_0 , SPI_3, 8}, + {P2_8 , SPI_4, 8}, + {P4_0 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_4 , SPI_1, 2}, + {P8_14 , SPI_2, 5}, + {P5_0 , SPI_3, 8}, + {P4_0 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_SPI_MOSI[] = { +#ifdef MAX_PERI + {P2_14 , SPI_0, 2}, + {P8_1 , SPI_0, 2}, + {P4_6 , SPI_1, 2}, + {P6_6 , SPI_1, 7}, + {P8_5 , SPI_2, 3}, + {P9_0 , SPI_2, 5}, + {P3_2 , SPI_3, 8}, + {P5_2 , SPI_3, 8}, + {P2_10 , SPI_4, 8}, + {P4_2 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_6 , SPI_1, 2}, + {P9_0 , SPI_2, 5}, + {P5_2 , SPI_3, 8}, + {P4_2 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_SPI_MISO[] = { +#ifdef MAX_PERI + {P2_15 , SPI_0, 2}, + {P8_2 , SPI_0, 2}, + {P4_7 , SPI_1, 2}, + {P6_7 , SPI_1, 7}, + {P8_6 , SPI_2, 3}, + {P9_1 , SPI_2, 5}, + {P3_3 , SPI_3, 8}, + {P5_3 , SPI_3, 8}, + {P2_11 , SPI_4, 8}, + {P4_3 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_7 , SPI_1, 2}, + {P9_1 , SPI_2, 5}, + {P5_3 , SPI_3, 8}, + {P4_3 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_SPI_SSEL[] = { +#ifdef MAX_PERI + {P2_13 , SPI_0, 2}, + {P8_0 , SPI_0, 2}, + {P4_5 , SPI_1, 2}, + {P6_5 , SPI_1, 7}, + {P8_4 , SPI_2, 3}, + {P8_15 , SPI_2, 5}, + {P3_1 , SPI_3, 8}, + {P5_1 , SPI_3, 8}, + {P2_9 , SPI_4, 8}, + {P4_1 , SPI_4, 7}, + {NC , NC , 0} +#else + {P4_5 , SPI_1, 2}, + {P8_15 , SPI_2, 5}, + {P5_1 , SPI_3, 8}, + {P4_1 , SPI_4, 7}, + {NC , NC , 0} +#endif +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { +#ifdef MAX_PERI + // TIOC0 A,C + {P4_0 , PWM_TIOC0A, 2}, //TIOC0A + {P5_0 , PWM_TIOC0A, 6}, //TIOC0A + {P7_0 , PWM_TIOC0A, 7}, //TIOC0A + {P4_2 , PWM_TIOC0C, 2}, //TIOC0C + {P5_5 , PWM_TIOC0C, 6}, //TIOC0C + {P7_2 , PWM_TIOC0C, 7}, //TIOC0C + //TIOC1 A + {P2_11 , PWM_TIOC1A, 5}, //TIOC1A + {P6_0 , PWM_TIOC1A, 5}, //TIOC1A + {P7_4 , PWM_TIOC1A, 7}, //TIOC1A + {P8_8 , PWM_TIOC1A, 5}, //TIOC1A + {P9_7 , PWM_TIOC1A, 4}, //TIOC1A + //TIOC2 A + {P2_1 , PWM_TIOC2A, 6}, //TIOC2A + {P6_2 , PWM_TIOC2A, 6}, //TIOC2A + {P7_6 , PWM_TIOC2A, 7}, //TIOC2A + {P8_14 , PWM_TIOC2A, 4}, //TIOC2A + //TIOC3 A,C + {P3_4 , PWM_TIOC3A, 6}, //TIOC3A + {P7_8 , PWM_TIOC3A, 7}, //TIOC3A + {P8_10 , PWM_TIOC3A, 4}, //TIOC3A + {P3_6 , PWM_TIOC3C, 6}, //TIOC3C + {P7_10 , PWM_TIOC3C, 7}, //TIOC3C + {P8_12 , PWM_TIOC3C, 4}, //TIOC3C + //TIOC4 A,C + {P3_8 , PWM_TIOC4A, 6}, //TIOC4A + {P4_4 , PWM_TIOC4A, 3}, //TIOC4A + {P7_12 , PWM_TIOC4A, 7}, //TIOC4A + {P3_10 , PWM_TIOC4C, 6}, //TIOC4C + {P4_6 , PWM_TIOC4C, 3}, //TIOC4C + {P7_14 , PWM_TIOC4C, 7}, //TIOC4C + //PWM1 + {P8_8 , PWM_PWM1A , 6}, //PWM1A + {P8_9 , PWM_PWM1B , 6}, //PWM1B + {P8_10 , PWM_PWM1C , 6}, //PWM1C + {P8_11 , PWM_PWM1D , 6}, //PWM1D + {P8_12 , PWM_PWM1E , 6}, //PWM1E + {P8_13 , PWM_PWM1F , 6}, //PWM1F + {P8_14 , PWM_PWM1G , 6}, //PWM1G + {P8_15 , PWM_PWM1H , 6}, //PWM1H + //PWM2 + {P3_0 , PWM_PWM2A , 7}, //PWM2A + {P3_1 , PWM_PWM2B , 7}, //PWM2B + {P3_2 , PWM_PWM2C , 7}, //PWM2C + {P3_3 , PWM_PWM2D , 7}, //PWM2D + {P4_4 , PWM_PWM2E , 4}, //PWM2E + {P4_5 , PWM_PWM2F , 4}, //PWM2F + {P4_6 , PWM_PWM2G , 4}, //PWM2G + {P4_7 , PWM_PWM2H , 4}, //PWM2H + {NC , NC , 0} +#else + //TIOC0 A,C + {P4_0 , PWM_TIOC0A, 2}, //TIOC0A + {P5_0 , PWM_TIOC0A, 6}, //TIOC0A + {P4_2 , PWM_TIOC0C, 2}, //TIOC0C + {P5_5 , PWM_TIOC0C, 6}, //TIOC0C + //TIOC2 A + {P8_14 , PWM_TIOC2A, 4}, //TIOC2A + //TIOC3 A,C + {P8_10 , PWM_TIOC3A, 4}, //TIOC3A + {P5_3 , PWM_TIOC3C, 6}, //TIOC3C + {P8_12 , PWM_TIOC3C, 4}, //TIOC3C + //TIOC4 A,C + {P3_8 , PWM_TIOC4A, 6}, //TIOC4A + {P4_4 , PWM_TIOC4A, 3}, //TIOC4A + {P3_10 , PWM_TIOC4C, 6}, //TIOC4C + {P4_6 , PWM_TIOC4C, 3}, //TIOC4C + //PWM1 + {P8_10 , PWM_PWM1C , 6}, //PWM1C + {P8_11 , PWM_PWM1D , 6}, //PWM1D + {P8_12 , PWM_PWM1E , 6}, //PWM1E + {P8_13 , PWM_PWM1F , 6}, //PWM1F + {P8_14 , PWM_PWM1G , 6}, //PWM1G + {P8_15 , PWM_PWM1H , 6}, //PWM1H + //PWM2 + {P3_0 , PWM_PWM2A , 7}, //PWM2A + {P3_1 , PWM_PWM2B , 7}, //PWM2B + {P3_2 , PWM_PWM2C , 7}, //PWM2C + {P4_4 , PWM_PWM2E , 4}, //PWM2E + {P4_5 , PWM_PWM2F , 4}, //PWM2F + {P4_6 , PWM_PWM2G , 4}, //PWM2G + {P4_7 , PWM_PWM2H , 4}, //PWM2H + {NC , NC , 0} +#endif +}; + +/************CAN***************/ +const PinMap PinMap_CAN_RD[] = { +#ifdef MAX_PERI + {P7_8 , CAN_0, 4}, + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P7_11 , CAN_1, 4}, + {P4_9 , CAN_2, 6}, + {P6_4 , CAN_2, 3}, + {P7_2 , CAN_2, 5}, + {P2_12 , CAN_3, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {P2_14 , CAN_4, 5}, + {NC , NC , 0} +#else + {P9_1 , CAN_0, 3}, + {P1_4 , CAN_1, 3}, + {P5_9 , CAN_1, 5}, + {P4_2 , CAN_3, 4}, + {P1_5 , CAN_4, 3}, + {NC , NC , 0} +#endif +}; + +const PinMap PinMap_CAN_TD[] = { +#ifdef MAX_PERI + {P7_9 , CAN_0, 4}, + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P7_10 , CAN_1, 4}, + {P4_8 , CAN_2, 6}, + {P6_5 , CAN_2, 3}, + {P7_3 , CAN_2, 5}, + {P2_13 , CAN_3, 5}, + {P4_3 , CAN_3, 4}, + {P4_11 , CAN_4, 6}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +#else + {P9_0 , CAN_0, 3}, + {P5_10 , CAN_1, 5}, + {P4_3 , CAN_3, 4}, + {P8_10 , CAN_4, 5}, + {NC , NC , 0} +#endif +}; + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/analogin_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/analogin_api.c deleted file mode 100644 index caada57bf3..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/analogin_api.c +++ /dev/null @@ -1,133 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#include "cmsis.h" -#include "pinmap.h" - -#include "adc_iodefine.h" -#include "cpg_iodefine.h" - -#define ANALOGIN_MEDIAN_FILTER 0 - -#ifdef MAX_PERI -static const PinMap PinMap_ADC[] = { - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_14, AN6, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -}; -#else -static const PinMap PinMap_ADC[] = { - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -}; -#endif - -static volatile uint16_t *ADCDR[] = { - &ADCADDRA, - &ADCADDRB, - &ADCADDRC, - &ADCADDRD, - &ADCADDRE, - &ADCADDRF, - &ADCADDRG, - &ADCADDRH, -}; - -void analogin_init(analogin_t *obj, PinName pin) { - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - CPGSTBCR3 &= ~(1 << 1); - CPGSTBCR6 &= ~(1 << 7); - - // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 - // [8:6] CKS 010 :: 340tclk - // [5:3] MDS 000 :: single mode - // [2:0] CH 000 :: AN0 - ADCADCSR = 0x0080; - - pinmap_pinout(pin, PinMap_ADC); -} - -static inline uint32_t adc_read(analogin_t *obj) { - volatile uint16_t data; - - // Select the appropriate channel and start conversion - ADCADCSR &= 0xfff8; - ADCADCSR |= (1 << 13 | (obj->adc & 0x7)); - - // Wait end of conversion - do { - data = ADCADCSR; - } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0)); - - // clear flag - ADCADCSR &= ~(1 << 15); - - return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range -} - -#if ANALOGIN_MEDIAN_FILTER -static inline void order(uint32_t *a, uint32_t *b) { - if (*a > *b) { - uint32_t t = *a; - *a = *b; - *b = t; - } -} -#endif - -static inline uint32_t adc_read_u32(analogin_t *obj) { - uint32_t value; -#if ANALOGIN_MEDIAN_FILTER - uint32_t v1 = adc_read(obj); - uint32_t v2 = adc_read(obj); - uint32_t v3 = adc_read(obj); - order(&v1, &v2); - order(&v2, &v3); - order(&v1, &v2); - value = v2; -#else - value = adc_read(obj); -#endif - return value; -} - -uint16_t analogin_read_u16(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - - return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion -} - -float analogin_read(analogin_t *obj) { - uint32_t value = adc_read_u32(obj); - - return (float)value * (1.0f / (float)0x0FFF); // 12 bits range -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c deleted file mode 100644 index ea826157ca..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c +++ /dev/null @@ -1,1042 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "mbed_assert.h" -#include "can_api.h" -#include "RZ_A1_Init.h" -#include "cmsis.h" -#include "pinmap.h" -#include "rscan0_iodefine.h" -#include "r_typedefs.h" -#include "VKRZA1H.h" - -#define CAN_NUM 5 -#define CAN_SND_RCV 2 -#define IRQ_NUM 8 - -static void can_rec_irq(uint32_t ch); -static void can_trx_irq(uint32_t ch); -static void can_err_irq(uint32_t ch, CanIrqType type); -static void can0_rec_irq(void); -static void can1_rec_irq(void); -static void can2_rec_irq(void); -static void can3_rec_irq(void); -static void can4_rec_irq(void); -static void can0_trx_irq(void); -static void can1_trx_irq(void); -static void can2_trx_irq(void); -static void can3_trx_irq(void); -static void can4_trx_irq(void); -static void can0_err_warning_irq(void); -static void can1_err_warning_irq(void); -static void can2_err_warning_irq(void); -static void can3_err_warning_irq(void); -static void can4_err_warning_irq(void); -static void can0_overrun_irq(void); -static void can1_overrun_irq(void); -static void can2_overrun_irq(void); -static void can3_overrun_irq(void); -static void can4_overrun_irq(void); -static void can0_passive_irq(void); -static void can1_passive_irq(void); -static void can2_passive_irq(void); -static void can3_passive_irq(void); -static void can4_passive_irq(void); -static void can0_arb_lost_irq(void); -static void can1_arb_lost_irq(void); -static void can2_arb_lost_irq(void); -static void can3_arb_lost_irq(void); -static void can4_arb_lost_irq(void); -static void can0_bus_err_irq(void); -static void can1_bus_err_irq(void); -static void can2_bus_err_irq(void); -static void can3_bus_err_irq(void); -static void can4_bus_err_irq(void); -static void can_reset_reg(can_t *obj); -static void can_reset_recv_rule(can_t *obj); -static void can_reset_buffer(can_t *obj); -static void can_reconfigure_channel(void); -static void can_set_frequency(can_t *obj, int f); -static void can_set_global_mode(int mode); -static void can_set_channel_mode(uint32_t ch, int mode); - -typedef enum { - CAN_SEND = 0, - CAN_RECV -} CANfunc; - -typedef enum { - GL_OPE = 0, - GL_RESET, - GL_TEST -} Globalmode; - -typedef enum { - CH_COMM = 0, - CH_RESET, - CH_HOLD -} Channelmode; - -typedef struct { - IRQn_Type int_num; /* Interrupt number */ - IRQHandler handler; /* Interrupt handler */ -} can_info_int_t; - -static can_irq_handler irq_handler; -static uint32_t can_irq_id[CAN_NUM]; -static int can_initialized[CAN_NUM] = {0}; - -#ifdef MAX_PERI -static const PinMap PinMap_CAN_RD[] = { - {P7_8 , CAN_0, 4}, - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P7_11 , CAN_1, 4}, - {P4_9 , CAN_2, 6}, - {P6_4 , CAN_2, 3}, - {P7_2 , CAN_2, 5}, - {P2_12 , CAN_3, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {P2_14 , CAN_4, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_CAN_TD[] = { - {P7_9 , CAN_0, 4}, - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P7_10 , CAN_1, 4}, - {P4_8 , CAN_2, 6}, - {P6_5 , CAN_2, 3}, - {P7_3 , CAN_2, 5}, - {P2_13 , CAN_3, 5}, - {P4_3 , CAN_3, 4}, - {P4_11 , CAN_4, 6}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -}; -#else -static const PinMap PinMap_CAN_RD[] = { - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {NC , NC , 0} -}; - -static const PinMap PinMap_CAN_TD[] = { - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P4_3 , CAN_3, 4}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -}; -#endif - -static __IO uint32_t *CTR_MATCH[] = { - &RSCAN0C0CTR, - &RSCAN0C1CTR, - &RSCAN0C2CTR, - &RSCAN0C3CTR, - &RSCAN0C4CTR, -}; - -static __IO uint32_t *CFG_MATCH[] = { - &RSCAN0C0CFG, - &RSCAN0C1CFG, - &RSCAN0C2CFG, - &RSCAN0C3CFG, - &RSCAN0C4CFG, -}; - -static __IO uint32_t *RFCC_MATCH[] = { - &RSCAN0RFCC0, - &RSCAN0RFCC1, - &RSCAN0RFCC2, - &RSCAN0RFCC3, - &RSCAN0RFCC4, - &RSCAN0RFCC5, - &RSCAN0RFCC6, - &RSCAN0RFCC7 -}; - -static __IO uint32_t *TXQCC_MATCH[] = { - &RSCAN0TXQCC0, - &RSCAN0TXQCC1, - &RSCAN0TXQCC2, - &RSCAN0TXQCC3, - &RSCAN0TXQCC4, -}; - -static __IO uint32_t *THLCC_MATCH[] = { - &RSCAN0THLCC0, - &RSCAN0THLCC1, - &RSCAN0THLCC2, - &RSCAN0THLCC3, - &RSCAN0THLCC4, -}; - -static __IO uint32_t *STS_MATCH[] = { - &RSCAN0C0STS, - &RSCAN0C1STS, - &RSCAN0C2STS, - &RSCAN0C3STS, - &RSCAN0C4STS, -}; - -static __IO uint32_t *ERFL_MATCH[] = { - &RSCAN0C0ERFL, - &RSCAN0C1ERFL, - &RSCAN0C2ERFL, - &RSCAN0C3ERFL, - &RSCAN0C4ERFL, -}; - -static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFCC0 , &RSCAN0CFCC1 }, - { &RSCAN0CFCC3 , &RSCAN0CFCC4 }, - { &RSCAN0CFCC6 , &RSCAN0CFCC7 }, - { &RSCAN0CFCC9 , &RSCAN0CFCC10 }, - { &RSCAN0CFCC12, &RSCAN0CFCC13 } -}; - -static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 }, - { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 }, - { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 }, - { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 }, - { &RSCAN0CFSTS12, &RSCAN0CFSTS13 } -}; - -static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 }, - { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 }, - { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 }, - { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 }, - { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 } -}; - -static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFID0 , &RSCAN0CFID1 }, - { &RSCAN0CFID3 , &RSCAN0CFID4 }, - { &RSCAN0CFID6 , &RSCAN0CFID7 }, - { &RSCAN0CFID9 , &RSCAN0CFID10 }, - { &RSCAN0CFID12, &RSCAN0CFID13 } -}; - -static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 }, - { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 }, - { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 }, - { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 }, - { &RSCAN0CFPTR12, &RSCAN0CFPTR13 } -}; - -static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFDF00 , &RSCAN0CFDF01 }, - { &RSCAN0CFDF03 , &RSCAN0CFDF04 }, - { &RSCAN0CFDF06 , &RSCAN0CFDF07 }, - { &RSCAN0CFDF09 , &RSCAN0CFDF010 }, - { &RSCAN0CFDF012, &RSCAN0CFDF013 } -}; - -static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = { - { &RSCAN0CFDF10 , &RSCAN0CFDF11 }, - { &RSCAN0CFDF13 , &RSCAN0CFDF14 }, - { &RSCAN0CFDF16 , &RSCAN0CFDF17 }, - { &RSCAN0CFDF19 , &RSCAN0CFDF110 }, - { &RSCAN0CFDF112, &RSCAN0CFDF113 } -}; - -static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = -{ - { /* ch0 */ - { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */ - { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */ - { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */ - { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */ - { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */ - { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */ - { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */ - }, - { /* ch1 */ - { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */ - { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */ - { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */ - { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */ - { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */ - { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */ - { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */ - }, - { /* ch2 */ - { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */ - { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */ - { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */ - { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */ - { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */ - { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */ - { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */ - }, - { /* ch3 */ - { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */ - { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */ - { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */ - { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */ - { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */ - { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */ - { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */ - }, - { /* ch4 */ - { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */ - { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */ - { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */ - { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */ - { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */ - { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */ - { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */ - { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */ - } -}; - -static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0; -static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0; -static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00; -static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10; - -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { - irq_handler = handler; - can_irq_id[obj->ch] = id; -} - -void can_irq_free(can_t *obj) { - can_irq_id[obj->ch] = 0; -} - -void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { - __IO uint32_t *dmy_ctr; - - /* Wake-up Irq is not supported */ - if (type != IRQ_WAKEUP) { - if (enable) { - dmy_ctr = CTR_MATCH[obj->ch]; - if (type == IRQ_ERROR) { - /* EWIE interrupts is enable */ - *dmy_ctr |= 0x00000200; - } else if (type == IRQ_OVERRUN) { - /* OLIE interrupts is enable */ - *dmy_ctr |= 0x00002000; - } else if (type == IRQ_PASSIVE) { - /* EPIE interrupts is enable */ - *dmy_ctr |= 0x00000400; - } else if (type == IRQ_ARB) { - /* ALIE interrupts is enable */ - *dmy_ctr |= 0x00008000; - } else if (type == IRQ_BUS) { - /* BEIE interrupts is enable */ - *dmy_ctr |= 0x00000100; - } - InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler); - GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5); - GIC_EnableIRQ(can_int_info[obj->ch][type].int_num); - } else { - GIC_DisableIRQ(can_int_info[obj->ch][type].int_num); - } - } -} - -static void can_rec_irq(uint32_t ch) { - __IO uint32_t *dmy_cfsts; - - dmy_cfsts = CFSTS_TBL[ch][CAN_RECV]; - *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF - - irq_handler(can_irq_id[ch], IRQ_RX); -} - -static void can_trx_irq(uint32_t ch) { - __IO uint32_t *dmy_cfsts; - - dmy_cfsts = CFSTS_TBL[ch][CAN_SEND]; - *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF - - irq_handler(can_irq_id[ch], IRQ_TX); -} - -static void can_err_irq(uint32_t ch, CanIrqType type) { - __IO uint32_t *dmy_erfl; - int val = 1; - - dmy_erfl = ERFL_MATCH[ch]; - switch (type) { - case IRQ_ERROR: - *dmy_erfl &= 0xFFFFFFFD; // Clear EWF - break; - case IRQ_OVERRUN: - *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF - break; - case IRQ_PASSIVE: - *dmy_erfl &= 0xFFFFFFFB; // Clear EPF - break; - case IRQ_ARB: - *dmy_erfl &= 0xFFFFFF7F; // Clear ALF - break; - case IRQ_BUS: - *dmy_erfl &= 0xFFFF00FF; // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR - *dmy_erfl &= 0xFFFFFFFE; // Clear BEF - break; - case IRQ_WAKEUP: - /* not supported */ - /* fall through */ - default: - val = 0; - break; - } - if (val == 1) { - irq_handler(can_irq_id[ch], type); - } -} - -static void can0_rec_irq(void) { - can_rec_irq(CAN_0); -} - -static void can1_rec_irq(void) { - can_rec_irq(CAN_1); -} - -static void can2_rec_irq(void) { - can_rec_irq(CAN_2); -} - -static void can3_rec_irq(void) { - can_rec_irq(CAN_3); -} - -static void can4_rec_irq(void) { - can_rec_irq(CAN_4); -} - -static void can0_trx_irq(void) { - can_trx_irq(CAN_0); -} - -static void can1_trx_irq(void) { - can_trx_irq(CAN_1); -} - -static void can2_trx_irq(void) { - can_trx_irq(CAN_2); -} - -static void can3_trx_irq(void) { - can_trx_irq(CAN_3); -} - -static void can4_trx_irq(void) { - can_trx_irq(CAN_4); -} - -static void can0_err_warning_irq(void) { - can_err_irq(CAN_0, IRQ_ERROR); -} - -static void can1_err_warning_irq(void) { - can_err_irq(CAN_1, IRQ_ERROR); -} - -static void can2_err_warning_irq(void) { - can_err_irq(CAN_2, IRQ_ERROR); -} - -static void can3_err_warning_irq(void) { - can_err_irq(CAN_3, IRQ_ERROR); -} - -static void can4_err_warning_irq(void) { - can_err_irq(CAN_4, IRQ_ERROR); -} - -static void can0_overrun_irq(void) { - can_err_irq(CAN_0, IRQ_OVERRUN); -} - -static void can1_overrun_irq(void) { - can_err_irq(CAN_1, IRQ_OVERRUN); -} - -static void can2_overrun_irq(void) { - can_err_irq(CAN_2, IRQ_OVERRUN); -} - -static void can3_overrun_irq(void) { - can_err_irq(CAN_3, IRQ_OVERRUN); -} - -static void can4_overrun_irq(void) { - can_err_irq(CAN_4, IRQ_OVERRUN); -} - -static void can0_passive_irq(void) { - can_err_irq(CAN_0, IRQ_PASSIVE); -} - -static void can1_passive_irq(void) { - can_err_irq(CAN_1, IRQ_PASSIVE); -} - -static void can2_passive_irq(void) { - can_err_irq(CAN_2, IRQ_PASSIVE); -} - -static void can3_passive_irq(void) { - can_err_irq(CAN_3, IRQ_PASSIVE); -} - -static void can4_passive_irq(void) { - can_err_irq(CAN_4, IRQ_PASSIVE); -} - -static void can0_arb_lost_irq(void) { - can_err_irq(CAN_0, IRQ_ARB); -} - -static void can1_arb_lost_irq(void) { - can_err_irq(CAN_1, IRQ_ARB); -} - -static void can2_arb_lost_irq(void) { - can_err_irq(CAN_2, IRQ_ARB); -} - -static void can3_arb_lost_irq(void) { - can_err_irq(CAN_3, IRQ_ARB); -} - -static void can4_arb_lost_irq(void) { - can_err_irq(CAN_4, IRQ_ARB); -} - -static void can0_bus_err_irq(void) { - can_err_irq(CAN_0, IRQ_BUS); -} - -static void can1_bus_err_irq(void) { - can_err_irq(CAN_1, IRQ_BUS); -} - -static void can2_bus_err_irq(void) { - can_err_irq(CAN_2, IRQ_BUS); -} - -static void can3_bus_err_irq(void) { - can_err_irq(CAN_3, IRQ_BUS); -} - -static void can4_bus_err_irq(void) { - can_err_irq(CAN_4, IRQ_BUS); -} - -void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) { - __IO uint32_t *dmy_ctr; - - /* determine the CAN to use */ - uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD); - uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD); - obj->ch = pinmap_merge(can_tx, can_rx); - MBED_ASSERT((int)obj->ch != NC); - - /* enable CAN clock */ - CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32); - /* Has CAN RAM initialisation completed ? */ - while ((RSCAN0GSTS & 0x08) == 0x08) { - __NOP(); - } - /* clear Global Stop mode bit */ - RSCAN0GCTR &= 0xFFFFFFFB; - /* clear Channel Stop mode bit */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr &= 0xFFFFFFFB; - /* Enter global reset mode */ - can_set_global_mode(GL_RESET); - /* Enter channel reset mode */ - can_set_channel_mode(obj->ch, CH_RESET); - /* reset register */ - can_reset_reg(obj); - - can_initialized[obj->ch] = 1; - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); - - /* pin out the can pins */ - pinmap_pinout(rd, PinMap_CAN_RD); - pinmap_pinout(td, PinMap_CAN_TD); - - /* set can frequency */ - can_frequency(obj, hz); -} - -void can_init(can_t *obj, PinName rd, PinName td) { - can_init_freq(obj, rd, td, 100000); -} - -void can_free(can_t *obj) { - /* disable CAN clock */ - CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32; -} - -int can_frequency(can_t *obj, int f) { - __IO uint32_t *dmy_cfcc; - int retval = 0; - - if (f <= 1000000) { - /* less than 1Mhz */ - /* set Channel Reset mode */ - can_set_channel_mode(obj->ch, CH_RESET); - can_set_frequency(obj, f); - /* set Channel Communication mode */ - can_set_channel_mode(obj->ch, CH_COMM); - /* restore CFE bit since it is cleared */ - /* Use send/receive FIFO buffer */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; - *dmy_cfcc |= 0x01; - dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; - *dmy_cfcc |= 0x01; - retval = 1; - } - - return retval; -} - -void can_reset(can_t *obj) { - /* Enter global reset mode */ - can_set_global_mode(GL_RESET); - /* Enter channel reset mode */ - can_set_channel_mode(obj->ch, CH_RESET); - /* reset register */ - can_reset_reg(obj); - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); -} - -int can_write(can_t *obj, CAN_Message msg, int cc) { - __IO uint32_t *dmy_sts; - __IO uint32_t *dmy_cfsts; - __IO uint32_t *dmy_cfid; - __IO uint32_t *dmy_cfptr; - __IO uint32_t *dmy_cfdf0; - __IO uint32_t *dmy_cfdf1; - __IO uint32_t *dmy_cfpctr; - int retval = 0; - - /* Wait to become channel communication mode */ - dmy_sts = STS_MATCH[obj->ch]; - while ((*dmy_sts & 0x07) != 0) { - __NOP(); - } - - if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) { - /* send/receive FIFO buffer isn't full */ - dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND]; - if ((*dmy_cfsts & 0x02) != 0x02) { - /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */ - dmy_cfid = CFID_TBL[obj->ch][CAN_SEND]; - *dmy_cfid = ((msg.format << 31) | (msg.type << 30)); - if (msg.format == CANStandard) { - *dmy_cfid |= (msg.id & 0x07FF); - } else { - *dmy_cfid |= (msg.id & 0x1FFFFFFF); - } - /* set length */ - dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND]; - *dmy_cfptr = msg.len << 28; - /* set data */ - dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND]; - memcpy((void *)dmy_cfdf0, &msg.data[0], 4); - dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND]; - memcpy((void *)dmy_cfdf1, &msg.data[4], 4); - /* send request */ - dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND]; - *dmy_cfpctr = 0xFF; - retval = 1; - } - } - - return retval; -} - -int can_read(can_t *obj, CAN_Message *msg, int handle) { - __IO uint32_t *dmy_sts; - __IO uint32_t *dmy_cfsts; - __IO uint32_t *dmy_cfid; - __IO uint32_t *dmy_cfptr; - __IO uint32_t *dmy_cfdf0; - __IO uint32_t *dmy_cfdf1; - __IO uint32_t *dmy_cfpctr; - int retval = 0; - - /* Wait to become channel communication mode */ - dmy_sts = STS_MATCH[obj->ch]; - while ((*dmy_sts & 0x07) != 0) { - __NOP(); - } - - /* send/receive FIFO buffer isn't empty */ - dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV]; - while ((*dmy_cfsts & 0x01) != 0x01) { - /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */ - dmy_cfid = CFID_TBL[obj->ch][CAN_RECV]; - msg->format = (CANFormat)(*dmy_cfid >> 31); - msg->type = (CANType)((*dmy_cfid >> 30) & 0x1); - if (msg->format == CANStandard) { - msg->id = (*dmy_cfid & 0x07FF); - } else { - msg->id = (*dmy_cfid & 0x1FFFFFFF); - } - /* get length */ - dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV]; - msg->len = (unsigned char)(*dmy_cfptr >> 28); - /* get data */ - dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV]; - memcpy(&msg->data[0], (void *)dmy_cfdf0, 4); - dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV]; - memcpy(&msg->data[4], (void *)dmy_cfdf1, 4); - /* receive(next data) request */ - dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV]; - *dmy_cfpctr = 0xFF; - retval = 1; - } - - return retval; -} - -unsigned char can_rderror(can_t *obj) { - __IO uint32_t *dmy_sts; - - dmy_sts = STS_MATCH[obj->ch]; - return (unsigned char)((*dmy_sts >> 16) & 0xFF); -} - -unsigned char can_tderror(can_t *obj) { - __IO uint32_t *dmy_sts; - - dmy_sts = STS_MATCH[obj->ch]; - return (unsigned char)((*dmy_sts >> 24) & 0xFF); -} - -int can_mode(can_t *obj, CanMode mode) { - __IO uint32_t *dmy_ctr; - __IO uint32_t *dmy_sts; - __IO uint32_t *dmy_cfcc; - int ch_cnt; - can_t *tmp_obj; - tmp_obj = obj; - int retval = 1; - - switch (mode) { - case MODE_RESET: - can_set_global_mode(GL_RESET); - can_set_channel_mode(obj->ch, CH_RESET); - for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) { - can_initialized[ch_cnt] = 0; - } - break; - case MODE_NORMAL: - can_set_global_mode(GL_OPE); - can_set_channel_mode(obj->ch, CH_COMM); - break; - case MODE_SILENT: - can_set_channel_mode(obj->ch, CH_HOLD); - /* set listen only mode, enable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000); - can_set_channel_mode(obj->ch, CH_COMM); - break; - case MODE_TEST_LOCAL: - can_set_channel_mode(obj->ch, CH_HOLD); - /* set self test mode 0, enable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000); - can_set_channel_mode(obj->ch, CH_COMM); - break; - case MODE_TEST_GLOBAL: - /* set the channel between the communication test on channel 1 and channel 2 */ - /* set Channel Hold mode */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { - dmy_sts = STS_MATCH[tmp_obj->ch]; - if ((*dmy_sts & 0x04) == 0x04) { - /* Channel Stop mode */ - /* clear Channel Stop mode bit */ - dmy_ctr = CTR_MATCH[tmp_obj->ch]; - *dmy_ctr &= 0xFFFFFFFB; - can_set_channel_mode(tmp_obj->ch, CH_RESET); - } - can_set_channel_mode(tmp_obj->ch, CH_HOLD); - } - can_set_global_mode(GL_TEST); - /* enable communication test between channel1 and channel2 */ - RSCAN0GTSTCFG = 0x06; - RSCAN0GTSTCTR = 0x01; - /* send and receive setting of channel1 and channel2 */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { - can_reset_buffer(tmp_obj); - /* set global interrrupt */ - /* THLEIE, MEIE and DEIE interrupts are disable */ - RSCAN0GCTR &= 0xFFFFF8FF; - /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */ - /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */ - dmy_ctr = CTR_MATCH[tmp_obj->ch]; - *dmy_ctr &= 0x00018700; - can_set_global_mode(GL_OPE); - can_set_channel_mode(tmp_obj->ch, CH_COMM); - /* Use send/receive FIFO buffer */ - dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND]; - *dmy_cfcc |= 0x01; - dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV]; - *dmy_cfcc |= 0x01; - } - break; - case MODE_TEST_SILENT: - /* not supported */ - /* fall through */ - default: - retval = 0; - break; - } - - return retval; -} - -int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { - int retval = 0; - - if ((format == CANStandard) || (format == CANExtended)) { - if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) { - /* set Global Reset mode and Channel Reset mode */ - can_set_global_mode(GL_RESET); - can_set_channel_mode(obj->ch, CH_RESET); - /* enable receive rule table writing */ - RSCAN0GAFLECTR = 0x00000100; - /* set the page number of receive rule table(page number = 0) */ - RSCAN0GAFLECTR |= (obj->ch * 4); - /* set IDE format */ - *dmy_gaflid = (format << 31); - if (format == CANExtended) { - /* set receive rule ID for bit28-0 */ - *dmy_gaflid |= (id & 0x1FFFFFFF); - } else { - /* set receive rule ID for bit10-0 */ - *dmy_gaflid |= (id & 0x07FF); - } - /* set ID mask bit */ - *dmy_gaflm = (0xC0000000 | mask); - /* disable receive rule table writing */ - RSCAN0GAFLECTR &= 0xFFFFFEFF; - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); - retval = 1; - } - } - - return retval; -} - -void can_monitor(can_t *obj, int silent) { - __IO uint32_t *dmy_ctr; - - /* set Channel Hold mode */ - can_set_channel_mode(obj->ch, CH_HOLD); - if (silent) { - /* set listen only mode, enable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000); - can_set_channel_mode(obj->ch, CH_COMM); - } else { - /* set normal test mode, disable communication test mode */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr &= 0x00FFFFFF; - /* reset register */ - can_reset_reg(obj); - /* reconfigure channel which is already initialized */ - can_reconfigure_channel(); - } -} - -static void can_reset_reg(can_t *obj) { - __IO uint32_t *dmy_ctr; - - /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */ - /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */ - RSCAN0GCFG = 0x00000003; - /* set default frequency at 100k */ - can_set_frequency(obj, 100000); - /* set receive rule */ - can_reset_recv_rule(obj); - /* set buffer */ - can_reset_buffer(obj); - /* set global interrrupt */ - /* THLEIE, MEIE and DEIE interrupts are disable */ - RSCAN0GCTR &= 0xFFFFF8FF; - /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */ - dmy_ctr = CTR_MATCH[obj->ch]; - *dmy_ctr &= 0xFFFF00FF; -} - -static void can_reset_recv_rule(can_t *obj) { - /* number of receive rules of each chanel = 64 */ - RSCAN0GAFLCFG0 = 0x40404040; - RSCAN0GAFLCFG1 = 0x40000000; - /* enable receive rule table writing */ - RSCAN0GAFLECTR = 0x00000100; - /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */ - RSCAN0GAFLECTR |= (obj->ch * 4); - /* set standard ID, data frame and receive rule ID */ - *dmy_gaflid = 0x07FF; - /* IDE bit, RTR bit and ID bit(28-0) are not compared */ - *dmy_gaflm = 0; - /* DLC check is 1 bytes, not use a receive buffer */ - *dmy_gaflp0 = 0x10000000; - /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */ - *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3)); - /* disable receive rule table writing */ - RSCAN0GAFLECTR &= 0xFFFFFEFF; -} - -static void can_reset_buffer(can_t *obj) { - __IO uint32_t *dmy_rfcc; - __IO uint32_t *dmy_cfcc; - __IO uint32_t *dmy_txqcc; - __IO uint32_t *dmy_thlcc; - int cnt; - - /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */ - /* number of rows of send/receive FIFO buffer = 4 */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; - *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; - *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */ - /* receive buffer is not used */ - RSCAN0RMNB = 0; - /* receive FIFO buffer is not used */ - for (cnt = 0; cnt < 8; cnt++) { - dmy_rfcc = RFCC_MATCH[cnt]; - *dmy_rfcc = 0; - } - /* send queue is not used */ - dmy_txqcc = TXQCC_MATCH[obj->ch]; - *dmy_txqcc = 0; - /* send history is not used */ - dmy_thlcc = THLCC_MATCH[obj->ch]; - *dmy_thlcc = 0; - - /* CFTXIE and CFRXIE interrupts are enable */ - dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND]; - *dmy_cfcc |= 0x04; - dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV]; - *dmy_cfcc |= 0x02; - /* TMIEp interrupt is disable */ - RSCAN0TMIEC0 = 0x00000000; - RSCAN0TMIEC1 = 0x00000000; - RSCAN0TMIEC2 = 0x00000000; -} - -static void can_reconfigure_channel(void) { - __IO uint32_t *dmy_cfcc; - int ch_cnt; - - for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) { - if (can_initialized[ch_cnt] == 1) { - /* set Global Operation mode and Channel Communication mode */ - can_set_global_mode(GL_OPE); - can_set_channel_mode(ch_cnt, CH_COMM); - /* Use send/receive FIFO buffer */ - dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND]; - *dmy_cfcc |= 0x01; - dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV]; - *dmy_cfcc |= 0x01; - } - } -} - -static void can_set_frequency(can_t *obj, int f) { - __IO uint32_t *dmy_cfg; - int oldfreq = 0; - int newfreq = 0; - uint32_t clkc_val; - uint8_t tmp_tq; - uint8_t tq = 0; - uint8_t tmp_brp; - uint8_t brp = 0; - uint8_t tseg1 = 0; - uint8_t tseg2 = 0; - uint8_t sjw = 0; - - /* set clkc */ - if (RZ_A1_IsClockMode0() == false) { - clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2; - } else { - clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2; - } - /* calculate BRP bit and Choose max value of calculated frequency */ - for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) { - /* f = fCAN / ((BRP+1) * Tq) */ - /* BRP = (fCAN / (f * Tq)) - 1 */ - tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry) - newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq); - if (newfreq >= oldfreq) { - oldfreq = newfreq; - tq = tmp_tq; - brp = tmp_brp; - } - } - /* calculate TSEG1 bit and TSEG2 bit */ - tseg1 = (tq - 1) * 0.666666667; - tseg2 = (tq - 1) - tseg1; - sjw = (tseg2 > 4)? 4 : tseg2; - /* set RSCAN0CmCFG register */ - dmy_cfg = CFG_MATCH[obj->ch]; - *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp; -} - -static void can_set_global_mode(int mode) { - /* set Global mode */ - RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode); - /* Wait to cahnge into Global XXXX mode */ - while ((RSCAN0GSTS & 0x07) != mode) { - __NOP(); - } -} - -static void can_set_channel_mode(uint32_t ch, int mode) { - __IO uint32_t *dmy_ctr; - __IO uint32_t *dmy_sts; - - /* set Channel mode */ - dmy_ctr = CTR_MATCH[ch]; - *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode); - /* Wait to cahnge into Channel XXXX mode */ - dmy_sts = STS_MATCH[ch]; - while ((*dmy_sts & 0x07) != mode) { - __NOP(); - } -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/ethernet_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/ethernet_api.c deleted file mode 100644 index de43879c16..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/ethernet_api.c +++ /dev/null @@ -1,695 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "ethernet_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "ether_iodefine.h" -#include "ethernetext_api.h" - -/* Descriptor info */ -#define NUM_OF_TX_DESCRIPTOR (16) -#define NUM_OF_RX_DESCRIPTOR (16) -#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */ -#define MAX_SEND_SIZE (1514) -/* Ethernet Descriptor Value Define */ -#define TD0_TFP_TOP_BOTTOM (0x30000000) -#define TD0_TACT (0x80000000) -#define TD0_TDLE (0x40000000) -#define RD0_RACT (0x80000000) -#define RD0_RDLE (0x40000000) -#define RD0_RFE (0x08000000) -#define RD0_RCSE (0x04000000) -#define RD0_RFS (0x03FF0000) -#define RD0_RCS (0x0000FFFF) -#define RD0_RFS_RFOF (0x02000000) -#define RD0_RFS_RUAF (0x00400000) -#define RD0_RFS_RRF (0x00100000) -#define RD0_RFS_RTLF (0x00080000) -#define RD0_RFS_RTSF (0x00040000) -#define RD0_RFS_PRE (0x00020000) -#define RD0_RFS_CERF (0x00010000) -#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \ - RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF) -#define RD1_RDL_MSK (0x0000FFFF) -/* PHY Register */ -#define BASIC_MODE_CONTROL_REG (0) -#define BASIC_MODE_STATUS_REG (1) -#define PHY_IDENTIFIER1_REG (2) -#define PHY_IDENTIFIER2_REG (3) -#define PHY_SP_CTL_STS_REG (31) -/* MII management interface access */ -#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */ -#define PHY_ST (1) -#define PHY_WRITE (1) -#define PHY_READ (2) -#define MDC_WAIT (6) /* 400ns/4 */ -#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */ -#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */ -#define M_PHY_ID (0xFFFFFFF0) -#define PHY_ID_LAN8710A (0x0007C0F0) -/* ETHERPIR0 */ -#define PIR0_MDI (0x00000008) -#define PIR0_MDO (0x00000004) -#define PIR0_MMD (0x00000002) -#define PIR0_MDC (0x00000001) -#define PIR0_MDC_HIGH (0x00000001) -#define PIR0_MDC_LOW (0x00000000) -/* ETHEREDRRR0 */ -#define EDRRR0_RR (0x00000001) -/* ETHEREDTRR0 */ -#define EDTRR0_TR (0x00000003) -/* software wait */ -#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ - -#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ - /* 0x00040000 : Detect frame reception */ - /* 0x00010000 : Receive FIFO overflow */ - /* 0x00000010 : Residual bit frame reception */ - /* 0x00000008 : Long frame reception */ - /* 0x00000004 : Short frame reception */ - /* 0x00000002 : PHY-LSI reception error */ - /* 0x00000001 : Receive frame CRC error */ -#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ - -/* Send descriptor */ -typedef struct tag_edmac_send_desc { - uint32_t td0; - uint32_t td1; - uint8_t *td2; - uint32_t padding4; -} edmac_send_desc_t; - -/* Receive descriptor */ -typedef struct tag_edmac_recv_desc { - uint32_t rd0; - uint32_t rd1; - uint8_t *rd2; - uint32_t padding4; -} edmac_recv_desc_t; - -/* memory */ -/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */ -/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */ -#if defined(__ICCARM__) -#pragma data_alignment=16 -static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned! - @ ".mirrorram"; -#else -static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] - __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! -#endif -static int32_t rx_read_offset; /* read offset */ -static int32_t tx_wite_offset; /* write offset */ -static uint32_t send_top_index; -static uint32_t recv_top_index; -static int32_t Interrupt_priority; -static edmac_send_desc_t *p_eth_desc_dsend = NULL; -static edmac_recv_desc_t *p_eth_desc_drecv = NULL; -static edmac_recv_desc_t *p_recv_end_desc = NULL; -static ethernetext_cb_fnc *p_recv_cb_fnc = NULL; -static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */ -static uint32_t phy_id = 0; -static uint32_t start_stop = 1; /* 0:stop 1:start */ - -/* function */ -static void lan_reg_reset(void); -static void lan_desc_create(void); -static void lan_reg_set(int32_t link); -static uint16_t phy_reg_read(uint16_t reg_addr); -static void phy_reg_write(uint16_t reg_addr, uint16_t data); -static void mii_preamble(void); -static void mii_cmd(uint16_t reg_addr, uint32_t option); -static void mii_reg_read(uint16_t *data); -static void mii_reg_write(uint16_t data); -static void mii_z(void); -static void mii_write_1(void); -static void mii_write_0(void); -static void set_ether_pir(uint32_t set_data); -static void wait_100us(int32_t wait_cnt); - - -int ethernetext_init(ethernet_cfg_t *p_ethcfg) { - int32_t i; - uint16_t val; - - CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ - - /* -->4F<-- P1_14(ET_COL) */ - GPIOPMC1 |= 0x4000; - GPIOPFCAE1 &= ~0x4000; - GPIOPFCE1 |= 0x4000; - GPIOPFC1 |= 0x4000; - GPIOPIPC1 |= 0x4000; - - /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0), - P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */ - GPIOPMC2 |= 0x0FFF; - GPIOPFCAE2 &= ~0x0FFF; - GPIOPFCE2 &= ~0x0FFF; - GPIOPFC2 |= 0x0FFF; - GPIOPIPC2 |= 0x0FFF; - - /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ - GPIOPMC3 |= 0x0078; - GPIOPFCAE3 &= ~0x0078; - GPIOPFCE3 &= ~0x0078; - GPIOPFC3 |= 0x0078; - GPIOPIPC3 |= 0x0078; - - /* -->3F<-- P7_0(ET_MDC) */ - GPIOPMC7 |= 0x0001; - GPIOPFCAE7 &= ~0x0001; - GPIOPFCE7 |= 0x0001; - GPIOPFC7 &= ~0x0001; - GPIOPIPC7 |= 0x0001; - - /* Resets the E-MAC,E-DMAC */ - lan_reg_reset(); - - /* Resets the PHY-LSI */ - phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); - for (i = 10000; i > 0; i--) { - val = phy_reg_read(BASIC_MODE_CONTROL_REG); - if (((uint32_t)val & 0x8000uL) == 0) { - break; /* Reset complete */ - } - } - - phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) - | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); - - Interrupt_priority = p_ethcfg->int_priority; - p_recv_cb_fnc = p_ethcfg->recv_cb; - start_stop = 1; - - if (p_ethcfg->ether_mac != NULL) { - (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr)); - } else { - ethernet_address(mac_addr); /* Get MAC Address */ - } - - return 0; -} - -void ethernetext_start_stop(int32_t mode) { - if (mode == 1) { - /* start */ - ETHEREDTRR0 |= EDTRR0_TR; - ETHEREDRRR0 |= EDRRR0_RR; - start_stop = 1; - } else { - /* stop */ - ETHEREDTRR0 &= ~EDTRR0_TR; - ETHEREDRRR0 &= ~EDRRR0_RR; - start_stop = 0; - } -} - -int ethernetext_chk_link_mode(void) { - int32_t link; - uint16_t data; - - if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) { - data = phy_reg_read(PHY_SP_CTL_STS_REG); - switch (((uint32_t)data >> 2) & 0x00000007) { - case 0x0001: - link = HALF_10M; - break; - case 0x0005: - link = FULL_10M; - break; - case 0x0002: - link = HALF_TX; - break; - case 0x0006: - link = FULL_TX; - break; - default: - link = NEGO_FAIL; - break; - } - } else { - link = NEGO_FAIL; - } - - return link; -} - -void ethernetext_set_link_mode(int32_t link) { - lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ - lan_desc_create(); /* Initialize of buffer memory */ - lan_reg_set(link); /* E-DMAC, E-MAC initialization */ -} - -int ethernet_init() { - ethernet_cfg_t ethcfg; - - ethcfg.int_priority = 5; - ethcfg.recv_cb = NULL; - ethcfg.ether_mac = NULL; - ethernetext_init(ðcfg); - ethernet_set_link(-1, 0); /* Auto-Negotiation */ - - return 0; -} - -void ethernet_free() { - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ -} - -int ethernet_write(const char *data, int slen) { - edmac_send_desc_t *p_send_desc; - int32_t copy_size; - - if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) - || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { - copy_size = 0; - } else { - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - if ((p_send_desc->td0 & TD0_TACT) != 0) { - copy_size = 0; - } else { - copy_size = MAX_SEND_SIZE - tx_wite_offset; - if (copy_size > slen) { - copy_size = slen; - } - (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size); - tx_wite_offset += copy_size; - } - } - - return copy_size; -} - -int ethernet_send() { - edmac_send_desc_t *p_send_desc; - int32_t ret; - - if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) { - ret = 0; - } else { - /* Transfer 1 frame */ - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - - /* Sets the frame length */ - p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16); - tx_wite_offset = 0; - - /* Sets the transmit descriptor to transmit again */ - p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM); - p_send_desc->td0 |= TD0_TACT; - if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) { - ETHEREDTRR0 |= EDTRR0_TR; - } - - /* Update the current descriptor */ - send_top_index++; - if (send_top_index >= NUM_OF_TX_DESCRIPTOR) { - send_top_index = 0; - } - ret = 1; - } - - return ret; -} - -int ethernet_receive() { - edmac_recv_desc_t *p_recv_desc; - int32_t receive_size = 0; - - if (p_eth_desc_drecv != NULL) { - if (p_recv_end_desc != NULL) { - /* Sets the receive descriptor to receive again */ - p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_end_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - p_recv_end_desc = NULL; - } - - p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */ - if ((p_recv_desc->rd0 & RD0_RACT) == 0) { - /* Receives 1 frame */ - if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) { - /* Receive frame error */ - /* Sets the receive descriptor to receive again */ - p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - } else { - /* Copies the received frame */ - rx_read_offset = 0; - p_recv_end_desc = p_recv_desc; - receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */ - } - - /* Update the current descriptor */ - recv_top_index++; - if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) { - recv_top_index = 0; - } - } - } - - return receive_size; -} - -int ethernet_read(char *data, int dlen) { - edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ - int32_t copy_size; - - if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) { - copy_size = 0; - } else { - copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset; - if (copy_size > dlen) { - copy_size = dlen; - } - (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size); - rx_read_offset += copy_size; - } - - return copy_size; -} - -void ethernet_address(char *mac) { - if (mac != NULL) { - mbed_mac_address(mac); /* Get MAC Address */ - } -} - -int ethernet_link(void) { - int32_t ret; - uint16_t data; - - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) { - ret = 1; - } else { - ret = 0; - } - - return ret; -} - -void ethernet_set_link(int speed, int duplex) { - uint16_t data; - int32_t i; - int32_t link; - - if ((speed < 0) || (speed > 1)) { - data = 0x1000; /* Auto-Negotiation Enable */ - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - for (i = 0; i < 1000; i++) { - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) { - break; - } - wait_100us(10); - } - } else { - data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8)); - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - wait_100us(1); - } - - link = ethernetext_chk_link_mode(); - ethernetext_set_link_mode(link); -} - -void INT_Ether(void) { - uint32_t stat_edmac; - uint32_t stat_etherc; - - /* Clear the interrupt request flag */ - stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */ - ETHEREESR0 = stat_edmac; - /* Reception-related */ - if (stat_edmac & EDMAC_EESIPR_INI_RECV) { - if (p_recv_cb_fnc != NULL) { - p_recv_cb_fnc(); - } - } - /* E-MAC-related */ - if (stat_edmac & EDMAC_EESIPR_INI_EtherC) { - /* Clear the interrupt request flag */ - stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */ - ETHERECSR0 = stat_etherc; - } -} - -static void lan_reg_reset(void) { - volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ - - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - while (j--) { - /* Do Nothing */ - } - - ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */ - ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */ - - /* Check clear software reset */ - while ((ETHEREDMR0 & 0x00000003) != 0) { - /* Do Nothing */ - } -} - -static void lan_desc_create(void) { - int32_t i; - uint8_t *p_memory_top; - - (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory)); - p_memory_top = ethernet_nc_memory; - - /* Descriptor area configuration */ - p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR); - p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR); - - /* Transmit descriptor */ - for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) { - p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */ - p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */ - } - p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */ - - /* Receive descriptor */ - for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) { - p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */ - p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */ - } - p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */ - - /* Initialize descriptor management information */ - send_top_index = 0; - recv_top_index = 0; - rx_read_offset = 0; - tx_wite_offset = 0; - p_recv_end_desc = NULL; -} - -static void lan_reg_set(int32_t link) { - /* MAC address setting */ - ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24) - | ((uint32_t)mac_addr[1] << 16) - | ((uint32_t)mac_addr[2] << 8) - | (uint32_t)mac_addr[3]; - ETHERMALR0 = ((uint32_t)mac_addr[4] << 8) - | (uint32_t)mac_addr[5]; - - /* E-DMAC */ - ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1]; - ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1]; - ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */ - ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */ - ETHEREDMR0 |= 0x00000040; /* Little endian */ - ETHERTRSCER0 &= ~0x0003009F; /* All clear */ - ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */ - ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */ - ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */ - ETHERFCFTR0 &= ~0x001F00FF; - ETHERFCFTR0 |= 0x00070007; - ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */ - - /* E-MAC */ - ETHERECMR0 &= ~0x04BF2063; /* All clear */ - ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */ - ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */ - ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */ - ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */ - ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */ - if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) { - ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */ - } else { - ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */ - } - - /* Interrupt-related */ - if (p_recv_cb_fnc != NULL) { - ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */ - ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */ - ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */ - ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ - InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ - GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ - GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ - } - - ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */ - - /* Enable transmission/reception */ - if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) { - ETHEREDRRR0 |= 0x00000001; /* RR */ - } -} - -static uint16_t phy_reg_read(uint16_t reg_addr) { - uint16_t data; - - mii_preamble(); - mii_cmd(reg_addr, PHY_READ); - mii_z(); - mii_reg_read(&data); - mii_z(); - - return data; -} - -static void phy_reg_write(uint16_t reg_addr, uint16_t data) { - mii_preamble(); - mii_cmd(reg_addr, PHY_WRITE); - mii_write_1(); - mii_write_0(); - mii_reg_write(data); - mii_z(); -} - -static void mii_preamble(void) { - int32_t i = 32; - - for (i = 32; i > 0; i--) { - /* 1 is output via the MII (Media Independent Interface) block. */ - mii_write_1(); - } -} - -static void mii_cmd(uint16_t reg_addr, uint32_t option) { - int32_t i; - uint16_t data = 0; - - data |= (PHY_ST << 14); /* ST code */ - data |= (option << 12); /* OP code */ - data |= (PHY_ADDR << 7); /* PHY Address */ - data |= (uint16_t)(reg_addr << 2); /* Reg Address */ - for (i = 14; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_reg_read(uint16_t *data) { - int32_t i; - uint16_t reg_data = 0; - - /* Data are read in one bit at a time */ - for (i = 16; i > 0; i--) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - reg_data <<= 1; - reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */ - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); - } - *data = reg_data; -} - -static void mii_reg_write(uint16_t data) { - int32_t i; - - /* Data are written one bit at a time */ - for (i = 16; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_z(void) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); -} - -static void mii_write_1(void) { - set_ether_pir(PIR0_MDO | PIR0_MMD); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD); -} - -static void mii_write_0(void) { - set_ether_pir(PIR0_MMD); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD); -} - -static void set_ether_pir(uint32_t set_data) { - int32_t i; - - for (i = MDC_WAIT; i > 0; i--) { - ETHERPIR0 = set_data; - } -} - -static void wait_100us(int32_t wait_cnt) { - volatile int32_t j = LOOP_100us * wait_cnt; - - while (--j) { - /* Do Nothing */ - } -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_irq_api.c deleted file mode 100644 index d6be236949..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_irq_api.c +++ /dev/null @@ -1,223 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "gpio_irq_api.h" -#include "intc_iodefine.h" -#include "pinmap.h" -#include "cmsis.h" -#include "gpio_addrdefine.h" - -#define CHANNEL_NUM 8 - -static void gpio_irq0(void); -static void gpio_irq1(void); -static void gpio_irq2(void); -static void gpio_irq3(void); -static void gpio_irq4(void); -static void gpio_irq5(void); -static void gpio_irq6(void); -static void gpio_irq7(void); - -static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL}; -static gpio_irq_handler irq_handler; -static const int nIRQn_h = 32; -extern PinName gpio_multi_guard; - -enum { - IRQ0,IRQ1, - IRQ2,IRQ3, - IRQ4,IRQ5, - IRQ6,IRQ7, - -} IRQNo; - -static const IRQHandler irq_tbl[CHANNEL_NUM] = { - &gpio_irq0, - &gpio_irq1, - &gpio_irq2, - &gpio_irq3, - &gpio_irq4, - &gpio_irq5, - &gpio_irq6, - &gpio_irq7, -}; - -#ifdef MAX_PERI -static const PinMap PinMap_IRQ[] = { - {P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4}, - {P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8}, - {P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4}, - {P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4}, - {P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4}, - {P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, - {P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8}, - {NC, NC, 0} -}; -#else -static const PinMap PinMap_IRQ[] = { - {P9_1, IRQ0, 4}, - {P7_8, IRQ1, 8}, - {P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P1_9, IRQ3, 3}, - {P1_4, IRQ4, 4}, {P1_10, IRQ4, 3}, - {P1_5, IRQ5, 4}, {P1_11, IRQ5, 3}, - {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6}, - {NC, NC, 0} -}; -#endif - -static void handle_interrupt_in(int irq_num) { - uint16_t irqs; - uint16_t edge_req; - gpio_irq_t *obj; - gpio_irq_event irq_event; - - irqs = INTCIRQRR; - if (irqs & (1 << irq_num)) { - obj = channel_obj[irq_num]; - if (obj != NULL) { - edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3); - if (edge_req == 1) { - irq_event = IRQ_FALL; - } else if (edge_req == 2) { - irq_event = IRQ_RISE; - } else { - uint32_t mask = (1 << (obj->pin & 0x0F)); - __I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin)); - - if ((*reg_in & mask) == 0) { - irq_event = IRQ_FALL; - } else { - irq_event = IRQ_RISE; - } - } - irq_handler(obj->port, irq_event); - } - INTCIRQRR &= ~(1 << irq_num); - } -} - -static void gpio_irq0(void) { - handle_interrupt_in(0); -} - -static void gpio_irq1(void) { - handle_interrupt_in(1); -} - -static void gpio_irq2(void) { - handle_interrupt_in(2); -} - -static void gpio_irq3(void) { - handle_interrupt_in(3); -} - -static void gpio_irq4(void) { - handle_interrupt_in(4); -} - -static void gpio_irq5(void) { - handle_interrupt_in(5); -} - -static void gpio_irq6(void) { - handle_interrupt_in(6); -} - -static void gpio_irq7(void) { - handle_interrupt_in(7); -} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - int shift; - if (pin == NC) return -1; - - obj->ch = pinmap_peripheral(pin, PinMap_IRQ); - obj->pin = (int)pin ; - obj->port = (int)id ; - - shift = obj->ch*2; - channel_obj[obj->ch] = obj; - irq_handler = handler; - - pinmap_pinout(pin, PinMap_IRQ); - gpio_multi_guard = pin; /* Set multi guard */ - - // INTC settings - InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]); - INTCICR1 &= ~(0x3 << shift); - INTCICR1 |= (0x3 << shift); - GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5); - GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); - obj->int_enable = 1; - __enable_irq(); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_obj[obj->ch] = NULL; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - int shift = obj->ch*2; - uint16_t val = event == IRQ_RISE ? 2 : - event == IRQ_FALL ? 1 : 0; - uint16_t work_icr_val; - - /* check edge interrupt setting */ - work_icr_val = INTCICR1; - if (enable == 1) { - /* Set interrupt serect */ - work_icr_val |= (val << shift); - } else { - /* Clear interrupt serect */ - work_icr_val &= ~(val << shift); - } - - if ((work_icr_val & (3 << shift)) == 0) { - /* No edge interrupt setting */ - GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch)); - /* Clear Interrupt flags */ - INTCIRQRR &= ~(1 << obj->ch); - INTCICR1 = work_icr_val; - } else if (obj->int_enable == 1) { - INTCICR1 = work_icr_val; - GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); - } else { - INTCICR1 = work_icr_val; - } -} - -void gpio_irq_enable(gpio_irq_t *obj) { - int shift = obj->ch*2; - uint16_t work_icr_val = INTCICR1; - - /* check edge interrupt setting */ - if ((work_icr_val & (3 << shift)) != 0) { - GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); - } - obj->int_enable = 1; -} - -void gpio_irq_disable(gpio_irq_t *obj) { - GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch)); - obj->int_enable = 0; -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c deleted file mode 100644 index 4904faa978..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c +++ /dev/null @@ -1,760 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "r_typedefs.h" - -#include "riic_iodefine.h" -#include "RZ_A1_Init.h" -#include "VKRZA1H.h" - -volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; - -#define REG(N) \ - RIIC[obj->i2c]->RIICn##N - -/* RIICnCR1 */ -#define CR1_RST (1 << 6) -#define CR1_ICE (1 << 7) - -/* RIICnCR2 */ -#define CR2_ST (1 << 1) -#define CR2_RS (1 << 2) -#define CR2_SP (1 << 3) -#define CR2_TRS (1 << 5) -#define CR2_BBSY (1 << 7) - -/* RIICnMR3 */ -#define MR3_ACKBT (1 << 3) -#define MR3_ACKWP (1 << 4) -#define MR3_WAIT (1 << 6) - -/* RIICnSER */ -#define SER_SAR0E (1 << 0) - -/* RIICnSR1 */ -#define SR1_AAS0 (1 << 0) - -/* RIICnSR2 */ -#define SR2_START (1 << 2) -#define SR2_STOP (1 << 3) -#define SR2_NACKF (1 << 4) -#define SR2_RDRF (1 << 5) -#define SR2_TEND (1 << 6) -#define SR2_TDRE (1 << 7) - -#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ - -static const PinMap PinMap_I2C_SDA[] = { - {P1_1 , I2C_0, 1}, - {P1_3 , I2C_1, 1}, - {P1_5 , I2C_2, 1}, - {P1_7 , I2C_3, 1}, - {NC , NC , 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {P1_0 , I2C_0, 1}, - {P1_2 , I2C_1, 1}, - {P1_4 , I2C_2, 1}, - {P1_6 , I2C_3, 1}, - {NC , NC, 0} -}; - - -static inline int i2c_status(i2c_t *obj) { - return REG(SR2.UINT8[0]); -} - -static void i2c_reg_reset(i2c_t *obj) { - /* full reset */ - REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off - REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on - REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on - - REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack) - REG(SER.UINT8[0]) = 0x00; // no slave addr enabled - - /* set frequency */ - REG(MR1.UINT8[0]) |= obj->pclk_bit; - REG(BRL.UINT8[0]) = obj->width_low; - REG(BRH.UINT8[0]) = obj->width_hi; - - REG(MR2.UINT8[0]) = 0x07; - REG(MR3.UINT8[0]) = 0x00; - - REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT - REG(IER.UINT8[0]) = 0x00; // no interrupt - - REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset -} - -static inline int i2c_wait_RDRF(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_RDRF) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_wait_TDRE(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_TDRE) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_wait_TEND(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_TEND) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - - -static int i2c_wait_START(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_START) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_wait_STOP(i2c_t *obj) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_STOP) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - - return 0; -} - -static int i2c_set_STOP(i2c_t *obj) { - /* SR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; - /* Stop condition */ - REG(CR2.UINT32) |= CR2_SP; - - return 0; -} - -static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { - /* SR2.NACKF = 0 */ - REG(SR2.UINT32) &= ~SR2_NACKF; - /* SR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; -} - -static void i2c_set_MR3_NACK(i2c_t *obj) { - /* send a NOT ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) |= MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; -} - -static void i2c_set_MR3_ACK(i2c_t *obj) { - /* send a ACK */ - REG(MR3.UINT32) |= MR3_ACKWP; - REG(MR3.UINT32) &= ~MR3_ACKBT; - REG(MR3.UINT32) &= ~MR3_ACKWP; -} - -static inline void i2c_power_enable(i2c_t *obj) { - volatile uint8_t dummy; - switch ((int)obj->i2c) { - case I2C_0: - CPGSTBCR9 &= ~(0x80); - break; - case I2C_1: - CPGSTBCR9 &= ~(0x40); - break; - case I2C_2: - CPGSTBCR9 &= ~(0x20); - break; - case I2C_3: - CPGSTBCR9 &= ~(0x10); - break; - } - dummy = CPGSTBCR9; -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - /* determine the I2C to use */ - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->i2c = pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->i2c != NC); - - /* enable power */ - i2c_power_enable(obj); - - /* set default frequency at 100k */ - i2c_frequency(obj, 100000); - - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - - obj->last_stop_flag = 1; -} - -inline int i2c_start(i2c_t *obj) { - int timeout = 0; - - while ((REG(CR2.UINT32) & CR2_BBSY) != 0) { - timeout ++; - if (timeout >= obj->bbsy_wait_cnt) { - break; - } - } - /* Start Condition */ - REG(CR2.UINT8[0]) |= CR2_ST; - - return 0; -} - -static inline int i2c_restart(i2c_t *obj) { - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - /* ReStart condition */ - REG(CR2.UINT32) |= CR2_RS; - - return 0; -} - -inline int i2c_stop(i2c_t *obj) { - (void)i2c_set_STOP(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - - return 0; -} - -static void i2c_set_err_noslave(i2c_t *obj) { - (void)i2c_set_STOP(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - obj->last_stop_flag = 1; -} - -static inline int i2c_do_write(i2c_t *obj, int value) { - int timeout = 0; - - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while ((i2c_status(obj) & SR2_TDRE) == 0) { - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - /* write the data */ - REG(DRT.UINT32) = value; - - return 0; -} - -static inline int i2c_read_address_write(i2c_t *obj, int value) { - int status; - - status = i2c_wait_TDRE(obj); - if (status == 0) { - /* write the data */ - REG(DRT.UINT32) = value; - } - - return status; - -} - -static inline int i2c_do_read(i2c_t *obj, int last) { - if (last == 2) { - /* this time is befor last byte read */ - /* Set MR3 WAIT bit is 1 */; - REG(MR3.UINT32) |= MR3_WAIT; - } else if (last == 1) { - i2c_set_MR3_NACK(obj); - } else { - i2c_set_MR3_ACK(obj); - } - - /* return the data */ - return (REG(DRR.UINT32) & 0xFF); -} - -void i2c_frequency(i2c_t *obj, int hz) { - float64_t pclk_val; - float64_t wait_utime; - volatile float64_t bps; - volatile float64_t L_time; /* H Width period */ - volatile float64_t H_time; /* L Width period */ - uint32_t tmp_L_width; - uint32_t tmp_H_width; - uint32_t remainder; - uint32_t wk_cks = 0; - - /* set PCLK */ - if (false == RZ_A1_IsClockMode0()) { - pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK; - } else { - pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK; - } - - /* Min 10kHz, Max 400kHz */ - if (hz < 10000) { - bps = 10000; - } else if (hz > 400000) { - bps = 400000; - } else { - bps = (float64_t)hz; - } - - /* Calculation L width time */ - L_time = (1 / (2 * bps)); /* Harf period of frequency */ - H_time = L_time; - - /* Check I2C mode of Speed */ - if (bps > 100000) { - /* Fast-mode */ - L_time -= 102E-9; /* Falling time of SCL clock. */ - H_time -= 138E-9; /* Rising time of SCL clock. */ - /* Check L wideth */ - if (L_time < 1.3E-6) { - /* Wnen L width less than 1.3us */ - /* Subtract Rise up and down time for SCL from H/L width */ - L_time = 1.3E-6; - H_time = (1 / bps) - L_time - 138E-9 - 102E-9; - } - } - - tmp_L_width = (uint32_t)(L_time * pclk_val * 10); - tmp_L_width >>= 1; - wk_cks++; - while (tmp_L_width >= 341) { - tmp_L_width >>= 1; - wk_cks++; - } - remainder = tmp_L_width % 10; - tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */ - - tmp_H_width = (uint32_t)(H_time * pclk_val * 10); - tmp_H_width >>= wk_cks; - if (remainder == 0) { - tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */ - } else { - remainder += tmp_H_width % 10; - tmp_H_width = (tmp_H_width / 10) - 3; - if (remainder > 10) { - tmp_H_width += 1; /* fine adjustment */ - } - } - /* timeout of BBSY bit is minimum low width by frequency */ - /* so timeout calculates "(low width) * 2" by frequency */ - wait_utime = (L_time * 2) * 1000000; - /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */ - if (wait_utime <= 0.3) { - obj->bbsy_wait_cnt = 1; - } else { - obj->bbsy_wait_cnt = (int)(wait_utime / 0.3); - } - - - /* I2C Rate */ - obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ - obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0); - obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0); - - /* full reset */ - i2c_reg_reset(obj); -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count = 0; - int status; - int value; - volatile uint32_t work_reg = 0; - - i2c_set_MR3_ACK(obj); - /* There is a STOP condition for last processing */ - if (obj->last_stop_flag != 0) { - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; - } - } - obj->last_stop_flag = stop; - /* Send Slave address */ - status = i2c_read_address_write(obj, (address | 0x01)); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* wait RDRF */ - status = i2c_wait_RDRF(obj); - /* check ACK/NACK */ - if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { - /* Slave sends NACK */ - (void)i2c_set_STOP(obj); - /* dummy read */ - value = REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - obj->last_stop_flag = 1; - return I2C_ERROR_NO_SLAVE; - } - if (length != 0) { - /* Read in all except last byte */ - if (length > 2) { - /* dummy read */ - value = REG(DRR.UINT32); - for (count = 0; count < (length - 1); count++) { - /* wait for it to arrive */ - status = i2c_wait_RDRF(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* Recieve the data */ - if (count == (length - 2)) { - value = i2c_do_read(obj, 1); - } else if ((length >= 3) && (count == (length - 3))) { - value = i2c_do_read(obj, 2); - } else { - value = i2c_do_read(obj, 0); - } - data[count] = (char)value; - } - } else if (length == 2) { - /* Set MR3 WAIT bit is 1 */ - REG(MR3.UINT32) |= MR3_WAIT; - /* dummy read */ - value = REG(DRR.UINT32); - /* wait for it to arrive */ - status = i2c_wait_RDRF(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - i2c_set_MR3_NACK(obj); - data[count] = (char)REG(DRR.UINT32); - count++; - } else { - /* length == 1 */ - /* Set MR3 WAIT bit is 1 */; - REG(MR3.UINT32) |= MR3_WAIT; - i2c_set_MR3_NACK(obj); - /* dummy read */ - value = REG(DRR.UINT32); - } - /* wait for it to arrive */ - status = i2c_wait_RDRF(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - - /* If not repeated start, send stop. */ - if (stop) { - (void)i2c_set_STOP(obj); - /* RIICnDRR read */ - value = (REG(DRR.UINT32) & 0xFF); - data[count] = (char)value; - /* RIICnMR3.WAIT = 0 */ - REG(MR3.UINT32) &= ~MR3_WAIT; - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - /* RIICnDRR read */ - value = (REG(DRR.UINT32) & 0xFF); - data[count] = (char)value; - /* RIICnMR3.WAIT = 0 */ - REG(MR3.UINT32) &= ~MR3_WAIT; - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } - } else { - /* If not repeated start, send stop. */ - if (stop) { - (void)i2c_set_STOP(obj); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - } else { - (void)i2c_restart(obj); - (void)i2c_wait_START(obj); - /* SR2.START = 0 */ - REG(SR2.UINT32) &= ~SR2_START; - } - } - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int cnt; - int status; - - /* There is a STOP condition for last processing */ - if (obj->last_stop_flag != 0) { - status = i2c_start(obj); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_BUS_BUSY; - } - } - obj->last_stop_flag = stop; - /* Send Slave address */ - status = i2c_do_write(obj, address); - if (status != 0) { - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* Wait send end */ - status = i2c_wait_TEND(obj); - if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { - /* Slave sends NACK */ - i2c_set_err_noslave(obj); - return I2C_ERROR_NO_SLAVE; - } - /* Send Write data */ - for (cnt=0; cnt= WAIT_TIMEOUT) { - return ack; - } - } - /* check ACK/NACK */ - if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { - /* NACK */ - i2c_set_SR2_NACKF_STOP(obj); - } else { - ack = 1; - } - } - - return ack; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - if (enable_slave != 0) { - REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled - } else { - REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled - } -} - -int i2c_slave_receive(i2c_t *obj) { - int status; - int retval; - - status = (REG(SR1.UINT8[0]) & SR1_AAS0); - status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4; - - switch(status) { - case 0x01: - /* the master is writing to this slave */ - retval = 3; - break; - case 0x02: - /* the master is writing to all slave */ - retval = 2; - break; - case 0x03: - /* the master has requested a read from this slave */ - retval = 1; - break; - default : - /* no data */ - retval = 0; - break; - } - - return retval; -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) { - int timeout = 0; - int count; - int break_flg = 0; - - if(length <= 0) { - return 0; - } - for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { - /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ - while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) { - if ((i2c_status(obj) & SR2_STOP) != 0) { - break_flg = 1; - break; - } - timeout ++; - if (timeout >= WAIT_TIMEOUT) { - return -1; - } - } - if (break_flg == 0) { - if (count == 0) { - /* dummy read */ - (void)REG(DRR.UINT32); - } else { - data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); - } - } - } - if (break_flg == 0) { - (void)i2c_wait_STOP(obj); - } else { - if ((i2c_status(obj) & SR2_RDRF) != 0) { - if (count <= 1) { - /* fail safe */ - /* dummy read */ - (void)REG(DRR.UINT32); - } else { - data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); - } - } - } - /* SR2.STOP = 0 */ - REG(SR2.UINT32) &= ~SR2_STOP; - - return (count - 1); -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int count = 0; - int status = 0; - - if(length <= 0) { - return 0; - } - - while ((count < length) && (status == 0)) { - status = i2c_do_write(obj, data[count]); - if(status == 0) { - /* Wait send end */ - status = i2c_wait_TEND(obj); - if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) { - /* NACK */ - break; - } - } - count++; - } - /* dummy read */ - (void)REG(DRR.UINT32); - (void)i2c_wait_STOP(obj); - i2c_set_SR2_NACKF_STOP(obj); - - return count; -} - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - REG(SAR0.UINT32) = (address & 0xfffffffe); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h new file mode 100644 index 0000000000..578173c473 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h @@ -0,0 +1,19 @@ +#ifndef MBED_DRV_CFG_H +#define MBED_DRV_CFG_H + +/* can_api.c */ +#define CAN_TEST_GLOBAL_CH 1 + +/* gpio_api.c */ +#define GPIO_GROUP_MAX 9 + +/* pwmout_api.c */ +#define FUNC_MOTOR_CTL_PWM +#define FUMC_MTU2_PWM + +/* rtc_api.c */ +#define USE_RTCX1_CLK +//#define USE_EXTAL_CLK +//#define USE_RTCX3_CLK + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c deleted file mode 100644 index 22bb560902..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c +++ /dev/null @@ -1,192 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pinmap.h" -#include "mbed_error.h" -#include "gpio_addrdefine.h" - -PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ - -typedef struct { - PinName pin; - int function; - int pm; -} PinFunc; - -#ifdef MAX_PERI -static const PinFunc PIPC_0_tbl[] = { -// pin func pm - {P4_0 , 2 , -1}, /* TIOC0A */ - {P5_0 , 6 , -1}, /* TIOC0A */ - {P7_0 , 7 , -1}, /* TIOC0A */ - {P4_1 , 2 , -1}, /* TIOC0B */ - {P5_1 , 6 , -1}, /* TIOC0B */ - {P7_1 , 7 , -1}, /* TIOC0B */ - {P4_2 , 2 , -1}, /* TIOC0C */ - {P5_5 , 6 , -1}, /* TIOC0C */ - {P7_2 , 7 , -1}, /* TIOC0C */ - {P4_3 , 2 , -1}, /* TIOC0D */ - {P5_7 , 6 , -1}, /* TIOC0D */ - {P7_3 , 7 , -1}, /* TIOC0D */ - {P2_11 , 5 , -1}, /* TIOC1A */ - {P6_0 , 5 , -1}, /* TIOC1A */ - {P7_4 , 7 , -1}, /* TIOC1A */ - {P8_8 , 5 , -1}, /* TIOC1A */ - {P9_7 , 4 , -1}, /* TIOC1A */ - {P2_12 , 8 , -1}, /* TIOC1B */ - {P5_2 , 6 , -1}, /* TIOC1B */ - {P6_1 , 5 , -1}, /* TIOC1B */ - {P7_5 , 7 , -1}, /* TIOC1B */ - {P8_9 , 5 , -1}, /* TIOC1B */ - {P2_1 , 6 , -1}, /* TIOC2A */ - {P6_2 , 6 , -1}, /* TIOC2A */ - {P7_6 , 7 , -1}, /* TIOC2A */ - {P8_14 , 4 , -1}, /* TIOC2A */ - {P2_2 , 6 , -1}, /* TIOC2B */ - {P6_3 , 6 , -1}, /* TIOC2B */ - {P7_7 , 7 , -1}, /* TIOC2B */ - {P8_15 , 4 , -1}, /* TIOC2B */ - {P3_4 , 6 , -1}, /* TIOC3A */ - {P7_8 , 7 , -1}, /* TIOC3A */ - {P8_10 , 4 , -1}, /* TIOC3A */ - {P3_5 , 6 , -1}, /* TIOC3B */ - {P7_9 , 7 , -1}, /* TIOC3B */ - {P8_11 , 4 , -1}, /* TIOC3B */ - {P3_6 , 6 , -1}, /* TIOC3C */ - {P5_3 , 6 , -1}, /* TIOC3C */ - {P7_10 , 7 , -1}, /* TIOC3C */ - {P8_12 , 4 , -1}, /* TIOC3C */ - {P3_7 , 6 , -1}, /* TIOC3D */ - {P5_4 , 6 , -1}, /* TIOC3D */ - {P7_11 , 7 , -1}, /* TIOC3D */ - {P8_13 , 4 , -1}, /* TIOC3D */ - {P3_8 , 6 , -1}, /* TIOC4A */ - {P4_4 , 3 , -1}, /* TIOC4A */ - {P7_12 , 7 , -1}, /* TIOC4A */ - {P3_9 , 6 , -1}, /* TIOC4B */ - {P4_5 , 3 , -1}, /* TIOC4B */ - {P7_13 , 7 , -1}, /* TIOC4B */ - {P3_10 , 6 , -1}, /* TIOC4C */ - {P4_6 , 3 , -1}, /* TIOC4C */ - {P7_14 , 7 , -1}, /* TIOC4C */ - {P3_11 , 6 , -1}, /* TIOC4D */ - {P4_7 , 3 , -1}, /* TIOC4D */ - {P7_15 , 7 , -1}, /* TIOC4D */ - {P5_7 , 1 , 1 }, /* TXOUT0M */ - {P5_6 , 1 , 1 }, /* TXOUT0P */ - {P5_5 , 1 , 1 }, /* TXOUT1M */ - {P5_4 , 1 , 1 }, /* TXOUT1P */ - {P5_3 , 1 , 1 }, /* TXOUT2M */ - {P5_2 , 1 , 1 }, /* TXOUT2P */ - {P5_1 , 1 , 1 }, /* TXCLKOUTM */ - {P5_0 , 1 , 1 }, /* TXCLKOUTP */ - {P2_11 , 4 , 0 }, /* SSITxD0 */ - {P4_7 , 5 , 0 }, /* SSITxD0 */ - {P7_4 , 6 , 0 }, /* SSITxD1 */ - {P4_15 , 6 , 0 }, /* SSITxD3 */ - {P7_11 , 2 , 0 }, /* SSITxD3 */ - {P2_7 , 4 , 0 }, /* SSITxD5 */ - {P4_11 , 5 , 0 }, /* SSITxD5 */ - {P8_10 , 8 , 0 }, /* SSITxD5 */ - {P3_7 , 8 , 0 }, /* WDTOVF */ - {NC , 0 , -1} -}; -#else -static const PinFunc PIPC_0_tbl[] = { - // pin func pm - {P4_0 , 2 , -1}, // TIOC0A - {P5_0 , 6 , -1}, // TIOC0A - {P4_2 , 2 , -1}, // TIOC0C - {P5_5 , 6 , -1}, // TIOC0C - // - {P8_14 , 4 , -1}, // TIOC2A - // - {P8_10 , 4 , -1}, // TIOC3A - {P5_3 , 6 , -1}, // TIOC3C - {P8_12 , 4 , -1}, // TIOC3C - // - {P3_8 , 6 , -1}, // TIOC4A - {P4_4 , 3 , -1}, // TIOC4A - {P3_10 , 6 , -1}, // TIOC4C - {P4_6 , 3 , -1}, // TIOC4C - // - {P5_7 , 1 , 1 }, // TXOUT0M - {P5_6 , 1 , 1 }, // TXOUT0P - {P5_5 , 1 , 1 }, // TXOUT1M - {P5_4 , 1 , 1 }, // TXOUT1P - {P5_3 , 1 , 1 }, // TXOUT2M - {P5_2 , 1 , 1 }, // TXOUT2P - {P5_1 , 1 , 1 }, // TXCLKOUTM - {P5_0 , 1 , 1 }, // TXCLKOUTP - {P4_7 , 5 , 0 }, // SSITxD0 - {P8_10 , 8 , 0 }, // SSITxD5 - {P3_7 , 8 , 0 }, // WDTOVF - {NC , 0 , -1} -}; -#endif - -void pin_function(PinName pin, int function) { - if (pin == (PinName)NC) return; - - int n = pin >> 4; - int bitmask = 1<<(pin & 0xf); - const PinFunc * Pipc_0_func = PIPC_0_tbl; - int pipc_data = 1; - - if (gpio_multi_guard != pin) { - if (function == 0) { - // means GPIO mode - *PMC(n) &= ~bitmask; - } else { - // alt-function mode - --function; - - if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} - if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} - if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} - - while (Pipc_0_func->pin != NC) { - if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) { - pipc_data = 0; - if (Pipc_0_func->pm == 0) { - *PMSR(n) = (bitmask << 16) | 0; - } else if (Pipc_0_func->pm == 1) { - *PMSR(n) = (bitmask << 16) | bitmask; - } else { - // Do Nothing - } - break; - } - Pipc_0_func++; - } - if (pipc_data == 1) { - *PIPC(n) |= bitmask; - } else { - *PIPC(n) &= ~bitmask; - } - - if (P1_0 <= pin && pin <= P1_7 && function == 0) { - *PBDC(n) |= bitmask; - } - *PMC(n) |= bitmask; - } - } else { - gpio_multi_guard = (PinName)NC; - } -} - -void pin_mode(PinName pin, PinMode mode) { -// if (pin == (PinName)NC) { return; } -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pwmout_api.c deleted file mode 100644 index 522290cd87..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pwmout_api.c +++ /dev/null @@ -1,700 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "RZ_A1_Init.h" -#include "cpg_iodefine.h" -#include "pwm_iodefine.h" -#include "gpio_addrdefine.h" - -#ifdef MAX_PERI -#define MTU2_PWM_NUM 27 -#define MTU2_PWM_SIGNAL 2 -#define MTU2_PWM_OFFSET 0x20 - -// PORT ID, PWM ID, Pin function -static const PinMap PinMap_PWM[] = { - // TIOC0 A,C - {P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A - {P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A - {P7_0 , MTU2_PWM2_PIN , 7}, //TIOC0A - {P4_2 , MTU2_PWM3_PIN , 2}, //TIOC0C - {P5_5 , MTU2_PWM4_PIN , 6}, //TIOC0C - {P7_2 , MTU2_PWM5_PIN , 7}, //TIOC0C - //TIOC1 A - {P2_11 , MTU2_PWM6_PIN , 5}, //TIOC1A - {P6_0 , MTU2_PWM7_PIN , 5}, //TIOC1A - {P7_4 , MTU2_PWM8_PIN , 7}, //TIOC1A - {P8_8 , MTU2_PWM9_PIN , 5}, //TIOC1A - {P9_7 , MTU2_PWM10_PIN , 4}, //TIOC1A - //TIOC2 A - {P2_1 , MTU2_PWM11_PIN , 6}, //TIOC2A - {P6_2 , MTU2_PWM12_PIN , 6}, //TIOC2A - {P7_6 , MTU2_PWM13_PIN , 7}, //TIOC2A - {P8_14 , MTU2_PWM14_PIN , 4}, //TIOC2A - //TIOC3 A,C - {P3_4 , MTU2_PWM15_PIN , 6}, //TIOC3A - {P7_8 , MTU2_PWM16_PIN , 7}, //TIOC3A - {P8_10 , MTU2_PWM17_PIN , 4}, //TIOC3A - {P3_6 , MTU2_PWM18_PIN , 6}, //TIOC3C - {P7_10 , MTU2_PWM19_PIN , 7}, //TIOC3C - {P8_12 , MTU2_PWM20_PIN , 4}, //TIOC3C - //TIOC4 A,C - {P3_8 , MTU2_PWM21_PIN , 6}, //TIOC4A - {P4_4 , MTU2_PWM22_PIN , 3}, //TIOC4A - {P7_12 , MTU2_PWM23_PIN , 7}, //TIOC4A - {P3_10 , MTU2_PWM24_PIN , 6}, //TIOC4C - {P4_6 , MTU2_PWM25_PIN , 3}, //TIOC4C - {P7_14 , MTU2_PWM26_PIN , 7}, //TIOC4C - //PWM1 - {P8_8 , PWM0_PIN , 6}, //PWM1A - {P8_9 , PWM1_PIN , 6}, //PWM1B - {P8_10 , PWM2_PIN , 6}, //PWM1C - {P8_11 , PWM3_PIN , 6}, //PWM1D - {P8_12 , PWM4_PIN , 6}, //PWM1E - {P8_13 , PWM5_PIN , 6}, //PWM1F - {P8_14 , PWM6_PIN , 6}, //PWM1G - {P8_15 , PWM7_PIN , 6}, //PWM1H - //PWM2 - {P3_0 , PWM8_PIN , 7}, //PWM2A - {P3_1 , PWM9_PIN , 7}, //PWM2B - {P3_2 , PWM10_PIN , 7}, //PWM2C - {P3_3 , PWM11_PIN , 7}, //PWM2D - {P4_4 , PWM12_PIN , 4}, //PWM2E - {P4_5 , PWM13_PIN , 4}, //PWM2F - {P4_6 , PWM14_PIN , 4}, //PWM2G - {P4_7 , PWM15_PIN , 4}, //PWM2H - {NC , NC , 0} -}; - -static const PWMType PORT[] = { - PWM1A, // PWM0_PIN - PWM1B, // PWM1_PIN - PWM1C, // PWM2_PIN - PWM1D, // PWM3_PIN - PWM1E, // PWM4_PIN - PWM1F, // PWM5_PIN - PWM1G, // PWM6_PIN - PWM1H, // PWM7_PIN - PWM2A, // PWM8_PIN - PWM2B, // PWM9_PIN - PWM2C, // PWM10_PIN - PWM2D, // PWM11_PIN - PWM2E, // PWM12_PIN - PWM2F, // PWM13_PIN - PWM2G, // PWM14_PIN - PWM2H, // PWM15_PIN -}; - -static const MTU2_PWMType MTU2_PORT[] = { - TIOC0A, // MTU2_PWM0_PIN - TIOC0A, // MTU2_PWM1_PIN - TIOC0A, // MTU2_PWM2_PIN - TIOC0C, // MTU2_PWM3_PIN - TIOC0C, // MTU2_PWM4_PIN - TIOC0C, // MTU2_PWM5_PIN - TIOC1A, // MTU2_PWM6_PIN - TIOC1A, // MTU2_PWM7_PIN - TIOC1A, // MTU2_PWM8_PIN - TIOC1A, // MTU2_PWM9_PIN - TIOC1A, // MTU2_PWM10_PIN - TIOC2A, // MTU2_PWM11_PIN - TIOC2A, // MTU2_PWM12_PIN - TIOC2A, // MTU2_PWM13_PIN - TIOC2A, // MTU2_PWM14_PIN - TIOC3A, // MTU2_PWM15_PIN - TIOC3A, // MTU2_PWM16_PIN - TIOC3A, // MTU2_PWM17_PIN - TIOC3C, // MTU2_PWM18_PIN - TIOC3C, // MTU2_PWM19_PIN - TIOC3C, // MTU2_PWM20_PIN - TIOC4A, // MTU2_PWM21_PIN - TIOC4A, // MTU2_PWM22_PIN - TIOC4A, // MTU2_PWM23_PIN - TIOC4C, // MTU2_PWM24_PIN - TIOC4C, // MTU2_PWM25_PIN - TIOC4C, // MTU2_PWM26_PIN -}; - -static __IO uint16_t *PWM_MATCH[] = { - &PWMPWBFR_1A, // PWM0_PIN - &PWMPWBFR_1A, // PWM1_PIN - &PWMPWBFR_1C, // PWM2_PIN - &PWMPWBFR_1C, // PWM3_PIN - &PWMPWBFR_1E, // PWM4_PIN - &PWMPWBFR_1E, // PWM5_PIN - &PWMPWBFR_1G, // PWM6_PIN - &PWMPWBFR_1G, // PWM7_PIN - &PWMPWBFR_2A, // PWM8_PIN - &PWMPWBFR_2A, // PWM9_PIN - &PWMPWBFR_2C, // PWM10_PIN - &PWMPWBFR_2C, // PWM11_PIN - &PWMPWBFR_2E, // PWM12_PIN - &PWMPWBFR_2E, // PWM13_PIN - &PWMPWBFR_2G, // PWM14_PIN - &PWMPWBFR_2G, // PWM15_PIN -}; - -static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { - { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM0_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM1_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM2_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM3_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM4_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM5_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM6_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM7_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM8_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM9_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM10_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM11_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM12_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM13_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM14_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM15_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM16_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM17_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM18_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM19_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM20_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM21_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM22_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM23_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM24_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM25_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM26_PIN -}; -#else -#define MTU2_PWM_NUM 12 -#define MTU2_PWM_SIGNAL 2 -#define MTU2_PWM_OFFSET 0x20 - -// PORT ID, PWM ID, Pin function -static const PinMap PinMap_PWM[] = { - //TIOC0 A,C - {P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A - {P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A - {P4_2 , MTU2_PWM2_PIN , 2}, //TIOC0C - {P5_5 , MTU2_PWM3_PIN , 6}, //TIOC0C - //TIOC2 A - {P8_14 , MTU2_PWM4_PIN , 4}, //TIOC2A - //TIOC3 A,C - {P8_10 , MTU2_PWM5_PIN , 4}, //TIOC3A - {P5_3 , MTU2_PWM6_PIN , 6}, //TIOC3C - {P8_12 , MTU2_PWM7_PIN , 4}, //TIOC3C - //TIOC4 A,C - {P3_8 , MTU2_PWM8_PIN , 6}, //TIOC4A - {P4_4 , MTU2_PWM9_PIN , 3}, //TIOC4A - {P3_10 , MTU2_PWM10_PIN , 6}, //TIOC4C - {P4_6 , MTU2_PWM11_PIN , 3}, //TIOC4C - //PWM1 - {P8_10 , PWM0_PIN , 6}, //PWM1C - {P8_11 , PWM1_PIN , 6}, //PWM1D - {P8_12 , PWM2_PIN , 6}, //PWM1E - {P8_13 , PWM3_PIN , 6}, //PWM1F - {P8_14 , PWM4_PIN , 6}, //PWM1G - {P8_15 , PWM5_PIN , 6}, //PWM1H - //PWM2 - {P3_0 , PWM6_PIN , 7}, //PWM2A - {P3_1 , PWM7_PIN , 7}, //PWM2B - {P3_2 , PWM8_PIN , 7}, //PWM2C - {P4_4 , PWM9_PIN , 4}, //PWM2E - {P4_5 , PWM10_PIN , 4}, //PWM2F - {P4_6 , PWM11_PIN , 4}, //PWM2G - {P4_7 , PWM12_PIN , 4}, //PWM2H - {NC , NC , 0} -}; - -static const PWMType PORT[] = { - PWM1C, // PWM0_PIN - PWM1D, // PWM1_PIN - PWM1E, // PWM2_PIN - PWM1F, // PWM3_PIN - PWM1G, // PWM4_PIN - PWM1H, // PWM5_PIN - PWM2A, // PWM6_PIN - PWM2B, // PWM7_PIN - PWM2C, // PWM8_PIN - PWM2E, // PWM9_PIN - PWM2F, // PWM10_PIN - PWM2G, // PWM11_PIN - PWM2H, // PWM12_PIN -}; - -static const MTU2_PWMType MTU2_PORT[] = { - TIOC0A, // MTU2_PWM0_PIN - TIOC0A, // MTU2_PWM1_PIN - TIOC0C, // MTU2_PWM2_PIN - TIOC0C, // MTU2_PWM3_PIN - TIOC2A, // MTU2_PWM4_PIN - TIOC3A, // MTU2_PWM5_PIN - TIOC3C, // MTU2_PWM6_PIN - TIOC3C, // MTU2_PWM7_PIN - TIOC4A, // MTU2_PWM8_PIN - TIOC4A, // MTU2_PWM9_PIN - TIOC4C, // MTU2_PWM10_PIN - TIOC4C, // MTU2_PWM11_PIN -}; - -static __IO uint16_t *PWM_MATCH[] = { - &PWMPWBFR_1C, // PWM0_PIN - &PWMPWBFR_1C, // PWM1_PIN - &PWMPWBFR_1E, // PWM2_PIN - &PWMPWBFR_1E, // PWM3_PIN - &PWMPWBFR_1G, // PWM4_PIN - &PWMPWBFR_1G, // PWM5_PIN - &PWMPWBFR_2A, // PWM6_PIN - &PWMPWBFR_2A, // PWM7_PIN - &PWMPWBFR_2C, // PWM8_PIN - &PWMPWBFR_2E, // PWM9_PIN - &PWMPWBFR_2E, // PWM10_PIN - &PWMPWBFR_2G, // PWM11_PIN - &PWMPWBFR_2G, // PWM12_PIN -}; - -static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM0_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM1_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM2_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM3_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM4_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM5_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM6_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM7_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM8_PIN - { &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM9_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM10_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM11_PIN -}; -#endif - - -static __IO uint8_t *TCR_MATCH[] = { - &MTU2TCR_0, - &MTU2TCR_1, - &MTU2TCR_2, - &MTU2TCR_3, - &MTU2TCR_4, -}; - -static __IO uint8_t *TIORH_MATCH[] = { - &MTU2TIORH_0, - &MTU2TIOR_1, - &MTU2TIOR_2, - &MTU2TIORH_3, - &MTU2TIORH_4, -}; - -static __IO uint8_t *TIORL_MATCH[] = { - &MTU2TIORL_0, - NULL, - NULL, - &MTU2TIORL_3, - &MTU2TIORL_4, -}; - -static __IO uint16_t *TGRA_MATCH[] = { - &MTU2TGRA_0, - &MTU2TGRA_1, - &MTU2TGRA_2, - &MTU2TGRA_3, - &MTU2TGRA_4, -}; - -static __IO uint16_t *TGRC_MATCH[] = { - &MTU2TGRC_0, - NULL, - NULL, - &MTU2TGRC_3, - &MTU2TGRC_4, -}; - -static __IO uint8_t *TMDR_MATCH[] = { - &MTU2TMDR_0, - &MTU2TMDR_1, - &MTU2TMDR_2, - &MTU2TMDR_3, - &MTU2TMDR_4, -}; - -static int MAX_PERIOD[] = { - 125000, - 503000, - 2000000, - 2000000, - 2000000, -}; - -typedef enum { - MODE_PWM = 0, - MODE_MTU2 -} PWMmode; - -typedef enum { - MTU2_PULSE = 0, - MTU2_PERIOD -} MTU2Signal; - -static int pwm_mode = MODE_PWM; -static uint16_t init_period_ch1 = 0; -static uint16_t init_period_ch2 = 0; -static uint16_t init_mtu2_period_ch[5] = {0}; -static int32_t period_ch1 = 1; -static int32_t period_ch2 = 1; -static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; - -void pwmout_init(pwmout_t* obj, PinName pin) { - // determine the channel - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - if (pwm >= MTU2_PWM_OFFSET) { - /* PWM by MTU2 */ - int tmp_pwm; - - pwm_mode = MODE_MTU2; - // power on - CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33); - - obj->pwm = pwm; - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) { - obj->ch = 4; - MTU2TOER |= 0x36; - } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) { - obj->ch = 3; - MTU2TOER |= 0x09; - } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) { - obj->ch = 2; - } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) { - obj->ch = 1; - } else { - obj->ch = 0; - } - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); - - int bitmask = 1 << (pin & 0xf); - - *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0; - - // default duty 0.0f - pwmout_write(obj, 0); - if (init_mtu2_period_ch[obj->ch] == 0) { - // default period 1ms - pwmout_period_us(obj, 1000); - init_mtu2_period_ch[obj->ch] = 1; - } - } else { - /* PWM */ - pwm_mode = MODE_PWM; - // power on - CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); - - obj->pwm = pwm; - if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) { - obj->ch = 2; - PWMPWPR_2_BYTE_L = 0x00; - } else { - obj->ch = 1; - PWMPWPR_1_BYTE_L = 0x00; - } - - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); - - // default to 491us: standard for servos, and fine for e.g. brightness control - pwmout_write(obj, 0); - if ((obj->ch == 2) && (init_period_ch2 == 0)) { - pwmout_period_us(obj, 491); - init_period_ch2 = 1; - } - if ((obj->ch == 1) && (init_period_ch1 == 0)) { - pwmout_period_us(obj, 491); - init_period_ch1 = 1; - } - } -} - -void pwmout_free(pwmout_t* obj) { - pwmout_write(obj, 0); -} - -void pwmout_write(pwmout_t* obj, float value) { - uint32_t wk_cycle; - uint16_t v; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - int tmp_pwm; - - if (value < 0.0f) { - value = 0.0f; - } else if (value > 1.0f) { - value = 1.0f; - } else { - // Do Nothing - } - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; - // set channel match to percentage - *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); - } else { - /* PWM */ - if (value < 0.0f) { - value = 0.0f; - } else if (value > 1.0f) { - value = 1.0f; - } else { - // Do Nothing - } - - if (obj->ch == 2) { - wk_cycle = PWMPWCYR_2 & 0x03ff; - } else { - wk_cycle = PWMPWCYR_1 & 0x03ff; - } - - // set channel match to percentage - v = (uint16_t)((float)wk_cycle * value); - *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); - } -} - -float pwmout_read(pwmout_t* obj) { - uint32_t wk_cycle; - float value; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - uint32_t wk_pulse; - int tmp_pwm; - - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; - wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; - value = ((float)wk_pulse / (float)wk_cycle); - } else { - /* PWM */ - if (obj->ch == 2) { - wk_cycle = PWMPWCYR_2 & 0x03ff; - } else { - wk_cycle = PWMPWCYR_1 & 0x03ff; - } - value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); - } - - return (value > 1.0f) ? (1.0f) : (value); -} - -void pwmout_period(pwmout_t* obj, float seconds) { - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) { - pwmout_period_us(obj, ms * 1000); -} - -static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ - uint16_t wk_pwmpbfr; - float value; - uint16_t v; - - wk_pwmpbfr = *p_pwmpbfr; - value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle); - v = (uint16_t)((float)new_cycle * value); - *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); -} - -static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ - uint16_t wk_pwmpbfr; - float value; - - wk_pwmpbfr = *p_pwmpbfr; - value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); - *p_pwmpbfr = (uint16_t)((float)new_cycle * value); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) { - uint64_t wk_cycle_mtu2; - uint32_t pclk_base; - uint32_t wk_cycle; - uint32_t wk_cks = 0; - uint16_t wk_last_cycle; - int max_us = 0; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - int tmp_pwm; - uint8_t tmp_tcr_up; - uint8_t tmp_tstr_sp; - uint8_t tmp_tstr_st; - - max_us = MAX_PERIOD[obj->ch]; - if (us > max_us) { - us = max_us; - } else if (us < 1) { - us = 1; - } else { - // Do Nothing - } - - if (RZ_A1_IsClockMode0() == false) { - pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK; - } else { - pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK; - } - - wk_cycle_mtu2 = (uint64_t)pclk_base * us; - while (wk_cycle_mtu2 >= 65535000000) { - if ((obj->ch == 1) && (wk_cks == 3)) { - wk_cks+=2; - } else if ((obj->ch == 2) && (wk_cks == 3)) { - wk_cycle_mtu2 >>= 2; - wk_cks+=3; - } - wk_cycle_mtu2 >>= 2; - wk_cks++; - } - wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); - - tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); - if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { - tmp_tcr_up = 0xC0; - } else { - tmp_tcr_up = 0x40; - } - if ((obj->ch == 4) || (obj->ch == 3)) { - tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3))); - tmp_tstr_st = (1 << (obj->ch + 3)); - } else { - tmp_tstr_sp = ~(0x38 | (1 << obj->ch)); - tmp_tstr_st = (1 << obj->ch); - } - // Counter Stop - MTU2TSTR &= tmp_tstr_sp; - wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; - *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks; - *TIORH_MATCH[obj->ch] = 0x21; - if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { - *TIORL_MATCH[obj->ch] = 0x21; - } - *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period - - // Set duty again(TGRA) - set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle); - if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { - // Set duty again(TGRC) - set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle); - } - *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1 - - // Counter Start - MTU2TSTR |= tmp_tstr_st; - // Save for future use - mtu2_period_ch[obj->ch] = us; - } else { - /* PWM */ - if (us > 491) { - us = 491; - } else if (us < 1) { - us = 1; - } else { - // Do Nothing - } - - if (RZ_A1_IsClockMode0() == false) { - pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000; - } else { - pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000; - } - - wk_cycle = pclk_base * us; - while (wk_cycle >= 102350) { - wk_cycle >>= 1; - wk_cks++; - } - wk_cycle = (wk_cycle + 50) / 100; - - if (obj->ch == 2) { - wk_last_cycle = PWMPWCYR_2 & 0x03ff; - PWMPWCR_2_BYTE_L = 0xc0 | wk_cks; - PWMPWCYR_2 = (uint16_t)wk_cycle; - - // Set duty again - set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle); - - // Counter Start - PWMPWCR_2_BYTE_L |= 0x08; - - // Save for future use - period_ch2 = us; - } else { - wk_last_cycle = PWMPWCYR_1 & 0x03ff; - PWMPWCR_1_BYTE_L = 0xc0 | wk_cks; - PWMPWCYR_1 = (uint16_t)wk_cycle; - - // Set duty again - set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle); - set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle); - - // Counter Start - PWMPWCR_1_BYTE_L |= 0x08; - - // Save for future use - period_ch1 = us; - } - } -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - float value = 0; - - if (pwm_mode == MODE_MTU2) { - /* PWM by MTU2 */ - if (mtu2_period_ch[obj->ch] != 0) { - value = (float)us / (float)mtu2_period_ch[obj->ch]; - } - } else { - /* PWM */ - if (obj->ch == 2) { - if (period_ch2 != 0) { - value = (float)us / (float)period_ch2; - } - } else { - if (period_ch1 != 0) { - value = (float)us / (float)period_ch1; - } - } - } - pwmout_write(obj, value); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/serial_api.c deleted file mode 100644 index f9a89359fd..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/serial_api.c +++ /dev/null @@ -1,672 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include "mbed_assert.h" -#include -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "mbed_critical.h" - -#include "scif_iodefine.h" -#include "cpg_iodefine.h" - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define PCLK (66666666) // Define the peripheral clock P1 frequency. - -#define UART_NUM 8 -#define IRQ_NUM 2 - -static void uart0_tx_irq(void); -static void uart1_tx_irq(void); -static void uart2_tx_irq(void); -static void uart3_tx_irq(void); -static void uart4_tx_irq(void); -static void uart5_tx_irq(void); -static void uart6_tx_irq(void); -static void uart7_tx_irq(void); -static void uart0_rx_irq(void); -static void uart1_rx_irq(void); -static void uart2_rx_irq(void); -static void uart3_rx_irq(void); -static void uart4_rx_irq(void); -static void uart5_rx_irq(void); -static void uart6_rx_irq(void); -static void uart7_rx_irq(void); - -#ifdef MAX_PERI -static const PinMap PinMap_UART_TX[] = { - {P2_14 , UART0, 6}, - {P4_9 , UART0, 7}, - {P6_9 , UART0, 5}, - {P2_5 , UART1, 6}, - {P4_12 , UART1, 7}, - {P6_12 , UART1, 5}, - {P9_3 , UART1, 4}, - {P3_0 , UART2, 6}, - {P3_1 , UART2, 4}, - {P4_2 , UART2, 5}, - {P4_14 , UART2, 7}, - {P6_3 , UART2, 7}, - {P8_6 , UART2, 7}, - {P3_5 , UART3, 7}, - {P5_3 , UART3, 5}, - {P6_1 , UART3, 7}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P7_1 , UART4, 4}, - {P8_14 , UART4, 7}, - {P6_6 , UART5, 5}, - {P8_1 , UART5, 4}, - {P8_13 , UART5, 5}, - {P5_6 , UART6, 5}, - {P6_14 , UART6, 4}, - {P7_4 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {P2_15 , UART0, 6}, - {P4_10 , UART0, 7}, - {P6_10 , UART0, 5}, - {P2_6 , UART1, 6}, - {P4_13 , UART1, 7}, - {P6_13 , UART1, 5}, - {P9_4 , UART1, 4}, - {P3_2 , UART2, 4}, - {P4_3 , UART2, 5}, - {P4_15 , UART2, 7}, - {P6_2 , UART2, 7}, - {P8_4 , UART2, 7}, - {P3_6 , UART3, 7}, - {P5_4 , UART3, 5}, - {P6_0 , UART3, 7}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P7_2 , UART4, 4}, - {P8_15 , UART4, 7}, - {P6_7 , UART5, 5}, - {P8_2 , UART5, 4}, - {P8_11 , UART5, 5}, - {P5_7 , UART6, 5}, - {P6_15 , UART6, 4}, - {P7_5 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_CTS[] = { - {P2_3 , UART1, 6}, - {P9_5 , UART1, 4}, - {P6_3 , UART5, 5}, - {P7_15 , UART5, 4}, - {P7_6 , UART7, 4}, - {NC , NC , 0} -}; -static const PinMap PinMap_UART_RTS[] = { - {P2_7 , UART1, 6}, - {P9_6 , UART1, 4}, - {P6_4 , UART5, 5}, - {P8_3 , UART5, 4}, - {P7_7 , UART7, 4}, - {NC , NC , 0} -}; -#else -static const PinMap PinMap_UART_TX[] = { - {P3_0 , UART2, 6}, - {P3_1 , UART2, 4}, - {P4_2 , UART2, 5}, - {P5_3 , UART3, 5}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P8_14 , UART4, 7}, - {P8_13 , UART5, 5}, - {P5_6 , UART6, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {P3_2 , UART2, 4}, - {P4_3 , UART2, 5}, - {P5_4 , UART3, 5}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P8_15 , UART4, 7}, - {P8_11 , UART5, 5}, - {P5_7 , UART6, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_CTS[] = { - {NC , NC , 0} -}; -static const PinMap PinMap_UART_RTS[] = { - {NC , NC , 0} -}; -#endif - -static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -struct serial_global_data_s { - uint32_t serial_irq_id; - gpio_t sw_rts, sw_cts; - uint8_t count, rx_irq_set_flow, rx_irq_set_api; -}; - -static struct serial_global_data_s uart_data[UART_NUM]; - -static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { - {SCIFRXI0_IRQn, SCIFTXI0_IRQn}, - {SCIFRXI1_IRQn, SCIFTXI1_IRQn}, - {SCIFRXI2_IRQn, SCIFTXI2_IRQn}, - {SCIFRXI3_IRQn, SCIFTXI3_IRQn}, - {SCIFRXI4_IRQn, SCIFTXI4_IRQn}, - {SCIFRXI5_IRQn, SCIFTXI5_IRQn}, - {SCIFRXI6_IRQn, SCIFTXI6_IRQn}, - {SCIFRXI7_IRQn, SCIFTXI7_IRQn} -}; - -static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { - {uart0_rx_irq, uart0_tx_irq}, - {uart1_rx_irq, uart1_tx_irq}, - {uart2_rx_irq, uart2_tx_irq}, - {uart3_rx_irq, uart3_tx_irq}, - {uart4_rx_irq, uart4_tx_irq}, - {uart5_rx_irq, uart5_tx_irq}, - {uart6_rx_irq, uart6_tx_irq}, - {uart7_rx_irq, uart7_tx_irq} -}; - -static __IO uint16_t *SCSCR_MATCH[] = { - &SCSCR_0, - &SCSCR_1, - &SCSCR_2, - &SCSCR_3, - &SCSCR_4, - &SCSCR_5, - &SCSCR_6, - &SCSCR_7, -}; - -static __IO uint16_t *SCFSR_MATCH[] = { - &SCFSR_0, - &SCFSR_1, - &SCFSR_2, - &SCFSR_3, - &SCFSR_4, - &SCFSR_5, - &SCFSR_6, - &SCFSR_7, -}; - - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - volatile uint8_t dummy ; - int is_stdio_uart = 0; - // determine the UART to use - uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - uint32_t uart = pinmap_merge(uart_tx, uart_rx); - - MBED_ASSERT((int)uart != NC); - - obj->uart = (struct st_scif *)SCIF[uart]; - // enable power - switch (uart) { - case UART0: - CPG.STBCR4 &= ~(1 << 7); - break; - case UART1: - CPG.STBCR4 &= ~(1 << 6); - break; - case UART2: - CPG.STBCR4 &= ~(1 << 5); - break; - case UART3: - CPG.STBCR4 &= ~(1 << 4); - break; - case UART4: - CPG.STBCR4 &= ~(1 << 3); - break; - case UART5: - CPG.STBCR4 &= ~(1 << 2); - break; - case UART6: - CPG.STBCR4 &= ~(1 << 1); - break; - case UART7: - CPG.STBCR4 &= ~(1 << 0); - break; - } - dummy = CPG.STBCR4; - - /* if this uart has been previously configured to tx, wait tx completion befor loading new configuration */ - if(obj->uart->SCSCR & 0xA0) - while(!(obj->uart->SCFSR & 0x0040)); - - /* ==== SCIF initial setting ==== */ - /* ---- Serial control register (SCSCR) setting ---- */ - /* B'00 : Internal CLK */ - obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */ - - /* ---- FIFO control register (SCFCR) setting ---- */ - /* Transmit FIFO reset & Receive FIFO data register reset */ - obj->uart->SCFCR = 0x0006; - - /* ---- Serial status register (SCFSR) setting ---- */ - dummy = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */ - - /* ---- Line status register (SCLSR) setting ---- */ - /* ORER bit clear */ - obj->uart->SCLSR = 0; - - /* ---- Serial extension mode register (SCEMR) setting ---- - b7 BGDM - Baud rate generator double-speed mode : Normal mode - b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ - obj->uart->SCEMR = 0x0000u; - - /* ---- Bit rate register (SCBRR) setting ---- */ - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - /* ---- FIFO control register (SCFCR) setting ---- */ - obj->uart->SCFCR = 0x0030u; - - /* ---- Serial port register (SCSPTR) setting ---- - b1 SPB2IO - Serial port break output : disabled - b0 SPB2DT - Serial port break data : High-level */ - obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 - - /* ---- Line status register (SCLSR) setting ---- - b0 ORER - Overrun error detect : clear */ - - if (obj->uart->SCLSR & 0x0001) { - obj->uart->SCLSR = 0u; // ORER clear - } - - // pinout the chosen uart - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - switch (uart) { - case UART0: - obj->index = 0; - break; - case UART1: - obj->index = 1; - break; - case UART2: - obj->index = 2; - break; - case UART3: - obj->index = 3; - break; - case UART4: - obj->index = 4; - break; - case UART5: - obj->index = 5; - break; - case UART6: - obj->index = 6; - break; - case UART7: - obj->index = 7; - break; - } - uart_data[obj->index].sw_rts.pin = NC; - uart_data[obj->index].sw_cts.pin = NC; - - /* ---- Serial control register (SCSCR) setting ---- */ - /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */ - obj->uart->SCSCR = (((uart_tx != (uint32_t)NC)? 0xA0 : 0) | ((uart_rx != (uint32_t)NC)? 0x50 : 0 )); //0x00F0; - - is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - uart_data[obj->index].serial_irq_id = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { - uint16_t DL; - - obj->uart->SCSMR &= ~0x0003; - - if (baudrate > 32552) { - obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 - DL = PCLK / (8 * baudrate); - if (DL > 0) { - DL--; - } - obj->uart->SCBRR = (uint8_t)DL; - } else if (baudrate > 16276) { - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; - } else if (baudrate > 8138) { - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; - } else if (baudrate > 4169) { - obj->uart->SCSMR |= 0x0001; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; - } else if (baudrate > 2034) { - obj->uart->SCSMR |= 0x0001; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; - } else if (baudrate > 1017) { - obj->uart->SCSMR |= 0x0002; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; - } else if (baudrate > 508) { - obj->uart->SCSMR |= 0x0002; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; - } else if (baudrate > 254) { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0080; // BGDM = 1 - obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; - } else if (baudrate > 127) { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; - } else { - obj->uart->SCSMR |= 0x0003; - obj->uart->SCEMR = 0x0000; - obj->uart->SCBRR = 0xFFu; - } -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - int parity_enable; - int parity_select; - - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || - (parity == ParityForced1) || (parity == ParityForced0)); - - stop_bits = (stop_bits == 1)? 0: - (stop_bits == 2)? 1: - 0; // must not to be - - data_bits = (data_bits == 8)? 0: - (data_bits == 7)? 1: - 0; // must not to be - - switch (parity) { - case ParityNone: - parity_enable = 0; - parity_select = 0; - break; - case ParityOdd: - parity_enable = 1; - parity_select = 1; - break; - case ParityEven: - parity_enable = 1; - parity_select = 0; - break; - case ParityForced1: - case ParityForced0: - default: - parity_enable = 0; - parity_select = 0; - break; - } - - obj->uart->SCSMR = data_bits << 6 - | parity_enable << 5 - | parity_select << 4 - | stop_bits << 3; -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ - -static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) { - __IO uint16_t *dmy_rd_scscr; - __IO uint16_t *dmy_rd_scfsr; - - dmy_rd_scscr = SCSCR_MATCH[index]; - *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0 - dmy_rd_scfsr = SCFSR_MATCH[index]; - *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE - - irq_handler(uart_data[index].serial_irq_id, TxIrq); -} - -static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { - __IO uint16_t *dmy_rd_scscr; - __IO uint16_t *dmy_rd_scfsr; - - dmy_rd_scscr = SCSCR_MATCH[index]; - *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0 - dmy_rd_scfsr = SCFSR_MATCH[index]; - *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR - - irq_handler(uart_data[index].serial_irq_id, RxIrq); -} - -/* TX handler */ -static void uart0_tx_irq(void) { - uart_tx_irq(SCIFTXI0_IRQn, 0); -} -static void uart1_tx_irq(void) { - uart_tx_irq(SCIFTXI1_IRQn, 1); -} -static void uart2_tx_irq(void) { - uart_tx_irq(SCIFTXI2_IRQn, 2); -} -static void uart3_tx_irq(void) { - uart_tx_irq(SCIFTXI3_IRQn, 3); -} -static void uart4_tx_irq(void) { - uart_tx_irq(SCIFTXI4_IRQn, 4); -} -static void uart5_tx_irq(void) { - uart_tx_irq(SCIFTXI5_IRQn, 5); -} -static void uart6_tx_irq(void) { - uart_tx_irq(SCIFTXI6_IRQn, 6); -} -static void uart7_tx_irq(void) { - uart_tx_irq(SCIFTXI7_IRQn, 7); -} -/* RX handler */ -static void uart0_rx_irq(void) { - uart_rx_irq(SCIFRXI0_IRQn, 0); -} -static void uart1_rx_irq(void) { - uart_rx_irq(SCIFRXI1_IRQn, 1); -} -static void uart2_rx_irq(void) { - uart_rx_irq(SCIFRXI2_IRQn, 2); -} -static void uart3_rx_irq(void) { - uart_rx_irq(SCIFRXI3_IRQn, 3); -} -static void uart4_rx_irq(void) { - uart_rx_irq(SCIFRXI4_IRQn, 4); -} -static void uart5_rx_irq(void) { - uart_rx_irq(SCIFRXI5_IRQn, 5); -} -static void uart6_rx_irq(void) { - uart_rx_irq(SCIFRXI6_IRQn, 6); -} -static void uart7_rx_irq(void) { - uart_rx_irq(SCIFRXI7_IRQn, 7); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - uart_data[obj->index].serial_irq_id = id; -} - -static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type IRQn; - IRQHandler handler; - - IRQn = irq_set_tbl[obj->index][irq]; - handler = hander_set_tbl[obj->index][irq]; - - if ((obj->index >= 0) && (obj->index <= 7)) { - if (enable) { - InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); - GIC_SetPriority(IRQn, 5); - GIC_EnableIRQ(IRQn); - } else { - GIC_DisableIRQ(IRQn); - } - } -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - if (RxIrq == irq) { - uart_data[obj->index].rx_irq_set_api = enable; - } - serial_irq_set_internal(obj, irq, enable); -} - -static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { - uart_data[obj->index].rx_irq_set_flow = enable; - serial_irq_set_internal(obj, RxIrq, enable); -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) { - uint16_t err_read; - int data; - - core_util_critical_section_enter(); - if (obj->uart->SCFSR & 0x93) { - err_read = obj->uart->SCFSR; - obj->uart->SCFSR = (err_read & ~0x93); - } - obj->uart->SCSCR |= 0x0040; // Set RIE - core_util_critical_section_exit(); - - if (obj->uart->SCLSR & 0x0001) { - obj->uart->SCLSR = 0u; // ORER clear - } - - while (!serial_readable(obj)); - data = obj->uart->SCFRDR & 0xff; - - core_util_critical_section_enter(); - - err_read = obj->uart->SCFSR; - obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF - - core_util_critical_section_exit(); - - if (err_read & 0x80) { - data = -1; //err - } - return data; -} - -void serial_putc(serial_t *obj, int c) { - uint16_t dummy_read; - - core_util_critical_section_enter(); - obj->uart->SCSCR |= 0x0080; // Set TIE - core_util_critical_section_exit(); - while (!serial_writable(obj)); - obj->uart->SCFTDR = c; - core_util_critical_section_enter(); - dummy_read = obj->uart->SCFSR; - obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE - core_util_critical_section_exit(); - uart_data[obj->index].count++; -} - -int serial_readable(serial_t *obj) { - return ((obj->uart->SCFSR & 0x02) != 0); // RDF -} - -int serial_writable(serial_t *obj) { - return ((obj->uart->SCFSR & 0x20) != 0); // TDFE -} - -void serial_clear(serial_t *obj) { - core_util_critical_section_enter(); - obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 - obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 - obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 - core_util_critical_section_exit(); -} - -void serial_pinout_tx(PinName tx) { - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) { - core_util_critical_section_enter(); - // TxD Output(L) - obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 - obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) - core_util_critical_section_exit(); -} - -void serial_break_clear(serial_t *obj) { - core_util_critical_section_enter(); - obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) - obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 - core_util_critical_section_exit(); -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { - // determine the UART to use - serial_flow_irq_set(obj, 0); - - if (type == FlowControlRTSCTS) { - core_util_critical_section_enter(); - obj->uart->SCFCR = 0x0008u; // CTS/RTS enable - core_util_critical_section_exit(); - pinmap_pinout(rxflow, PinMap_UART_RTS); - pinmap_pinout(txflow, PinMap_UART_CTS); - } else { - core_util_critical_section_enter(); - obj->uart->SCFCR = 0x0000u; // CTS/RTS diable - core_util_critical_section_exit(); - } -} - - - - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c deleted file mode 100644 index 1464aaacd3..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c +++ /dev/null @@ -1,343 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include - -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "RZ_A1_Init.h" - - -#ifdef MAX_PERI -static const PinMap PinMap_SPI_SCLK[] = { - {P2_12 , SPI_0, 2}, - {P7_15 , SPI_0, 2}, - {P4_4 , SPI_1, 2}, - {P6_4 , SPI_1, 7}, - {P8_3 , SPI_2, 3}, - {P8_14 , SPI_2, 5}, - {P3_0 , SPI_3, 8}, - {P5_0 , SPI_3, 8}, - {P2_8 , SPI_4, 8}, - {P4_0 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P2_13 , SPI_0, 2}, - {P8_0 , SPI_0, 2}, - {P4_5 , SPI_1, 2}, - {P6_5 , SPI_1, 7}, - {P8_4 , SPI_2, 3}, - {P8_15 , SPI_2, 5}, - {P3_1 , SPI_3, 8}, - {P5_1 , SPI_3, 8}, - {P2_9 , SPI_4, 8}, - {P4_1 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P2_14 , SPI_0, 2}, - {P8_1 , SPI_0, 2}, - {P4_6 , SPI_1, 2}, - {P6_6 , SPI_1, 7}, - {P8_5 , SPI_2, 3}, - {P9_0 , SPI_2, 5}, - {P3_2 , SPI_3, 8}, - {P5_2 , SPI_3, 8}, - {P2_10 , SPI_4, 8}, - {P4_2 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P2_15 , SPI_0, 2}, - {P8_2 , SPI_0, 2}, - {P4_7 , SPI_1, 2}, - {P6_7 , SPI_1, 7}, - {P8_6 , SPI_2, 3}, - {P9_1 , SPI_2, 5}, - {P3_3 , SPI_3, 8}, - {P5_3 , SPI_3, 8}, - {P2_11 , SPI_4, 8}, - {P4_3 , SPI_4, 7}, - {NC , NC , 0} -}; -#else -static const PinMap PinMap_SPI_SCLK[] = { - {P4_4 , SPI_1, 2}, - {P8_14 , SPI_2, 5}, - {P5_0 , SPI_3, 8}, - {P4_0 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P4_5 , SPI_1, 2}, - {P8_15 , SPI_2, 5}, - {P5_1 , SPI_3, 8}, - {P4_1 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P4_6 , SPI_1, 2}, - {P9_0 , SPI_2, 5}, - {P5_2 , SPI_3, 8}, - {P4_2 , SPI_4, 7}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P4_7 , SPI_1, 2}, - {P9_1 , SPI_2, 5}, - {P5_3 , SPI_3, 8}, - {P4_3 , SPI_4, 7}, - {NC , NC , 0} -}; -#endif - - -static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; - -static inline void spi_disable(spi_t *obj); -static inline void spi_enable(spi_t *obj); -static inline int spi_readable(spi_t *obj); -static inline void spi_write(spi_t *obj, int value); -static inline int spi_read(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - // determine the SPI to use - volatile uint8_t dummy; - uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); - uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); - uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); - uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); - uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); - uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); - uint32_t spi = pinmap_merge(spi_data, spi_cntl); - - MBED_ASSERT((int)spi != NC); - - obj->spi = (struct st_rspi *)RSPI[spi]; - - // enable power and clocking - switch (spi) { - case SPI_1: CPGSTBCR10 &= ~(0x40); break; - case SPI_2: CPGSTBCR10 &= ~(0x20); break; - case SPI_3: CPGSTBCR10 &= ~(0x10); break; - case SPI_4: CPGSTBCR10 &= ~(0x08); break; - } - dummy = CPGSTBCR10; - - obj->spi->SPCR = 0x00; // CTRL to 0 - obj->spi->SPSCR = 0x00; // no sequential operation - obj->spi->SSLP = 0x00; // SSL 'L' active - obj->spi->SPDCR = 0x20; // byte access - obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK - obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK - obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK - obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0 - obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1 - obj->spi->SPBFCR = 0x30; // and reset buffer - - // pin out the spi pins - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - if ((int)ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); - } -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - int DSS; // DSS (data select size) - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - uint16_t tmp = 0; - uint16_t mask = 0xf03; - uint16_t wk_spcmd0; - uint8_t splw; - - switch (mode) { - case 0: - case 1: - case 2: - case 3: - // Do Nothing - break; - default: - error("SPI format error"); - return; - } - - switch (bits) { - case 8: - DSS = 0x7; - splw = 0x20; - break; - case 16: - DSS = 0xf; - splw = 0x40; - break; - case 32: - DSS = 0x2; - splw = 0x60; - break; - default: - error("SPI module don't support other than 8/16/32bits"); - return; - } - tmp |= phase; - tmp |= (polarity << 1); - tmp |= (DSS << 8); - obj->bits = bits; - - spi_disable(obj); - wk_spcmd0 = obj->spi->SPCMD0; - wk_spcmd0 &= ~mask; - wk_spcmd0 |= (mask & tmp); - obj->spi->SPCMD0 = wk_spcmd0; - obj->spi->SPDCR = splw; - if (slave) { - obj->spi->SPCR &=~(1 << 3); // MSTR to 0 - } else { - obj->spi->SPCR |= (1 << 3); // MSTR to 1 - } - spi_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - uint32_t pclk_base; - uint32_t div; - uint32_t brdv = 0; - uint32_t hz_max; - uint32_t hz_min; - uint16_t mask = 0x000c; - uint16_t wk_spcmd0; - - /* set PCLK */ - if (RZ_A1_IsClockMode0() == false) { - pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; - } else { - pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; - } - - hz_min = pclk_base / 2 / 256 / 8; - hz_max = pclk_base / 2; - if ((hz < hz_min) || (hz > hz_max)) { - error("Couldn't setup requested SPI frequency"); - return; - } - - div = (pclk_base / hz / 2); - while (div > 256) { - div >>= 1; - brdv++; - } - div -= 1; - brdv = (brdv << 2); - - spi_disable(obj); - obj->spi->SPBR = div; - wk_spcmd0 = obj->spi->SPCMD0; - wk_spcmd0 &= ~mask; - wk_spcmd0 |= (mask & brdv); - obj->spi->SPCMD0 = wk_spcmd0; - spi_enable(obj); -} - -static inline void spi_disable(spi_t *obj) { - obj->spi->SPCR &= ~(1 << 6); // SPE to 0 -} - -static inline void spi_enable(spi_t *obj) { - obj->spi->SPCR |= (1 << 6); // SPE to 1 -} - -static inline int spi_readable(spi_t *obj) { - return obj->spi->SPSR & (1 << 7); // SPRF -} - -static inline int spi_tend(spi_t *obj) { - return obj->spi->SPSR & (1 << 6); // TEND -} - -static inline void spi_write(spi_t *obj, int value) { - if (obj->bits == 8) { - obj->spi->SPDR.UINT8[0] = (uint8_t)value; - } else if (obj->bits == 16) { - obj->spi->SPDR.UINT16[0] = (uint16_t)value; - } else { - obj->spi->SPDR.UINT32 = (uint32_t)value; - } -} - -static inline int spi_read(spi_t *obj) { - int read_data; - - if (obj->bits == 8) { - read_data = obj->spi->SPDR.UINT8[0]; - } else if (obj->bits == 16) { - read_data = obj->spi->SPDR.UINT16[0]; - } else { - read_data = obj->spi->SPDR.UINT32; - } - - return read_data; -} - -int spi_master_write(spi_t *obj, int value) { - spi_write(obj, value); - while(!spi_tend(obj)); - return spi_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *obj) { - return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); -} - -int spi_slave_read(spi_t *obj) { - return spi_read(obj); -} - -void spi_slave_write(spi_t *obj, int value) { - spi_write(obj, value); -} - -int spi_busy(spi_t *obj) { - return 0; -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/us_ticker.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/us_ticker.c deleted file mode 100644 index e2c15edbde..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/us_ticker.c +++ /dev/null @@ -1,136 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" -#include "ostm_iodefine.h" - -#include "RZ_A1_Init.h" -#include "VKRZA1H.h" -#include "mbed_critical.h" - -#define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) -#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ - -#define US_TICKER_CLOCK_US_DEV (1000000) - -int us_ticker_inited = 0; -static double count_clock = 0; -static uint32_t last_read = 0; -static uint32_t wrap_arround = 0; -static uint64_t ticker_us_last64 = 0; - -void us_ticker_interrupt(void) { - us_ticker_irq_handler(); -} - -void us_ticker_init(void) { - if (us_ticker_inited) return; - us_ticker_inited = 1; - - /* set Counter Clock(us) */ - if (false == RZ_A1_IsClockMode0()) { - count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); - } else { - count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); - } - - /* Power Control for Peripherals */ - CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */ - - // timer settings - OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */ - OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ - - OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ - - // INTC settings - InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt); - GIC_SetPriority(US_TICKER_TIMER_IRQn, 5); - GIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -static uint64_t ticker_read_counter64(void) { - uint32_t cnt_val; - uint64_t cnt_val64; - - if (!us_ticker_inited) - us_ticker_init(); - - /* read counter */ - cnt_val = OSTM1CNT; - if (last_read > cnt_val) { - wrap_arround++; - } - last_read = cnt_val; - cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val; - - return cnt_val64; -} - -uint32_t us_ticker_read() { - uint64_t cnt_val64; - uint64_t us_val64; - - core_util_critical_section_enter(); - - cnt_val64 = ticker_read_counter64(); - us_val64 = (cnt_val64 / count_clock); - ticker_us_last64 = us_val64; - - core_util_critical_section_exit(); - /* clock to us */ - return (uint32_t)us_val64; -} - -void us_ticker_set_interrupt(timestamp_t timestamp) { - // set match value - uint64_t timestamp64; - uint64_t set_cmp_val64; - volatile uint32_t set_cmp_val; - uint64_t count_val_64; - - /* calc compare mach timestamp */ - timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp; - if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) { - /* This event is wrap arround */ - timestamp64 += 0x100000000; - } - - /* calc compare mach timestamp */ - set_cmp_val64 = timestamp64 * count_clock; - set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF); - count_val_64 = ticker_read_counter64(); - if (set_cmp_val64 <= (count_val_64 + 500)) { - GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); - GIC_EnableIRQ(US_TICKER_TIMER_IRQn); - return; - } - OSTM1CMP = set_cmp_val; - GIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -void us_ticker_fire_interrupt(void) { - GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); -} - -void us_ticker_disable_interrupt(void) { - GIC_DisableIRQ(US_TICKER_TIMER_IRQn); -} - -void us_ticker_clear_interrupt(void) { - GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn); -} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/analogin_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/analogin_api.c similarity index 89% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/analogin_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/analogin_api.c index 90dc113be4..c3eaac7961 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/analogin_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/analogin_api.c @@ -17,25 +17,12 @@ #include "analogin_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" -#include "adc_iodefine.h" -#include "cpg_iodefine.h" +#include "iodefine.h" #define ANALOGIN_MEDIAN_FILTER 0 -static const PinMap PinMap_ADC[] = { - {P1_8, AN0, 1}, - {P1_9, AN1, 1}, - {P1_10, AN2, 1}, - {P1_11, AN3, 1}, - {P1_12, AN4, 1}, - {P1_13, AN5, 1}, - {P1_14, AN6, 1}, - {P1_15, AN7, 1}, - {NC, NC, 0} -}; - static volatile uint16_t *ADCDR[] = { &ADCADDRA, &ADCADDRB, diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c similarity index 95% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/can_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c index 11bd6dcfc2..b91e608f87 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/can_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c @@ -18,12 +18,16 @@ #include "can_api.h" #include "RZ_A1_Init.h" #include "cmsis.h" -#include "pinmap.h" -#include "rscan0_iodefine.h" +#include "PeripheralPins.h" +#include "iodefine.h" #include "r_typedefs.h" -#include "MBRZA1H.h" +#include "mbed_drv_cfg.h" +#if defined(TARGET_RZA1H) #define CAN_NUM 5 +#else +#define CAN_NUM 2 +#endif #define CAN_SND_RCV 2 #define IRQ_NUM 8 @@ -31,40 +35,43 @@ static void can_rec_irq(uint32_t ch); static void can_trx_irq(uint32_t ch); static void can_err_irq(uint32_t ch, CanIrqType type); static void can0_rec_irq(void); -static void can1_rec_irq(void); -static void can2_rec_irq(void); -static void can3_rec_irq(void); -static void can4_rec_irq(void); static void can0_trx_irq(void); -static void can1_trx_irq(void); -static void can2_trx_irq(void); -static void can3_trx_irq(void); -static void can4_trx_irq(void); static void can0_err_warning_irq(void); -static void can1_err_warning_irq(void); -static void can2_err_warning_irq(void); -static void can3_err_warning_irq(void); -static void can4_err_warning_irq(void); static void can0_overrun_irq(void); -static void can1_overrun_irq(void); -static void can2_overrun_irq(void); -static void can3_overrun_irq(void); -static void can4_overrun_irq(void); static void can0_passive_irq(void); -static void can1_passive_irq(void); -static void can2_passive_irq(void); -static void can3_passive_irq(void); -static void can4_passive_irq(void); static void can0_arb_lost_irq(void); -static void can1_arb_lost_irq(void); -static void can2_arb_lost_irq(void); -static void can3_arb_lost_irq(void); -static void can4_arb_lost_irq(void); static void can0_bus_err_irq(void); +static void can1_rec_irq(void); +static void can1_trx_irq(void); +static void can1_err_warning_irq(void); +static void can1_overrun_irq(void); +static void can1_passive_irq(void); +static void can1_arb_lost_irq(void); static void can1_bus_err_irq(void); +#if defined(TARGET_RZA1H) +static void can2_rec_irq(void); +static void can2_trx_irq(void); +static void can2_err_warning_irq(void); +static void can2_overrun_irq(void); +static void can2_passive_irq(void); +static void can2_arb_lost_irq(void); static void can2_bus_err_irq(void); +static void can3_rec_irq(void); +static void can3_trx_irq(void); +static void can3_err_warning_irq(void); +static void can3_overrun_irq(void); +static void can3_passive_irq(void); +static void can3_arb_lost_irq(void); static void can3_bus_err_irq(void); +static void can4_rec_irq(void); +static void can4_trx_irq(void); +static void can4_err_warning_irq(void); +static void can4_overrun_irq(void); +static void can4_passive_irq(void); +static void can4_arb_lost_irq(void); static void can4_bus_err_irq(void); +#endif + static void can_reset_reg(can_t *obj); static void can_reset_recv_rule(can_t *obj); static void can_reset_buffer(can_t *obj); @@ -99,53 +106,25 @@ static can_irq_handler irq_handler; static uint32_t can_irq_id[CAN_NUM]; static int can_initialized[CAN_NUM] = {0}; -static const PinMap PinMap_CAN_RD[] = { - {P7_8 , CAN_0, 4}, - {P9_1 , CAN_0, 3}, - {P1_4 , CAN_1, 3}, - {P5_9 , CAN_1, 5}, - {P7_11 , CAN_1, 4}, - {P11_12, CAN_1, 1}, - {P4_9 , CAN_2, 6}, - {P6_4 , CAN_2, 3}, - {P7_2 , CAN_2, 5}, - {P2_12 , CAN_3, 5}, - {P4_2 , CAN_3, 4}, - {P1_5 , CAN_4, 3}, - {P2_14 , CAN_4, 5}, - {NC , NC , 0} -}; - -static const PinMap PinMap_CAN_TD[] = { - {P7_9 , CAN_0, 4}, - {P9_0 , CAN_0, 3}, - {P5_10 , CAN_1, 5}, - {P7_10 , CAN_1, 4}, - {P11_13, CAN_1, 1}, - {P4_8 , CAN_2, 6}, - {P6_5 , CAN_2, 3}, - {P7_3 , CAN_2, 5}, - {P2_13 , CAN_3, 5}, - {P4_3 , CAN_3, 4}, - {P4_11 , CAN_4, 6}, - {P8_10 , CAN_4, 5}, - {NC , NC , 0} -}; static __IO uint32_t *CTR_MATCH[] = { &RSCAN0C0CTR, &RSCAN0C1CTR, +#if defined(TARGET_RZA1H) &RSCAN0C2CTR, &RSCAN0C3CTR, &RSCAN0C4CTR, +#endif }; static __IO uint32_t *CFG_MATCH[] = { &RSCAN0C0CFG, &RSCAN0C1CFG, +#if defined(TARGET_RZA1H) &RSCAN0C2CFG, &RSCAN0C3CFG, &RSCAN0C4CFG, +#endif }; static __IO uint32_t *RFCC_MATCH[] = { @@ -162,89 +141,111 @@ static __IO uint32_t *RFCC_MATCH[] = { static __IO uint32_t *TXQCC_MATCH[] = { &RSCAN0TXQCC0, &RSCAN0TXQCC1, +#if defined(TARGET_RZA1H) &RSCAN0TXQCC2, &RSCAN0TXQCC3, &RSCAN0TXQCC4, +#endif }; static __IO uint32_t *THLCC_MATCH[] = { &RSCAN0THLCC0, &RSCAN0THLCC1, +#if defined(TARGET_RZA1H) &RSCAN0THLCC2, &RSCAN0THLCC3, &RSCAN0THLCC4, +#endif }; static __IO uint32_t *STS_MATCH[] = { &RSCAN0C0STS, &RSCAN0C1STS, +#if defined(TARGET_RZA1H) &RSCAN0C2STS, &RSCAN0C3STS, &RSCAN0C4STS, +#endif }; static __IO uint32_t *ERFL_MATCH[] = { &RSCAN0C0ERFL, &RSCAN0C1ERFL, +#if defined(TARGET_RZA1H) &RSCAN0C2ERFL, &RSCAN0C3ERFL, &RSCAN0C4ERFL, +#endif }; static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFCC0 , &RSCAN0CFCC1 }, { &RSCAN0CFCC3 , &RSCAN0CFCC4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFCC6 , &RSCAN0CFCC7 }, { &RSCAN0CFCC9 , &RSCAN0CFCC10 }, - { &RSCAN0CFCC12, &RSCAN0CFCC13 } + { &RSCAN0CFCC12, &RSCAN0CFCC13 }, +#endif }; static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 }, { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 }, { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 }, - { &RSCAN0CFSTS12, &RSCAN0CFSTS13 } + { &RSCAN0CFSTS12, &RSCAN0CFSTS13 }, +#endif }; static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 }, { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 }, { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 }, - { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 } + { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 }, +#endif }; static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFID0 , &RSCAN0CFID1 }, { &RSCAN0CFID3 , &RSCAN0CFID4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFID6 , &RSCAN0CFID7 }, { &RSCAN0CFID9 , &RSCAN0CFID10 }, - { &RSCAN0CFID12, &RSCAN0CFID13 } + { &RSCAN0CFID12, &RSCAN0CFID13 }, +#endif }; static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 }, { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 }, { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 }, { &RSCAN0CFPTR12, &RSCAN0CFPTR13 } +#endif }; static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFDF00 , &RSCAN0CFDF01 }, { &RSCAN0CFDF03 , &RSCAN0CFDF04 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFDF06 , &RSCAN0CFDF07 }, { &RSCAN0CFDF09 , &RSCAN0CFDF010 }, - { &RSCAN0CFDF012, &RSCAN0CFDF013 } + { &RSCAN0CFDF012, &RSCAN0CFDF013 }, +#endif }; static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = { { &RSCAN0CFDF10 , &RSCAN0CFDF11 }, { &RSCAN0CFDF13 , &RSCAN0CFDF14 }, +#if defined(TARGET_RZA1H) { &RSCAN0CFDF16 , &RSCAN0CFDF17 }, { &RSCAN0CFDF19 , &RSCAN0CFDF110 }, - { &RSCAN0CFDF112, &RSCAN0CFDF113 } + { &RSCAN0CFDF112, &RSCAN0CFDF113 }, +#endif }; static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = @@ -269,6 +270,7 @@ static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */ { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */ }, +#if defined(TARGET_RZA1H) { /* ch2 */ { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */ { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */ @@ -298,7 +300,8 @@ static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */ { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */ { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */ - } + }, +#endif }; static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0; @@ -404,141 +407,143 @@ static void can0_rec_irq(void) { can_rec_irq(CAN_0); } -static void can1_rec_irq(void) { - can_rec_irq(CAN_1); -} - -static void can2_rec_irq(void) { - can_rec_irq(CAN_2); -} - -static void can3_rec_irq(void) { - can_rec_irq(CAN_3); -} - -static void can4_rec_irq(void) { - can_rec_irq(CAN_4); -} - static void can0_trx_irq(void) { can_trx_irq(CAN_0); } -static void can1_trx_irq(void) { - can_trx_irq(CAN_1); -} - -static void can2_trx_irq(void) { - can_trx_irq(CAN_2); -} - -static void can3_trx_irq(void) { - can_trx_irq(CAN_3); -} - -static void can4_trx_irq(void) { - can_trx_irq(CAN_4); -} - static void can0_err_warning_irq(void) { can_err_irq(CAN_0, IRQ_ERROR); } -static void can1_err_warning_irq(void) { - can_err_irq(CAN_1, IRQ_ERROR); -} - -static void can2_err_warning_irq(void) { - can_err_irq(CAN_2, IRQ_ERROR); -} - -static void can3_err_warning_irq(void) { - can_err_irq(CAN_3, IRQ_ERROR); -} - -static void can4_err_warning_irq(void) { - can_err_irq(CAN_4, IRQ_ERROR); -} - static void can0_overrun_irq(void) { can_err_irq(CAN_0, IRQ_OVERRUN); } -static void can1_overrun_irq(void) { - can_err_irq(CAN_1, IRQ_OVERRUN); -} - -static void can2_overrun_irq(void) { - can_err_irq(CAN_2, IRQ_OVERRUN); -} - -static void can3_overrun_irq(void) { - can_err_irq(CAN_3, IRQ_OVERRUN); -} - -static void can4_overrun_irq(void) { - can_err_irq(CAN_4, IRQ_OVERRUN); -} - static void can0_passive_irq(void) { can_err_irq(CAN_0, IRQ_PASSIVE); } -static void can1_passive_irq(void) { - can_err_irq(CAN_1, IRQ_PASSIVE); -} - -static void can2_passive_irq(void) { - can_err_irq(CAN_2, IRQ_PASSIVE); -} - -static void can3_passive_irq(void) { - can_err_irq(CAN_3, IRQ_PASSIVE); -} - -static void can4_passive_irq(void) { - can_err_irq(CAN_4, IRQ_PASSIVE); -} - static void can0_arb_lost_irq(void) { can_err_irq(CAN_0, IRQ_ARB); } -static void can1_arb_lost_irq(void) { - can_err_irq(CAN_1, IRQ_ARB); -} - -static void can2_arb_lost_irq(void) { - can_err_irq(CAN_2, IRQ_ARB); -} - -static void can3_arb_lost_irq(void) { - can_err_irq(CAN_3, IRQ_ARB); -} - -static void can4_arb_lost_irq(void) { - can_err_irq(CAN_4, IRQ_ARB); -} - static void can0_bus_err_irq(void) { can_err_irq(CAN_0, IRQ_BUS); } +static void can1_rec_irq(void) { + can_rec_irq(CAN_1); +} + +static void can1_trx_irq(void) { + can_trx_irq(CAN_1); +} + +static void can1_err_warning_irq(void) { + can_err_irq(CAN_1, IRQ_ERROR); +} + +static void can1_overrun_irq(void) { + can_err_irq(CAN_1, IRQ_OVERRUN); +} + +static void can1_passive_irq(void) { + can_err_irq(CAN_1, IRQ_PASSIVE); +} + +static void can1_arb_lost_irq(void) { + can_err_irq(CAN_1, IRQ_ARB); +} + static void can1_bus_err_irq(void) { can_err_irq(CAN_1, IRQ_BUS); } +#if defined(TARGET_RZA1H) +static void can2_rec_irq(void) { + can_rec_irq(CAN_2); +} + +static void can2_trx_irq(void) { + can_trx_irq(CAN_2); +} + +static void can2_err_warning_irq(void) { + can_err_irq(CAN_2, IRQ_ERROR); +} + +static void can2_overrun_irq(void) { + can_err_irq(CAN_2, IRQ_OVERRUN); +} + +static void can2_passive_irq(void) { + can_err_irq(CAN_2, IRQ_PASSIVE); +} + +static void can2_arb_lost_irq(void) { + can_err_irq(CAN_2, IRQ_ARB); +} + static void can2_bus_err_irq(void) { can_err_irq(CAN_2, IRQ_BUS); } +static void can3_rec_irq(void) { + can_rec_irq(CAN_3); +} + +static void can3_trx_irq(void) { + can_trx_irq(CAN_3); +} + +static void can3_err_warning_irq(void) { + can_err_irq(CAN_3, IRQ_ERROR); +} + +static void can3_overrun_irq(void) { + can_err_irq(CAN_3, IRQ_OVERRUN); +} + +static void can3_passive_irq(void) { + can_err_irq(CAN_3, IRQ_PASSIVE); +} + +static void can3_arb_lost_irq(void) { + can_err_irq(CAN_3, IRQ_ARB); +} + static void can3_bus_err_irq(void) { can_err_irq(CAN_3, IRQ_BUS); } +static void can4_rec_irq(void) { + can_rec_irq(CAN_4); +} + +static void can4_trx_irq(void) { + can_trx_irq(CAN_4); +} + +static void can4_err_warning_irq(void) { + can_err_irq(CAN_4, IRQ_ERROR); +} + +static void can4_overrun_irq(void) { + can_err_irq(CAN_4, IRQ_OVERRUN); +} + +static void can4_passive_irq(void) { + can_err_irq(CAN_4, IRQ_PASSIVE); +} + +static void can4_arb_lost_irq(void) { + can_err_irq(CAN_4, IRQ_ARB); +} + static void can4_bus_err_irq(void) { can_err_irq(CAN_4, IRQ_BUS); } +#endif void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) { __IO uint32_t *dmy_ctr; @@ -763,9 +768,9 @@ int can_mode(can_t *obj, CanMode mode) { can_set_channel_mode(obj->ch, CH_COMM); break; case MODE_TEST_GLOBAL: - /* set the channel between the communication test on channel 1 and channel 2 */ + /* set the channel between the communication test on CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */ /* set Channel Hold mode */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { + for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) { dmy_sts = STS_MATCH[tmp_obj->ch]; if ((*dmy_sts & 0x04) == 0x04) { /* Channel Stop mode */ @@ -777,11 +782,11 @@ int can_mode(can_t *obj, CanMode mode) { can_set_channel_mode(tmp_obj->ch, CH_HOLD); } can_set_global_mode(GL_TEST); - /* enable communication test between channel1 and channel2 */ + /* enable communication test between CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */ RSCAN0GTSTCFG = 0x06; RSCAN0GTSTCTR = 0x01; /* send and receive setting of channel1 and channel2 */ - for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { + for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) { can_reset_buffer(tmp_obj); /* set global interrrupt */ /* THLEIE, MEIE and DEIE interrupts are disable */ @@ -888,7 +893,9 @@ static void can_reset_reg(can_t *obj) { static void can_reset_recv_rule(can_t *obj) { /* number of receive rules of each chanel = 64 */ RSCAN0GAFLCFG0 = 0x40404040; +#if defined(TARGET_RZA1H) RSCAN0GAFLCFG1 = 0x40000000; +#endif /* enable receive rule table writing */ RSCAN0GAFLECTR = 0x00000100; /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */ @@ -939,8 +946,10 @@ static void can_reset_buffer(can_t *obj) { *dmy_cfcc |= 0x02; /* TMIEp interrupt is disable */ RSCAN0TMIEC0 = 0x00000000; +#if defined(TARGET_RZA1H) RSCAN0TMIEC1 = 0x00000000; RSCAN0TMIEC2 = 0x00000000; +#endif } static void can_reconfigure_channel(void) { @@ -1003,9 +1012,9 @@ static void can_set_frequency(can_t *obj, int f) { static void can_set_global_mode(int mode) { /* set Global mode */ - RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode); + RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | (uint32_t)mode); /* Wait to cahnge into Global XXXX mode */ - while ((RSCAN0GSTS & 0x07) != mode) { + while ((RSCAN0GSTS & 0x07) != (uint32_t)mode) { __NOP(); } } @@ -1016,10 +1025,10 @@ static void can_set_channel_mode(uint32_t ch, int mode) { /* set Channel mode */ dmy_ctr = CTR_MATCH[ch]; - *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode); + *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | (uint32_t)mode); /* Wait to cahnge into Channel XXXX mode */ dmy_sts = STS_MATCH[ch]; - while ((*dmy_sts & 0x07) != mode) { + while ((*dmy_sts & 0x07) != (uint32_t)mode) { __NOP(); } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/ethernet_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c similarity index 95% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/ethernet_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c index 706e75cc6f..ae3317b20d 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/ethernet_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c @@ -19,9 +19,11 @@ #include "mbed_interface.h" #include "mbed_toolchain.h" #include "mbed_error.h" -#include "ether_iodefine.h" +#include "iodefine.h" #include "ethernetext_api.h" +#if DEVICE_ETHERNET + /* Descriptor info */ #define NUM_OF_TX_DESCRIPTOR (16) #define NUM_OF_RX_DESCRIPTOR (16) @@ -160,6 +162,7 @@ int ethernetext_init(ethernet_cfg_t *p_ethcfg) { CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ +#if defined(TARGET_RZ_A1H) /* P4_2(PHY Reset) */ GPIOP4 &= ~0x0004; /* Outputs low level */ GPIOPMC4 &= ~0x0004; /* Port mode */ @@ -201,6 +204,41 @@ int ethernetext_init(ethernet_cfg_t *p_ethcfg) { wait_100us(250); /* 25msec */ GPIOP4 |= 0x0004; /* P4_2 Outputs high level */ wait_100us(100); /* 10msec */ +#elif defined(TARGET_VK_RZ_A1H) + /* -->4F<-- P1_14(ET_COL) */ + GPIOPMC1 |= 0x4000; + GPIOPFCAE1 &= ~0x4000; + GPIOPFCE1 |= 0x4000; + GPIOPFC1 |= 0x4000; + GPIOPIPC1 |= 0x4000; + + /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0), + P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */ + GPIOPMC2 |= 0x0FFF; + GPIOPFCAE2 &= ~0x0FFF; + GPIOPFCE2 &= ~0x0FFF; + GPIOPFC2 |= 0x0FFF; + GPIOPIPC2 |= 0x0FFF; + + /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ + GPIOPMC3 |= 0x0078; + GPIOPFCAE3 &= ~0x0078; + GPIOPFCE3 &= ~0x0078; + GPIOPFC3 |= 0x0078; + GPIOPIPC3 |= 0x0078; + + /* -->3F<-- P7_0(ET_MDC) */ + GPIOPMC7 |= 0x0001; + GPIOPFCAE7 &= ~0x0001; + GPIOPFCE7 |= 0x0001; + GPIOPFC7 &= ~0x0001; + GPIOPIPC7 |= 0x0001; + + /* Resets the E-MAC,E-DMAC */ + lan_reg_reset(); +#else +#error "There is no initialization processing." +#endif /* Resets the PHY-LSI */ phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); @@ -708,3 +746,4 @@ static void wait_100us(int32_t wait_cnt) { /* Do Nothing */ } } +#endif /* DEVICE_ETHERNET */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_api.c similarity index 96% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_api.c index a0540aa825..ea1351c769 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_api.c @@ -16,6 +16,7 @@ #include "gpio_api.h" #include "pinmap.h" #include "gpio_addrdefine.h" +#include "mbed_drv_cfg.h" uint32_t gpio_set(PinName pin) { @@ -31,7 +32,7 @@ void gpio_init(gpio_t *obj, PinName pin) { obj->mask = gpio_set(pin); group = PINGROUP(pin); - if (group > 9) return; + if (group > GPIO_GROUP_MAX) return; obj->reg_set = (volatile uint32_t *) PSR(group); obj->reg_in = (volatile uint32_t *) PPR(group); diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c similarity index 77% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_irq_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c index e63ab2594e..5c0950f556 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_irq_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c @@ -16,8 +16,8 @@ #include #include "gpio_irq_api.h" -#include "intc_iodefine.h" -#include "pinmap.h" +#include "iodefine.h" +#include "PeripheralPins.h" #include "cmsis.h" #include "gpio_addrdefine.h" @@ -37,14 +37,6 @@ static gpio_irq_handler irq_handler; static const int nIRQn_h = 32; extern PinName gpio_multi_guard; -enum { - IRQ0,IRQ1, - IRQ2,IRQ3, - IRQ4,IRQ5, - IRQ6,IRQ7, - -} IRQNo; - static const IRQHandler irq_tbl[CHANNEL_NUM] = { &gpio_irq0, &gpio_irq1, @@ -56,34 +48,6 @@ static const IRQHandler irq_tbl[CHANNEL_NUM] = { &gpio_irq7, }; -static const PinMap PinMap_IRQ[] = { - {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4}, - {P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4}, - {P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3}, - {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11 - {P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8}, - {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16 - {P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3}, - {P3_9, IRQ6, 8}, // 20 - {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8}, - {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8}, - {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28 - {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31 - {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4}, - {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8}, - {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8}, - {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8}, - {P6_15, IRQ7, 8}, // 44 - {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8}, - {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8}, - {P7_14, IRQ6, 8}, // 51 - {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4}, - {P9_1, IRQ0, 4}, // 55 - {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57 - - {NC, NC, 0} -}; - static void handle_interrupt_in(int irq_num) { uint16_t irqs; uint16_t edge_req; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c similarity index 98% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/i2c_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c index be70f1eb80..227ac68f4e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/i2c_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c @@ -17,12 +17,11 @@ #include "dma_api.h" #include "i2c_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "r_typedefs.h" -#include "riic_iodefine.h" +#include "iodefine.h" #include "RZ_A1_Init.h" -#include "MBRZA1H.h" volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; @@ -61,20 +60,6 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; #define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ -static const PinMap PinMap_I2C_SDA[] = { - {P1_1 , I2C_0, 1}, - {P1_3 , I2C_1, 1}, - {P1_7 , I2C_3, 1}, - {NC , NC , 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {P1_0 , I2C_0, 1}, - {P1_2 , I2C_1, 1}, - {P1_6 , I2C_3, 1}, - {NC , NC, 0} -}; - static inline int i2c_status(i2c_t *obj) { return REG(SR2.UINT8[0]); } @@ -220,6 +205,7 @@ static inline void i2c_power_enable(i2c_t *obj) { break; } dummy = CPGSTBCR9; + (void)dummy; } void i2c_init(i2c_t *obj, PinName sda, PinName scl) { @@ -414,7 +400,6 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count = 0; int status; int value; - volatile uint32_t work_reg = 0; i2c_set_MR3_ACK(obj); /* There is a STOP condition for last processing */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/objects.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/objects.h similarity index 98% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/objects.h rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/objects.h index e6b0455d88..be1a9e5487 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/objects.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/objects.h @@ -22,7 +22,6 @@ #include "PeripheralNames.h" #include "PinNames.h" #include "gpio_object.h" -#include "rspi_iodefine.h" #ifdef __cplusplus extern "C" { @@ -41,6 +40,7 @@ struct i2c_s { struct spi_s { struct st_rspi *spi; uint32_t bits; + int index; }; struct gpio_irq_s { diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c new file mode 100644 index 0000000000..aa096aa1a1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PeripheralPins.h" +#include "mbed_error.h" +#include "gpio_addrdefine.h" + +PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ + +void pin_function(PinName pin, int function) { + if (pin == (PinName)NC) return; + + int n = pin >> 4; + int bitmask = 1<<(pin & 0xf); + const PinFunc * Pipc_0_func = PIPC_0_tbl; + int pipc_data = 1; + + if (gpio_multi_guard != pin) { + if (function == 0) { + // means GPIO mode + *PMC(n) &= ~bitmask; + } else { + // alt-function mode + --function; + + if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} + if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} + if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} + + while (Pipc_0_func->pin != NC) { + if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) { + pipc_data = 0; + if (Pipc_0_func->pm == 0) { + *PMSR(n) = (bitmask << 16) | 0; + } else if (Pipc_0_func->pm == 1) { + *PMSR(n) = (bitmask << 16) | bitmask; + } else { + // Do Nothing + } + break; + } + Pipc_0_func++; + } + if (pipc_data == 1) { + *PIPC(n) |= bitmask; + } else { + *PIPC(n) &= ~bitmask; + } + + if (P1_0 <= pin && pin <= P1_7 && function == 0) { + *PBDC(n) |= bitmask; + } + *PMC(n) |= bitmask; + } + } else { + gpio_multi_guard = (PinName)NC; + } +} + +void pin_mode(PinName pin, PinMode mode) { +// if (pin == (PinName)NC) { return; } +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/port_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/port_api.c similarity index 86% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/port_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/port_api.c index a330077018..91cc3056cb 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/port_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/port_api.c @@ -23,20 +23,20 @@ PinName port_pin(PortName port, int pin_n) { } void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + uint32_t i; + obj->port = port; obj->mask = mask; - obj->reg_dir = (volatile uint32_t *)PMSR(port); obj->reg_out = (volatile uint32_t *)PORT(port); obj->reg_in = (volatile uint32_t *)PPR(port); obj->reg_buf = (volatile uint32_t *)PIBC(port); // Do not use masking, because it prevents the use of the unmasked pins // port_reg->FIOMASK = ~mask; - - uint32_t i; + // The function is set per pin: reuse gpio logic - for (i=0; i<32; i++) { - if (obj->mask & (1<mask & (1 << i)) { gpio_set(port_pin(obj->port, i)); } } @@ -47,8 +47,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { void port_mode(port_t *obj, PinMode mode) { uint32_t i; // The mode is set per pin: reuse pinmap logic - for (i=0; i<32; i++) { - if (obj->mask & (1<mask & (1 << i)) { pin_mode(port_pin(obj->port, i), mode); } } @@ -57,11 +57,14 @@ void port_mode(port_t *obj, PinMode mode) { void port_dir(port_t *obj, PinDirection dir) { switch (dir) { case PIN_INPUT : *obj->reg_dir = (obj->mask << 16) | obj->mask; - *obj->reg_buf |= obj->mask; - break; + *obj->reg_buf |= obj->mask; + break; case PIN_OUTPUT: *obj->reg_dir = (obj->mask << 16) | ~obj->mask; - *obj->reg_buf &= ~obj->mask; - break; + *obj->reg_buf &= ~obj->mask; + break; + default: + // do nothing + break; } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c similarity index 71% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pwmout_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c index 469fe6fed4..0bed1c4aa3 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pwmout_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c @@ -16,139 +16,120 @@ #include "mbed_assert.h" #include "pwmout_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "RZ_A1_Init.h" -#include "cpg_iodefine.h" -#include "pwm_iodefine.h" +#include "iodefine.h" #include "gpio_addrdefine.h" +#include "mbed_drv_cfg.h" -#define MTU2_PWM_NUM 22 -#define MTU2_PWM_SIGNAL 2 #define MTU2_PWM_OFFSET 0x20 -// PORT ID, PWM ID, Pin function -static const PinMap PinMap_PWM[] = { - {P2_1 , MTU2_PWM0_PIN , 6}, - {P2_11 , MTU2_PWM1_PIN , 5}, - {P3_8 , MTU2_PWM2_PIN , 6}, - {P3_10 , MTU2_PWM3_PIN , 6}, - {P4_0 , MTU2_PWM4_PIN , 2}, - {P4_4 , MTU2_PWM5_PIN , 3}, - {P4_6 , MTU2_PWM6_PIN , 3}, - {P5_0 , MTU2_PWM7_PIN , 6}, - {P5_3 , MTU2_PWM8_PIN , 6}, - {P5_5 , MTU2_PWM9_PIN , 6}, - {P7_2 , MTU2_PWM10_PIN , 7}, - {P7_4 , MTU2_PWM11_PIN , 7}, - {P7_6 , MTU2_PWM12_PIN , 7}, - {P7_10 , MTU2_PWM13_PIN , 7}, - {P7_12 , MTU2_PWM14_PIN , 7}, - {P7_14 , MTU2_PWM15_PIN , 7}, - {P8_8 , MTU2_PWM16_PIN , 5}, - {P8_10 , MTU2_PWM17_PIN , 4}, - {P8_12 , MTU2_PWM18_PIN , 4}, - {P8_14 , MTU2_PWM19_PIN , 4}, - {P11_0 , MTU2_PWM20_PIN , 2}, - {P11_2 , MTU2_PWM21_PIN , 2}, - {P4_4 , PWM0_PIN , 4}, - {P3_2 , PWM1_PIN , 7}, - {P4_6 , PWM2_PIN , 4}, - {P4_7 , PWM3_PIN , 4}, - {P8_14 , PWM4_PIN , 6}, - {P8_15 , PWM5_PIN , 6}, - {P8_13 , PWM6_PIN , 6}, - {P8_11 , PWM7_PIN , 6}, - {P8_8 , PWM8_PIN , 6}, - {P10_0 , PWM9_PIN , 3}, - {P8_12 , PWM10_PIN , 6}, - {P8_9 , PWM11_PIN , 6}, - {P8_10 , PWM12_PIN , 6}, - {P4_5 , PWM13_PIN , 4}, - {NC , NC , 0} -}; +#ifdef FUNC_MOTOR_CTL_PWM +typedef enum { + PWM1A = 0, + PWM1B, + PWM1C, + PWM1D, + PWM1E, + PWM1F, + PWM1G, + PWM1H, + PWM2A = 0x10, + PWM2B, + PWM2C, + PWM2D, + PWM2E, + PWM2F, + PWM2G, + PWM2H, +} PWMType; static const PWMType PORT[] = { - PWM2E, // PWM0_PIN - PWM2C, // PWM1_PIN - PWM2G, // PWM2_PIN - PWM2H, // PWM3_PIN - PWM1G, // PWM4_PIN - PWM1H, // PWM5_PIN - PWM1F, // PWM6_PIN - PWM1D, // PWM7_PIN - PWM1A, // PWM8_PIN - PWM2A, // PWM9_PIN - PWM1E, // PWM10_PIN - PWM1B, // PWM11_PIN - PWM1C, // PWM12_PIN - PWM2F, // PWM13_PIN -}; - -static const MTU2_PWMType MTU2_PORT[] = { - TIOC2A, // MTU2_PWM0_PIN - TIOC1A, // MTU2_PWM1_PIN - TIOC4A, // MTU2_PWM2_PIN - TIOC4C, // MTU2_PWM3_PIN - TIOC0A, // MTU2_PWM4_PIN - TIOC4A, // MTU2_PWM5_PIN - TIOC4C, // MTU2_PWM6_PIN - TIOC0A, // MTU2_PWM7_PIN - TIOC3C, // MTU2_PWM8_PIN - TIOC0C, // MTU2_PWM9_PIN - TIOC0C, // MTU2_PWM10_PIN - TIOC1A, // MTU2_PWM11_PIN - TIOC2A, // MTU2_PWM12_PIN - TIOC3C, // MTU2_PWM13_PIN - TIOC4A, // MTU2_PWM14_PIN - TIOC4C, // MTU2_PWM15_PIN - TIOC1A, // MTU2_PWM16_PIN - TIOC3A, // MTU2_PWM17_PIN - TIOC3C, // MTU2_PWM18_PIN - TIOC2A, // MTU2_PWM19_PIN - TIOC4A, // MTU2_PWM20_PIN - TIOC4C, // MTU2_PWM21_PIN + PWM1A, // PWM_PWM1A + PWM1B, // PWM_PWM1B + PWM1C, // PWM_PWM1C + PWM1D, // PWM_PWM1D + PWM1E, // PWM_PWM1E + PWM1F, // PWM_PWM1F + PWM1G, // PWM_PWM1G + PWM1H, // PWM_PWM1H + PWM2A, // PWM_PWM2A + PWM2B, // PWM_PWM2B + PWM2C, // PWM_PWM2C + PWM2D, // PWM_PWM2D + PWM2E, // PWM_PWM2E + PWM2F, // PWM_PWM2F + PWM2G, // PWM_PWM2G + PWM2H, // PWM_PWM2H }; static __IO uint16_t *PWM_MATCH[] = { - &PWMPWBFR_2E, // PWM0_PIN - &PWMPWBFR_2C, // PWM1_PIN - &PWMPWBFR_2G, // PWM2_PIN - &PWMPWBFR_2G, // PWM3_PIN - &PWMPWBFR_1G, // PWM4_PIN - &PWMPWBFR_1G, // PWM5_PIN - &PWMPWBFR_1E, // PWM6_PIN - &PWMPWBFR_1C, // PWM7_PIN - &PWMPWBFR_1A, // PWM8_PIN - &PWMPWBFR_2A, // PWM9_PIN - &PWMPWBFR_1E, // PWM10_PIN - &PWMPWBFR_1A, // PWM11_PIN - &PWMPWBFR_1C, // PWM12_PIN - &PWMPWBFR_2E, // PWM13_PIN + &PWMPWBFR_1A, // PWM_PWM1A + &PWMPWBFR_1A, // PWM_PWM1B + &PWMPWBFR_1C, // PWM_PWM1C + &PWMPWBFR_1C, // PWM_PWM1D + &PWMPWBFR_1E, // PWM_PWM1E + &PWMPWBFR_1E, // PWM_PWM1F + &PWMPWBFR_1G, // PWM_PWM1G + &PWMPWBFR_1G, // PWM_PWM1H + &PWMPWBFR_2A, // PWM_PWM2A + &PWMPWBFR_2A, // PWM_PWM2B + &PWMPWBFR_2C, // PWM_PWM2C + &PWMPWBFR_2C, // PWM_PWM2D + &PWMPWBFR_2E, // PWM_PWM2E + &PWMPWBFR_2E, // PWM_PWM2F + &PWMPWBFR_2G, // PWM_PWM2G + &PWMPWBFR_2G, // PWM_PWM2H }; -static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM0_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM1_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM2_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM3_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM4_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM5_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM6_PIN - { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM7_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM8_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM9_PIN - { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM10_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM11_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM12_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM13_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM14_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM15_PIN - { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM16_PIN - { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM17_PIN - { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM18_PIN - { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM19_PIN - { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM20_PIN - { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM21_PIN +static uint16_t init_period_ch1 = 0; +static uint16_t init_period_ch2 = 0; +static int32_t period_ch1 = 1; +static int32_t period_ch2 = 1; +#endif + +#ifdef FUMC_MTU2_PWM +#define MTU2_PWM_SIGNAL 2 + +typedef enum { + TIOC0A = 0, + TIOC0B, + TIOC0C, + TIOC0D, + TIOC1A = 0x10, + TIOC1B, + TIOC2A = 0x20, + TIOC2B, + TIOC3A = 0x30, + TIOC3B, + TIOC3C, + TIOC3D, + TIOC4A = 0x40, + TIOC4B, + TIOC4C, + TIOC4D, +} MTU2_PWMType; + +static const MTU2_PWMType MTU2_PORT[] = { + TIOC0A, // PWM_TIOC0A + TIOC0C, // PWM_TIOC0C + TIOC1A, // PWM_TIOC1A + TIOC2A, // PWM_TIOC2A + TIOC3A, // PWM_TIOC3A + TIOC3C, // PWM_TIOC3C + TIOC4A, // PWM_TIOC4A + TIOC4C, // PWM_TIOC4C +}; + +static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = { + { &MTU2TGRA_0, &MTU2TGRB_0 }, // PWM_TIOC0A + { &MTU2TGRC_0, &MTU2TGRD_0 }, // PWM_TIOC0C + { &MTU2TGRA_1, &MTU2TGRB_1 }, // PWM_TIOC1A + { &MTU2TGRA_2, &MTU2TGRB_2 }, // PWM_TIOC2A + { &MTU2TGRA_3, &MTU2TGRB_3 }, // PWM_TIOC3A + { &MTU2TGRC_3, &MTU2TGRD_3 }, // PWM_TIOC3C + { &MTU2TGRA_4, &MTU2TGRB_4 }, // PWM_TIOC4A + { &MTU2TGRC_4, &MTU2TGRD_4 }, // PWM_TIOC4C }; static __IO uint8_t *TCR_MATCH[] = { @@ -212,12 +193,9 @@ typedef enum { MTU2_PERIOD } MTU2Signal; -static uint16_t init_period_ch1 = 0; -static uint16_t init_period_ch2 = 0; static uint16_t init_mtu2_period_ch[5] = {0}; -static int32_t period_ch1 = 1; -static int32_t period_ch2 = 1; static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; +#endif void pwmout_init(pwmout_t* obj, PinName pin) { // determine the channel @@ -225,6 +203,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) { MBED_ASSERT(pwm != (PWMName)NC); if (pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ int tmp_pwm; @@ -260,7 +239,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) { pwmout_period_us(obj, 1000); init_mtu2_period_ch[obj->ch] = 1; } +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ // power on CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); @@ -287,6 +268,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) { pwmout_period_us(obj, 491); init_period_ch1 = 1; } +#endif } } @@ -296,12 +278,12 @@ void pwmout_free(pwmout_t* obj) { void pwmout_write(pwmout_t* obj, float value) { uint32_t wk_cycle; - uint16_t v; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ int tmp_pwm; - + if (value < 0.0f) { value = 0.0f; } else if (value > 1.0f) { @@ -312,8 +294,16 @@ void pwmout_write(pwmout_t* obj, float value) { tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; // set channel match to percentage - *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); + if (value == 1.0f) { + *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1); + } else { + *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); + } +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM + uint16_t v; + /* PWM */ if (value < 0.0f) { value = 0.0f; @@ -332,6 +322,7 @@ void pwmout_write(pwmout_t* obj, float value) { // set channel match to percentage v = (uint16_t)((float)wk_cycle * value); *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); +#endif } } @@ -340,6 +331,7 @@ float pwmout_read(pwmout_t* obj) { float value; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ uint32_t wk_pulse; int tmp_pwm; @@ -348,7 +340,9 @@ float pwmout_read(pwmout_t* obj) { wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; value = ((float)wk_pulse / (float)wk_cycle); +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ if (obj->ch == 2) { wk_cycle = PWMPWCYR_2 & 0x03ff; @@ -356,6 +350,7 @@ float pwmout_read(pwmout_t* obj) { wk_cycle = PWMPWCYR_1 & 0x03ff; } value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); +#endif } return (value > 1.0f) ? (1.0f) : (value); @@ -369,6 +364,7 @@ void pwmout_period_ms(pwmout_t* obj, int ms) { pwmout_period_us(obj, ms * 1000); } +#ifdef FUNC_MOTOR_CTL_PWM static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ uint16_t wk_pwmpbfr; float value; @@ -379,7 +375,9 @@ static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16 v = (uint16_t)((float)new_cycle * value); *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); } +#endif +#ifdef FUMC_MTU2_PWM static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ uint16_t wk_pwmpbfr; float value; @@ -388,17 +386,20 @@ static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, u value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); *p_pwmpbfr = (uint16_t)((float)new_cycle * value); } +#endif // Set the PWM period, keeping the duty cycle the same. void pwmout_period_us(pwmout_t* obj, int us) { - uint64_t wk_cycle_mtu2; uint32_t pclk_base; uint32_t wk_cycle; uint32_t wk_cks = 0; uint16_t wk_last_cycle; - int max_us = 0; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM + uint64_t wk_cycle_mtu2; + int max_us = 0; + /* PWM by MTU2 */ int tmp_pwm; uint8_t tmp_tcr_up; @@ -432,7 +433,7 @@ void pwmout_period_us(pwmout_t* obj, int us) { wk_cks++; } wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); - + tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { tmp_tcr_up = 0xC0; @@ -468,7 +469,9 @@ void pwmout_period_us(pwmout_t* obj, int us) { MTU2TSTR |= tmp_tstr_st; // Save for future use mtu2_period_ch[obj->ch] = us; +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ if (us > 491) { us = 491; @@ -524,6 +527,7 @@ void pwmout_period_us(pwmout_t* obj, int us) { // Save for future use period_ch1 = us; } +#endif } } @@ -539,11 +543,14 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) { float value = 0; if (obj->pwm >= MTU2_PWM_OFFSET) { +#ifdef FUMC_MTU2_PWM /* PWM by MTU2 */ if (mtu2_period_ch[obj->ch] != 0) { value = (float)us / (float)mtu2_period_ch[obj->ch]; } +#endif } else { +#ifdef FUNC_MOTOR_CTL_PWM /* PWM */ if (obj->ch == 2) { if (period_ch2 != 0) { @@ -554,6 +561,7 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) { value = (float)us / (float)period_ch1; } } +#endif } pwmout_write(obj, value); } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c similarity index 98% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/rtc_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c index 8754a5d257..f3c19958e8 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/rtc_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c @@ -19,15 +19,11 @@ #if DEVICE_RTC -#define USE_RTCX1_CLK -//#define USE_EXTAL_CLK -//#define USE_RTCX3_CLK - #include "rtc_api.h" -#include "rtc_iodefine.h" +#include "iodefine.h" +#include "mbed_drv_cfg.h" #include "mbed_mktime.h" - #define RCR1_VAL_ON (0x08u) // AIE = 1 #define RCR1_VAL_OFF (0x00u) #define RCR3_VAL (0x00u) @@ -138,6 +134,7 @@ void rtc_init(void) { // Dummy read dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT; + (void)dummy_read; } @@ -188,6 +185,7 @@ void rtc_free(void) { // Dummy read dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT; + (void)dummy_read; } @@ -365,6 +363,7 @@ void rtc_write(time_t t) { dummy_read = (uint16_t)RTC.RCR2; dummy_read = (uint16_t)RTC.RCR2; + (void)dummy_read; } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c similarity index 77% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/serial_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c index 0d91ccb88d..e658c30214 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/serial_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c @@ -21,103 +21,55 @@ #include "serial_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "gpio_api.h" +#include "RZ_A1_Init.h" -#include "scif_iodefine.h" -#include "cpg_iodefine.h" +#include "iodefine.h" +#include "mbed_drv_cfg.h" #include "mbed_critical.h" /****************************************************************************** * INITIALIZATION ******************************************************************************/ -#define PCLK (66666666) // Define the peripheral clock P1 frequency. - +#if defined(TARGET_RZA1H) #define UART_NUM 8 +#else +#define UART_NUM 5 +#endif #define IRQ_NUM 4 static void uart0_tx_irq(void); -static void uart1_tx_irq(void); -static void uart2_tx_irq(void); -static void uart3_tx_irq(void); -static void uart4_tx_irq(void); -static void uart5_tx_irq(void); -static void uart6_tx_irq(void); -static void uart7_tx_irq(void); static void uart0_rx_irq(void); -static void uart1_rx_irq(void); -static void uart2_rx_irq(void); -static void uart3_rx_irq(void); -static void uart4_rx_irq(void); -static void uart5_rx_irq(void); -static void uart6_rx_irq(void); -static void uart7_rx_irq(void); static void uart0_er_irq(void); +static void uart1_tx_irq(void); +static void uart1_rx_irq(void); static void uart1_er_irq(void); +static void uart2_tx_irq(void); +static void uart2_rx_irq(void); static void uart2_er_irq(void); +static void uart3_tx_irq(void); +static void uart3_rx_irq(void); static void uart3_er_irq(void); +static void uart4_tx_irq(void); +static void uart4_rx_irq(void); static void uart4_er_irq(void); +#if defined(TARGET_RZA1H) +static void uart5_tx_irq(void); +static void uart5_rx_irq(void); static void uart5_er_irq(void); +static void uart6_tx_irq(void); +static void uart6_rx_irq(void); static void uart6_er_irq(void); +static void uart7_tx_irq(void); +static void uart7_rx_irq(void); static void uart7_er_irq(void); +#endif static void serial_put_done(serial_t *obj); static uint8_t serial_available_buffer(serial_t *obj); static void serial_irq_err_set(serial_t *obj, uint32_t enable); -static const PinMap PinMap_UART_TX[] = { - {P2_14 , UART0, 6}, - {P2_5 , UART1, 6}, - {P4_12 , UART1, 7}, - {P6_3 , UART2, 7}, - {P4_14 , UART2, 7}, - {P5_3 , UART3, 5}, - {P8_8 , UART3, 7}, - {P5_0 , UART4, 5}, - {P8_14 , UART4, 7}, - {P8_13 , UART5, 5}, - {P11_10, UART5, 3}, - {P6_6 , UART5, 5}, - {P5_6 , UART6, 5}, - {P11_1 , UART6, 4}, - {P7_4 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {P2_15 , UART0, 6}, - {P2_6 , UART1, 6}, - {P4_13 , UART1, 7}, - {P6_2 , UART2, 7}, - {P4_15 , UART2, 7}, - {P5_4 , UART3, 5}, - {P8_9 , UART3, 7}, - {P5_1 , UART4, 5}, - {P8_15 , UART4, 7}, - {P8_11 , UART5, 5}, - {P11_11, UART5, 3}, - {P6_7 , UART5, 5}, - {P5_7 , UART6, 5}, - {P11_2 , UART6, 4}, - {P7_5 , UART7, 4}, - {NC , NC , 0} -}; - -static const PinMap PinMap_UART_CTS[] = { - {P2_3 , UART1, 6}, - {P11_7 , UART5, 3}, - {P7_6 , UART7, 4}, - {NC , NC , 0} -}; -static const PinMap PinMap_UART_RTS[] = { - {P2_7 , UART1, 6}, - {P11_8 , UART5, 3}, - {P7_7 , UART7, 4}, - {NC , NC , 0} -}; - - - static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; static uart_irq_handler irq_handler; @@ -127,7 +79,6 @@ serial_t stdio_uart; struct serial_global_data_s { uint32_t serial_irq_id; gpio_t sw_rts, sw_cts; - uint8_t rx_irq_set_flow, rx_irq_set_api; serial_t *tranferring_obj, *receiving_obj; uint32_t async_tx_callback, async_rx_callback; int event, wanted_rx_events; @@ -141,9 +92,11 @@ static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn}, {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn}, {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn}, +#if defined(TARGET_RZA1H) {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn}, {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn}, - {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn} + {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn}, +#endif }; static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { @@ -152,9 +105,11 @@ static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq}, {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq}, {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq}, +#if defined(TARGET_RZA1H) {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq}, {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq}, - {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq} + {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq}, +#endif }; static __IO uint16_t *SCSCR_MATCH[] = { @@ -163,9 +118,11 @@ static __IO uint16_t *SCSCR_MATCH[] = { &SCSCR_2, &SCSCR_3, &SCSCR_4, +#if defined(TARGET_RZA1H) &SCSCR_5, &SCSCR_6, &SCSCR_7, +#endif }; static __IO uint16_t *SCFSR_MATCH[] = { @@ -174,9 +131,11 @@ static __IO uint16_t *SCFSR_MATCH[] = { &SCFSR_2, &SCFSR_3, &SCFSR_4, +#if defined(TARGET_RZA1H) &SCFSR_5, &SCFSR_6, &SCFSR_7, +#endif }; @@ -192,32 +151,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { obj->serial.uart = (struct st_scif *)SCIF[uart]; // enable power - switch (uart) { - case UART0: - CPG.STBCR4 &= ~(1 << 7); - break; - case UART1: - CPG.STBCR4 &= ~(1 << 6); - break; - case UART2: - CPG.STBCR4 &= ~(1 << 5); - break; - case UART3: - CPG.STBCR4 &= ~(1 << 4); - break; - case UART4: - CPG.STBCR4 &= ~(1 << 3); - break; - case UART5: - CPG.STBCR4 &= ~(1 << 2); - break; - case UART6: - CPG.STBCR4 &= ~(1 << 1); - break; - case UART7: - CPG.STBCR4 &= ~(1 << 0); - break; - } + CPG.STBCR4 &= ~(1 << (7 - uart)); dummy = CPG.STBCR4; /* ==== SCIF initial setting ==== */ @@ -227,7 +161,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { /* ---- FIFO control register (SCFCR) setting ---- */ /* Transmit FIFO reset & Receive FIFO data register reset */ - obj->serial.uart->SCFCR = 0x0006; + obj->serial.uart->SCFCR = 0x0006u; /* ---- Serial status register (SCFSR) setting ---- */ dummy = obj->serial.uart->SCFSR; @@ -265,32 +199,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); - switch (uart) { - case UART0: - obj->serial.index = 0; - break; - case UART1: - obj->serial.index = 1; - break; - case UART2: - obj->serial.index = 2; - break; - case UART3: - obj->serial.index = 3; - break; - case UART4: - obj->serial.index = 4; - break; - case UART5: - obj->serial.index = 5; - break; - case UART6: - obj->serial.index = 6; - break; - case UART7: - obj->serial.index = 7; - break; - } + obj->serial.index = uart; + uart_data[obj->serial.index].sw_rts.pin = NC; uart_data[obj->serial.index].sw_cts.pin = NC; @@ -313,51 +223,43 @@ void serial_free(serial_t *obj) { // serial_baud // set the baud rate, taking in to account the current SystemFrequency void serial_baud(serial_t *obj, int baudrate) { - uint16_t DL; + uint32_t pclk_base; + uint32_t bgdm = 1; + uint32_t cks = 0; + uint32_t DL; - obj->serial.uart->SCSMR &= ~0x0003; + if (RZ_A1_IsClockMode0() == false) { + pclk_base = CM1_RENESAS_RZ_A1_P1_CLK; + } else { + pclk_base = CM0_RENESAS_RZ_A1_P1_CLK; + } - if (baudrate > 32552) { - obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 - DL = PCLK / (8 * baudrate); + if (baudrate > (int)(pclk_base / 0x800)) { + obj->serial.uart->SCSMR &= ~0x0003; + obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 + DL = (pclk_base + (4 * baudrate)) / (8 * baudrate); // Rounding if (DL > 0) { DL--; } obj->serial.uart->SCBRR = (uint8_t)DL; - } else if (baudrate > 16276) { - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (16 * baudrate) - 1; - } else if (baudrate > 8138) { - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (32 * baudrate) - 1; - } else if (baudrate > 4169) { - obj->serial.uart->SCSMR |= 0x0001; - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (64 * baudrate) - 1; - } else if (baudrate > 2034) { - obj->serial.uart->SCSMR |= 0x0001; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (128 * baudrate) - 1; - } else if (baudrate > 1017) { - obj->serial.uart->SCSMR |= 0x0002; - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (256 * baudrate) - 1; - } else if (baudrate > 508) { - obj->serial.uart->SCSMR |= 0x0002; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (512 * baudrate) - 1; - } else if (baudrate > 254) { + } else if (baudrate < (int)(pclk_base / 0x80000)) { obj->serial.uart->SCSMR |= 0x0003; - obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 - obj->serial.uart->SCBRR = PCLK / (1024 * baudrate) - 1; - } else if (baudrate > 127) { - obj->serial.uart->SCSMR |= 0x0003; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = PCLK / (2048 * baudrate) - 1; + obj->serial.uart->SCEMR = 0x0000; + obj->serial.uart->SCBRR = 0xFFu; } else { - obj->serial.uart->SCSMR |= 0x0003; - obj->serial.uart->SCEMR = 0x0000; - obj->serial.uart->SCBRR = 0xFFu; + DL = (pclk_base + (8 * baudrate)) / (16 * baudrate); // Rounding + while (DL > 256) { + DL >>= 1; + if (bgdm == 1) { + bgdm = 0; + } else { + bgdm = 1; + cks++; + } + } + obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0003) | (uint8_t)cks; + obj->serial.uart->SCEMR = (uint8_t)(bgdm << 7); + obj->serial.uart->SCBRR = (uint8_t)(DL - 1); } } @@ -399,11 +301,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b break; } - obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078) - | (data_bits << 6) - | (parity_enable << 5) - | (parity_select << 4) - | (stop_bits << 3); + obj->serial.uart->SCSMR = data_bits << 6 + | parity_enable << 5 + | parity_select << 4 + | stop_bits << 3; } /****************************************************************************** @@ -538,89 +439,87 @@ static void uart_err_irq(IRQn_Type irq_num, uint32_t index) { } } -/* TX handler */ -static void uart0_tx_irq(void) { +static void uart0_tx_irq(void) { uart_tx_irq(SCIFTXI0_IRQn, 0); } -static void uart1_tx_irq(void) { - uart_tx_irq(SCIFTXI1_IRQn, 1); -} -static void uart2_tx_irq(void) { - uart_tx_irq(SCIFTXI2_IRQn, 2); -} -static void uart3_tx_irq(void) { - uart_tx_irq(SCIFTXI3_IRQn, 3); -} -static void uart4_tx_irq(void) { - uart_tx_irq(SCIFTXI4_IRQn, 4); -} -static void uart5_tx_irq(void) { - uart_tx_irq(SCIFTXI5_IRQn, 5); -} -static void uart6_tx_irq(void) { - uart_tx_irq(SCIFTXI6_IRQn, 6); -} -static void uart7_tx_irq(void) { - uart_tx_irq(SCIFTXI7_IRQn, 7); -} -/* RX handler */ -static void uart0_rx_irq(void) { +static void uart0_rx_irq(void) { uart_rx_irq(SCIFRXI0_IRQn, 0); } -static void uart1_rx_irq(void) { - uart_rx_irq(SCIFRXI1_IRQn, 1); -} -static void uart2_rx_irq(void) { - uart_rx_irq(SCIFRXI2_IRQn, 2); -} -static void uart3_rx_irq(void) { - uart_rx_irq(SCIFRXI3_IRQn, 3); -} -static void uart4_rx_irq(void) { - uart_rx_irq(SCIFRXI4_IRQn, 4); -} -static void uart5_rx_irq(void) { - uart_rx_irq(SCIFRXI5_IRQn, 5); -} -static void uart6_rx_irq(void) { - uart_rx_irq(SCIFRXI6_IRQn, 6); -} -static void uart7_rx_irq(void) { - uart_rx_irq(SCIFRXI7_IRQn, 7); -} -/* Error handler */ -static void uart0_er_irq(void) -{ +static void uart0_er_irq(void) { uart_err_irq(SCIFERI0_IRQn, 0); } -static void uart1_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 1); + +static void uart1_tx_irq(void) { + uart_tx_irq(SCIFTXI1_IRQn, 1); } -static void uart2_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 2); +static void uart1_rx_irq(void) { + uart_rx_irq(SCIFRXI1_IRQn, 1); } -static void uart3_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 3); +static void uart1_er_irq(void) { + uart_err_irq(SCIFERI1_IRQn, 1); } -static void uart4_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 4); + +static void uart2_tx_irq(void) { + uart_tx_irq(SCIFTXI2_IRQn, 2); } -static void uart5_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 5); +static void uart2_rx_irq(void) { + uart_rx_irq(SCIFRXI2_IRQn, 2); } -static void uart6_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 6); +static void uart2_er_irq(void) { + uart_err_irq(SCIFERI2_IRQn, 2); } -static void uart7_er_irq(void) -{ - uart_err_irq(SCIFERI0_IRQn, 7); + +static void uart3_tx_irq(void) { + uart_tx_irq(SCIFTXI3_IRQn, 3); } +static void uart3_rx_irq(void) { + uart_rx_irq(SCIFRXI3_IRQn, 3); +} +static void uart3_er_irq(void) { + uart_err_irq(SCIFERI3_IRQn, 3); +} + +static void uart4_tx_irq(void) { + uart_tx_irq(SCIFTXI4_IRQn, 4); +} +static void uart4_rx_irq(void) { + uart_rx_irq(SCIFRXI4_IRQn, 4); +} +static void uart4_er_irq(void) { + uart_err_irq(SCIFERI4_IRQn, 4); +} + +#if defined(TARGET_RZA1H) +static void uart5_tx_irq(void) { + uart_tx_irq(SCIFTXI5_IRQn, 5); +} +static void uart5_rx_irq(void) { + uart_rx_irq(SCIFRXI5_IRQn, 5); +} +static void uart5_er_irq(void) { + uart_err_irq(SCIFERI5_IRQn, 5); +} + +static void uart6_tx_irq(void) { + uart_tx_irq(SCIFTXI6_IRQn, 6); +} +static void uart6_rx_irq(void) { + uart_rx_irq(SCIFRXI6_IRQn, 6); +} +static void uart6_er_irq(void) { + uart_err_irq(SCIFERI6_IRQn, 6); +} + +static void uart7_tx_irq(void) { + uart_tx_irq(SCIFTXI7_IRQn, 7); +} +static void uart7_rx_irq(void) { + uart_rx_irq(SCIFRXI7_IRQn, 7); +} +static void uart7_er_irq(void) { + uart_err_irq(SCIFERI7_IRQn, 7); +} +#endif void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -638,7 +537,13 @@ static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enab } } -static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { +static void serial_irq_err_set(serial_t *obj, uint32_t enable) +{ + serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable); + serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable); +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type IRQn; IRQHandler handler; @@ -650,24 +555,6 @@ static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enabl } } -static void serial_irq_err_set(serial_t *obj, uint32_t enable) -{ - serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable); - serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable); -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - if (RxIrq == irq) { - uart_data[obj->serial.index].rx_irq_set_api = enable; - } - serial_irq_set_internal(obj, irq, enable); -} - -static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { - uart_data[obj->serial.index].rx_irq_set_flow = enable; - serial_irq_set_internal(obj, RxIrq, enable); -} - /****************************************************************************** * READ/WRITE ******************************************************************************/ @@ -729,8 +616,8 @@ int serial_writable(serial_t *obj) { void serial_clear(serial_t *obj) { core_util_critical_section_enter(); - obj->serial.uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 - obj->serial.uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 + obj->serial.uart->SCFCR |= 0x0006u; // TFRST = 1, RFRST = 1 + obj->serial.uart->SCFCR &= ~0x0006u; // TFRST = 0, RFRST = 0 obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 core_util_critical_section_exit(); @@ -755,23 +642,23 @@ void serial_break_clear(serial_t *obj) { core_util_critical_section_exit(); } +#if DEVICE_SERIAL_FC void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { // determine the UART to use - serial_flow_irq_set(obj, 0); - if (type == FlowControlRTSCTS) { core_util_critical_section_enter(); - obj->serial.uart->SCFCR = 0x0008u; // CTS/RTS enable + obj->serial.uart->SCFCR |= 0x0008u; // CTS/RTS enable core_util_critical_section_exit(); pinmap_pinout(rxflow, PinMap_UART_RTS); pinmap_pinout(txflow, PinMap_UART_CTS); } else { core_util_critical_section_enter(); - obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable + obj->serial.uart->SCFCR &= ~0x0008u; // CTS/RTS diable core_util_critical_section_exit(); } } +#endif static uint8_t serial_available_buffer(serial_t *obj) { diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/spi_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c similarity index 89% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/spi_api.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c index 6e94a0db4f..fd3db3716f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/spi_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c @@ -18,49 +18,10 @@ #include "spi_api.h" #include "cmsis.h" -#include "pinmap.h" +#include "PeripheralPins.h" #include "mbed_error.h" #include "RZ_A1_Init.h" - -static const PinMap PinMap_SPI_SCLK[] = { - {P10_12, SPI_0, 4}, - {P4_4 , SPI_1, 2}, - {P6_4 , SPI_1, 7}, - {P11_12, SPI_1, 2}, - {P8_3 , SPI_2, 3}, - {P5_0 , SPI_3, 8}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_SSEL[] = { - {P10_13, SPI_0, 4}, - {P4_5 , SPI_1, 2}, - {P6_5 , SPI_1, 7}, - {P11_13, SPI_1, 2}, - {P8_4 , SPI_2, 3}, - {P5_1 , SPI_3, 8}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MOSI[] = { - {P10_14, SPI_0, 4}, - {P4_6 , SPI_1, 2}, - {P6_6 , SPI_1, 7}, - {P11_14, SPI_1, 2}, - {P8_5 , SPI_2, 3}, - {P5_2 , SPI_3, 8}, - {NC , NC , 0} -}; - -static const PinMap PinMap_SPI_MISO[] = { - {P10_15, SPI_0, 4}, - {P4_7 , SPI_1, 2}, - {P6_7 , SPI_1, 7}, - {P11_15, SPI_1, 2}, - {P8_6 , SPI_2, 3}, - {P5_3 , SPI_3, 8}, - {NC , NC , 0} -}; +#include "mbed_drv_cfg.h" static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; @@ -87,13 +48,9 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->spi.index = spi; // enable power and clocking - switch (spi) { - case SPI_0: CPGSTBCR10 &= ~(0x80); break; - case SPI_1: CPGSTBCR10 &= ~(0x40); break; - case SPI_2: CPGSTBCR10 &= ~(0x20); break; - case SPI_3: CPGSTBCR10 &= ~(0x10); break; - } + CPGSTBCR10 &= ~(0x80 >> spi); dummy = CPGSTBCR10; + (void)dummy; obj->spi.spi->SPCR = 0x00; // CTRL to 0 obj->spi.spi->SPSCR = 0x00; // no sequential operation @@ -192,7 +149,7 @@ void spi_frequency(spi_t *obj, int hz) { hz_min = pclk_base / 2 / 256 / 8; hz_max = pclk_base / 2; - if ((hz < hz_min) || (hz > hz_max)) { + if (((uint32_t)hz < hz_min) || ((uint32_t)hz > hz_max)) { error("Couldn't setup requested SPI frequency"); return; } @@ -293,37 +250,38 @@ int spi_busy(spi_t *obj) { #if DEVICE_SPI_ASYNCH -#define IRQ_NUM 2 +#define SPI_NUM 5 +#define IRQ_NUM 2 static void spi_irqs_set(spi_t *obj, uint32_t enable); static void spi_async_write(spi_t *obj); static void spi_async_read(spi_t *obj); static void spi0_rx_irq(void); -static void spi1_rx_irq(void); -static void spi2_rx_irq(void); -static void spi3_rx_irq(void); -static void spi4_rx_irq(void); static void spi0_er_irq(void); +static void spi1_rx_irq(void); static void spi1_er_irq(void); +static void spi2_rx_irq(void); static void spi2_er_irq(void); +static void spi3_rx_irq(void); static void spi3_er_irq(void); +static void spi4_rx_irq(void); static void spi4_er_irq(void); -static const IRQn_Type irq_set_tbl[RSPI_COUNT][IRQ_NUM] = { +static const IRQn_Type irq_set_tbl[SPI_NUM][IRQ_NUM] = { {RSPISPRI0_IRQn, RSPISPEI0_IRQn}, {RSPISPRI1_IRQn, RSPISPEI1_IRQn}, {RSPISPRI2_IRQn, RSPISPEI2_IRQn}, {RSPISPRI3_IRQn, RSPISPEI3_IRQn}, - {RSPISPRI4_IRQn, RSPISPEI4_IRQn} + {RSPISPRI4_IRQn, RSPISPEI4_IRQn}, }; -static const IRQHandler hander_set_tbl[RSPI_COUNT][IRQ_NUM] = { +static const IRQHandler hander_set_tbl[SPI_NUM][IRQ_NUM] = { {spi0_rx_irq, spi0_er_irq}, {spi1_rx_irq, spi1_er_irq}, {spi2_rx_irq, spi2_er_irq}, {spi3_rx_irq, spi3_er_irq}, - {spi4_rx_irq, spi4_er_irq} + {spi4_rx_irq, spi4_er_irq}, }; struct spi_global_data_s { @@ -331,7 +289,7 @@ struct spi_global_data_s { uint32_t async_callback, event, wanted_events; }; -static struct spi_global_data_s spi_data[RSPI_COUNT]; +static struct spi_global_data_s spi_data[SPI_NUM]; static void spi_rx_irq(IRQn_Type irq_num, uint32_t index) { @@ -388,53 +346,34 @@ static void spi_err_irq(IRQn_Type irq_num, uint32_t index) } } -static void spi0_rx_irq(void) -{ +static void spi0_rx_irq(void) { spi_rx_irq(RSPISPRI0_IRQn, 0); } - -static void spi1_rx_irq(void) -{ - spi_rx_irq(RSPISPRI1_IRQn, 1); -} - -static void spi2_rx_irq(void) -{ - spi_rx_irq(RSPISPRI2_IRQn, 2); -} - -static void spi3_rx_irq(void) -{ - spi_rx_irq(RSPISPRI3_IRQn, 3); -} - -static void spi4_rx_irq(void) -{ - spi_rx_irq(RSPISPRI4_IRQn, 4); -} - -static void spi0_er_irq(void) -{ +static void spi0_er_irq(void) { spi_err_irq(RSPISPEI0_IRQn, 0); } - -static void spi1_er_irq(void) -{ +static void spi1_rx_irq(void) { + spi_rx_irq(RSPISPRI1_IRQn, 1); +} +static void spi1_er_irq(void) { spi_err_irq(RSPISPEI1_IRQn, 1); } - -static void spi2_er_irq(void) -{ +static void spi2_rx_irq(void) { + spi_rx_irq(RSPISPRI2_IRQn, 2); +} +static void spi2_er_irq(void) { spi_err_irq(RSPISPEI2_IRQn, 2); } - -static void spi3_er_irq(void) -{ +static void spi3_rx_irq(void) { + spi_rx_irq(RSPISPRI3_IRQn, 3); +} +static void spi3_er_irq(void) { spi_err_irq(RSPISPEI3_IRQn, 3); } - -static void spi4_er_irq(void) -{ +static void spi4_rx_irq(void) { + spi_rx_irq(RSPISPRI4_IRQn, 4); +} +static void spi4_er_irq(void) { spi_err_irq(RSPISPEI4_IRQn, 4); } @@ -562,7 +501,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, obj->rx_buff.length = rx_length * bit_width / 8; obj->rx_buff.pos = 0; obj->rx_buff.width = bit_width; - for (i = 0; i < obj->rx_buff.length; i++) { + for (i = 0; i < (int)obj->rx_buff.length; i++) { ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD; } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/us_ticker.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/us_ticker.c similarity index 98% rename from targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/us_ticker.c rename to targets/TARGET_RENESAS/TARGET_RZ_A1XX/us_ticker.c index 83e58dbe43..e6951fb7c9 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/us_ticker.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/us_ticker.c @@ -16,10 +16,10 @@ #include #include "us_ticker_api.h" #include "PeripheralNames.h" -#include "ostm_iodefine.h" +#include "iodefine.h" +#include "cmsis.h" #include "RZ_A1_Init.h" -#include "MBRZA1H.h" #include "vfp_neon_push_pop.h" #include "mbed_critical.h" From 5a08da08070a13d0a7f49c873d65aa2b9ea3a9af Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Tue, 9 Jan 2018 18:25:12 +0900 Subject: [PATCH 128/133] Change the values of RZ_A1 related "extra_labels" in targets.json As a result of revision of folder structure, I changed the values of "extra_labels" of RZ_A1-related in targets.json. --- targets/targets.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 8dfeb0f2f7..5196f652b7 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2551,7 +2551,7 @@ "supported_form_factors": ["ARDUINO"], "core": "Cortex-A9", "program_cycle_s": 2, - "extra_labels": ["RENESAS", "MBRZA1H"], + "extra_labels": ["RENESAS", "RZ_A1XX", "RZA1H", "MBRZA1H"], "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "inherits": ["Target"], "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], @@ -2561,7 +2561,7 @@ "VK_RZ_A1H": { "inherits": ["Target"], "core": "Cortex-A9", - "extra_labels": ["RENESAS", "VKRZA1H"], + "extra_labels": ["RENESAS", "RZ_A1XX", "RZA1H", "VKRZA1H"], "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "default_toolchain": "ARM", "program_cycle_s": 2, From 78bd1e3e4b4cc1f82790f4621fcd067453f3082b Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Tue, 9 Jan 2018 18:28:39 +0900 Subject: [PATCH 129/133] Performance improvement of LWIP communication in RZ_A1 related For LWIP communication speedup in RZ_A1 related, I changed the below macro value and added the definition processing in RZ/A1 related header file(lwipopts_conf.h). For this reason, those macros are overrode by RZ/A1 related values, not default values. --- .../lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h index 1ad186c7a1..0e272a25fc 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/lwipopts_conf.h @@ -23,4 +23,11 @@ #define MEM_SIZE (1600 * 16) +#define MEMP_NUM_TCP_SEG 32 +#define TCP_MSS 1460 +#define PBUF_POOL_SIZE 16 +#define TCP_SND_BUF (8 * TCP_MSS) +#define TCP_WND (TCP_MSS * 8) +#define PBUF_POOL_BUFSIZE 1600 + #endif From 70f017cdaabc92ccca68b330b48b7ba02f74b2e2 Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Tue, 9 Jan 2018 18:30:07 +0900 Subject: [PATCH 130/133] Modify the TYPO of debug info when using LWIP in RZ/A1 related I modified the debug message when using LWIP in RZ/A1 related mbed boards. In eth_arch_enetif_init(), sys_thread_new() was called and task name is appeared as debug information, but task name for debug was a mistake. --- .../lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c index 65515507a0..0953de1da4 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c @@ -195,8 +195,8 @@ err_t eth_arch_enetif_init(struct netif *netif) sys_sem_new(&recv_ready_sem, 0); /* task */ - sys_thread_new("rza1_emac_rx_thread", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI); - sys_thread_new("rza1_emac_phy_thread", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI); + sys_thread_new("rza1_recv_task", rza1_recv_task, netif, DEFAULT_THREAD_STACKSIZE, RECV_TASK_PRI); + sys_thread_new("rza1_phy_task", rza1_phy_task, netif, DEFAULT_THREAD_STACKSIZE, PHY_TASK_PRI); return ERR_OK; } From d1c21109fff6be2c5d6fd9b96dda47d298b187c4 Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Thu, 11 Jan 2018 17:39:24 +0900 Subject: [PATCH 131/133] Add the function declarations of WEAK attribute to use LWIP on GR-LYCHEE I added the function declarations of Ethernet functions that have a WEAK attribute. Although several Ethernet functions was called in rza1_emac.c, GR-LYCHEE don't have Ethernert feature. But there may be case that GR-LYCHEE uses LWIP feature. In this case, since GR-LYCHEE will occur the build error, I addressed the error by defining the functions with a WEAK attribute. For reason of WEAK attribute, there is no influence in GR-PEACH and VK_RZ_A1H that have Ethernet feature. --- .../lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c index 0953de1da4..1d033e12da 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_RZ_A1XX/rza1_emac.c @@ -5,11 +5,73 @@ #include "mbed_interface.h" #include "ethernet_api.h" #include "ethernetext_api.h" +#include "platform/mbed_toolchain.h" #define RECV_TASK_PRI (osPriorityNormal) #define PHY_TASK_PRI (osPriorityNormal) #define PHY_TASK_WAIT (200) +WEAK int ethernetext_init(ethernet_cfg_t *p_ethcfg) +{ + return -1; +} + +WEAK void ethernetext_start_stop(int32_t mode) +{ +} + +WEAK int ethernetext_chk_link_mode(void) +{ + return NEGO_FAIL; +} + +WEAK void ethernetext_set_link_mode(int32_t link) +{ +} + +WEAK int ethernet_init(void) +{ + return -1; +} + +WEAK void ethernet_free(void) +{ +} + +WEAK int ethernet_write(const char *data, int size) +{ + return 0; +} + +WEAK int ethernet_send(void) +{ + return 0; +} + +WEAK int ethernet_receive(void) +{ + return 0; +} + +WEAK int ethernet_read(char *data, int size) +{ + return 0; +} + +WEAK void ethernet_address(char *mac) +{ +} + +WEAK int ethernet_link(void) +{ + return 0; +} + +WEAK void ethernet_set_link(int speed, int duplex) +{ +} + + /* memory */ static sys_sem_t recv_ready_sem; /* receive ready semaphore */ From da01e544c92c1e93d610e595e209eaffca9cfda8 Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Fri, 12 Jan 2018 14:18:54 +0900 Subject: [PATCH 132/133] Modify the lack of copyright to header files I modified the lack of copyright in the below header files that I added for commonizing the RZ_A1 related files. - targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h - targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h --- .../TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h | 16 ++++++++++++++++ .../TARGET_VK_RZ_A1H/mbed_drv_cfg.h | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h index 1ee094dce6..827ad7fce3 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h @@ -1,3 +1,19 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #ifndef MBED_DRV_CFG_H #define MBED_DRV_CFG_H diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h index 578173c473..9b3c35d31f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h @@ -1,3 +1,19 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #ifndef MBED_DRV_CFG_H #define MBED_DRV_CFG_H From 0c344ffd58425bb26afc7f87a427d8c37a7ac011 Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Fri, 12 Jan 2018 15:01:52 +0900 Subject: [PATCH 133/133] Add "RZ_A1XX" label for commonizing in targets.json I added the "RZ_A1XX" label for commonizing the setting in targets.json, and inherited in both RZ_A1H and VK_RZ_A1H. --- targets/targets.json | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 5196f652b7..599d3d467f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2547,27 +2547,24 @@ "features": ["BLE"], "release_versions": ["2", "5"] }, - "RZ_A1H": { - "supported_form_factors": ["ARDUINO"], - "core": "Cortex-A9", - "program_cycle_s": 2, - "extra_labels": ["RENESAS", "RZ_A1XX", "RZA1H", "MBRZA1H"], - "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "RZ_A1XX": { "inherits": ["Target"], + "core": "Cortex-A9", + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "extra_labels": ["RENESAS", "RZ_A1XX"], "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "features": ["LWIP"], + "program_cycle_s": 2 + }, + "RZ_A1H": { + "inherits": ["RZ_A1XX"], + "supported_form_factors": ["ARDUINO"], + "extra_labels_add": ["RZA1H", "MBRZA1H"], "release_versions": ["2", "5"] }, "VK_RZ_A1H": { - "inherits": ["Target"], - "core": "Cortex-A9", - "extra_labels": ["RENESAS", "RZ_A1XX", "RZA1H", "VKRZA1H"], - "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], - "default_toolchain": "ARM", - "program_cycle_s": 2, - "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"], - "features": ["LWIP"], - "default_lib": "std", + "inherits": ["RZ_A1XX"], + "extra_labels": ["RZA1H", "VKRZA1H"], "release_versions": [] }, "MAXWSNENV": {