mirror of https://github.com/ARMmbed/mbed-os.git
Teensy3.1 Updated clock set up.
Utilised Header file mask defines for clock set up's. Tested default Teensy3.1 set up 3 and set up 0 (IRC mode). Modes 1 and 2 require 8MHz crystal to test.pull/957/head
Paul Staron
parent
5a803e8ad4
commit
ca5fe8afd7
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@ -47,6 +47,7 @@
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0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
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Reference clock source for MCG module is the slow internal clock source 32.768kHz
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Core clock = 41.94MHz, BusClock = 41.94MHz
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This works on Teensy3.1
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1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
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Reference clock source for MCG module is an external crystal 8MHz
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Core clock = 48MHz, BusClock = 48MHz
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@ -56,7 +57,7 @@
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3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
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Reference clock source for MCG module is an external crystal 16MHz
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Core clock = 72MHz, BusClock = 48MHz
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This is the Teensy3.1 72Mhz set up
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This is the default Teensy3.1 72Mhz set up
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*/
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/*----------------------------------------------------------------------------
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@ -98,7 +99,6 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if (DISABLE_WDOG)
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/* Disable the WDOG module */
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@ -106,145 +106,120 @@ void SystemInit (void) {
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WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
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/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
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WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
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/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
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/* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
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WDOG->STCTRLH = (uint16_t)0x01D2u;
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#endif /* (DISABLE_WDOG) */
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#if (CLOCK_SETUP == 0)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
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/* Switch to FEI Mode */
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/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x06u;
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/* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
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MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
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/* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x00u;
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/* MCG_C4: DMX32=0,DRST_DRS=1 */
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MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
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/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
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MCG->C5 = (uint8_t)0x00u;
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
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}
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while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
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}
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while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */
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while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
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#elif (CLOCK_SETUP == 1)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
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/* Switch to FBE Mode */
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/* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC0->CR = (uint8_t)0x00u;
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/* MCG->C7: OSCSEL=0 */
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MCG->C7 = (uint8_t)0x00u;
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/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x24u;
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/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(2);
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/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x9Au;
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MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = (uint8_t)0x03u;
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/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = MCG_C5_PRDIV0(3);
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
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}
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#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
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while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
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}
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#endif
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while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
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}
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
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while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
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/* Switch to PBE Mode */
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/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = (uint8_t)0x03u;
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = MCG_C5_PRDIV0(3);
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/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x40u;
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while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
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}
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
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}
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MCG->C6 = MCG_C6_PLLS_MASK;
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while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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/* Switch to PEE Mode */
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/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x1Au;
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while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
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}
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
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}
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MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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#elif (CLOCK_SETUP == 2)
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
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/* Switch to FBE Mode */
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/* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC0->CR = (uint8_t)0x00u;
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/* MCG->C7: OSCSEL=0 */
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MCG->C7 = (uint8_t)0x00u;
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/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x24u;
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/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
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/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x9Au;
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MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
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/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
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MCG->C5 = (uint8_t)0x00u;
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
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}
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#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
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while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
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}
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#endif
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while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
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}
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
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while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
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/* Switch to BLPE Mode */
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/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x24u;
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/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
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#elif (CLOCK_SETUP == 3)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
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/* SIM->CLKDIV2: USBDIV=5,USBFRAC=0 */
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SIM->CLKDIV2 = (uint32_t)0x05u; /* Divide 72MHz system clock for USB 48MHz */
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 72MHz system, 36MHz flash*/
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
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/* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
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SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
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/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
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OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
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/* Switch to FBE Mode */
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/* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 */
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OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; /* 10pF loading capacitors for 16MHz system oscillator*/
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/* MCG->C7: OSCSEL=0 */
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MCG->C7 = (uint8_t)0x00u;
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/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x24u;
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/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
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//MCG->C2 = (uint8_t)0x24u;
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/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x9Au;
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = (uint8_t)0x07u;
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MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
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/* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
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MCG->C5 = MCG_C5_PRDIV0(7);
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
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}
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#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
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while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
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}
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#endif
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while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
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}
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while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
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while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
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/* Switch to PBE Mode */
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/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
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MCG->C5 = (uint8_t)0x05u;
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/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
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MCG->C6 = (uint8_t)0x43u;
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while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
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}
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
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}
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/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
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MCG->C5 = MCG_C5_PRDIV0(5);
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/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
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MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
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while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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/* Switch to PEE Mode */
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/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x22u;
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while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
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}
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
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}
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#endif /* (CLOCK_SETUP == 3) */
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/* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
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while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
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while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
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#endif /* (CLOCK_SETUP) */
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}
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/* ----------------------------------------------------------------------------
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