ARMmbed
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mbed-os
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Merge branch 'master' into K20D50

pull/135/head
0xc0170 2013-12-23 20:01:05 +01:00
parent 366221524a 728084c52f
commit c9a029ce6f
40 changed files with 853 additions and 614 deletions
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96
MANIFEST
View File

@ -1,96 +0,0 @@
# file GENERATED by distutils, do NOT edit
LICENSE
setup.py
workspace_tools/__init__.py
workspace_tools/__init__.pyc
workspace_tools/autotest.py
workspace_tools/build.py
workspace_tools/build_api.py
workspace_tools/build_release.py
workspace_tools/client.py
workspace_tools/export_test.py
workspace_tools/hooks.py
workspace_tools/libraries.py
workspace_tools/make.py
workspace_tools/options.py
workspace_tools/patch.py
workspace_tools/paths.py
workspace_tools/project.py
workspace_tools/server.py
workspace_tools/settings.py
workspace_tools/size.py
workspace_tools/syms.py
workspace_tools/synch.py
workspace_tools/targets.py
workspace_tools/tests.py
workspace_tools/utils.py
workspace_tools/data/__init__.py
workspace_tools/data/example_test_spec.json
workspace_tools/data/support.py
workspace_tools/data/rpc/RPCClasses.h
workspace_tools/data/rpc/class.cpp
workspace_tools/dev/__init__.py
workspace_tools/dev/dsp_fir.py
workspace_tools/dev/rpc_classes.py
workspace_tools/export/__init__.py
workspace_tools/export/codered.py
workspace_tools/export/codered_lpc1768_cproject.tmpl
workspace_tools/export/codered_lpc1768_project.tmpl
workspace_tools/export/codered_lpc4088_cproject.tmpl
workspace_tools/export/codered_lpc4088_project.tmpl
workspace_tools/export/codesourcery.py
workspace_tools/export/codesourcery_lpc1768.tmpl
workspace_tools/export/ds5_5.py
workspace_tools/export/ds5_5_lpc11u24.cproject.tmpl
workspace_tools/export/ds5_5_lpc11u24.launch.tmpl
workspace_tools/export/ds5_5_lpc11u24.project.tmpl
workspace_tools/export/ds5_5_lpc1768.cproject.tmpl
workspace_tools/export/ds5_5_lpc1768.launch.tmpl
workspace_tools/export/ds5_5_lpc1768.project.tmpl
workspace_tools/export/exporters.py
workspace_tools/export/gcc_arm_lpc1768.tmpl
workspace_tools/export/gccarm.py
workspace_tools/export/iar.ewp.tmpl
workspace_tools/export/iar.eww.tmpl
workspace_tools/export/iar.py
workspace_tools/export/uvision4.py
workspace_tools/export/uvision4_kl25z.uvopt.tmpl
workspace_tools/export/uvision4_kl25z.uvproj.tmpl
workspace_tools/export/uvision4_lpc1114.uvopt.tmpl
workspace_tools/export/uvision4_lpc1114.uvproj.tmpl
workspace_tools/export/uvision4_lpc11c24.uvopt.tmpl
workspace_tools/export/uvision4_lpc11c24.uvproj.tmpl
workspace_tools/export/uvision4_lpc11u24.uvopt.tmpl
workspace_tools/export/uvision4_lpc11u24.uvproj.tmpl
workspace_tools/export/uvision4_lpc1347.uvopt.tmpl
workspace_tools/export/uvision4_lpc1347.uvproj.tmpl
workspace_tools/export/uvision4_lpc1768.uvopt.tmpl
workspace_tools/export/uvision4_lpc1768.uvproj.tmpl
workspace_tools/export/uvision4_lpc4088.uvopt.tmpl
workspace_tools/export/uvision4_lpc4088.uvproj.tmpl
workspace_tools/export/uvision4_lpc812.uvopt.tmpl
workspace_tools/export/uvision4_lpc812.uvproj.tmpl
workspace_tools/host_tests/__init__.py
workspace_tools/host_tests/echo.py
workspace_tools/host_tests/host_test.py
workspace_tools/host_tests/mbedrpc.py
workspace_tools/host_tests/net_test.py
workspace_tools/host_tests/rpc.py
workspace_tools/host_tests/tcpecho_client.py
workspace_tools/host_tests/tcpecho_server.py
workspace_tools/host_tests/tcpecho_server_loop.py
workspace_tools/host_tests/udpecho_client.py
workspace_tools/host_tests/udpecho_server.py
workspace_tools/host_tests/example/BroadcastReceive.py
workspace_tools/host_tests/example/BroadcastSend.py
workspace_tools/host_tests/example/MulticastReceive.py
workspace_tools/host_tests/example/MulticastSend.py
workspace_tools/host_tests/example/TCPEchoClient.py
workspace_tools/host_tests/example/TCPEchoServer.py
workspace_tools/host_tests/example/UDPEchoClient.py
workspace_tools/host_tests/example/UDPEchoServer.py
workspace_tools/host_tests/example/__init__.py
workspace_tools/toolchains/__init__.py
workspace_tools/toolchains/arm.py
workspace_tools/toolchains/gcc.py
workspace_tools/toolchains/iar.py

3
MANIFEST.in
View File

@ -1,2 +1,3 @@
graft workspace_tools
include __init__.py LICENSE
recursive-exclude workspace_tools *.pyc
include LICENSE

10
libraries/mbed/api/RawSerial.h
View File

@ -71,6 +71,16 @@ public:
* @returns The char read from the serial port
*/
int getc();
/** Write a string to the serial port
*
* @param str The string to write
*
* @returns 0 if the write succeeds, EOF for error
*/
int puts(const char *str);
int printf(const char *format, ...);
};
} // namespace mbed

17
libraries/mbed/api/SerialBase.h
View File

@ -51,6 +51,13 @@ public:
TxIrq
};
enum Flow {
Disabled = 0,
RTS,
CTS,
RTSCTS
};
/** Set the transmission format used by the serial port
*
* @param bits The number of bits in a word (5-8; default = 8)
@ -99,6 +106,16 @@ public:
/** Generate a break condition on the serial line
*/
void send_break();
#if DEVICE_SERIAL_FC
/** Set the flow control type on the serial port
*
* @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
* @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
* @param flow2 the second flow control pin (CTS for RTSCTS)
*/
void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
#endif
static void _irq_handler(uint32_t id, SerialIrq irq_type);

31
libraries/mbed/common/RawSerial.cpp
View File

@ -15,9 +15,12 @@
*/
#include "RawSerial.h"
#include "wait_api.h"
#include <cstdarg>
#if DEVICE_SERIAL
#define STRING_STACK_LIMIT 120
namespace mbed {
RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
@ -31,6 +34,34 @@ int RawSerial::putc(int c) {
return _base_putc(c);
}
int RawSerial::puts(const char *str) {
while (*str)
putc(*str ++);
return 0;
}
// Experimental support for printf in RawSerial. No Stream inheritance
// means we can't call printf() directly, so we use sprintf() instead.
// We only call malloc() for the sprintf() buffer if the buffer
// length is above a certain threshold, otherwise we use just the stack.
int RawSerial::printf(const char *format, ...) {
std::va_list arg;
va_start(arg, format);
int len = vsnprintf(NULL, 0, format, arg);
if (len < STRING_STACK_LIMIT) {
char temp[STRING_STACK_LIMIT];
vsprintf(temp, format, arg);
puts(temp);
} else {
char *temp = new char[len + 1];
vsprintf(temp, format, arg);
puts(temp);
delete[] temp;
}
va_end(arg);
return len;
}
} // namespace mbed
#endif

23
libraries/mbed/common/SerialBase.cpp
View File

@ -81,6 +81,29 @@ void SerialBase::send_break() {
serial_break_clear(&_serial);
}
#ifdef DEVICE_SERIAL_FC
void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
FlowControl flow_type = (FlowControl)type;
switch(type) {
case RTS:
serial_set_flow_control(&_serial, flow_type, flow1, NC);
break;
case CTS:
serial_set_flow_control(&_serial, flow_type, NC, flow1);
break;
case RTSCTS:
case Disabled:
serial_set_flow_control(&_serial, flow_type, flow1, flow2);
break;
default:
break;
}
}
#endif
} // namespace mbed
#endif

19
libraries/mbed/common/pinmap_common.c
View File

@ -44,17 +44,22 @@ uint32_t pinmap_merge(uint32_t a, uint32_t b) {
return (uint32_t)NC;
}
uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
if (pin == (PinName)NC)
return (uint32_t)NC;
uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
while (map->pin != NC) {
if (map->pin == pin)
return map->peripheral;
map++;
}
// no mapping available
error("pinmap not found for peripheral");
return (uint32_t)NC;
}
uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
uint32_t peripheral = (uint32_t)NC;
if (pin == (PinName)NC)
return (uint32_t)NC;
peripheral = pinmap_find_peripheral(pin, map);
if ((uint32_t)NC == peripheral) // no mapping available
error("pinmap not found for peripheral");
return peripheral;
}

1
libraries/mbed/hal/pinmap.h
View File

@ -34,6 +34,7 @@ void pin_mode (PinName pin, PinMode mode);
uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
uint32_t pinmap_merge (uint32_t a, uint32_t b);
void pinmap_pinout (PinName pin, const PinMap *map);
uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
#ifdef __cplusplus
}

9
libraries/mbed/hal/serial_api.h
View File

@ -37,6 +37,13 @@ typedef enum {
TxIrq
} SerialIrq;
typedef enum {
FlowControlNone,
FlowControlRTS,
FlowControlCTS,
FlowControlRTSCTS
} FlowControl;
typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
typedef struct serial_s serial_t;
@ -60,6 +67,8 @@ void serial_break_clear(serial_t *obj);
void serial_pinout_tx(PinName tx);
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
#ifdef __cplusplus
}
#endif

73
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -189,38 +189,41 @@ Reset_Handler:
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler DMA0_IRQHandler
def_default_handler DMA1_IRQHandler
def_default_handler DMA2_IRQHandler
def_default_handler DMA3_IRQHandler
def_default_handler FTFA_IRQHandler
def_default_handler LVD_LVW_IRQHandler
def_default_handler LLW_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler SPI0_IRQHandler
def_default_handler SPI1_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler ADC0_IRQHandler
def_default_handler CMP0_IRQHandler
def_default_handler TPM0_IRQHandler
def_default_handler TPM1_IRQHandler
def_default_handler TPM2_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler RTC_Seconds_IRQHandler
def_default_handler PIT_IRQHandler
def_default_handler USB0_IRQHandler
def_default_handler DAC0_IRQHandler
def_default_handler TSI0_IRQHandler
def_default_handler MCG_IRQHandler
def_default_handler LPTimer_IRQHandler
def_default_handler PORTA_IRQHandler
def_default_handler PORTD_IRQHandler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_irq_default_handler DMA0_IRQHandler
def_irq_default_handler DMA1_IRQHandler
def_irq_default_handler DMA2_IRQHandler
def_irq_default_handler DMA3_IRQHandler
def_irq_default_handler FTFA_IRQHandler
def_irq_default_handler LVD_LVW_IRQHandler
def_irq_default_handler LLW_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler CMP0_IRQHandler
def_irq_default_handler TPM0_IRQHandler
def_irq_default_handler TPM1_IRQHandler
def_irq_default_handler TPM2_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler RTC_Seconds_IRQHandler
def_irq_default_handler PIT_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler DAC0_IRQHandler
def_irq_default_handler TSI0_IRQHandler
def_irq_default_handler MCG_IRQHandler
def_irq_default_handler LPTimer_IRQHandler
def_irq_default_handler PORTA_IRQHandler
def_irq_default_handler PORTD_IRQHandler
def_irq_default_handler DEF_IRQHandler
/* Flash protection region, placed at 0x400 */
.text

81
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -187,44 +187,45 @@ Reset_Handler:
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler Default_Handler
def_default_handler DMA0_IRQHandler
def_default_handler DMA1_IRQHandler
def_default_handler DMA2_IRQHandler
def_default_handler DMA3_IRQHandler
def_default_handler FTFA_IRQHandler
def_default_handler LVD_LVW_IRQHandler
def_default_handler LLW_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler SPI0_IRQHandler
def_default_handler SPI1_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler ADC0_IRQHandler
def_default_handler CMP0_IRQHandler
def_default_handler TPM0_IRQHandler
def_default_handler TPM1_IRQHandler
def_default_handler TPM2_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler RTC_Seconds_IRQHandler
def_default_handler PIT_IRQHandler
def_default_handler I2S_IRQHandler
def_default_handler USB0_IRQHandler
def_default_handler DAC0_IRQHandler
def_default_handler TSI0_IRQHandler
def_default_handler MCG_IRQHandler
def_default_handler LPTimer_IRQHandler
def_default_handler LCD_IRQHandler
def_default_handler PORTA_IRQHandler
def_default_handler PORTD_IRQHandler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_irq_default_handler DMA0_IRQHandler
def_irq_default_handler DMA1_IRQHandler
def_irq_default_handler DMA2_IRQHandler
def_irq_default_handler DMA3_IRQHandler
def_irq_default_handler FTFA_IRQHandler
def_irq_default_handler LVD_LVW_IRQHandler
def_irq_default_handler LLW_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler CMP0_IRQHandler
def_irq_default_handler TPM0_IRQHandler
def_irq_default_handler TPM1_IRQHandler
def_irq_default_handler TPM2_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler RTC_Seconds_IRQHandler
def_irq_default_handler PIT_IRQHandler
def_irq_default_handler I2S_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler DAC0_IRQHandler
def_irq_default_handler TSI0_IRQHandler
def_irq_default_handler MCG_IRQHandler
def_irq_default_handler LPTimer_IRQHandler
def_irq_default_handler LCD_IRQHandler
def_irq_default_handler PORTA_IRQHandler
def_irq_default_handler PORTD_IRQHandler
def_irq_default_handler DEF_IRQHandler
/* Flash protection region, placed at 0x400 */
.text

63
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -181,33 +181,36 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WAKEUP_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler I2C_IRQHandler
def_default_handler TIMER16_0_IRQHandler
def_default_handler TIMER16_1_IRQHandler
def_default_handler TIMER32_0_IRQHandler
def_default_handler TIMER32_1_IRQHandler
def_default_handler SSP0_IRQHandler
def_default_handler UART_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler WDT_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler PIOINT3_IRQHandler
def_default_handler PIOINT2_IRQHandler
def_default_handler PIOINT1_IRQHandler
def_default_handler PIOINT0_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WAKEUP_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler I2C_IRQHandler
def_irq_default_handler TIMER16_0_IRQHandler
def_irq_default_handler TIMER16_1_IRQHandler
def_irq_default_handler TIMER32_0_IRQHandler
def_irq_default_handler TIMER32_1_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler UART_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler PIOINT3_IRQHandler
def_irq_default_handler PIOINT2_IRQHandler
def_irq_default_handler PIOINT1_IRQHandler
def_irq_default_handler PIOINT0_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

63
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s
View File

@ -150,16 +150,16 @@ Reset_Handler:
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
ble .Lflash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
@ -181,33 +181,36 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WAKEUP_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler I2C_IRQHandler
def_default_handler TIMER16_0_IRQHandler
def_default_handler TIMER16_1_IRQHandler
def_default_handler TIMER32_0_IRQHandler
def_default_handler TIMER32_1_IRQHandler
def_default_handler SSP0_IRQHandler
def_default_handler UART_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler WDT_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler PIOINT3_IRQHandler
def_default_handler PIOINT2_IRQHandler
def_default_handler PIOINT1_IRQHandler
def_default_handler PIOINT0_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WAKEUP_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler I2C_IRQHandler
def_irq_default_handler TIMER16_0_IRQHandler
def_irq_default_handler TIMER16_1_IRQHandler
def_irq_default_handler TIMER32_0_IRQHandler
def_irq_default_handler TIMER32_1_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler UART_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler PIOINT3_IRQHandler
def_irq_default_handler PIOINT2_IRQHandler
def_irq_default_handler PIOINT1_IRQHandler
def_irq_default_handler PIOINT0_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

70
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/startup_LPC13xx.s
View File

@ -135,12 +135,12 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.flash_to_ram_loop:
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .flash_to_ram_loop
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
@ -149,6 +149,7 @@ Reset_Handler:
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -161,7 +162,7 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
@ -173,37 +174,40 @@ Reset_Handler:
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler PIN_INT0_Handler
def_default_handler PIN_INT1_Handler
def_default_handler PIN_INT2_Handler
def_default_handler PIN_INT3_Handler
def_default_handler PIN_INT4_Handler
def_default_handler PIN_INT5_Handler
def_default_handler PIN_INT6_Handler
def_default_handler PIN_INT7_Handler
def_default_handler GINT0_Handler
def_default_handler GINT1_Handler
def_default_handler OSTIMER_Handler
def_default_handler SSP1_Handler
def_default_handler I2C_Handler
def_default_handler CT16B0_Handler
def_default_handler CT16B1_Handler
def_default_handler CT32B0_Handler
def_default_handler CT32B1_Handler
def_default_handler SSP0_Handler
def_default_handler USART_Handler
def_default_handler USB_Handler
def_default_handler USB_FIQHandler
def_default_handler ADC_Handler
def_default_handler WDT_Handler
def_default_handler BOD_Handler
def_default_handler FMC_Handler
def_default_handler OSCFAIL_Handler
def_default_handler PVTCIRCUIT_Handler
def_default_handler USBWakeup_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_irq_default_handler PIN_INT0_Handler
def_irq_default_handler PIN_INT1_Handler
def_irq_default_handler PIN_INT2_Handler
def_irq_default_handler PIN_INT3_Handler
def_irq_default_handler PIN_INT4_Handler
def_irq_default_handler PIN_INT5_Handler
def_irq_default_handler PIN_INT6_Handler
def_irq_default_handler PIN_INT7_Handler
def_irq_default_handler GINT0_Handler
def_irq_default_handler GINT1_Handler
def_irq_default_handler OSTIMER_Handler
def_irq_default_handler SSP1_Handler
def_irq_default_handler I2C_Handler
def_irq_default_handler CT16B0_Handler
def_irq_default_handler CT16B1_Handler
def_irq_default_handler CT32B0_Handler
def_irq_default_handler CT32B1_Handler
def_irq_default_handler SSP0_Handler
def_irq_default_handler USART_Handler
def_irq_default_handler USB_Handler
def_irq_default_handler USB_FIQHandler
def_irq_default_handler ADC_Handler
def_irq_default_handler WDT_Handler
def_irq_default_handler BOD_Handler
def_irq_default_handler FMC_Handler
def_irq_default_handler OSCFAIL_Handler
def_irq_default_handler PVTCIRCUIT_Handler
def_irq_default_handler USBWakeup_Handler
def_irq_default_handler DEF_IRQHandler
.end

86
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.s
View File

@ -138,12 +138,12 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.flash_to_ram_loop:
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .flash_to_ram_loop
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
@ -152,6 +152,7 @@ Reset_Handler:
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -164,7 +165,7 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
@ -175,45 +176,48 @@ Reset_Handler:
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WDT_IRQHandler
def_default_handler TIMER0_IRQHandler
def_default_handler TIMER1_IRQHandler
def_default_handler TIMER2_IRQHandler
def_default_handler TIMER3_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler UART3_IRQHandler
def_default_handler PWM1_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler I2C2_IRQHandler
def_default_handler SPI_IRQHandler
def_default_handler SSP0_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler PLL0_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler EINT0_IRQHandler
def_default_handler EINT1_IRQHandler
def_default_handler EINT2_IRQHandler
def_default_handler EINT3_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler USB_IRQHandler
def_default_handler CAN_IRQHandler
def_default_handler DMA_IRQHandler
def_default_handler I2S_IRQHandler
def_default_handler ENET_IRQHandler
def_default_handler RIT_IRQHandler
def_default_handler MCPWM_IRQHandler
def_default_handler QEI_IRQHandler
def_default_handler PLL1_IRQHandler
def_default_handler USBActivity_IRQHandler
def_default_handler CANActivity_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler TIMER0_IRQHandler
def_irq_default_handler TIMER1_IRQHandler
def_irq_default_handler TIMER2_IRQHandler
def_irq_default_handler TIMER3_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler UART3_IRQHandler
def_irq_default_handler PWM1_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler I2C2_IRQHandler
def_irq_default_handler SPI_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler PLL0_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler EINT0_IRQHandler
def_irq_default_handler EINT1_IRQHandler
def_irq_default_handler EINT2_IRQHandler
def_irq_default_handler EINT3_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler USB_IRQHandler
def_irq_default_handler CAN_IRQHandler
def_irq_default_handler DMA_IRQHandler
def_irq_default_handler I2S_IRQHandler
def_irq_default_handler ENET_IRQHandler
def_irq_default_handler RIT_IRQHandler
def_irq_default_handler MCPWM_IRQHandler
def_irq_default_handler QEI_IRQHandler
def_irq_default_handler PLL1_IRQHandler
def_irq_default_handler USBActivity_IRQHandler
def_irq_default_handler CANActivity_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

98
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/startup_LPC408x.s
View File

@ -144,12 +144,12 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.flash_to_ram_loop:
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .flash_to_ram_loop
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
@ -158,6 +158,7 @@ Reset_Handler:
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -170,7 +171,7 @@ Reset_Handler:
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
@ -181,51 +182,54 @@ Reset_Handler:
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WDT_IRQHandler
def_default_handler TIMER0_IRQHandler
def_default_handler TIMER1_IRQHandler
def_default_handler TIMER2_IRQHandler
def_default_handler TIMER3_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler UART3_IRQHandler
def_default_handler PWM1_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler I2C2_IRQHandler
/* def_default_handler SPI_IRQHandler */
def_default_handler SSP0_IRQHandler
def_default_handler SSP1_IRQHandler
def_default_handler PLL0_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler EINT0_IRQHandler
def_default_handler EINT1_IRQHandler
def_default_handler EINT2_IRQHandler
def_default_handler EINT3_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler BOD_IRQHandler
def_default_handler USB_IRQHandler
def_default_handler CAN_IRQHandler
def_default_handler DMA_IRQHandler
def_default_handler I2S_IRQHandler
def_default_handler ENET_IRQHandler
def_default_handler MCI_IRQHandler
def_default_handler MCPWM_IRQHandler
def_default_handler QEI_IRQHandler
def_default_handler PLL1_IRQHandler
def_default_handler USBActivity_IRQHandler
def_default_handler CANActivity_IRQHandler
def_default_handler UART4_IRQHandler
def_default_handler SSP2_IRQHandler
def_default_handler LCD_IRQHandler
def_default_handler GPIO_IRQHandler
def_default_handler PWM0_IRQHandler
def_default_handler EEPROM_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler WDT_IRQHandler
def_irq_default_handler TIMER0_IRQHandler
def_irq_default_handler TIMER1_IRQHandler
def_irq_default_handler TIMER2_IRQHandler
def_irq_default_handler TIMER3_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler UART2_IRQHandler
def_irq_default_handler UART3_IRQHandler
def_irq_default_handler PWM1_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler I2C2_IRQHandler
/* def_irq_default_handler SPI_IRQHandler */
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler PLL0_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler EINT0_IRQHandler
def_irq_default_handler EINT1_IRQHandler
def_irq_default_handler EINT2_IRQHandler
def_irq_default_handler EINT3_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler BOD_IRQHandler
def_irq_default_handler USB_IRQHandler
def_irq_default_handler CAN_IRQHandler
def_irq_default_handler DMA_IRQHandler
def_irq_default_handler I2S_IRQHandler
def_irq_default_handler ENET_IRQHandler
def_irq_default_handler MCI_IRQHandler
def_irq_default_handler MCPWM_IRQHandler
def_irq_default_handler QEI_IRQHandler
def_irq_default_handler PLL1_IRQHandler
def_irq_default_handler USBActivity_IRQHandler
def_irq_default_handler CANActivity_IRQHandler
def_irq_default_handler UART4_IRQHandler
def_irq_default_handler SSP2_IRQHandler
def_irq_default_handler LCD_IRQHandler
def_irq_default_handler GPIO_IRQHandler
def_irq_default_handler PWM0_IRQHandler
def_irq_default_handler EEPROM_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

170
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.s
View File

@ -164,62 +164,25 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__data_end__
.if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
.else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
.endif
.ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
.endif /* __STARTUP_CLEAR_BSS */
.ifndef __NO_SYSTEM_INIT
bl SystemInit
.endif
.ifndef __START
.set __START,_start
.endif
bl __START
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
@ -229,64 +192,69 @@ Reset_Handler:
.size \handler_name, . - \handler_name
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler Default_Handler
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_irq_handler DAC_IRQHandler
def_irq_handler M0CORE_IRQHandler
def_irq_handler DMA_IRQHandler
def_irq_handler FLASHEEPROM_IRQHandler
def_irq_handler ETHERNET_IRQHandler
def_irq_handler SDIO_IRQHandler
def_irq_handler LCD_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler USB1_IRQHandler
def_irq_handler SCT_IRQHandler
def_irq_handler RITIMER_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler MCPWM_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler SPI_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler SSP0_IRQHandler
def_irq_handler SSP1_IRQHandler
def_irq_handler USART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler USART2_IRQHandler
def_irq_handler USART3_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler I2S1_IRQHandler
def_irq_handler SPIFI_IRQHandler
def_irq_handler SGPIO_IRQHandler
def_irq_handler PIN_INT0_IRQHandler
def_irq_handler PIN_INT1_IRQHandler
def_irq_handler PIN_INT2_IRQHandler
def_irq_handler PIN_INT3_IRQHandler
def_irq_handler PIN_INT4_IRQHandler
def_irq_handler PIN_INT5_IRQHandler
def_irq_handler PIN_INT6_IRQHandler
def_irq_handler PIN_INT7_IRQHandler
def_irq_handler GINT0_IRQHandler
def_irq_handler GINT1_IRQHandler
def_irq_handler EVENTROUTER_IRQHandler
def_irq_handler C_CAN1_IRQHandler
def_irq_handler ATIMER_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler WWDT_IRQHandler
def_irq_handler C_CAN0_IRQHandler
def_irq_handler QEI_IRQHandler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler DAC_IRQHandler
def_irq_default_handler M0CORE_IRQHandler
def_irq_default_handler DMA_IRQHandler
def_irq_default_handler FLASHEEPROM_IRQHandler
def_irq_default_handler ETHERNET_IRQHandler
def_irq_default_handler SDIO_IRQHandler
def_irq_default_handler LCD_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler USB1_IRQHandler
def_irq_default_handler SCT_IRQHandler
def_irq_default_handler RITIMER_IRQHandler
def_irq_default_handler TIMER0_IRQHandler
def_irq_default_handler TIMER1_IRQHandler
def_irq_default_handler TIMER2_IRQHandler
def_irq_default_handler TIMER3_IRQHandler
def_irq_default_handler MCPWM_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI_IRQHandler
def_irq_default_handler ADC1_IRQHandler
def_irq_default_handler SSP0_IRQHandler
def_irq_default_handler SSP1_IRQHandler
def_irq_default_handler USART0_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler USART2_IRQHandler
def_irq_default_handler USART3_IRQHandler
def_irq_default_handler I2S0_IRQHandler
def_irq_default_handler I2S1_IRQHandler
def_irq_default_handler SPIFI_IRQHandler
def_irq_default_handler SGPIO_IRQHandler
def_irq_default_handler PIN_INT0_IRQHandler
def_irq_default_handler PIN_INT1_IRQHandler
def_irq_default_handler PIN_INT2_IRQHandler
def_irq_default_handler PIN_INT3_IRQHandler
def_irq_default_handler PIN_INT4_IRQHandler
def_irq_default_handler PIN_INT5_IRQHandler
def_irq_default_handler PIN_INT6_IRQHandler
def_irq_default_handler PIN_INT7_IRQHandler
def_irq_default_handler GINT0_IRQHandler
def_irq_default_handler GINT1_IRQHandler
def_irq_default_handler EVENTROUTER_IRQHandler
def_irq_default_handler C_CAN1_IRQHandler
def_irq_default_handler ATIMER_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler WWDT_IRQHandler
def_irq_default_handler C_CAN0_IRQHandler
def_irq_default_handler QEI_IRQHandler
.end

194
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_GCC_ARM/startup_STM32F40x.s
View File

@ -196,27 +196,6 @@ Reset_Handler:
strlt r0, [r2], #4
blt .LC0
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*
* Question - Why is this not in the mbed version?
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
# End clearing the BSS section
ldr r0, =SystemInit
blx r0
ldr r0, =_start
@ -224,6 +203,7 @@ Reset_Handler:
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -248,91 +228,93 @@ Reset_Handler:
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler WWDG_IRQHandler
def_default_handler PVD_IRQHandler
def_default_handler TAMP_STAMP_IRQHandler
def_default_handler RTC_WKUP_IRQHandler
def_default_handler FLASH_IRQHandler
def_default_handler RCC_IRQHandler
def_default_handler EXTI0_IRQHandler
def_default_handler EXTI1_IRQHandler
def_default_handler EXTI2_IRQHandler
def_default_handler EXTI3_IRQHandler
def_default_handler EXTI4_IRQHandler
def_default_handler DMA1_Stream0_IRQHandler
def_default_handler DMA1_Stream1_IRQHandler
def_default_handler DMA1_Stream2_IRQHandler
def_default_handler DMA1_Stream3_IRQHandler
def_default_handler DMA1_Stream4_IRQHandler
def_default_handler DMA1_Stream5_IRQHandler
def_default_handler DMA1_Stream6_IRQHandler
def_default_handler ADC_IRQHandler
def_default_handler CAN1_TX_IRQHandler
def_default_handler CAN1_RX0_IRQHandler
def_default_handler CAN1_RX1_IRQHandler
def_default_handler CAN1_SCE_IRQHandler
def_default_handler EXTI9_5_IRQHandler
def_default_handler TIM1_BRK_TIM9_IRQHandler
def_default_handler TIM1_UP_TIM10_IRQHandler
def_default_handler TIM1_TRG_COM_TIM11_IRQHandler
def_default_handler TIM1_CC_IRQHandler
def_default_handler TIM2_IRQHandler
def_default_handler TIM3_IRQHandler
def_default_handler TIM4_IRQHandler
def_default_handler I2C1_EV_IRQHandler
def_default_handler I2C1_ER_IRQHandler
def_default_handler I2C2_EV_IRQHandler
def_default_handler I2C2_ER_IRQHandler
def_default_handler SPI1_IRQHandler
def_default_handler SPI2_IRQHandler
def_default_handler USART1_IRQHandler
def_default_handler USART2_IRQHandler
def_default_handler USART3_IRQHandler
def_default_handler EXTI15_10_IRQHandler
def_default_handler RTC_Alarm_IRQHandler
def_default_handler OTG_FS_WKUP_IRQHandler
def_default_handler TIM8_BRK_TIM12_IRQHandler
def_default_handler TIM8_UP_TIM13_IRQHandler
def_default_handler TIM8_TRG_COM_TIM14_IRQHandler
def_default_handler TIM8_CC_IRQHandler
def_default_handler DMA1_Stream7_IRQHandler
def_default_handler FSMC_IRQHandler
def_default_handler SDIO_IRQHandler
def_default_handler TIM5_IRQHandler
def_default_handler SPI3_IRQHandler
def_default_handler UART4_IRQHandler
def_default_handler UART5_IRQHandler
def_default_handler TIM6_DAC_IRQHandler
def_default_handler TIM7_IRQHandler
def_default_handler DMA2_Stream0_IRQHandler
def_default_handler DMA2_Stream1_IRQHandler
def_default_handler DMA2_Stream2_IRQHandler
def_default_handler DMA2_Stream3_IRQHandler
def_default_handler DMA2_Stream4_IRQHandler
def_default_handler ETH_IRQHandler
def_default_handler ETH_WKUP_IRQHandler
def_default_handler CAN2_TX_IRQHandler
def_default_handler CAN2_RX0_IRQHandler
def_default_handler CAN2_RX1_IRQHandler
def_default_handler CAN2_SCE_IRQHandler
def_default_handler OTG_FS_IRQHandler
def_default_handler DMA2_Stream5_IRQHandler
def_default_handler DMA2_Stream6_IRQHandler
def_default_handler DMA2_Stream7_IRQHandler
def_default_handler USART6_IRQHandler
def_default_handler I2C3_EV_IRQHandler
def_default_handler I2C3_ER_IRQHandler
def_default_handler OTG_HS_EP1_OUT_IRQHandler
def_default_handler OTG_HS_EP1_IN_IRQHandler
def_default_handler OTG_HS_WKUP_IRQHandler
def_default_handler OTG_HS_IRQHandler
def_default_handler DCMI_IRQHandler
def_default_handler CRYP_IRQHandler
def_default_handler HASH_RNG_IRQHandler
def_default_handler FPU_IRQHandler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
def_irq_default_handler WWDG_IRQHandler
def_irq_default_handler PVD_IRQHandler
def_irq_default_handler TAMP_STAMP_IRQHandler
def_irq_default_handler RTC_WKUP_IRQHandler
def_irq_default_handler FLASH_IRQHandler
def_irq_default_handler RCC_IRQHandler
def_irq_default_handler EXTI0_IRQHandler
def_irq_default_handler EXTI1_IRQHandler
def_irq_default_handler EXTI2_IRQHandler
def_irq_default_handler EXTI3_IRQHandler
def_irq_default_handler EXTI4_IRQHandler
def_irq_default_handler DMA1_Stream0_IRQHandler
def_irq_default_handler DMA1_Stream1_IRQHandler
def_irq_default_handler DMA1_Stream2_IRQHandler
def_irq_default_handler DMA1_Stream3_IRQHandler
def_irq_default_handler DMA1_Stream4_IRQHandler
def_irq_default_handler DMA1_Stream5_IRQHandler
def_irq_default_handler DMA1_Stream6_IRQHandler
def_irq_default_handler ADC_IRQHandler
def_irq_default_handler CAN1_TX_IRQHandler
def_irq_default_handler CAN1_RX0_IRQHandler
def_irq_default_handler CAN1_RX1_IRQHandler
def_irq_default_handler CAN1_SCE_IRQHandler
def_irq_default_handler EXTI9_5_IRQHandler
def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
def_irq_default_handler TIM1_UP_TIM10_IRQHandler
def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
def_irq_default_handler TIM1_CC_IRQHandler
def_irq_default_handler TIM2_IRQHandler
def_irq_default_handler TIM3_IRQHandler
def_irq_default_handler TIM4_IRQHandler
def_irq_default_handler I2C1_EV_IRQHandler
def_irq_default_handler I2C1_ER_IRQHandler
def_irq_default_handler I2C2_EV_IRQHandler
def_irq_default_handler I2C2_ER_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler SPI2_IRQHandler
def_irq_default_handler USART1_IRQHandler
def_irq_default_handler USART2_IRQHandler
def_irq_default_handler USART3_IRQHandler
def_irq_default_handler EXTI15_10_IRQHandler
def_irq_default_handler RTC_Alarm_IRQHandler
def_irq_default_handler OTG_FS_WKUP_IRQHandler
def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
def_irq_default_handler TIM8_UP_TIM13_IRQHandler
def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
def_irq_default_handler TIM8_CC_IRQHandler
def_irq_default_handler DMA1_Stream7_IRQHandler
def_irq_default_handler FSMC_IRQHandler
def_irq_default_handler SDIO_IRQHandler
def_irq_default_handler TIM5_IRQHandler
def_irq_default_handler SPI3_IRQHandler
def_irq_default_handler UART4_IRQHandler
def_irq_default_handler UART5_IRQHandler
def_irq_default_handler TIM6_DAC_IRQHandler
def_irq_default_handler TIM7_IRQHandler
def_irq_default_handler DMA2_Stream0_IRQHandler
def_irq_default_handler DMA2_Stream1_IRQHandler
def_irq_default_handler DMA2_Stream2_IRQHandler
def_irq_default_handler DMA2_Stream3_IRQHandler
def_irq_default_handler DMA2_Stream4_IRQHandler
def_irq_default_handler ETH_IRQHandler
def_irq_default_handler ETH_WKUP_IRQHandler
def_irq_default_handler CAN2_TX_IRQHandler
def_irq_default_handler CAN2_RX0_IRQHandler
def_irq_default_handler CAN2_RX1_IRQHandler
def_irq_default_handler CAN2_SCE_IRQHandler
def_irq_default_handler OTG_FS_IRQHandler
def_irq_default_handler DMA2_Stream5_IRQHandler
def_irq_default_handler DMA2_Stream6_IRQHandler
def_irq_default_handler DMA2_Stream7_IRQHandler
def_irq_default_handler USART6_IRQHandler
def_irq_default_handler I2C3_EV_IRQHandler
def_irq_default_handler I2C3_ER_IRQHandler
def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
def_irq_default_handler OTG_HS_WKUP_IRQHandler
def_irq_default_handler OTG_HS_IRQHandler
def_irq_default_handler DCMI_IRQHandler
def_irq_default_handler CRYP_IRQHandler
def_irq_default_handler HASH_RNG_IRQHandler
def_irq_default_handler FPU_IRQHandler
def_irq_default_handler DEF_IRQHandler
.end

16
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11UXX/pwmout_api.c
View File

@ -66,8 +66,6 @@ static LPC_CTxxBx_Type *Timers[4] = {
LPC_CT32B0, LPC_CT32B1
};
static unsigned int pwm_clock_mhz;
void pwmout_init(pwmout_t* obj, PinName pin) {
// determine the channel
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
@ -92,8 +90,6 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
/* Reset Functionality on MR3 controlling the PWM period */
timer->MCR = 1 << 10;
pwm_clock_mhz = SystemCoreClock / 1000000;
// default to 20ms: standard for servos, and fine for e.g. brightness control
pwmout_period_ms(obj, 20);
pwmout_write (obj, 0);
@ -141,11 +137,18 @@ void pwmout_period_ms(pwmout_t* obj, int ms) {
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
int i = 0;
uint32_t period_ticks = pwm_clock_mhz * us;
uint32_t period_ticks = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
timer_mr tid = pwm_timer_map[obj->pwm];
LPC_CTxxBx_Type *timer = Timers[tid.timer];
uint32_t old_period_ticks = timer->MR3;
// for 16bit timer, set prescaler to avoid overflow
uint16_t high_period_ticks = period_ticks >> 16;
if ((high_period_ticks) && (timer == LPC_CT16B0 || timer == LPC_CT16B1)) {
timer->PR = high_period_ticks;
period_ticks /= (high_period_ticks + 1);
}
timer->TCR = TCR_RESET;
timer->MR3 = period_ticks;
@ -169,13 +172,14 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
uint32_t t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
timer_mr tid = pwm_timer_map[obj->pwm];
LPC_CTxxBx_Type *timer = Timers[tid.timer];
uint32_t t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000 / (timer->PR + 1));
timer->TCR = TCR_RESET;
if (t_on > timer->MR3) {
pwmout_period_us(obj, us);
t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000 / (timer->PR + 1));
}
uint32_t t_off = timer->MR3 - t_on;
timer->MR[tid.mr] = t_off;

1
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/device.h
View File

@ -26,6 +26,7 @@
#define DEVICE_ANALOGOUT 1
#define DEVICE_SERIAL 1
#define DEVICE_SERIAL_FC 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1

4
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/objects.h
View File

@ -20,6 +20,7 @@
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "gpio_object.h"
#ifdef __cplusplus
extern "C" {
@ -47,7 +48,6 @@ struct pwmout_s {
struct serial_s {
LPC_UART_TypeDef *uart;
int index;
uint8_t count;
};
struct analogin_s {
@ -71,8 +71,6 @@ struct spi_s {
LPC_SSP_TypeDef *spi;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif

134
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c
View File

@ -21,6 +21,7 @@
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "gpio_api.h"
/******************************************************************************
* INITIALIZATION
@ -51,12 +52,35 @@ static const PinMap PinMap_UART_RX[] = {
{NC , NC , 0}
};
static uint32_t serial_irq_ids[UART_NUM] = {0};
static const PinMap PinMap_UART_RTS[] = {
{P0_22, UART_1, 1},
{P2_7, UART_1, 2},
{NC, NC, 0}
};
static const PinMap PinMap_UART_CTS[] = {
{P0_17, UART_1, 1},
{P2_2, UART_1, 2},
{NC, NC, 0}
};
#define UART_MCR_RTSEN_MASK (1 << 6)
#define UART_MCR_CTSEN_MASK (1 << 7)
#define UART_MCR_FLOWCTRL_MASK (UART_MCR_RTSEN_MASK | UART_MCR_CTSEN_MASK)
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
@ -106,7 +130,9 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
case UART_2: obj->index = 2; break;
case UART_3: obj->index = 3; break;
}
obj->count = 0;
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
serial_set_flow_control(obj, FlowControlNone, NC, NC);
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
@ -117,7 +143,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
}
void serial_free(serial_t *obj) {
serial_irq_ids[obj->index] = 0;
uart_data[obj->index].serial_irq_id = 0;
}
// serial_baud
@ -251,7 +277,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t iir, uint32_t index) {
static inline void uart_irq(uint32_t iir, uint32_t index, LPC_UART_TypeDef *puart) {
// [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
SerialIrq irq_type;
switch (iir) {
@ -259,22 +285,28 @@ static inline void uart_irq(uint32_t iir, uint32_t index) {
case 2: irq_type = RxIrq; break;
default: return;
}
if (serial_irq_ids[index] != 0)
irq_handler(serial_irq_ids[index], irq_type);
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api)
puart->IER &= ~(1 << RxIrq);
}
if (uart_data[index].serial_irq_id != 0)
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
irq_handler(uart_data[index].serial_irq_id, irq_type);
}
void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0, (LPC_UART_TypeDef*)LPC_UART0);}
void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);}
void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);}
void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
serial_irq_ids[obj->index] = id;
uart_data[obj->index].serial_irq_id = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
@ -288,7 +320,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
obj->uart->IER |= 1 << irq;
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else { // disable
} else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->IER &= ~(1 << irq);
@ -298,18 +330,33 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
if (RxIrq == irq)
uart_data[obj->index].rx_irq_set_api = enable;
serial_irq_set_internal(obj, irq, enable);
}
static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
uart_data[obj->index].rx_irq_set_flow = enable;
serial_irq_set_internal(obj, RxIrq, enable);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (!serial_readable(obj));
return obj->uart->RBR;
int data = obj->uart->RBR;
if (NC != uart_data[obj->index].sw_rts.pin) {
gpio_write(&uart_data[obj->index].sw_rts, 0);
obj->uart->IER |= 1 << RxIrq;
}
return data;
}
void serial_putc(serial_t *obj, int c) {
while (!serial_writable(obj));
obj->uart->THR = c;
obj->count++;
}
int serial_readable(serial_t *obj) {
@ -318,11 +365,10 @@ int serial_readable(serial_t *obj) {
int serial_writable(serial_t *obj) {
int isWritable = 1;
if (obj->uart->LSR & 0x20)
obj->count = 0;
else if (obj->count >= 16)
isWritable = 0;
if (NC != uart_data[obj->index].sw_cts.pin)
isWritable = gpio_read(&uart_data[obj->index].sw_cts) == 0;
if (isWritable)
isWritable = obj->uart->LSR & 0x40;
return isWritable;
}
@ -345,3 +391,49 @@ void serial_break_clear(serial_t *obj) {
obj->uart->LCR &= ~(1 << 6);
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
// Only UART1 has hardware flow control on LPC176x
LPC_UART1_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)LPC_UART1 ? LPC_UART1 : NULL;
int index = obj->index;
// First, disable flow control completely
if (uart1)
uart1->MCR = uart1->MCR & ~UART_MCR_FLOWCTRL_MASK;
uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
serial_flow_irq_set(obj, 0);
if (FlowControlNone == type)
return;
// Check type(s) of flow control to use
UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
if (((FlowControlCTS == type) || (FlowControlRTSCTS == type)) && (NC != txflow)) {
// Can this be enabled in hardware?
if ((UART_1 == uart_cts) && (NULL != uart1)) {
// Enable auto-CTS mode
uart1->MCR |= UART_MCR_CTSEN_MASK;
pinmap_pinout(txflow, PinMap_UART_CTS);
} else {
// Can't enable in hardware, use software emulation
gpio_init(&uart_data[index].sw_cts, txflow, PIN_INPUT);
}
}
if (((FlowControlRTS == type) || (FlowControlRTSCTS == type)) && (NC != rxflow)) {
// Enable FIFOs, trigger level of 1 char on RX FIFO
obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
| 1 << 1 // Rx Fifo Reset
| 1 << 2 // Tx Fifo Reset
| 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
// Can this be enabled in hardware?
if ((UART_1 == uart_rts) && (NULL != uart1)) {
// Enable auto-RTS mode
uart1->MCR |= UART_MCR_RTSEN_MASK;
pinmap_pinout(rxflow, PinMap_UART_RTS);
} else { // can't enable in hardware, use software emulation
gpio_init(&uart_data[index].sw_rts, rxflow, PIN_OUTPUT);
gpio_write(&uart_data[index].sw_rts, 0);
// Enable RX interrupt
serial_flow_irq_set(obj, 1);
}
}
}

1
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h
View File

@ -26,6 +26,7 @@
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_SERIAL_FC 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 0

44
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c
View File

@ -39,6 +39,18 @@ static const SWM_Map SWM_UART_RX[] = {
{2, 24},
};
static const SWM_Map SWM_UART_RTS[] = {
{0, 16},
{1, 24},
{3, 0},
};
static const SWM_Map SWM_UART_CTS[] = {
{0, 24},
{2, 0},
{3, 8}
};
// bit flags for used UARTs
static unsigned char uart_used = 0;
static int get_available_uart(void) {
@ -60,6 +72,7 @@ static int get_available_uart(void) {
#define TXRDY (0x01<<2)
#define TXBRKEN (0x01<<1)
#define CTSEN (0x01<<9)
static uint32_t UARTSysClk;
@ -278,3 +291,34 @@ void serial_break_clear(serial_t *obj) {
obj->uart->CTRL &= ~TXBRKEN;
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
const SWM_Map *swm_rts, *swm_cts;
uint32_t regVal_rts, regVal_cts;
swm_rts = &SWM_UART_RTS[obj->index];
swm_cts = &SWM_UART_CTS[obj->index];
regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
if (FlowControlNone == type) {
LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
obj->uart->CFG &= ~CTSEN;
return;
}
if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (rxflow << swm_rts->offset);
if (FlowControlRTS == type) {
LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
obj->uart->CFG &= ~CTSEN;
}
}
if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (txflow << swm_cts->offset);
obj->uart->CFG |= CTSEN;
if (FlowControlCTS == type) {
LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
}
}
}

34
libraries/tests/mbed/echo_flow_control/main.cpp Normal file
View File

@ -0,0 +1,34 @@
#include "mbed.h"
#if defined(TARGET_LPC1768)
#define UART_TX p9
#define UART_RX p10
#define FLOW_CONTROL_RTS p30
#define FLOW_CONTROL_CTS p29
#define RTS_CHECK_PIN p8
#else
#error This test is not supported on this target
#endif
Serial pc(UART_TX, UART_RX);
#ifdef RTS_CHECK_PIN
InterruptIn in(RTS_CHECK_PIN);
DigitalOut led(LED1);
static void checker(void) {
led = !led;
}
#endif
int main() {
char buf[256];
pc.set_flow_control(Serial::RTSCTS, FLOW_CONTROL_RTS, FLOW_CONTROL_CTS);
#ifdef RTS_CHECK_PIN
in.fall(checker);
#endif
while (1) {
pc.gets(buf, 256);
pc.printf("%s", buf);
}
}

26
setup.py
View File

@ -4,6 +4,10 @@ PyPI package for the Mbed SDK
"""
from distutils.core import setup
from setuptools import find_packages
from os.path import isfile, join
from tempfile import TemporaryFile
from shutil import copyfileobj
LICENSE = open('LICENSE').read()
DESCRIPTION = """A set of Python scripts that can be used to compile programs written on top of the `mbed framework`_. It can also be used to export mbed projects to other build systems and IDEs (uVision, IAR, makefiles).
@ -12,8 +16,21 @@ DESCRIPTION = """A set of Python scripts that can be used to compile programs wr
OWNER_NAMES = 'emilmont, bogdanm'
OWNER_EMAILS = 'Emilio.Monti@arm.com, Bogdan.Marinescu@arm.com'
# If private_settings.py exists in workspace_tools, read it in a temporary file
# so it can be restored later
private_settings = join('workspace_tools', 'private_settings.py')
backup = None
if isfile(private_settings):
backup = TemporaryFile()
with open(private_settings, "rb") as f:
copyfileobj(f, backup)
# Create the correct private_settings.py for the distribution
with open(private_settings, "wt") as f:
f.write("from mbed_settings import *\n")
setup(name='mbed-tools',
version='0.1.7',
version='0.1.14',
description='Build and test system for mbed',
long_description=DESCRIPTION,
author=OWNER_NAMES,
@ -21,4 +38,11 @@ setup(name='mbed-tools',
maintainer=OWNER_NAMES,
maintainer_email=OWNER_EMAILS,
url='https://github.com/mbedmicro/mbed',
packages=find_packages(),
license=LICENSE)
# Restore previous private_settings if needed
if backup:
backup.seek(0)
with open(private_settings, "wb") as f:
copyfileobj(backup, f)

2
workspace_tools/autotest.py
View File

@ -21,7 +21,7 @@ import datetime
from time import time
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.build_api import build_project, build_mbed_libs
from workspace_tools.tests import TEST_MAP, GROUPS

2
workspace_tools/build.py
View File

@ -23,7 +23,7 @@ from os.path import join, abspath, dirname
# Be sure that the tools directory is in the search path
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.toolchains import TOOLCHAINS
from workspace_tools.targets import TARGET_NAMES, TARGET_MAP

2
workspace_tools/build_release.py
View File

@ -20,7 +20,7 @@ from os.path import join, abspath, dirname
# Be sure that the tools directory is in the search path
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.build_api import build_mbed_libs
from workspace_tools.targets import TARGET_MAP

2
workspace_tools/export_test.py
View File

@ -17,7 +17,7 @@ limitations under the License.
import sys
from os.path import join, abspath, dirname, exists
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from shutil import move

48
workspace_tools/host_tests/echo_flow_control.py Normal file
View File

@ -0,0 +1,48 @@
"""
mbed SDK
Copyright (c) 2011-2013 ARM Limited
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
"""
from host_test import Test
class EchoTest(Test):
def __init__(self):
Test.__init__(self)
self.mbed.init_serial()
self.mbed.extra_serial.rtscts = True
self.mbed.reset()
def test(self):
self.mbed.flush()
self.notify("Starting the ECHO test")
TEST="longer serial test"
check = True
for i in range(1, 100):
self.mbed.extra_serial.write(TEST + "\n")
l = self.mbed.extra_serial.readline().strip()
if not l: continue
if l != TEST:
check = False
self.notify('"%s" != "%s"' % (l, TEST))
else:
if (i % 10) == 0:
self.notify('.')
return check
if __name__ == '__main__':
EchoTest().run()

14
workspace_tools/host_tests/host_test.py
View File

@ -38,6 +38,9 @@ class Mbed:
parser.add_option("-t", "--timeout", dest="timeout",
help="Timeout", metavar="TIMEOUT")
parser.add_option("-e", "--extra", dest="extra",
help="Extra serial port (used by some tests)", metavar="EXTRA")
(self.options, _) = parser.parse_args()
@ -46,14 +49,19 @@ class Mbed:
self.port = self.options.port
self.disk = self.options.disk
self.extra_port = self.options.extra
self.extra_serial = None
self.serial = None
self.timeout = 10 if self.options.timeout is None else self.options.timeout
print 'Mbed: "%s" "%s"' % (self.port, self.disk)
def init_serial(self, baud=9600):
def init_serial(self, baud=9600, extra_baud=9600):
self.serial = Serial(self.port, timeout = 1)
self.serial.setBaudrate(baud)
if self.extra_port:
self.extra_serial = Serial(self.extra_port, timeout = 1)
self.extra_serial.setBaudrate(extra_baud)
self.flush()
def reset(self):
@ -64,7 +72,9 @@ class Mbed:
def flush(self):
self.serial.flushInput()
self.serial.flushOutput()
if self.extra_serial:
self.extra_serial.flushInput()
self.extra_serial.flushOutput()
class Test:
def __init__(self):

2
workspace_tools/host_tests/tcpecho_server_loop.py
View File

@ -18,7 +18,7 @@ limitations under the License.
import sys
from os.path import join, abspath, dirname
ROOT = abspath(join(dirname(__file__), "..", ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.private_settings import LOCALHOST
from SocketServer import BaseRequestHandler, TCPServer

2
workspace_tools/make.py
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@ -25,7 +25,7 @@ from time import sleep
# Be sure that the tools directory is in the search path
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.options import get_default_options_parser
from workspace_tools.build_api import build_project

2
workspace_tools/project.py
View File

@ -1,7 +1,7 @@
import sys
from os.path import join, abspath, dirname, exists
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from shutil import move
from optparse import OptionParser

9
workspace_tools/server.py
View File

@ -27,7 +27,7 @@ import json
# Be sure that the tools directory is in the search path
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.utils import delete_dir_files
from workspace_tools.settings import *
@ -57,9 +57,9 @@ class ProcessObserver(Thread):
pass
def run_host_test(client, name, disk, port, duration):
def run_host_test(client, name, disk, port, duration, extra_serial):
print "{%s}" % name,
cmd = ["python", "%s.py" % name, '-p', port, '-d', disk, '-t', str(duration)]
cmd = ["python", "%s.py" % name, '-p', port, '-d', disk, '-t', str(duration), "-e", extra_serial]
proc = Popen(cmd, stdout=PIPE, cwd=HOST_TESTS)
obs = ProcessObserver(proc)
start = time()
@ -144,6 +144,7 @@ class Tester(BaseRequestHandler):
disk = mut['disk']
port = mut['port']
extra_serial = mut.get('extra_serial', "")
target = TARGET_MAP[mut['mcu']]
# Program
@ -169,7 +170,7 @@ class Tester(BaseRequestHandler):
# Host test
self.request.setblocking(0)
result = run_host_test(self.request, test.host_test, disk, port, duration)
result = run_host_test(self.request, test.host_test, disk, port, duration, extra_serial)
self.send_result(result)

2
workspace_tools/settings.py
View File

@ -106,4 +106,4 @@ try:
# settings file stored in the repository
from workspace_tools.private_settings import *
except ImportError:
print '[WARNING] Using default settings. Define you settings in the file "workspace_tools/private_settings.py"'
print '[WARNING] Using default settings. Define you settings in the file "workspace_tools/private_settings.py" or in "./mbed_settings.py"'

2
workspace_tools/size.py
View File

@ -21,7 +21,7 @@ import csv
from collections import defaultdict
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.paths import BUILD_DIR, TOOLS_DATA
from workspace_tools.settings import GCC_ARM_PATH

2
workspace_tools/synch.py
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@ -29,7 +29,7 @@ import re
import string
ROOT = abspath(join(dirname(__file__), ".."))
sys.path.append(ROOT)
sys.path.insert(0, ROOT)
from workspace_tools.settings import MBED_ORG_PATH, MBED_ORG_USER, BUILD_DIR
from workspace_tools.paths import LIB_DIR

9
workspace_tools/tests.py
View File

@ -219,6 +219,15 @@ TESTS = [
"automated": True,
"mcu": ["LPC4088"]
},
{
"id": "MBED_A24", "description": "Serial echo with RTS/CTS flow control",
"source_dir": join(TEST_DIR, "mbed", "echo_flow_control"),
"dependencies": [MBED_LIBRARIES],
"automated": "True",
"host_test": "echo_flow_control",
"mcu": ["LPC1768"],
"peripherals": ["extra_serial"]
},
# Size benchmarks
{