diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index 8a5faac289..85de28c548 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -24,3 +24,10 @@ [ ] Test update [ ] Breaking change +### Reviewers + + + diff --git a/.travis.yml b/.travis.yml index 37d7617af3..cf30d9bb0b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,3 +1,19 @@ +# Copyright (c) 2013-2018 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + language: python python: 2.7 @@ -30,8 +46,6 @@ before_install: # Setup ppa to make sure arm-none-eabi-gcc is correct version - sudo add-apt-repository -y ppa:team-gcc-arm-embedded/ppa - sudo add-apt-repository -y ppa:deadsnakes/ppa - # import the new keys for rabbitmq (fix for https://github.com/ARMmbed/mbed-os/issues/8945) - - curl -s https://packagecloud.io/install/repositories/rabbitmq/rabbitmq-server/script.deb.sh | sudo bash # Loop until update succeeds (timeouts can occur) - travis_retry $(! sudo apt-get update 2>&1 |grep Failed) @@ -120,7 +134,7 @@ matrix: - env: - NAME=astyle install: - - curl -L0 http://mbed-os.s3-eu-west-1.amazonaws.com/builds/deps/astyle_3.1_linux.tar.gz --output astyle.tar.gz; + - curl -L0 https://mbed-os.s3-eu-west-1.amazonaws.com/builds/deps/astyle_3.1_linux.tar.gz --output astyle.tar.gz; mkdir -p BUILD && tar xf astyle.tar.gz -C BUILD; pushd BUILD/astyle/build/gcc; make; diff --git a/TESTS/mbed_drivers/flashiap/main.cpp b/TESTS/mbed_drivers/flashiap/main.cpp index be46362d55..263376c919 100644 --- a/TESTS/mbed_drivers/flashiap/main.cpp +++ b/TESTS/mbed_drivers/flashiap/main.cpp @@ -59,8 +59,8 @@ void flashiap_program_test() // the one before the last sector in the system uint32_t address = (flash_device.get_flash_start() + flash_device.get_flash_size()) - (sector_size); TEST_ASSERT_TRUE(address != 0UL); - utest_printf("ROM ends at 0x%lx, test starts at 0x%lx\n", FLASHIAP_ROM_END, address); - TEST_SKIP_UNLESS_MESSAGE(address >= FLASHIAP_ROM_END, "Test skipped. Test region overlaps code."); + utest_printf("ROM ends at 0x%lx, test starts at 0x%lx\n", FLASHIAP_APP_ROM_END_ADDR, address); + TEST_SKIP_UNLESS_MESSAGE(address >= FLASHIAP_APP_ROM_END_ADDR, "Test skipped. Test region overlaps code."); ret = flash_device.erase(address, sector_size); TEST_ASSERT_EQUAL_INT32(0, ret); @@ -128,7 +128,7 @@ void flashiap_cross_sector_program_test() agg_size += sector_size; address -= sector_size; } - TEST_SKIP_UNLESS_MESSAGE(address >= FLASHIAP_ROM_END, "Test skipped. Test region overlaps code."); + TEST_SKIP_UNLESS_MESSAGE(address >= FLASHIAP_APP_ROM_END_ADDR, "Test skipped. Test region overlaps code."); ret = flash_device.erase(address, agg_size); TEST_ASSERT_EQUAL_INT32(0, ret); @@ -184,7 +184,7 @@ void flashiap_program_error_test() TEST_ASSERT_TRUE(address != 0UL); // unaligned address - TEST_SKIP_UNLESS_MESSAGE(address >= FLASHIAP_ROM_END, "Test skipped. Test region overlaps code."); + TEST_SKIP_UNLESS_MESSAGE(address >= FLASHIAP_APP_ROM_END_ADDR, "Test skipped. Test region overlaps code."); ret = flash_device.erase(address + 1, sector_size); TEST_ASSERT_EQUAL_INT32(-1, ret); if (flash_device.get_page_size() > 1) { diff --git a/TESTS/mbed_hal/qspi/flash_configs/MX25L51245G_config.h b/TESTS/mbed_hal/qspi/flash_configs/MX25L51245G_config.h new file mode 100644 index 0000000000..8a71a9f37a --- /dev/null +++ b/TESTS/mbed_hal/qspi/flash_configs/MX25L51245G_config.h @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_QSPI_FLASH_MX25L51245G_H +#define MBED_QSPI_FLASH_MX25L51245G_H + + +#define QSPI_FLASH_CHIP_STRING "macronix MX25L51245G" + +// Command for reading status register +#define QSPI_CMD_RDSR 0x05 +// Command for reading configuration register +#define QSPI_CMD_RDCR0 0x15 +// Command for writing status/configuration register +#define QSPI_CMD_WRSR 0x01 +// Command for reading security register +#define QSPI_CMD_RDSCUR 0x2B + +// Command for setting Reset Enable +#define QSPI_CMD_RSTEN 0x66 +// Command for setting Reset +#define QSPI_CMD_RST 0x99 + +// Command for setting write enable +#define QSPI_CMD_WREN 0x06 +// Command for setting write disable +#define QSPI_CMD_WRDI 0x04 + +// WRSR operations max time [us] (datasheet max time + 15%) +#define QSPI_WRSR_MAX_TIME 34500 // 30ms +// general wait max time [us] +#define QSPI_WAIT_MAX_TIME 100000 // 100ms + + +// Commands for writing (page programming) +#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode +#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode + +// write operations max time [us] (datasheet max time + 15%) +#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms + +#define QSPI_PAGE_SIZE 256 // 256B +#define QSPI_SECTOR_SIZE 4096 // 4kB +#define QSPI_SECTOR_COUNT 2048 // + +// Commands for reading +#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode +#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode +#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode +#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode +#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode +#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode + +#define QSPI_READ_1IO_DUMMY_CYCLE 0 +#define QSPI_READ_FAST_DUMMY_CYCLE 8 +#define QSPI_READ_2IO_DUMMY_CYCLE 4 +#define QSPI_READ_1I2O_DUMMY_CYCLE 8 +#define QSPI_READ_4IO_DUMMY_CYCLE 6 +#define QSPI_READ_1I4O_DUMMY_CYCLE 8 + +// Commands for erasing +#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB +#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB +#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB +#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7 + +// erase operations max time [us] (datasheet max time + 15%) +#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms +#define QSPI_ERASE_BLOCK_32_MAX_TIME 1200000 // 1s +#define QSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s + +// max frequency for basic rw operation (for fast mode) +#define QSPI_COMMON_MAX_FREQUENCY 32000000 + +#define QSPI_STATUS_REG_SIZE 1 +#define QSPI_CONFIG_REG_0_SIZE 2 +#define QSPI_SECURITY_REG_SIZE 1 +#define QSPI_MAX_REG_SIZE 2 + +// status register +#define STATUS_BIT_WIP (1 << 0) // write in progress bit +#define STATUS_BIT_WEL (1 << 1) // write enable latch +#define STATUS_BIT_BP0 (1 << 2) // +#define STATUS_BIT_BP1 (1 << 3) // +#define STATUS_BIT_BP2 (1 << 4) // +#define STATUS_BIT_BP3 (1 << 5) // +#define STATUS_BIT_QE (1 << 6) // Quad Enable +#define STATUS_BIT_SRWD (1 << 7) // status register write protect + +// configuration register 0 +// bit 0, 1, 2, 4, 5, 7 reserved +#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect + +#endif // MBED_QSPI_FLASH_MX25L51245G_H diff --git a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h index 59380febf8..6358a0aafa 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h +++ b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h @@ -18,19 +18,45 @@ #define MBED_FLASH_CONFIGS_H #if defined(TARGET_DISCO_L475VG_IOT01A) -#include "STM/DISCO_L475VG_IOT01A/flash_config.h" +#include "MX25RXX35F_config.h" // MX25R6435F + +#elif defined(TARGET_DISCO_F413ZH) +#include "N25Q128A_config.h" // N25Q128A13EF840F + +#elif defined(TARGET_DISCO_F746NG) +#include "N25Q128A_config.h" // N25Q128A13EF840E + +#elif defined(TARGET_DISCO_F469NI) +#include "N25Q128A_config.h" // N25Q128A13EF840E + +#elif defined(TARGET_DISCO_F769NI) +#include "MX25L51245G_config.h" // MX25L51245G + +#elif defined(TARGET_DISCO_L476VG) +#include "N25Q128A_config.h" // N25Q128A13EF840E +/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */ +#undef QSPI_CMD_READ_DPI +#undef QSPI_CMD_READ_QPI +#undef QSPI_CMD_WRITE_DPI +#undef QSPI_CMD_WRITE_QPI + +#elif defined(TARGET_DISCO_L496AG) +#include "MX25RXX35F_config.h" // MX25R6435F + #elif defined(TARGET_NRF52840) #include "NORDIC/NRF52840_DK/flash_config.h" -#elif defined(TARGET_DISCO_F413ZH) -#include "STM/DISCO_F413ZH/flash_config.h" + #elif defined(TARGET_EFM32GG11_STK3701) #include "SiliconLabs/EFM32GG11_STK3701/flash_config.h" + #elif defined(TARGET_K82F) #include "NXP/K82F/flash_config.h" + #elif defined(TARGET_KL82Z) #include "NXP/KL82Z/flash_config.h" + #elif defined(TARGET_LPC546XX) #include "NXP/LPC546XX/flash_config.h" -#endif +#endif #endif // MBED_FLASH_CONFIGS_H diff --git a/TESTS/mbed_hal/sleep/main.cpp b/TESTS/mbed_hal/sleep/main.cpp index bfcee25c5d..cf469f9731 100644 --- a/TESTS/mbed_hal/sleep/main.cpp +++ b/TESTS/mbed_hal/sleep/main.cpp @@ -95,7 +95,7 @@ void sleep_usticker_test() TEST_ASSERT_TRUE(sleep_manager_can_deep_sleep()); } -#ifdef DEVICE_LPTICKER +#if DEVICE_LPTICKER /* Test that wake-up time from sleep should be less than 10 ms and * low power ticker interrupt can wake-up target from sleep. */ diff --git a/TESTS/mbed_hal/sleep/sleep_test_utils.h b/TESTS/mbed_hal/sleep/sleep_test_utils.h index b5f16b7627..59724014af 100644 --- a/TESTS/mbed_hal/sleep/sleep_test_utils.h +++ b/TESTS/mbed_hal/sleep/sleep_test_utils.h @@ -105,7 +105,7 @@ void us_ticker_isr(const ticker_data_t *const ticker_data) us_ticker_clear_interrupt(); } -#ifdef DEVICE_LPTICKER +#if DEVICE_LPTICKER void lp_ticker_isr(const ticker_data_t *const ticker_data) { lp_ticker_clear_interrupt(); diff --git a/TESTS/mbed_platform/FileHandle/main.cpp b/TESTS/mbed_platform/FileHandle/main.cpp index 7d5a2c21f5..0bf9d2c18b 100644 --- a/TESTS/mbed_platform/FileHandle/main.cpp +++ b/TESTS/mbed_platform/FileHandle/main.cpp @@ -384,17 +384,15 @@ void test_fprintf_fscanf() /** Test fseek and ftell * - * Given already opened file is empty - * - * When set the file position indicator via fseek - * Then underneath retargeting layer seek function is called - * fseek return with succeed and ftell return already set position + * ARM library is quite good at optimising out unnecessary calls to underlying + * seek, so only test real non empty files. * * Given already opened file is not empty * * When set the file position indicator via fseek * Then underneath retargeting layer seek function is called * fseek return with succeed and ftell return already set position + * Check actual character read or written. * */ void test_fseek_ftell() @@ -413,19 +411,6 @@ void test_fseek_ftell() ftell_ret = std::ftell(file); TEST_ASSERT_EQUAL(0, ftell_ret); - TestFile::resetFunctionCallHistory(); - fssek_ret = std::fseek(file, 0, SEEK_CUR); - TEST_ASSERT_EQUAL(0, fssek_ret); - - TestFile::resetFunctionCallHistory(); - fssek_ret = std::fseek(file, 0, SEEK_SET); - TEST_ASSERT_EQUAL(0, fssek_ret); - - TestFile::resetFunctionCallHistory(); - fssek_ret = std::fseek(file, 0, SEEK_END); - TEST_ASSERT_TRUE(TestFile::functionCalled(TestFile::fnSeek)); - TEST_ASSERT_EQUAL(0, fssek_ret); - const char *str = "Hello world"; const std::size_t size = std::strlen(str); @@ -440,19 +425,28 @@ void test_fseek_ftell() TEST_ASSERT_EQUAL(0, fssek_ret); ftell_ret = std::ftell(file); TEST_ASSERT_EQUAL(5, ftell_ret); + int c = std::fgetc(file); + TEST_ASSERT_TRUE(TestFile::functionCalled(TestFile::fnRead)); + TEST_ASSERT_EQUAL(c, str[5]); TestFile::resetFunctionCallHistory(); - fssek_ret = std::fseek(file, -5, SEEK_CUR); + fssek_ret = std::fseek(file, -6, SEEK_CUR); TEST_ASSERT_EQUAL(0, fssek_ret); ftell_ret = std::ftell(file); TEST_ASSERT_EQUAL(0, ftell_ret); + c = std::fgetc(file); + TEST_ASSERT_TRUE(TestFile::functionCalled(TestFile::fnRead)); + TEST_ASSERT_EQUAL(c, str[0]); TestFile::resetFunctionCallHistory(); fssek_ret = std::fseek(file, 0, SEEK_END); - TEST_ASSERT_TRUE(TestFile::functionCalled(TestFile::fnSeek)); TEST_ASSERT_EQUAL(0, fssek_ret); ftell_ret = std::ftell(file); TEST_ASSERT_EQUAL(size, ftell_ret); + c = std::fputc('!', file); + TEST_ASSERT_TRUE(TestFile::functionCalled(TestFile::fnWrite)); + TEST_ASSERT_EQUAL(c, '!'); + TEST_ASSERT_EQUAL(fh.size(), size + 1); std::fclose(file); } diff --git a/TESTS/mbed_platform/Stream/main.cpp b/TESTS/mbed_platform/Stream/main.cpp index e615e8adfc..288be0aff0 100644 --- a/TESTS/mbed_platform/Stream/main.cpp +++ b/TESTS/mbed_platform/Stream/main.cpp @@ -18,43 +18,196 @@ #include "utest/utest.h" #include "unity/unity.h" #include "mbed.h" +#include "Stream.h" + +/* This test suite verifies that write/read/write/read sequence can be + * successfully executed on the Stream objects. + * + * A qute from C99 standard, paragraph 7.19.5.3, point 6: + * + * When a file is opened with update mode ('+' as the second or third character in the + * above list of mode argument values), both input and output may be performed on the + * associated stream. However, output shall not be directly followed by input without an + * intervening call to the fflush function or to a file positioning function (fseek, + * fsetpos, or rewind), and input shall not be directly followed by output without an + * intervening call to a file positioning function, unless the input operation encounters end- + * of-file. + */ using utest::v1::Case; +const char FMT[] = "Foo%02ibar."; +const size_t FORMATTED_STR_SIZE = 3 + 2 + 4 + 1; +// The test Stream instance has to be able to store two printf() output strings. +const size_t LOOPBACK_BUFF_SIZE = 2 * FORMATTED_STR_SIZE; + class Loopback : public Stream { public: - Loopback(const char *name = NULL) : Stream(name) {} + Loopback(const char *name = NULL) : Stream(name) + { + // The `fgets()` stops reading after a newline or EOF. + // Fill the buffer with newlines to simplify fgets() usage in this test. + memset(_buff, '\n', LOOPBACK_BUFF_SIZE); + _p_index = 0; + _g_index = 0; + } + + virtual ~Loopback() + { + } + + int test_vprintf(const char *fmt, ...) + { + int rc = -1; + std::va_list args; + va_start(args, fmt); + rc = vprintf(fmt, args); + va_end(args); + return rc; + } + + int test_vscanf(const char *fmt, ...) + { + int rc = EOF; + std::va_list args; + va_start(args, fmt); + rc = vscanf(fmt, args); + va_end(args); + return rc; + } protected: - virtual int _getc() - { - return _c; - } virtual int _putc(int c) { - _c = c; + if (_p_index >= LOOPBACK_BUFF_SIZE) { + return -1; + } + _buff[_p_index++] = (int8_t)c; return c; } + + virtual int _getc() + { + if (_g_index >= LOOPBACK_BUFF_SIZE) { + return -1; + } + return _buff[_g_index++]; + } + private: - char _c; + int8_t _buff[LOOPBACK_BUFF_SIZE]; + size_t _p_index; + size_t _g_index; }; -Loopback loop("loopback"); - +/* Test intermixed Stream::putc() / Stream::getc(). + * + * Given a Stream object, + * when a write/read/write/read sequence is executed + * with the use of Stream::putc() and Stream::getc() methods, + * then all operations succeed. + */ void test_putc_getc() { + char char_buff[2] = {'a', 'b'}; + Loopback loop("loopback"); int ret; - char char_buf[2] = {'a', 'b'}; - ret = loop.putc(char_buf[0]); - TEST_ASSERT_EQUAL_INT(char_buf[0], ret); + ret = loop.putc(char_buff[0]); + TEST_ASSERT_EQUAL_INT(char_buff[0], ret); ret = loop.getc(); - TEST_ASSERT_EQUAL_INT(char_buf[0], ret); - ret = loop.putc(char_buf[1]); - TEST_ASSERT_EQUAL_INT(char_buf[1], ret); + TEST_ASSERT_EQUAL_INT(char_buff[0], ret); + ret = loop.putc(char_buff[1]); + TEST_ASSERT_EQUAL_INT(char_buff[1], ret); ret = loop.getc(); - TEST_ASSERT_EQUAL_INT(char_buf[1], ret); - return; + TEST_ASSERT_EQUAL_INT(char_buff[1], ret); +} + +/* Test intermixed Stream::puts() / Stream::gets(). + * + * Given a Stream object, + * when a write/read/write/read sequence is executed, + * with the use of Stream::puts() and Stream::gets() methods, + * then all operations succeed. + */ +void test_puts_gets() +{ + const size_t STR_LEN = 3; + const size_t STR_SIZE = STR_LEN + 1; // +1 for '\0' + char strings[2][STR_SIZE] = {"Foo", "Bar"}; + const size_t GETS_BUFF_SIZE = STR_LEN + 2; // +1 for '\n' (gets() stops AFTER a '\n'), +1 for '\0' + char g_buff[GETS_BUFF_SIZE] = {}; + Loopback loop("loopback"); + int p_rc; + char *g_rc; + + p_rc = loop.puts(strings[0]); + TEST_ASSERT(p_rc >= 0); + g_rc = loop.gets(g_buff, GETS_BUFF_SIZE); + TEST_ASSERT_EQUAL_PTR(g_buff, g_rc); + + p_rc = loop.puts(strings[1]); + TEST_ASSERT(p_rc >= 0); + g_rc = loop.gets(g_buff, GETS_BUFF_SIZE); + TEST_ASSERT_EQUAL_PTR(g_buff, g_rc); +} + +/* Test intermixed Stream::printf() / Stream::scanf(). + * + * Given a Stream object, + * when a write/read/write/read sequence is executed, + * with the use of Stream::printf() and Stream::scanf() methods, + * then all operations succeed. + */ +void test_printf_scanf() +{ + Loopback loop("loopback"); + int p_val, g_val, rc; + + p_val = 42; + g_val = p_val + 1; + rc = loop.printf(FMT, p_val); + TEST_ASSERT(rc > 0); + rc = loop.scanf(FMT, &g_val); + TEST_ASSERT(rc == 1); + TEST_ASSERT_EQUAL_INT(p_val, g_val); + + p_val += 5; + g_val = p_val + 1; + rc = loop.printf(FMT, p_val); + TEST_ASSERT(rc > 0); + rc = loop.scanf(FMT, &g_val); + TEST_ASSERT(rc == 1); + TEST_ASSERT_EQUAL_INT(p_val, g_val); +} + +/* Test intermixed Stream::vprintf() / Stream::vscanf(). + * + * Given a Stream object, + * when a write/read/write/read sequence is executed, + * with the use of Stream::vprintf() and Stream::vscanf() methods, + * then all operations succeed. + */ +void test_vprintf_vscanf() +{ + Loopback loop("loopback"); + int p_val, g_val, rc; + + p_val = 42; + g_val = p_val + 1; + rc = loop.test_vprintf(FMT, p_val); + TEST_ASSERT(rc > 0); + rc = loop.test_vscanf(FMT, &g_val); + TEST_ASSERT(rc == 1); + TEST_ASSERT_EQUAL_INT(p_val, g_val); + + p_val += 5; + g_val = p_val + 1; + rc = loop.test_vprintf(FMT, p_val); + TEST_ASSERT(rc > 0); + rc = loop.test_vscanf(FMT, &g_val); + TEST_ASSERT(rc == 1); + TEST_ASSERT_EQUAL_INT(p_val, g_val); } utest::v1::status_t test_setup(const size_t number_of_cases) @@ -64,7 +217,10 @@ utest::v1::status_t test_setup(const size_t number_of_cases) } Case cases[] = { - Case("Test putc/getc", test_putc_getc) + Case("Test putc/getc", test_putc_getc), + Case("Test puts/gets", test_puts_gets), + Case("Test printf/scanf", test_printf_scanf), + Case("Test vprintf/vscanf", test_vprintf_vscanf) }; utest::v1::Specification specification(test_setup, cases); diff --git a/TESTS/mbed_platform/stats_cpu/main.cpp b/TESTS/mbed_platform/stats_cpu/main.cpp index 51915d92d6..f4c77526fd 100644 --- a/TESTS/mbed_platform/stats_cpu/main.cpp +++ b/TESTS/mbed_platform/stats_cpu/main.cpp @@ -21,7 +21,7 @@ #include "mbed.h" -#if !defined(MBED_CPU_STATS_ENABLED) || !defined(DEVICE_LPTICKER) || !defined(DEVICE_SLEEP) +#if !defined(MBED_CPU_STATS_ENABLED) || !DEVICE_LPTICKER || !DEVICE_SLEEP #error [NOT_SUPPORTED] test not supported #endif diff --git a/TESTS/netsocket/README.md b/TESTS/netsocket/README.md index 971c9d61f6..ae321e4afd 100644 --- a/TESTS/netsocket/README.md +++ b/TESTS/netsocket/README.md @@ -243,8 +243,7 @@ content at minimum: "help" : "Port of echo server", "value" : "7" } - }, - "macros": ["MBED_EXTENDED_TESTS"] + } } ``` @@ -299,7 +298,6 @@ the `mbed_app.json` might look like this: "value" : "7" } }, - "macros": ["MBED_EXTENDED_TESTS"], "target_overrides": { "*": { "target.network-default-interface-type": "WIFI", diff --git a/TESTS/netsocket/dns/asynchronous_dns.cpp b/TESTS/netsocket/dns/asynchronous_dns.cpp index 8dcac3c65c..a9eb6b517d 100644 --- a/TESTS/netsocket/dns/asynchronous_dns.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns.cpp @@ -34,8 +34,8 @@ void ASYNCHRONOUS_DNS() { do_asynchronous_gethostbyname(dns_test_hosts, 1, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == 1); - TEST_ASSERT(result_no_mem == 0); - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(1, result_ok); + TEST_ASSERT_EQUAL(0, result_no_mem); + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } diff --git a/TESTS/netsocket/dns/asynchronous_dns_cache.cpp b/TESTS/netsocket/dns/asynchronous_dns_cache.cpp index 3a25296a3c..caa10bd6ae 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_cache.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_cache.cpp @@ -50,7 +50,7 @@ void ASYNCHRONOUS_DNS_CACHE() semaphore.wait(); - TEST_ASSERT(data.result == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, data.result); TEST_ASSERT(strlen(data.addr.get_ip_address()) > 1); int delay_ms = (ticker_us - started_us) / 1000; diff --git a/TESTS/netsocket/dns/asynchronous_dns_external_event_queue.cpp b/TESTS/netsocket/dns/asynchronous_dns_external_event_queue.cpp index 11291f5e93..2a2493a76d 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_external_event_queue.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_external_event_queue.cpp @@ -57,10 +57,10 @@ void ASYNCHRONOUS_DNS_EXTERNAL_EVENT_QUEUE() do_asynchronous_gethostbyname(dns_test_hosts, MBED_CONF_NSAPI_DNS_CACHE_SIZE, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == MBED_CONF_NSAPI_DNS_CACHE_SIZE); - TEST_ASSERT(result_no_mem == 0); - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(MBED_CONF_NSAPI_DNS_CACHE_SIZE, result_ok); + TEST_ASSERT_EQUAL(0, result_no_mem); + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); // Dispatch event queue Thread eventThread(osPriorityNormal, EXTERNAL_THREAD_SIZE); @@ -73,10 +73,10 @@ void ASYNCHRONOUS_DNS_EXTERNAL_EVENT_QUEUE() do_asynchronous_gethostbyname(dns_test_hosts_second, MBED_CONF_APP_DNS_SIMULT_QUERIES + 1, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == MBED_CONF_APP_DNS_SIMULT_QUERIES); - TEST_ASSERT(result_no_mem == 1); // last query fails for no memory as expected - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(MBED_CONF_APP_DNS_SIMULT_QUERIES, result_ok); + TEST_ASSERT_EQUAL(1, result_no_mem); // last query fails for no memory as expected + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); // Give event queue time to finalise before destructors wait(2.0); diff --git a/TESTS/netsocket/dns/asynchronous_dns_invalid_host.cpp b/TESTS/netsocket/dns/asynchronous_dns_invalid_host.cpp index 57780b26ef..29bed790e9 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_invalid_host.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_invalid_host.cpp @@ -61,8 +61,8 @@ void ASYNCHRONOUS_DNS_INVALID_HOST() do_asynchronous_gethostbyname(dns_test_hosts_new, MBED_CONF_APP_DNS_SIMULT_QUERIES + 1, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == exp_ok); - TEST_ASSERT(result_no_mem == 1); // last query fails for no memory as expected + TEST_ASSERT_EQUAL(exp_ok, result_ok); + TEST_ASSERT_EQUAL(1, result_no_mem); // last query fails for no memory as expected TEST_ASSERT(result_dns_failure == exp_dns_failure || result_dns_failure == exp_dns_failure + 1); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } diff --git a/TESTS/netsocket/dns/asynchronous_dns_non_async_and_async.cpp b/TESTS/netsocket/dns/asynchronous_dns_non_async_and_async.cpp index a565ed50b9..e1b8e7367b 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_non_async_and_async.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_non_async_and_async.cpp @@ -47,7 +47,7 @@ void ASYNCHRONOUS_DNS_NON_ASYNC_AND_ASYNC() semaphore.wait(100); - TEST_ASSERT(data.result == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, data.result); printf("DNS: query \"%s\" => \"%s\"\n", dns_test_hosts_second[0], data.addr.get_ip_address()); diff --git a/TESTS/netsocket/dns/asynchronous_dns_simultaneous.cpp b/TESTS/netsocket/dns/asynchronous_dns_simultaneous.cpp index ae99074570..51806882b5 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_simultaneous.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_simultaneous.cpp @@ -35,8 +35,8 @@ void ASYNCHRONOUS_DNS_SIMULTANEOUS() do_asynchronous_gethostbyname(dns_test_hosts_second, MBED_CONF_APP_DNS_SIMULT_QUERIES + 1, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == MBED_CONF_APP_DNS_SIMULT_QUERIES); - TEST_ASSERT(result_no_mem == 1); // last query fails for no memory as expected - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(MBED_CONF_APP_DNS_SIMULT_QUERIES, result_ok); + TEST_ASSERT_EQUAL(1, result_no_mem); // last query fails for no memory as expected + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } diff --git a/TESTS/netsocket/dns/asynchronous_dns_simultaneous_cache.cpp b/TESTS/netsocket/dns/asynchronous_dns_simultaneous_cache.cpp index 3fef74aa55..8bae6e065a 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_simultaneous_cache.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_simultaneous_cache.cpp @@ -36,8 +36,8 @@ void ASYNCHRONOUS_DNS_SIMULTANEOUS_CACHE() &result_dns_failure, &result_exp_timeout); // Addresses were cached on last step, OK for all - TEST_ASSERT(result_ok == MBED_CONF_APP_DNS_SIMULT_QUERIES + 1); - TEST_ASSERT(result_no_mem == 0); - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(MBED_CONF_APP_DNS_SIMULT_QUERIES + 1, result_ok); + TEST_ASSERT_EQUAL(0, result_no_mem); + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } diff --git a/TESTS/netsocket/dns/asynchronous_dns_simultaneous_repeat.cpp b/TESTS/netsocket/dns/asynchronous_dns_simultaneous_repeat.cpp index 98c8dcb685..9759aa4872 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_simultaneous_repeat.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_simultaneous_repeat.cpp @@ -40,7 +40,7 @@ void ASYNCHRONOUS_DNS_SIMULTANEOUS_REPEAT() // For 1st round can fail to no memory, on other rounds some of the addresses are found from cache TEST_ASSERT(result_ok == MBED_CONF_APP_DNS_SIMULT_QUERIES || result_ok == MBED_CONF_APP_DNS_SIMULT_QUERIES + 1); TEST_ASSERT(result_no_mem == 1 || result_no_mem == 0); // last query fails for 1st round to no memory as expected - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } } diff --git a/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp b/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp index 37401df1e9..30b1ef537a 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp @@ -53,10 +53,10 @@ void ASYNCHRONOUS_DNS_TIMEOUTS() do_asynchronous_gethostbyname(dns_test_hosts, MBED_CONF_NSAPI_DNS_CACHE_SIZE, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == MBED_CONF_NSAPI_DNS_CACHE_SIZE); - TEST_ASSERT(result_no_mem == 0); - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(MBED_CONF_NSAPI_DNS_CACHE_SIZE, result_ok); + TEST_ASSERT_EQUAL(0, result_no_mem); + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); // Dispatch event queue Thread eventThread(osPriorityNormal, EXTERNAL_THREAD_SIZE); diff --git a/TESTS/netsocket/dns/main.cpp b/TESTS/netsocket/dns/main.cpp index ecc63ce40c..9c2fedf92d 100644 --- a/TESTS/netsocket/dns/main.cpp +++ b/TESTS/netsocket/dns/main.cpp @@ -122,7 +122,6 @@ void do_gethostbyname(const char hosts[][DNS_TEST_HOST_LEN], unsigned int op_cou SocketAddress address; nsapi_error_t err = net->gethostbyname(hosts[i], &address); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_NO_MEMORY || err == NSAPI_ERROR_DNS_FAILURE || err == NSAPI_ERROR_TIMEOUT); if (err == NSAPI_ERROR_OK) { (*exp_ok)++; printf("DNS: query \"%s\" => \"%s\"\n", @@ -136,6 +135,9 @@ void do_gethostbyname(const char hosts[][DNS_TEST_HOST_LEN], unsigned int op_cou } else if (err == NSAPI_ERROR_NO_MEMORY) { (*exp_no_mem)++; printf("DNS: query \"%s\" => no memory\n", hosts[i]); + } else { + printf("DNS: query \"%s\" => %d, unexpected answer\n", hosts[i], err); + TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_NO_MEMORY || err == NSAPI_ERROR_DNS_FAILURE || err == NSAPI_ERROR_TIMEOUT); } } } @@ -173,9 +175,7 @@ Case cases[] = { Case("ASYNCHRONOUS_DNS_EXTERNAL_EVENT_QUEUE", ASYNCHRONOUS_DNS_EXTERNAL_EVENT_QUEUE), Case("ASYNCHRONOUS_DNS_INVALID_HOST", ASYNCHRONOUS_DNS_INVALID_HOST), Case("ASYNCHRONOUS_DNS_TIMEOUTS", ASYNCHRONOUS_DNS_TIMEOUTS), -#ifdef MBED_EXTENDED_TESTS Case("ASYNCHRONOUS_DNS_SIMULTANEOUS_REPEAT", ASYNCHRONOUS_DNS_SIMULTANEOUS_REPEAT), -#endif Case("SYNCHRONOUS_DNS", SYNCHRONOUS_DNS), Case("SYNCHRONOUS_DNS_MULTIPLE", SYNCHRONOUS_DNS_MULTIPLE), Case("SYNCHRONOUS_DNS_INVALID", SYNCHRONOUS_DNS_INVALID), diff --git a/TESTS/netsocket/dns/synchronous_dns.cpp b/TESTS/netsocket/dns/synchronous_dns.cpp index a6be9e004d..93ef9fe857 100644 --- a/TESTS/netsocket/dns/synchronous_dns.cpp +++ b/TESTS/netsocket/dns/synchronous_dns.cpp @@ -34,8 +34,8 @@ void SYNCHRONOUS_DNS() { do_gethostbyname(dns_test_hosts, 1, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == 1); - TEST_ASSERT(result_no_mem == 0); - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(1, result_ok); + TEST_ASSERT_EQUAL(0, result_no_mem); + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } diff --git a/TESTS/netsocket/dns/synchronous_dns_invalid.cpp b/TESTS/netsocket/dns/synchronous_dns_invalid.cpp index 7623f24753..70f20fa3e1 100644 --- a/TESTS/netsocket/dns/synchronous_dns_invalid.cpp +++ b/TESTS/netsocket/dns/synchronous_dns_invalid.cpp @@ -53,8 +53,8 @@ void SYNCHRONOUS_DNS_INVALID() do_gethostbyname(dns_test_hosts_new, MBED_CONF_APP_DNS_TEST_HOSTS_NUM, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == expected_successes); - TEST_ASSERT(result_no_mem == 0); - TEST_ASSERT(result_dns_failure == expected_failures); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(expected_successes, result_ok); + TEST_ASSERT_EQUAL(0, result_no_mem); + TEST_ASSERT_EQUAL(expected_failures, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } diff --git a/TESTS/netsocket/dns/synchronous_dns_multiple.cpp b/TESTS/netsocket/dns/synchronous_dns_multiple.cpp index 28dcb513f8..ad2787393a 100644 --- a/TESTS/netsocket/dns/synchronous_dns_multiple.cpp +++ b/TESTS/netsocket/dns/synchronous_dns_multiple.cpp @@ -34,8 +34,8 @@ void SYNCHRONOUS_DNS_MULTIPLE() { do_gethostbyname(dns_test_hosts, MBED_CONF_APP_DNS_TEST_HOSTS_NUM, &result_ok, &result_no_mem, &result_dns_failure, &result_exp_timeout); - TEST_ASSERT(result_ok == MBED_CONF_APP_DNS_TEST_HOSTS_NUM); - TEST_ASSERT(result_no_mem == 0); - TEST_ASSERT(result_dns_failure == 0); - TEST_ASSERT(result_exp_timeout == 0); + TEST_ASSERT_EQUAL(MBED_CONF_APP_DNS_TEST_HOSTS_NUM, result_ok); + TEST_ASSERT_EQUAL(0, result_no_mem); + TEST_ASSERT_EQUAL(0, result_dns_failure); + TEST_ASSERT_EQUAL(0, result_exp_timeout); } diff --git a/TESTS/netsocket/tcp/main.cpp b/TESTS/netsocket/tcp/main.cpp index 8401c56f94..0f0810c51a 100644 --- a/TESTS/netsocket/tcp/main.cpp +++ b/TESTS/netsocket/tcp/main.cpp @@ -149,17 +149,26 @@ Case cases[] = { Case("TCPSOCKET_OPEN_CLOSE_REPEAT", TCPSOCKET_OPEN_CLOSE_REPEAT), Case("TCPSOCKET_OPEN_LIMIT", TCPSOCKET_OPEN_LIMIT), Case("TCPSOCKET_THREAD_PER_SOCKET_SAFETY", TCPSOCKET_THREAD_PER_SOCKET_SAFETY), -#ifdef MBED_EXTENDED_TESTS Case("TCPSOCKET_CONNECT_INVALID", TCPSOCKET_CONNECT_INVALID), Case("TCPSOCKET_ECHOTEST_BURST", TCPSOCKET_ECHOTEST_BURST), Case("TCPSOCKET_ECHOTEST_BURST_NONBLOCK", TCPSOCKET_ECHOTEST_BURST_NONBLOCK), + Case("TCPSOCKET_OPEN_DESTRUCT", TCPSOCKET_OPEN_DESTRUCT), + Case("TCPSOCKET_OPEN_TWICE", TCPSOCKET_OPEN_TWICE), + Case("TCPSOCKET_BIND_PORT", TCPSOCKET_BIND_PORT), + Case("TCPSOCKET_BIND_PORT_FAIL", TCPSOCKET_BIND_PORT_FAIL), + Case("TCPSOCKET_BIND_ADDRESS_PORT", TCPSOCKET_BIND_ADDRESS_PORT), + Case("TCPSOCKET_BIND_ADDRESS_NULL", TCPSOCKET_BIND_ADDRESS_NULL), + Case("TCPSOCKET_BIND_ADDRESS_INVALID", TCPSOCKET_BIND_ADDRESS_INVALID), + Case("TCPSOCKET_BIND_ADDRESS", TCPSOCKET_BIND_ADDRESS), + Case("TCPSOCKET_BIND_WRONG_TYPE", TCPSOCKET_BIND_WRONG_TYPE), + Case("TCPSOCKET_BIND_UNOPENED", TCPSOCKET_BIND_UNOPENED), + Case("TCPSOCKET_SETSOCKOPT_KEEPALIVE_VALID", TCPSOCKET_SETSOCKOPT_KEEPALIVE_VALID), Case("TCPSOCKET_RECV_100K", TCPSOCKET_RECV_100K), Case("TCPSOCKET_RECV_100K_NONBLOCK", TCPSOCKET_RECV_100K_NONBLOCK), Case("TCPSOCKET_RECV_TIMEOUT", TCPSOCKET_RECV_TIMEOUT), Case("TCPSOCKET_SEND_REPEAT", TCPSOCKET_SEND_REPEAT), Case("TCPSOCKET_SEND_TIMEOUT", TCPSOCKET_SEND_TIMEOUT), Case("TCPSOCKET_ENDPOINT_CLOSE", TCPSOCKET_ENDPOINT_CLOSE), -#endif }; Specification specification(greentea_setup, cases, greentea_teardown, greentea_continue_handlers); diff --git a/TESTS/netsocket/tcp/tcp_tests.h b/TESTS/netsocket/tcp/tcp_tests.h index 2d799883b8..8314a30da5 100644 --- a/TESTS/netsocket/tcp/tcp_tests.h +++ b/TESTS/netsocket/tcp/tcp_tests.h @@ -54,13 +54,24 @@ void TCPSOCKET_ECHOTEST_NONBLOCK(); void TCPSOCKET_ECHOTEST_BURST(); void TCPSOCKET_ECHOTEST_BURST_NONBLOCK(); void TCPSOCKET_ENDPOINT_CLOSE(); +void TCPSOCKET_OPEN_DESTRUCT(); void TCPSOCKET_OPEN_CLOSE_REPEAT(); void TCPSOCKET_OPEN_LIMIT(); +void TCPSOCKET_OPEN_TWICE(); +void TCPSOCKET_BIND_PORT(); +void TCPSOCKET_BIND_PORT_FAIL(); +void TCPSOCKET_BIND_ADDRESS_PORT(); +void TCPSOCKET_BIND_ADDRESS_NULL(); +void TCPSOCKET_BIND_ADDRESS_INVALID(); +void TCPSOCKET_BIND_ADDRESS(); +void TCPSOCKET_BIND_WRONG_TYPE(); +void TCPSOCKET_BIND_UNOPENED(); void TCPSOCKET_RECV_100K(); void TCPSOCKET_RECV_100K_NONBLOCK(); void TCPSOCKET_RECV_TIMEOUT(); void TCPSOCKET_SEND_REPEAT(); void TCPSOCKET_SEND_TIMEOUT(); void TCPSOCKET_THREAD_PER_SOCKET_SAFETY(); +void TCPSOCKET_SETSOCKOPT_KEEPALIVE_VALID(); #endif //TCP_TESTS_H diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_address.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_address.cpp new file mode 100644 index 0000000000..6101425b72 --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_address.cpp @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_ADDRESS() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + SocketAddress sockAddr = SocketAddress(get_interface()->get_ip_address(), 80); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(sockAddr)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_address_invalid.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_address_invalid.cpp new file mode 100644 index 0000000000..971499d991 --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_address_invalid.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_ADDRESS_INVALID() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock->bind("190.2.3.4", 1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_address_null.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_address_null.cpp new file mode 100644 index 0000000000..e31d757f7f --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_address_null.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_ADDRESS_NULL() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(NULL, 1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_address_port.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_address_port.cpp new file mode 100644 index 0000000000..25a7c52ffc --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_address_port.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_ADDRESS_PORT() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(get_interface()->get_ip_address(), 80)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_port.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_port.cpp new file mode 100644 index 0000000000..862879cf56 --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_port.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_PORT() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_port_fail.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_port_fail.cpp new file mode 100644 index 0000000000..96fee05e37 --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_port_fail.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_PORT_FAIL() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(1024)); + + TCPSocket *sock2 = new TCPSocket; + if (!sock2) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock2->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock2->bind(1024)); + + delete sock; + delete sock2; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_unopened.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_unopened.cpp new file mode 100644 index 0000000000..c15743160f --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_unopened.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_UNOPENED() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_NO_SOCKET, sock->bind(1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp b/TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp new file mode 100644 index 0000000000..b22b688043 --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_bind_wrong_type.cpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_BIND_WRONG_TYPE() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + char addr_bytes[16] = {0xfe, 0x80, 0xff, 0x1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + SocketAddress sockAddr = SocketAddress(addr_bytes, NSAPI_IPv4, 80); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock->bind(sockAddr)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_open_destruct.cpp b/TESTS/netsocket/tcp/tcpsocket_open_destruct.cpp new file mode 100644 index 0000000000..d82c4ac9cc --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_open_destruct.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_OPEN_DESTRUCT() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + + for (int i = 0; i < 1000; i++) { + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + delete sock; + } +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_open_twice.cpp b/TESTS/netsocket/tcp/tcpsocket_open_twice.cpp new file mode 100644 index 0000000000..4edb4f3209 --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_open_twice.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "tcp_tests.h" +#include "TCPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void TCPSOCKET_OPEN_TWICE() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif + TCPSocket *sock = new TCPSocket; + if (!sock) { + TEST_FAIL(); + } + + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock->open(get_interface())); + + delete sock; +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, tcp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/tcp/tcpsocket_setsockopt_keepalive_valid.cpp b/TESTS/netsocket/tcp/tcpsocket_setsockopt_keepalive_valid.cpp new file mode 100644 index 0000000000..62ceaa315d --- /dev/null +++ b/TESTS/netsocket/tcp/tcpsocket_setsockopt_keepalive_valid.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "TCPSocket.h" +#include "greentea-client/test_env.h" +#include "unity/unity.h" +#include "utest.h" +#include "tcp_tests.h" + +using namespace utest::v1; + +void TCPSOCKET_SETSOCKOPT_KEEPALIVE_VALID() +{ + TCPSocket sock; + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(get_interface())); + int32_t seconds = 7200; + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.setsockopt(NSAPI_SOCKET, NSAPI_KEEPALIVE, &seconds, sizeof(int))); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.connect(MBED_CONF_APP_ECHO_SERVER_ADDR, 9)); + // LWIP stack does not support getsockopt so the part below is commented out + // int32_t optval; + // unsigned int optlen; + // TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.getsockopt(NSAPI_SOCKET, NSAPI_KEEPALIVE, &optval, &optlen)); + // TEST_ASSERT_EQUAL(optlen, sizeof(seconds)); + // TEST_ASSERT_EQUAL(optval, seconds); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.close()); +} diff --git a/TESTS/netsocket/udp/main.cpp b/TESTS/netsocket/udp/main.cpp index 234ce670f8..18471f7ef9 100644 --- a/TESTS/netsocket/udp/main.cpp +++ b/TESTS/netsocket/udp/main.cpp @@ -102,17 +102,26 @@ void greentea_teardown(const size_t passed, const size_t failed, const failure_t } Case cases[] = { + Case("UDPSOCKET_ECHOTEST", UDPSOCKET_ECHOTEST), Case("UDPSOCKET_ECHOTEST_NONBLOCK", UDPSOCKET_ECHOTEST_NONBLOCK), Case("UDPSOCKET_OPEN_CLOSE_REPEAT", UDPSOCKET_OPEN_CLOSE_REPEAT), Case("UDPSOCKET_OPEN_LIMIT", UDPSOCKET_OPEN_LIMIT), Case("UDPSOCKET_SENDTO_TIMEOUT", UDPSOCKET_SENDTO_TIMEOUT), -#ifdef MBED_EXTENDED_TESTS + Case("UDPSOCKET_OPEN_DESTRUCT", UDPSOCKET_OPEN_DESTRUCT), + Case("UDPSOCKET_OPEN_TWICE", UDPSOCKET_OPEN_TWICE), + Case("UDPSOCKET_BIND_PORT", UDPSOCKET_BIND_PORT), + Case("UDPSOCKET_BIND_PORT_FAIL", UDPSOCKET_BIND_PORT_FAIL), + Case("UDPSOCKET_BIND_ADDRESS_PORT", UDPSOCKET_BIND_ADDRESS_PORT), + Case("UDPSOCKET_BIND_ADDRESS_NULL", UDPSOCKET_BIND_ADDRESS_NULL), + Case("UDPSOCKET_BIND_ADDRESS_INVALID", UDPSOCKET_BIND_ADDRESS_INVALID), + Case("UDPSOCKET_BIND_ADDRESS", UDPSOCKET_BIND_ADDRESS), + Case("UDPSOCKET_BIND_WRONG_TYPE", UDPSOCKET_BIND_WRONG_TYPE), + Case("UDPSOCKET_BIND_UNOPENED", UDPSOCKET_BIND_UNOPENED), Case("UDPSOCKET_SENDTO_INVALID", UDPSOCKET_SENDTO_INVALID), Case("UDPSOCKET_ECHOTEST", UDPSOCKET_ECHOTEST), Case("UDPSOCKET_ECHOTEST_BURST", UDPSOCKET_ECHOTEST_BURST), Case("UDPSOCKET_ECHOTEST_BURST_NONBLOCK", UDPSOCKET_ECHOTEST_BURST_NONBLOCK), Case("UDPSOCKET_SENDTO_REPEAT", UDPSOCKET_SENDTO_REPEAT), -#endif }; Specification specification(greentea_setup, cases, greentea_teardown, greentea_continue_handlers); diff --git a/TESTS/netsocket/udp/udp_tests.h b/TESTS/netsocket/udp/udp_tests.h index a265688877..b740ada298 100644 --- a/TESTS/netsocket/udp/udp_tests.h +++ b/TESTS/netsocket/udp/udp_tests.h @@ -35,7 +35,17 @@ void UDPSOCKET_ECHOTEST_NONBLOCK(); void UDPSOCKET_ECHOTEST_BURST(); void UDPSOCKET_ECHOTEST_BURST_NONBLOCK(); void UDPSOCKET_OPEN_CLOSE_REPEAT(); +void UDPSOCKET_OPEN_DESTRUCT(); void UDPSOCKET_OPEN_LIMIT(); +void UDPSOCKET_OPEN_TWICE(); +void UDPSOCKET_BIND_PORT(); +void UDPSOCKET_BIND_PORT_FAIL(); +void UDPSOCKET_BIND_ADDRESS_PORT(); +void UDPSOCKET_BIND_ADDRESS_NULL(); +void UDPSOCKET_BIND_ADDRESS_INVALID(); +void UDPSOCKET_BIND_ADDRESS(); +void UDPSOCKET_BIND_WRONG_TYPE(); +void UDPSOCKET_BIND_UNOPENED(); void UDPSOCKET_RECV_TIMEOUT(); void UDPSOCKET_SENDTO_INVALID(); void UDPSOCKET_SENDTO_REPEAT(); diff --git a/TESTS/netsocket/udp/udpsocket_bind_address.cpp b/TESTS/netsocket/udp/udpsocket_bind_address.cpp new file mode 100644 index 0000000000..139c98ea51 --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_address.cpp @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_ADDRESS() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + SocketAddress sockAddr = SocketAddress(get_interface()->get_ip_address(), 80); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(sockAddr)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_bind_address_invalid.cpp b/TESTS/netsocket/udp/udpsocket_bind_address_invalid.cpp new file mode 100644 index 0000000000..33a29f12d2 --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_address_invalid.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_ADDRESS_INVALID() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock->bind("190.2.3.4", 1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_bind_address_null.cpp b/TESTS/netsocket/udp/udpsocket_bind_address_null.cpp new file mode 100644 index 0000000000..addacb1126 --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_address_null.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_ADDRESS_NULL() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(NULL, 1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_bind_address_port.cpp b/TESTS/netsocket/udp/udpsocket_bind_address_port.cpp new file mode 100644 index 0000000000..633f887c31 --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_address_port.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_ADDRESS_PORT() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(get_interface()->get_ip_address(), 80)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_bind_port.cpp b/TESTS/netsocket/udp/udpsocket_bind_port.cpp new file mode 100644 index 0000000000..fbe98e45ee --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_port.cpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_PORT() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_bind_port_fail.cpp b/TESTS/netsocket/udp/udpsocket_bind_port_fail.cpp new file mode 100644 index 0000000000..81ebfda069 --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_port_fail.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_PORT_FAIL() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->bind(1024)); + + UDPSocket *sock2 = new UDPSocket; + if (!sock2) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock2->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock2->bind(1024)); + + delete sock; + delete sock2; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_bind_unopened.cpp b/TESTS/netsocket/udp/udpsocket_bind_unopened.cpp new file mode 100644 index 0000000000..aca434c7e4 --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_unopened.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_UNOPENED() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_NO_SOCKET, sock->bind(1024)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp b/TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp new file mode 100644 index 0000000000..11836666e9 --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_bind_wrong_type.cpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_BIND_WRONG_TYPE() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + char addr_bytes[16] = {0xfe, 0x80, 0xff, 0x1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + SocketAddress sockAddr = SocketAddress(addr_bytes, NSAPI_IPv4, 80); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock->bind(sockAddr)); + + delete sock; + +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_open_destruct.cpp b/TESTS/netsocket/udp/udpsocket_open_destruct.cpp new file mode 100644 index 0000000000..7c79951d0d --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_open_destruct.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_OPEN_DESTRUCT() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + + for (int i = 0; i < 1000; i++) { + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + delete sock; + } +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/netsocket/udp/udpsocket_open_twice.cpp b/TESTS/netsocket/udp/udpsocket_open_twice.cpp new file mode 100644 index 0000000000..fe8f6df95e --- /dev/null +++ b/TESTS/netsocket/udp/udpsocket_open_twice.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "greentea-client/test_env.h" +#include "mbed.h" +#include "udp_tests.h" +#include "UDPSocket.h" +#include "unity/unity.h" +#include "utest.h" + +using namespace utest::v1; + +void UDPSOCKET_OPEN_TWICE() +{ +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + int count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif + UDPSocket *sock = new UDPSocket; + if (!sock) { + TEST_FAIL(); + } + + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock->open(get_interface())); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, sock->open(get_interface())); + + delete sock; +#if MBED_CONF_NSAPI_SOCKET_STATS_ENABLE + count = fetch_stats(); + for (int j = 0; j < count; j++) { + TEST_ASSERT_EQUAL(SOCK_CLOSED, udp_stats[j].state); + } +#endif +} diff --git a/TESTS/network/wifi/main.cpp b/TESTS/network/wifi/main.cpp index 7043e00b42..aeb139137a 100644 --- a/TESTS/network/wifi/main.cpp +++ b/TESTS/network/wifi/main.cpp @@ -62,32 +62,24 @@ Case cases[] = { Case("WIFI-CONNECT-NOCREDENTIALS", wifi_connect_nocredentials), Case("WIFI-SET-CREDENTIAL", wifi_set_credential), Case("WIFI-SET-CHANNEL", wifi_set_channel), + Case("WIFI-CONNECT-PARAMS-NULL", wifi_connect_params_null), + Case("WIFI-SCAN-NULL", wifi_scan_null), +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) || defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) + Case("WIFI-SCAN", wifi_scan), +#endif #if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) Case("WIFI-GET-RSSI", wifi_get_rssi), -#endif - Case("WIFI-CONNECT-PARAMS-NULL", wifi_connect_params_null), -#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) Case("WIFI-CONNECT-PARAMS-VALID-UNSECURE", wifi_connect_params_valid_unsecure), + Case("WIFI-CONNECT", wifi_connect), + Case("WIFI-CONNECT-DISCONNECT-REPEAT", wifi_connect_disconnect_repeat), #endif #if defined(MBED_CONF_APP_WIFI_SECURE_SSID) Case("WIFI-CONNECT-PARAMS-VALID-SECURE", wifi_connect_params_valid_secure), Case("WIFI-CONNECT-PARAMS-CHANNEL", wifi_connect_params_channel), Case("WIFI-CONNECT-PARAMS-CHANNEL-FAIL", wifi_connect_params_channel_fail), -#endif -#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) - Case("WIFI-CONNECT", wifi_connect), -#endif -#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) Case("WIFI-CONNECT-SECURE", wifi_connect_secure), Case("WIFI-CONNECT-SECURE-FAIL", wifi_connect_secure_fail), #endif -#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) - Case("WIFI-CONNECT-DISCONNECT-REPEAT", wifi_connect_disconnect_repeat), -#endif - Case("WIFI-SCAN-NULL", wifi_scan_null), -#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) && defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) - Case("WIFI-SCAN", wifi_scan), -#endif }; Specification specification(test_setup, cases, greentea_continue_handlers); diff --git a/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp index e23980e18a..e70546c486 100644 --- a/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp +++ b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp @@ -31,13 +31,13 @@ void wifi_connect_disconnect_repeat(void) nsapi_error_t error; error = wifi->set_credentials(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); for (int i = 0; i < 10; i++) { error = wifi->connect(); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = wifi->disconnect(); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); } } diff --git a/TESTS/network/wifi/wifi_connect_nocredentials.cpp b/TESTS/network/wifi/wifi_connect_nocredentials.cpp index 2fe2b16261..73e8c015fc 100644 --- a/TESTS/network/wifi/wifi_connect_nocredentials.cpp +++ b/TESTS/network/wifi/wifi_connect_nocredentials.cpp @@ -30,5 +30,5 @@ void wifi_connect_nocredentials(void) error_connect = wifi->connect(); error_disconnect = wifi->disconnect(); TEST_ASSERT(error_connect == NSAPI_ERROR_NO_SSID || error_connect == NSAPI_ERROR_PARAMETER); - TEST_ASSERT(error_disconnect == NSAPI_ERROR_NO_CONNECTION); + TEST_ASSERT_EQUAL(NSAPI_ERROR_NO_CONNECTION, error_disconnect); } diff --git a/TESTS/network/wifi/wifi_connect_params_null.cpp b/TESTS/network/wifi/wifi_connect_params_null.cpp index 21bb8cc96e..0c2350dfce 100644 --- a/TESTS/network/wifi/wifi_connect_params_null.cpp +++ b/TESTS/network/wifi/wifi_connect_params_null.cpp @@ -29,8 +29,8 @@ void wifi_connect_params_null(void) WiFiInterface *wifi = get_interface(); error = wifi->connect(NULL, NULL); wifi->disconnect(); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = wifi->connect("", ""); wifi->disconnect(); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); } diff --git a/TESTS/network/wifi/wifi_scan.cpp b/TESTS/network/wifi/wifi_scan.cpp index 92130ad3fd..202a33181c 100644 --- a/TESTS/network/wifi/wifi_scan.cpp +++ b/TESTS/network/wifi/wifi_scan.cpp @@ -24,8 +24,6 @@ using namespace utest::v1; -#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) && defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) - void wifi_scan(void) { WiFiInterface *wifi = get_interface(); @@ -33,7 +31,7 @@ void wifi_scan(void) WiFiAccessPoint ap[MBED_CONF_APP_MAX_SCAN_SIZE]; int size = wifi->scan(ap, MBED_CONF_APP_MAX_SCAN_SIZE); - TEST_ASSERT(size >= 2); + TEST_ASSERT(size >= 1); bool secure_found = false; bool unsecure_found = false; @@ -49,17 +47,19 @@ void wifi_scan(void) nsapi_security_t security = ap[i].get_security(); int8_t rssi = ap[i].get_rssi(); TEST_ASSERT_INT8_WITHIN(-10, -100, rssi); +#if defined(MBED_CONF_APP_WIFI_SECURE_SSID) if (strcmp(MBED_CONF_APP_WIFI_SECURE_SSID, ssid) == 0) { secure_found = true; TEST_ASSERT_EQUAL_INT(get_security(), security); } +#endif +#if defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) if (strcmp(MBED_CONF_APP_WIFI_UNSECURE_SSID, ssid) == 0) { unsecure_found = true; TEST_ASSERT_EQUAL_INT(NSAPI_SECURITY_NONE, security); } +#endif } // Finding one SSID is enough TEST_ASSERT_TRUE(secure_found || unsecure_found); } - -#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) && defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) diff --git a/TESTS/network/wifi/wifi_scan_null.cpp b/TESTS/network/wifi/wifi_scan_null.cpp index 784d91b896..fd5116ac7f 100644 --- a/TESTS/network/wifi/wifi_scan_null.cpp +++ b/TESTS/network/wifi/wifi_scan_null.cpp @@ -26,6 +26,6 @@ using namespace utest::v1; void wifi_scan_null(void) { WiFiInterface *wifi = get_interface(); - TEST_ASSERT(wifi->scan(NULL, 0) >= 2); + TEST_ASSERT(wifi->scan(NULL, 0) >= 1); } diff --git a/TESTS/network/wifi/wifi_set_channel.cpp b/TESTS/network/wifi/wifi_set_channel.cpp index 5f609e0848..f9f35f1d00 100644 --- a/TESTS/network/wifi/wifi_set_channel.cpp +++ b/TESTS/network/wifi/wifi_set_channel.cpp @@ -51,22 +51,22 @@ void wifi_set_channel(void) if (is_2Ghz) { error = wifi->set_channel(0); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = wifi->set_channel(1); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = wifi->set_channel(13); TEST_ASSERT(error == NSAPI_ERROR_OK || error == NSAPI_ERROR_PARAMETER); error = wifi->set_channel(15); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); } if (is_5Ghz) { error = wifi->set_channel(30); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = wifi->set_channel(36); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = wifi->set_channel(169); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); } wifi->set_channel(0); diff --git a/TESTS/network/wifi/wifi_set_credential.cpp b/TESTS/network/wifi/wifi_set_credential.cpp index cf659a81d4..d2c0ba6613 100644 --- a/TESTS/network/wifi/wifi_set_credential.cpp +++ b/TESTS/network/wifi/wifi_set_credential.cpp @@ -29,31 +29,31 @@ void wifi_set_credential(void) nsapi_error_t error; error = iface->set_credentials(NULL, NULL, NSAPI_SECURITY_NONE); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = iface->set_credentials("", "", NSAPI_SECURITY_NONE); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_NONE); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = iface->set_credentials("OK", "", NSAPI_SECURITY_NONE); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_WEP); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = iface->set_credentials("OK", "", NSAPI_SECURITY_WEP); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_WPA_WPA2); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = iface->set_credentials("OK", "", NSAPI_SECURITY_WPA_WPA2); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_NONE); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WEP); TEST_ASSERT((error == NSAPI_ERROR_OK) || (error == NSAPI_ERROR_UNSUPPORTED)); @@ -65,11 +65,11 @@ void wifi_set_credential(void) TEST_ASSERT((error == NSAPI_ERROR_OK) || (error == NSAPI_ERROR_UNSUPPORTED)); error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA_WPA2); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = iface->set_credentials("OK", "kUjd0PHHeAqaDoyfcDDEOvbyiVbYMpUHDukGoR6EJZnO5iLzWsfwiM9JQqOngni", get_security()); - TEST_ASSERT(error == NSAPI_ERROR_OK); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); error = iface->set_credentials("OK", "kUjd0PHHeAqaDoyfcDDEOvbyiVbYMpUHDukGoR6EJZnO5iLzWsfwiM9JQqOngni8", get_security()); - TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); } diff --git a/TESTS/nfc/eeprom/main.cpp b/TESTS/nfc/eeprom/main.cpp index 593e42c602..4f25ce7483 100644 --- a/TESTS/nfc/eeprom/main.cpp +++ b/TESTS/nfc/eeprom/main.cpp @@ -66,7 +66,7 @@ typedef enum { TERMINATE = 0xFF00 } TestCommand_t; -/* We group the command based on their fist byte to simplify step checking. +/* We group the command based on their first byte to simplify step checking. * Individual conditions of a step are checked in the event so this doesn't * sacrifice any correctness checking */ const size_t TEST_COMMAND_GROUP_MASK = 0xFF00; @@ -359,7 +359,7 @@ public: _driver->write_bytes(_address, _operation_data, _operation_size); break; case ERASE_BYTES: - _driver->erase_bytes(_address, 4); + _driver->erase_bytes(_address, _operation_size); break; case READ_SIZE: _driver->read_size(); diff --git a/TESTS/psa/crypto_init/COMPONENT_SPE/psa_setup.c b/TESTS/psa/crypto_init/COMPONENT_SPE/psa_setup.c deleted file mode 100644 index 95398b17b1..0000000000 --- a/TESTS/psa/crypto_init/COMPONENT_SPE/psa_setup.c +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright (c) 2017-2018 ARM Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*********************************************************************************************************************** - * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - * THIS FILE IS AN AUTO-GENERATED FILE - DO NOT MODIFY IT. - * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - * Template Version 1.0 - * Generated by tools/spm/generate_partition_code.py Version 1.0 - **********************************************************************************************************************/ - -#include "spm_panic.h" -#include "spm_internal.h" -#include "handles_manager.h" -#include "cmsis.h" -#include "psa_crypto_srv_partition.h" -#include "psa_its_partition.h" - -extern const uint32_t crypto_srv_external_sids[4]; - -spm_partition_t g_partitions[2] = { - { - .partition_id = CRYPTO_SRV_ID, - .thread_id = 0, - .flags_rot_srv = CRYPTO_SRV_WAIT_ANY_SID_MSK, - .flags_interrupts = 0, - .rot_services = NULL, - .rot_services_count = CRYPTO_SRV_ROT_SRV_COUNT, - .extern_sids = crypto_srv_external_sids, - .extern_sids_count = CRYPTO_SRV_EXT_ROT_SRV_COUNT, - .irq_mapper = NULL, - }, - { - .partition_id = ITS_ID, - .thread_id = 0, - .flags_rot_srv = ITS_WAIT_ANY_SID_MSK, - .flags_interrupts = 0, - .rot_services = NULL, - .rot_services_count = ITS_ROT_SRV_COUNT, - .extern_sids = NULL, - .extern_sids_count = ITS_EXT_ROT_SRV_COUNT, - .irq_mapper = NULL, - }, -}; - -/* Check all the defined memory regions for overlapping. */ - -/* A list of all the memory regions. */ -const mem_region_t *mem_regions = NULL; - -const uint32_t mem_region_count = 0; - -// forward declaration of partition initializers -void crypto_srv_init(spm_partition_t *partition); -void its_init(spm_partition_t *partition); - -uint32_t init_partitions(spm_partition_t **partitions) -{ - if (NULL == partitions) { - SPM_PANIC("partitions is NULL!\n"); - } - - crypto_srv_init(&(g_partitions[0])); - its_init(&(g_partitions[1])); - - *partitions = g_partitions; - return 2; -} - diff --git a/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.cpp b/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.cpp index ceef2f6a39..08117b7482 100644 --- a/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.cpp +++ b/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.cpp @@ -477,6 +477,7 @@ void mac_data_confirm_handler(const mac_api_t *api, const mcps_data_conf_t *data if (data->status == expected_statuses.data_conf) { cmd_ready(CMDLINE_RETCODE_SUCCESS); } else { + cmd_printf("CMD failed, status: %hhu (%s)\n", data->status, mlme_status_string(data->status)); cmd_ready(CMDLINE_RETCODE_FAIL); } } @@ -501,12 +502,14 @@ void mac_data_indication_handler(const mac_api_t *api, const mcps_data_ind_t *da } if (data->msdu_ptr && expected_statuses.data_ind) { if (data->msduLength != expected_statuses.data_ind_len) { + cmd_printf("Bad recv length %d != %d!\n", data->msduLength, expected_statuses.data_ind_len); return; } if (strncmp((const char *)data->msdu_ptr, (const char *)expected_statuses.data_ind, expected_statuses.data_ind_len) == 0) { ++data_count; + cmd_printf("Data count %d\n", data_count); } else { - tr_warn("Received unexpected data!"); + cmd_printf("Received unexpected data!\n"); } } } @@ -521,6 +524,7 @@ void mac_purge_confirm_handler(const mac_api_t *api, mcps_purge_conf_t *data) if (data->status == expected_statuses.purge_conf) { cmd_ready(CMDLINE_RETCODE_SUCCESS); } else { + cmd_printf("CMD failed, status: %hhu (%s)\n", data->status, mlme_status_string(data->status)); cmd_ready(CMDLINE_RETCODE_FAIL); } } @@ -547,6 +551,7 @@ void mac_mlme_confirm_handler(const mac_api_t *api, mlme_primitive id, const voi if (get_data->status == expected_statuses.get_conf) { cmd_ready(CMDLINE_RETCODE_SUCCESS); } else { + cmd_printf("CMD failed, status: %hhu (%s)\n", get_data->status, mlme_status_string(get_data->status)); cmd_ready(CMDLINE_RETCODE_FAIL); } break; @@ -585,6 +590,7 @@ void mac_mlme_confirm_handler(const mac_api_t *api, mlme_primitive id, const voi if (scan_data->status == expected_statuses.scan_conf || scan_data->status == MLME_LIMIT_REACHED) { cmd_ready(CMDLINE_RETCODE_SUCCESS); } else { + cmd_printf("CMD failed, status: %hhu (%s)\n", scan_data->status, mlme_status_string(scan_data->status)); cmd_ready(CMDLINE_RETCODE_FAIL); } break; @@ -599,24 +605,28 @@ void mac_mlme_confirm_handler(const mac_api_t *api, mlme_primitive id, const voi mlme_poll_conf_t *poll_data = (mlme_poll_conf_t *)data; cmd_printf("MLME-POLL.confirm\n"); if (!silent_mode) { - cmd_printf("status: %hhu (%s)\n", poll_data->status, mlme_status_string(poll_data->status)); - cmd_printf("data_count %u\n", data_count); + cmd_printf("status: %hhu (%s)\n", poll_data->status, mlme_status_string(poll_data->status)); + cmd_printf("expected status: %hhu (%s)\n", expected_statuses.poll_conf, mlme_status_string(expected_statuses.poll_conf)); + cmd_printf("data_count %u\n", data_count); } if (expected_statuses.poll_conf == MLME_SUCCESS) { if (data_count == 1 && poll_data->status == MLME_SUCCESS) { cmd_ready(CMDLINE_RETCODE_SUCCESS); } else { + cmd_printf("CMD failed, data_count = %u, status:%hhu\n", data_count, poll_data->status); cmd_ready(CMDLINE_RETCODE_FAIL); } } else if (expected_statuses.poll_conf == poll_data->status) { cmd_ready(CMDLINE_RETCODE_SUCCESS); } else { + cmd_printf("CMD failed, data_count = %u, status:%hhu, expected ret:%hhu\n", data_count, poll_data->status, expected_statuses.poll_conf); cmd_ready(CMDLINE_RETCODE_FAIL); } break; } default: { cmd_ready(CMDLINE_RETCODE_COMMAND_NOT_IMPLEMENTED); + cmd_printf("CMD failed, not implemented\n"); break; } } diff --git a/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.h b/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.h index a57e97fc31..a15d97faf6 100644 --- a/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.h +++ b/TEST_APPS/device/nanostack_mac_tester/source/mac_commands.h @@ -28,7 +28,7 @@ #include "mac_mcps.h" #include "mac_common_defines.h" #include "mac_filter_api.h" -#include "util.h" +#include "mac_tester_util.h" #define LOOKUP_DESCRIPTOR_TABLE_SIZE 2 #define DEVICE_DESCRIPTOR_TABLE_SIZE 2 diff --git a/TEST_APPS/device/nanostack_mac_tester/source/util.cpp b/TEST_APPS/device/nanostack_mac_tester/source/mac_tester_util.cpp similarity index 99% rename from TEST_APPS/device/nanostack_mac_tester/source/util.cpp rename to TEST_APPS/device/nanostack_mac_tester/source/mac_tester_util.cpp index 7a914a7edb..15fec17bef 100644 --- a/TEST_APPS/device/nanostack_mac_tester/source/util.cpp +++ b/TEST_APPS/device/nanostack_mac_tester/source/mac_tester_util.cpp @@ -14,7 +14,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include "util.h" +#include "mac_tester_util.h" int string_to_bytes(const char *str, uint8_t *buf, int bytes) { diff --git a/TEST_APPS/device/nanostack_mac_tester/source/util.h b/TEST_APPS/device/nanostack_mac_tester/source/mac_tester_util.h similarity index 100% rename from TEST_APPS/device/nanostack_mac_tester/source/util.h rename to TEST_APPS/device/nanostack_mac_tester/source/mac_tester_util.h diff --git a/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py b/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py index 28cada4f69..3bac432fbf 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/ED_scan.py @@ -18,12 +18,13 @@ limitations under the License. import threading import os,sys from icetea_lib.bench import Bench +from icetea_lib.TestStepError import TestStepFail class Testcase(Bench): def __init__(self): Bench.__init__(self, name = "ED_scan", title = "ED scan test", - status = "development", + status = "released", type = "smoke", subtype = "", execution = { @@ -54,9 +55,6 @@ class Testcase(Bench): def setUp(self): self.channel = 11 - self.command("First", "addr --64-bit 01:02:03:00:00:00:00:01") - self.command("Second", "addr --64-bit 01:02:03:00:00:00:00:02") - self.command("Third", "addr --64-bit 01:02:03:00:00:00:00:03") def spam_channel(self, event): while not event.wait(0.1): @@ -71,8 +69,16 @@ class Testcase(Bench): res = res | ( 1 << ch) return hex(res) - def case(self): + def do_test_iteration(self): self.lock_th = threading.Lock() + self.command("First", "mlme-reset") + self.command("Second", "mlme-reset") + self.command("Third", "mlme-reset") + + self.command("First", "addr --64-bit 01:02:03:00:00:00:00:01") + self.command("Second", "addr --64-bit 01:02:03:00:00:00:00:02") + self.command("Third", "addr --64-bit 01:02:03:00:00:00:00:03") + self.payload = "01234567890123456789012345678901234567890123456789" # Start PAN coordinator @@ -105,6 +111,20 @@ class Testcase(Bench): # Energy detection analysis self.command("Second", "analyze-ed --channel {} --above 100".format(self.channel)) + def case(self): + # Try tests few times because of potential RF failures + loop = 0 + while loop < 5: + try: + self.do_test_iteration() + break + except TestStepFail: + self.logger.info("Warning, iteration failed #" + str(loop+1)) + loop = loop + 1 + self.delay(5) + else: + raise TestStepFail("Too many failed iterations!") + def tearDown(self): self.command("First", "silent-mode off") self.command("Third", "silent-mode off") @@ -112,3 +132,4 @@ class Testcase(Bench): self.th.join() del self.th self.reset_dut() + diff --git a/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py b/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py index 217d876c57..ffda6107ab 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/address_read_and_write.py @@ -17,12 +17,13 @@ limitations under the License. import os,sys from icetea_lib.bench import Bench +from icetea_lib.TestStepError import TestStepFail class Testcase(Bench): def __init__(self): Bench.__init__(self, name = "address_read_and_write", title = "MAC address and PAN id read/write test", - status = "development", + status = "released", type = "smoke", subtype = "", execution = { @@ -52,7 +53,8 @@ class Testcase(Bench): def setUp(self): pass - def case(self): + def do_test_iteration(self): + self.command("First", "mlme-reset") self.command("First", "addr") self.command("First", "addr --64-bit 01:02:03:00:00:00:00:01") self.command("First", "addr --16-bit 0xABCD") @@ -61,5 +63,20 @@ class Testcase(Bench): self.command("First", "addr") self.verify_trace(1, "MAC64: 01:02:03:00:00:00:00:01") + def case(self): + # Try tests few times because of potential RF failures + loop = 0 + while loop < 5: + try: + self.do_test_iteration() + break + except TestStepFail: + self.logger.info("Warning, iteration failed #" + str(loop+1)) + loop = loop + 1 + self.delay(5) + else: + raise TestStepFail("Too many failed iterations!") + def tearDown(self): self.reset_dut() + diff --git a/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py b/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py index 9f861cd9be..eb52328fbe 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/create_and_join_PAN.py @@ -17,12 +17,13 @@ limitations under the License. import os,sys from icetea_lib.bench import Bench +from icetea_lib.TestStepError import TestStepFail class Testcase(Bench): def __init__(self): Bench.__init__(self, name = "create_and_join_PAN", title = "Create a PAN and have a device join it", - status = "development", + status = "released", type = "smoke", subtype = "", execution = { @@ -60,12 +61,16 @@ class Testcase(Bench): def setUp(self): self.channel = 11 - def case(self): + def do_test_iteration(self): + self.command("First", "mlme-reset") + self.command("Second", "mlme-reset") + self.command("Third", "mlme-reset") + # Beacon payload self.command("First", "mlme-set --attr 0x45 --value_ascii mac-tester --value_size 10") # Beacon payload length self.command("First", "mlme-set --attr 0x46 --value_uint8 10 --value_size 1") - + self.command("Second", "mlme-set --attr 0x45 --value_ascii second-mac-tester --value_size 17") self.command("Second", "mlme-set --attr 0x46 --value_uint8 17 --value_size 1") @@ -84,5 +89,19 @@ class Testcase(Bench): self.command("Third", "find-beacon --data mac-tester") self.command("Third", "find-beacon --data second-mac-tester") + def case(self): + # Try tests few times because of potential RF failures + loop = 0 + while loop < 5: + try: + self.do_test_iteration() + break + except TestStepFail: + self.logger.info("Warning, iteration failed #" + str(loop+1)) + loop = loop + 1 + self.delay(5) + else: + raise TestStepFail("Too many failed iterations!") + def tearDown(self): self.reset_dut() diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_data.py b/TEST_APPS/testcases/nanostack_mac_tester/send_data.py index 559f49c7ef..a2da5d0840 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_data.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_data.py @@ -17,12 +17,13 @@ limitations under the License. import os,sys from icetea_lib.bench import Bench +from icetea_lib.TestStepError import TestStepFail class Testcase(Bench): def __init__(self): Bench.__init__(self, name = "send_data", title = "Simple data transmission test", - status = "development", + status = "released", type = "smoke", subtype = "", execution = { @@ -52,10 +53,14 @@ class Testcase(Bench): def setUp(self): self.channel = 11 + + def do_test_iteration(self): + self.command("First", "mlme-reset") + self.command("Second", "mlme-reset") + self.command("First", "addr --64-bit 01:02:03:00:00:00:00:01") self.command("Second", "addr --64-bit 01:02:03:00:00:00:00:02") - def case(self): # Start PAN coordinator self.command("First", "start --pan_coordinator true --logical_channel {}".format(self.channel)) # Start PAN beacon @@ -65,5 +70,20 @@ class Testcase(Bench): self.command("First", "data --dst_addr 01:02:03:00:00:00:00:02 --msdu_length 5 --msdu abcde") self.command("Second", "data --dst_addr 01:02:03:00:00:00:00:01 --msdu_length 5 --msdu 12345") + def case(self): + # Try tests few times because of potential RF failures + loop = 0 + while loop < 5: + try: + self.do_test_iteration() + break + except TestStepFail: + self.logger.info("Warning, iteration failed #" + str(loop+1)) + loop = loop + 1 + self.delay(5) + else: + raise TestStepFail("Too many failed iterations!") + def tearDown(self): self.reset_dut() + diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py b/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py index 9836db91ee..540c1365cf 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_data_indirect.py @@ -17,12 +17,13 @@ limitations under the License. import os,sys from icetea_lib.bench import Bench +from icetea_lib.TestStepError import TestStepFail class Testcase(Bench): def __init__(self): Bench.__init__(self, name = "send_data_indirect", title = "Indirect data transmission test", - status = "development", + status = "released", type = "smoke", subtype = "", execution = { @@ -53,11 +54,17 @@ class Testcase(Bench): def setUp(self): self.channel = 11 + + def do_test_iteration(self): + self.channel = 11 + self.command("First", "mlme-reset") + self.command("Second", "mlme-reset") + self.command("Third", "mlme-reset") + self.command("First", "addr --64-bit 01:02:03:00:00:00:00:01") self.command("Second", "addr --64-bit 01:02:03:00:00:00:00:02") self.command("Third", "addr --64-bit 01:02:03:00:00:00:00:03") - def case(self): # Start PAN coordinator self.command("First", "start --pan_coordinator true --logical_channel {}".format(self.channel)) # Start PAN beacon @@ -107,5 +114,21 @@ class Testcase(Bench): self.command("Third", "poll --coord_address 01:02:03:00:00:00:00:01") self.command("*", "silent-mode off") + def case(self): + # Try tests few times because of potential RF failures + loop = 0 + while loop < 5: + try: + self.do_test_iteration() + break + except TestStepFail: + self.logger.info("Warning, iteration failed #" + str(loop+1)) + loop = loop + 1 + self.delay(5) + else: + raise TestStepFail("Too many failed iterations!") + def tearDown(self): + self.command("*", "silent-mode off") self.reset_dut() + diff --git a/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py b/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py index 19beaaef01..ee12489d38 100644 --- a/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py +++ b/TEST_APPS/testcases/nanostack_mac_tester/send_large_payloads.py @@ -17,12 +17,13 @@ limitations under the License. import os,sys from icetea_lib.bench import Bench +from icetea_lib.TestStepError import TestStepFail class Testcase(Bench): def __init__(self): Bench.__init__(self, name = "send_large_payloads", title = "Data transmission test with large packets", - status = "development", + status = "released", type = "reliability", subtype = "", execution = { @@ -52,10 +53,14 @@ class Testcase(Bench): def setUp(self): self.channel = 11 + + def do_test_iteration(self): + self.command("First", "mlme-reset") + self.command("Second", "mlme-reset") + self.command("First", "addr --64-bit 01:02:03:00:00:00:00:01") self.command("Second", "addr --64-bit 01:02:03:00:00:00:00:02") - def case(self): #104 characters, headers are 2+1+2+8+8+2=23 bytes, resulting in a packet size of 127 (max) large_payload = "0123456789abcdefghjiklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZZZZZZZZZ0123456789012345678901234567891234" # Start PAN coordinator @@ -83,5 +88,20 @@ class Testcase(Bench): self.command("Second", "data") self.command("First", "wait") + def case(self): + # Try tests few times because of potential RF failures + loop = 0 + while loop < 5: + try: + self.do_test_iteration() + break + except TestStepFail: + self.logger.info("Warning, iteration failed #" + str(loop+1)) + loop = loop + 1 + self.delay(5) + else: + raise TestStepFail("Too many failed iterations!") + def tearDown(self): self.reset_dut() + diff --git a/UNITTESTS/README.md b/UNITTESTS/README.md index 9757cef939..69288cd74c 100644 --- a/UNITTESTS/README.md +++ b/UNITTESTS/README.md @@ -1,27 +1,29 @@ ## Unit testing -This document describes how to write and test unit tests for Arm Mbed OS. To prevent and solve problems, please see the [troubleshooting](#troubleshooting) section. +This document describes how to write and use unit tests for Arm Mbed OS. ### Introduction -Unit tests test code in small sections on a host machine. Unlike other testing tools, unit testing doesn't require embedded hardware, and it doesn't need to build the full operating system. Because of this, unit testing can result in faster tests than other testing tools. Unit testing takes place in a build environment where we test each C or C++ class or module in isolation. This means we build test suites into separate test binaries and stub all access outside to remove dependencies on any specific embedded hardware or software combination. This allows us to complete the testing using native compilers on the build machine. +Unit tests test code in small sections on a host machine. Unlike other testing tools, unit testing doesn't require embedded hardware or need to build a full operating system. Because of this, unit testing can result in faster tests than other tools. Unit testing happens in a build environment where you test each C or C++ class or module in isolation. Build test suites into separate test binaries and stub all access outside to remove dependencies on any specific embedded hardware or software combination. This allows you to complete tests using native compilers on the build machine. ### Prerequisites -Please install the following dependencies to use Mbed OS unit testing. +Please install the following dependencies to use Mbed OS unit testing: -- GNU toolchains. - - GCC 6 or later. We recommend you use MinGW-W64 on Windows, but any Windows port of the above GCC versions works. Default compilers can be used on Mac OS instead of GCC to shorten build times, but code coverage results can then differ. -- CMake 3.0 or newer. -- Python 2.7.x, 3.5 or newer. -- Pip 10.0 or newer. -- Gcovr 4.1 or newer. -- Arm Mbed CLI 1.8.0 or newer. +* GNU toolchains. + * GCC 6 or later. We recommend you use MinGW-W64 on Windows, but any Windows port of the above GCC versions works. Default compilers can be used on Mac OS instead of GCC to shorten build times, but code coverage results can differ. +* CMake 3.0 or newer. +* Python 2.7.x, 3.5 or newer. +* Pip 10.0 or newer. +* Gcovr 4.1 or newer. +* Arm Mbed CLI 1.8.0 or newer. Detailed instructions for supported operating systems are below. #### Installing dependencies on Debian or Ubuntu +In a terminal window: + 1. `sudo apt-get -y install build-essential cmake` 1. Install Python and Pip with: @@ -34,6 +36,8 @@ Detailed instructions for supported operating systems are below. #### Installing dependencies on macOS +In a terminal window: + 1. Install [Homebrew](https://brew.sh/). 1. Install Xcode Command Line Tools with `xcode-select --install`. 1. Install CMake with: `brew install cmake`. @@ -49,7 +53,9 @@ Detailed instructions for supported operating systems are below. #### Installing dependencies on Windows -1. Download and install [MinGW-W64](http://mingw-w64.org/). +In a terminal window: + +1. Download and install MinGW-W64 from [SourceForge](https://sourceforge.net/projects/mingw-w64/files/Toolchains%20targetting%20Win64/Personal%20Builds/mingw-builds/). 1. Download CMake binaries from https://cmake.org/download/, and run the installer. 1. Download Python 2.7 or Python 3 from https://www.python.org/getit/, and run the installer. 1. Add MinGW, CMake and Python into system PATH. @@ -57,13 +63,15 @@ Detailed instructions for supported operating systems are below. ### Test code structure -Unit tests are located in the Mbed OS repository under the `UNITTESTS` folder. We recommend unit test files use an identical directory path to the file under test. This makes it easier to find unit tests for a particular class or a module. For example, if the file under test is `some/example/path/ClassName.cpp`, then all the test files are in the `UNITTESTS/some/example/path/ClassName` directory. Each test suite needs to have its own `unittest.cmake` file for test configuration. +Find unit tests in the Mbed OS repository under the `UNITTESTS` folder. We recommend unit test files use an identical directory path as the file under test. This makes it easier to find unit tests for a particular class or a module. For example, if the file you're testing is `some/example/path/ClassName.cpp`, then all the test files are in the `UNITTESTS/some/example/path/ClassName` directory. Each test suite needs to have its own `unittest.cmake` file for test configuration. + +All the class stubs should be located in the `UNITTESTS/stubs` directory. A single stub class can be used by multiple test suites and should follow the naming convention `ClassName_stub.cpp` for the source file, and `ClassName_stub.h` for the header file. Use the actual header files for the unit tests, and don't stub headers if possible. The stubbed headers reside in the `UNITTESTS/target_h` directory. #### Test discovery -Registering unit tests for running is automatic, and the test runner handles registration. However, test files are not automatically assigned to be built. We build unit tests by using a separate build system, which searches for unit tests under the `UNITTESTS` directory. +Registering unit tests to run happens automatically, and the test runner handles registration. However, test files do not automatically build. Build unit tests with a separate system that searches for unit tests under the `UNITTESTS` directory. -For the build system to find and build any test suite automatically, you must include a unit test configuration file named `unittest.cmake` for each unit test suite. This configuration file contains all the source files required for the build. +For the build system to find and build any test suite automatically, include a unit test configuration file named `unittest.cmake` for each unit test suite. This configuration file lists all the source files required for the test build. #### Test names @@ -71,20 +79,30 @@ The build system automatically generates names of test suites. The name is const ### Unit testing with Mbed CLI -Mbed CLI supports unit tests through `mbed test --unittests` command. For information on using Mbed CLI, please see the [CLI documentation](https://os.mbed.com/docs/latest/tools/developing-arm-mbed-cli.html). +Mbed CLI supports unit tests through the `mbed test --unittests` command. For information on using Mbed CLI, please see the [CLI documentation](https://os.mbed.com/docs/latest/tools/developing-arm-mbed-cli.html). ### Writing unit tests +A unit tests suite consists of one or more test cases. The test cases should cover all the functions in a class under test. All the external dependencies are stubbed including the other classes in the same module. Avoid stubbing header files. Finally, analyze code coverage to ensure all code is tested, and no dead code is found. + +Please see the [documentation for Google Test](https://github.com/google/googletest/blob/master/googletest/docs/primer.md) to learn how to write unit tests using its framework. See the [documentation for Google Mock](https://github.com/google/googletest/blob/master/googlemock/docs/Documentation.md) if you want to write and use C++ mock classes instead of stubs. + +#### Test suite configuration + Create two files in the test directory for each test suite: -- Unit test source file (`test_ClassName.cpp`). -- Unit test configuration file (`unittest.cmake`). +* Unit test source file (`test_ClassName.cpp`). +* Unit test configuration file (`unittest.cmake`). -List all the files required for the build in the `unittest.cmake` file. We recommend you list the file paths relative to the `UNITTESTS` folder. Use the following variables to list the source files and include paths: +List all the required files for the build in the `unittest.cmake` file with paths relative to the `UNITTESTS` folder. Use the following variables to list the source files and include paths: -- **unittest-includes** - List of header include paths. You can use this to extend or overwrite default paths listed in CMakeLists.txt. -- **unittest-sources** - List of files under test. -- **unittest-test-sources** - List of test sources and stubs. +* **unittest-includes**: List of header include paths. You can use this to extend or overwrite default paths listed in `UNITTESTS/CMakeLists.txt`. +* **unittest-sources**: List of files under test. +* **unittest-test-sources**: List of test sources and stubs. + +You can also set custom compiler flags and other configurations supported by CMake in `unittest.cmake`. + +#### Example With the following steps, you can write a simple unit test. In this example, `rtos/Semaphore.cpp` is a class under test. @@ -97,11 +115,13 @@ With the following steps, you can write a simple unit test. In this example, `rt ) set(unittest-test-sources - stubs/mbed_assert.c + stubs/mbed_assert_stub.c + stubs/Kernel_stub.cpp rtos/Semaphore/test_Semaphore.cpp ) ``` - +1. Stub all external dependencies. Create stubs `UNITTESTS/stubs/mbed_assert_stub.c` and `UNITTESTS/stubs/Kernel_stub.cpp` if they don't already exist. +1. Update header stubs with any missing type or function declarations. 1. Create a test source file `UNITTESTS/rtos/Semaphore/test_Semaphore.cpp` with the following content: ``` @@ -163,28 +183,28 @@ Use Mbed CLI to build and run unit tests. For advanced use, you can run CMake an 1. Create a build directory `mkdir UNITTESTS/build`. 1. Move to the build directory `cd UNITTESTS/build`. 1. Run CMake using a relative path to `UNITTESTS` folder as the argument. So from `UNITTESTS/build` use `cmake ..`: - - Add `-g [generator]` if generating other than Unix Makefiles such in case of MinGW use `-g "MinGW Makefiles"`. - - Add `-DCMAKE_MAKE_PROGRAM=`, `-DCMAKE_CXX_COMPILER=` and `-DCMAKE_C_COMPILER=` to use a specific Make program and compilers. - - Add `-DCMAKE_BUILD_TYPE=Debug` to build a debug build. - - Add `-DCOVERAGE=True` to add coverage compiler flags. - - See the [CMake manual](https://cmake.org/cmake/help/v3.0/manual/cmake.1.html) for more information. -1. Run a Make program to build the tests. + * Add `-g [generator]` if generating other than Unix Makefiles such in case of MinGW use `-g "MinGW Makefiles"`. + * Add `-DCMAKE_MAKE_PROGRAM=`, `-DCMAKE_CXX_COMPILER=` and `-DCMAKE_C_COMPILER=` to use a specific Make program and compilers. + * Add `-DCMAKE_BUILD_TYPE=Debug` for a debug build. + * Add `-DCOVERAGE=True` to add coverage compiler flags. + * See the [CMake manual](https://cmake.org/cmake/help/v3.0/manual/cmake.1.html) for more information. +1. Run a Make program to build tests. #### Run tests directly with CTest -Run a test binary in the build directory to run a unit test suite. To run multiple test suites at once, use CTest test runner. Run CTest with `ctest`. Add `-v` to get results for each test case. See the [CTest manual](https://cmake.org/cmake/help/v3.0/manual/ctest.1.html) for more information. +Run a test binary in the build directory to run a unit test suite. To run multiple test suites at once, use the CTest test runner. Run CTest with `ctest`. Add `-v` to get results for each test case. See the [CTest manual](https://cmake.org/cmake/help/v3.0/manual/ctest.1.html) for more information. #### Run tests with GUI test runner -1. Install *gtest-runner* using the [documentation](https://github.com/nholthaus/gtest-runner). -1. Run *gtest-runner* -1. Add test executables into the list. -1. Run them. +1. Install `gtest-runner` according to the [documentation](https://github.com/nholthaus/gtest-runner). +1. Run `gtest-runner`. +1. Add test executables into the list and run. ### Debugging 1. Use Mbed CLI to build a debug build. For advanced use, run CMake directly with `-DCMAKE_BUILD_TYPE=Debug`, and then run a Make program. 1. Run GDB with a test executable as an argument to debug unit tests. +1. Run tests with Valgrind to analyze the test memory profile. ### Get code coverage @@ -200,8 +220,11 @@ Use Mbed CLI to generate code coverage reports. For advanced use, follow these s **Problem:** Generic problems with CMake or with the build process. * **Solution**: Delete the build directory. Make sure that CMake, g++, GCC and a Make program can be found in the path and are correct versions. -**Problem:** Virus protection identifies files generated by CMake as malicious and quarantines the files on Windows. -* **Solution**: Restore the false positive files from the quarantine. +**Problem:** (Windows) Virus protection identifies files generated by CMake as malicious and quarantines the files. +* **Solution**: Restore false-positive files from the quarantine. -**Problem:** CMake compiler check fails on Mac OS Mojave when using GCC-8. +**Problem:** (Windows) Git with shell installation adds sh.exe to the path and then CMake throws an error: sh.exe was found in your PATH. For MinGW make to work correctly, sh.exe must NOT be in your path. +* **Solution**: Remove sh.exe from the system path. + +**Problem:** (Mac OS) CMake compiler check fails on Mac OS Mojave when using GCC-8. * **Solution**: Make sure gnm (binutils) is not installed. Uninstall binutils with `brew uninstall binutils`. diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp index 2f5bbdb199..4d7b80cb98 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp @@ -53,7 +53,6 @@ protected: ATHandler_stub::bool_value = false; ATHandler_stub::uint8_value = 0; ATHandler_stub::fh_value = NULL; - ATHandler_stub::callback = NULL; ATHandler_stub::call_immediately = false; ATHandler_stub::resp_info_true_counter = false; ATHandler_stub::info_elem_true_counter = false; @@ -63,6 +62,9 @@ protected: ATHandler_stub::read_string_table[kRead_string_table_size]; ATHandler_stub::resp_stop_success_count = kResp_stop_count_default; CellularDevice_stub::connect_counter = 2; + for (int i=0; i < kATHandler_urc_table_max_size; i++) { + ATHandler_stub::callback[i] = NULL; + } } void TearDown() diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp index 28c80e1126..9609ab3935 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp @@ -211,6 +211,71 @@ TEST_F(TestAT_CellularNetwork, test_AT_CellularNetwork_get_registration_params) EXPECT_TRUE(reg_params_check._cell_id == -1 && reg_params_check._active_time == -1 && reg_params_check._periodic_tau == -1); } +static int disconnect_cb_count = 0; +static bool disconnect_cb_param_check = false; +static void disconnect_cb(nsapi_event_t ev, intptr_t intptr) +{ + disconnect_cb_count++; + + if (disconnect_cb_count == 3 && disconnect_cb_param_check) { + EXPECT_TRUE(ev == NSAPI_EVENT_CONNECTION_STATUS_CHANGE); + EXPECT_TRUE(intptr == NSAPI_STATUS_DISCONNECTED); + } +} + +TEST_F(TestAT_CellularNetwork, test_AT_CellularNetwork_registration_status_change) +{ + EventQueue que; + FileHandle_stub fh1; + ATHandler at(&fh1, que, 0, ","); + + AT_CellularNetwork cn(at); + + + cn.attach(&disconnect_cb); + + ATHandler_stub::nsapi_error_value = NSAPI_ERROR_OK; + ATHandler_stub::process_oob_urc = true; + + ATHandler_stub::read_string_index = 2; + ATHandler_stub::read_string_table[2] = "+CREG:"; + ATHandler_stub::read_string_table[1] = "00C3"; + ATHandler_stub::read_string_table[0] = "A13F"; + ATHandler_stub::int_count = 2; + //ATHandler_stub::int_valid_count_table[2] = 1; //URC status is skipped + ATHandler_stub::int_valid_count_table[1] = 0; //not registered + ATHandler_stub::int_valid_count_table[0] = 1; + at.process_oob(); + + disconnect_cb_count = 0; + disconnect_cb_param_check = true; + ATHandler_stub::read_string_index = 4; + ATHandler_stub::read_string_table[4] = "+CREG:"; + ATHandler_stub::read_string_table[3] = "00C3"; + ATHandler_stub::read_string_table[2] = "A13F"; + ATHandler_stub::read_string_table[1] = "FF"; + ATHandler_stub::read_string_table[0] = "FF"; + ATHandler_stub::int_count = 2; + //ATHandler_stub::int_valid_count_table[2] = 1; //URC status is skipped + ATHandler_stub::int_valid_count_table[1] = 1; //registered, home network + ATHandler_stub::int_valid_count_table[0] = 1; + at.process_oob(); + + ATHandler_stub::read_string_index = 5; + ATHandler_stub::int_count = 3; + ATHandler_stub::read_string_index = 4; + ATHandler_stub::read_string_table[4] = "+CREG:"; + ATHandler_stub::read_string_table[3] = "00C3"; + ATHandler_stub::read_string_table[2] = "A13F"; + ATHandler_stub::read_string_table[1] = "FF"; + ATHandler_stub::read_string_table[0] = "FF"; + ATHandler_stub::int_count = 2; + //ATHandler_stub::int_valid_count_table[2] = 1; //URC status is skipped + ATHandler_stub::int_valid_count_table[1] = 4; //unknown registration status + ATHandler_stub::int_valid_count_table[0] = 1; + at.process_oob(); +} + TEST_F(TestAT_CellularNetwork, test_AT_CellularNetwork_get_network_registering_mode) { EventQueue que; diff --git a/UNITTESTS/features/lorawan/loraphy/unittest.cmake b/UNITTESTS/features/lorawan/loraphy/unittest.cmake index c1abde4e46..b3c8a5854a 100644 --- a/UNITTESTS/features/lorawan/loraphy/unittest.cmake +++ b/UNITTESTS/features/lorawan/loraphy/unittest.cmake @@ -37,5 +37,5 @@ set(unittest-test-sources ) -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -DMBED_CONF_LORA_DUTY_CYCLE_ON_JOIN=true") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -DMBED_CONF_LORA_DUTY_CYCLE_ON_JOIN=true") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -DMBED_CONF_LORA_DUTY_CYCLE_ON_JOIN=true -DMBED_CONF_LORA_WAKEUP_TIME=5") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -DMBED_CONF_LORA_DUTY_CYCLE_ON_JOIN=true -DMBED_CONF_LORA_WAKEUP_TIME=5") diff --git a/UNITTESTS/stubs/ATHandler_stub.cpp b/UNITTESTS/stubs/ATHandler_stub.cpp index ff58ade4ac..54003807f5 100644 --- a/UNITTESTS/stubs/ATHandler_stub.cpp +++ b/UNITTESTS/stubs/ATHandler_stub.cpp @@ -43,16 +43,19 @@ bool ATHandler_stub::bool_value = false; uint8_t ATHandler_stub::uint8_value = 0; FileHandle_stub *ATHandler_stub::fh_value = NULL; device_err_t ATHandler_stub::device_err_value; -Callback ATHandler_stub::callback = NULL; bool ATHandler_stub::call_immediately = false; uint8_t ATHandler_stub::resp_info_true_counter = false; uint8_t ATHandler_stub::info_elem_true_counter = false; int ATHandler_stub::int_valid_count_table[kRead_int_table_size]; int ATHandler_stub::int_count = kRead_int_table_size; +bool ATHandler_stub::process_oob_urc = false; int ATHandler_stub::read_string_index = kRead_string_table_size; const char *ATHandler_stub::read_string_table[kRead_string_table_size]; int ATHandler_stub::resp_stop_success_count = kResp_stop_count_default; +int ATHandler_stub::urc_amount = 0; +mbed::Callback ATHandler_stub::callback[kATHandler_urc_table_max_size]; +char *ATHandler_stub::urc_string_table[kATHandler_urc_table_max_size]; ATHandler::ATHandler(FileHandle *fh, EventQueue &queue, int timeout, const char *output_delimiter, uint16_t send_delay) : _nextATHandler(0), @@ -60,6 +63,14 @@ ATHandler::ATHandler(FileHandle *fh, EventQueue &queue, int timeout, const char _queue(queue) { ATHandler_stub::ref_count = 1; + + ATHandler_stub::process_oob_urc = false; + ATHandler_stub::urc_amount = 0; + int i = 0; + while (i < kATHandler_urc_table_max_size) { + ATHandler_stub::callback[i] = NULL; + ATHandler_stub::urc_string_table[i++] = NULL; + } } void ATHandler::set_debug(bool debug_on) @@ -70,6 +81,16 @@ void ATHandler::set_debug(bool debug_on) ATHandler::~ATHandler() { ATHandler_stub::ref_count = kATHandler_destructor_ref_ount; + + int i = 0; + while (i < kATHandler_urc_table_max_size) { + if (ATHandler_stub::urc_string_table[i]) { + delete [] ATHandler_stub::urc_string_table[i]; + i++; + } else { + break; + } + } } void ATHandler::inc_ref_count() @@ -98,7 +119,18 @@ void ATHandler::set_file_handle(FileHandle *fh) nsapi_error_t ATHandler::set_urc_handler(const char *urc, mbed::Callback cb) { - ATHandler_stub::callback = cb; + if (ATHandler_stub::urc_amount < kATHandler_urc_table_max_size) { + ATHandler_stub::callback[ATHandler_stub::urc_amount] = cb; + ATHandler_stub::urc_string_table[ATHandler_stub::urc_amount] = new char[kATHandler_urc_string_max_size]; + if (urc) { + int bytes_to_copy = strlen(urc) < kATHandler_urc_string_max_size ? strlen(urc) : kATHandler_urc_string_max_size; + memcpy(ATHandler_stub::urc_string_table[ATHandler_stub::urc_amount], urc, bytes_to_copy); + } + ATHandler_stub::urc_amount++; + } else { + ATHandler_stub::callback[0] = cb; + MBED_ASSERT("ATHandler URC amount limit reached"); + } if (ATHandler_stub::call_immediately) { cb(); } @@ -143,6 +175,20 @@ void ATHandler::restore_at_timeout() void ATHandler::process_oob() { + if (ATHandler_stub::process_oob_urc) { + int i = 0; + while (i < ATHandler_stub::urc_amount) { + if (ATHandler_stub::read_string_index >= 0) { + if (!memcmp(ATHandler_stub::urc_string_table[i], + ATHandler_stub::read_string_table[ATHandler_stub::read_string_index], + strlen(ATHandler_stub::urc_string_table[i]))) { + ATHandler_stub::callback[i](); + break; + } + } + i++; + } + } } void ATHandler::clear_error() diff --git a/UNITTESTS/stubs/ATHandler_stub.h b/UNITTESTS/stubs/ATHandler_stub.h index c506ccf017..e243e355ba 100644 --- a/UNITTESTS/stubs/ATHandler_stub.h +++ b/UNITTESTS/stubs/ATHandler_stub.h @@ -31,6 +31,8 @@ static const int kRead_int_table_size = 100; static const int kResp_stop_count_default = 100; // set reference count to -909 to separate it from zero so we can test that ATHandler is really deleted. static const int kATHandler_destructor_ref_ount = -909; +static const int kATHandler_urc_table_max_size = 10; +static const int kATHandler_urc_string_max_size = 16; namespace ATHandler_stub { extern nsapi_error_t nsapi_error_value; @@ -50,13 +52,16 @@ extern uint8_t info_elem_true_counter; extern uint8_t uint8_value; extern mbed::FileHandle_stub *fh_value; extern mbed::device_err_t device_err_value; -extern mbed::Callback callback; +extern mbed::Callback callback[kATHandler_urc_table_max_size]; extern bool call_immediately; extern const char *read_string_table[kRead_string_table_size]; extern int read_string_index; extern int int_valid_count_table[kRead_int_table_size]; extern int int_count; extern int resp_stop_success_count; +extern bool process_oob_urc; +extern int urc_amount; +extern char *urc_string_table[kATHandler_urc_table_max_size]; } #endif diff --git a/UNITTESTS/stubs/LoRaPHY_stub.cpp b/UNITTESTS/stubs/LoRaPHY_stub.cpp index 56862af5df..01b7312b7c 100644 --- a/UNITTESTS/stubs/LoRaPHY_stub.cpp +++ b/UNITTESTS/stubs/LoRaPHY_stub.cpp @@ -168,9 +168,10 @@ uint8_t LoRaPHY::verify_link_ADR_req(verify_adr_params_t *verify_params, return LoRaPHY_stub::uint8_value; } -void LoRaPHY::get_rx_window_params(double t_symb, uint8_t min_rx_symb, - uint32_t rx_error, uint32_t wakeup_time, - uint32_t *window_timeout, int32_t *window_offset) +void LoRaPHY::get_rx_window_params(float t_symbol, uint8_t min_rx_symbols, + float rx_error, float wakeup_time, + uint32_t *window_length, int32_t *window_offset, + uint8_t phy_dr) { } diff --git a/UNITTESTS/unit_test/utils.py b/UNITTESTS/unit_test/utils.py index fe41dc8158..0a26cc7111 100644 --- a/UNITTESTS/unit_test/utils.py +++ b/UNITTESTS/unit_test/utils.py @@ -51,8 +51,13 @@ def execute_program(args, error_msg="An error occurred!", success_msg=None): stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + # Output is stripped to remove newline character. logging adds its own + # so we avoid double newlines. + # Because the process can terminate before the loop has read all lines, + # we read the output remnant just in case. Otherwise we lose it. while process.poll() is None: - logging.info(process.stdout.readline().decode("utf8")) + logging.info(process.stdout.readline().decode('utf8').rstrip('\n')) + logging.info(process.stdout.read().decode('utf8').rstrip('\n')) retcode = process.wait() diff --git a/cmsis/TARGET_CORTEX_A/core_ca.h b/cmsis/TARGET_CORTEX_A/core_ca.h index dbe9794d4f..c62c99f4f2 100644 --- a/cmsis/TARGET_CORTEX_A/core_ca.h +++ b/cmsis/TARGET_CORTEX_A/core_ca.h @@ -59,7 +59,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else diff --git a/cmsis/TARGET_CORTEX_M/core_armv8mbl.h b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h index 251e4ede3a..e213d727e0 100644 --- a/cmsis/TARGET_CORTEX_M/core_armv8mbl.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif diff --git a/cmsis/TARGET_CORTEX_M/core_armv8mml.h b/cmsis/TARGET_CORTEX_M/core_armv8mml.h index 3a3148ea31..923f9f1557 100644 --- a/cmsis/TARGET_CORTEX_M/core_armv8mml.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mml.h @@ -97,7 +97,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else diff --git a/cmsis/TARGET_CORTEX_M/core_cm0.h b/cmsis/TARGET_CORTEX_M/core_cm0.h index f929bba07b..5ce991e100 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm0.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif diff --git a/cmsis/TARGET_CORTEX_M/core_cm0plus.h b/cmsis/TARGET_CORTEX_M/core_cm0plus.h index 424011ac36..55a26f6689 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm0plus.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0plus.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif diff --git a/cmsis/TARGET_CORTEX_M/core_cm1.h b/cmsis/TARGET_CORTEX_M/core_cm1.h index 0ed678e3b8..f9b962fe11 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm1.h +++ b/cmsis/TARGET_CORTEX_M/core_cm1.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif diff --git a/cmsis/TARGET_CORTEX_M/core_cm23.h b/cmsis/TARGET_CORTEX_M/core_cm23.h index acbc5dfea2..8a73801ba7 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm23.h +++ b/cmsis/TARGET_CORTEX_M/core_cm23.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif diff --git a/cmsis/TARGET_CORTEX_M/core_cm3.h b/cmsis/TARGET_CORTEX_M/core_cm3.h index 74bff64be4..fa010da6ec 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm3.h +++ b/cmsis/TARGET_CORTEX_M/core_cm3.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -668,7 +668,7 @@ typedef struct #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ - +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ @@ -677,6 +677,7 @@ typedef struct #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif /*@} end of group CMSIS_SCnotSCB */ diff --git a/cmsis/TARGET_CORTEX_M/core_cm33.h b/cmsis/TARGET_CORTEX_M/core_cm33.h index 6cd2db77fe..5bcaa49413 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm33.h +++ b/cmsis/TARGET_CORTEX_M/core_cm33.h @@ -97,7 +97,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_PCS_VFP) + #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else diff --git a/cmsis/TARGET_CORTEX_M/core_cm4.h b/cmsis/TARGET_CORTEX_M/core_cm4.h index 7d56873532..040082f436 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm4.h +++ b/cmsis/TARGET_CORTEX_M/core_cm4.h @@ -86,7 +86,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else diff --git a/cmsis/TARGET_CORTEX_M/core_cm7.h b/cmsis/TARGET_CORTEX_M/core_cm7.h index a14dc623b7..5f9d1498ae 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm7.h +++ b/cmsis/TARGET_CORTEX_M/core_cm7.h @@ -86,7 +86,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else diff --git a/cmsis/TARGET_CORTEX_M/core_sc000.h b/cmsis/TARGET_CORTEX_M/core_sc000.h index 9b67c92f3b..67d3851b12 100644 --- a/cmsis/TARGET_CORTEX_M/core_sc000.h +++ b/cmsis/TARGET_CORTEX_M/core_sc000.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif diff --git a/cmsis/TARGET_CORTEX_M/core_sc300.h b/cmsis/TARGET_CORTEX_M/core_sc300.h index 3e8a47109a..0c1e324948 100644 --- a/cmsis/TARGET_CORTEX_M/core_sc300.h +++ b/cmsis/TARGET_CORTEX_M/core_sc300.h @@ -81,7 +81,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif diff --git a/cmsis/TARGET_CORTEX_M/mbed_fault_handler.c b/cmsis/TARGET_CORTEX_M/mbed_fault_handler.c index 62fa90ff07..5c0f20b21a 100644 --- a/cmsis/TARGET_CORTEX_M/mbed_fault_handler.c +++ b/cmsis/TARGET_CORTEX_M/mbed_fault_handler.c @@ -18,6 +18,7 @@ #define __STDC_FORMAT_MACROS #endif #include +#include #include "device.h" #include "mbed_error.h" diff --git a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp index d585cd1812..2c06a77753 100644 --- a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp +++ b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp @@ -50,6 +50,8 @@ #define RFF_TX 0x04 #define RFF_CCA 0x08 +namespace { + typedef enum { RF_MODE_NORMAL = 0, RF_MODE_SNIFFER = 1, @@ -82,6 +84,8 @@ typedef enum { STATE_TRANSITION_IN_PROGRESS = 0x1F } rf_trx_states_t; +} // anonymous namespace + static const uint8_t *rf_tx_data; // Points to Nanostack's buffer static uint8_t rf_tx_length; /*ACK wait duration changes depending on data rate*/ diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp index 08ba4cf1bc..3039a0b6f8 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp @@ -65,6 +65,8 @@ extern "C" { #define gXcvrLowPowerState_d gXcvrPwrAutodoze_c #endif +namespace { + /* MCR20A XCVR states */ typedef enum xcvrState_tag { gIdle_c, @@ -106,6 +108,8 @@ typedef enum { TX_ARET_ON = 0x19 } rf_trx_states_t; +} // anonymous namespace + /*RF receive buffer*/ static uint8_t rf_buffer[RF_BUFFER_SIZE]; diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/source/rf_configuration.c b/components/802.15.4_RF/stm-s2lp-rf-driver/source/rf_configuration.c index 0e0045784a..fee60bd667 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/source/rf_configuration.c +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/source/rf_configuration.c @@ -101,7 +101,7 @@ void rf_conf_calculate_rx_filter_bandwidth_registers(uint32_t rx_bandwidth, uint uint8_t chflt_e_tmp = 0; uint8_t chflt_m_tmp = 0; - while (rx_bandwidth < 900000 / (2 << chflt_e_tmp)) { + while (rx_bandwidth < 900000u / (2 << chflt_e_tmp)) { chflt_e_tmp++; } uint32_t rx_bandwidth_tmp = rx_bandwidth; diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h b/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h index 1c855d7523..8dbb4a9545 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h @@ -301,7 +301,11 @@ typedef enum { S2LP_STATE_SYNTH_SETUP = 0x50 } s2lp_states_e; +#if defined __cplusplus && __cplusplus >= 201103 +typedef enum : uint8_t { +#else typedef enum { +#endif S2LP_CMD_TX = 0x60, S2LP_CMD_RX, S2LP_CMD_READY, diff --git a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp index 445ab7978c..7fd590fc2f 100644 --- a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.cpp @@ -14,7 +14,7 @@ * limitations under the License. */ -#ifdef DEVICE_FLASH +#if DEVICE_FLASH #include "FlashIAPBlockDevice.h" #include "mbed_critical.h" diff --git a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h index 0b6e68125b..3e83bb0b3a 100644 --- a/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h +++ b/components/storage/blockdevice/COMPONENT_FLASHIAP/FlashIAPBlockDevice.h @@ -17,7 +17,7 @@ #ifndef MBED_FLASHIAP_BLOCK_DEVICE_H #define MBED_FLASHIAP_BLOCK_DEVICE_H -#ifdef DEVICE_FLASH +#if DEVICE_FLASH #include "FlashIAP.h" #include "BlockDevice.h" diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp index 7ac7a22dbc..f9513ad941 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp @@ -421,7 +421,7 @@ int QSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t in_size) if (_set_write_enable() != 0) { tr_error("QSPI Erase Device not ready - failed"); erase_failed = true; - status = QSPIF_BD_ERROR_READY_FAILED; + status = QSPIF_BD_ERROR_WREN_FAILED; goto exit_point; } @@ -1024,12 +1024,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table //_inst_width = QSPI_CFG_BUS_QUAD; _address_width = QSPI_CFG_BUS_QUAD; _data_width = QSPI_CFG_BUS_QUAD; - - break; } } - - + is_qpi_mode = false; examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_FAST_READ_SUPPORT_BYTE]; if (examined_byte & 0x40) { // Fast Read 1-4-4 Supported diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/TESTS/block_device/qspif/main.cpp b/components/storage/blockdevice/COMPONENT_QSPIF/TESTS/block_device/qspif/main.cpp index 9297d53812..0674fc463d 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/TESTS/block_device/qspif/main.cpp +++ b/components/storage/blockdevice/COMPONENT_QSPIF/TESTS/block_device/qspif/main.cpp @@ -48,6 +48,10 @@ void basic_erase_program_read_test(QSPIFBlockDevice &blockD, bd_size_t block_siz { int err = 0; _mutex->lock(); + + static unsigned block_seed = 1; + srand(block_seed++); + // Find a random block bd_addr_t block = (rand() * block_size) % blockD.size(); diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json b/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json index b611268a5a..dc49d3f462 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json @@ -20,9 +20,18 @@ "DISCO_L476VG": { "QSPI_FREQ": "80000000" }, + "DISCO_L496AG": { + "QSPI_FREQ": "8000000" + }, "DISCO_F469NI": { "QSPI_FREQ": "80000000" }, + "DISCO_F746NG": { + "QSPI_FREQ": "80000000" + }, + "DISCO_F769NI": { + "QSPI_FREQ": "8000000" + }, "NRF52840_DK": { "QSPI_FREQ": "32000000" } diff --git a/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.cpp index f579dde2c1..aaaa3233df 100644 --- a/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.cpp @@ -136,7 +136,7 @@ */ /* If the target has no SPI support then SDCard is not supported */ -#ifdef DEVICE_SPI +#if DEVICE_SPI #include "SDBlockDevice.h" #include "platform/mbed_debug.h" @@ -791,7 +791,7 @@ int SDBlockDevice::_cmd(SDBlockDevice::cmdSupported cmd, uint32_t arg, bool isAc switch (cmd) { case CMD8_SEND_IF_COND: // Response R7 debug_if(_dbg, "V2-Version Card\n"); - _card_type = SDCARD_V2; + _card_type = SDCARD_V2; // fallthrough // Note: No break here, need to read rest of the response case CMD58_READ_OCR: // Response R3 response = (_spi.write(SPI_FILL_CHAR) << 24); diff --git a/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.h b/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.h index de166e67a4..790f550367 100644 --- a/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.h +++ b/components/storage/blockdevice/COMPONENT_SD/SDBlockDevice.h @@ -18,7 +18,7 @@ #define MBED_SD_BLOCK_DEVICE_H /* If the target has no SPI support then SDCard is not supported */ -#ifdef DEVICE_SPI +#if DEVICE_SPI #include "BlockDevice.h" #include "drivers/SPI.h" diff --git a/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp b/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp index b1d64d9a87..3916616ad6 100644 --- a/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp +++ b/components/storage/blockdevice/COMPONENT_SD/TESTS/filesystem/fopen/fopen.cpp @@ -68,7 +68,7 @@ using namespace utest::v1; * <<< lines removed >>> */ -#if defined(DEVICE_SPI) && ( defined(MBED_CONF_APP_FSFAT_SDCARD_INSTALLED) || (MBED_CONF_SD_FSFAT_SDCARD_INSTALLED)) +#if DEVICE_SPI && ( defined(MBED_CONF_APP_FSFAT_SDCARD_INSTALLED) || (MBED_CONF_SD_FSFAT_SDCARD_INSTALLED)) static char fsfat_fopen_utest_msg_g[FSFAT_UTEST_MSG_BUF_SIZE]; #define FSFAT_FOPEN_TEST_MOUNT_PT_NAME "sd" #define FSFAT_FOPEN_TEST_MOUNT_PT_PATH "/" FSFAT_FOPEN_TEST_MOUNT_PT_NAME diff --git a/components/storage/blockdevice/COMPONENT_SD/config/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SD/config/mbed_lib.json index 1c9d7fe2ce..943fc1d05e 100644 --- a/components/storage/blockdevice/COMPONENT_SD/config/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SD/config/mbed_lib.json @@ -202,7 +202,7 @@ "SPI_MOSI": "D11", "SPI_MISO": "D12", "SPI_CLK": "D13", - "SPI_CS": "D9" + "SPI_CS": "D10" }, "NUCLEO_F207ZG": { "SPI_MOSI": "PC_12", diff --git a/components/wifi/esp8266-driver/ESP8266/ESP8266.cpp b/components/wifi/esp8266-driver/ESP8266/ESP8266.cpp index bcddc4a2d1..61ae9839bc 100644 --- a/components/wifi/esp8266-driver/ESP8266/ESP8266.cpp +++ b/components/wifi/esp8266-driver/ESP8266/ESP8266.cpp @@ -782,10 +782,9 @@ int32_t ESP8266::recv_udp(int id, void *data, uint32_t amount, uint32_t timeout) _smutex.lock(); set_timeout(timeout); - // No flow control, drain the USART receive register ASAP to avoid data overrun - if (_serial_rts == NC) { - _process_oob(timeout, true); - } + // Process OOB data since this is + // how UDP packets are received + _process_oob(timeout, true); set_timeout(); diff --git a/components/wifi/esp8266-driver/ESP8266Interface.cpp b/components/wifi/esp8266-driver/ESP8266Interface.cpp index c81af3a91c..51e77a8b1c 100644 --- a/components/wifi/esp8266-driver/ESP8266Interface.cpp +++ b/components/wifi/esp8266-driver/ESP8266Interface.cpp @@ -190,11 +190,6 @@ int ESP8266Interface::connect() return NSAPI_ERROR_IS_CONNECTED; } - status = _startup(ESP8266::WIFIMODE_STATION); - if (status != NSAPI_ERROR_OK) { - return status; - } - if (!_esp.dhcp(true, 1)) { return NSAPI_ERROR_DHCP_FAILURE; } @@ -315,11 +310,6 @@ int ESP8266Interface::scan(WiFiAccessPoint *res, unsigned count) return status; } - status = _startup(ESP8266::WIFIMODE_STATION); - if (status != NSAPI_ERROR_OK) { - return status; - } - return _esp.scan(res, count); } @@ -370,6 +360,9 @@ nsapi_error_t ESP8266Interface::_init(void) if (!_esp.cond_enable_tcp_passive_mode()) { return NSAPI_ERROR_DEVICE_ERROR; } + if (!_esp.startup(ESP8266::WIFIMODE_STATION)) { + return NSAPI_ERROR_DEVICE_ERROR; + } _initialized = true; } @@ -385,16 +378,6 @@ void ESP8266Interface::_hw_reset() _rst_pin.rst_deassert(); } -nsapi_error_t ESP8266Interface::_startup(const int8_t wifi_mode) -{ - if (_conn_stat == NSAPI_STATUS_DISCONNECTED) { - if (!_esp.startup(wifi_mode)) { - return NSAPI_ERROR_DEVICE_ERROR; - } - } - return NSAPI_ERROR_OK; -} - struct esp8266_socket { int id; nsapi_protocol_t proto; diff --git a/components/wifi/esp8266-driver/ESP8266Interface.h b/components/wifi/esp8266-driver/ESP8266Interface.h index b50f9dbfd4..415e291d7d 100644 --- a/components/wifi/esp8266-driver/ESP8266Interface.h +++ b/components/wifi/esp8266-driver/ESP8266Interface.h @@ -353,7 +353,6 @@ private: bool _get_firmware_ok(); nsapi_error_t _init(void); void _hw_reset(); - nsapi_error_t _startup(const int8_t wifi_mode); //sigio struct { diff --git a/components/wifi/esp8266-driver/README.md b/components/wifi/esp8266-driver/README.md index 4b60886cc6..70554dd765 100644 --- a/components/wifi/esp8266-driver/README.md +++ b/components/wifi/esp8266-driver/README.md @@ -22,7 +22,7 @@ protocol, where data would be lost without notification. On UDP using all firmwa ## Mandatory configuration -![mbed_lib.json](mbed_lib.json) configuration assumes Arduino form factor. Please adjust according to your board. You can override parameters from your app config file. +[mbed_lib.json](mbed_lib.json) configuration assumes Arduino form factor. Please adjust according to your board. You can override parameters from your app config file. At minimum, check the following configuration parameters: diff --git a/drivers/AnalogIn.cpp b/drivers/AnalogIn.cpp index 86fd7be235..dd9d22f306 100644 --- a/drivers/AnalogIn.cpp +++ b/drivers/AnalogIn.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/AnalogIn.h b/drivers/AnalogIn.h index 287e6a3d7e..8f247e5975 100644 --- a/drivers/AnalogIn.h +++ b/drivers/AnalogIn.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_ANALOGIN) || defined(DOXYGEN_ONLY) +#if DEVICE_ANALOGIN || defined(DOXYGEN_ONLY) #include "hal/analogin_api.h" #include "platform/SingletonPtr.h" diff --git a/drivers/AnalogOut.h b/drivers/AnalogOut.h index 111e1006bf..d12cbafcc4 100644 --- a/drivers/AnalogOut.h +++ b/drivers/AnalogOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_ANALOGOUT) || defined(DOXYGEN_ONLY) +#if DEVICE_ANALOGOUT || defined(DOXYGEN_ONLY) #include "hal/analogout_api.h" #include "platform/PlatformMutex.h" diff --git a/drivers/BusIn.cpp b/drivers/BusIn.cpp index c14351f3fe..7aa557738c 100644 --- a/drivers/BusIn.cpp +++ b/drivers/BusIn.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/BusIn.h b/drivers/BusIn.h index da3f44545f..61bf7b536e 100644 --- a/drivers/BusIn.h +++ b/drivers/BusIn.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/BusInOut.cpp b/drivers/BusInOut.cpp index 170e035b96..8039a45040 100644 --- a/drivers/BusInOut.cpp +++ b/drivers/BusInOut.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/BusInOut.h b/drivers/BusInOut.h index 02f62fbf3f..64a4e0e189 100644 --- a/drivers/BusInOut.h +++ b/drivers/BusInOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/BusOut.cpp b/drivers/BusOut.cpp index 769d2e6891..654040103c 100644 --- a/drivers/BusOut.cpp +++ b/drivers/BusOut.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/BusOut.h b/drivers/BusOut.h index 46e21240a7..ca83d00a17 100644 --- a/drivers/BusOut.h +++ b/drivers/BusOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/CAN.cpp b/drivers/CAN.cpp index e3a0d42854..a3699e3919 100644 --- a/drivers/CAN.cpp +++ b/drivers/CAN.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/CAN.h b/drivers/CAN.h index d3565ee727..c34b1f0265 100644 --- a/drivers/CAN.h +++ b/drivers/CAN.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_CAN) || defined(DOXYGEN_ONLY) +#if DEVICE_CAN || defined(DOXYGEN_ONLY) #include "hal/can_api.h" #include "platform/Callback.h" diff --git a/drivers/DigitalIn.h b/drivers/DigitalIn.h index 8eceb07707..348a87bf33 100644 --- a/drivers/DigitalIn.h +++ b/drivers/DigitalIn.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/DigitalInOut.h b/drivers/DigitalInOut.h index 88411957df..9ceb025aee 100644 --- a/drivers/DigitalInOut.h +++ b/drivers/DigitalInOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/DigitalOut.h b/drivers/DigitalOut.h index 8f9059173e..b9fe1f2d3e 100644 --- a/drivers/DigitalOut.h +++ b/drivers/DigitalOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Ethernet.cpp b/drivers/Ethernet.cpp index 6b0a2bfab6..b2b73c113c 100644 --- a/drivers/Ethernet.cpp +++ b/drivers/Ethernet.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Ethernet.h b/drivers/Ethernet.h index a9b7c2c1db..30618806e5 100644 --- a/drivers/Ethernet.h +++ b/drivers/Ethernet.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,7 +20,7 @@ #include "platform/platform.h" #include "platform/NonCopyable.h" -#if defined (DEVICE_ETHERNET) || defined(DOXYGEN_ONLY) +#if DEVICE_ETHERNET || defined(DOXYGEN_ONLY) namespace mbed { /** \addtogroup drivers */ diff --git a/drivers/FlashIAP.cpp b/drivers/FlashIAP.cpp index 8ef6f6e1b0..3f67093900 100644 --- a/drivers/FlashIAP.cpp +++ b/drivers/FlashIAP.cpp @@ -29,7 +29,7 @@ #include "platform/ScopedRomWriteLock.h" -#ifdef DEVICE_FLASH +#if DEVICE_FLASH namespace mbed { diff --git a/drivers/FlashIAP.h b/drivers/FlashIAP.h index befb45ac23..0c3c8e1049 100644 --- a/drivers/FlashIAP.h +++ b/drivers/FlashIAP.h @@ -22,7 +22,7 @@ #ifndef MBED_FLASHIAP_H #define MBED_FLASHIAP_H -#if defined (DEVICE_FLASH) || defined(DOXYGEN_ONLY) +#if DEVICE_FLASH || defined(DOXYGEN_ONLY) #include "flash_api.h" #include "platform/SingletonPtr.h" @@ -33,14 +33,18 @@ // Export ROM end address #if defined(TOOLCHAIN_GCC_ARM) extern uint32_t __etext; -#define FLASHIAP_ROM_END ((uint32_t) &__etext) +extern uint32_t __data_start__; +extern uint32_t __data_end__; +#define FLASHIAP_APP_ROM_END_ADDR (((uint32_t) &__etext) + ((uint32_t) &__data_end__) - ((uint32_t) &__data_start__)) #elif defined(TOOLCHAIN_ARM) extern uint32_t Load$$LR$$LR_IROM1$$Limit[]; -#define FLASHIAP_ROM_END ((uint32_t)Load$$LR$$LR_IROM1$$Limit) +#define FLASHIAP_APP_ROM_END_ADDR ((uint32_t)Load$$LR$$LR_IROM1$$Limit) #elif defined(TOOLCHAIN_IAR) #pragma section=".rodata" #pragma section=".text" -#define FLASHIAP_ROM_END (std::max((uint32_t) __section_end(".rodata"), (uint32_t) __section_end(".text"))) +#pragma section=".init_array" +#define FLASHIAP_APP_ROM_END_ADDR std::max(std::max((uint32_t) __section_end(".rodata"), (uint32_t) __section_end(".text")), \ + (uint32_t) __section_end(".init_array")) #endif namespace mbed { diff --git a/drivers/I2C.cpp b/drivers/I2C.cpp index 2cdcc49d8c..3e06825c17 100644 --- a/drivers/I2C.cpp +++ b/drivers/I2C.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/I2C.h b/drivers/I2C.h index daca532ef5..9a19bd1247 100644 --- a/drivers/I2C.h +++ b/drivers/I2C.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,7 +20,7 @@ #include "platform/platform.h" #include "hal/gpio_api.h" -#if defined (DEVICE_I2C) || defined(DOXYGEN_ONLY) +#if DEVICE_I2C || defined(DOXYGEN_ONLY) #include "hal/i2c_api.h" #include "platform/SingletonPtr.h" diff --git a/drivers/I2CSlave.cpp b/drivers/I2CSlave.cpp index b29b4e74e2..f0697460be 100644 --- a/drivers/I2CSlave.cpp +++ b/drivers/I2CSlave.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/I2CSlave.h b/drivers/I2CSlave.h index 12d9ce08c7..78715ba934 100644 --- a/drivers/I2CSlave.h +++ b/drivers/I2CSlave.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_I2CSLAVE) || defined(DOXYGEN_ONLY) +#if DEVICE_I2CSLAVE || defined(DOXYGEN_ONLY) #include "hal/i2c_api.h" diff --git a/drivers/InterruptIn.cpp b/drivers/InterruptIn.cpp index 51d947f7a3..a4ab5f0135 100644 --- a/drivers/InterruptIn.cpp +++ b/drivers/InterruptIn.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/InterruptIn.h b/drivers/InterruptIn.h index 85928e3e85..32cc6619ee 100644 --- a/drivers/InterruptIn.h +++ b/drivers/InterruptIn.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY) +#if DEVICE_INTERRUPTIN || defined(DOXYGEN_ONLY) #include "hal/gpio_api.h" #include "hal/gpio_irq_api.h" diff --git a/drivers/InterruptManager.cpp b/drivers/InterruptManager.cpp index f557cf4378..179731b419 100644 --- a/drivers/InterruptManager.cpp +++ b/drivers/InterruptManager.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/InterruptManager.h b/drivers/InterruptManager.h index 6b3c1d086c..8b207f0c5e 100644 --- a/drivers/InterruptManager.h +++ b/drivers/InterruptManager.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/LowPowerTicker.h b/drivers/LowPowerTicker.h index a77307e68b..a6f9fa9401 100644 --- a/drivers/LowPowerTicker.h +++ b/drivers/LowPowerTicker.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/LowPowerTimeout.h b/drivers/LowPowerTimeout.h index 561c4a2201..7198d7dc64 100644 --- a/drivers/LowPowerTimeout.h +++ b/drivers/LowPowerTimeout.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_LPTICKER) || defined(DOXYGEN_ONLY) +#if DEVICE_LPTICKER || defined(DOXYGEN_ONLY) #include "hal/lp_ticker_api.h" #include "drivers/LowPowerTicker.h" diff --git a/drivers/LowPowerTimer.h b/drivers/LowPowerTimer.h index 19bb8fdc3e..abd03dd48e 100644 --- a/drivers/LowPowerTimer.h +++ b/drivers/LowPowerTimer.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,7 +21,7 @@ #include "drivers/Timer.h" #include "platform/NonCopyable.h" -#if defined (DEVICE_LPTICKER) || defined(DOXYGEN_ONLY) +#if DEVICE_LPTICKER || defined(DOXYGEN_ONLY) #include "hal/lp_ticker_api.h" diff --git a/drivers/MbedCRC.cpp b/drivers/MbedCRC.cpp index 34e777a251..6353e052c3 100644 --- a/drivers/MbedCRC.cpp +++ b/drivers/MbedCRC.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/MbedCRC.h b/drivers/MbedCRC.h index 9c7328bd00..9e99e9049f 100644 --- a/drivers/MbedCRC.h +++ b/drivers/MbedCRC.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -100,7 +101,7 @@ class MbedCRC { public: enum CrcMode { -#ifdef DEVICE_CRC +#if DEVICE_CRC HARDWARE = 0, #endif TABLE = 1, @@ -197,7 +198,7 @@ public: int32_t status = 0; switch (_mode) { -#ifdef DEVICE_CRC +#if DEVICE_CRC case HARDWARE: hal_crc_compute_partial((uint8_t *)buffer, size); *crc = 0; @@ -231,7 +232,7 @@ public: { MBED_ASSERT(crc != NULL); -#ifdef DEVICE_CRC +#if DEVICE_CRC if (_mode == HARDWARE) { lock(); crc_mbed_config_t config; @@ -263,7 +264,7 @@ public: { MBED_ASSERT(crc != NULL); -#ifdef DEVICE_CRC +#if DEVICE_CRC if (_mode == HARDWARE) { *crc = hal_crc_get_result(); unlock(); @@ -315,7 +316,7 @@ private: */ void lock() { -#ifdef DEVICE_CRC +#if DEVICE_CRC if (_mode == HARDWARE) { mbed_crc_mutex->lock(); } @@ -326,7 +327,7 @@ private: */ virtual void unlock() { -#ifdef DEVICE_CRC +#if DEVICE_CRC if (_mode == HARDWARE) { mbed_crc_mutex->unlock(); } @@ -502,7 +503,7 @@ private: { MBED_STATIC_ASSERT(width <= 32, "Max 32-bit CRC supported"); -#ifdef DEVICE_CRC +#if DEVICE_CRC if (POLY_32BIT_REV_ANSI == polynomial) { _crc_table = (uint32_t *)Table_CRC_32bit_Rev_ANSI; _mode = TABLE; diff --git a/drivers/PortIn.h b/drivers/PortIn.h index fbecc257e0..f3ae250e98 100644 --- a/drivers/PortIn.h +++ b/drivers/PortIn.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_PORTIN) || defined(DOXYGEN_ONLY) +#if DEVICE_PORTIN || defined(DOXYGEN_ONLY) #include "hal/port_api.h" #include "platform/mbed_critical.h" diff --git a/drivers/PortInOut.h b/drivers/PortInOut.h index 00c972c2a0..2036eba252 100644 --- a/drivers/PortInOut.h +++ b/drivers/PortInOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_PORTINOUT) || defined(DOXYGEN_ONLY) +#if DEVICE_PORTINOUT || defined(DOXYGEN_ONLY) #include "hal/port_api.h" #include "platform/mbed_critical.h" diff --git a/drivers/PortOut.h b/drivers/PortOut.h index 8df644e56c..18a0bcd3c5 100644 --- a/drivers/PortOut.h +++ b/drivers/PortOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_PORTOUT) || defined(DOXYGEN_ONLY) +#if DEVICE_PORTOUT || defined(DOXYGEN_ONLY) #include "hal/port_api.h" #include "platform/mbed_critical.h" diff --git a/drivers/PwmOut.h b/drivers/PwmOut.h index 6d6f847f8f..acdd4a2e66 100644 --- a/drivers/PwmOut.h +++ b/drivers/PwmOut.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY) +#if DEVICE_PWMOUT || defined(DOXYGEN_ONLY) #include "hal/pwmout_api.h" #include "platform/mbed_critical.h" #include "platform/mbed_power_mgmt.h" diff --git a/drivers/QSPI.cpp b/drivers/QSPI.cpp index 9a75d79727..c79c949e3b 100644 --- a/drivers/QSPI.cpp +++ b/drivers/QSPI.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/QSPI.h b/drivers/QSPI.h index 764a1167ff..e247e8f651 100644 --- a/drivers/QSPI.h +++ b/drivers/QSPI.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_QSPI) || defined(DOXYGEN_ONLY) +#if DEVICE_QSPI || defined(DOXYGEN_ONLY) #include "hal/qspi_api.h" #include "platform/PlatformMutex.h" diff --git a/drivers/RawSerial.cpp b/drivers/RawSerial.cpp index 2943bd9520..b473fddae4 100644 --- a/drivers/RawSerial.cpp +++ b/drivers/RawSerial.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/RawSerial.h b/drivers/RawSerial.h index bb06fe4787..4841eb9038 100644 --- a/drivers/RawSerial.h +++ b/drivers/RawSerial.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY) +#if DEVICE_SERIAL || defined(DOXYGEN_ONLY) #include "mbed_toolchain.h" #include "drivers/SerialBase.h" diff --git a/drivers/SPI.cpp b/drivers/SPI.cpp index d679a9c0a8..8ae1ee2f4e 100644 --- a/drivers/SPI.cpp +++ b/drivers/SPI.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/SPI.h b/drivers/SPI.h index 10efc7d0aa..65db21bbb3 100644 --- a/drivers/SPI.h +++ b/drivers/SPI.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_SPI) || defined(DOXYGEN_ONLY) +#if DEVICE_SPI || defined(DOXYGEN_ONLY) #include "platform/PlatformMutex.h" #include "hal/spi_api.h" diff --git a/drivers/SPISlave.cpp b/drivers/SPISlave.cpp index 1f826bb343..db870cdea2 100644 --- a/drivers/SPISlave.cpp +++ b/drivers/SPISlave.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/SPISlave.h b/drivers/SPISlave.h index 6ee9ba6171..878bc8d672 100644 --- a/drivers/SPISlave.h +++ b/drivers/SPISlave.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,7 +20,7 @@ #include "platform/platform.h" #include "platform/NonCopyable.h" -#if defined (DEVICE_SPISLAVE) || defined(DOXYGEN_ONLY) +#if DEVICE_SPISLAVE || defined(DOXYGEN_ONLY) #include "hal/spi_api.h" diff --git a/drivers/Serial.cpp b/drivers/Serial.cpp index 55e5a38bba..d0f87263b6 100644 --- a/drivers/Serial.cpp +++ b/drivers/Serial.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Serial.h b/drivers/Serial.h index 1b1e6aa34e..d19010808d 100644 --- a/drivers/Serial.h +++ b/drivers/Serial.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY) +#if DEVICE_SERIAL || defined(DOXYGEN_ONLY) #include "platform/Stream.h" #include "SerialBase.h" diff --git a/drivers/SerialBase.cpp b/drivers/SerialBase.cpp index c4333d9f97..6557a93e65 100644 --- a/drivers/SerialBase.cpp +++ b/drivers/SerialBase.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/SerialBase.h b/drivers/SerialBase.h index a78d7d0088..b00abe5bae 100644 --- a/drivers/SerialBase.h +++ b/drivers/SerialBase.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include "platform/platform.h" -#if defined (DEVICE_SERIAL) || defined(DOXYGEN_ONLY) +#if DEVICE_SERIAL || defined(DOXYGEN_ONLY) #include "platform/Callback.h" #include "hal/serial_api.h" diff --git a/drivers/SerialWireOutput.h b/drivers/SerialWireOutput.h index 1e90ebc17c..0379687c9b 100644 --- a/drivers/SerialWireOutput.h +++ b/drivers/SerialWireOutput.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/TableCRC.cpp b/drivers/TableCRC.cpp index b6e55aaae8..b0d316e471 100644 --- a/drivers/TableCRC.cpp +++ b/drivers/TableCRC.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/TableCRC.h b/drivers/TableCRC.h index 478bb25958..1ab5bf8365 100644 --- a/drivers/TableCRC.h +++ b/drivers/TableCRC.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Ticker.cpp b/drivers/Ticker.cpp index efa3efb9c0..feb27ef57b 100644 --- a/drivers/Ticker.cpp +++ b/drivers/Ticker.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Ticker.h b/drivers/Ticker.h index 059d6a1792..31ce72cfad 100644 --- a/drivers/Ticker.h +++ b/drivers/Ticker.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Timeout.cpp b/drivers/Timeout.cpp index 159cc0d4b4..42141c4c48 100644 --- a/drivers/Timeout.cpp +++ b/drivers/Timeout.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Timeout.h b/drivers/Timeout.h index f39dcc03d1..c155c9bcec 100644 --- a/drivers/Timeout.h +++ b/drivers/Timeout.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Timer.cpp b/drivers/Timer.cpp index 5a6d7df9e4..b13f86ce90 100644 --- a/drivers/Timer.cpp +++ b/drivers/Timer.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/Timer.h b/drivers/Timer.h index 9cc3586d98..010f6019b5 100644 --- a/drivers/Timer.h +++ b/drivers/Timer.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/TimerEvent.cpp b/drivers/TimerEvent.cpp index 9c5174dc72..9c77eb86f5 100644 --- a/drivers/TimerEvent.cpp +++ b/drivers/TimerEvent.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/TimerEvent.h b/drivers/TimerEvent.h index 87e2481cf2..88f4c3b750 100644 --- a/drivers/TimerEvent.h +++ b/drivers/TimerEvent.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/UARTSerial.cpp b/drivers/UARTSerial.cpp index 845f0a19e8..2f317b5310 100644 --- a/drivers/UARTSerial.cpp +++ b/drivers/UARTSerial.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/drivers/UARTSerial.h b/drivers/UARTSerial.h index 792d3e0f36..2a47da1a38 100644 --- a/drivers/UARTSerial.h +++ b/drivers/UARTSerial.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/events/Event.h b/events/Event.h index dd0d8e6cf3..a8a2ff6234 100644 --- a/events/Event.h +++ b/events/Event.h @@ -1,5 +1,6 @@ /* events * Copyright (c) 2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/events/EventQueue.cpp b/events/EventQueue.cpp index f04917c4ef..3cd89a6b23 100644 --- a/events/EventQueue.cpp +++ b/events/EventQueue.cpp @@ -1,5 +1,6 @@ /* events * Copyright (c) 2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/events/EventQueue.h b/events/EventQueue.h index 02d3d31da1..c5d7ef1f55 100644 --- a/events/EventQueue.h +++ b/events/EventQueue.h @@ -1,5 +1,6 @@ /* events * Copyright (c) 2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/events/equeue/equeue.c b/events/equeue/equeue.c index 4d985539da..942f62cf49 100644 --- a/events/equeue/equeue.c +++ b/events/equeue/equeue.c @@ -108,13 +108,15 @@ void equeue_destroy(equeue_t *q) { // call destructors on pending events for (struct equeue_event *es = q->queue; es; es = es->next) { - for (struct equeue_event *e = q->queue; e; e = e->sibling) { + for (struct equeue_event *e = es->sibling; e; e = e->sibling) { if (e->dtor) { e->dtor(e + 1); } } + if (es->dtor) { + es->dtor(es + 1); + } } - // notify background timer if (q->background.update) { q->background.update(q->background.timer, -1); @@ -239,8 +241,8 @@ static int equeue_enqueue(equeue_t *q, struct equeue_event *e, unsigned tick) if (e->next) { e->next->ref = &e->next; } - e->sibling = *p; + e->sibling->next = 0; e->sibling->ref = &e->sibling; } else { e->next = *p; diff --git a/events/equeue/tests/tests.c b/events/equeue/tests/tests.c index 547255b2c4..96f1842962 100644 --- a/events/equeue/tests/tests.c +++ b/events/equeue/tests/tests.c @@ -779,6 +779,29 @@ void break_request_cleared_on_timeout(void) equeue_destroy(&q); } +void sibling_test(void) +{ + equeue_t q; + int err = equeue_create(&q, 1024); + test_assert(!err); + + int id0 = equeue_call_in(&q, 1, pass_func, 0); + int id1 = equeue_call_in(&q, 1, pass_func, 0); + int id2 = equeue_call_in(&q, 1, pass_func, 0); + + struct equeue_event *e = q.queue; + + for (; e; e = e->next) { + for (struct equeue_event *s = e->sibling; s; s = s->sibling) { + test_assert(!s->next); + } + } + equeue_cancel(&q, id0); + equeue_cancel(&q, id1); + equeue_cancel(&q, id2); + equeue_destroy(&q); +} + int main() { printf("beginning tests...\n"); @@ -806,7 +829,7 @@ int main() test_run(fragmenting_barrage_test, 20); test_run(multithreaded_barrage_test, 20); test_run(break_request_cleared_on_timeout); - + test_run(sibling_test); printf("done!\n"); return test_failure; } diff --git a/events/mbed_events.h b/events/mbed_events.h index 341bf16087..466b82bb17 100644 --- a/events/mbed_events.h +++ b/events/mbed_events.h @@ -3,6 +3,7 @@ /** @{*/ /* events * Copyright (c) 2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/features/FEATURE_BLE/ble/common/Duration.h b/features/FEATURE_BLE/ble/common/Duration.h index 70e6c559e8..5441f7a057 100644 --- a/features/FEATURE_BLE/ble/common/Duration.h +++ b/features/FEATURE_BLE/ble/common/Duration.h @@ -86,7 +86,7 @@ struct Value { * Model BLE durations. * * @tparam Rep The representation type of the duration. - * @tparam TB The time base in us. + * @tparam TB The time base in micro seconds. * @tparam Range Closed interval of the duration * @tparam Forever The special value (if applicable) that represents a forever * duration. @@ -115,7 +115,7 @@ struct Duration { /** * Construct a Duration from an integer value. * - * @param v The value of the duration in TN units. + * @param v The value of the duration in TIME_BASE units. */ explicit Duration(Rep v) : duration(clamp(v)) { @@ -124,10 +124,10 @@ struct Duration { /** * Construct a Duration from another Duration. * - * @note The operation fail at compile time of there is a loss of precision. + * @note The operation fail at compile time if there is a loss of precision. * * @tparam OtherRep The type used to represent the other Duration. - * @tparam OtherTB The time base in us units of the other Duration. + * @tparam OtherTB The time base in micro seconds of the other Duration. * @tparam OtherRange The range of the other Duration. * @tparam OtherF The forever value of the other type. * @@ -149,7 +149,7 @@ struct Duration { * @tparam OtherRange The range used by other_ms. * @tparam OtherF The forever value used by other_ms. * - * @param other_ms The Duration in ms to convert. + * @param other_ms The Duration in millisecond to convert. */ template explicit Duration(Duration other_ms, void* = NULL) : @@ -270,7 +270,7 @@ typedef Duration second_t; * @tparam RangeIn The range of duration. * @tparam FIn The Forever value of duration. * @param duration The duration to convert. - * @return The converted duration. It is rounded up if precision is loss. + * @return The converted duration. It is rounded up if precision is lost. * * @related Duration */ diff --git a/features/FEATURE_BLE/ble/gap/ScanParameters.h b/features/FEATURE_BLE/ble/gap/ScanParameters.h index 9eb9c610bc..778f0ba91e 100644 --- a/features/FEATURE_BLE/ble/gap/ScanParameters.h +++ b/features/FEATURE_BLE/ble/gap/ScanParameters.h @@ -41,8 +41,8 @@ namespace ble { * same value. * * To get extra data from the advertising device, the scanner can send scan - * requests to the advertiser that respond with a scan response. It is possible - * to select what type of address is used to issue the scan request. + * requests to the advertiser; the advertiser may respond with scan responses. + * It is possible to select what type of address is used to issue the scan request. * * With Bluetooth 5, devices can advertise on more physical channels, and by * extension, they can scan on more physical channels. It is possible to define diff --git a/features/FEATURE_BLE/source/BLE.cpp b/features/FEATURE_BLE/source/BLE.cpp index 8a631bbb76..6e95af82c4 100644 --- a/features/FEATURE_BLE/source/BLE.cpp +++ b/features/FEATURE_BLE/source/BLE.cpp @@ -29,7 +29,7 @@ #if !defined(YOTTA_CFG_MBED_OS) #include -#include +#include #endif #if defined(__GNUC__) && !defined(__CC_ARM) diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp index 57c02f8c3d..8a096aab26 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/source/CordioGattServer.cpp @@ -596,14 +596,10 @@ ble_error_t GattServer::write( uint16_t cccd_value; memcpy(&cccd_value, buffer, sizeof(cccd_value)); - uint16_t conn_id = 0; - uint16_t conn_found = 0; - while ((conn_found < DM_CONN_MAX) && (conn_id < CONNECTION_ID_LIMIT)) { + for (dmConnId_t conn_id = DM_CONN_MAX; conn_id > DM_CONN_ID_NONE; --conn_id) { if (DmConnInUse(conn_id) == true) { - ++conn_found; AttsCccSet(conn_id, cccd_index, cccd_value); } - ++conn_id; } return BLE_ERROR_NONE; @@ -622,13 +618,10 @@ ble_error_t GattServer::write( // This characteristic has a CCCD attribute. Handle notifications and // indications for all active connections if the authentication is // successful - uint16_t conn_id = 0; - uint16_t conn_found = 0; size_t updates_sent = 0; - while((conn_found < DM_CONN_MAX) && (conn_id < CONNECTION_ID_LIMIT)) { + for (dmConnId_t conn_id = DM_CONN_MAX; conn_id > DM_CONN_ID_NONE; --conn_id) { if (DmConnInUse(conn_id) == true) { - ++conn_found; if (is_update_authorized(conn_id, att_handle)) { uint16_t cccd_config = AttsCccEnabled(conn_id, cccd_index); if (cccd_config & ATT_CLIENT_CFG_NOTIFY) { @@ -641,7 +634,6 @@ ble_error_t GattServer::write( } } } - ++conn_id; } if (updates_sent) { @@ -709,12 +701,8 @@ ble_error_t GattServer::areUpdatesEnabled( ) { for (size_t idx = 0; idx < cccd_cnt; idx++) { if (characteristic.getValueHandle() == cccd_handles[idx]) { - uint16_t conn_id = 0; - uint16_t conn_found = 0; - - while ((conn_found < DM_CONN_MAX) && (conn_id < CONNECTION_ID_LIMIT)) { + for (dmConnId_t conn_id = DM_CONN_MAX; conn_id > DM_CONN_ID_NONE; --conn_id) { if (DmConnInUse(conn_id) == true) { - ++conn_found; uint16_t cccd_value = AttsCccGet(conn_id, idx); if (cccd_value & (ATT_CLIENT_CFG_NOTIFY | ATT_CLIENT_CFG_INDICATE)) { *enabled = true; @@ -722,7 +710,6 @@ ble_error_t GattServer::areUpdatesEnabled( } } - ++conn_id; } *enabled = false; return BLE_ERROR_NONE; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF51/source/nRF5xGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF51/source/nRF5xGattServer.cpp index 4963145059..619e199896 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF51/source/nRF5xGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF51/source/nRF5xGattServer.cpp @@ -664,6 +664,7 @@ void nRF5xGattServer::hwCallback(const ble_evt_t *p_ble_evt) * set to AUTH_CALLBACK_REPLY_SUCCESS if the client * request is to proceed. */ }; + characteristicIndex = resolveValueHandleToCharIndex(req->attr_handle); uint16_t write_authorization = p_characteristics[characteristicIndex]->authorizeWrite(&cbParams); // the user code didn't provide the write authorization, diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xGattServer.cpp index 8c93ac118c..821ee59e54 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_SOFTDEVICE/TARGET_NRF52/source/nRF5xGattServer.cpp @@ -670,6 +670,7 @@ void nRF5xGattServer::hwCallback(const ble_evt_t *p_ble_evt) * set to AUTH_CALLBACK_REPLY_SUCCESS if the client * request is to proceed. */ }; + characteristicIndex = resolveValueHandleToCharIndex(req->attr_handle); uint16_t write_authorization = p_characteristics[characteristicIndex]->authorizeWrite(&cbParams); // the user code didn't provide the write authorization, diff --git a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/LICENSE b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/LICENSE new file mode 100644 index 0000000000..591ac29615 --- /dev/null +++ b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/LICENSE @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, September 2015 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named "DEPENDENCIES" and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/mbed-bootloader-nucleo_f439zi-block_device-sotp-v3_4_0.bin b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/mbed-bootloader-nucleo_f439zi-block_device-sotp-v3_4_0.bin new file mode 100644 index 0000000000..27b7049bc1 Binary files /dev/null and b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/mbed-bootloader-nucleo_f439zi-block_device-sotp-v3_4_0.bin differ diff --git a/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/mbed_lib.json b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/mbed_lib.json new file mode 100644 index 0000000000..d5bd34e177 --- /dev/null +++ b/features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/mbed_lib.json @@ -0,0 +1,10 @@ +{ + "name": "bootloader_NUCLEO_F439ZI", + "target_overrides": { + "*": { + "target.app_offset": "0x10400", + "target.header_offset": "0x10000", + "target.bootloader_img": "mbed-bootloader-nucleo_f439zi-block_device-sotp-v3_4_0.bin" + } + } +} diff --git a/features/cellular/framework/API/CellularContext.h b/features/cellular/framework/API/CellularContext.h index 9107d585e6..0e3cdaa4b5 100644 --- a/features/cellular/framework/API/CellularContext.h +++ b/features/cellular/framework/API/CellularContext.h @@ -98,7 +98,7 @@ public: // pointer for next item when used as a linked list CellularContext *_next; protected: - // friend of CellularDevice so that it's the only way to close/delete this class. + // friend of CellularDevice, so it's the only way to close or delete this class. friend class CellularDevice; virtual ~CellularContext() {} @@ -106,6 +106,16 @@ public: // from NetworkInterface virtual nsapi_error_t set_blocking(bool blocking) = 0; virtual NetworkStack *get_stack() = 0; virtual const char *get_ip_address() = 0; + + /** Register callback for status reporting. + * + * The specified status callback function is called on the network, and the cellular device status changes. + * The parameters on the callback are the event type and event type dependent reason parameter. + * + * @remark deleting CellularDevice/CellularContext in callback is not allowed. + * + * @param status_cb The callback for status changes. + */ virtual void attach(mbed::Callback status_cb) = 0; virtual nsapi_error_t connect() = 0; virtual nsapi_error_t disconnect() = 0; @@ -122,13 +132,13 @@ public: // from NetworkInterface static CellularContext *get_default_instance(); -// Operations, can be sync/async. Also Connect() is this kind of operations, inherited from NetworkInterface above. +// Operations, can be sync/async. Also Connect() is this kind of operation, inherited from NetworkInterface above. /** Start the interface * - * Power on the device and does the initializations for communication with the modem.. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with + * Powers on the device and does the initializations for communication with the modem. + * By default, this API is synchronous. API can be set to asynchronous with method set_blocking(...). + * In synchronous and asynchronous mode, the application can get result in from callback, which is set with * attach(...) * * @return NSAPI_ERROR_OK on success @@ -138,9 +148,9 @@ public: // from NetworkInterface /** Start the interface * - * Attempts to open the sim. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with + * Attempts to open the SIM. + * By default, this API is synchronous. API can be set to asynchronous with method set_blocking(...). + * In synchronous and asynchronous mode, the application can get result in from callback, which is set with * attach(...) * * @return NSAPI_ERROR_OK on success @@ -151,8 +161,8 @@ public: // from NetworkInterface /** Start the interface * * Attempts to register the device to cellular network. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with + * By default, this API is synchronous. API can be set to asynchronous with method set_blocking(...). + * In synchronous and asynchronous mode, the application can get result in from callback, which is set with * attach(...) * * @return NSAPI_ERROR_OK on success @@ -163,8 +173,8 @@ public: // from NetworkInterface /** Start the interface * * Attempts to attach the device to cellular network. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with + * By default, this API is synchronous. API can be set to asynchronous with method set_blocking(...). + * In synchronous and asynchronous mode, the application can get result in from callback, which is set with * attach(...) * * @return NSAPI_ERROR_OK on success @@ -186,7 +196,7 @@ public: // from NetworkInterface virtual nsapi_error_t get_rate_control(CellularContext::RateControlExceptionReports &reports, CellularContext::RateControlUplinkTimeUnit &time_unit, int &uplink_rate) = 0; - /** Get the relevant information for an active non secondary PDP context. + /** Get the relevant information for an active nonsecondary PDP context. * * @remark optional params are not updated if not received from network. * @param params_list reference to linked list, which is filled on successful call @@ -205,7 +215,7 @@ public: // from NetworkInterface */ virtual nsapi_error_t get_apn_backoff_timer(int &backoff_timer) = 0; - /** Set the file handle used to communicate with the modem. Can be used to change default file handle. + /** Set the file handle used to communicate with the modem. You can use this to change the default file handle. * * @param fh file handle for communicating with the modem */ @@ -222,8 +232,7 @@ protected: // Device specific implementations might need these so protected OP_MAX = 5 }; - /** Status callback function will be called on status changes on the network or CellularDevice - * by the CellularDevice. + /** The CellularDevice calls the status callback function on status changes on the network or CellularDevice. * * @param ev event type * @param ptr event-type dependent reason parameter diff --git a/features/cellular/framework/API/CellularDevice.h b/features/cellular/framework/API/CellularDevice.h index 4dc952f863..e42bad08e6 100644 --- a/features/cellular/framework/API/CellularDevice.h +++ b/features/cellular/framework/API/CellularDevice.h @@ -20,6 +20,7 @@ #include "CellularTargets.h" #include "CellularStateMachine.h" +#include "Callback.h" namespace mbed { @@ -38,13 +39,13 @@ const int MAX_PLMN_SIZE = 16; * Class CellularDevice * * An abstract interface that defines opening and closing of cellular interfaces. - * Deleting/Closing of opened interfaces can be done only via this class. + * You can delete or close opened interfaces only through this class. */ class CellularDevice { public: - /** Return singleton instance of CellularDevice if CELLULAR_DEVICE is defined. If CELLULAR_DEVICE is not - * defined then returns NULL. Implementation is marked as weak. + /** Returns singleton instance of CellularDevice if CELLULAR_DEVICE is defined. If CELLULAR_DEVICE is not + * defined, then it returns NULL. Implementation is marked as weak. * * @return CellularDevice* instance if any */ @@ -62,7 +63,7 @@ public: /** Creates a new CellularContext interface. * - * @param fh file handle used in communication to modem. Can be for example UART handle. If null then the default + * @param fh file handle used in communication to modem. This can be, for example, UART handle. If null, then the default * file handle is used. * @param apn access point to use with context, can be null. * @@ -94,8 +95,8 @@ public: void set_sim_pin(const char *sim_pin); /** Plmn to use when registering to cellular network. - * If plmn is set then registering is forced to this plmn. If plmn is not set then automatic - * registering is used when registering to a cellular network. Does not start any operations. + * If plmn is set, then registering is forced to this plmn. If plmn is not set, then automatic + * registering is used when registering to a cellular network. It doesn't start any operations. * * @param plmn plmn used when registering to cellular network */ @@ -103,10 +104,9 @@ public: /** Start the interface * - * Power on the device and does the initializations for communication with the modem.. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with - * attach(...) + * Powers on the device and does the initializations for communication with the modem. + * API is asynchronous. Application can get results from CellularContext callback, which is set + * with attach(...), or callback, which is set by attach(...), in this class. * * @return NSAPI_ERROR_OK on success * NSAPI_ERROR_NO_MEMORY on case of memory failure @@ -116,9 +116,8 @@ public: /** Start the interface * * Attempts to open the sim. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with - * attach(...) + * API is asynchronous. Application can get results from CellularContext callback, which is set + * with attach(...), or callback, which is set by attach(...), in this class. * * @return NSAPI_ERROR_OK on success * NSAPI_ERROR_NO_MEMORY on case of memory failure @@ -128,9 +127,8 @@ public: /** Start the interface * * Attempts to register the device to cellular network. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with - * attach(...) + * API is asynchronous. Application can get results from CellularContext callback, which is set + * with attach(...), or callback, which is set by attach(...), in this class. * * @return NSAPI_ERROR_OK on success * NSAPI_ERROR_NO_MEMORY on case of memory failure @@ -140,18 +138,30 @@ public: /** Start the interface * * Attempts to attach the device to cellular network. - * By default this API is synchronous. API can be set to asynchronous with method set_blocking(...). - * In synchronous and asynchronous mode application can get result in from callback which is set with - * attach(...) + * API is asynchronous. Application can get results from CellularContext callback, which is set + * with attach(...), or callback, which is set by attach(...), in this class. * * @return NSAPI_ERROR_OK on success * NSAPI_ERROR_NO_MEMORY on case of memory failure */ nsapi_error_t attach_to_network(); + /** Register callback for status reporting. + * + * The specified status callback function is called on the network, and the cellular device status changes. + * The parameters on the callback are the event type and event type dependent reason parameter. + * + * @remark deleting CellularDevice/CellularContext in callback is not allowed. + * @remark application should not attach to this function if it uses CellularContext::attach because it contains the + * same information. + * + * @param status_cb The callback for status changes. + */ + void attach(Callback status_cb); + /** Create new CellularNetwork interface. * - * @param fh file handle used in communication to modem. Can be for example UART handle. If null then the default + * @param fh file handle used in communication to modem. This can be, for example, UART handle. If null, then the default * file handle is used. * @return New instance of interface CellularNetwork. */ @@ -159,7 +169,7 @@ public: /** Create new CellularSMS interface. * - * @param fh file handle used in communication to modem. Can be for example UART handle. If null then the default + * @param fh file handle used in communication to modem. This can be, for example, UART handle. If null, then the default * file handle is used. * @return New instance of interface CellularSMS. */ @@ -167,7 +177,7 @@ public: /** Create new CellularPower interface. * - * @param fh file handle used in communication to modem. Can be for example UART handle. If null then the default + * @param fh file handle used in communication to modem. This can be, for example, UART handle. If null, then the default * file handle is used. * @return New instance of interface CellularPower. */ @@ -175,7 +185,7 @@ public: /** Create new CellularSIM interface. * - * @param fh file handle used in communication to modem. Can be for example UART handle. If null then the default + * @param fh file handle used in communication to modem. This can be, for example, UART handle. If null, then the default * file handle is used. * @return New instance of interface CellularSIM. */ @@ -183,7 +193,7 @@ public: /** Create new CellularInformation interface. * - * @param fh file handle used in communication to modem. Can be for example UART handle. If null then the default + * @param fh file handle used in communication to modem. This can be, for example, UART handle. If null, then the default * file handle is used. * @return New instance of interface CellularInformation. */ @@ -266,6 +276,7 @@ private: char _sim_pin[MAX_PIN_SIZE + 1]; char _plmn[MAX_PLMN_SIZE + 1]; PlatformMutex _mutex; + Callback _status_cb; }; } // namespace mbed diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index b1463f5d58..26129793f4 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -467,7 +467,7 @@ ssize_t ATHandler::read_string(char *buf, size_t size, bool read_even_stop_tag) return -1; } - int len = 0; + unsigned int len = 0; size_t match_pos = 0; bool delimiter_found = false; @@ -952,25 +952,31 @@ bool ATHandler::consume_char(char ch) bool ATHandler::consume_to_tag(const char *tag, bool consume_tag) { size_t match_pos = 0; + size_t tag_length = strlen(tag); while (true) { int c = get_char(); if (c == -1) { - break; - // compares c against tag at current position and if this match fails - // compares c against tag[0] and also resets match_pos to 0 - } else if (c == tag[match_pos] || ((match_pos = 1) && (c == tag[--match_pos]))) { + tr_debug("consume_to_tag not found"); + return false; + } + if (c == tag[match_pos]) { match_pos++; - if (match_pos == strlen(tag)) { - if (!consume_tag) { - _recv_pos -= strlen(tag); - } - return true; + } else if (match_pos != 0) { + match_pos = 0; + if (c == tag[match_pos]) { + match_pos++; } } + if (match_pos == tag_length) { + break; + } } - tr_debug("consume_to_tag not found"); - return false; + + if (!consume_tag) { + _recv_pos -= tag_length; + } + return true; } bool ATHandler::consume_to_stop_tag() diff --git a/features/cellular/framework/AT/AT_CellularNetwork.cpp b/features/cellular/framework/AT/AT_CellularNetwork.cpp index 6c84f08355..d04de64d09 100644 --- a/features/cellular/framework/AT/AT_CellularNetwork.cpp +++ b/features/cellular/framework/AT/AT_CellularNetwork.cpp @@ -161,9 +161,17 @@ void AT_CellularNetwork::read_reg_params_and_compare(RegistrationType type) _connection_status_cb((nsapi_event_t)CellularRadioAccessTechnologyChanged, (intptr_t)&data); } if (reg_params._status != _reg_params._status) { + RegistrationStatus previous_registration_status = _reg_params._status; _reg_params._status = reg_params._status; data.status_data = reg_params._status; _connection_status_cb((nsapi_event_t)CellularRegistrationStatusChanged, (intptr_t)&data); + if (!(reg_params._status == RegisteredHomeNetwork || + reg_params._status == RegisteredRoaming)) { + if (previous_registration_status == RegisteredHomeNetwork || + previous_registration_status == RegisteredRoaming) { + _connection_status_cb(NSAPI_EVENT_CONNECTION_STATUS_CHANGE, NSAPI_STATUS_DISCONNECTED); + } + } } if (reg_params._cell_id != -1 && reg_params._cell_id != _reg_params._cell_id) { _reg_params._cell_id = reg_params._cell_id; diff --git a/features/cellular/framework/device/CellularDevice.cpp b/features/cellular/framework/device/CellularDevice.cpp index 6ad46ddc67..bb623fe501 100644 --- a/features/cellular/framework/device/CellularDevice.cpp +++ b/features/cellular/framework/device/CellularDevice.cpp @@ -51,7 +51,7 @@ MBED_WEAK CellularDevice *CellularDevice::get_default_instance() #endif // CELLULAR_DEVICE CellularDevice::CellularDevice(FileHandle *fh) : _network_ref_count(0), _sms_ref_count(0), _power_ref_count(0), _sim_ref_count(0), - _info_ref_count(0), _fh(fh), _queue(5 * EVENTS_EVENT_SIZE), _state_machine(0), _nw(0) + _info_ref_count(0), _fh(fh), _queue(5 * EVENTS_EVENT_SIZE), _state_machine(0), _nw(0), _status_cb(0) { set_sim_pin(NULL); set_plmn(NULL); @@ -158,6 +158,11 @@ nsapi_error_t CellularDevice::start_state_machine(CellularStateMachine::Cellular return err; } +void CellularDevice::attach(Callback status_cb) +{ + _status_cb = status_cb; +} + void CellularDevice::cellular_callback(nsapi_event_t ev, intptr_t ptr) { if (ev >= NSAPI_EVENT_CELLULAR_STATUS_BASE && ev <= NSAPI_EVENT_CELLULAR_STATUS_END) { @@ -200,6 +205,11 @@ void CellularDevice::cellular_callback(nsapi_event_t ev, intptr_t ptr) curr->cellular_callback(ev, ptr); curr = curr->_next; } + + // forward to callback function if set by attach(...) + if (_status_cb) { + _status_cb(ev, ptr); + } } } // namespace mbed diff --git a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp index 5b59dd9a9b..1dd1e58cf9 100644 --- a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp +++ b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.cpp @@ -16,7 +16,6 @@ */ #include "GEMALTO_CINTERION_CellularNetwork.h" -#include "GEMALTO_CINTERION_Module.h" #include "GEMALTO_CINTERION_CellularContext.h" #include "GEMALTO_CINTERION.h" #include "AT_CellularInformation.h" @@ -28,6 +27,8 @@ using namespace events; const uint16_t RESPONSE_TO_SEND_DELAY = 100; // response-to-send delay in milliseconds at bit-rate over 9600 +GEMALTO_CINTERION::Module GEMALTO_CINTERION::_module; + GEMALTO_CINTERION::GEMALTO_CINTERION(FileHandle *fh) : AT_CellularDevice(fh) { } @@ -59,10 +60,60 @@ nsapi_error_t GEMALTO_CINTERION::init_module() tr_error("Cellular model not found!"); return NSAPI_ERROR_DEVICE_ERROR; } - return GEMALTO_CINTERION_Module::detect_model(model); + + if (memcmp(model, "ELS61", sizeof("ELS61") - 1) == 0) { + init_module_els61(); + } else if (memcmp(model, "BGS2", sizeof("BGS2") - 1) == 0) { + init_module_bgs2(); + } else if (memcmp(model, "EMS31", sizeof("EMS31") - 1) == 0) { + init_module_ems31(); + } else { + tr_error("Cinterion model unsupported %s", model); + return NSAPI_ERROR_UNSUPPORTED; + } + tr_info("Cinterion model %s (%d)", model, _module); + + return NSAPI_ERROR_OK; } uint16_t GEMALTO_CINTERION::get_send_delay() const { return RESPONSE_TO_SEND_DELAY; } + +GEMALTO_CINTERION::Module GEMALTO_CINTERION::get_module() +{ + return _module; +} + +void GEMALTO_CINTERION::init_module_bgs2() +{ + // BGS2-W_ATC_V00.100 + static const AT_CellularBase::SupportedFeature unsupported_features[] = { + AT_CellularBase::AT_CGSN_WITH_TYPE, + AT_CellularBase::SUPPORTED_FEATURE_END_MARK + }; + AT_CellularBase::set_unsupported_features(unsupported_features); + _module = ModuleBGS2; +} + +void GEMALTO_CINTERION::init_module_els61() +{ + // ELS61-E2_ATC_V01.000 + static const AT_CellularBase::SupportedFeature unsupported_features[] = { + AT_CellularBase::AT_CGSN_WITH_TYPE, + AT_CellularBase::SUPPORTED_FEATURE_END_MARK + }; + AT_CellularBase::set_unsupported_features(unsupported_features); + _module = ModuleELS61; +} + +void GEMALTO_CINTERION::init_module_ems31() +{ + // EMS31-US_ATC_V4.9.5 + static const AT_CellularBase::SupportedFeature unsupported_features[] = { + AT_CellularBase::SUPPORTED_FEATURE_END_MARK + }; + AT_CellularBase::set_unsupported_features(unsupported_features); + _module = ModuleEMS31; +} diff --git a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.h b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.h index 137641f0f6..2a58da242b 100644 --- a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.h +++ b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION.h @@ -34,6 +34,23 @@ protected: // AT_CellularDevice public: virtual nsapi_error_t init_module(); virtual uint16_t get_send_delay() const; + + /** Actual model of cellular module is needed to make AT command adaptation at runtime + * to support many different models in one cellular driver. + */ + enum Module { + ModuleUnknown = 0, + ModuleELS61, + ModuleBGS2, + ModuleEMS31, + }; + static Module get_module(); + +private: + static Module _module; + void init_module_bgs2(); + void init_module_els61(); + void init_module_ems31(); }; } // namespace mbed diff --git a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp index 322f53e1c7..bce1fb077d 100644 --- a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp +++ b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularContext.cpp @@ -16,7 +16,7 @@ */ #include "GEMALTO_CINTERION_CellularContext.h" #include "GEMALTO_CINTERION_CellularStack.h" -#include "GEMALTO_CINTERION_Module.h" +#include "GEMALTO_CINTERION.h" namespace mbed { @@ -41,7 +41,7 @@ NetworkStack *GEMALTO_CINTERION_CellularContext::get_stack() bool GEMALTO_CINTERION_CellularContext::stack_type_supported(nsapi_ip_stack_t requested_stack) { - if (GEMALTO_CINTERION_Module::get_model() == GEMALTO_CINTERION_Module::ModelBGS2) { + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleBGS2) { return (requested_stack == IPV4_STACK); } return (requested_stack == IPV4_STACK || requested_stack == IPV6_STACK); diff --git a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp index 65f944fc1d..baf4b47be7 100644 --- a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp +++ b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularNetwork.cpp @@ -16,7 +16,7 @@ */ #include "GEMALTO_CINTERION_CellularNetwork.h" -#include "GEMALTO_CINTERION_Module.h" +#include "GEMALTO_CINTERION.h" using namespace mbed; @@ -30,10 +30,10 @@ GEMALTO_CINTERION_CellularNetwork::~GEMALTO_CINTERION_CellularNetwork() AT_CellularNetwork::RegistrationMode GEMALTO_CINTERION_CellularNetwork::has_registration(RegistrationType reg_type) { - if (GEMALTO_CINTERION_Module::get_model() == GEMALTO_CINTERION_Module::ModelEMS31) { + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleEMS31) { return (reg_type == C_EREG) ? RegistrationModeLAC : RegistrationModeDisable; } - if (GEMALTO_CINTERION_Module::get_model() == GEMALTO_CINTERION_Module::ModelBGS2) { + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleBGS2) { if (reg_type == C_GREG) { return RegistrationModeEnable; } diff --git a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp index 1c0128ea91..14fb6543fc 100644 --- a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp +++ b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_CellularStack.cpp @@ -17,7 +17,7 @@ #include #include "GEMALTO_CINTERION_CellularStack.h" -#include "GEMALTO_CINTERION_Module.h" +#include "GEMALTO_CINTERION.h" #include "CellularLog.h" // defines as per ELS61-E2_ATC_V01.000 and BGS2-W_ATC_V00.100 @@ -91,7 +91,7 @@ void GEMALTO_CINTERION_CellularStack::sisw_urc_handler(int sock_id, int urc_code if (urc_code == 1) { // ready if (sock->_cb) { sock->tx_ready = true; - if (sock->proto == NSAPI_TCP || GEMALTO_CINTERION_Module::get_model() == GEMALTO_CINTERION_Module::ModelBGS2) { + if (sock->proto == NSAPI_TCP || GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleBGS2) { sock->started = true; } sock->_cb(sock->_data); @@ -180,7 +180,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::socket_open_defer(CellularSocket char sock_addr[sizeof("sockudp://") - 1 + NSAPI_IPv6_SIZE + sizeof("[]:12345;port=12345") - 1 + 1]; if (socket->proto == NSAPI_UDP) { - if (GEMALTO_CINTERION_Module::get_model() != GEMALTO_CINTERION_Module::ModelBGS2) { + if (GEMALTO_CINTERION::get_module() != GEMALTO_CINTERION::ModuleBGS2) { std::sprintf(sock_addr, "sockudp://%s:%u", address ? address->get_ip_address() : "", socket->localAddress.get_port()); } else { std::sprintf(sock_addr, "sockudp://%s:%u;port=%u", address->get_ip_address(), address->get_port(), socket->localAddress.get_port()); @@ -286,7 +286,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::create_socket_impl(CellularSocket } if (socket->proto == NSAPI_UDP) { - if (GEMALTO_CINTERION_Module::get_model() != GEMALTO_CINTERION_Module::ModelBGS2) { + if (GEMALTO_CINTERION::get_module() != GEMALTO_CINTERION::ModuleBGS2) { return socket_open_defer(socket); } } @@ -306,7 +306,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_sendto_impl(Cellul } } - if (socket->proto == NSAPI_UDP && GEMALTO_CINTERION_Module::get_model() == GEMALTO_CINTERION_Module::ModelBGS2) { + if (socket->proto == NSAPI_UDP && GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleBGS2) { tr_debug("Send addr %s, prev addr %s", address.get_ip_address(), socket->remoteAddress.get_ip_address()); if (address != socket->remoteAddress) { if (socket->started) { @@ -349,7 +349,7 @@ nsapi_size_or_error_t GEMALTO_CINTERION_CellularStack::socket_sendto_impl(Cellul _at.write_int(socket->id); _at.write_int(size); - if (GEMALTO_CINTERION_Module::get_model() != GEMALTO_CINTERION_Module::ModelBGS2) { + if (GEMALTO_CINTERION::get_module() != GEMALTO_CINTERION::ModuleBGS2) { _at.write_int(0); // UDP requires Udp_RemClient @@ -466,7 +466,7 @@ sisr_retry: } // UDP Udp_RemClient - if (socket->proto == NSAPI_UDP && GEMALTO_CINTERION_Module::get_model() != GEMALTO_CINTERION_Module::ModelBGS2) { + if (socket->proto == NSAPI_UDP && GEMALTO_CINTERION::get_module() != GEMALTO_CINTERION::ModuleBGS2) { char ip_address[NSAPI_IPv6_SIZE + sizeof("[]:12345") - 1 + 1]; int ip_len = _at.read_string(ip_address, sizeof(ip_address)); if (ip_len <= 0) { @@ -513,7 +513,7 @@ sisr_retry: // setup internet connection profile for sockets nsapi_error_t GEMALTO_CINTERION_CellularStack::create_connection_profile(int connection_profile_id) { - if (GEMALTO_CINTERION_Module::get_model() == GEMALTO_CINTERION_Module::ModelEMS31) { + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleEMS31) { // EMS31 connection has only DNS settings and there is no need to modify those here for now return NSAPI_ERROR_OK; } @@ -579,7 +579,7 @@ nsapi_error_t GEMALTO_CINTERION_CellularStack::create_connection_profile(int con void GEMALTO_CINTERION_CellularStack::close_connection_profile(int connection_profile_id) { - if (GEMALTO_CINTERION_Module::get_model() == GEMALTO_CINTERION_Module::ModelEMS31) { + if (GEMALTO_CINTERION::get_module() == GEMALTO_CINTERION::ModuleEMS31) { return; } diff --git a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_Module.cpp b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_Module.cpp deleted file mode 100644 index 0f52bfcbe8..0000000000 --- a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_Module.cpp +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#include "AT_CellularBase.h" -#include "GEMALTO_CINTERION_Module.h" -#include "CellularLog.h" - -using namespace mbed; - -// unsupported features as per ELS61-E2_ATC_V01.000 -static const AT_CellularBase::SupportedFeature unsupported_features_els61[] = { - AT_CellularBase::AT_CGSN_WITH_TYPE, - AT_CellularBase::SUPPORTED_FEATURE_END_MARK -}; - -// unsupported features as per BGS2-W_ATC_V00.100 -static const AT_CellularBase::SupportedFeature unsupported_features_bgs2[] = { - AT_CellularBase::AT_CGSN_WITH_TYPE, - AT_CellularBase::SUPPORTED_FEATURE_END_MARK -}; - -// unsupported features as per EMS31-US_ATC_V4.9.5 -static const AT_CellularBase::SupportedFeature unsupported_features_ems31[] = { - AT_CellularBase::SUPPORTED_FEATURE_END_MARK -}; - -GEMALTO_CINTERION_Module::Model GEMALTO_CINTERION_Module::_model; - -nsapi_error_t GEMALTO_CINTERION_Module::detect_model(const char *model) -{ - static const AT_CellularBase::SupportedFeature *unsupported_features; - if (memcmp(model, "ELS61", sizeof("ELS61") - 1) == 0) { - _model = ModelELS61; - unsupported_features = unsupported_features_els61; - } else if (memcmp(model, "BGS2", sizeof("BGS2") - 1) == 0) { - _model = ModelBGS2; - unsupported_features = unsupported_features_bgs2; - } else if (memcmp(model, "EMS31", sizeof("EMS31") - 1) == 0) { - _model = ModelEMS31; - unsupported_features = unsupported_features_ems31; - } else { - tr_error("Cinterion model unsupported %s", model); - return NSAPI_ERROR_UNSUPPORTED; - } - tr_info("Cinterion model %s (%d)", model, _model); - AT_CellularBase::set_unsupported_features(unsupported_features); - return NSAPI_ERROR_OK; -} - -GEMALTO_CINTERION_Module::Model GEMALTO_CINTERION_Module::get_model() -{ - return _model; -} diff --git a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_Module.h b/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_Module.h deleted file mode 100644 index 63e6020403..0000000000 --- a/features/cellular/framework/targets/GEMALTO/CINTERION/GEMALTO_CINTERION_Module.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef GEMALTO_CINTERION_MODULE_H_ -#define GEMALTO_CINTERION_MODULE_H_ - -#include "nsapi_types.h" - -namespace mbed { - -class FileHandle; - -class GEMALTO_CINTERION_Module { -public: - /** Actual model of cellular module is needed to make AT command adaptation at runtime - * to support many different models in one cellular driver. - */ - enum Model { - ModelUnknown = 0, - ModelELS61, - ModelBGS2, - ModelEMS31, - }; - static nsapi_error_t detect_model(const char *model); - static Model get_model(); - -private: - static Model _model; -}; - -} // namespace mbed - -#endif // GEMALTO_CINTERION_MODULE_H_ diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.cpp b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.cpp index f6d5e5a6ef..0f87bac48c 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.cpp +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.cpp @@ -28,6 +28,7 @@ QUECTEL_BC95_CellularContext::~QUECTEL_BC95_CellularContext() { } +#if !NSAPI_PPP_AVAILABLE NetworkStack *QUECTEL_BC95_CellularContext::get_stack() { if (!_stack) { @@ -35,6 +36,7 @@ NetworkStack *QUECTEL_BC95_CellularContext::get_stack() } return _stack; } +#endif // #if !NSAPI_PPP_AVAILABLE bool QUECTEL_BC95_CellularContext::stack_type_supported(nsapi_ip_stack_t stack_type) { diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.h b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.h index e241275aeb..d1421c20b5 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.h +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularContext.h @@ -27,7 +27,9 @@ public: virtual ~QUECTEL_BC95_CellularContext(); protected: +#if !NSAPI_PPP_AVAILABLE virtual NetworkStack *get_stack(); +#endif // #if !NSAPI_PPP_AVAILABLE virtual bool stack_type_supported(nsapi_ip_stack_t stack_type); }; diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp index c63feb2888..e07b7001c0 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp @@ -34,6 +34,7 @@ using namespace events; static const AT_CellularBase::SupportedFeature unsupported_features[] = { AT_CellularBase::AT_CGSN_WITH_TYPE, + AT_CellularBase::AT_CGDATA, AT_CellularBase::SUPPORTED_FEATURE_END_MARK }; diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.cpp index 295b0d3af9..73a971df52 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.cpp @@ -36,6 +36,7 @@ bool QUECTEL_BG96_CellularContext::stack_type_supported(nsapi_ip_stack_t stack_t return false; } +#if !NSAPI_PPP_AVAILABLE NetworkStack *QUECTEL_BG96_CellularContext::get_stack() { if (!_stack) { @@ -43,6 +44,7 @@ NetworkStack *QUECTEL_BG96_CellularContext::get_stack() } return _stack; } +#endif // #if !NSAPI_PPP_AVAILABLE nsapi_error_t QUECTEL_BG96_CellularContext::do_user_authentication() { diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.h b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.h index 363aaa095e..89d20fc231 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.h +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularContext.h @@ -28,7 +28,9 @@ public: protected: virtual bool stack_type_supported(nsapi_ip_stack_t stack_type); +#if !NSAPI_PPP_AVAILABLE virtual NetworkStack *get_stack(); +#endif // #if !NSAPI_PPP_AVAILABLE virtual nsapi_error_t do_user_authentication(); }; diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md index 941954e45a..4ab2853ac0 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md @@ -8,6 +8,13 @@ The CC 310 driver consists of three libraries: * A platform-specific TRNG library, containing TRNG-related information, for sampling sufficient entropy on the specific platform(`libcc_trng.a`). * A platform-specific library containing extra information, such as the CC register's base addresses on the specific board. (`libcc_ext.a`) +Library version information: + +* The CC 310 libraries were built from version `arm_sw-cc310-1.1.0.1285` +* The `IAR` libraries were built using `IAR ANSI C/C++ Compiler V7.80.1.11864/W32 for ARM` with `--cpu Cortex-M4f`. +* The `ARM` libraries were built using `ARM Compiler 5.06 update 4 (build 422)` with `--cpu cortex-m4`. +* The `GCC_ARM` libraries were built using `arm-none-eabi-gcc 6.3.1 20170620 (release)` with `-mcpu=cortex-m4`. + To port your CC 310 driver to Mbed OS on your specific target, do the following: 1. In `targets.json` add the following to your target: diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_ext.ar b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_ext.ar index 07f546ccf2..40e27f7e4a 100644 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_ext.ar and b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_ext.ar differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_trng.ar b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_trng.ar index e1e34ce810..17f0057fcd 100644 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_trng.ar and b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_ARM/libcc_310_trng.ar differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_ext.a b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_ext.a index 68b3dce450..64c57cceb7 100644 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_ext.a and b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_ext.a differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_trng.a b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_trng.a index e518506248..df24c2c2c9 100644 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_trng.a and b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_GCC_ARM/libcc_310_trng.a differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/lib_cc310_ext.a b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/lib_cc310_ext.a new file mode 100644 index 0000000000..3b54c60613 Binary files /dev/null and b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/lib_cc310_ext.a differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/lib_cc310_trng.a b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/lib_cc310_trng.a new file mode 100644 index 0000000000..312518e1e6 Binary files /dev/null and b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/lib_cc310_trng.a differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/libnrf_cc310_ext_short_wchar_0.9.9.a b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/libnrf_cc310_ext_short_wchar_0.9.9.a deleted file mode 100644 index 2613095953..0000000000 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/libnrf_cc310_ext_short_wchar_0.9.9.a and /dev/null differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/libnrf_cc310_trng_short_wchar_0.9.9.a b/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/libnrf_cc310_trng_short_wchar_0.9.9.a deleted file mode 100644 index 889c117f19..0000000000 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_MCU_NRF52840/TOOLCHAIN_IAR/libnrf_cc310_trng_short_wchar_0.9.9.a and /dev/null differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_ARM/libcc_310_core.ar b/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_ARM/libcc_310_core.ar index d6db74847a..3121265c28 100644 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_ARM/libcc_310_core.ar and b/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_ARM/libcc_310_core.ar differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_GCC_ARM/libcc_310_core.a b/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_GCC_ARM/libcc_310_core.a index 4d0d895777..bace518f9b 100644 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_GCC_ARM/libcc_310_core.a and b/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_GCC_ARM/libcc_310_core.a differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_IAR/lib_cc310_core.a b/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_IAR/lib_cc310_core.a index b23330ccc4..498bd54c80 100644 Binary files a/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_IAR/lib_cc310_core.a and b/features/cryptocell/FEATURE_CRYPTOCELL310/binaries/TOOLCHAIN_IAR/lib_cc310_core.a differ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/cc_internal.c b/features/cryptocell/FEATURE_CRYPTOCELL310/cc_internal.c index 5415975c0b..d3502e45dc 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/cc_internal.c +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/cc_internal.c @@ -144,6 +144,8 @@ int convert_CrysError_to_mbedtls_err( CRYSError_t Crys_err ) case CRYS_ECPKI_GEN_KEY_INVALID_PRIVATE_KEY_PTR_ERROR: case CRYS_ECPKI_EXPORT_PUBL_KEY_INVALID_PUBL_KEY_DATA_ERROR: case CRYS_ECPKI_BUILD_KEY_INVALID_PRIV_KEY_DATA_ERROR: + case CRYS_ECPKI_BUILD_KEY_INVALID_PRIV_KEY_SIZE_ERROR: + case CRYS_ECPKI_BUILD_KEY_INVALID_PUBL_KEY_SIZE_ERROR: return ( MBEDTLS_ERR_ECP_INVALID_KEY ); default: diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.c b/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.c index c721fb7b9f..f750485413 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.c +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.c @@ -21,11 +21,11 @@ #include "mbedtls/sha1.h" #if defined(MBEDTLS_SHA1_ALT) #include +#include "mbedtls/platform.h" void mbedtls_sha1_init( mbedtls_sha1_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_sha1_context ) ); - } void mbedtls_sha1_free( mbedtls_sha1_context *ctx ) @@ -64,10 +64,10 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] ) { - CRYSError_t CrysErr = CRYS_OK; + CRYSError_t crys_err = CRYS_OK; CRYS_HASH_Result_t crys_result = {0}; - CrysErr = CRYS_HASH_Finish( &ctx->crys_hash_ctx, crys_result ); - if( CrysErr == CRYS_OK ) + crys_err = CRYS_HASH_Finish( &ctx->crys_hash_ctx, crys_result ); + if( crys_err == CRYS_OK ) { memcpy( output, crys_result, 20 ); return ( 0 ); @@ -79,8 +79,6 @@ int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] ) { - if( CRYS_HASH_Update( &ctx->crys_hash_ctx, (uint8_t*)data, 64 ) != CRYS_OK ) - return ( MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED ); - return ( 0 ); + return( MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED ); } #endif //MBEDTLS_SHA1_ALT diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.h b/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.h index d9a74f2410..245910b330 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.h +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/sha1_alt.h @@ -22,10 +22,6 @@ #define __SHA1_ALT__ #if defined(MBEDTLS_SHA1_ALT) #include "crys_hash.h" -#ifdef __cplusplus -extern "C" { -#endif - /** * \brief SHA-1 context structure @@ -35,114 +31,6 @@ typedef struct CRYS_HASHUserContext_t crys_hash_ctx; } mbedtls_sha1_context; -/** - * \brief This function initializes a SHA-1 context. - * - * \param ctx The SHA-1 context to initialize. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -void mbedtls_sha1_init( mbedtls_sha1_context *ctx ); - -/** - * \brief This function clears a SHA-1 context. - * - * \param ctx The SHA-1 context to clear. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -void mbedtls_sha1_free( mbedtls_sha1_context *ctx ); - -/** - * \brief This function clones the state of a SHA-1 context. - * - * \param dst The destination context. - * \param src The context to clone. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -void mbedtls_sha1_clone( mbedtls_sha1_context *dst, - const mbedtls_sha1_context *src ); - -/** - * \brief This function starts a SHA-1 checksum calculation. - * - * \param ctx The context to initialize. - * - * \return \c 0 if successful - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ); - -/** - * \brief This function feeds an input buffer into an ongoing SHA-1 - * checksum calculation. - * - * \param ctx The SHA-1 context. - * \param input The buffer holding the input data. - * \param ilen The length of the input data. - * - * \return \c 0 if successful - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, - const unsigned char *input, - size_t ilen ); - -/** - * \brief This function finishes the SHA-1 operation, and writes - * the result to the output buffer. - * - * \param ctx The SHA-1 context. - * \param output The SHA-1 checksum result. - * - * \return \c 0 if successful - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, - unsigned char output[20] ); - -/** - * \brief SHA-1 process data block (internal use only) - * - * \param ctx SHA-1 context - * \param data The data block being processed. - * - * \return \c 0 if successful - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, - const unsigned char data[64] ); - -#ifdef __cplusplus -} -#endif - #endif //MBEDTLS_SHA1_ALT #endif //__SHA1_ALT__ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.c b/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.c index b2a7942512..71c42013e9 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.c +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.c @@ -21,11 +21,11 @@ #include "mbedtls/sha256.h" #if defined(MBEDTLS_SHA256_ALT) #include +#include "mbedtls/platform.h" void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_sha256_context ) ); - } void mbedtls_sha256_free( mbedtls_sha256_context *ctx ) @@ -54,9 +54,7 @@ int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ) int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] ) { - if( CRYS_HASH_Update( &ctx->crys_hash_ctx, (uint8_t*)data, 64 ) != CRYS_OK ) - return ( MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED ); - return ( 0 ); + return( MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED ); } int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, @@ -71,10 +69,10 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] ) { - CRYSError_t CrysErr = CRYS_OK; + CRYSError_t crys_err = CRYS_OK; CRYS_HASH_Result_t crys_result = {0}; - CrysErr = CRYS_HASH_Finish( &ctx->crys_hash_ctx, crys_result ); - if( CrysErr == CRYS_OK ) + crys_err = CRYS_HASH_Finish( &ctx->crys_hash_ctx, crys_result ); + if( crys_err == CRYS_OK ) { memcpy( output, crys_result, 32 ); return ( 0 ); diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.h b/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.h index bdb7c45e80..6be25f9b40 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.h +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/sha256_alt.h @@ -24,10 +24,6 @@ #if defined(MBEDTLS_SHA256_ALT) #include "crys_hash.h" -#ifdef __cplusplus -extern "C" { -#endif - /** * \brief SHA-256 context structure @@ -37,85 +33,5 @@ typedef struct CRYS_HASHUserContext_t crys_hash_ctx; } mbedtls_sha256_context; - -/** - * \brief This function initializes a SHA-256 context. - * - * \param ctx The SHA-256 context to initialize. - */ -void mbedtls_sha256_init( mbedtls_sha256_context *ctx ); - -/** - * \brief This function clears a SHA-256 context. - * - * \param ctx The SHA-256 context to clear. - */ -void mbedtls_sha256_free( mbedtls_sha256_context *ctx ); - -/** - * \brief This function clones the state of a SHA-256 context. - * - * \param dst The destination context. - * \param src The context to clone. - */ -void mbedtls_sha256_clone( mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src ); - -/** - * \brief This function starts a SHA-224 or SHA-256 checksum - * calculation. - * - * \param ctx The context to initialize. - * \param is224 Determines which function to use. - *
  • 0: Use SHA-256.
    • - *
  • 1: Use SHA-224.
- * - * \return \c 0 on success. - */ -int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ); - -/** - * \brief This function feeds an input buffer into an ongoing - * SHA-256 checksum calculation. - * - * \param ctx SHA-256 context - * \param input buffer holding the data - * \param ilen length of the input data - * - * \return \c 0 on success. - */ -int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, - const unsigned char *input, - size_t ilen ); - -/** - * \brief This function finishes the SHA-256 operation, and writes - * the result to the output buffer. - * - * \param ctx The SHA-256 context. - * \param output The SHA-224 or SHA-256 checksum result. - * - * \return \c 0 on success. - */ -int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, - unsigned char output[32] ); - -/** - * \brief This function processes a single data block within - * the ongoing SHA-256 computation. This function is for - * internal use only. - * - * \param ctx The SHA-256 context. - * \param data The buffer holding one block of data. - * - * \return \c 0 on success. - */ -int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, - const unsigned char data[64] ); - -#ifdef __cplusplus -} -#endif - #endif // MBEDTLS_SHA256_ALT__ #endif //__SHA256_ALT__ diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/trng.c b/features/cryptocell/FEATURE_CRYPTOCELL310/trng.c index 5c3431d2e3..4f1c3991ee 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/trng.c +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/trng.c @@ -18,7 +18,7 @@ * */ -#if defined(DEVICE_TRNG) +#if DEVICE_TRNG #include #include "trng_api.h" diff --git a/features/device_key/TESTS/device_key/functionality/main.cpp b/features/device_key/TESTS/device_key/functionality/main.cpp index a88145d032..7be7afabf8 100644 --- a/features/device_key/TESTS/device_key/functionality/main.cpp +++ b/features/device_key/TESTS/device_key/functionality/main.cpp @@ -51,7 +51,7 @@ void generate_derived_key_consistency_32_byte_key_long_consistency_test(char *ke */ int inject_dummy_rot_key() { -#if !defined(DEVICE_TRNG) +#if !DEVICE_TRNG uint32_t key[DEVICE_KEY_16BYTE / sizeof(uint32_t)]; memcpy(key, "1234567812345678", DEVICE_KEY_16BYTE); diff --git a/features/device_key/source/DeviceKey.cpp b/features/device_key/source/DeviceKey.cpp index a76db59afb..d2125c6805 100644 --- a/features/device_key/source/DeviceKey.cpp +++ b/features/device_key/source/DeviceKey.cpp @@ -259,7 +259,7 @@ int DeviceKey::generate_key_by_random(uint32_t *output, size_t size) return DEVICEKEY_INVALID_PARAM; } -#if defined(DEVICE_TRNG) +#if DEVICE_TRNG mbedtls_entropy_context *entropy = new mbedtls_entropy_context; mbedtls_entropy_init(entropy); memset(output, 0, size); diff --git a/features/device_key/source/DeviceKey.h b/features/device_key/source/DeviceKey.h index 6dd83ecc67..6ca024127e 100644 --- a/features/device_key/source/DeviceKey.h +++ b/features/device_key/source/DeviceKey.h @@ -24,7 +24,7 @@ // Whole class is not supported if entropy is not enabled // Flash device is required as Device Key is currently depending on it -#if !defined(DEVICE_FLASH) || !defined(COMPONENT_FLASHIAP) +#if !DEVICE_FLASH || !defined(COMPONENT_FLASHIAP) #undef DEVICEKEY_ENABLED #define DEVICEKEY_ENABLED 0 #endif @@ -91,7 +91,7 @@ public: */ int generate_derived_key(const unsigned char *isalt, size_t isalt_size, unsigned char *output, uint16_t ikey_type); - /** Set a device key into the KVStore. If TRNG support is missing, call this method + /** Set a device key into the KVStore. If entropy support is missing, call this method * before calling device_key_derived_key. This method should be called only once! * @param value Input buffer contain the key. * @param isize Size of the supplied key. Must be 16 bytes or 32 bytes. @@ -131,7 +131,7 @@ private: int get_derived_key(uint32_t *ikey_buff, size_t ikey_size, const unsigned char *isalt, size_t isalt_size, unsigned char *output, uint32_t ikey_type); - /** Generate a random ROT key by using TRNG + /** Generate a random ROT key by using entropy * @param output Output buffer for the generated key. * @param size Input: The size of the buffer. If size is less * than 16 bytes, the method generates an diff --git a/features/frameworks/mbed-coap/CHANGELOG.md b/features/frameworks/mbed-coap/CHANGELOG.md index 230a23d44b..7da355071f 100644 --- a/features/frameworks/mbed-coap/CHANGELOG.md +++ b/features/frameworks/mbed-coap/CHANGELOG.md @@ -1,5 +1,14 @@ # Change Log +## [v4.7.3](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.7.3) + +- Do not store EMPTY response to blockwise list + An Empty message only contains the 4-byte header so it does not require any blockwise operations. + This will fix unneseccary message sending timeouts which leads mbed cloud client to do unnecessary + reconnections which increases the network traffic. + +-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.7.2...v4.7.3) + ## [v4.7.2](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.7.2) - Fix handling of duplicate blockwise ACK's diff --git a/features/frameworks/mbed-coap/module.json b/features/frameworks/mbed-coap/module.json index c170db093c..980b25d078 100644 --- a/features/frameworks/mbed-coap/module.json +++ b/features/frameworks/mbed-coap/module.json @@ -1,6 +1,6 @@ { "name": "mbed-coap", - "version": "4.7.2", + "version": "4.7.3", "description": "COAP library", "keywords": [ "coap", diff --git a/features/frameworks/mbed-coap/source/sn_coap_protocol.c b/features/frameworks/mbed-coap/source/sn_coap_protocol.c index caca1f1e90..0a87eb3f1a 100644 --- a/features/frameworks/mbed-coap/source/sn_coap_protocol.c +++ b/features/frameworks/mbed-coap/source/sn_coap_protocol.c @@ -564,7 +564,8 @@ int16_t sn_coap_protocol_build(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_p stored_blockwise_msg_ptr->param = param; stored_blockwise_msg_ptr->msg_id = stored_blockwise_msg_ptr->coap_msg_ptr->msg_id; ns_list_add_to_end(&handle->linked_list_blockwise_sent_msgs, stored_blockwise_msg_ptr); - } else if (src_coap_msg_ptr->msg_code <= COAP_MSG_CODE_REQUEST_DELETE) { + } else if (src_coap_msg_ptr->msg_code <= COAP_MSG_CODE_REQUEST_DELETE && + src_coap_msg_ptr->msg_code != COAP_MSG_CODE_EMPTY) { /* Add message to linked list - response can be in blocks and we need header to build response.. */ coap_blockwise_msg_s *stored_blockwise_msg_ptr; diff --git a/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_types.h b/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_types.h index f9b7815b26..f19382a67e 100644 --- a/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_types.h +++ b/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_types.h @@ -121,7 +121,15 @@ typedef int_fast32_t int_fast24_t; #define alignas(n) __align(n) #define __alignas_is_defined 1 #elif (defined __STDC_VERSION__ && __STDC_VERSION__ >= 201112L) || (defined __cplusplus && __cplusplus >= 201103L) -#include +# if defined __ARMCC_VERSION && __ARMCC_VERSION < 6120000 + /* Workaround for Arm Compiler versions prior to 6.12 */ +# if !defined __cplusplus +# define alignas _Alignas +# endif +# define __alignas_is_defined 1 +# else +# include +# endif #elif defined __GNUC__ #define alignas(n) __attribute__((__aligned__(n))) #define __alignas_is_defined 1 diff --git a/features/lorawan/LoRaWANStack.cpp b/features/lorawan/LoRaWANStack.cpp index 0f125c5448..79f899ef2a 100644 --- a/features/lorawan/LoRaWANStack.cpp +++ b/features/lorawan/LoRaWANStack.cpp @@ -614,6 +614,8 @@ void LoRaWANStack::post_process_tx_with_reception() _loramac.get_device_class() == CLASS_A ? "A" : "C"); _ctrl_flags &= ~TX_DONE_FLAG; _ctrl_flags |= RETRY_EXHAUSTED_FLAG; + _loramac.post_process_mcps_req(); + make_tx_metadata_available(); state_controller(DEVICE_STATE_STATUS_CHECK); } } diff --git a/features/lorawan/lorastack/mac/LoRaMac.cpp b/features/lorawan/lorastack/mac/LoRaMac.cpp index 05c58a97cf..a971fb9cd4 100644 --- a/features/lorawan/lorastack/mac/LoRaMac.cpp +++ b/features/lorawan/lorastack/mac/LoRaMac.cpp @@ -166,11 +166,12 @@ void LoRaMac::post_process_mcps_req() _params.is_node_ack_requested = false; _mcps_confirmation.ack_received = false; _mcps_indication.is_ack_recvd = false; - _params.ul_frame_counter++; - _params.adr_ack_counter++; } else { _mcps_confirmation.status = LORAMAC_EVENT_INFO_STATUS_ERROR; } + + _params.ul_frame_counter++; + _params.adr_ack_counter++; } else { //UNCONFIRMED or PROPRIETARY _params.ul_frame_counter++; diff --git a/features/lorawan/lorastack/phy/LoRaPHY.cpp b/features/lorawan/lorastack/phy/LoRaPHY.cpp index c995cd211b..29414ee7aa 100644 --- a/features/lorawan/lorastack/phy/LoRaPHY.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHY.cpp @@ -32,8 +32,9 @@ SPDX-License-Identifier: BSD-3-Clause #define BACKOFF_DC_1_HOUR 100 #define BACKOFF_DC_10_HOURS 1000 #define BACKOFF_DC_24_HOURS 10000 - -#define CHANNELS_IN_MASK 16 +#define MAX_PREAMBLE_LENGTH 8.0f +#define TICK_GRANULARITY_JITTER 1.0f +#define CHANNELS_IN_MASK 16 LoRaPHY::LoRaPHY() : _radio(NULL), @@ -388,23 +389,56 @@ uint8_t LoRaPHY::verify_link_ADR_req(verify_adr_params_t *verify_params, return status; } -double LoRaPHY::compute_symb_timeout_lora(uint8_t phy_dr, uint32_t bandwidth) +float LoRaPHY::compute_symb_timeout_lora(uint8_t phy_dr, uint32_t bandwidth) { - return ((double)(1 << phy_dr) / (double) bandwidth) * 1000; + // in milliseconds + return ((float)(1 << phy_dr) / (float) bandwidth * 1000); } -double LoRaPHY::compute_symb_timeout_fsk(uint8_t phy_dr) +float LoRaPHY::compute_symb_timeout_fsk(uint8_t phy_dr) { - return (8.0 / (double) phy_dr); // 1 symbol equals 1 byte + return (8.0f / (float) phy_dr); // 1 symbol equals 1 byte } -void LoRaPHY::get_rx_window_params(double t_symb, uint8_t min_rx_symb, - uint32_t rx_error, uint32_t wakeup_time, - uint32_t *window_timeout, int32_t *window_offset) + +void LoRaPHY::get_rx_window_params(float t_symb, uint8_t min_rx_symb, + float error_fudge, float wakeup_time, + uint32_t *window_length, int32_t *window_offset, + uint8_t phy_dr) { - // Computed number of symbols - *window_timeout = MAX((uint32_t) ceil(((2 * min_rx_symb - 8) * t_symb + 2 * rx_error) / t_symb), min_rx_symb); - *window_offset = (int32_t) ceil((4.0 * t_symb) - ((*window_timeout * t_symb) / 2.0) - wakeup_time); + float target_rx_window_offset; + float window_len_in_ms; + + if (phy_params.fsk_supported && phy_dr == phy_params.max_rx_datarate) { + min_rx_symb = MAX_PREAMBLE_LENGTH; + } + + // We wish to be as close as possible to the actual start of data, i.e., + // we are interested in the preamble symbols which are at the tail of the + // preamble sequence. + target_rx_window_offset = (MAX_PREAMBLE_LENGTH - min_rx_symb) * t_symb; //in ms + + // Actual window offset in ms in response to timing error fudge factor and + // radio wakeup/turned around time. + *window_offset = floor(target_rx_window_offset - error_fudge - wakeup_time); + + // possible wait for next symbol start if we start inside the preamble + float possible_wait_for_symb_start = MIN(t_symb, + ((2 * error_fudge) + wakeup_time + TICK_GRANULARITY_JITTER)); + + // how early we might start reception relative to transmit start (so negative if before transmit starts) + float earliest_possible_start_time = *window_offset - error_fudge - TICK_GRANULARITY_JITTER; + + // time in (ms) we may have to wait for the other side to start transmission + float possible_wait_for_transmit = -earliest_possible_start_time; + + // Minimum reception time plus extra time (in ms) we may have turned on before the + // other side started transmission + window_len_in_ms = (min_rx_symb * t_symb) + MAX(possible_wait_for_transmit, possible_wait_for_symb_start); + + // Setting the window_length in terms of 'symbols' for LoRa modulation or + // in terms of 'bytes' for FSK + *window_length = (uint32_t) ceil(window_len_in_ms / t_symb); } int8_t LoRaPHY::compute_tx_power(int8_t tx_power_idx, float max_eirp, @@ -791,7 +825,7 @@ void LoRaPHY::compute_rx_win_params(int8_t datarate, uint8_t min_rx_symbols, uint32_t rx_error, rx_config_params_t *rx_conf_params) { - double t_symbol = 0.0; + float t_symbol = 0.0; // Get the datarate, perform a boundary check rx_conf_params->datarate = MIN(datarate, phy_params.max_rx_datarate); @@ -811,9 +845,9 @@ void LoRaPHY::compute_rx_win_params(int8_t datarate, uint8_t min_rx_symbols, rx_conf_params->frequency = phy_params.channels.channel_list[rx_conf_params->channel].frequency; } - - get_rx_window_params(t_symbol, min_rx_symbols, rx_error, RADIO_WAKEUP_TIME, - &rx_conf_params->window_timeout, &rx_conf_params->window_offset); + get_rx_window_params(t_symbol, min_rx_symbols, (float) rx_error, MBED_CONF_LORA_WAKEUP_TIME, + &rx_conf_params->window_timeout, &rx_conf_params->window_offset, + rx_conf_params->datarate); } bool LoRaPHY::rx_config(rx_config_params_t *rx_conf) @@ -847,13 +881,13 @@ bool LoRaPHY::rx_config(rx_config_params_t *rx_conf) // Radio configuration if (dr == DR_7 && phy_params.fsk_supported) { modem = MODEM_FSK; - _radio->set_rx_config(modem, 50000, phy_dr * 1000, 0, 83333, 5, + _radio->set_rx_config(modem, 50000, phy_dr * 1000, 0, 83333, MAX_PREAMBLE_LENGTH, rx_conf->window_timeout, false, 0, true, 0, 0, false, rx_conf->is_rx_continuous); } else { modem = MODEM_LORA; _radio->set_rx_config(modem, rx_conf->bandwidth, phy_dr, 1, 0, - MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH, + MAX_PREAMBLE_LENGTH, rx_conf->window_timeout, false, 0, false, 0, 0, true, rx_conf->is_rx_continuous); } @@ -899,8 +933,8 @@ bool LoRaPHY::tx_config(tx_config_params_t *tx_conf, int8_t *tx_power, // High Speed FSK channel modem = MODEM_FSK; _radio->set_tx_config(modem, phy_tx_power, 25000, bandwidth, - phy_dr * 1000, 0, 5, false, true, 0, 0, false, - 3000); + phy_dr * 1000, 0, MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH, + false, true, 0, 0, false, 3000); } else { modem = MODEM_LORA; _radio->set_tx_config(modem, phy_tx_power, 0, bandwidth, phy_dr, 1, diff --git a/features/lorawan/lorastack/phy/LoRaPHY.h b/features/lorawan/lorastack/phy/LoRaPHY.h index 76bad8993c..d6be36b1dc 100644 --- a/features/lorawan/lorastack/phy/LoRaPHY.h +++ b/features/lorawan/lorastack/phy/LoRaPHY.h @@ -202,40 +202,63 @@ public: /** Computing Receive Windows * - * For more details please consult the following document, chapter 3.1.2. - * http://www.semtech.com/images/datasheet/SX1272_settings_for_LoRaWAN_v2.0.pdf - * or - * http://www.semtech.com/images/datasheet/SX1276_settings_for_LoRaWAN_v2.0.pdf + * The algorithm tries to calculate the length of receive windows (i.e., + * the minimum time it should remain to acquire a lock on the Preamble + * for synchronization) and the error offset which compensates for the system + * timing errors. Basic idea behind the algorithm is to optimize for the + * reception of last 'min_rx_symbols' symbols out of transmitted Premable + * symbols. The algorithm compensates for the clock drifts, tick granularity + * and system wake up time (from sleep state) by opening the window early for + * the lower SFs. For higher SFs, the symbol time is large enough that we can + * afford to open late (hence the positive offset). + * The table below shows the calculated values for SF7 to SF12 with 125 kHz + * bandwidth. * - * Downlink start: T = Tx + 1s (+/- 20 us) - * | - * TRxEarly | TRxLate - * | | | - * | | +---+---+---+---+---+---+---+---+ - * | | | Latest Rx window | - * | | +---+---+---+---+---+---+---+---+ - * | | | + * +----+-----+----------+---------+-------------------------+----------------------+-------------------------+ + * | SF | BW (kHz) | rx_error (ms) | wake_up (ms) | min_rx_symbols | window_timeout(symb) | window_offset(ms) | + * +----+-----+----------+---------+-------------------------+----------------------+-------------------------+ + * | 7 | 125 | 5 | 5 | 5 | 18 | -7 | + * | 8 | 125 | 5 | 5 | 5 | 10 | -4 | + * | 9 | 125 | 5 | 5 | 5 | 6 | 2 | + * | 10 | 125 | 5 | 5 | 5 | 6 | 14 | + * | 11 | 125 | 5 | 5 | 5 | 6 | 39 | + * | 12 | 125 | 5 | 5 | 5 | 6 | 88 | + * +----+-----+----------+---------+-------------------------+----------------------+-------------------------+ + * + * For example for SF7, the receive window will open at downlink start time + * plus the offset calculated and will remain open for the length window_timeout. + * + * Symbol time = 1.024 ms + * Downlink start: T = Tx + 1s (+/- 20 us) + * | + * | + * | + * | + * | + * +---+---+---+---+---+---+---+---+ + * | 8 Preamble Symbols | + * +---+---+---+---+---+---+---+---+ + * | RX Window start time = T +/- Offset + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * | | | | | | | | | | | | | | | | | | | + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * + * Similarly for SF12: + * + * Symbol time = 32.768 ms + * Downlink start: T = Tx + 1s (+/- 20 us) + * | + * | + * | + * | + * | * +---+---+---+---+---+---+---+---+ - * | Earliest Rx window | + * | 8 Preamble Symbols | * +---+---+---+---+---+---+---+---+ - * | - * +---+---+---+---+---+---+---+---+ - *Downlink preamble 8 symbols | | | | | | | | | - * +---+---+---+---+---+---+---+---+ - * - * Worst case Rx window timings - * - * TRxLate = DEFAULT_MIN_RX_SYMBOLS * tSymbol - RADIO_WAKEUP_TIME - * TRxEarly = 8 - DEFAULT_MIN_RX_SYMBOLS * tSymbol - RxWindowTimeout - RADIO_WAKEUP_TIME - * - * TRxLate - TRxEarly = 2 * DEFAULT_SYSTEM_MAX_RX_ERROR - * - * RxOffset = ( TRxLate + TRxEarly ) / 2 - * - * RxWindowTimeout = ( 2 * DEFAULT_MIN_RX_SYMBOLS - 8 ) * tSymbol + 2 * DEFAULT_SYSTEM_MAX_RX_ERROR - * RxOffset = 4 * tSymbol - RxWindowTimeout / 2 - RADIO_WAKE_UP_TIME - * - * The minimum value of RxWindowTimeout must be 5 symbols which implies that the system always tolerates at least an error of 1.5 * tSymbol. + * | RX Window start time = T +/- Offset + * +---+---+---+---+---+---+ + * | | | | | | | + * +---+---+---+---+---+---+ */ /*! * Computes the RX window timeout and offset. @@ -597,9 +620,10 @@ protected: /** * Computes the RX window timeout and the RX window offset. */ - void get_rx_window_params(double t_symbol, uint8_t min_rx_symbols, - uint32_t rx_error, uint32_t wakeup_time, - uint32_t *window_timeout, int32_t *window_offset); + void get_rx_window_params(float t_symbol, uint8_t min_rx_symbols, + float rx_error, float wakeup_time, + uint32_t *window_length, int32_t *window_offset, + uint8_t phy_dr); /** * Computes the txPower, based on the max EIRP and the antenna gain. @@ -632,12 +656,12 @@ private: /** * Computes the symbol time for LoRa modulation. */ - double compute_symb_timeout_lora(uint8_t phy_dr, uint32_t bandwidth); + float compute_symb_timeout_lora(uint8_t phy_dr, uint32_t bandwidth); /** * Computes the symbol time for FSK modulation. */ - double compute_symb_timeout_fsk(uint8_t phy_dr); + float compute_symb_timeout_fsk(uint8_t phy_dr); protected: LoRaRadio *_radio; diff --git a/features/lorawan/mbed_lib.json b/features/lorawan/mbed_lib.json index e4eefd00e5..30e130b364 100644 --- a/features/lorawan/mbed_lib.json +++ b/features/lorawan/mbed_lib.json @@ -70,24 +70,28 @@ "value": true }, "max-sys-rx-error": { - "help": "Maximum timing error of the receiver in ms. The receiver will turn on in [-RxError : + RxError]", - "value": 10 + "help": "Max. timing error fudge. The receiver will turn on in [-RxError : + RxError]", + "value": 5 + }, + "wakeup-time": { + "help": "Time in (ms) the platform takes to wakeup from sleep/deep sleep state. This number is platform dependent", + "value": 5 }, "downlink-preamble-length": { - "help": "Number of preamble symbols need to be captured (out of 8) for successful demodulation", - "value": 5 + "help": "Number of whole preamble symbols needed to have a firm lock on the signal.", + "value": 5 }, "uplink-preamble-length": { - "help": "Number of preamble symbols to transmit. Must be <= 8", - "value": 8 + "help": "Number of preamble symbols to transmit. Default: 8", + "value": 8 }, "fsb-mask": { - "help": "FSB mask for upstream [Only for US915 & AU915] Check lorawan/FSB_Usage.txt for more details", - "value": "{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" + "help": "FSB mask for upstream [Only for US915 & AU915] Check lorawan/FSB_Usage.txt for more details", + "value": "{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" }, "fsb-mask-china": { - "help": "FSB mask for upstream [CN470 PHY] Check lorawan/FSB_Usage.txt for more details", - "value": "{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}" + "help": "FSB mask for upstream [CN470 PHY] Check lorawan/FSB_Usage.txt for more details", + "value": "{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}" } } } diff --git a/features/lorawan/system/lorawan_data_structures.h b/features/lorawan/system/lorawan_data_structures.h index e35d542761..dafcb29ff1 100644 --- a/features/lorawan/system/lorawan_data_structures.h +++ b/features/lorawan/system/lorawan_data_structures.h @@ -44,9 +44,6 @@ typedef uint32_t lorawan_time_t; #endif -// Radio wake-up time from sleep - unit ms. -#define RADIO_WAKEUP_TIME 1 - /*! * Sets the length of the LoRaMAC footer field. * Mainly indicates the MIC field length. @@ -1259,8 +1256,8 @@ typedef struct { /*! * LoRaMac reception windows delay - * \remark normal frame: RxWindowXDelay = ReceiveDelayX - RADIO_WAKEUP_TIME - * join frame : RxWindowXDelay = JoinAcceptDelayX - RADIO_WAKEUP_TIME + * \remark normal frame: RxWindowXDelay = ReceiveDelayX - Offset + * join frame : RxWindowXDelay = JoinAcceptDelayX - Offset */ uint32_t rx_window1_delay; uint32_t rx_window2_delay; diff --git a/features/lwipstack/mbed_lib.json b/features/lwipstack/mbed_lib.json index d04cdef3b8..f9edca1620 100644 --- a/features/lwipstack/mbed_lib.json +++ b/features/lwipstack/mbed_lib.json @@ -115,7 +115,8 @@ }, "target_overrides": { "REALTEK_RTL8195AM": { - "tcpip-thread-stacksize": 1600 + "tcpip-thread-stacksize": 1600, + "mem-size": 12800 }, "UBLOX_EVK_ODIN_W2": { "pbuf-pool-size" : 10 diff --git a/features/mbedtls/importer/adjust-config.sh b/features/mbedtls/importer/adjust-config.sh index d6cc758a73..347ca5c155 100755 --- a/features/mbedtls/importer/adjust-config.sh +++ b/features/mbedtls/importer/adjust-config.sh @@ -140,6 +140,12 @@ conf unset MBEDTLS_SSL_TRUNCATED_HMAC conf unset MBEDTLS_PLATFORM_TIME_TYPE_MACRO +# The default size of MBEDTLS_MPI_MAX_SIZE is 1024 bytes. +# In some cases, this value is set to stack buffers. +# Reduce the maximal MBEDTLS_MPI_MAX_SIZE to 512 bytes, +# which should fit RSA 4096 bit keys. +conf set MBEDTLS_MPI_MAX_SIZE 512 + # The following configurations are a needed for Mbed Crypto submodule. # They are related to the persistent key storage feature. conf set MBEDTLS_PSA_CRYPTO_STORAGE_C diff --git a/features/mbedtls/platform/inc/platform_mbed.h b/features/mbedtls/platform/inc/platform_mbed.h index 0da5014e97..9ccaf08ab0 100644 --- a/features/mbedtls/platform/inc/platform_mbed.h +++ b/features/mbedtls/platform/inc/platform_mbed.h @@ -17,7 +17,7 @@ * This file is part of mbed TLS (https://tls.mbed.org) */ -#if defined(DEVICE_TRNG) +#if DEVICE_TRNG #define MBEDTLS_ENTROPY_HARDWARE_ALT #endif diff --git a/features/mbedtls/platform/src/mbed_trng.c b/features/mbedtls/platform/src/mbed_trng.c index e5a1cbbe1f..d4dd771c01 100644 --- a/features/mbedtls/platform/src/mbed_trng.c +++ b/features/mbedtls/platform/src/mbed_trng.c @@ -14,7 +14,7 @@ * limitations under the License. */ -#if defined(DEVICE_TRNG) +#if DEVICE_TRNG #include "hal/trng_api.h" diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c index 69a6f790af..a70ca65812 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/aes/aes_alt.c @@ -144,10 +144,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - /* TODO: Change busy-wait to other means to release CPU */ /* Acquire ownership of AES H/W */ - while (! crypto_aes_acquire()); - + crypto_aes_acquire(); + /* Init crypto module */ crypto_init(); /* Enable AES interrupt */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c index 2ef63f4b3c..834592a51a 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/des/des_alt.c @@ -349,10 +349,9 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - /* TODO: Change busy-wait to other means to release CPU */ /* Acquire ownership of DES H/W */ - while (! crypto_des_acquire()); - + crypto_des_acquire(); + /* Init crypto module */ crypto_init(); /* Enable DES interrupt */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/ecp/ecp_internal_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/ecp/ecp_internal_alt.c index be73b1f1d8..9d5bd95bed 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/ecp/ecp_internal_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/ecp/ecp_internal_alt.c @@ -53,6 +53,7 @@ * would be defined in mbedtls/ecp.h from ecp.c for our inclusion */ #define ECP_SHORTWEIERSTRASS +#include "mbedtls/platform.h" #include "mbedtls/ecp_internal.h" #include "mbed_toolchain.h" #include "mbed_assert.h" @@ -222,12 +223,23 @@ unsigned char mbedtls_internal_ecp_grp_capable( const mbedtls_ecp_group *grp ) int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) { - /* TODO: Change busy-wait with other means to release CPU */ - /* Acquire ownership of ECC accelerator */ - while (! crypto_ecc_acquire()); + /* Behavior of mbedtls_internal_ecp_init()/mbedtls_internal_ecp_free() + * + * mbedtls_internal_ecp_init()/mbedtls_internal_ecp_free() are like pre-op/post-op calls + * and they guarantee: + * + * 1. Paired + * 2. No overlapping + * 3. Upper public function cannot return when ECP alter. is still activated. + */ - /* Init crypto module */ + /* Acquire ownership of ECC accelerator */ + crypto_ecc_acquire(); + + /* Initialize crypto module */ crypto_init(); + + /* Enable ECC interrupt */ ECC_ENABLE_INT(); return 0; @@ -237,9 +249,10 @@ void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) { /* Disable ECC interrupt */ ECC_DISABLE_INT(); + /* Uninit crypto module */ crypto_uninit(); - + /* Release ownership of ECC accelerator */ crypto_ecc_release(); } @@ -589,7 +602,7 @@ NU_STATIC int internal_run_eccop(const mbedtls_ecp_group *grp, ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; goto cleanup; } - + /* Configure ECC curve coefficients A/B */ /* Special case for A = -3 */ if (grp->A.p == NULL) { @@ -632,10 +645,9 @@ NU_STATIC int internal_run_eccop(const mbedtls_ecp_group *grp, crypto_ecc_prestart(); CRPT->ECC_CTL = (grp->pbits << CRPT_ECC_CTL_CURVEM_Pos) | eccop | CRPT_ECC_CTL_FSEL_Msk | CRPT_ECC_CTL_START_Msk; ecc_done = crypto_ecc_wait(); - - /* FIXME: Better error code for ECC accelerator error */ - MBEDTLS_MPI_CHK(ecc_done ? 0 : -1); - + + MBEDTLS_MPI_CHK(ecc_done ? 0 : MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + /* (X1, Y1) hold the normalized result. */ MBEDTLS_MPI_CHK(internal_mpi_read_eccreg(&R->X, (uint32_t *) CRPT->ECC_X1, NU_ECC_BIGNUM_MAXWORD)); MBEDTLS_MPI_CHK(internal_mpi_read_eccreg(&R->Y, (uint32_t *) CRPT->ECC_Y1, NU_ECC_BIGNUM_MAXWORD)); @@ -644,7 +656,7 @@ NU_STATIC int internal_run_eccop(const mbedtls_ecp_group *grp, cleanup: mbedtls_mpi_free(&N_); - + return ret; } @@ -698,7 +710,7 @@ NU_STATIC int internal_run_modop(mbedtls_mpi *r, const mbedtls_mpi *Np; mbedtls_mpi_init(&N_); - + /* Use INTERNAL_MPI_NORM(Np, N1, N_, P) to get normalized MPI * * N_: Holds normalized MPI if the passed-in MPI N1 is not @@ -726,10 +738,9 @@ NU_STATIC int internal_run_modop(mbedtls_mpi *r, crypto_ecc_prestart(); CRPT->ECC_CTL = (pbits << CRPT_ECC_CTL_CURVEM_Pos) | (ECCOP_MODULE | modop) | CRPT_ECC_CTL_FSEL_Msk | CRPT_ECC_CTL_START_Msk; ecc_done = crypto_ecc_wait(); - - /* FIXME: Better error code for ECC accelerator error */ - MBEDTLS_MPI_CHK(ecc_done ? 0 : -1); - + + MBEDTLS_MPI_CHK(ecc_done ? 0 : MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + /* X1 holds the result. */ MBEDTLS_MPI_CHK(internal_mpi_read_eccreg(r, (uint32_t *) CRPT->ECC_X1, NU_ECC_BIGNUM_MAXWORD)); diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c index 75c2c983e4..38981bc1ed 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha1_alt.c @@ -31,7 +31,7 @@ */ static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { - if (try_hw && crypto_sha_acquire()) { + if (try_hw && crypto_sha_try_acquire()) { ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha1_hw_init(&ctx->hw_ctx); } else { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c index 3b392534ce..b0948e1c63 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha256_alt.c @@ -31,7 +31,7 @@ */ static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { - if (try_hw && crypto_sha_acquire()) { + if (try_hw && crypto_sha_try_acquire()) { ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha256_hw_init(&ctx->hw_ctx); } else { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c index c80085d91e..4b4a540551 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha512_alt.c @@ -31,7 +31,7 @@ */ static void mbedtls_sha512_init_internal(mbedtls_sha512_context *ctx, int try_hw) { - if (try_hw && crypto_sha_acquire()) { + if (try_hw && crypto_sha_try_acquire()) { ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha512_hw_init(&ctx->hw_ctx); } else { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c index af52848035..162e4016d0 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/aes/aes_alt.c @@ -144,10 +144,9 @@ static void __nvt_aes_crypt( mbedtls_aes_context *ctx, error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - /* TODO: Change busy-wait to other means to release CPU */ /* Acquire ownership of AES H/W */ - while (! crypto_aes_acquire()); - + crypto_aes_acquire(); + /* Init crypto module */ crypto_init(); /* Enable AES interrupt */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c index 2ef63f4b3c..78db79e731 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/des/des_alt.c @@ -348,11 +348,10 @@ static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_S (! crypto_dma_buff_compat(dmabuf_out, MAXSIZE_DMABUF, 8))) { error("Buffer for DES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); } - - /* TODO: Change busy-wait to other means to release CPU */ + /* Acquire ownership of DES H/W */ - while (! crypto_des_acquire()); - + crypto_des_acquire(); + /* Init crypto module */ crypto_init(); /* Enable DES interrupt */ diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c index 75c2c983e4..38981bc1ed 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha1_alt.c @@ -31,7 +31,7 @@ */ static void mbedtls_sha1_init_internal(mbedtls_sha1_context *ctx, int try_hw) { - if (try_hw && crypto_sha_acquire()) { + if (try_hw && crypto_sha_try_acquire()) { ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha1_hw_init(&ctx->hw_ctx); } else { diff --git a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c index 0307929ebf..7bc12497e7 100644 --- a/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_NUVOTON/TARGET_NUC472/sha/sha256_alt.c @@ -31,7 +31,7 @@ */ static void mbedtls_sha256_init_internal(mbedtls_sha256_context *ctx, int try_hw) { - if (try_hw && crypto_sha_acquire()) { + if (try_hw && crypto_sha_try_acquire()) { ctx->active_ctx = &ctx->hw_ctx; mbedtls_sha256_hw_init(&ctx->hw_ctx); } else { diff --git a/features/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp b/features/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp index 7b911865b7..d660b0968d 100644 --- a/features/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp +++ b/features/nanostack/mbed-mesh-api/source/LoWPANNDInterface.cpp @@ -178,8 +178,19 @@ bool LoWPANNDInterface::getRouterIpAddress(char *address, int8_t len) #if MBED_CONF_NSAPI_DEFAULT_MESH_TYPE == LOWPAN && DEVICE_802_15_4_PHY MBED_WEAK MeshInterface *MeshInterface::get_target_default_instance() { - static LoWPANNDInterface lowpan(&NanostackRfPhy::get_default_instance()); - - return &lowpan; + static bool inited; + static LoWPANNDInterface interface; + singleton_lock(); + if (!inited) { + nsapi_error_t result = interface.initialize(&NanostackRfPhy::get_default_instance()); + if (result != 0) { + tr_error("LoWPANND initialize failed: %d", error); + singleton_unlock(); + return NULL; + } + inited = true; + } + singleton_unlock(); + return &interface; } #endif diff --git a/features/nanostack/mbed-mesh-api/source/NanostackEMACInterface.cpp b/features/nanostack/mbed-mesh-api/source/NanostackEMACInterface.cpp index 989b6f8c88..a62acd69ff 100644 --- a/features/nanostack/mbed-mesh-api/source/NanostackEMACInterface.cpp +++ b/features/nanostack/mbed-mesh-api/source/NanostackEMACInterface.cpp @@ -7,6 +7,7 @@ #include "nsdynmemLIB.h" #include "arm_hal_phy.h" #include "EMAC.h" +#include "enet_tasklet.h" class EMACPhy : public NanostackEthernetPhy { public: @@ -137,6 +138,7 @@ int8_t EMACPhy::phy_register() emac.set_memory_manager(memory_manager); emac.set_link_input_cb(mbed::callback(this, &EMACPhy::emac_phy_rx)); + emac.set_link_state_cb(enet_tasklet_link_state_changed); if (!emac.power_up()) { return -1; diff --git a/features/nanostack/mbed-mesh-api/source/NanostackEthernetInterface.cpp b/features/nanostack/mbed-mesh-api/source/NanostackEthernetInterface.cpp index a502b86886..04bca1b9a6 100644 --- a/features/nanostack/mbed-mesh-api/source/NanostackEthernetInterface.cpp +++ b/features/nanostack/mbed-mesh-api/source/NanostackEthernetInterface.cpp @@ -97,6 +97,8 @@ nsapi_error_t NanostackEthernetInterface::do_initialize() nsapi_error_t Nanostack::EthernetInterface::bringdown() { - enet_tasklet_disconnect(); - return 0; + if (enet_tasklet_disconnect(true)) { + return NSAPI_ERROR_DEVICE_ERROR; + } + return NSAPI_ERROR_OK; } diff --git a/features/nanostack/mbed-mesh-api/source/ThreadInterface.cpp b/features/nanostack/mbed-mesh-api/source/ThreadInterface.cpp index 60e16f3fb9..608af2462a 100644 --- a/features/nanostack/mbed-mesh-api/source/ThreadInterface.cpp +++ b/features/nanostack/mbed-mesh-api/source/ThreadInterface.cpp @@ -269,10 +269,22 @@ mesh_error_t Nanostack::ThreadInterface::device_pskd_set(const char *pskd) #define THREAD 0x2345 #if MBED_CONF_NSAPI_DEFAULT_MESH_TYPE == THREAD && DEVICE_802_15_4_PHY + MBED_WEAK MeshInterface *MeshInterface::get_target_default_instance() { - static ThreadInterface thread(&NanostackRfPhy::get_default_instance()); - - return &thread; + static bool inited; + static ThreadInterface interface; + singleton_lock(); + if (!inited) { + nsapi_error_t result = interface.initialize(&NanostackRfPhy::get_default_instance()); + if (result != 0) { + tr_error("Thread initialize failed: %d", error); + singleton_unlock(); + return NULL; + } + inited = true; + } + singleton_unlock(); + return &interface; } #endif diff --git a/features/nanostack/mbed-mesh-api/source/WisunInterface.cpp b/features/nanostack/mbed-mesh-api/source/WisunInterface.cpp index 252656a4bb..9952bdc6ea 100644 --- a/features/nanostack/mbed-mesh-api/source/WisunInterface.cpp +++ b/features/nanostack/mbed-mesh-api/source/WisunInterface.cpp @@ -178,8 +178,19 @@ bool WisunInterface::getRouterIpAddress(char *address, int8_t len) #if MBED_CONF_NSAPI_DEFAULT_MESH_TYPE == WISUN && DEVICE_802_15_4_PHY MBED_WEAK MeshInterface *MeshInterface::get_target_default_instance() { - static WisunInterface wisun(&NanostackRfPhy::get_default_instance()); - - return &wisun; + static bool inited; + static WisunInterface interface; + singleton_lock(); + if (!inited) { + nsapi_error_t result = interface.initialize(&NanostackRfPhy::get_default_instance()); + if (result != 0) { + tr_error("Wi-SUN initialize failed: %d", error); + singleton_unlock(); + return NULL; + } + inited = true; + } + singleton_unlock(); + return &interface; } #endif diff --git a/features/nanostack/mbed-mesh-api/source/ethernet_tasklet.c b/features/nanostack/mbed-mesh-api/source/ethernet_tasklet.c index d86b98a36d..e66afd0335 100644 --- a/features/nanostack/mbed-mesh-api/source/ethernet_tasklet.c +++ b/features/nanostack/mbed-mesh-api/source/ethernet_tasklet.c @@ -24,6 +24,7 @@ #include "ns_event_loop.h" #include "mesh_interface_types.h" #include "eventOS_event.h" +#include "enet_tasklet.h" // For tracing we need to define flag, have include and define group #include "ns_trace.h" @@ -119,6 +120,25 @@ void enet_tasklet_main(arm_event_s *event) case APPLICATION_EVENT: if (event->event_id == APPL_EVENT_CONNECT) { enet_tasklet_configure_and_connect_to_network(); + } else if (event->event_id == APPL_BACKHAUL_INTERFACE_PHY_UP) { + // Ethernet cable has been plugged in + arm_nwk_interface_configure_ipv6_bootstrap_set( + tasklet_data_ptr->network_interface_id, NET_IPV6_BOOTSTRAP_AUTONOMOUS, NULL); + enet_tasklet_configure_and_connect_to_network(); + + if (tasklet_data_ptr->poll_network_status_timeout != NULL) { + // Restart poll timer + eventOS_timeout_cancel(tasklet_data_ptr->poll_network_status_timeout); + } + tasklet_data_ptr->poll_network_status_timeout = + eventOS_timeout_every_ms(enet_tasklet_poll_network_status, 2000, NULL); + } else if (event->event_id == APPL_BACKHAUL_INTERFACE_PHY_DOWN) { + // Ethernet cable has been removed + arm_nwk_interface_down(tasklet_data_ptr->network_interface_id); + eventOS_timeout_cancel(tasklet_data_ptr->poll_network_status_timeout); + tasklet_data_ptr->poll_network_status_timeout = NULL; + memset(tasklet_data_ptr->ip, 0x0, 16); + enet_tasklet_network_state_changed(MESH_BOOTSTRAP_STARTED); } break; @@ -209,8 +229,18 @@ static void enet_tasklet_poll_network_status(void *param) */ void enet_tasklet_configure_and_connect_to_network(void) { - arm_nwk_interface_up(tasklet_data_ptr->network_interface_id); - enet_tasklet_network_state_changed(MESH_BOOTSTRAP_STARTED); + int8_t status; + + status = arm_nwk_interface_up(tasklet_data_ptr->network_interface_id); + if (status >= 0) { + tasklet_data_ptr->tasklet_state = TASKLET_STATE_BOOTSTRAP_STARTED; + tr_info("Start Bootstrap"); + enet_tasklet_network_state_changed(MESH_BOOTSTRAP_STARTED); + } else { + tasklet_data_ptr->tasklet_state = TASKLET_STATE_BOOTSTRAP_FAILED; + tr_err("Bootstrap start failed, %d", status); + enet_tasklet_network_state_changed(MESH_BOOTSTRAP_START_FAILED); + } } /* @@ -264,7 +294,7 @@ int8_t enet_tasklet_disconnect(bool send_cb) if (tasklet_data_ptr->network_interface_id != INVALID_INTERFACE_ID) { status = arm_nwk_interface_down(tasklet_data_ptr->network_interface_id); tasklet_data_ptr->network_interface_id = INVALID_INTERFACE_ID; - if (send_cb == true) { + if (send_cb) { enet_tasklet_network_state_changed(MESH_DISCONNECTED); } } @@ -300,3 +330,15 @@ int8_t enet_tasklet_network_init(int8_t device_id) tasklet_data_ptr->network_interface_id, NET_IPV6_BOOTSTRAP_AUTONOMOUS, NULL); return tasklet_data_ptr->network_interface_id; } + +void enet_tasklet_link_state_changed(bool up) +{ + arm_event_s event = { + .receiver = tasklet_data_ptr->tasklet, + .sender = tasklet_data_ptr->tasklet, + .event_type = APPLICATION_EVENT, + .priority = ARM_LIB_LOW_PRIORITY_EVENT, + .event_id = up ? APPL_BACKHAUL_INTERFACE_PHY_UP : APPL_BACKHAUL_INTERFACE_PHY_DOWN, + }; + eventOS_event_send(&event); +} diff --git a/features/nanostack/mbed-mesh-api/source/include/enet_tasklet.h b/features/nanostack/mbed-mesh-api/source/include/enet_tasklet.h index f8a8edf3b1..4aba04cbab 100644 --- a/features/nanostack/mbed-mesh-api/source/include/enet_tasklet.h +++ b/features/nanostack/mbed-mesh-api/source/include/enet_tasklet.h @@ -17,15 +17,49 @@ #ifndef ENET_TASKLET_H #define ENET_TASKLET_H +#include "mesh_interface_types.h" #ifdef __cplusplus extern "C" { #endif +/* + * \brief Initialize system. + */ void enet_tasklet_init(void); -uint8_t enet_tasklet_network_init(int8_t); + +/* + * \brief Create network interface. + * + * \param device_id Registered physical device. + * \return interface ID used to communication with this interface. + */ +int8_t enet_tasklet_network_init(int8_t device_id); + +/* + * \brief Connect to Ethernet network. + * + * \param callback Call when network state changes. + * \param nwk_interface_id To use for networking. + * + */ int8_t enet_tasklet_connect(void (*)(mesh_connection_status_t mesh_status), int8_t nwk_interface_id); -void enet_tasklet_disconnect(); + +/* + * \brief Disconnect network interface. + * + * \param send_cb Send possible network status change event if set to `true`. + * \return >= 0 if disconnected successfully. + * \return < 0 if error. + */ +int8_t enet_tasklet_disconnect(bool send_cb); + +/* + * \brief Callback to call when the link state changes. + * + * \param up Tells if link is up or down. + */ +void enet_tasklet_link_state_changed(bool up); #ifdef __cplusplus } diff --git a/features/nanostack/mbed-mesh-api/source/include/mesh_system.h b/features/nanostack/mbed-mesh-api/source/include/mesh_system.h index 43fef4c4f0..66b0a9bbaf 100644 --- a/features/nanostack/mbed-mesh-api/source/include/mesh_system.h +++ b/features/nanostack/mbed-mesh-api/source/include/mesh_system.h @@ -25,7 +25,11 @@ extern "C" { /* * Event type for connecting */ -#define APPL_EVENT_CONNECT 0x01 +enum { + APPL_EVENT_CONNECT = 0x01, + APPL_BACKHAUL_INTERFACE_PHY_DOWN, + APPL_BACKHAUL_INTERFACE_PHY_UP +}; /* * \brief Send application connect event to receiver tasklet to diff --git a/features/nanostack/mbed-mesh-api/source/wisun_tasklet.c b/features/nanostack/mbed-mesh-api/source/wisun_tasklet.c index 194c9bb851..9b751248cb 100644 --- a/features/nanostack/mbed-mesh-api/source/wisun_tasklet.c +++ b/features/nanostack/mbed-mesh-api/source/wisun_tasklet.c @@ -27,6 +27,7 @@ #include "multicast_api.h" #include "mac_api.h" #include "sw_mac.h" +#include "ws_management_api.h" //ws_management_node_init // For tracing we need to define flag, have include and define group //#define HAVE_DEBUG @@ -255,7 +256,7 @@ int8_t wisun_tasklet_connect(mesh_interface_cb callback, int8_t nwk_interface_id re_connecting = false; } - memset(wisun_tasklet_data_ptr, 0, sizeof(wisun_tasklet_data_ptr)); + memset(wisun_tasklet_data_ptr, 0, sizeof(wisun_tasklet_data_str_t)); wisun_tasklet_data_ptr->mesh_api_cb = callback; wisun_tasklet_data_ptr->network_interface_id = nwk_interface_id; wisun_tasklet_data_ptr->tasklet_state = TASKLET_STATE_INITIALIZED; diff --git a/features/netsocket/TCPSocket.cpp b/features/netsocket/TCPSocket.cpp index a88fece796..b2c9f5a0e0 100644 --- a/features/netsocket/TCPSocket.cpp +++ b/features/netsocket/TCPSocket.cpp @@ -288,6 +288,8 @@ TCPSocket *TCPSocket::accept(nsapi_error_t *error) if (0 == ret) { connection = new TCPSocket(this, socket, address); + _socket_stats.stats_update_peer(connection, address); + _socket_stats.stats_update_socket_state(connection, SOCK_CONNECTED); break; } else if ((_timeout == 0) || (ret != NSAPI_ERROR_WOULD_BLOCK)) { break; diff --git a/features/netsocket/emac-drivers/TARGET_GD_EMAC/TARGET_GD32F30X/gd32f3_eth_init.c b/features/netsocket/emac-drivers/TARGET_GD_EMAC/TARGET_GD32F30X/gd32f3_eth_init.c new file mode 100644 index 0000000000..326acd8de1 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_GD_EMAC/TARGET_GD32F30X/gd32f3_eth_init.c @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gd32f30x.h" + +/** + * Initializes the HW pin for enet + * + */ +void enet_bsp_init(void) +{ + /* Enable GPIOs clocks */ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_AF); + + gpio_para_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_8); + rcu_pll2_config(RCU_PLL2_MUL10); + rcu_osci_on(RCU_PLL2_CK); + rcu_osci_stab_wait(RCU_PLL2_CK); + rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2); + gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + /* PA1: ETH_RMII_REF_CLK */ + gpio_para_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_1); + /* PA2: ETH_MDIO */ + gpio_para_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_2); + /* PA7: ETH_RMII_CRS_DV */ + gpio_para_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_7); + + /* PB11: ETH_RMII_TX_EN */ + gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_11); + /* PB12: ETH_RMII_TXD0 */ + gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_12); + /* PB13: ETH_RMII_TXD1 */ + gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_13); + + /* PC1: ETH_MDC */ + gpio_para_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_1); + /* PC4: ETH_RMII_RXD0 */ + gpio_para_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_4); + /* PC5: ETH_RMII_RXD1 */ + gpio_para_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_5); + + /* Enable the Ethernet global Interrupt */ + nvic_irq_enable(ENET_IRQn, 0x7, 0); + + /* Enable ETHERNET clock */ + rcu_periph_clock_enable(RCU_ENET); + rcu_periph_clock_enable(RCU_ENETTX); + rcu_periph_clock_enable(RCU_ENETRX); +} diff --git a/features/netsocket/emac-drivers/TARGET_GD_EMAC/gd32xx_emac.cpp b/features/netsocket/emac-drivers/TARGET_GD_EMAC/gd32xx_emac.cpp new file mode 100644 index 0000000000..8dc808d9f5 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_GD_EMAC/gd32xx_emac.cpp @@ -0,0 +1,505 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "cmsis_os.h" + +#include "mbed_interface.h" +#include "mbed_assert.h" +#include "mbed_shared_queues.h" +#include "netsocket/nsapi_types.h" + +#include "gd32xx_emac.h" + +/* \brief Flags for worker thread */ +#define _ENET_FLAG_RX (1) + +/** \brief Driver thread priority */ +#define _THREAD_STACKSIZE (512) +#define _THREAD_PRIORITY (osPriorityHigh) + +#define _PHY_TASK_PERIOD_MS (200) + +#define _ENET_HW_ADDR_SIZE (6) +#define _ENET_MTU_SIZE (1500) +#define _ENET_IF_NAME "gd" + +#define _ENET_BOARD_PHY_ADDRESS (0x01) +#define _ENET_HARDWARE_CHECKSUM (0) + +#define _GD_MAC_ADDR0 0x02 +#define _GD_MAC_ADDR1 0xaa +#define _GD_MAC_ADDR2 0xbb +#define _GD32_ID_ADDR 0x1FFFF7E8 +/* ENET RxDMA/TxDMA descriptor */ +extern enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM], txdesc_tab[ENET_TXBUF_NUM]; +/* ENET receive buffer */ +extern uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; +/* ENET transmit buffer */ +extern uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; +/*global transmit and receive descriptors pointers */ +extern enet_descriptors_struct *dma_current_txdesc; +extern enet_descriptors_struct *dma_current_rxdesc; + +#ifdef __cplusplus +extern "C" { +#endif + +void ENET_IRQHandler(void); +void enet_bsp_init(void); +#ifdef __cplusplus +} +#endif + +/** + * Ethernet IRQ Handler + * + */ +void ENET_IRQHandler(void) +{ + /* frame received */ + if (SET == enet_interrupt_flag_get(ENET_DMA_INT_FLAG_RS)) { + /* clear the enet DMA Rx interrupt pending bits */ + enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_RS_CLR); + enet_interrupt_flag_clear(ENET_DMA_INT_FLAG_NI_CLR); + /* Ethernet Rx Transfer completed callback */ + GD32_EMAC &emac = GD32_EMAC::get_instance(); + if (emac.rx_thread) { + osThreadFlagsSet(emac.rx_thread, _ENET_FLAG_RX); + } + } +} + +GD32_EMAC::GD32_EMAC() + : rx_thread(0), + phy_status(0) +{ +} + +static osThreadId_t create_new_thread(const char *threadName, void (*thread)(void *arg), void *arg, int stacksize, osPriority_t priority, mbed_rtos_storage_thread_t *thread_cb) +{ + osThreadAttr_t attr = {0}; + attr.name = threadName; + attr.stack_mem = malloc(stacksize); + attr.cb_mem = thread_cb; + attr.stack_size = stacksize; + attr.cb_size = sizeof(mbed_rtos_storage_thread_t); + attr.priority = priority; + return osThreadNew(thread, arg, &attr); +} + +/** \brief Low level init of the MAC and PHY. + * + */ +bool GD32_EMAC::low_level_init() +{ + /* Init ETH */ + uint8_t macaddr[6]; + uint32_t i; + +#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE) + MACAddr[0] = MBED_MAC_ADDR_0; + MACAddr[1] = MBED_MAC_ADDR_1; + MACAddr[2] = MBED_MAC_ADDR_2; + MACAddr[3] = MBED_MAC_ADDR_3; + MACAddr[4] = MBED_MAC_ADDR_4; + MACAddr[5] = MBED_MAC_ADDR_5; +#else + mbed_mac_address((char *)macaddr); +#endif + + enet_bsp_init(); + /* reset ethernet on AHB bus */ + enet_deinit(); + + if (ERROR == enet_software_reset()) { + while (1); + } + +#if (1 == _ENET_HARDWARE_CHECKSUM) + if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS)) { + while (1); + } +#else + if (ERROR == enet_init(ENET_AUTO_NEGOTIATION, ENET_NO_AUTOCHECKSUM, ENET_BROADCAST_FRAMES_PASS)) { + while (1); + } +#endif + /* initialize MAC address in ethernet MAC */ + enet_mac_address_set(ENET_MAC_ADDRESS0, macaddr); + + enet_interrupt_enable(ENET_DMA_INT_NIE); + enet_interrupt_enable(ENET_DMA_INT_RIE); + + /* Initialize Tx Descriptors list: Chain Mode */ + enet_descriptors_chain_init(ENET_DMA_TX); + +#if (1 == _ENET_HARDWARE_CHECKSUM) + /* enable the TCP, UDP and ICMP checksum insertion for the Tx frames */ + for (i = 0; i < ENET_TXBUF_NUM; i++) { + enet_transmit_checksum_config(&txdesc_tab[i], ENET_CHECKSUM_TCPUDPICMP_FULL); + } +#endif + + /* Initialize Rx Descriptors list: Chain Mode */ + enet_descriptors_chain_init(ENET_DMA_RX); + + /* enable ethernet Rx interrrupt */ + for (i = 0; i < ENET_RXBUF_NUM; i++) { + enet_rx_desc_immediate_receive_complete_interrupt(&rxdesc_tab[i]); + } + + /* enable MAC and DMA transmission and reception */ + enet_enable(); + + return true; +} + +/** + * Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ +bool GD32_EMAC::link_out(emac_mem_buf_t *buf) +{ + emac_mem_buf_t *q; + uint8_t *buffer; + uint16_t framelength = 0; + + /* Get exclusive access */ + TXLockMutex.lock(); + + while ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) {} + + /* copy frame from pbufs to driver buffers */ + buffer = reinterpret_cast(enet_desc_information_get(dma_current_txdesc, TXDESC_BUFFER_1_ADDR)); + + for (q = buf; q != NULL; q = memory_manager->get_next(q)) { + memcpy(static_cast(&buffer[framelength]), static_cast(memory_manager->get_ptr(q)), memory_manager->get_len(q)); + framelength = framelength + memory_manager->get_len(q); + } + + /* Prepare transmit descriptors to give to DMA */ + if (SUCCESS != ENET_NOCOPY_FRAME_TRANSMIT(framelength)) { + while (1); + } + + memory_manager->free(buf); + /* Restore access */ + TXLockMutex.unlock(); + + return true; +} + +/** \brief Attempt to read a packet from the EMAC interface. + * + */ +emac_mem_buf_t *GD32_EMAC::low_level_input(void) +{ + emac_mem_buf_t *p = NULL, *q; + uint32_t l = 0; + uint16_t len; + uint8_t *buffer; + + /* obtain the size of the packet and put it into the "len" variable. */ + len = enet_desc_information_get(dma_current_rxdesc, RXDESC_FRAME_LENGTH); + buffer = reinterpret_cast(enet_desc_information_get(dma_current_rxdesc, RXDESC_BUFFER_1_ADDR)); + + if (len > 0) { + /* Allocate a memory buffer chain from buffer pool */ + p = memory_manager->alloc_pool(len, 0); + } else { + return p; + } + + if (p != NULL) { + for (q = p; q != NULL; q = memory_manager->get_next(q)) { + memcpy(static_cast(memory_manager->get_ptr(q)), static_cast(&buffer[l]), memory_manager->get_len(q)); + l = l + memory_manager->get_len(q); + } + } + ENET_NOCOPY_FRAME_RECEIVE(); + + return p; +} + + +/** \brief Attempt to read a packet from the EMAC interface. + * + */ +void GD32_EMAC::packet_rx() +{ + /* move received packet into a new buf */ + while (1) { + emac_mem_buf_t *p = NULL; + p = low_level_input(); + + if (p) { + emac_link_input_cb(p); + } else { + break; + } + } +} + +/** \brief Worker thread. + * + * Woken by thread flags to receive packets or clean up transmit + * + * \param[in] pvParameters pointer to the interface data + */ +void GD32_EMAC::thread_function(void *pvParameters) +{ + static struct GD32_EMAC *gd32_enet = static_cast(pvParameters); + + while (1) { + uint32_t flags = osThreadFlagsWait(_ENET_FLAG_RX, osFlagsWaitAny, osWaitForever); + + if (flags & _ENET_FLAG_RX) { + gd32_enet->packet_rx(); + } + } +} + +/** + * This task checks phy link status and updates net status + */ +void GD32_EMAC::phy_task() +{ + uint16_t regval; + + enet_phy_write_read(ENET_PHY_READ, _ENET_BOARD_PHY_ADDRESS, PHY_REG_BSR, ®val); + if (emac_link_state_cb) { + regval &= PHY_LINKED_STATUS; + + if (phy_status != regval) { + if (regval == PHY_LINKED_STATUS) { + emac_link_state_cb(true);; + } else { + emac_link_state_cb(false); + } + } + } + + phy_status = regval; +} + +void GD32_EMAC::eth_arch_enable_interrupts(void) +{ + nvic_irq_enable(ENET_IRQn, 7, 0); +} + +void GD32_EMAC::eth_arch_disable_interrupts(void) +{ + nvic_irq_disable(ENET_IRQn); +} + +/** This returns a unique 6-byte MAC address, based on the device UID +* This function overrides hal/common/mbed_interface.c function +* @param mac A 6-byte array to write the MAC address +*/ +void mbed_mac_address(char *mac) +{ + uint32_t unique_id; + + unique_id = *(uint32_t *)_GD32_ID_ADDR; + mac[0] = _GD_MAC_ADDR0; + mac[1] = _GD_MAC_ADDR1; + mac[2] = _GD_MAC_ADDR2; + mac[3] = (unique_id & 0x00ff0000) >> 16; + mac[4] = (unique_id & 0x0000ff00) >> 8; + mac[5] = (unique_id & 0x000000ff); +} + +/** + * Initializes the HW + * + * @return True on success, False in case of an error. + */ +bool GD32_EMAC::power_up() +{ + /* Initialize the hardware */ + if (true != low_level_init()) { + return false; + } + + /* Worker thread */ + rx_thread = create_new_thread("gd32_emac_thread", &GD32_EMAC::thread_function, this, _THREAD_STACKSIZE, _THREAD_PRIORITY, &rx_thread_cb); + + phy_task_handle = mbed::mbed_event_queue()->call_every(_PHY_TASK_PERIOD_MS, mbed::callback(this, &GD32_EMAC::phy_task)); + + /* Allow the PHY task to detect the initial link state and set up the proper flags */ + osDelay(10); + + eth_arch_enable_interrupts(); + + return true; +} + +/** + * Return maximum transmission unit + * + * @return MTU in bytes + */ +uint32_t GD32_EMAC::get_mtu_size() const +{ + return _ENET_MTU_SIZE; +} + +/** + * Gets memory buffer alignment preference + * + * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not + * align link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes + */ +uint32_t GD32_EMAC::get_align_preference() const +{ + return 0; +} + +/** + * Return interface name + * + * @param name Pointer to where the name should be written + * @param size Maximum number of character to copy + */ +void GD32_EMAC::get_ifname(char *name, uint8_t size) const +{ + memcpy(name, _ENET_IF_NAME, (size < sizeof(_ENET_IF_NAME)) ? size : sizeof(_ENET_IF_NAME)); +} + +/** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ +uint8_t GD32_EMAC::get_hwaddr_size() const +{ + return _ENET_HW_ADDR_SIZE; +} + +/** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ +bool GD32_EMAC::get_hwaddr(uint8_t *addr) const +{ + mbed_mac_address((char *)addr); + return true; +} + +/** + * Set HW address for interface + * + * Provided address has to be of correct size, see @a get_hwaddr_size + * + * Called to set the MAC address to actually use - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden, eg for test + * purposes. + * + * @param addr Address to be set + */ +void GD32_EMAC::set_hwaddr(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +/** + * Sets a callback that needs to be called for packets received for that interface + * + * @param input_cb Function to be register as a callback + */ +void GD32_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + emac_link_input_cb = input_cb; +} + +/** + * Sets a callback that needs to be called on link status changes for given interface + * + * @param state_cb Function to be register as a callback + */ +void GD32_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + emac_link_state_cb = state_cb; +} + +/** Add device to a multicast group + * + * @param address A multicast group hardware address + */ +void GD32_EMAC::add_multicast_group(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +/** Remove device from a multicast group + * + * @param address A multicast group hardware address + */ +void GD32_EMAC::remove_multicast_group(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +/** Request reception of all multicast packets + * + * @param all True to receive all multicasts + * False to receive only multicasts addressed to specified groups + */ +void GD32_EMAC::set_all_multicast(bool all) +{ + /* No-op at this stage */ +} + +/** + * Deinitializes the HW + * + */ +void GD32_EMAC::power_down() +{ + /* No-op at this stage */ +} + +/** Sets memory manager that is used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager + */ +void GD32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + memory_manager = &mem_mngr; +} + +GD32_EMAC &GD32_EMAC::get_instance() +{ + static GD32_EMAC emac; + return emac; +} + +/* Weak so a module can override */ +MBED_WEAK EMAC &EMAC::get_default_instance() +{ + return GD32_EMAC::get_instance(); +} diff --git a/features/netsocket/emac-drivers/TARGET_GD_EMAC/gd32xx_emac.h b/features/netsocket/emac-drivers/TARGET_GD_EMAC/gd32xx_emac.h new file mode 100644 index 0000000000..e88ab32073 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_GD_EMAC/gd32xx_emac.h @@ -0,0 +1,176 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 Gigadevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef GD32_EMAC_H_ +#define GD32_EMAC_H_ + +#include "EMAC.h" +#include "rtos/Semaphore.h" +#include "rtos/Mutex.h" + +class GD32_EMAC : public EMAC { +public: + GD32_EMAC(); + + static GD32_EMAC &get_instance(); + + /** + * Return maximum transmission unit + * + * @return MTU in bytes + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets memory buffer alignment preference + * + * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not + * align link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes + */ + virtual uint32_t get_align_preference() const; + + /** + * Return interface name + * + * @param name Pointer to where the name should be written + * @param size Maximum number of character to copy + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Return interface-supplied HW address + * + * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size + * + * HW address need not be provided if this interface does not have its own HW + * address configuration; stack will choose address from central system + * configuration if the function returns false and does not write to addr. + * + * @param addr HW address for underlying interface + * @return true if HW address is available + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for interface + * + * Provided address has to be of correct size, see @a get_hwaddr_size + * + * Called to set the MAC address to actually use - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden, eg for test + * purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success, False in case of an error. + */ + virtual bool power_up(); + + /** + * Deinitializes the HW + * + */ + virtual void power_down(); + + /** + * Sets a callback that needs to be called for packets received for that interface + * + * @param input_cb Function to be register as a callback + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that needs to be called on link status changes for given interface + * + * @param state_cb Function to be register as a callback + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Add device to a multicast group + * + * @param address A multicast group hardware address + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Remove device from a multicast group + * + * @param address A multicast group hardware address + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Request reception of all multicast packets + * + * @param all True to receive all multicasts + * False to receive only multicasts addressed to specified groups + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager that is used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + + /* Called from driver functions */ + osThreadId_t rx_thread; /**< Processing rx thread */ + +private: + bool low_level_init(); + void packet_rx(); + emac_mem_buf_t *low_level_input(void); + static void thread_function(void *pvParameters); + void phy_task(); + void eth_arch_enable_interrupts(); + void eth_arch_disable_interrupts(); + + mbed_rtos_storage_thread_t rx_thread_cb; + + rtos::Mutex TXLockMutex;/**< TX critical section mutex */ + emac_link_input_cb_t emac_link_input_cb; /**< Callback for incoming data */ + emac_link_state_change_cb_t emac_link_state_cb; /**< Link state change callback */ + EMACMemoryManager *memory_manager; /**< Memory manager */ + + uint32_t phy_status; + int phy_task_handle; /**< Handle for phy task event */ +}; + +#endif /* GD32_EMAC_H_ */ diff --git a/features/nfc/nfc/NFCEEPROM.h b/features/nfc/nfc/NFCEEPROM.h index e431823caf..1e940c745a 100644 --- a/features/nfc/nfc/NFCEEPROM.h +++ b/features/nfc/nfc/NFCEEPROM.h @@ -144,6 +144,7 @@ private: Delegate *_delegate; NFCEEPROMDriver *_driver; + events::EventQueue *_event_queue; bool _initialized; nfc_eeprom_operation_t _current_op; diff --git a/features/nfc/source/nfc/NFCEEPROM.cpp b/features/nfc/source/nfc/NFCEEPROM.cpp index 1772b63fa1..01f2715a85 100644 --- a/features/nfc/source/nfc/NFCEEPROM.cpp +++ b/features/nfc/source/nfc/NFCEEPROM.cpp @@ -21,7 +21,7 @@ using namespace mbed; using namespace mbed::nfc; NFCEEPROM::NFCEEPROM(NFCEEPROMDriver *driver, events::EventQueue *queue, const Span &ndef_buffer) : NFCTarget(ndef_buffer), - _delegate(NULL), _driver(driver), _initialized(false), _current_op(nfc_eeprom_idle), _ndef_buffer_read_sz(0), _eeprom_address(0), _operation_result(NFC_ERR_UNKNOWN) + _delegate(NULL), _driver(driver), _event_queue(queue), _initialized(false), _current_op(nfc_eeprom_idle), _ndef_buffer_read_sz(0), _eeprom_address(0), _operation_result(NFC_ERR_UNKNOWN) { _driver->set_delegate(this); _driver->set_event_queue(queue); @@ -68,7 +68,6 @@ void NFCEEPROM::write_ndef_message() // Reset EEPROM address _eeprom_address = 0; - // Go through the steps! _driver->start_session(); @@ -87,7 +86,6 @@ void NFCEEPROM::read_ndef_message() } return; } - _current_op = nfc_eeprom_read_start_session; // Reset EEPROM address @@ -114,7 +112,6 @@ void NFCEEPROM::erase_ndef_message() } return; } - _current_op = nfc_eeprom_erase_start_session; // Reset EEPROM address @@ -230,7 +227,7 @@ void NFCEEPROM::on_bytes_read(size_t count) ac_buffer_builder_write_n_skip(buffer_builder, count); // Continue reading - continue_read(); + _event_queue->call(this, &NFCEEPROM::continue_read); break; } default: @@ -254,7 +251,7 @@ void NFCEEPROM::on_bytes_written(size_t count) ac_buffer_read_n_skip(&_ndef_buffer_reader, count); // Continue writing - continue_write(); + _event_queue->call(this, &NFCEEPROM::continue_write); break; default: // Should not happen, state machine is broken or driver is doing something wrong @@ -331,7 +328,7 @@ void NFCEEPROM::on_size_read(bool success, size_t size) // Start reading bytes _current_op = nfc_eeprom_read_read_bytes; - continue_read(); + _event_queue->call(this, &NFCEEPROM::continue_read); break; } default: @@ -343,6 +340,7 @@ void NFCEEPROM::on_size_read(bool success, size_t size) void NFCEEPROM::on_bytes_erased(size_t count) { + switch (_current_op) { case nfc_eeprom_erase_erase_bytes: if (count == 0) { @@ -354,7 +352,7 @@ void NFCEEPROM::on_bytes_erased(size_t count) _eeprom_address += count; // Continue erasing - continue_erase(); + _event_queue->call(this, &NFCEEPROM::continue_erase); break; default: // Should not happen, state machine is broken or driver is doing something wrong diff --git a/features/storage/TESTS/filesystem/fat_filesystem/main.cpp b/features/storage/TESTS/filesystem/fat_filesystem/main.cpp index cca9acca1c..86f7b68dd1 100644 --- a/features/storage/TESTS/filesystem/fat_filesystem/main.cpp +++ b/features/storage/TESTS/filesystem/fat_filesystem/main.cpp @@ -29,15 +29,26 @@ using namespace utest::v1; #error [NOT_SUPPORTED] Filesystem tests not supported by default #endif +static const int mem_alloc_threshold = 32 * 1024; + // Test block device #define BLOCK_SIZE 512 -HeapBlockDevice bd(128 * BLOCK_SIZE, BLOCK_SIZE); +#define BLOCK_COUNT 128 +HeapBlockDevice *bd = 0; // Test formatting void test_format() { - int err = FATFileSystem::format(&bd); + uint8_t *dummy = new (std::nothrow) uint8_t[mem_alloc_threshold]; + TEST_SKIP_UNLESS_MESSAGE(dummy, "Not enough heap memory to run test. Test skipped."); + + delete[] dummy; + + bd = new (std::nothrow) HeapBlockDevice(BLOCK_COUNT * BLOCK_SIZE, BLOCK_SIZE); + TEST_SKIP_UNLESS_MESSAGE(bd, "Not enough heap memory to run test. Test skipped."); + + int err = FATFileSystem::format(bd); TEST_ASSERT_EQUAL(0, err); } @@ -46,13 +57,15 @@ void test_format() template void test_read_write() { + TEST_SKIP_UNLESS_MESSAGE(bd, "Not enough heap memory to run test. Test skipped."); + FATFileSystem fs("fat"); - int err = fs.mount(&bd); + int err = fs.mount(bd); TEST_ASSERT_EQUAL(0, err); - uint8_t *buffer = (uint8_t *)malloc(TEST_SIZE); - TEST_ASSERT(buffer); + uint8_t *buffer = new (std::nothrow) uint8_t[TEST_SIZE]; + TEST_SKIP_UNLESS_MESSAGE(buffer, "Not enough heap memory to run test. Test skipped."); // Fill with random sequence srand(1); @@ -84,15 +97,19 @@ void test_read_write() err = fs.unmount(); TEST_ASSERT_EQUAL(0, err); + + delete[] buffer; } // Simple test for iterating dir entries void test_read_dir() { + TEST_SKIP_UNLESS_MESSAGE(bd, "Not enough heap memory to run test. Test skipped."); + FATFileSystem fs("fat"); - int err = fs.mount(&bd); + int err = fs.mount(bd); TEST_ASSERT_EQUAL(0, err); err = fs.mkdir("test_read_dir", S_IRWXU | S_IRWXG | S_IRWXO); @@ -146,6 +163,9 @@ void test_read_dir() err = fs.unmount(); TEST_ASSERT_EQUAL(0, err); + + delete bd; + bd = 0; } diff --git a/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp b/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp index 91dc8c1683..de1d8405e0 100644 --- a/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp +++ b/features/storage/TESTS/filesystem/multipart_fat_filesystem/main.cpp @@ -30,28 +30,36 @@ using namespace utest::v1; #error [NOT_SUPPORTED] Filesystem tests not supported by default #endif +static const int mem_alloc_threshold = 32 * 1024; + // Test block device #define BLOCK_SIZE 512 #define BLOCK_COUNT 512 -HeapBlockDevice bd(BLOCK_COUNT *BLOCK_SIZE, BLOCK_SIZE); - +HeapBlockDevice *bd = 0; // Test formatting and partitioning void test_format() { + uint8_t *dummy = new (std::nothrow) uint8_t[mem_alloc_threshold]; + TEST_SKIP_UNLESS_MESSAGE(dummy, "Not enough heap memory to run test. Test skipped."); + delete[] dummy; + + bd = new (std::nothrow) HeapBlockDevice(BLOCK_COUNT * BLOCK_SIZE, BLOCK_SIZE); + TEST_SKIP_UNLESS_MESSAGE(bd, "Not enough heap memory to run test. Test skipped."); + // Create two partitions splitting device in ~half - int err = MBRBlockDevice::partition(&bd, 1, 0x83, 0, (BLOCK_COUNT / 2) * BLOCK_SIZE); + int err = MBRBlockDevice::partition(bd, 1, 0x83, 0, (BLOCK_COUNT / 2) * BLOCK_SIZE); TEST_ASSERT_EQUAL(0, err); - err = MBRBlockDevice::partition(&bd, 2, 0x83, -(BLOCK_COUNT / 2) * BLOCK_SIZE); + err = MBRBlockDevice::partition(bd, 2, 0x83, -(BLOCK_COUNT / 2) * BLOCK_SIZE); TEST_ASSERT_EQUAL(0, err); // Load both partitions - MBRBlockDevice part1(&bd, 1); + MBRBlockDevice part1(bd, 1); err = part1.init(); TEST_ASSERT_EQUAL(0, err); - MBRBlockDevice part2(&bd, 2); + MBRBlockDevice part2(bd, 2); err = part2.init(); TEST_ASSERT_EQUAL(0, err); @@ -75,12 +83,14 @@ void test_format() template void test_read_write() { + TEST_SKIP_UNLESS_MESSAGE(bd, "Not enough heap memory to run test. Test skipped."); + // Load both partitions - MBRBlockDevice part1(&bd, 1); + MBRBlockDevice part1(bd, 1); int err = part1.init(); TEST_ASSERT_EQUAL(0, err); - MBRBlockDevice part2(&bd, 2); + MBRBlockDevice part2(bd, 2); err = part2.init(); TEST_ASSERT_EQUAL(0, err); @@ -94,11 +104,11 @@ void test_read_write() err = fs2.mount(&part2); TEST_ASSERT_EQUAL(0, err); - uint8_t *buffer1 = (uint8_t *)malloc(TEST_SIZE); - TEST_ASSERT(buffer1); + uint8_t *buffer1 = new (std::nothrow) uint8_t[TEST_SIZE]; + TEST_SKIP_UNLESS_MESSAGE(buffer1, "Not enough heap memory to run test. Test skipped."); - uint8_t *buffer2 = (uint8_t *)malloc(TEST_SIZE); - TEST_ASSERT(buffer2); + uint8_t *buffer2 = new (std::nothrow) uint8_t[TEST_SIZE]; + TEST_SKIP_UNLESS_MESSAGE(buffer2, "Not enough heap memory to run test. Test skipped."); // Fill with random sequence srand(1); @@ -163,47 +173,55 @@ void test_read_write() err = part2.deinit(); TEST_ASSERT_EQUAL(0, err); + + delete[] buffer1; + delete[] buffer2; } void test_single_mbr() { - int err = bd.init(); + TEST_SKIP_UNLESS_MESSAGE(bd, "Not enough heap memory to run test. Test skipped."); + + int err = bd->init(); TEST_ASSERT_EQUAL(0, err); const bd_addr_t MBR_OFFSET = 0; const bd_addr_t FAT1_OFFSET = 1; const bd_addr_t FAT2_OFFSET = BLOCK_COUNT / 2; - uint8_t *buffer = (uint8_t *)malloc(BLOCK_SIZE); - TEST_ASSERT(buffer); + uint8_t *buffer = new (std::nothrow) uint8_t[BLOCK_SIZE]; + TEST_SKIP_UNLESS_MESSAGE(buffer, "Not enough heap memory to run test. Test skipped."); // Check that all three header blocks have the 0x55aa signature - err = bd.read(buffer, MBR_OFFSET * BLOCK_SIZE, BLOCK_SIZE); + err = bd->read(buffer, MBR_OFFSET * BLOCK_SIZE, BLOCK_SIZE); TEST_ASSERT_EQUAL(0, err); TEST_ASSERT(memcmp(&buffer[BLOCK_SIZE - 2], "\x55\xaa", 2) == 0); - err = bd.read(buffer, FAT1_OFFSET * BLOCK_SIZE, BLOCK_SIZE); + err = bd->read(buffer, FAT1_OFFSET * BLOCK_SIZE, BLOCK_SIZE); TEST_ASSERT_EQUAL(0, err); TEST_ASSERT(memcmp(&buffer[BLOCK_SIZE - 2], "\x55\xaa", 2) == 0); - err = bd.read(buffer, FAT2_OFFSET * BLOCK_SIZE, BLOCK_SIZE); + err = bd->read(buffer, FAT2_OFFSET * BLOCK_SIZE, BLOCK_SIZE); TEST_ASSERT_EQUAL(0, err); TEST_ASSERT(memcmp(&buffer[BLOCK_SIZE - 2], "\x55\xaa", 2) == 0); // Check that the headers for both filesystems contain a jump code // indicating they are actual FAT superblocks and not an extra MBR - err = bd.read(buffer, FAT1_OFFSET * BLOCK_SIZE, BLOCK_SIZE); + err = bd->read(buffer, FAT1_OFFSET * BLOCK_SIZE, BLOCK_SIZE); TEST_ASSERT_EQUAL(0, err); TEST_ASSERT(buffer[0] == 0xe9 || buffer[0] == 0xeb || buffer[0] == 0xe8); - err = bd.read(buffer, FAT2_OFFSET * BLOCK_SIZE, BLOCK_SIZE); + err = bd->read(buffer, FAT2_OFFSET * BLOCK_SIZE, BLOCK_SIZE); TEST_ASSERT_EQUAL(0, err); TEST_ASSERT(buffer[0] == 0xe9 || buffer[0] == 0xeb || buffer[0] == 0xe8); - free(buffer); + delete[] buffer; - bd.deinit(); + bd->deinit(); TEST_ASSERT_EQUAL(0, err); + + delete bd; + bd = 0; } diff --git a/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp b/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp index 5c299765ff..2dab435e7b 100644 --- a/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp +++ b/features/storage/TESTS/kvstore/general_tests_phase_1/main.cpp @@ -207,7 +207,7 @@ static void set_buffer_size_is_zero() int res = kvstore->set(key, data, 0, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -225,7 +225,7 @@ static void set_same_key_several_time() res = kvstore->set(key, data, data_size, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -239,7 +239,7 @@ static void test_thread_set(char *th_key) static void set_several_keys_multithreaded() { TEST_SKIP_UNLESS(kvstore != NULL); - + int i = 0, res = 0; rtos::Thread kvstore_thread[num_of_threads]; osStatus threadStatus; @@ -248,23 +248,25 @@ static void set_several_keys_multithreaded() kvstore_thread[2].start(callback(test_thread_set, (char *)keys[2])); - for (int i = 0; i < num_of_threads; i++) { + for (i = 0; i < num_of_threads; i++) { threadStatus = kvstore_thread[i].join(); if (threadStatus != 0) { utest_printf("\nthread %d join failed!", i + 1); } } - for (int i = 0; i < num_of_threads; i++) { - int res = kvstore->get(keys[i], buffer, buffer_size, &actual_size, 0); + for (i = 0; i < num_of_threads; i++) { + res = kvstore->get(keys[i], buffer, buffer_size, &actual_size, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); TEST_ASSERT_EQUAL_STRING_LEN(buffer, data, data_size); } - int res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + for (i = 0; i < num_of_threads; i++) { + res = kvstore->remove(keys[i]); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + } } //set key "write once" and try to set it again @@ -313,7 +315,7 @@ static void set_key_value_one_byte_size() TEST_ASSERT_EQUAL_ERROR_CODE(0, res); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -330,7 +332,7 @@ static void set_key_value_two_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_two, 1); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -347,7 +349,7 @@ static void set_key_value_five_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_five, 4); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -364,7 +366,7 @@ static void set_key_value_fifteen_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_fif, 14); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -381,36 +383,78 @@ static void set_key_value_seventeen_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_fif, 16); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } -//set several different key value byte size +//set several different keys and retrieve them static void set_several_key_value_sizes() { TEST_SKIP_UNLESS(kvstore != NULL); char name[7] = "name_"; - char c[2] = {0}; + char c = 0; int i = 0, res = 0; - for (i = 0; i < 30; i++) { - c[0] = i + '0'; - name[6] = c[0]; + name[6] = 0; + + for (i = 0; i < 26; i++) { + c = i + 'a'; + name[5] = c; res = kvstore->set(name, name, sizeof(name), 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } - for (i = 0; i < 30; i++) { - c[0] = i + '0'; - name[6] = c[0]; + for (i = 0; i < 26; i++) { + c = i + 'a'; + name[5] = c; res = kvstore->get(name, buffer, sizeof(buffer), &actual_size, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); TEST_ASSERT_EQUAL_STRING_LEN(name, buffer, sizeof(name)); memset(buffer, 0, sizeof(buffer)); - } - res = kvstore->reset(); + res = kvstore->remove(name); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + } +} + +//try to set several different unvalid key names +static void set_several_unvalid_key_names() +{ + TEST_SKIP_UNLESS(kvstore != NULL); + + char name[7] = "name_"; + char unvalid[] = {'*', '?', ':', ';', '"', '|', ' ', '<', '>', '\\', '/'}; + int i = 0, res = 0; + + name[6] = 0; + + for (i = 0; i < 11; i++) { + name[5] = unvalid[i]; + res = kvstore->set(name, name, sizeof(name), 0); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_INVALID_ARGUMENT, res); + } +} + +//set key initialize kvstore and retrieve it +static void set_key_init_deinit() +{ + TEST_SKIP_UNLESS(kvstore != NULL); + + int res = kvstore->set(key, data, data_size, 0); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + + res = kvstore->deinit(); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + + res = kvstore->init(); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + + res = kvstore->get(key, buffer, buffer_size, &actual_size, 0); + TEST_ASSERT_EQUAL_STRING(buffer, data); + memset(buffer, 0, buffer_size); + + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -453,29 +497,13 @@ static void Sec_set_key_encrypt() res = kvstore->get(key, buffer, sizeof(buffer), &actual_size, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); TEST_ASSERT_EQUAL_STRING_LEN(data, buffer, sizeof(data)); + + res = kvstore->get_info(key, &info); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + TEST_ASSERT_EQUAL_ERROR_CODE(KVStore::REQUIRE_CONFIDENTIALITY_FLAG, info.flags); memset(buffer, 0, sizeof(buffer)); - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); -} - -//set key with AUTH flag and retrieve it -static void Sec_set_key_auth() -{ - TEST_SKIP_UNLESS(kvstore != NULL); - if (kv_setup != SecStoreSet) { - return; - } - - int res = kvstore->set(key, data, data_size, 0); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - - res = kvstore->get(key, buffer, sizeof(buffer), &actual_size, 0); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - TEST_ASSERT_EQUAL_STRING_LEN(data, buffer, sizeof(data)); - memset(buffer, 0, sizeof(buffer)); - - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -537,7 +565,7 @@ static void get_buffer_size_smaller_than_data_real_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, big_data, &actual_size); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -555,7 +583,7 @@ static void get_buffer_size_bigger_than_data_real_size() TEST_ASSERT_EQUAL_STRING_LEN(big_buffer, data, &actual_size); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -570,7 +598,7 @@ static void get_offset_bigger_than_data_size() res = kvstore->get(key, buffer, buffer_size, &actual_size, data_size + 1); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_INVALID_SIZE, res); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -596,9 +624,6 @@ static void get_removed_key() res = kvstore->get(key, buffer, buffer_size, &actual_size, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); - - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //set the same key twice and get latest data @@ -618,7 +643,7 @@ static void get_key_that_was_set_twice() TEST_ASSERT_EQUAL_STRING_LEN(buffer, new_data, &actual_size); memset(buffer, 0, buffer_size); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -652,8 +677,10 @@ static void get_several_keys_multithreaded() } } - int res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + for (int i = 0; i < num_of_threads; i++) { + int res = kvstore->remove(keys[i]); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + } } @@ -702,9 +729,6 @@ static void remove_removed_key() res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); - - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //key exist - valid flow @@ -717,9 +741,6 @@ static void remove_existed_key() res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } /*----------------setup------------------*/ @@ -755,10 +776,11 @@ template_case_t template_cases[] = { {"set_key_value_fifteen_byte_size", set_key_value_fifteen_byte_size, greentea_failure_handler}, {"set_key_value_seventeen_byte_size", set_key_value_seventeen_byte_size, greentea_failure_handler}, {"set_several_key_value_sizes", set_several_key_value_sizes, greentea_failure_handler}, + {"set_several_unvalid_key_names", set_several_unvalid_key_names, greentea_failure_handler}, + {"set_key_init_deinit", set_key_init_deinit, greentea_failure_handler}, {"Sec_set_key_rollback_set_again_no_rollback", Sec_set_key_rollback_set_again_no_rollback, greentea_failure_handler}, {"Sec_set_key_encrypt", Sec_set_key_encrypt, greentea_failure_handler}, - {"Sec_set_key_auth", Sec_set_key_auth, greentea_failure_handler}, {"get_key_null", get_key_null, greentea_failure_handler}, {"get_key_length_exceeds_max", get_key_length_exceeds_max, greentea_failure_handler}, diff --git a/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp b/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp index 6b0db131bc..ebce63a19a 100644 --- a/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp +++ b/features/storage/TESTS/kvstore/general_tests_phase_2/main.cpp @@ -204,9 +204,6 @@ static void get_info_removed_key() res = kvstore->get_info(key, &info); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); - - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //get_info of existing key - valid flow @@ -236,8 +233,7 @@ static void get_info_overwritten_key() { TEST_SKIP_UNLESS(kvstore != NULL); - char new_key[] = "get_info_key"; - int res = kvstore->set(new_key, data, data_size, 0); + int res = kvstore->set(key, data, data_size, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); char new_data[] = "new_data"; @@ -248,7 +244,7 @@ static void get_info_overwritten_key() TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); TEST_ASSERT_EQUAL_ERROR_CODE(info.size, sizeof(new_data)); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -310,15 +306,15 @@ static void iterator_next_one_key_list() res = kvstore->iterator_open(&kvstore_it, NULL); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - char key[KVStore::MAX_KEY_SIZE]; + char key_buf[KVStore::MAX_KEY_SIZE]; - res = kvstore->iterator_next(kvstore_it, key, sizeof(key)); + res = kvstore->iterator_next(kvstore_it, key_buf, sizeof(key_buf)); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); res = kvstore->iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -344,16 +340,13 @@ static void iterator_next_empty_list_keys_removed() res = kvstore->iterator_open(&kvstore_it, NULL); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - char key[KVStore::MAX_KEY_SIZE]; + char key_buf[KVStore::MAX_KEY_SIZE]; - res = kvstore->iterator_next(kvstore_it, key, sizeof(key)); + res = kvstore->iterator_next(kvstore_it, key_buf, sizeof(key_buf)); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); res = kvstore->iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //iteartor_next with non matching prefix (empty list) @@ -372,15 +365,18 @@ static void iterator_next_empty_list_non_matching_prefix() res = kvstore->iterator_open(&kvstore_it, "Key*"); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - char key[KVStore::MAX_KEY_SIZE]; + char key_buf[KVStore::MAX_KEY_SIZE]; - res = kvstore->iterator_next(kvstore_it, key, sizeof(key)); + res = kvstore->iterator_next(kvstore_it, key_buf, sizeof(key_buf)); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); res = kvstore->iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kvstore->reset(); + res = kvstore->remove(new_key_1); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + + res = kvstore->remove(new_key_2); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -408,7 +404,7 @@ static void iterator_next_several_overwritten_keys() res = kvstore->iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -449,8 +445,10 @@ static void iterator_next_full_list() res = kvstore->iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + for (i = 0; i < num_of_keys; i++) { + int res = kvstore->remove(keys[i]); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + } } //iteartor_next remove while iterating @@ -483,7 +481,6 @@ static void iterator_next_remove_while_iterating() if (res != MBED_SUCCESS) { break; } - res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -496,15 +493,14 @@ static void iterator_next_remove_while_iterating() if (res != MBED_SUCCESS) { break; } - TEST_ASSERT_EQUAL_STRING_LEN("new", key, 3); + + res = kvstore->remove(key); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } res = kvstore->iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - - res = kvstore->reset(); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } /*----------------iterator_close()------------------*/ @@ -628,7 +624,7 @@ static void set_add_data_data_size_is_zero() res = kvstore->set_finalize(handle); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -683,7 +679,7 @@ static void set_add_data_set_different_data_size_in_same_transaction() TEST_ASSERT_EQUAL_STRING(new_data, buffer); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -715,7 +711,7 @@ static void set_add_data_set_key_value_five_Kbytes() TEST_ASSERT_EQUAL_STRING_LEN(temp_buf, read_temp_buf, sizeof(temp_buf)); - res = kvstore->reset(); + res = kvstore->remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } diff --git a/features/storage/TESTS/kvstore/static_tests/main.cpp b/features/storage/TESTS/kvstore/static_tests/main.cpp index 11f39ffa29..166567604a 100644 --- a/features/storage/TESTS/kvstore/static_tests/main.cpp +++ b/features/storage/TESTS/kvstore/static_tests/main.cpp @@ -116,7 +116,7 @@ static void set_buffer_size_is_zero() int res = kv_set(key, data, 0, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -133,7 +133,7 @@ static void set_same_key_several_time() res = kv_set(key, data, data_size, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -169,24 +169,22 @@ static void set_several_keys_multithreaded() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data, data_size); + res = kv_remove(keys[i]); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } - - int res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //set key "write once" and try to set it again static void set_write_once_flag_try_set_twice() { TEST_SKIP_UNLESS(!init_res); - int res = kv_set(key, data, data_size, KV_WRITE_ONCE_FLAG); + char write_once_key[] = "write_once_key"; + + int res = kv_set(write_once_key, data, data_size, KV_WRITE_ONCE_FLAG); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_set(key, data, data_size, KV_WRITE_ONCE_FLAG); + res = kv_set(write_once_key, data, data_size, KV_WRITE_ONCE_FLAG); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_WRITE_PROTECTED, res); - - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //set key "write once" and try to remove it @@ -218,7 +216,7 @@ static void set_key_value_one_byte_size() TEST_ASSERT_EQUAL_ERROR_CODE(0, res); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -234,7 +232,7 @@ static void set_key_value_two_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_two, 1); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -250,7 +248,7 @@ static void set_key_value_five_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_five, 4); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -266,7 +264,7 @@ static void set_key_value_fifteen_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_fif, 14); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -282,36 +280,59 @@ static void set_key_value_seventeen_byte_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, data_fif, 16); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } -//set several different key value byte size +//set several different keys and retrieve them static void set_several_key_value_sizes() { TEST_SKIP_UNLESS(!init_res); char name[7] = "name_"; - char c[2] = {0}; + char c = 0; int i = 0, res = 0; - for (i = 0; i < 30; i++) { - c[0] = i + '0'; - name[6] = c[0]; + name[6] = 0; + + for (i = 0; i < 26; i++) { + c = i + 'a'; + name[5] = c; res = kv_set(name, name, sizeof(name), 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } - for (i = 0; i < 30; i++) { - c[0] = i + '0'; - name[6] = c[0]; + for (i = 0; i < 26; i++) { + c = i + 'a'; + name[5] = c; res = kv_get(name, buffer, sizeof(buffer), &actual_size); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); TEST_ASSERT_EQUAL_STRING_LEN(name, buffer, sizeof(name)); memset(buffer, 0, sizeof(buffer)); - } - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + res = kv_remove(name); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + } +} + +//try to set several different unvalid key names +static void set_several_unvalid_key_names() +{ + TEST_SKIP_UNLESS(!init_res); + char name[7] = "name_"; + char unvalid[] = {'*', '?', ':', ';', '"', '|', ' ', '<', '>', '\\', '/'}; + int i = 0, res = 0; + + name[6] = 0; + + for (i = 0; i < 11; i++) { + name[5] = unvalid[i]; + res = kv_set(name, name, sizeof(name), 0); + if (unvalid[i] != '/') { + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_INVALID_ARGUMENT, res); + } else { + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); + } + } } /*----------------get()------------------*/ @@ -352,7 +373,7 @@ static void get_buffer_size_is_zero() res = kv_get(key, buffer, 0, &actual_size); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -370,7 +391,7 @@ static void get_buffer_size_smaller_than_data_real_size() TEST_ASSERT_EQUAL_STRING_LEN(buffer, big_data, &actual_size); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -387,7 +408,7 @@ static void get_buffer_size_bigger_than_data_real_size() TEST_ASSERT_EQUAL_STRING_LEN(big_buffer, data, &actual_size); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -411,9 +432,6 @@ static void get_removed_key() res = kv_get(key, buffer, buffer_size, &actual_size); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); - - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //set the same key twice and get latest data @@ -432,7 +450,7 @@ static void get_key_that_was_set_twice() TEST_ASSERT_EQUAL_STRING_LEN(buffer, new_data, &actual_size); memset(buffer, 0, buffer_size); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -450,11 +468,12 @@ static void test_thread_get(const void *th_key) static void get_several_keys_multithreaded() { TEST_SKIP_UNLESS(!init_res); + int i = 0, res = 0; rtos::Thread kvstore_thread[num_of_threads]; osStatus threadStatus; - for (int i = 0; i < num_of_threads; i++) { - int res = kv_set(keys[i], keys[i], strlen(keys[i]) + 1, 0); + for (i = 0; i < num_of_threads; i++) { + res = kv_set(keys[i], keys[i], strlen(keys[i]) + 1, 0); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -462,15 +481,17 @@ static void get_several_keys_multithreaded() kvstore_thread[1].start(callback(test_thread_get, "key2")); kvstore_thread[2].start(callback(test_thread_get, "key3")); - for (int i = 0; i < num_of_threads; i++) { + for (i = 0; i < num_of_threads; i++) { threadStatus = kvstore_thread[i].join(); if (threadStatus != 0) { utest_printf("\nthread %d join failed!", i + 1); } } - int res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + for (i = 0; i < num_of_threads; i++) { + res = kv_remove(keys[i]); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + } } /*----------------remove()------------------*/ @@ -514,9 +535,6 @@ static void remove_removed_key() res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); - - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //key exist - valid flow @@ -528,9 +546,6 @@ static void remove_existed_key() res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } /*----------------get_info()------------------*/ @@ -582,9 +597,6 @@ static void get_info_removed_key() res = kv_get_info(key, &info); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_ERROR_ITEM_NOT_FOUND, res); - - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //get_info of existing key - valid flow @@ -617,7 +629,7 @@ static void get_info_overwritten_key() TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); TEST_ASSERT_EQUAL_ERROR_CODE(info.size, sizeof(new_data)); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -677,7 +689,7 @@ static void iterator_next_one_key_list() res = kv_iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -707,9 +719,6 @@ static void iterator_next_empty_list_keys_removed() res = kv_iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } //iteartor_next with non matching prefix (empty list) @@ -733,7 +742,10 @@ static void iterator_next_empty_list_non_matching_prefix() res = kv_iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); + res = kv_remove(new_key_1); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + + res = kv_remove(new_key_2); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -758,7 +770,7 @@ static void iterator_next_several_overwritten_keys() res = kv_iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -799,8 +811,10 @@ static void iterator_next_full_list() res = kv_iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + for (i = 0; i < num_of_threads; i++) { + res = kv_remove(keys[i]); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); + } delete[] key_found; } @@ -819,13 +833,12 @@ static void iterator_next_path_check() res = kv_iterator_next(kvstore_it, temp_key, sizeof(temp_key)); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - TEST_ASSERT_EQUAL_STRING(key, temp_key); res = kv_iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - res = kv_reset(def_kv); + res = kv_remove(key); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } @@ -874,13 +887,13 @@ static void iterator_next_remove_while_iterating() } TEST_ASSERT_EQUAL_STRING_LEN("new", key, 3); + + res = kv_remove(key); + TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } res = kv_iterator_close(kvstore_it); TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); - - res = kv_reset(def_kv); - TEST_ASSERT_EQUAL_ERROR_CODE(MBED_SUCCESS, res); } /*----------------iterator_close()------------------*/ @@ -922,6 +935,7 @@ Case cases[] = { Case("set_key_value_fifteen_byte_size", set_key_value_fifteen_byte_size, greentea_failure_handler), Case("set_key_value_seventeen_byte_size", set_key_value_seventeen_byte_size, greentea_failure_handler), Case("set_several_key_value_sizes", set_several_key_value_sizes, greentea_failure_handler), + Case("set_several_unvalid_key_names", set_several_unvalid_key_names, greentea_failure_handler), Case("get_key_null", get_key_null, greentea_failure_handler), Case("get_key_length_exceeds_max", get_key_length_exceeds_max, greentea_failure_handler), diff --git a/features/storage/kvstore/KVStore.h b/features/storage/kvstore/KVStore.h index 7c24fc763a..a3383997da 100644 --- a/features/storage/kvstore/KVStore.h +++ b/features/storage/kvstore/KVStore.h @@ -190,7 +190,8 @@ public: */ virtual int iterator_close(iterator_t it) = 0; - /** Convenience function for checking key validity + /** Convenience function for checking key validity. + * Key must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * * @param[in] key Key buffer. * diff --git a/features/storage/kvstore/conf/kv_config.cpp b/features/storage/kvstore/conf/kv_config.cpp index ea9bdddd93..bd69e4346a 100644 --- a/features/storage/kvstore/conf/kv_config.cpp +++ b/features/storage/kvstore/conf/kv_config.cpp @@ -264,7 +264,7 @@ BlockDevice *_get_blockdevice_FLASHIAP(bd_addr_t start_address, bd_size_t size) } //Get flash parameters before starting - flash_first_writable_sector_address = align_up(FLASHIAP_ROM_END, flash.get_sector_size(FLASHIAP_ROM_END)); + flash_first_writable_sector_address = align_up(FLASHIAP_APP_ROM_END_ADDR, flash.get_sector_size(FLASHIAP_APP_ROM_END_ADDR)); flash_start_address = flash.get_flash_start(); flash_end_address = flash_start_address + flash.get_flash_size();; @@ -551,7 +551,7 @@ int _storage_config_TDB_INTERNAL() if (flash.init() != 0) { return MBED_ERROR_FAILED_OPERATION; } - internal_start_address = align_up(FLASHIAP_ROM_END, flash.get_sector_size(FLASHIAP_ROM_END)); + internal_start_address = align_up(FLASHIAP_APP_ROM_END_ADDR, flash.get_sector_size(FLASHIAP_APP_ROM_END_ADDR)); flash.deinit(); } diff --git a/features/storage/kvstore/conf/kv_config.h b/features/storage/kvstore/conf/kv_config.h index 43b8677296..6a78cf3390 100644 --- a/features/storage/kvstore/conf/kv_config.h +++ b/features/storage/kvstore/conf/kv_config.h @@ -34,7 +34,7 @@ extern "C" { #define _STORAGE_CONFIG(dev) _STORAGE_CONFIG_concat(dev) /** - * @brief This function initializes one of the configuration that exists in Mbed OS. To overwite + * @brief This function initializes one of the configuration that exists in Mbed OS. To overwrite * the default configuration, please overwrite this function. * * @returns 0 on success or negative value on failure. diff --git a/features/storage/kvstore/conf/mbed_lib.json b/features/storage/kvstore/conf/mbed_lib.json index f58eb32772..dea0be27c5 100644 --- a/features/storage/kvstore/conf/mbed_lib.json +++ b/features/storage/kvstore/conf/mbed_lib.json @@ -12,7 +12,7 @@ }, "target_overrides": { "K64F": { - "storage_type": "TDB_INTERNAL" + "storage_type": "FILESYSTEM" }, "FUTURE_SEQUANA_M0_PSA": { "storage_type": "TDB_INTERNAL" diff --git a/features/storage/kvstore/filesystemstore/FileSystemStore.cpp b/features/storage/kvstore/filesystemstore/FileSystemStore.cpp index bdd77a6bc6..3e4fc2381b 100644 --- a/features/storage/kvstore/filesystemstore/FileSystemStore.cpp +++ b/features/storage/kvstore/filesystemstore/FileSystemStore.cpp @@ -39,6 +39,8 @@ static const uint32_t supported_flags = mbed::KVStore::WRITE_ONCE_FLAG; using namespace mbed; +namespace { + // incremental set handle typedef struct { char *key; @@ -53,6 +55,8 @@ typedef struct { char *prefix; } key_iterator_handle_t; +} // anonymous namespace + // Local Functions static char *string_ndup(const char *src, size_t size); diff --git a/features/storage/kvstore/filesystemstore/FileSystemStore.h b/features/storage/kvstore/filesystemstore/FileSystemStore.h index 0112044d88..2ea9590e40 100644 --- a/features/storage/kvstore/filesystemstore/FileSystemStore.h +++ b/features/storage/kvstore/filesystemstore/FileSystemStore.h @@ -23,7 +23,9 @@ namespace mbed { -/** FileSystemStore for Secure Store +/** FileSystemStore for Secure Store. + * This class implements the KVStore interface to + * create a key value store over FileSystem. * * @code * ... @@ -34,7 +36,7 @@ class FileSystemStore : public KVStore { public: /** Create FileSystemStore - A Key Value API on top of FS * - * @param fs File system on top which FileSystemStore is adding KV API + * @param fs File system (FAT/LITTLE) on top of which FileSystemStore is adding KV API */ FileSystemStore(FileSystem *fs); @@ -44,7 +46,8 @@ public: virtual ~FileSystemStore() {} /** - * @brief Initialize FileSystemStore + * @brief Initialize FileSystemStore, checking validity of + * KVStore writing folder and if it doesn't exist, creating it. * * @returns MBED_SUCCESS Success. * MBED_ERROR_FAILED_OPERATION Underlying file system failed operation. @@ -52,7 +55,7 @@ public: virtual int init(); /** - * @brief Deinitialize FileSystemStore + * @brief Deinitialize FileSystemStore, release and free resources. * * @returns MBED_SUCCESS Success. */ @@ -85,7 +88,7 @@ public: virtual int set(const char *key, const void *buffer, size_t size, uint32_t create_flags); /** - * @brief Get one FileSystemStore item, given key. + * @brief Get one FileSystemStore item by given key. * * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[in] buffer Value data buffer. @@ -98,13 +101,13 @@ public: * MBED_ERROR_FAILED_OPERATION Underlying file system failed operation. * MBED_ERROR_INVALID_ARGUMENT Invalid argument given in function arguments. * MBED_ERROR_INVALID_SIZE Invalid size given in function arguments. - * MBED_ERROR_INVALID_DATA_DETECTED Data is corrupt. + * MBED_ERROR_INVALID_DATA_DETECTED Data is corrupted. * MBED_ERROR_ITEM_NOT_FOUND No such key. */ virtual int get(const char *key, void *buffer, size_t buffer_size, size_t *actual_size = NULL, size_t offset = 0); /** - * @brief Get information of a given key. + * @brief Get information of a given key. The returned info contains size and flags * * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[out] info Returned information structure. @@ -114,13 +117,13 @@ public: * MBED_ERROR_FAILED_OPERATION Underlying file system failed operation. * MBED_ERROR_INVALID_ARGUMENT Invalid argument given in function arguments. * MBED_ERROR_INVALID_SIZE Invalid size given in function arguments. - * MBED_ERROR_INVALID_DATA_DETECTED Data is corrupt. + * MBED_ERROR_INVALID_DATA_DETECTED Data is corrupted. * MBED_ERROR_ITEM_NOT_FOUND No such key. */ virtual int get_info(const char *key, info_t *info); /** - * @brief Remove a FileSystemStore item, given key. + * @brief Remove a FileSystemStore item by given key. * * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @@ -134,7 +137,8 @@ public: virtual int remove(const char *key); /** - * @brief Start an incremental FileSystemStore set sequence. + * @brief Start an incremental FileSystemStore set sequence. This operation is blocking other operations. + * Any get/set/remove/iterator operation will be blocked until set_finalize is called. * * @param[out] handle Returned incremental set handle. * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. @@ -151,7 +155,8 @@ public: virtual int set_start(set_handle_t *handle, const char *key, size_t final_data_size, uint32_t create_flags); /** - * @brief Add data to incremental FileSystemStore set sequence. + * @brief Add data to incremental FileSystemStore set sequence. This operation is blocking other operations. + * Any get/set/remove operation will be blocked until set_finalize is called. * * @param[in] handle Incremental set handle. * @param[in] value_data Value data to add. @@ -180,6 +185,7 @@ public: /** * @brief Start an iteration over FileSystemStore keys. + * There are no issues with any other operations while iterator is open. * * @param[out] it Returned iterator handle. * @param[in] prefix Key prefix (null for all keys). @@ -192,6 +198,7 @@ public: /** * @brief Get next key in iteration. + * There are no issues with any other operations while iterator is open. * * @param[in] it Iterator handle. * @param[in] key Buffer for returned key. diff --git a/features/storage/kvstore/global_api/kvstore_global_api.h b/features/storage/kvstore/global_api/kvstore_global_api.h index 44c1971297..12cfe067f3 100644 --- a/features/storage/kvstore/global_api/kvstore_global_api.h +++ b/features/storage/kvstore/global_api/kvstore_global_api.h @@ -62,7 +62,7 @@ typedef struct info { int kv_set(const char *full_name_key, const void *buffer, size_t size, uint32_t create_flags); /** - * @brief Get one KVStore item, given key. + * @brief Get one KVStore item by given key. * * @param[in] full_name_key /Partition_path/Key. Must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[in] buffer Value data buffer. @@ -74,7 +74,7 @@ int kv_set(const char *full_name_key, const void *buffer, size_t size, uint32_t int kv_get(const char *full_name_key, void *buffer, size_t buffer_size, size_t *actual_size); /** - * @brief Get information of a given key. + * @brief Get information of a given key.The returned info contains size and flags * * @param[in] full_name_key /Partition_path/Key. Must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[out] info Returned information structure. @@ -84,7 +84,7 @@ int kv_get(const char *full_name_key, void *buffer, size_t buffer_size, size_t * int kv_get_info(const char *full_name_key, kv_info_t *info); /** - * @brief Remove a KVStore item, given key. + * @brief Remove a KVStore item by given key. * * @param[in] full_name_key /Partition_path/Key. Must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @@ -94,7 +94,8 @@ int kv_remove(const char *full_name_key); /** * @brief Start an iteration over KVStore keys to find all the entries - * that fit the full_prefix + * that fit the full_prefix. There are no issues with any other operations while + * iterator is open. * * @param[out] it Allocating iterator handle. * Do not forget to call kv_iterator_close @@ -108,7 +109,8 @@ int kv_remove(const char *full_name_key); int kv_iterator_open(kv_iterator_t *it, const char *full_prefix); /** - * @brief Get next key in iteration that matches the prefix. + * @brief Get next key in iteration that matches the prefix. There are no issues with any + * other operations while iterator is open. * * @param[in] it Iterator handle. * @param[in] key Buffer for returned key. @@ -128,7 +130,7 @@ int kv_iterator_next(kv_iterator_t it, char *key, size_t key_size); int kv_iterator_close(kv_iterator_t it); /** - * @brief Remove all keys and related data + * @brief Remove all keys and related data from a specified partition. * * @param[in] kvstore_path /Partition/ * diff --git a/features/storage/kvstore/kv_map/KVMap.h b/features/storage/kvstore/kv_map/KVMap.h index 8f128f2f01..14acbe152c 100644 --- a/features/storage/kvstore/kv_map/KVMap.h +++ b/features/storage/kvstore/kv_map/KVMap.h @@ -144,10 +144,11 @@ public: /** * @brief Full name lookup, and then break it into KVStore instance and key * - * @param full_name String parameter contains the /partition name/key. - * @param kv_instance The main KVStore instance associated with the required partition name. - * @param key_index An index to the first character of the key. - * @param flags_mask Return the flag masking for the current configuration + * @param[in] full_name String parameter contains the partition name to look for. + * The String should be formated as follow "/partition name/key". The key is optional. + * @param[out] kv_instance Returns the main KVStore instance associated with the required partition name. + * @param[out] key_index Returns an index to the first character of the key. + * @param[out] flags_mask Return the flag masking for the current configuration * @return 0 on success, negative error code on failure */ int lookup(const char *full_name, mbed::KVStore **kv_instance, size_t *key_index, uint32_t *flags_mask = NULL); @@ -211,7 +212,7 @@ public: private: /** - * @brief Deinitialize all components of a partition configuration struct. + * @brief Deinitialize all components of a partition configuration struct. * * @param partition Partition configuration struct. */ @@ -220,9 +221,9 @@ private: /** * @brief Full name lookup, and then break it into KVStore config and key * - * @param full_name String parameter contains the /partition name/key. - * @param kv_config The configuration struct associated with the partition name - * @param key_index An index to the first character of the key. + * @param[in] full_name String parameter contains the /partition name/key. + * @param[out] kv_config Returns The configuration struct associated with the partition name + * @param[out] key_index Returns an index to the first character of the key. * @return 0 on success, negative error code on failure */ int config_lookup(const char *full_name, kvstore_config_t **kv_config, size_t *key_index); diff --git a/features/storage/kvstore/securestore/SecureStore.cpp b/features/storage/kvstore/securestore/SecureStore.cpp index c4ac4b15c8..20cfeca0c9 100644 --- a/features/storage/kvstore/securestore/SecureStore.cpp +++ b/features/storage/kvstore/securestore/SecureStore.cpp @@ -48,6 +48,8 @@ static const char *const auth_prefix = "AUTH"; static const uint32_t security_flags = KVStore::REQUIRE_CONFIDENTIALITY_FLAG | KVStore::REQUIRE_REPLAY_PROTECTION_FLAG; +namespace { + typedef struct { uint16_t metadata_size; uint16_t revision; @@ -72,6 +74,8 @@ typedef struct { KVStore::iterator_t underlying_it; } key_iterator_handle_t; +} // anonymous namespace + // -------------------------------------------------- Local Functions Declaration ---------------------------------------------------- diff --git a/features/storage/kvstore/securestore/SecureStore.h b/features/storage/kvstore/securestore/SecureStore.h index 842f25f1e6..2dbda2dd2f 100644 --- a/features/storage/kvstore/securestore/SecureStore.h +++ b/features/storage/kvstore/securestore/SecureStore.h @@ -53,8 +53,8 @@ public: /** * @brief Class constructor * - * @param[in] underlying_kv Underlying KVStore. - * @param[in] rbp_kv Rollback protect KVStore. + * @param[in] underlying_kv KVStore that will hold the data. + * @param[in] rbp_kv Additional KVStore used for rollback protection. * * @returns none */ @@ -68,7 +68,8 @@ public: virtual ~SecureStore(); /** - * @brief Initialize SecureStore + * @brief Initialize SecureStore class. It will also initialize + * the underlying KVStore and the rollback protection KVStore. * * @returns MBED_SUCCESS Success. * or any other error from underlying KVStore instances. @@ -76,7 +77,7 @@ public: virtual int init(); /** - * @brief Deinitialize SecureStore + * @brief Deinitialize SecureStore class, free handles and memory allocations. * * @returns MBED_SUCCESS Success. * or any other error from underlying KVStore instances. @@ -100,7 +101,8 @@ public: * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[in] buffer Value data buffer. * @param[in] size Value data size. - * @param[in] create_flags Flag mask. + * @param[in] create_flags Flag mask - WRITE_ONCE_FLAG|REQUIRE_CONFIDENTIALITY_FLAG| + * REQUIRE_INTEGRITY_FLAG|REQUIRE_REPLAY_PROTECTION_FLAG * * @returns MBED_SUCCESS Success. * MBED_ERROR_NOT_READY Not initialized. @@ -141,7 +143,7 @@ public: * @brief Get information of a given key. * * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. - * @param[out] info Returned information structure. + * @param[out] info Returned information structure containing size and flags. * * @returns MBED_SUCCESS Success. * MBED_ERROR_NOT_READY Not initialized. @@ -173,12 +175,14 @@ public: /** - * @brief Start an incremental KVStore set sequence. + * @brief Start an incremental KVStore set sequence. This operation is blocking other operations. + * Any get/set/remove/iterator operation will be blocked until set_finalize is called. * * @param[out] handle Returned incremental set handle. * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[in] final_data_size Final value data size. - * @param[in] create_flags Flag mask. + * @param[in] create_flags Flag mask - WRITE_ONCE_FLAG|REQUIRE_CONFIDENTIALITY_FLAG| + * REQUIRE_INTEGRITY_FLAG|REQUIRE_REPLAY_PROTECTION_FLAG * * @returns MBED_SUCCESS Success. * MBED_ERROR_NOT_READY Not initialized. @@ -192,7 +196,8 @@ public: virtual int set_start(set_handle_t *handle, const char *key, size_t final_data_size, uint32_t create_flags); /** - * @brief Add data to incremental KVStore set sequence. + * @brief Add data to incremental KVStore set sequence. This operation is blocking other operations. + * Any get/set/remove operation will be blocked until set_finalize is called. * * @param[in] handle Incremental set handle. * @param[in] value_data value data to add. @@ -223,6 +228,7 @@ public: /** * @brief Start an iteration over KVStore keys. + * There are no issue with any other operation while iterator is open. * * @param[out] it Returned iterator handle. * @param[in] prefix Key prefix (null for all keys). @@ -236,6 +242,7 @@ public: /** * @brief Get next key in iteration. + * There are no issue with any other operation while iterator is open. * * @param[in] it Iterator handle. * @param[in] key Buffer for returned key. diff --git a/features/storage/kvstore/tdbstore/TDBStore.cpp b/features/storage/kvstore/tdbstore/TDBStore.cpp index 463f4f8163..9ba1fd4130 100644 --- a/features/storage/kvstore/tdbstore/TDBStore.cpp +++ b/features/storage/kvstore/tdbstore/TDBStore.cpp @@ -33,6 +33,8 @@ static const uint32_t delete_flag = (1UL << 31); static const uint32_t internal_flags = delete_flag; static const uint32_t supported_flags = KVStore::WRITE_ONCE_FLAG; +namespace { + typedef struct { uint32_t magic; uint16_t header_size; @@ -93,6 +95,8 @@ typedef struct { char *prefix; } key_iterator_handle_t; +} // anonymous namespace + // -------------------------------------------------- Local Functions Declaration ---------------------------------------------------- diff --git a/features/storage/kvstore/tdbstore/TDBStore.h b/features/storage/kvstore/tdbstore/TDBStore.h index 8a5ca7d8cc..727ad7c7eb 100644 --- a/features/storage/kvstore/tdbstore/TDBStore.h +++ b/features/storage/kvstore/tdbstore/TDBStore.h @@ -39,7 +39,10 @@ public: /** * @brief Class constructor * - * @param[in] bd Underlying block device. + * @param[in] bd Underlying block device. The BlockDevice + * can be any BlockDevice with flash characteristics. + * If using a BlockDevice without flash, such as SDBlockDevice, + * please add the FlashSimBlockDevice on top of it. * * @returns none */ @@ -53,7 +56,9 @@ public: virtual ~TDBStore(); /** - * @brief Initialize TDBStore + * @brief Initialize TDBStore. If data exists, TDBStore will check the data integrity + * on initialize. If the integrity checks fails, the TDBStore will use GC to collect + * the available data and clean corrupted and erroneous records. * * @returns MBED_SUCCESS Success. * MBED_ERROR_READ_FAILED Unable to read from media. @@ -62,7 +67,7 @@ public: virtual int init(); /** - * @brief Deinitialize TDBStore + * @brief Deinitialize TDBStore, release and free resources. * * @returns MBED_SUCCESS Success. */ @@ -99,7 +104,7 @@ public: virtual int set(const char *key, const void *buffer, size_t size, uint32_t create_flags); /** - * @brief Get one TDBStore item, given key. + * @brief Get one TDBStore item by given key. * * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[in] buffer Value data buffer. @@ -119,7 +124,7 @@ public: size_t offset = 0); /** - * @brief Get information of a given key. + * @brief Get information of a given key. The returned info contains size and flags * * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @param[out] info Returned information structure. @@ -134,7 +139,7 @@ public: virtual int get_info(const char *key, info_t *info); /** - * @brief Remove a TDBStore item, given key. + * @brief Remove a TDBStore item by given key. * * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. * @@ -151,7 +156,8 @@ public: /** - * @brief Start an incremental TDBStore set sequence. + * @brief Start an incremental TDBStore set sequence. This operation is blocking other operations. + * Any get/set/remove/iterator operation will be blocked until set_finalize is called. * * @param[out] handle Returned incremental set handle. * @param[in] key Key - must not include '*' '/' '?' ':' ';' '\' '"' '|' ' ' '<' '>' '\'. @@ -170,7 +176,8 @@ public: virtual int set_start(set_handle_t *handle, const char *key, size_t final_data_size, uint32_t create_flags); /** - * @brief Add data to incremental TDBStore set sequence. + * @brief Add data to incremental TDBStore set sequence. This operation is blocking other operations. + * Any get/set/remove operation will be blocked until set_finalize will be called. * * @param[in] handle Incremental set handle. * @param[in] value_data Value data to add. @@ -198,6 +205,7 @@ public: /** * @brief Start an iteration over KVStore keys. + * There are no issues with any other operations while iterator is open. * * @param[out] it Returned iterator handle. * @param[in] prefix Key prefix (null for all keys). @@ -210,6 +218,7 @@ public: /** * @brief Get next key in iteration. + * There are no issues with any other operations while iterator is open. * * @param[in] it Iterator handle. * @param[in] key Buffer for returned key. @@ -237,7 +246,8 @@ public: virtual int iterator_close(iterator_t it); /** - * @brief Set data in reserved area. + * @brief Set data in reserved area, which is a special location for special data, such as ROT. + * The data written to reserved area can't be overwritten. * * @param[in] reserved_data Reserved data buffer. * @param[in] reserved_data_buf_size @@ -253,7 +263,7 @@ public: virtual int reserved_data_set(const void *reserved_data, size_t reserved_data_buf_size); /** - * @brief Get data from reserved area. + * @brief Get data from reserved area, which is a special location for special data, such as ROT. * * @param[in] reserved_data Reserved data buffer. * @param[in] reserved_data_buf_size diff --git a/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp b/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp index dade9a7d2c..bd157ded43 100644 --- a/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp +++ b/features/storage/nvstore/TESTS/nvstore/functionality/main.cpp @@ -88,7 +88,7 @@ static void nvstore_basic_functionality_test() size_t area_size; nvstore.get_area_params(area, area_address, area_size); printf("Area %d: address 0x%08lx, size %d (0x%x)\n", area, area_address, area_size, area_size); - if (area_address < FLASHIAP_ROM_END) { + if (area_address < FLASHIAP_APP_ROM_END_ADDR) { nvstore_overlaps_code = true; } TEST_SKIP_UNLESS_MESSAGE(!nvstore_overlaps_code, "Test skipped. NVStore region overlaps code."); @@ -449,12 +449,13 @@ static void thread_test_worker() static void nvstore_multi_thread_test() { #ifdef MBED_CONF_RTOS_PRESENT - int i; + int i, result; uint16_t size; uint16_t key; int ret; char *dummy; - uint16_t max_possible_keys; + uint16_t max_possible_keys, actual_len_bytes = 0; + char test[] = "Test", read_buf[10] = {}; NVStore &nvstore = NVStore::get_instance(); @@ -483,6 +484,10 @@ static void nvstore_multi_thread_test() TEST_SKIP_UNLESS_MESSAGE(max_possible_keys >= max_possible_keys_threshold, "Max possible keys below threshold. Test skipped."); + nvstore.set_max_keys(max_test_keys + 1); + result = nvstore.set(max_test_keys, strlen(test), test); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + thr_test_data->stop_threads = false; for (key = 0; key < thr_test_data->max_keys; key++) { for (i = 0; i < thr_test_num_buffs; i++) { @@ -527,6 +532,12 @@ static void nvstore_multi_thread_test() for (key = 0; key < thr_test_data->max_keys; key++) { thread_test_check_key(key); } + + result = nvstore.get(max_test_keys, sizeof(read_buf), read_buf, actual_len_bytes); + TEST_ASSERT_EQUAL(NVSTORE_SUCCESS, result); + TEST_ASSERT_EQUAL(strlen(test), actual_len_bytes); + TEST_ASSERT_EQUAL_UINT8_ARRAY(test, read_buf, strlen(test)); + goto clean; mem_fail: diff --git a/features/storage/nvstore/mbed_lib.json b/features/storage/nvstore/mbed_lib.json index 13358563e3..7221fb8104 100644 --- a/features/storage/nvstore/mbed_lib.json +++ b/features/storage/nvstore/mbed_lib.json @@ -29,6 +29,9 @@ } }, "target_overrides": { + "NUCLEO_F410RB": { + "enabled" : false + }, "FUTURE_SEQUANA": { "area_1_address": "0x100F8000", "area_1_size": 16384, diff --git a/features/storage/nvstore/source/nvstore.cpp b/features/storage/nvstore/source/nvstore.cpp index f049062af1..e6df0f6cfa 100644 --- a/features/storage/nvstore/source/nvstore.cpp +++ b/features/storage/nvstore/source/nvstore.cpp @@ -30,6 +30,8 @@ // --------------------------------------------------------- Definitions ---------------------------------------------------------- +namespace { + static const uint16_t delete_item_flag = 0x8000; static const uint16_t set_once_flag = 0x4000; static const uint16_t header_flag_mask = 0xF000; @@ -61,8 +63,8 @@ static const unsigned int owner_bit_pos = 12; typedef struct { uint16_t version; - uint16_t reserved1; - uint32_t reserved2; + uint16_t max_keys; + uint32_t reserved; } master_record_data_t; static const uint32_t min_area_size = 4096; @@ -72,6 +74,17 @@ static const int num_write_retries = 16; static const uint8_t blank_flash_val = 0xFF; +typedef enum { + NVSTORE_AREA_STATE_NONE = 0, + NVSTORE_AREA_STATE_EMPTY, + NVSTORE_AREA_STATE_VALID, +} area_state_e; + +static const uint32_t initial_crc = 0xFFFFFFFF; + +} // anonymous namespace + + // See whether any of these defines are given (by config files) // If so, this means that that area configuration is given by the user #if defined(NVSTORE_AREA_1_ADDRESS) || defined(NVSTORE_AREA_1_SIZE) ||\ @@ -95,15 +108,6 @@ NVStore::nvstore_area_data_t NVStore::initial_area_params[] = {{0, 0}, }; #endif -typedef enum { - NVSTORE_AREA_STATE_NONE = 0, - NVSTORE_AREA_STATE_EMPTY, - NVSTORE_AREA_STATE_VALID, -} area_state_e; - -static const uint32_t initial_crc = 0xFFFFFFFF; - - // -------------------------------------------------- Local Functions Declaration ---------------------------------------------------- // -------------------------------------------------- Functions Implementation ---------------------------------------------------- @@ -171,11 +175,54 @@ uint16_t NVStore::get_max_possible_keys() void NVStore::set_max_keys(uint16_t num_keys) { + uint16_t key = 0, old_max_keys = 0; + MBED_ASSERT(num_keys < get_max_possible_keys()); + + if (num_keys < NVSTORE_NUM_PREDEFINED_KEYS) { + return; + } + + if (!_init_done) { + int ret = init(); + if (ret != NVSTORE_SUCCESS) { + return; + } + } + + _mutex->lock(); + + //check if there are values that might be discarded + if (num_keys < _max_keys) { + for (key = num_keys; key < _max_keys; key++) { + if (_offset_by_key[key] != 0) { + return; + } + } + } + + old_max_keys = _max_keys; _max_keys = num_keys; - // User is allowed to change number of keys. As this affects init, need to deinitialize now. - // Don't call init right away - it is lazily called by get/set functions if needed. - deinit(); + + // Invoke GC to write new max_keys to master record + garbage_collection(no_key, 0, 0, 0, NULL, std::min(_max_keys, old_max_keys)); + + // Reallocate _offset_by_key with new size + if (_max_keys != old_max_keys) { + // Reallocate _offset_by_key with new size + uint32_t *old_offset_by_key = (uint32_t *) _offset_by_key; + uint32_t *new_offset_by_key = new uint32_t[_max_keys]; + MBED_ASSERT(new_offset_by_key); + + // Copy old content to new table + memset(new_offset_by_key, 0, sizeof(uint32_t) * _max_keys); + memcpy(new_offset_by_key, old_offset_by_key, sizeof(uint32_t) * std::min(_max_keys, old_max_keys)); + + _offset_by_key = new_offset_by_key; + delete[] old_offset_by_key; + } + + _mutex->unlock(); } int NVStore::flash_read_area(uint8_t area, uint32_t offset, uint32_t size, void *buf) @@ -444,8 +491,8 @@ int NVStore::write_master_record(uint8_t area, uint16_t version, uint32_t &next_ master_record_data_t master_rec; master_rec.version = version; - master_rec.reserved1 = 0; - master_rec.reserved2 = 0; + master_rec.max_keys = _max_keys; + master_rec.reserved = 0; return write_record(area, 0, master_record_key, 0, 0, sizeof(master_rec), &master_rec, next_offset); } @@ -518,7 +565,7 @@ int NVStore::copy_record(uint8_t from_area, uint32_t from_offset, uint32_t to_of return NVSTORE_SUCCESS; } -int NVStore::garbage_collection(uint16_t key, uint16_t flags, uint8_t owner, uint16_t buf_size, const void *buf) +int NVStore::garbage_collection(uint16_t key, uint16_t flags, uint8_t owner, uint16_t buf_size, const void *buf, uint16_t num_keys) { uint32_t curr_offset, new_area_offset, next_offset, curr_owner; int ret; @@ -542,7 +589,7 @@ int NVStore::garbage_collection(uint16_t key, uint16_t flags, uint8_t owner, uin // Now iterate on all types, and copy the ones who have valid offsets (meaning that they exist) // to the other area. - for (key = 0; key < _max_keys; key++) { + for (key = 0; key < num_keys; key++) { curr_offset = _offset_by_key[key]; uint16_t save_flags = curr_offset & offs_by_key_flag_mask & ~offs_by_key_area_mask; curr_area = (uint8_t)(curr_offset >> offs_by_key_area_bit_pos) & 1; @@ -579,7 +626,6 @@ int NVStore::garbage_collection(uint16_t key, uint16_t flags, uint8_t owner, uin return ret; } - int NVStore::do_get(uint16_t key, uint16_t buf_size, void *buf, uint16_t &actual_size, int validate_only) { @@ -684,7 +730,7 @@ int NVStore::do_set(uint16_t key, uint16_t buf_size, const void *buf, uint16_t f // If we cross the area limit, we need to invoke GC. if (new_free_space >= _size) { - ret = garbage_collection(key, flags, owner, buf_size, buf); + ret = garbage_collection(key, flags, owner, buf_size, buf, _max_keys); _mutex->unlock(); return ret; } @@ -800,6 +846,7 @@ int NVStore::init() uint16_t key; uint16_t flags; uint16_t versions[NVSTORE_NUM_AREAS]; + uint16_t keys[NVSTORE_NUM_AREAS]; uint16_t actual_size; uint8_t owner; @@ -818,13 +865,6 @@ int NVStore::init() return NVSTORE_SUCCESS; } - _offset_by_key = new uint32_t[_max_keys]; - MBED_ASSERT(_offset_by_key); - - for (key = 0; key < _max_keys; key++) { - _offset_by_key[key] = 0; - } - _mutex = new PlatformMutex; MBED_ASSERT(_mutex); @@ -841,10 +881,12 @@ int NVStore::init() calc_validate_area_params(); + //retrieve max keys from master record for (uint8_t area = 0; area < NVSTORE_NUM_AREAS; area++) { area_state[area] = NVSTORE_AREA_STATE_NONE; free_space_offset_of_area[area] = 0; versions[area] = 0; + keys[area] = 0; _size = std::min(_size, _flash_area_params[area].size); @@ -878,6 +920,7 @@ int NVStore::init() continue; } versions[area] = master_rec.version; + keys[area] = master_rec.max_keys; // Place _free_space_offset after the master record (for the traversal, // which takes place after this loop). @@ -888,6 +931,17 @@ int NVStore::init() // that we found our active area. _active_area = area; _active_area_version = versions[area]; + if (!keys[area]) { + keys[area] = NVSTORE_NUM_PREDEFINED_KEYS; + } + _max_keys = keys[area]; + } + + _offset_by_key = new uint32_t[_max_keys]; + MBED_ASSERT(_offset_by_key); + + for (key = 0; key < _max_keys; key++) { + _offset_by_key[key] = 0; } // In case we have two empty areas, arbitrarily assign 0 to the active one. @@ -920,9 +974,9 @@ int NVStore::init() MBED_ASSERT(ret == NVSTORE_SUCCESS); // In case we have a faulty record, this probably means that the system crashed when written. - // Perform a garbage collection, to make the the other area valid. + // Perform a garbage collection, to make the other area valid. if (!valid) { - ret = garbage_collection(no_key, 0, 0, 0, NULL); + ret = garbage_collection(no_key, 0, 0, 0, NULL, _max_keys); break; } if (flags & delete_item_flag) { diff --git a/features/storage/nvstore/source/nvstore.h b/features/storage/nvstore/source/nvstore.h index 53f3f7dcdf..2890437a9e 100644 --- a/features/storage/nvstore/source/nvstore.h +++ b/features/storage/nvstore/source/nvstore.h @@ -18,7 +18,7 @@ #define MBED_NVSTORE_H // These addresses need to be configured according to board (in mbed_lib.json) -#ifndef DEVICE_FLASH +#if !DEVICE_FLASH #undef NVSTORE_ENABLED #define NVSTORE_ENABLED 0 #endif @@ -272,7 +272,6 @@ public: */ int get_area_params(uint8_t area, uint32_t &address, size_t &size); - private: typedef struct { uint32_t address; @@ -417,10 +416,11 @@ private: * @param[in] owner Owner. * @param[in] buf_size Data size (bytes). * @param[in] buf Data buffer. + * @param[in] num_keys number of keys. * * @returns 0 for success, nonzero for failure. */ - int garbage_collection(uint16_t key, uint16_t flags, uint8_t owner, uint16_t buf_size, const void *buf); + int garbage_collection(uint16_t key, uint16_t flags, uint8_t owner, uint16_t buf_size, const void *buf, uint16_t num_keys); /** * @brief Actual logics of get API (covers also get size API). diff --git a/features/storage/system_storage/SystemStorage.cpp b/features/storage/system_storage/SystemStorage.cpp index 0277700264..0fff9c6c27 100644 --- a/features/storage/system_storage/SystemStorage.cpp +++ b/features/storage/system_storage/SystemStorage.cpp @@ -116,7 +116,7 @@ MBED_WEAK BlockDevice *BlockDevice::get_default_instance() } //Find the start of first sector after text area - bottom_address = align_up(FLASHIAP_ROM_END, flash.get_sector_size(FLASHIAP_ROM_END)); + bottom_address = align_up(FLASHIAP_APP_ROM_END_ADDR, flash.get_sector_size(FLASHIAP_APP_ROM_END_ADDR)); start_address = flash.get_flash_start(); flash_size = flash.get_flash_size(); diff --git a/features/unsupported/tests/utest/general/general.cpp b/features/unsupported/tests/utest/general/general.cpp index b5b665290e..95ad463fd4 100644 --- a/features/unsupported/tests/utest/general/general.cpp +++ b/features/unsupported/tests/utest/general/general.cpp @@ -64,7 +64,7 @@ TEST(C_String_Format, Sprintf_Negative_Integers) STRCMP_EQUAL(buffer, "-32768 -3214 -999 -100 -1 0 -1 -4231 -999 -4123 -32760 -99999"); } -#ifdef DEVICE_SEMIHOST +#if DEVICE_SEMIHOST #include "mbed_semihost_api.h" TEST_GROUP(Device_Semihost) diff --git a/hal/LowPowerTickerWrapper.cpp b/hal/LowPowerTickerWrapper.cpp index 179895f7ff..a61a7a67fd 100644 --- a/hal/LowPowerTickerWrapper.cpp +++ b/hal/LowPowerTickerWrapper.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -32,7 +33,12 @@ void LowPowerTickerWrapper::irq_handler(ticker_irq_handler_type handler) { core_util_critical_section_enter(); - if (_pending_fire_now || _match_check(_intf->read()) || _suspended) { + // This code no longer filters out early interrupts. Instead it + // passes them through to the next layer and ignores further interrupts + // until the next call to set_interrrupt or fire_interrupt (when not suspended). + // This is to ensure that the device doesn't get stuck in sleep due to an + // early low power ticker interrupt that was ignored. + if (_pending_fire_now || _pending_match || _suspended) { _timeout.detach(); _pending_timeout = false; _pending_match = false; diff --git a/hal/LowPowerTickerWrapper.h b/hal/LowPowerTickerWrapper.h index 8a6a05aca0..5ce81c59e3 100644 --- a/hal/LowPowerTickerWrapper.h +++ b/hal/LowPowerTickerWrapper.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c b/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c index b91191d9eb..6eff41aa72 100644 --- a/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c +++ b/hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h b/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h index fe6732a673..91c87b1ab1 100644 --- a/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h +++ b/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/analogin_api.h b/hal/analogin_api.h index 674e1af24e..4152440293 100644 --- a/hal/analogin_api.h +++ b/hal/analogin_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/analogout_api.h b/hal/analogout_api.h index 6875b77617..7c25369a12 100644 --- a/hal/analogout_api.h +++ b/hal/analogout_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/buffer.h b/hal/buffer.h index bf01cd6009..a68b940801 100644 --- a/hal/buffer.h +++ b/hal/buffer.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2014-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/can_api.h b/hal/can_api.h index 7fb6390511..777dc6b443 100644 --- a/hal/can_api.h +++ b/hal/can_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/can_helper.h b/hal/can_helper.h index bf04f4c47a..5a117509fd 100644 --- a/hal/can_helper.h +++ b/hal/can_helper.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/crc_api.h b/hal/crc_api.h index 29336feb9b..c2b20cc8c7 100644 --- a/hal/crc_api.h +++ b/hal/crc_api.h @@ -2,6 +2,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -51,7 +52,7 @@ typedef struct crc_mbed_config { bool reflect_out; } crc_mbed_config_t; -#ifdef DEVICE_CRC +#if DEVICE_CRC #ifdef __cplusplus extern "C" { diff --git a/hal/critical_section_api.h b/hal/critical_section_api.h index d5cb24296f..8c6ac5971f 100644 --- a/hal/critical_section_api.h +++ b/hal/critical_section_api.h @@ -2,6 +2,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/dma_api.h b/hal/dma_api.h index 1c9755d975..864439e3f0 100644 --- a/hal/dma_api.h +++ b/hal/dma_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2014-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/ethernet_api.h b/hal/ethernet_api.h index 1802db955e..1a14fda06e 100644 --- a/hal/ethernet_api.h +++ b/hal/ethernet_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/flash_api.h b/hal/flash_api.h index 4b59193e45..e98c806a0a 100644 --- a/hal/flash_api.h +++ b/hal/flash_api.h @@ -3,6 +3,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/gpio_api.h b/hal/gpio_api.h index 9f11937be4..51156acd23 100644 --- a/hal/gpio_api.h +++ b/hal/gpio_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/gpio_irq_api.h b/hal/gpio_irq_api.h index eb631716df..6ca858f600 100644 --- a/hal/gpio_irq_api.h +++ b/hal/gpio_irq_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/i2c_api.h b/hal/i2c_api.h index 18f902369e..43ed7bcebd 100644 --- a/hal/i2c_api.h +++ b/hal/i2c_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/itm_api.h b/hal/itm_api.h index 38607789ce..897f6fa792 100644 --- a/hal/itm_api.h +++ b/hal/itm_api.h @@ -2,6 +2,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,7 +20,7 @@ #ifndef MBED_ITM_API_H #define MBED_ITM_API_H -#if defined(DEVICE_ITM) +#if DEVICE_ITM #include #include diff --git a/hal/lp_ticker_api.h b/hal/lp_ticker_api.h index 374990803c..aecaf8ac4a 100644 --- a/hal/lp_ticker_api.h +++ b/hal/lp_ticker_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_critical_section_api.c b/hal/mbed_critical_section_api.c index 21e3338b64..05b42b6f8f 100644 --- a/hal/mbed_critical_section_api.c +++ b/hal/mbed_critical_section_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_flash_api.c b/hal/mbed_flash_api.c index 83fa7f1805..a5d009bc87 100644 --- a/hal/mbed_flash_api.c +++ b/hal/mbed_flash_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_gpio.c b/hal/mbed_gpio.c index 7bf52dd76d..b58a6ca61a 100644 --- a/hal/mbed_gpio.c +++ b/hal/mbed_gpio.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_itm_api.c b/hal/mbed_itm_api.c index 17afe5e156..46d7e3dcc0 100644 --- a/hal/mbed_itm_api.c +++ b/hal/mbed_itm_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,7 +15,7 @@ * limitations under the License. */ -#if defined(DEVICE_ITM) +#if DEVICE_ITM #include "hal/itm_api.h" #include "cmsis.h" @@ -130,4 +131,4 @@ void mbed_itm_send_block(uint32_t port, const void *data, size_t len) } } } -#endif // defined(DEVICE_ITM) +#endif // DEVICE_ITM diff --git a/hal/mbed_lp_ticker_api.c b/hal/mbed_lp_ticker_api.c index 477c1b1387..7a29964fd2 100644 --- a/hal/mbed_lp_ticker_api.c +++ b/hal/mbed_lp_ticker_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_lp_ticker_wrapper.cpp b/hal/mbed_lp_ticker_wrapper.cpp index 403141fcea..09c1a9bf3c 100644 --- a/hal/mbed_lp_ticker_wrapper.cpp +++ b/hal/mbed_lp_ticker_wrapper.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_lp_ticker_wrapper.h b/hal/mbed_lp_ticker_wrapper.h index e1c1fe4a26..3493abe496 100644 --- a/hal/mbed_lp_ticker_wrapper.h +++ b/hal/mbed_lp_ticker_wrapper.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_pinmap_common.c b/hal/mbed_pinmap_common.c index 1805607502..0f2083d92e 100644 --- a/hal/mbed_pinmap_common.c +++ b/hal/mbed_pinmap_common.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_sleep_manager.c b/hal/mbed_sleep_manager.c index 03f678e826..c512e44ef7 100644 --- a/hal/mbed_sleep_manager.c +++ b/hal/mbed_sleep_manager.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -35,13 +36,13 @@ static uint16_t deep_sleep_lock = 0U; static us_timestamp_t sleep_time = 0; static us_timestamp_t deep_sleep_time = 0; -#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER) +#if defined(MBED_CPU_STATS_ENABLED) && DEVICE_LPTICKER static ticker_data_t *sleep_ticker = NULL; #endif static inline us_timestamp_t read_us(void) { -#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER) +#if defined(MBED_CPU_STATS_ENABLED) && DEVICE_LPTICKER if (NULL == sleep_ticker) { sleep_ticker = (ticker_data_t *)get_lp_ticker_data(); } diff --git a/hal/mbed_ticker_api.c b/hal/mbed_ticker_api.c index 5c9fc55bce..36ea2938fd 100644 --- a/hal/mbed_ticker_api.c +++ b/hal/mbed_ticker_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mbed_us_ticker_api.c b/hal/mbed_us_ticker_api.c index 433a035540..28626e0bd6 100644 --- a/hal/mbed_us_ticker_api.c +++ b/hal/mbed_us_ticker_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/mpu/mbed_mpu_v7m.c b/hal/mpu/mbed_mpu_v7m.c index 5778e74739..7b7a7c7259 100644 --- a/hal/mpu/mbed_mpu_v7m.c +++ b/hal/mpu/mbed_mpu_v7m.c @@ -15,7 +15,6 @@ */ #include "hal/mpu_api.h" #include "platform/mbed_assert.h" -#include "platform/mbed_error.h" #include "cmsis.h" #if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_6M__ == 1U)) && \ @@ -26,7 +25,9 @@ #error "Device has v7m MPU but it is not enabled. Add 'MPU' to device_has in targets.json" #endif -#if !defined(MBED_MPU_ROM_END) +#ifdef MBED_CONF_TARGET_MPU_ROM_END +#define MBED_MPU_ROM_END MBED_CONF_TARGET_MPU_ROM_END +#else #define MBED_MPU_ROM_END (0x10000000 - 1) #endif #define MBED_MPU_RAM_START (MBED_MPU_ROM_END + 1) @@ -45,12 +46,17 @@ MBED_STATIC_ASSERT( void mbed_mpu_init() { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); const uint32_t regions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; - if (regions < 4) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_EINVAL), "Device is not capable of supporting an MPU - remove DEVICE_MPU for device_has."); - } + + // Our MPU setup requires 3 or 4 regions - if this assert is hit, remove + // a region by setting MPU_ROM_END to 0x1fffffff, or remove MPU from device_has +#if MBED_MPU_RAM_START == 0x20000000 + MBED_ASSERT(regions >= 3); +#else + MBED_ASSERT(regions >= 4); +#endif // Disable the MCU MPU->CTRL = 0; @@ -74,13 +80,12 @@ void mbed_mpu_init() * 0xE0000000 - 0xFFFFFFFF System No */ - // Select region 1 and used it for the WT rom region - // - RAM 0x00000000 to MBED_MPU_ROM_END - MPU->RNR = 0; - // Set address to 0 - MPU->RBAR = 0; - // Configure and enable region - MPU->RASR = + // Select region 0 and use it for the WT read-only rom region + // - Code 0x00000000 to MBED_MPU_ROM_END + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + 0, // Region + 0x00000000), // Base ARM_MPU_RASR( 0, // DisableExec ARM_MPU_AP_RO, // AccessPermission @@ -97,16 +102,16 @@ void mbed_mpu_init() ((MBED_MPU_ROM_END >= 0x14000000) ? 0 : (1 << 5)) | ((MBED_MPU_ROM_END >= 0x18000000) ? 0 : (1 << 6)) | ((MBED_MPU_ROM_END >= 0x1C000000) ? 0 : (1 << 7)), - ARM_MPU_REGION_SIZE_512MB // Size - ); + ARM_MPU_REGION_SIZE_512MB) // Size + ); - // Select region 1 and used it for the WT rom region - // - RAM MBED_MPU_ROM_END + 1 to 0x1FFFFFFF - MPU->RNR = 1; - // Set address to 0 - MPU->RBAR = 0; - // Configure and enable region - MPU->RASR = +#if MBED_MPU_RAM_START < 0x20000000 + // Select region 3 and use it for a WT ram region in the Code area + // - Code MBED_MPU_ROM_END + 1 to 0x1FFFFFFF + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + 3, // Region + 0x00000000), // Base ARM_MPU_RASR( 1, // DisableExec ARM_MPU_AP_FULL, // AccessPermission @@ -123,17 +128,20 @@ void mbed_mpu_init() ((MBED_MPU_RAM_START <= 0x18000000) ? 0 : (1 << 5)) | ((MBED_MPU_RAM_START <= 0x1C000000) ? 0 : (1 << 6)) | ((MBED_MPU_RAM_START <= 0x20000000) ? 0 : (1 << 7)), - ARM_MPU_REGION_SIZE_512MB // Size - ); + ARM_MPU_REGION_SIZE_512MB) // Size + ); +#define LAST_RAM_REGION 3 +#else +#define LAST_RAM_REGION 2 +#endif - // Select region 2 and used it for WBWA ram regions + // Select region 1 and use it for WBWA ram regions // - SRAM 0x20000000 to 0x3FFFFFFF // - RAM 0x60000000 to 0x7FFFFFFF - MPU->RNR = 2; - // Set address to 0 - MPU->RBAR = 0; - // Configure and enable region - MPU->RASR = + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + 1, // Region + 0x00000000), // Base ARM_MPU_RASR( 1, // DisableExec ARM_MPU_AP_FULL, // AccessPermission @@ -150,16 +158,15 @@ void mbed_mpu_init() (1 << 5) | // Disable Sub-region (1 << 6) | // Disable Sub-region (1 << 7), // Disable Sub-region - ARM_MPU_REGION_SIZE_4GB // Size - ); + ARM_MPU_REGION_SIZE_4GB) // Size + ); - // Select region 3 and used it for the WT ram region - // - RAM RAM 0x80000000 to 0x9FFFFFFF - MPU->RNR = 3; - // Set address - MPU->RBAR = 0x80000000; - // Configure and enable region - MPU->RASR = + // Select region 2 and use it for the WT ram region + // - RAM 0x80000000 to 0x9FFFFFFF + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + 2, // Region + 0x80000000), // Base ARM_MPU_RASR( 1, // DisableExec ARM_MPU_AP_FULL, // AccessPermission @@ -167,9 +174,9 @@ void mbed_mpu_init() 0, // IsShareable 1, // IsCacheable 0, // IsBufferable - ~0U, // SubRegionDisable - ARM_MPU_REGION_SIZE_512MB // Size - ); + 0U, // SubRegionDisable + ARM_MPU_REGION_SIZE_512MB) // Size + ); // Enable the MPU MPU->CTRL = @@ -178,53 +185,53 @@ void mbed_mpu_init() (1 << MPU_CTRL_ENABLE_Pos); // Enable MPU // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); } void mbed_mpu_free() { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); // Disable the MPU MPU->CTRL = 0; // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); +} + +static void enable_region(bool enable, uint32_t region) +{ + MPU->RNR = region; + MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable << MPU_RASR_ENABLE_Pos); } void mbed_mpu_enable_rom_wn(bool enable) { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); - MPU->RNR = 0; - MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable ? MPU_RASR_ENABLE_Msk : 0); + enable_region(enable, 0); // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); } void mbed_mpu_enable_ram_xn(bool enable) { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); - MPU->RNR = 1; - MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable ? MPU_RASR_ENABLE_Msk : 0); - - MPU->RNR = 2; - MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable ? MPU_RASR_ENABLE_Msk : 0); - - MPU->RNR = 3; - MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable ? MPU_RASR_ENABLE_Msk : 0); + for (uint32_t region = 1; region <= LAST_RAM_REGION; region++) { + enable_region(enable, region); + } // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); } #endif diff --git a/hal/mpu/mbed_mpu_v8m.c b/hal/mpu/mbed_mpu_v8m.c index 7304c149b9..4b992f543d 100644 --- a/hal/mpu/mbed_mpu_v8m.c +++ b/hal/mpu/mbed_mpu_v8m.c @@ -15,7 +15,6 @@ */ #include "hal/mpu_api.h" #include "platform/mbed_assert.h" -#include "platform/mbed_error.h" #include "cmsis.h" #if ((__ARM_ARCH_8M_BASE__ == 1U) || (__ARM_ARCH_8M_MAIN__ == 1U)) && \ @@ -26,35 +25,44 @@ #error "Device has v8m MPU but it is not enabled. Add 'MPU' to device_has in targets.json" #endif -#if !defined(MBED_MPU_ROM_END) -#define MBED_MPU_ROM_END (0x20000000 - 1) +#ifdef MBED_CONF_TARGET_MPU_ROM_END +#define MBED_MPU_ROM_END MBED_CONF_TARGET_MPU_ROM_END +#else +#define MBED_MPU_ROM_END (0x10000000 - 1) #endif +#define MBED_MPU_RAM_START (MBED_MPU_ROM_END + 1) -MBED_STATIC_ASSERT(MBED_MPU_ROM_END == 0x1fffffff, "Changing MBED_MPU_ROM_END for ARMv8-M is not supported."); +MBED_STATIC_ASSERT(MBED_MPU_ROM_END <= 0x20000000 - 1, + "Unsupported value for MBED_MPU_ROM_END"); void mbed_mpu_init() { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); const uint32_t regions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; - if (regions < 4) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_EINVAL), "Device is not capable of supporting an MPU - remove DEVICE_MPU for device_has."); - } + + // Our MPU setup requires 4 or 5 regions - if this assert is hit, remove + // a region by setting MPU_ROM_END to 0x1fffffff, or remove MPU from device_has +#if MBED_MPU_RAM_START == 0x20000000 + MBED_ASSERT(regions >= 4); +#else + MBED_ASSERT(regions >= 5); +#endif // Disable the MCU MPU->CTRL = 0; // Reset all mapping for (uint32_t i = 0; i < regions; i++) { - ARM_MPU_ClrRegionEx(MPU, i); + ARM_MPU_ClrRegion(i); } /* * ARMv8-M memory map: * * Start End Name Executable by default Default cache Mbed MPU protection - * 0x00000000 - 0x1FFFFFFF Code Yes WT, WA Write disabled + * 0x00000000 - 0x1FFFFFFF Code Yes WT, WA Write disabled for first portion and execute disabled for the rest * 0x20000000 - 0x3FFFFFFF SRAM Yes WB, WA, RA Execute disabled * 0x40000000 - 0x5FFFFFFF Peripheral No * 0x60000000 - 0x7FFFFFFF RAM Yes WB, WA, RA Execute disabled @@ -64,61 +72,85 @@ void mbed_mpu_init() * 0xE0000000 - 0xFFFFFFFF System No */ - uint32_t region; - uint8_t outer; - uint8_t inner; + const uint8_t WTRA = ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0); // Non-transient, Write-Through, Read-allocate, Not Write-allocate + const uint8_t WBWARA = ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1); // Non-transient, Write-Back, Read-allocate, Write-allocate + enum { + AttrIndex_WTRA, + AttrIndex_WBWARA, + }; - region = 0; - MPU->RNR = region; - outer = 0xA; // Write-Through, Non-transient, Read-allocate - inner = 0xA; // Write-Through, Non-transient, Read-allocate - ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0)); - MPU->RBAR = (0x00000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x00000000 - (0 << MPU_RBAR_SH_Pos) | // Not shareable - (3 << MPU_RBAR_AP_Pos) | // RO allowed by all privilege levels - (0 << MPU_RBAR_XN_Pos); // Execute Never disabled - MPU->RLAR = (0x1FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x1FFFFFFF - (region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number - (1 << MPU_RLAR_EN_Pos); // Region enabled + ARM_MPU_SetMemAttr(AttrIndex_WTRA, ARM_MPU_ATTR(WTRA, WTRA)); + ARM_MPU_SetMemAttr(AttrIndex_WBWARA, ARM_MPU_ATTR(WBWARA, WBWARA)); - region = 1; - MPU->RNR = region; - outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate - outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate - ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0)); - MPU->RBAR = (0x20000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x20000000 - (0 << MPU_RBAR_SH_Pos) | // Not shareable - (1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels - (1 << MPU_RBAR_XN_Pos); // Execute Never enabled - MPU->RLAR = (0x3FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x3FFFFFFF - (region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number - (1 << MPU_RLAR_EN_Pos); // Region enabled + ARM_MPU_SetRegion( + 0, // Region + ARM_MPU_RBAR( + 0x00000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 1, // Read-Only + 1, // Non-Privileged + 0), // Execute Never disabled + ARM_MPU_RLAR( + MBED_MPU_ROM_END, // Limit + AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate + ); - region = 2; - MPU->RNR = region; - outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate - outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate - ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0)); - MPU->RBAR = (0x60000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x60000000 - (0 << MPU_RBAR_SH_Pos) | // Not shareable - (1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels - (1 << MPU_RBAR_XN_Pos); // Execute Never enabled - MPU->RLAR = (0x7FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x7FFFFFFF - (region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number - (1 << MPU_RLAR_EN_Pos); // Region enabled +#if MBED_MPU_RAM_START != 0x20000000 + ARM_MPU_SetRegion( + 4, // Region + ARM_MPU_RBAR( + MBED_MPU_RAM_START, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // Execute Never enabled + ARM_MPU_RLAR( + 0x1FFFFFFF, // Limit + AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate + ); +#define LAST_RAM_REGION 4 +#else +#define LAST_RAM_REGION 3 +#endif - region = 3; - MPU->RNR = region; - outer = 0xA; // Write-Through, Non-transient, Read-allocate - inner = 0xA; // Write-Through, Non-transient, Read-allocate - ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0)); - MPU->RBAR = (0x80000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x80000000 - (0 << MPU_RBAR_SH_Pos) | // Not shareable - (1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels - (1 << MPU_RBAR_XN_Pos); // Execute Never enabled - MPU->RLAR = (0x9FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x9FFFFFFF - (region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number - (1 << MPU_RLAR_EN_Pos); // Region enabled + ARM_MPU_SetRegion( + 1, // Region + ARM_MPU_RBAR( + 0x20000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // Execute Never enabled + ARM_MPU_RLAR( + 0x3FFFFFFF, // Limit + AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate + ); + + ARM_MPU_SetRegion( + 2, // Region + ARM_MPU_RBAR( + 0x60000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // Execute Never enabled + ARM_MPU_RLAR( + 0x7FFFFFFF, // Limit + AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate + ); + + ARM_MPU_SetRegion( + 3, // Region + ARM_MPU_RBAR( + 0x80000000, // Base + ARM_MPU_SH_NON, // Non-shareable + 0, // Read-Write + 1, // Non-Privileged + 1), // Execute Never enabled + ARM_MPU_RLAR( + 0x9FFFFFFF, // Limit + AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate + ); // Enable the MPU MPU->CTRL = @@ -127,53 +159,53 @@ void mbed_mpu_init() (1 << MPU_CTRL_ENABLE_Pos); // Enable MPU // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); } void mbed_mpu_free() { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); // Disable the MCU MPU->CTRL = 0; // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); +} + +static void enable_region(bool enable, uint32_t region) +{ + MPU->RNR = region; + MPU->RLAR = (MPU->RLAR & ~MPU_RLAR_EN_Msk) | (enable << MPU_RLAR_EN_Pos); } void mbed_mpu_enable_rom_wn(bool enable) { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); - MPU->RNR = 0; - MPU->RLAR = (MPU->RLAR & ~MPU_RLAR_EN_Msk) | (enable ? MPU_RLAR_EN_Msk : 0); + enable_region(enable, 0); // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); } void mbed_mpu_enable_ram_xn(bool enable) { // Flush memory writes before configuring the MPU. - __DSB(); + __DMB(); - MPU->RNR = 1; - MPU->RLAR = (MPU->RLAR & ~MPU_RLAR_EN_Msk) | (enable ? MPU_RLAR_EN_Msk : 0); - - MPU->RNR = 2; - MPU->RLAR = (MPU->RLAR & ~MPU_RLAR_EN_Msk) | (enable ? MPU_RLAR_EN_Msk : 0); - - MPU->RNR = 3; - MPU->RLAR = (MPU->RLAR & ~MPU_RLAR_EN_Msk) | (enable ? MPU_RLAR_EN_Msk : 0); + for (uint32_t region = 1; region <= LAST_RAM_REGION; region++) { + enable_region(enable, region); + } // Ensure changes take effect - __ISB(); __DSB(); + __ISB(); } #endif diff --git a/hal/pinmap.h b/hal/pinmap.h index 4b3db4afa4..d94892a7c6 100644 --- a/hal/pinmap.h +++ b/hal/pinmap.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/port_api.h b/hal/port_api.h index 6e718c54a0..48bd0d27f1 100644 --- a/hal/port_api.h +++ b/hal/port_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/pwmout_api.h b/hal/pwmout_api.h index 00588c0092..5ede26df1c 100644 --- a/hal/pwmout_api.h +++ b/hal/pwmout_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/qspi_api.h b/hal/qspi_api.h index 24ba473545..561e0afb5c 100644 --- a/hal/qspi_api.h +++ b/hal/qspi_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/rtc_api.h b/hal/rtc_api.h index b049087968..5685f88158 100644 --- a/hal/rtc_api.h +++ b/hal/rtc_api.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/serial_api.h b/hal/serial_api.h index 30f100f8c7..1da952a6c7 100644 --- a/hal/serial_api.h +++ b/hal/serial_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/sleep_api.h b/hal/sleep_api.h index bc484d6f1b..1dd2d0dfcd 100644 --- a/hal/sleep_api.h +++ b/hal/sleep_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/spi_api.h b/hal/spi_api.h index 90117c822b..423f113c78 100644 --- a/hal/spi_api.h +++ b/hal/spi_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/ticker_api.h b/hal/ticker_api.h index 98b2786ee3..f7615e4aae 100644 --- a/hal/ticker_api.h +++ b/hal/ticker_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/trng_api.h b/hal/trng_api.h index 946c25331c..7677094103 100644 --- a/hal/trng_api.h +++ b/hal/trng_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/hal/us_ticker_api.h b/hal/us_ticker_api.h index e27c8051f4..ca43e74dc7 100644 --- a/hal/us_ticker_api.h +++ b/hal/us_ticker_api.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/ATCmdParser.cpp b/platform/ATCmdParser.cpp index 0108e8bb18..7ff2ae00ac 100644 --- a/platform/ATCmdParser.cpp +++ b/platform/ATCmdParser.cpp @@ -1,4 +1,5 @@ /* Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/ATCmdParser.h b/platform/ATCmdParser.h index 0ff4fbd1c5..927b24d992 100644 --- a/platform/ATCmdParser.h +++ b/platform/ATCmdParser.h @@ -1,4 +1,5 @@ /* Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/CThunk.h b/platform/CThunk.h index 0610d5a111..5bd6998ea6 100644 --- a/platform/CThunk.h +++ b/platform/CThunk.h @@ -13,6 +13,7 @@ * - ideally suited for class object receiving interrupts (NVIC_SetVector) * * Copyright (c) 2014-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/CThunkBase.cpp b/platform/CThunkBase.cpp index 39ebea47b6..ce9271bc53 100644 --- a/platform/CThunkBase.cpp +++ b/platform/CThunkBase.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/CThunkBase.h b/platform/CThunkBase.h index ec54a22d4f..c2ae68c28c 100644 --- a/platform/CThunkBase.h +++ b/platform/CThunkBase.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/CallChain.cpp b/platform/CallChain.cpp index 6a72d932a4..db8be12f7e 100644 --- a/platform/CallChain.cpp +++ b/platform/CallChain.cpp @@ -1,3 +1,19 @@ +/* + * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ // Suppress deprecation warnings since this whole // class is deprecated already diff --git a/platform/CallChain.h b/platform/CallChain.h index 3fe17231b0..0f35dc1b5e 100644 --- a/platform/CallChain.h +++ b/platform/CallChain.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/Callback.h b/platform/Callback.h index 1a6b6751bc..52f6732c71 100644 --- a/platform/Callback.h +++ b/platform/Callback.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/CircularBuffer.h b/platform/CircularBuffer.h index 2eb5fd5a04..d1b15e7d5e 100644 --- a/platform/CircularBuffer.h +++ b/platform/CircularBuffer.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/CriticalSectionLock.h b/platform/CriticalSectionLock.h index f654f5d26c..cf861f93a2 100644 --- a/platform/CriticalSectionLock.h +++ b/platform/CriticalSectionLock.h @@ -1,6 +1,6 @@ /* - * PackageLicenseDeclared: Apache-2.0 * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/DeepSleepLock.h b/platform/DeepSleepLock.h index b383770b9a..37aa98376e 100644 --- a/platform/DeepSleepLock.h +++ b/platform/DeepSleepLock.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/DirHandle.h b/platform/DirHandle.h index 47e4b9a449..859d833428 100644 --- a/platform/DirHandle.h +++ b/platform/DirHandle.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileBase.cpp b/platform/FileBase.cpp index 5ee1a98c0d..7a6f0a32b7 100644 --- a/platform/FileBase.cpp +++ b/platform/FileBase.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileBase.h b/platform/FileBase.h index 25b650145b..68b74ed968 100644 --- a/platform/FileBase.h +++ b/platform/FileBase.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileHandle.cpp b/platform/FileHandle.cpp index c8cd9032a7..be8b9cef45 100644 --- a/platform/FileHandle.cpp +++ b/platform/FileHandle.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileHandle.h b/platform/FileHandle.h index c9aea35833..07010df495 100644 --- a/platform/FileHandle.h +++ b/platform/FileHandle.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileLike.h b/platform/FileLike.h index e75be50bfd..f4e1911f23 100644 --- a/platform/FileLike.h +++ b/platform/FileLike.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FilePath.cpp b/platform/FilePath.cpp index 92511d1b68..18cb871986 100644 --- a/platform/FilePath.cpp +++ b/platform/FilePath.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FilePath.h b/platform/FilePath.h index 6183ffbcef..19f1c1b94a 100644 --- a/platform/FilePath.h +++ b/platform/FilePath.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileSystemHandle.cpp b/platform/FileSystemHandle.cpp index 0ce6f1603e..24dc0b2acb 100644 --- a/platform/FileSystemHandle.cpp +++ b/platform/FileSystemHandle.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileSystemHandle.h b/platform/FileSystemHandle.h index bfdf667dc6..d5bd217fc0 100644 --- a/platform/FileSystemHandle.h +++ b/platform/FileSystemHandle.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FileSystemLike.h b/platform/FileSystemLike.h index abcd6358d3..ce6df43881 100644 --- a/platform/FileSystemLike.h +++ b/platform/FileSystemLike.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/FunctionPointer.h b/platform/FunctionPointer.h index c17f53a9a9..90a808015c 100644 --- a/platform/FunctionPointer.h +++ b/platform/FunctionPointer.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/LocalFileSystem.cpp b/platform/LocalFileSystem.cpp index c5c7d33dff..3a5a09cfa8 100644 --- a/platform/LocalFileSystem.cpp +++ b/platform/LocalFileSystem.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/LocalFileSystem.h b/platform/LocalFileSystem.h index 78ca499375..7314320d44 100644 --- a/platform/LocalFileSystem.h +++ b/platform/LocalFileSystem.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/NonCopyable.h b/platform/NonCopyable.h index 4322e4149a..70f76e7177 100644 --- a/platform/NonCopyable.h +++ b/platform/NonCopyable.h @@ -1,4 +1,5 @@ /* Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/PlatformMutex.h b/platform/PlatformMutex.h index ac06a81855..a63672dc0c 100644 --- a/platform/PlatformMutex.h +++ b/platform/PlatformMutex.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/ScopedLock.h b/platform/ScopedLock.h index 8e9018c178..d6d1854d9a 100644 --- a/platform/ScopedLock.h +++ b/platform/ScopedLock.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/SharedPtr.h b/platform/SharedPtr.h index d273507255..0663b2147d 100644 --- a/platform/SharedPtr.h +++ b/platform/SharedPtr.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/SingletonPtr.h b/platform/SingletonPtr.h index 81791ca93f..82b7bcf50a 100644 --- a/platform/SingletonPtr.h +++ b/platform/SingletonPtr.h @@ -7,6 +7,7 @@ */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/Span.h b/platform/Span.h index 04ef2e1ab0..9859402aa2 100644 --- a/platform/Span.h +++ b/platform/Span.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/Stream.cpp b/platform/Stream.cpp index e395425ae7..bdc7af9177 100644 --- a/platform/Stream.cpp +++ b/platform/Stream.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -146,7 +147,7 @@ int Stream::printf(const char *format, ...) lock(); std::va_list arg; va_start(arg, format); - fflush(_file); + std::fseek(_file, 0, SEEK_CUR); int r = vfprintf(_file, format, arg); va_end(arg); unlock(); @@ -168,7 +169,7 @@ int Stream::scanf(const char *format, ...) int Stream::vprintf(const char *format, std::va_list args) { lock(); - fflush(_file); + std::fseek(_file, 0, SEEK_CUR); int r = vfprintf(_file, format, args); unlock(); return r; diff --git a/platform/Stream.h b/platform/Stream.h index bd705c4966..e8783038f4 100644 --- a/platform/Stream.h +++ b/platform/Stream.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/Transaction.h b/platform/Transaction.h index 1d8d6ff9de..6917c4d12b 100644 --- a/platform/Transaction.h +++ b/platform/Transaction.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_alloc_wrappers.cpp b/platform/mbed_alloc_wrappers.cpp index 44521573f7..1d06a4873f 100644 --- a/platform/mbed_alloc_wrappers.cpp +++ b/platform/mbed_alloc_wrappers.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_application.c b/platform/mbed_application.c index eab55bc1cd..c23520b0b3 100644 --- a/platform/mbed_application.c +++ b/platform/mbed_application.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +19,7 @@ #include #include "device.h" #include "platform/mbed_application.h" -#include "hal/mpu_api.h" +#include "platform/mbed_mpu_mgmt.h" #if MBED_APPLICATION_SUPPORT @@ -68,7 +69,18 @@ void mbed_start_application(uintptr_t address) SysTick->CTRL = 0x00000000; powerdown_nvic(); powerdown_scb(address); - mbed_mpu_free(); + mbed_mpu_manager_deinit(); + +#ifdef MBED_DEBUG + // Configs to make debugging easier +#ifdef SCnSCB_ACTLR_DISDEFWBUF_Msk + // Disable write buffer to make BusFaults (eg write to ROM via NULL pointer) precise. + // Possible on Cortex-M3 and M4, not on M0, M7 or M33. + // Would be less necessary if ROM was write-protected in MPU to give a + // precise MemManage exception. + SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk; +#endif +#endif sp = *((void **)address + 0); pc = *((void **)address + 1); diff --git a/platform/mbed_application.h b/platform/mbed_application.h index ba2aebaecb..1cccfb83bc 100644 --- a/platform/mbed_application.h +++ b/platform/mbed_application.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_assert.c b/platform/mbed_assert.c index bc1934461a..5ed490a110 100644 --- a/platform/mbed_assert.c +++ b/platform/mbed_assert.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_assert.h b/platform/mbed_assert.h index 4976c11b45..a748f3aceb 100644 --- a/platform/mbed_assert.h +++ b/platform/mbed_assert.h @@ -7,6 +7,7 @@ */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_board.c b/platform/mbed_board.c index 59635d1d33..d882f6ec1c 100644 --- a/platform/mbed_board.c +++ b/platform/mbed_board.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -58,7 +59,7 @@ void mbed_error_vprintf(const char *format, va_list arg) { char buffer[132]; int size = vsnprintf(buffer, sizeof buffer, format, arg); - if (size >= sizeof buffer) { + if ((unsigned int)size >= sizeof buffer) { /* Output was truncated - indicate by overwriting tail of buffer * with ellipsis, newline and null terminator. */ diff --git a/platform/mbed_debug.h b/platform/mbed_debug.h index 38da79a821..f560f3db33 100644 --- a/platform/mbed_debug.h +++ b/platform/mbed_debug.h @@ -8,6 +8,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_error.c b/platform/mbed_error.c index 0faca8b7fc..9c38322773 100644 --- a/platform/mbed_error.c +++ b/platform/mbed_error.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -210,7 +211,9 @@ mbed_error_status_t mbed_error_initialize(void) if ((report_error_ctx->crc_error_ctx == crc_val) && (report_error_ctx->is_error_processed == 0)) { is_reboot_error_valid = true; //Report the error info +#ifndef NDEBUG printf("\n== The system has been rebooted due to a fatal error. ==\n"); +#endif //Call the mbed_error_reboot_callback, this enables applications to do some handling before we do the handling mbed_error_reboot_callback(report_error_ctx); @@ -222,7 +225,9 @@ mbed_error_status_t mbed_error_initialize(void) #if MBED_CONF_PLATFORM_FATAL_ERROR_AUTO_REBOOT_ENABLED if (report_error_ctx->error_reboot_count >= MBED_CONF_PLATFORM_ERROR_REBOOT_MAX) { //We have rebooted more than enough, hold the system here. +#ifndef NDEBUG printf("\n== Reboot count(=%ld) exceeded maximum, system halting ==\n", report_error_ctx->error_reboot_count); +#endif mbed_halt_system(); } #endif diff --git a/platform/mbed_error.h b/platform/mbed_error.h index 56355e48e0..d91c967f6c 100644 --- a/platform/mbed_error.h +++ b/platform/mbed_error.h @@ -6,6 +6,7 @@ */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_error_hist.c b/platform/mbed_error_hist.c index 411ae097ca..9a618e5dda 100644 --- a/platform/mbed_error_hist.c +++ b/platform/mbed_error_hist.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_error_hist.h b/platform/mbed_error_hist.h index e83315bfec..791b562b65 100644 --- a/platform/mbed_error_hist.h +++ b/platform/mbed_error_hist.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_interface.c b/platform/mbed_interface.c index b1a43697e9..ddacbb99ae 100644 --- a/platform/mbed_interface.c +++ b/platform/mbed_interface.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_interface.h b/platform/mbed_interface.h index 241cd7be8d..dd20080ed2 100644 --- a/platform/mbed_interface.h +++ b/platform/mbed_interface.h @@ -8,6 +8,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_mem_trace.cpp b/platform/mbed_mem_trace.cpp index f34453cfd3..8ba4dd8095 100644 --- a/platform/mbed_mem_trace.cpp +++ b/platform/mbed_mem_trace.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_mem_trace.h b/platform/mbed_mem_trace.h index a1b2f10f87..28760b8607 100644 --- a/platform/mbed_mem_trace.h +++ b/platform/mbed_mem_trace.h @@ -4,6 +4,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_mktime.c b/platform/mbed_mktime.c index 68e3b9f62d..7c282325a4 100644 --- a/platform/mbed_mktime.c +++ b/platform/mbed_mktime.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_mktime.h b/platform/mbed_mktime.h index eed21a9fc3..58b7624969 100644 --- a/platform/mbed_mktime.h +++ b/platform/mbed_mktime.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2017-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_mpu_mgmt.h b/platform/mbed_mpu_mgmt.h index 6140c3110f..8364941d79 100644 --- a/platform/mbed_mpu_mgmt.h +++ b/platform/mbed_mpu_mgmt.h @@ -35,6 +35,8 @@ extern "C" { #define mbed_mpu_manager_init() mbed_mpu_init() +#define mbed_mpu_manager_deinit() mbed_mpu_free() + /** Lock ram execute never mode off * * This disables the MPU's execute never ram protection and allows @@ -87,6 +89,8 @@ void mbed_mpu_manager_unlock_rom_write(void); #define mbed_mpu_manager_init() (void)0 +#define mbed_mpu_manager_deinit() (void)0 + #define mbed_mpu_manager_lock_ram_execution() (void)0 #define mbed_mpu_manager_unlock_ram_execution() (void)0 diff --git a/platform/mbed_poll.cpp b/platform/mbed_poll.cpp index da9e825d8a..a1e7627616 100644 --- a/platform/mbed_poll.cpp +++ b/platform/mbed_poll.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_poll.h b/platform/mbed_poll.h index f9c894c21f..43d7cce57c 100644 --- a/platform/mbed_poll.h +++ b/platform/mbed_poll.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_power_mgmt.h b/platform/mbed_power_mgmt.h index ba0d1bda39..3b8791f2b1 100644 --- a/platform/mbed_power_mgmt.h +++ b/platform/mbed_power_mgmt.h @@ -7,6 +7,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_preprocessor.h b/platform/mbed_preprocessor.h index 7df3bb6812..42685cda1c 100644 --- a/platform/mbed_preprocessor.h +++ b/platform/mbed_preprocessor.h @@ -7,6 +7,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp index 7e8ed8725d..276701f70b 100644 --- a/platform/mbed_retarget.cpp +++ b/platform/mbed_retarget.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2015 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h index d61f3c8c65..9eb27dca6a 100644 --- a/platform/mbed_retarget.h +++ b/platform/mbed_retarget.h @@ -1,6 +1,7 @@ /* * mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_rtc_time.cpp b/platform/mbed_rtc_time.cpp index 7ec6171b4d..37cb1cf526 100644 --- a/platform/mbed_rtc_time.cpp +++ b/platform/mbed_rtc_time.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_rtc_time.h b/platform/mbed_rtc_time.h index f1b04c3d68..1dc021c806 100644 --- a/platform/mbed_rtc_time.h +++ b/platform/mbed_rtc_time.h @@ -7,6 +7,7 @@ */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_sdk_boot.c b/platform/mbed_sdk_boot.c index 32658ef60c..9f3aef1899 100644 --- a/platform/mbed_sdk_boot.c +++ b/platform/mbed_sdk_boot.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_semihost_api.c b/platform/mbed_semihost_api.c index f655862c3a..c9975519fc 100644 --- a/platform/mbed_semihost_api.c +++ b/platform/mbed_semihost_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_semihost_api.h b/platform/mbed_semihost_api.h index 2f20c8cbb2..dde34f8a53 100644 --- a/platform/mbed_semihost_api.h +++ b/platform/mbed_semihost_api.h @@ -1,6 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_stats.c b/platform/mbed_stats.c index b4a3d3de32..ffc464c6de 100644 --- a/platform/mbed_stats.c +++ b/platform/mbed_stats.c @@ -13,7 +13,7 @@ #warning Statistics are currently not supported without the rtos. #endif -#if defined(MBED_CPU_STATS_ENABLED) && (!defined(DEVICE_LPTICKER) || !defined(DEVICE_SLEEP)) +#if defined(MBED_CPU_STATS_ENABLED) && (!DEVICE_LPTICKER || !DEVICE_SLEEP) #warning CPU statistics are not supported without low power timer support. #endif @@ -21,7 +21,7 @@ void mbed_stats_cpu_get(mbed_stats_cpu_t *stats) { MBED_ASSERT(stats != NULL); memset(stats, 0, sizeof(mbed_stats_cpu_t)); -#if defined(MBED_CPU_STATS_ENABLED) && defined(DEVICE_LPTICKER) && defined(DEVICE_SLEEP) +#if defined(MBED_CPU_STATS_ENABLED) && DEVICE_LPTICKER && DEVICE_SLEEP stats->uptime = mbed_uptime(); stats->idle_time = mbed_time_idle(); stats->sleep_time = mbed_time_sleep(); diff --git a/platform/mbed_stats.h b/platform/mbed_stats.h index bb6617334f..1f93f42d95 100644 --- a/platform/mbed_stats.h +++ b/platform/mbed_stats.h @@ -7,6 +7,7 @@ */ /* mbed Microcontroller Library * Copyright (c) 2016-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -155,14 +156,14 @@ typedef enum { * struct mbed_stats_sys_t definition */ typedef struct { - uint32_t os_version; /**< Mbed OS version (populated only for tagged releases) */ - uint32_t cpu_id; /**< CPUID register data (Cortex-M only supported) */ - mbed_compiler_id_t compiler_id; /**< Compiler ID \ref mbed_compiler_id_t */ - uint32_t compiler_version; /**< Compiler version */ - uint32_t ram_start[MBED_MAX_MEM_REGIONS];/**< Start addresses of all internal RAM memories */ - uint32_t ram_size[MBED_MAX_MEM_REGIONS];/**< Size of all internal RAM memories in target */ - uint32_t rom_start[MBED_MAX_MEM_REGIONS];/**< Start addresses of all internal ROM memories */ - uint32_t rom_size[MBED_MAX_MEM_REGIONS];/**< Size of all internal ROM memories in target */ + uint32_t os_version; /**< Mbed OS version (populated only for tagged releases) */ + uint32_t cpu_id; /**< CPUID register data (Cortex-M only supported) */ + mbed_compiler_id_t compiler_id; /**< Compiler ID \ref mbed_compiler_id_t */ + uint32_t compiler_version; /**< Compiler version */ + uint32_t ram_start[MBED_MAX_MEM_REGIONS]; /**< Start addresses of all internal RAM memories */ + uint32_t ram_size[MBED_MAX_MEM_REGIONS]; /**< Size of all internal RAM memories in target */ + uint32_t rom_start[MBED_MAX_MEM_REGIONS]; /**< Start addresses of all internal ROM memories */ + uint32_t rom_size[MBED_MAX_MEM_REGIONS]; /**< Size of all internal ROM memories in target */ } mbed_stats_sys_t; /** diff --git a/platform/mbed_toolchain.h b/platform/mbed_toolchain.h index fba7d32bed..b36775c5f4 100644 --- a/platform/mbed_toolchain.h +++ b/platform/mbed_toolchain.h @@ -8,6 +8,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_version.h b/platform/mbed_version.h index 383044190c..1a21d28b63 100644 --- a/platform/mbed_version.h +++ b/platform/mbed_version.h @@ -7,6 +7,7 @@ */ /* mbed Microcontroller Library * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -43,7 +44,7 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_PATCH_VERSION 0 +#define MBED_PATCH_VERSION 1 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch)) diff --git a/platform/mbed_wait_api.h b/platform/mbed_wait_api.h index 92a380ed9d..9402d6050a 100644 --- a/platform/mbed_wait_api.h +++ b/platform/mbed_wait_api.h @@ -8,6 +8,7 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_wait_api_no_rtos.c b/platform/mbed_wait_api_no_rtos.c index c29ba17217..d03840e866 100644 --- a/platform/mbed_wait_api_no_rtos.c +++ b/platform/mbed_wait_api_no_rtos.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/mbed_wait_api_rtos.cpp b/platform/mbed_wait_api_rtos.cpp index f859093900..f3b987ae69 100644 --- a/platform/mbed_wait_api_rtos.cpp +++ b/platform/mbed_wait_api_rtos.cpp @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -53,7 +54,7 @@ void wait_ms(int ms) if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) { #if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_INVALID_OPERATION), - "Deprecated behavior: milli-sec delay should not be used in interrupt.\n"); + "Deprecated behavior: milli-sec delay should not be used in interrupt.\n"); #else wait_us(ms * 1000); #endif diff --git a/platform/platform.h b/platform/platform.h index a5802ff655..33a48c9499 100644 --- a/platform/platform.h +++ b/platform/platform.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/platform/toolchain.h b/platform/toolchain.h index 6fbef808ca..cf561fca75 100644 --- a/platform/toolchain.h +++ b/platform/toolchain.h @@ -3,6 +3,7 @@ /** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/requirements.txt b/requirements.txt index 49d67828bf..b1bd56b1c9 100644 --- a/requirements.txt +++ b/requirements.txt @@ -7,6 +7,7 @@ junit-xml==1.8 pyYAML==3.13 urllib3[secure]==1.23 requests>=2.20,<2.21 +intervaltree>=2,<3 mbed-ls>=1.5.1,<1.7 mbed-host-tests>=1.1.2,<=1.5 mbed-greentea>=0.2.24,<=1.5 diff --git a/rtos/TARGET_CORTEX/SysTimer.h b/rtos/TARGET_CORTEX/SysTimer.h index dd6b30cf33..e4c008e317 100644 --- a/rtos/TARGET_CORTEX/SysTimer.h +++ b/rtos/TARGET_CORTEX/SysTimer.h @@ -22,7 +22,7 @@ #ifndef MBED_SYS_TIMER_H #define MBED_SYS_TIMER_H -#if defined(DEVICE_LPTICKER) || defined(DOXYGEN_ONLY) +#if DEVICE_LPTICKER || defined(DOXYGEN_ONLY) #include "platform/NonCopyable.h" #include "drivers/TimerEvent.h" diff --git a/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c b/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c index c968deb755..58080a168d 100644 --- a/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c +++ b/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_STD/mbed_boot_arm_std.c b/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_STD/mbed_boot_arm_std.c index 1475082d8a..482870f501 100644 --- a/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_STD/mbed_boot_arm_std.c +++ b/rtos/TARGET_CORTEX/TOOLCHAIN_ARM_STD/mbed_boot_arm_std.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c b/rtos/TARGET_CORTEX/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c index 105f780860..1060f349f6 100644 --- a/rtos/TARGET_CORTEX/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c +++ b/rtos/TARGET_CORTEX/TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/TOOLCHAIN_IAR/mbed_boot_iar.c b/rtos/TARGET_CORTEX/TOOLCHAIN_IAR/mbed_boot_iar.c index 387b7f8dc1..0812be93f0 100644 --- a/rtos/TARGET_CORTEX/TOOLCHAIN_IAR/mbed_boot_iar.c +++ b/rtos/TARGET_CORTEX/TOOLCHAIN_IAR/mbed_boot_iar.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/mbed_boot.c b/rtos/TARGET_CORTEX/mbed_boot.c index b652649bc3..c3f691888b 100644 --- a/rtos/TARGET_CORTEX/mbed_boot.c +++ b/rtos/TARGET_CORTEX/mbed_boot.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/mbed_boot.h b/rtos/TARGET_CORTEX/mbed_boot.h index 7aef50fe91..aed0cdd707 100644 --- a/rtos/TARGET_CORTEX/mbed_boot.h +++ b/rtos/TARGET_CORTEX/mbed_boot.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/mbed_rtos1_types.h b/rtos/TARGET_CORTEX/mbed_rtos1_types.h index 73df37f061..e44fa25edb 100644 --- a/rtos/TARGET_CORTEX/mbed_rtos1_types.h +++ b/rtos/TARGET_CORTEX/mbed_rtos1_types.h @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2017 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/rtos/TARGET_CORTEX/mbed_rtos_rtx.c b/rtos/TARGET_CORTEX/mbed_rtos_rtx.c index 6e7a11c2e8..6446ab34b1 100644 --- a/rtos/TARGET_CORTEX/mbed_rtos_rtx.c +++ b/rtos/TARGET_CORTEX/mbed_rtos_rtx.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2018-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/mbed_rtx_handlers.c b/rtos/TARGET_CORTEX/mbed_rtx_handlers.c index 8bc395cba3..845990c7c1 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_handlers.c +++ b/rtos/TARGET_CORTEX/mbed_rtx_handlers.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index 9c095396d0..aaf23db94a 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -35,7 +35,7 @@ extern "C" { using namespace mbed; -#if (defined(MBED_TICKLESS) && defined(DEVICE_LPTICKER)) +#if (defined(MBED_TICKLESS) && DEVICE_LPTICKER) #include "rtos/TARGET_CORTEX/SysTimer.h" @@ -138,7 +138,7 @@ extern "C" { core_util_critical_section_exit(); } -#endif // (defined(MBED_TICKLESS) && defined(DEVICE_LPTICKER)) +#endif // (defined(MBED_TICKLESS) && DEVICE_LPTICKER) static void (*idle_hook_fptr)(void) = &default_idle_hook; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md index abd8627062..2ebdb602db 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md @@ -3,7 +3,7 @@ README for pre-compiled PSoC 6 Cortex M0+ core images This folder contains precompiled program images for the CM0+ core of the PSoC 6(63xx) MCU suitable for use with MBed OS applications running on CM4 core. Two images are available: -* `psoc63_m0_default_1.01.hex` +* `psoc63_m0_default_1.02.hex` This image contains basic code, that brings up the chip, starts CM4 core and puts CM0+ core into a deep sleep. It is suitable for use with all Mbed applications except those intendif to use BLE feature. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_default_1.01.hex b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_default_1.01.hex deleted file mode 100644 index d605fa34de..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_default_1.01.hex +++ /dev/null @@ -1,150 +0,0 @@ -:020000041000EA -:4000000000000108310100100D00000095010010000000000000000000000000000000000000000000000000000000009101001000000000000000009101001091010010DC -:4000400091010010F10700109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010FA -:400080009101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001091010010910100109101001020 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+:40238000844601BC604700BF010D001001B40248844601BC604700BFE50300100000000000000000000000000000000000000000000000000000000000000000000000002E +:4023C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000DD +:0200000490303A +:02000000355376 +:0200000490501A +:0C0000000005E20721002101E212565326 +:00000001FF \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h index 9a1f9870c0..f343bdeb40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h @@ -64,11 +64,11 @@ // Reservations below apply to default M0 hex image. // P0_0 and p0_1 reserved for WCO, P6-6 and P6_7 reserved for SWD -#define M0_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(6, 0xc0), SRM_PORT(11, 0x02) -// 8-bit divider 0 reserved for us ticker. -#define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01), \ - SRM_DIVIDER(CY_SYSCLK_DIV_16_BIT, 0x01) +#define M0_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(6, 0xc0) +// 8-bit divider 0 reserved for us ticker +#define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01) #define M0_ASSIGNED_SCBS -#define M0_ASSIGNED_TCPWMS +// TCPWM 0,0 used for us_ticker +#define M0_ASSIGNED_TCPWMS SRM_TCPWM(0) /* End of File */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c index 076f4c01d2..1ea8352f53 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6_utils.c @@ -100,8 +100,8 @@ do { \ #define SRM_TCPWM(num) {(num), (0)} #define DEFAULT_PORT_RES 0xff -#define DEFAULT_DIVIDER8_RES 0xff #define DEFAULT_DIVIDER_RES 0xffff +#define DEFAULT_DIVIDER8_RES 0xffff #define DEFAULT_SCM_RES 1 #define DEFAULT_TCPWM_RES 1 @@ -439,6 +439,21 @@ void cy_get_bd_mac_address(uint8_t *buffer) void cy_srm_initialize(void) { +#if defined(TARGET_MCU_PSOC6_M0) || PSOC6_DYNSRM_DISABLE || !defined(__MBED__) + uint32_t i; + + for (i = 0; i < CY_NUM_PSOC6_PORTS; ++i) { + port_reservations[i] = DEFAULT_PORT_RES; + } + + for (i = 0; i < NUM_SCB; ++i) { + scb_reservations[i] = DEFAULT_SCM_RES; + } + + for (i = 0; i < NUM_TCPWM; ++i) { + tcpwm_reservations[i] = DEFAULT_TCPWM_RES; + } + #if PSOC6_DYNSRM_DISABLE #ifdef M0_ASSIGNED_PORTS SRM_INIT_RESOURCE(uint8_t, port_reservations,, M0_ASSIGNED_PORTS); @@ -453,5 +468,6 @@ void cy_srm_initialize(void) SRM_INIT_RESOURCE(uint8_t, tcpwm_reservations,, M0_ASSIGNED_TCPWMS); #endif #endif // PSOC6_DYNSRM_DISABLE +#endif // defined(TARGET_MCU_PSOC6_M0) || PSOC6_DSRM_DISABLE || !defined(__MBED__) } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/mbed_overrides.c index 3c62ed7ca4..a80b1e7a22 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/mbed_overrides.c @@ -17,12 +17,42 @@ #define CRC16 #include "crc.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -34,13 +64,6 @@ void NMI_Handler(void) gpio_init_in(&gpio, PTA4); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} - // Provide ethernet devices with a semi-unique MAC address from the UUID void mbed_mac_address(char *mac) { @@ -55,7 +78,7 @@ void mbed_mac_address(char *mac) // generate three CRC16's using different slices of the UUID MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word - MAC[1] = crcSlow((const uint8_t *)UID, 12); + MAC[1] = crcSlow((const uint8_t *)UID, 12); MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word // The network stack expects an array of 6 bytes diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c index 19fc8cc11d..dbec2c7c68 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_FRDM/mbed_overrides.c @@ -14,12 +14,42 @@ * limitations under the License. */ #include "gpio_api.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -31,13 +61,6 @@ void NMI_Handler(void) gpio_init_in(&gpio, PTA4); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} - // Set the UART clock source void serial_clock_init(void) { diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c index bb690f2fde..5295be6fd9 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c @@ -17,13 +17,18 @@ #include "fsl_smc.h" #include "fsl_rcm.h" #include "fsl_pmc.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" //!< this contains the wakeup source rcm_reset_source_t kinetisResetSource; // called before main -void mbed_sdk_init() { +void mbed_sdk_init() +{ + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); // check the power mode source @@ -36,6 +41,31 @@ void mbed_sdk_init() { BOARD_BootClockRUN(); + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -47,13 +77,6 @@ void NMI_Handler(void) gpio_init_in(&gpio, PTA4); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} - // Set the UART clock source void serial_clock_init(void) { diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c index 1018bac9e4..a85b0e651c 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/TARGET_FRDM/mbed_overrides.c @@ -15,22 +15,45 @@ */ #include "gpio_api.h" #include "pinmap.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main - implement here if board needs it otherwise, let // the application override this if necessary void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); /* Set the TPM clock source to be IRC48M, do not change as TPM2 is used for the usticker */ CLOCK_SetTpmClock(1U); -} -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/TARGET_FRDM/mbed_overrides.c index 1018bac9e4..a85b0e651c 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/TARGET_FRDM/mbed_overrides.c @@ -15,22 +15,45 @@ */ #include "gpio_api.h" #include "pinmap.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main - implement here if board needs it otherwise, let // the application override this if necessary void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); /* Set the TPM clock source to be IRC48M, do not change as TPM2 is used for the usticker */ CLOCK_SetTpmClock(1U); -} -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c index 68f82af26f..7ce11c7d89 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c @@ -15,20 +15,43 @@ */ #include "gpio_api.h" #include "pinmap.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main - implement here if board needs it otherwise, let // the application override this if necessary void mbed_sdk_init() { - BOARD_BootClockRUN(); -} + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c index 19ab30c8a4..3c72d889ea 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c @@ -17,13 +17,18 @@ #include "fsl_smc.h" #include "fsl_rcm.h" #include "fsl_pmc.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" //!< this contains the wakeup source rcm_reset_source_t kinetisResetSource; // called before main -void mbed_sdk_init() { +void mbed_sdk_init() +{ + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); // check the power mode source @@ -35,6 +40,32 @@ void mbed_sdk_init() { } BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -46,15 +77,6 @@ void NMI_Handler(void) gpio_init_in(&gpio, PTA4); } -#if DEVICE_RTC || DEVICE_LPTICKER -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} -#endif - // Set the UART clock source void serial_clock_init(void) { diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c index 8b86ba6b16..55e6972f88 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/mbed_overrides.c @@ -14,20 +14,43 @@ * limitations under the License. */ #include "gpio_api.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main - implement here if board needs it otherwise, let // the application override this if necessary void mbed_sdk_init() { - BOARD_BootClockRUN(); -} + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_FRDM/mbed_overrides.c index ff33f79a84..aa7e31c942 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_FRDM/mbed_overrides.c @@ -14,22 +14,45 @@ * limitations under the License. */ #include "gpio_api.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main - implement here if board needs it otherwise, let // the application override this if necessary void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); /* Set the TPM clock source to be OSCERCLK, do not change as TPM2 is used for the usticker */ CLOCK_SetTpmClock(2U); -} -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PeripheralNames.h new file mode 100644 index 0000000000..c30c20b51f --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PeripheralNames.h @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0 +} RTCName; + +typedef enum { + LPUART_0 = 0 +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART LPUART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3 + PWM_5 = (1 << TPM_SHIFT) | (0), // TPM1 CH0 + PWM_6 = (1 << TPM_SHIFT) | (1) // TPM1 CH1 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE1 = (0 << ADC_INSTANCE_SHIFT) | 1, + ADC0_SE2 = (0 << ADC_INSTANCE_SHIFT) | 2, + ADC0_SE3 = (0 << ADC_INSTANCE_SHIFT) | 3, + ADC0_SE4 = (0 << ADC_INSTANCE_SHIFT) | 4, + ADC0_SE5 = (0 << ADC_INSTANCE_SHIFT) | 5, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PeripheralPins.c new file mode 100644 index 0000000000..5bc469c698 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PeripheralPins.c @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTB1, ADC0_SE1, 0}, + {PTB3, ADC0_SE2, 0}, + {PTB2, ADC0_SE3, 0}, + {PTB18, ADC0_SE4, 0}, + {PTA19, ADC0_SE5, 0}, + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTB1, I2C_0, 3}, + {PTB17, I2C_1, 3}, + {PTC1, I2C_0, 3}, + {PTC3, I2C_1, 3}, + {PTC7, I2C_1, 3}, + {PTC16, I2C_0, 3}, + {PTC18, I2C_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTB0, I2C_0, 3}, + {PTB16, I2C_1, 3}, + {PTB18, I2C_1, 3}, + {PTC2, I2C_1, 3}, + {PTC6, I2C_1, 3}, + {PTC17, I2C_1, 3}, + {PTC19, I2C_0, 3}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTC3, LPUART_0, 4}, + {PTC7, LPUART_0, 4}, + {PTC18, LPUART_0, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTC2, LPUART_0, 4}, + {PTC6, LPUART_0, 4}, + {PTC17, LPUART_0, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PTC4, LPUART_0, 4}, + {PTC19, LPUART_0, 4}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PTC1, LPUART_0, 4}, + {PTC5, LPUART_0, 4}, + {PTC16, LPUART_0, 4}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTA18, SPI_1, 2}, + {PTC16, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTA16, SPI_1, 2}, + {PTC17, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTA17, SPI_1, 2}, + {PTC18, SPI_0, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTA1, SPI_1, 2}, + {PTA19, SPI_1, 2}, + {PTC19, SPI_0, 2}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + /* TPM 0 */ + {PTA16, PWM_1, 5}, + {PTB0, PWM_2, 5}, + {PTB1, PWM_3, 5}, + {PTA2, PWM_4, 5}, + {PTB18, PWM_1, 5}, + {PTC3, PWM_2, 5}, + {PTC1, PWM_3, 5}, + {PTC16, PWM_4, 5}, + /* TPM 1 */ + {PTA0, PWM_5, 5}, + {PTA1, PWM_6, 5}, + {PTB2, PWM_5, 5}, + {PTB3, PWM_6, 5}, + {PTC4, PWM_5, 5}, + {PTC5, PWM_6, 5}, + {NC , NC , 0} +}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PinNames.h new file mode 100644 index 0000000000..373fcaf1f2 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/PinNames.h @@ -0,0 +1,126 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0), + PTA1 = (0 << GPIO_PORT_SHIFT | 1), + PTA2 = (0 << GPIO_PORT_SHIFT | 2), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTB0 = (1 << GPIO_PORT_SHIFT | 0), + PTB1 = (1 << GPIO_PORT_SHIFT | 1), + PTB2 = (1 << GPIO_PORT_SHIFT | 2), + PTB3 = (1 << GPIO_PORT_SHIFT | 3), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTC1 = (2 << GPIO_PORT_SHIFT | 1), + PTC2 = (2 << GPIO_PORT_SHIFT | 2), + PTC3 = (2 << GPIO_PORT_SHIFT | 3), + PTC4 = (2 << GPIO_PORT_SHIFT | 4), + PTC5 = (2 << GPIO_PORT_SHIFT | 5), + PTC6 = (2 << GPIO_PORT_SHIFT | 6), + PTC7 = (2 << GPIO_PORT_SHIFT | 7), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + + LED_RED = PTC1, + LED_GREEN = PTA19, + LED_BLUE = PTA18, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + //Push buttons + SW3 = PTC4, + SW4 = PTC5, + // Standardized button names + BUTTON1 = SW3, + BUTTON2 = SW4, + + // USB Pins + USBTX = PTC7, + USBRX = PTC6, + + // Arduino Headers + D0 = PTC6, + D1 = PTC7, + D2 = PTC19, + D3 = PTC16, + D4 = PTC4, + D5 = PTC17, + D6 = PTC18, + D7 = PTA1, + D8 = PTA0, + D9 = PTC1, + D10 = PTA19, + D11 = PTA16, + D12 = PTA17, + D13 = PTA18, + D14 = PTC3, + D15 = PTC2, + + I2C_SCL = D15, + I2C_SDA = D14, + + DAC0_OUT = PTB18, + + A1 = DAC0_OUT, + A2 = PTB2, + A3 = PTB3, + A4 = PTB1, + A5 = PTB0, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/device.h new file mode 100644 index 0000000000..822469f611 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/device.h @@ -0,0 +1,40 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + + + + + + + + + + + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/fsl_clock_config.c new file mode 100644 index 0000000000..f0809a1dd6 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/fsl_clock_config.c @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 5U, + .drs = kMCG_DrsLow, /* Low frequency range */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ + .oscsel = kMCG_OscselOsc, /* Select OSC */ + }, + .simConfig = + { + .er32kSrc = 0U, /* ERCLK32K selection, use OSC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = + { + .freq = BOARD_XTAL0_CLK_HZ, /* Feed by RF XTAL_32M */ + .workMode = kOSC_ModeExt, /* Must work in external source mode. */ + }, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 40MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModeFEE, /* Work in FEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 5U, + .drs = kMCG_DrsMid, /* Middle frequency range */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ + .oscsel = kMCG_OscselOsc, /* Select OSC */ + }, + .simConfig = + { + .er32kSrc = 0U, /* ERCLK32K selection, use OSC. */ + .clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = + { + .freq = BOARD_XTAL0_CLK_HZ, /* Feed by RF XTAL_32M */ + .workMode = kOSC_ModeExt, /* Must work in external source mode. */ + }, + .coreClock = 40000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +static void CLOCK_SYS_FllStableDelay(void) +{ + uint32_t i = 30000U; + while (i--) + { + __NOP(); + } +} + +void BOARD_BootClockVLPR(void) +{ + /* ERR010224 */ + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */ + + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + BOARD_RfOscInit(); + + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + CLOCK_BootToFeeMode(kMCG_OscselOsc, g_defaultClockConfigRun.mcgConfig.frdiv, + g_defaultClockConfigRun.mcgConfig.dmx32, g_defaultClockConfigRun.mcgConfig.drs, + CLOCK_SYS_FllStableDelay); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, + g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} + +void BOARD_RfOscInit(void) +{ + uint32_t temp, tempTrim; + uint8_t revId; + + /* Obtain REV ID from SIM */ + temp = SIM->SDID; + revId = (uint8_t)((temp & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT); + + if(0 == revId) + { + tempTrim = RSIM->ANA_TRIM; + RSIM->ANA_TRIM |= RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK; /* Set max trim for BB LDO for XO */ + }/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */ + + /* Turn on clocks for the XCVR */ + /* Enable RF OSC in RSIM and wait for ready */ + temp = RSIM->CONTROL; + temp &= ~RSIM_CONTROL_RF_OSC_EN_MASK; + RSIM->CONTROL = temp | RSIM_CONTROL_RF_OSC_EN(1); + + /* ERR010224 */ + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */ + + while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0); /* Wait for RF_OSC_READY */ + + if(0 == revId) + { + SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; + XCVR_TSM->OVRD0 |= XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK | XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK; /* Force ADC DAC LDO on to prevent BGAP failure */ + + RSIM->ANA_TRIM = tempTrim; /* Reset LDO trim settings */ + }/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */ +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/fsl_clock_config.h new file mode 100644 index 0000000000..beecd44218 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/fsl_clock_config.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 32000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); +void BOARD_RfOscInit(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/mbed_overrides.c new file mode 100644 index 0000000000..1900ac4832 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/TARGET_RAPIDIOT/mbed_overrides.c @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "fsl_rtc.h" +#include "fsl_clock_config.h" + +// called before main - implement here if board needs it otherwise, let +// the application override this if necessary +void mbed_sdk_init() +{ + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + + BOARD_BootClockRUN(); + /* Set the TPM clock source to be OSCERCLK, do not change as TPM2 is used for the usticker */ + CLOCK_SetTpmClock(2U); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/TARGET_FRDM/mbed_overrides.c index d518bef318..75b2741945 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/TARGET_MCU_K22F512/TARGET_FRDM/mbed_overrides.c @@ -15,21 +15,44 @@ */ #include "gpio_api.h" #include "pinmap.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main - implement here if board needs it otherwise, let // the application override this if necessary void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); pin_function(PTA2, 1); //By default the GREEN LED is enabled. This disables it -} -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -40,3 +63,4 @@ void NMI_Handler(void) gpio_t gpio; gpio_init_in(&gpio, PTA4); } + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c index 0fa409f8c7..be4c287c2a 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c @@ -17,12 +17,42 @@ #define CRC16 #include "crc.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -34,10 +64,3 @@ void NMI_Handler(void) gpio_init_in(&gpio, PTA4); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c index 3c62ed7ca4..a80b1e7a22 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c @@ -17,12 +17,42 @@ #define CRC16 #include "crc.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -34,13 +64,6 @@ void NMI_Handler(void) gpio_init_in(&gpio, PTA4); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} - // Provide ethernet devices with a semi-unique MAC address from the UUID void mbed_mac_address(char *mac) { @@ -55,7 +78,7 @@ void mbed_mac_address(char *mac) // generate three CRC16's using different slices of the UUID MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word - MAC[1] = crcSlow((const uint8_t *)UID, 12); + MAC[1] = crcSlow((const uint8_t *)UID, 12); MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word // The network stack expects an array of 6 bytes diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/mbed_overrides.c index 7b93dffa50..13694063f3 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/mbed_overrides.c @@ -14,19 +14,41 @@ * limitations under the License. */ #include "gpio_api.h" - +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); -} - -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c index 3d28610d0a..13694063f3 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c @@ -14,16 +14,41 @@ * limitations under the License. */ #include "gpio_api.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" + // called before main void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/mbed_overrides.c index d7b02e69f3..cf39e207cd 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_RAPIDIOT/mbed_overrides.c @@ -33,6 +33,9 @@ void mbed_sdk_init() /* Check if the Rtc oscillator is enabled */ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + RTC_Init(RTC, &rtc_basic_config); /* Enable the RTC 32KHz oscillator */ @@ -48,6 +51,8 @@ void mbed_sdk_init() /* 32kHz Oscillator is ready. */ RTC_Deinit(RTC); } + + CLOCK_DisableClock(kCLOCK_Rtc0); } void rtc_setup_oscillator(void) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c index 3c62ed7ca4..f4318d9fb5 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_SDT64B/mbed_overrides.c @@ -17,12 +17,42 @@ #define CRC16 #include "crc.h" +#include "fsl_rtc.h" #include "fsl_clock_config.h" // called before main void mbed_sdk_init() { + rtc_config_t rtc_basic_config; + uint32_t u32cTPR_counter = 0; + BOARD_BootClockRUN(); + + CLOCK_EnableClock(kCLOCK_Rtc0); + + /* Check if the Rtc oscillator is enabled */ + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { + /*Init the RTC with default configuration*/ + RTC_GetDefaultConfig(&rtc_basic_config); + + /* Setup the 32K RTC OSC */ + RTC_Init(RTC, &rtc_basic_config); + + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + + /* Start the RTC time counter */ + RTC_StartTimer(RTC); + + /* Verify TPR register reaches 4096 counts */ + while (u32cTPR_counter < 4096) { + u32cTPR_counter = RTC->TPR; + } + /* 32kHz Oscillator is ready. */ + RTC_Deinit(RTC); + } + + CLOCK_DisableClock(kCLOCK_Rtc0); } // Change the NMI pin to an input. This allows NMI pin to @@ -34,13 +64,6 @@ void NMI_Handler(void) gpio_init_in(&gpio, PTA4); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(RTC_Type *base) -{ - /* Enable the RTC oscillator */ - RTC->CR |= RTC_CR_OSCE_MASK; -} - // Provide ethernet devices with a semi-unique MAC address from the UUID void mbed_mac_address(char *mac) { @@ -55,7 +78,7 @@ void mbed_mac_address(char *mac) // generate three CRC16's using different slices of the UUID MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word - MAC[1] = crcSlow((const uint8_t *)UID, 12); + MAC[1] = crcSlow((const uint8_t *)UID, 12); MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word // The network stack expects an array of 6 bytes @@ -76,5 +99,3 @@ void mbed_mac_address(char *mac) } - - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c index 488f09f298..5d66dbca2a 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c @@ -33,8 +33,6 @@ const ticker_info_t* lp_ticker_get_info() static bool lp_ticker_inited = false; -extern void rtc_setup_oscillator(RTC_Type *base); - static void lptmr_isr(void) { LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag); @@ -52,9 +50,6 @@ void lp_ticker_init(void) /* Setup high resolution clock - LPTMR */ LPTMR_GetDefaultConfig(&lptmrConfig); - /* Setup the RTC 32KHz oscillator */ - CLOCK_EnableClock(kCLOCK_Rtc0); - rtc_setup_oscillator(RTC); /* Use 32kHz drive */ CLOCK_SetXtal32Freq(OSC32K_CLK_HZ); @@ -68,8 +63,7 @@ void lp_ticker_init(void) lp_ticker_inited = true; } else { - LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); - NVIC_EnableIRQ(LPTMR0_IRQn); + lp_ticker_disable_interrupt(); } } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c index 91334e9d59..96ed417f66 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c @@ -21,8 +21,6 @@ #include "fsl_rtc.h" #include "PeripheralPins.h" -extern void rtc_setup_oscillator(RTC_Type *base); - static bool rtc_time_set = false; void rtc_init(void) @@ -32,8 +30,6 @@ void rtc_init(void) RTC_GetDefaultConfig(&rtcConfig); RTC_Init(RTC, &rtcConfig); - /* Setup the RTC 32KHz oscillator */ - rtc_setup_oscillator(RTC); RTC_StartTimer(RTC); } diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h new file mode 100644 index 0000000000..2a5848611d --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h @@ -0,0 +1,396 @@ +/*! + \file gd32f30x_adc.h + \brief definitions for the ADC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_ADC_H +#define GD32F30X_ADC_H + +#include "gd32f30x.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x400U) +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define ADC2 (ADC_BASE + 0x1800U) +#endif + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< oversampling shift */ + + +/* constants definitions */ +/* adc_stat register value */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + +#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ +#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ + +/* adc_ctl1 register value */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< timer 2 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< timer 3 CC3 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< timer 7 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + +#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< timer 2 CC0 event select */ +#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< timer 1 CC2 event select */ +#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< timer 7 CC0 event select */ +#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< timer 7 TRGO event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< timer 4 CC0 event select */ +#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */ + +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ +#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< timer 1 CC0 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< timer 2 CC3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< timer 3 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< timer 7 CC3 event select */ +#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + +#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ +#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< timer 3 CC2 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< timer 7 CC1 event select */ +#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< timer 7 CC3 event select */ +#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< timer 4 TRGO event select */ +#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< timer 4 CC3 event select */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* adc_ovsampctl register value */ +#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ +#define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ + +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ + +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* ADC interrupt */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* function declarations */ +/* reset ADC */ +void adc_deinit(uint32_t adc_periph); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); + +/* configure ADC resolution */ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); + +/* configure the ADC mode */ +void adc_mode_config(uint32_t mode); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); + +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); +/* read the last ADC0 and ADC1 conversion result data in sync mode */ +uint32_t adc_sync_mode_convert_value_read(void); + +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); + +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); + +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); +#endif /* GD32F30X_ADC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h new file mode 100644 index 0000000000..ae79546051 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h @@ -0,0 +1,242 @@ +/*! + \file gd32f30x_bkp.h + \brief definitions for the BKP + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_BKP_H +#define GD32F30X_BKP_H + +#include "gd32f30x.h" + +/* BKP definitions */ +#define BKP BKP_BASE /*!< BKP base address */ + +/* registers definitions */ +#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ +#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ +#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ +#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ +#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ +#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ +#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ +#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ +#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ +#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ +#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ +#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ +#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ +#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ +#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ +#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ +#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ +#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ +#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ +#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ +#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ +#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ +#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ +#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ +#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ +#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ +#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ +#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ +#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ +#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ +#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ +#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ +#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ +#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ +#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ +#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ +#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ +#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ +#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ +#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ +#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ +#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ +#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ +#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ +#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ + +/* bits definitions */ +/* BKP_DATA */ +#define BKP_DATA BITS(0,15) /*!< backup data */ + +/* BKP_OCTL */ +#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ +#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ +#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ +#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ +#define BKP_OCTL_CCOSEL BIT(14) /*!< RTC clock output selection */ +#define BKP_OCTL_CALDIR BIT(15) /*!< RTC clock calibration direction */ + +/* BKP_TPCTL */ +#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ +#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ + +/* BKP_TPCS */ +#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ +#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ +#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ +#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ +#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ + +/* constants definitions */ +/* BKP register */ +#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) +#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) + +/* get data of BKP data register */ +#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + +/* RTC clock calibration value */ +#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* RTC output selection */ +#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ +#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ + +/* RTC clock output selection */ +#define RTC_CLOCK_DIV_64 ((uint16_t)0x0000U) /*!< RTC clock div 64 */ +#define RTC_CLOCK_DIV_1 ((uint16_t)0x4000U) /*!< RTC clock div 1 */ + +/* RTC clock calibration direction */ +#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */ +#define RTC_CLOCK_SPEED_UP ((uint16_t)0x8000U) /*!< RTC clock speed up */ + +/* tamper pin active level */ +#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ +#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ + +/* tamper flag */ +#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ + +/* tamper interrupt flag */ +#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ + +/* BKP data register number */ +typedef enum { + BKP_DATA_0 = 1, /*!< BKP data register 0 */ + BKP_DATA_1, /*!< BKP data register 1 */ + BKP_DATA_2, /*!< BKP data register 2 */ + BKP_DATA_3, /*!< BKP data register 3 */ + BKP_DATA_4, /*!< BKP data register 4 */ + BKP_DATA_5, /*!< BKP data register 5 */ + BKP_DATA_6, /*!< BKP data register 6 */ + BKP_DATA_7, /*!< BKP data register 7 */ + BKP_DATA_8, /*!< BKP data register 8 */ + BKP_DATA_9, /*!< BKP data register 9 */ + BKP_DATA_10, /*!< BKP data register 10 */ + BKP_DATA_11, /*!< BKP data register 11 */ + BKP_DATA_12, /*!< BKP data register 12 */ + BKP_DATA_13, /*!< BKP data register 13 */ + BKP_DATA_14, /*!< BKP data register 14 */ + BKP_DATA_15, /*!< BKP data register 15 */ + BKP_DATA_16, /*!< BKP data register 16 */ + BKP_DATA_17, /*!< BKP data register 17 */ + BKP_DATA_18, /*!< BKP data register 18 */ + BKP_DATA_19, /*!< BKP data register 19 */ + BKP_DATA_20, /*!< BKP data register 20 */ + BKP_DATA_21, /*!< BKP data register 21 */ + BKP_DATA_22, /*!< BKP data register 22 */ + BKP_DATA_23, /*!< BKP data register 23 */ + BKP_DATA_24, /*!< BKP data register 24 */ + BKP_DATA_25, /*!< BKP data register 25 */ + BKP_DATA_26, /*!< BKP data register 26 */ + BKP_DATA_27, /*!< BKP data register 27 */ + BKP_DATA_28, /*!< BKP data register 28 */ + BKP_DATA_29, /*!< BKP data register 29 */ + BKP_DATA_30, /*!< BKP data register 30 */ + BKP_DATA_31, /*!< BKP data register 31 */ + BKP_DATA_32, /*!< BKP data register 32 */ + BKP_DATA_33, /*!< BKP data register 33 */ + BKP_DATA_34, /*!< BKP data register 34 */ + BKP_DATA_35, /*!< BKP data register 35 */ + BKP_DATA_36, /*!< BKP data register 36 */ + BKP_DATA_37, /*!< BKP data register 37 */ + BKP_DATA_38, /*!< BKP data register 38 */ + BKP_DATA_39, /*!< BKP data register 39 */ + BKP_DATA_40, /*!< BKP data register 40 */ + BKP_DATA_41, /*!< BKP data register 41 */ +} bkp_data_register_enum; + +/* function declarations */ +/* reset BKP registers */ +void bkp_deinit(void); +/* write BKP data register */ +void bkp_write_data(bkp_data_register_enum register_number, uint16_t data); +/* read BKP data register */ +uint16_t bkp_read_data(bkp_data_register_enum register_number); + +/* RTC related functions */ +/* enable RTC clock calibration output */ +void bkp_rtc_calibration_output_enable(void); +/* disable RTC clock calibration output */ +void bkp_rtc_calibration_output_disable(void); +/* enable RTC alarm or second signal output */ +void bkp_rtc_signal_output_enable(void); +/* disable RTC alarm or second signal output */ +void bkp_rtc_signal_output_disable(void); +/* RTC output selection */ +void bkp_rtc_output_select(uint16_t outputsel); +/* RTC clock output selection */ +void bkp_rtc_clock_output_select(uint16_t clocksel); +/* RTC clock calibration direction */ +void bkp_rtc_clock_calibration_direction(uint16_t direction); +/* set RTC clock calibration value */ +void bkp_rtc_calibration_value_set(uint8_t value); + +/* tamper pin related functions */ +/* enable tamper pin detection */ +void bkp_tamper_detection_enable(void); +/* disable tamper pin detection */ +void bkp_tamper_detection_disable(void); +/* set tamper pin active level */ +void bkp_tamper_active_level_set(uint16_t level); +/* enable tamper pin interrupt */ +void bkp_tamper_interrupt_enable(void); +/* disable tamper pin interrupt */ +void bkp_tamper_interrupt_disable(void); + +/* flag functions */ +/* get BKP flag state */ +FlagStatus bkp_flag_get(uint16_t flag); +/* clear BKP flag state */ +void bkp_flag_clear(uint16_t flag); +/* get BKP interrupt flag state */ +FlagStatus bkp_interrupt_flag_get(uint16_t flag); +/* clear BKP interrupt flag state */ +void bkp_interrupt_flag_clear(uint16_t flag); + +#endif /* GD32F30X_BKP_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h new file mode 100644 index 0000000000..e351cdf8bd --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h @@ -0,0 +1,701 @@ +/*! + \file gd32f30x_can.h + \brief definitions for the CAN + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_CAN_H +#define GD32F30X_CAN_H + +#include "gd32f30x.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive fifo mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD BITS(0,31) /*!< filter data */ + +/* consts definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum { + /* flags in TSTAT register */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +} can_flag_enum; + +/* CAN interrupt flags */ +typedef enum { + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ +} can_interrupt_flag_enum; + +/* CAN initiliaze parameters struct */ +typedef struct { + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus auto_retrans; /*!< automatic retransmission mode */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +} can_parameter_struct; + +/* CAN transmit message struct */ +typedef struct { + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +} can_trasnmit_message_struct; + +/* CAN receive message struct */ +typedef struct { + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters struct */ +typedef struct { + uint16_t filter_list_high; /*!< filter list number high bits*/ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +} can_filter_parameter_struct; + +/* CAN errors */ +typedef enum { + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +} can_error_enum; + +/* transmit states */ +typedef enum { + CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ +} can_transmit_state_enum; + +/* CAN baudrate prescaler*/ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1*/ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2*/ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width*/ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode*/ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number*/ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier*/ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier*/ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier*/ +#define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) + +/* receive mailbox standrad identifier*/ +#define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) + +/* receive data length */ +#define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) + +/* the index of the filter by which the frame is passed */ +#define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 0 */ +#define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 1 */ +#define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 2 */ +#define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 3 */ +#define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* receive data byte 4 */ +#define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* receive data byte 5 */ +#define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) + +/* receive data byte 6 */ +#define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) + +/* receive data byte 7 */ +#define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive fifo */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive fifo */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN */ +#ifdef GD_MBED_USED +ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); +#else +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); +#endif +/* CAN filter init */ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); + +/* set can1 fliter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time triggle mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time triggle mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); +/* CAN release fifo */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32F30X_CAN_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h new file mode 100644 index 0000000000..2404bb3e85 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h @@ -0,0 +1,80 @@ +/*! + \file gd32f30x_crc.h + \brief definitions for the CRC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_CRC_H +#define GD32F30X_CRC_H + +#include "gd32f30x.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register to the value of initializaiton data register */ +void crc_data_register_reset(void); +/* read the data register */ +uint32_t crc_data_register_read(void); + +/* read the free data register */ +uint8_t crc_free_data_register_read(void); +/* write the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* CRC calculate a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* CRC calculate a 32-bit data array */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32F30X_CRC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h new file mode 100644 index 0000000000..183209f208 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h @@ -0,0 +1,186 @@ +/*! + \file gd32f30x_ctc.h + \brief definitions for the CTC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_CTC_H +#define GD32F30X_CTC_H + +#include "gd32f30x.h" + +/* CTC definitions */ +#define CTC CTC_BASE + +/* registers definitions */ +#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ +#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ +#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ +#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ + +/* bits definitions */ +/* CTC_CTL0 */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ +#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ +#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ +#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ +#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ +#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ + +/* CTC_CTL1 */ +#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ +#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + +/* CTC_STAT */ +#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ +#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ +#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ +#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ +#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ +#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ +#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ +#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + +/* CTC_INTC */ +#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ +#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ +#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ +#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ + +/* constants definitions */ +/* hardware automatically trim mode definitions */ +#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ +#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ + +/* reference signal source polarity definitions */ +#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ +#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + +/* reference signal source selection definitions */ +#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ +#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ +#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBDSOF or USBFSSOF selected */ + +/* reference signal source prescaler definitions */ +#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ +#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ +#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ +#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ +#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ +#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ +#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ +#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ + +/* CTC interrupt enable definitions */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ + +/* CTC interrupt source definitions */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ + +/* CTC flag definitions */ +#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ +#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ +#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ +#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ +#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ + +/* function declarations */ +/* reset ctc clock trim controller */ +void ctc_deinit(void); + +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t ctc_interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t ctc_interrupt); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t ctc_interrupt); + +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t ctc_flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t ctc_flag); + +/* configure the IRC48M trim value */ +void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value); +/* generate software reference source sync pulse */ +void ctc_software_refsource_pulse_generate(void); +/* configure hardware automatically trim mode */ +void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode); + +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); + +/* configure reference signal source polarity */ +void ctc_refsource_polarity_config(uint32_t ctc_polarity); +/* select reference signal source */ +void ctc_refsource_signal_select(uint32_t ctc_refs); +/* configure reference signal source prescaler */ +void ctc_refsource_prescaler_config(uint32_t ctc_prescaler); +/* configure clock trim base limit value */ +void ctc_clock_limit_value_config(uint8_t ctc_limit_value); +/* configure CTC counter reload value */ +void ctc_counter_reload_value_config(uint16_t ctc_reload_value); + +/* read CTC counter capture value when reference sync pulse occurred */ +uint16_t ctc_counter_capture_value_read(void); +/* read CTC trim counter direction when reference sync pulse occurred */ +FlagStatus ctc_counter_direction_read(void); +/* read CTC counter reload value */ +uint16_t ctc_counter_reload_value_read(void); +/* read the IRC48M trim value */ +uint8_t ctc_irc48m_trim_value_read(void); + +#endif /* GD32F30X_CTC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h new file mode 100644 index 0000000000..8a83872026 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h @@ -0,0 +1,245 @@ +/*! + \file gd32f30x_dac.h + \brief definitions for the DAC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_DAC_H +#define GD32F30X_DAC_H + +#include "gd32f30x.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 0U +#define DAC1 1U + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#elif defined(GD32F30X_CL) +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ + +/* function declarations */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); + +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); + +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); + +#endif /* GD32F30X_DAC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h new file mode 100644 index 0000000000..bf1c6ca01c --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h @@ -0,0 +1,143 @@ +/*! + \file gd32f30x_dbg.h + \brief definitions for the DBG + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_DBG_H +#define GD32F30X_DBG_H + +#include "gd32f30x.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL0 */ +#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ +#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ +#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL0_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL0_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL0_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL0_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL0_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL0_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F30X_CL +#define DBG_CTL0_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD +#define DBG_CTL0_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ +#define DBG_CTL0_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ +#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ +#define DBG_CTL0_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ +#define DBG_CTL0_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ +#define DBG_CTL0_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F30X_HD */ + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ + +typedef enum { + DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ + DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ + DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ + DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ +#ifdef GD32F30X_CL + DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD + DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ + DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ +#endif /* GD32F30X_HD */ +} dbg_periph_enum; + +#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) +#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ +#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ +#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ +#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ + +/* function declarations */ +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +/* enable trace pin assignment */ +void dbg_trace_pin_enable(void); +/* disable trace pin assignment */ +void dbg_trace_pin_disable(void); +/* set trace pin mode */ +void dbg_trace_pin_mode_set(uint32_t trace_mode); + +#endif /* GD32F30X_DBG_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h new file mode 100644 index 0000000000..dc378349e4 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h @@ -0,0 +1,288 @@ +/*! + \file gd32f30x_dma.h + \brief definitions for the DMA + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_DMA_H +#define GD32F30X_DMA_H + +#include "gd32f30x.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL, x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT,x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR,x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum { + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ + DMA_CH5, /*!< DMA Channel5 */ + DMA_CH6 /*!< DMA Channel6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct { + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + +} dma_parameter_struct; + +#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ +/* circular mode */ +#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */ +#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ + +/* memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) +#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ + + + +/* function declarations */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +#ifdef GD_MBED_USED +/* initialize DMA channel */ +void dma_para_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct); +#else +/* initialize DMA channel */ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct); +#endif +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA Memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); + +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); + +#endif /* GD32F30X_DMA_H */ + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h new file mode 100644 index 0000000000..2c8a931092 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h @@ -0,0 +1,1673 @@ +/*! + \file gd32f30x_enet.h + \brief definitions for the ENET + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_ENET_H +#define GD32F30X_ENET_H + +#include "gd32f30x.h" +#include + +#define IF_USE_EXTERNPHY_LIB 0 +#if (1 == IF_USE_EXTERNPHY_LIB) +#include "phy.h" +#endif + +#ifndef ENET_RXBUF_NUM +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ +#endif + +#ifndef ENET_TXBUF_NUM +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ +#endif + +#ifndef ENET_RXBUF_SIZE +#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ +#endif + +#ifndef ENET_TXBUF_SIZE +#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ +#endif + +/* #define SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* #define USE_DELAY */ + +#ifndef _PHY_H_ +#define DP83848 0 +#define LAN8700 1 +#define PHY_TYPE DP83848 + +#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ + +/* PHY read write timeouts */ +#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ +#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ + +/* PHY delay */ +#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ +#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ + +/* PHY register address */ +#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ +#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ + +/* PHY basic control register */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ + +#if(PHY_TYPE == LAN8700) +#define PHY_SR 31U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ +#elif(PHY_TYPE == DP83848) +#define PHY_SR 16U /*!< tranceiver status register */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ +#endif /* PHY_TYPE */ + +#endif /* _PHY_H_ */ + + +/* ENET definitions */ +#define ENET ENET_BASE + +/* registers definitions */ +#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_DBG REG32((ENET) + 0x34U) /*!< ethernet MAC debug register */ +#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ +#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ + +#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ + +#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ +#define ENET_PTP_TSF REG32((ENET) + 0x728U) /*!< ethernet PTP time stamp flag register */ +#define ENET_PTP_PPSCTL REG32((ENET) + 0x72CU) /*!< ethernet PTP PPS control register */ + +#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ +#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ +#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ +#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ +#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ +#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ +#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ +#define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ +#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ +#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ + +/* bits definitions */ +/* ENET_MAC_CFG */ +#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ +#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ +#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ +#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ +#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ +#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ +#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ +#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ +#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ +#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ +#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ +#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ +#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ +#define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ + +/* ENET_MAC_FRMF */ +#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ +#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + +/* ENET_MAC_HLH */ +#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ + +/* ENET_MAC_HLL */ +#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ + +/* ENET_MAC_PHY_CTL */ +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + +/* ENET_MAC_PHY_DATA */ +#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ + +/* ENET_MAC_FCTL */ +#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ +#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ +#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ +#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ +#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ + +/* ENET_MAC_VLT */ +#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ +#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ + +/* ENET_MAC_RWFF */ +#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ + +/* ENET_MAC_WUM */ +#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ +#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ +#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ +#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ +#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ +#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ +#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ + +/* ENET_MAC_DBG */ +#define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ +#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ +#define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ +#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ +#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ +#define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ +#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ +#define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ +#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ +#define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ +#define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ +#define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ + +/* ENET_MAC_INTF */ +#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ +#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ +#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ +#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ +#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ + +/* ENET_MAC_INTMSK */ +#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ +#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ + +/* ENET_MAC_ADDR0H */ +#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ +#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ + +/* ENET_MAC_ADDR0L */ +#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ + +/* ENET_MAC_ADDR1H */ +#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR1L */ +#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ + +/* ENET_MAC_ADDR2H */ +#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ +#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR2L */ +#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ + +/* ENET_MAC_ADDR3H */ +#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ +#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ +#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ + +/* ENET_MAC_ADDR3L */ +#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ + +/* ENET_MAC_FCTH */ +#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ +#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ + +/* ENET_MSC_CTL */ +#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ +#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ +#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ +#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ +#define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */ +#define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */ + +/* ENET_MSC_RINTF */ +#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ +#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ +#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ + +/* ENET_MSC_TINTF */ +#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ +#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ +#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ + +/* ENET_MSC_RINTMSK */ +#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ +#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ +#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ + +/* ENET_MSC_TINTMSK */ +#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ +#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ + +/* ENET_MSC_SCCNT */ +#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ + +/* ENET_MSC_MSCCNT */ +#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ + +/* ENET_MSC_TGFCNT */ +#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ + +/* ENET_MSC_RFCECNT */ +#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ + +/* ENET_MSC_RFAECNT */ +#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ + +/* ENET_MSC_RGUFCNT */ +#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ + +/* ENET_PTP_TSCTL */ +#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ +#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ +#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ +#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ +#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ +#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ +#define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */ +#define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */ +#define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */ +#define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */ +#define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */ +#define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ +#define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ +#define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ +#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ +#define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ + +/* ENET_PTP_SSINC */ +#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ + +/* ENET_PTP_TSH */ +#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ + +/* ENET_PTP_TSL */ +#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ +#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ + +/* ENET_PTP_TSUH */ +#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ + +/* ENET_PTP_TSUL */ +#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ +#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ + +/* ENET_PTP_TSADDEND */ +#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ + +/* ENET_PTP_ETH */ +#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ + +/* ENET_PTP_ETL */ +#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ + +/* ENET_PTP_TSF */ +#define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ +#define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ + +/* ENET_PTP_PPSCTL */ +#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ + +/* ENET_DMA_BCTL */ +#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ +#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ +#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ +#define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ +#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ +#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ +#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ +#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ +#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ +#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ +#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ +#define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ + +/* ENET_DMA_TPEN */ +#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ + +/* ENET_DMA_RPEN */ +#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ + +/* ENET_DMA_RDTADDR */ +#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ + +/* ENET_DMA_TDTADDR */ +#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ + +/* ENET_DMA_STAT */ +#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ +#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ +#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ +#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ +#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ +#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ +#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ +#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ +#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ +#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ +#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ +#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ +#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ +#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ +#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ +#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ +#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ +#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ +#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ +#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ +#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ + +/* ENET_DMA_CTL */ +#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ +#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ +#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ +#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ +#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ +#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ +#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ +#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ +#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ +#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ +#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ +#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ + +/* ENET_DMA_INTEN */ +#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ +#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ +#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ +#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ +#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ +#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ +#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ +#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ +#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ +#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ +#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ +#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ +#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ +#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ + +/* ENET_DMA_MFBOCNT */ +#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ +#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ + +/* ENET_DMA_RSWDC */ +#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ + +/* ENET_DMA_CTDADDR */ +#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ + +/* ENET_DMA_CRDADDR */ +#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ + +/* ENET_DMA_CTBADDR */ +#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ + +/* ENET_DMA_CRBADDR */ +#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ + +/* ENET DMA Tx descriptor TDES0 */ +#define ENET_TDES0_DB BIT(0) /*!< deferred */ +#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ +#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ +#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ +#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ +#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ +#define ENET_TDES0_LCO BIT(9) /*!< late collision */ +#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ +#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ +#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ +#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ +#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ +#define ENET_TDES0_ES BIT(15) /*!< error summary */ +#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ +#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ +#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ +#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ +#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ +#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ +#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ +#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ +#define ENET_TDES0_FSG BIT(28) /*!< first segment */ +#define ENET_TDES0_LSG BIT(29) /*!< last segment */ +#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ +#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ + +/* ENET DMA Tx descriptor TDES1 */ +#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ +#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ + +/* ENET DMA Tx descriptor TDES2 */ +#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES3 */ +#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Tx descriptor TDES6 */ +#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ + +/* ENET DMA Tx descriptor TDES7 */ +#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* ENET DMA Rx descriptor RDES0 */ +#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ +#define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */ +#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ +#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ +#define ENET_RDES0_RERR BIT(3) /*!< receive error */ +#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ +#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ +#define ENET_RDES0_LCO BIT(6) /*!< late collision */ +#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ +#define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ +#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ +#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ +#define ENET_RDES0_LERR BIT(12) /*!< length error */ +#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ +#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ +#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ +#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ +#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ +#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ + +/* ENET DMA Rx descriptor RDES1 */ +#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ +#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ +#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ +#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ +#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ + +/* ENET DMA Rx descriptor RDES2 */ +#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ + +/* ENET DMA Rx descriptor RDES3 */ +#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* ENET DMA Rx descriptor RDES4 */ +#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ +#define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ +#define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ +#define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ +#define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ +#define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ +#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ +#define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ +#define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ + +/* ENET DMA Rx descriptor RDES6 */ +#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ + +/* ENET DMA Rx descriptor RDES7 */ +#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* constants definitions */ +/* define bit position and its register index offset */ +#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) +#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* ENET clock range judgement */ +#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) + +/* define MAC address configuration and reference address */ +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) +#define ENET_ADDRH_BASE ((ENET) + 0x40U) +#define ENET_ADDRL_BASE ((ENET) + 0x44U) +#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) + +/* register offset */ +#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ + +#define PTP_TSF_REG_OFFSET 0x0728U /*!< PTP time stamp flag register offset */ + +#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ + +/* ENET status flag get */ +typedef enum { + /* ENET_MAC_WUM register */ + ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + /* ENET_MAC_FCTL register */ + ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ + /* ENET_MAC_INTF register */ + ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_PTP_TSF register */ + ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ + ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ + ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ + ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ + ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +} enet_flag_enum; + +/* ENET stutus flag clear */ +typedef enum { + /* ENET_DMA_STAT register */ + ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +} enet_flag_clear_enum; + +/* ENET interrupt enable/disable */ +typedef enum { + /* ENET_MAC_INTMSK register */ + ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ + ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ + /* ENET_MSC_RINTMSK register */ + ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ + ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ + ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ + /* ENET_MSC_TINTMSK register */ + ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ + ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ + ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ + /* ENET_DMA_INTEN register */ + ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ + ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ + ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ + ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ + ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ + ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ + ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ + ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ + ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ + ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ + ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ + ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ + ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ + ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ + ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ +} enet_int_enum; + +/* ENET interrupt flag get */ +typedef enum { + /* ENET_MAC_INTF register */ + ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ + ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ + ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ + ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ + ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ + /* ENET_MSC_RINTF register */ + ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ + ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ + ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ + /* ENET_MSC_TINTF register */ + ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ + ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ + ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ + ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ +} enet_int_flag_enum; + +/* ENET interrupt flag clear */ +typedef enum { + /* ENET_DMA_STAT register */ + ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ + ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ + ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ + ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ + ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ + ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ + ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ + ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ + ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ + ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ + ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ + ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ + ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ + ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ + ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ +} enet_int_flag_clear_enum; + +/* current RX/TX descriptor/buffer/descriptor table address get */ +typedef enum { + ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ + ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ + ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ + ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ + ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ + ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ +} enet_desc_reg_enum; + +/* MAC statistics counter get */ +typedef enum { + ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ + ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ + ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ + ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ + ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ + ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ +} enet_msc_counter_enum; + +/* function option, used for ENET initialization */ +typedef enum { + FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ + DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ + DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ + DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ + STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ + DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ + VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ + FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ + HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ + HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ + FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ + HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ + TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ + INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ +} enet_option_enum; + +/* phy mode and mac loopback configurations */ +typedef enum { + ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ + ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ + ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD, /*!< 100Mbit/s, half-duplex */ + ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ + ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ + ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ +} enet_mediamode_enum; + +/* IP frame checksum function */ +typedef enum { + ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ + ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ + ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO | ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped */ +} enet_chksumconf_enum; + +/* received frame filter function */ +typedef enum { + ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ + ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ + ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ + ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ +} enet_frmrecept_enum; + +/* register group value get */ +typedef enum { + ALL_MAC_REG = 0, /*!< MAC register group */ + ALL_MSC_REG = 22, /*!< MSC register group */ + ALL_PTP_REG = 33, /*!< PTP register group */ + ALL_DMA_REG = 44, /*!< DMA register group */ +} enet_registers_type_enum; + +/* dma direction select */ +typedef enum { + ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ + ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ +} enet_dmadirection_enum; + +/* PHY operation direction select */ +typedef enum { + ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ + ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ +} enet_phydirection_enum; + +/* register operation direction select */ +typedef enum { + ENET_REG_READ, /*!< read register */ + ENET_REG_WRITE /*!< write register */ +} enet_regdirection_enum; + +/* ENET MAC addresses */ +typedef enum { + ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ + ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ + ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ + ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ +} enet_macaddress_enum; + +/* descriptor information */ +typedef enum { + TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ + TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ + RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ + RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ + RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ + RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ +} enet_descstate_enum; + +/* MSC counters preset mode */ +typedef enum { + ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ + ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ + ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ +} enet_msc_preset_enum; + +/* structure for initialization of the ENET */ +typedef struct { + uint32_t option_enable; /*!< select which function to configure */ + uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ + uint32_t dma_maxburst; /*!< DMA max burst related parameters */ + uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ + uint32_t store_forward_mode; /*!< store forward mode related parameters */ + uint32_t dma_function; /*!< DMA control related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t flow_control; /*!< flow control related parameters */ + uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ + uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ + uint32_t framesfilter_mode; /*!< frame filter control related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t timer_config; /*!< frame timer related parameters */ + uint32_t interframegap; /*!< inter frame gap related parameters */ +} enet_initpara_struct; + +/* structure for ENET DMA desciptors */ +typedef struct { + uint32_t status; /*!< status */ + uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ + uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ + uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + uint32_t extended_status; /*!< extended status */ + uint32_t reserved; /*!< reserved */ + uint32_t timestamp_low; /*!< timestamp low */ + uint32_t timestamp_high; /*!< timestamp high */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +} enet_descriptors_struct; + +/* structure of PTP system time */ +typedef struct { + uint32_t second; /*!< second of system time */ + uint32_t nanosecond; /*!< nanosecond of system time */ + uint32_t sign; /*!< sign of system time */ +} enet_ptp_systime_struct; + +/* mac_cfg register value */ +#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ +#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ +#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ +#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ + +#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ +#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ +#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ +#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ + +#define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ +#define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */ + +#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ +#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ + +#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ +#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ + +#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ +#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ + +#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ +#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ + +#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ +#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ + +#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ +#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ + +#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ +#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ + +#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ +#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ + +#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ +#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ + +#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ +#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ +#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ + +#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ +#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ + +/* mac_frmf register value */ +#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ +#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ +#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ +#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ +#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ + +#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ +#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ + +#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ +#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ +#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ +#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ +#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ + +#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ +#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ + +#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ +#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ + +#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ +#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ + +#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ +#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ +#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ +#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ +#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ +#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ +#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ + +#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ +#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ +#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ +#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ + +/* mac_phy_ctl register value */ +#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ +#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ +#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ + +#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ + +#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ + +/* mac_phy_data register value */ +#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ + +/* mac_fctl register value */ +#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ +#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ +#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ +#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ + +#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ +#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ + +#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ +#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ + +#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ +#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ +#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ + +#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ +#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ + +#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ +#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ + +#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ +/* mac_vlt register value */ +#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + +#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ +#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ + +/* mac_wum register value */ +#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ +#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ +#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + +/* mac_dbg register value */ +#define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ +#define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ +#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ +#define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ +#define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ +#define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ +#define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ +#define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ +#define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ +#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ +#define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ +#define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ + +#define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */ + +#define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */ + +#define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */ + +#define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */ + +#define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ + +/* mac_addr0h register value */ +#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ + +/* mac_addrxh register value, x = 1,2,3 */ +#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ + +#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ +#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ +#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ +#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ +#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ + +#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ +#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + +/* mac_fcth register value */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ +#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ +#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ +#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ +#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ +#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ +#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ + +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ +#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ +#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ +#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ + +/* msc_ctl register value */ +#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ +#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ +#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ + +/* ptp_tsctl register value */ +#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ + +#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ +#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ +#define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */ +#define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */ +#define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */ +#define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */ +#define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ + +/* ptp_ssinc register value */ +#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ + +/* ptp_tsl register value */ +#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ + +#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ +#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ + +#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ + +/* ptp_tsul register value */ +#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ + +#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ + +/* ptp_ppsctl register value */ +#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ +#define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ +#define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ +#define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ +#define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */ +#define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */ +#define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */ +#define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */ +#define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */ +#define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */ +#define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */ +#define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */ +#define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */ +#define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */ +#define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */ +#define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */ +#define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ + +/* dma_bctl register value */ +#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ +#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + +#define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ +#define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ + +#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ +#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ +#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ +#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ +#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ +#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ +#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ +#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ + +#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ +#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ +#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ +#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ +#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ +#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ +#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ +#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ +#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ +#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ + +#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ +#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ + +#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ +#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ + +#define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */ +#define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */ + +/* dma_stat register value */ +#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ +#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ +#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ +#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ +#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ +#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ +#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ + +#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ +#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ +#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ +#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ +#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ +#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ +#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ + +#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ +#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ +#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ +#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ + +/* dma_ctl register value */ +#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ +#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ +#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ +#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ + +#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ +#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ +#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ +#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ +#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ +#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ +#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ +#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ +#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ + +#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ +#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ + +#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ +#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ + +#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ +#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ + +#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ +#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ + +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ + +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ + +#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ +#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ +#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ + +/* dma_mfbocnt register value */ +#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ + +#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ + +/* dma_rswdc register value */ +#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ + +/* dma tx descriptor tdes0 register value */ +#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ +#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ + +#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ + +/* dma tx descriptor tdes1 register value */ +#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ + +#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ + +/* dma rx descriptor rdes0 register value */ +#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ +#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ + +/* dma rx descriptor rdes1 register value */ +#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ + +#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ + +#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ + +/* dma rx descriptor rdes4 register value */ +#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ +#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ + +#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ +#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ + +/* ENET register mask value */ +#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ +#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ +#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ +#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ +#define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#define ETH_DMATXDESC_SIZE 0x20U /*!< TxDMA enhanced descriptor size */ +#define ETH_DMARXDESC_SIZE 0x20U /*!< RxDMA enhanced descriptor size */ +#else +#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + +typedef enum { + ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ + ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ + ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ + ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ + ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ + ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU | BIT(31)), /*!< the system timestamp uses the fine method for updating */ + ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ + ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ + ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ + ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV | BIT(31)), /*!< version 2 */ + ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ + ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN | BIT(31)), /*!< only event type messages are taken snapshot */ + ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ + ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN | BIT(31)), /*!< snapshot is only take for master node message */ + ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ +} enet_ptp_function_enum; + + +/* ENET remote wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ + +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ + +/* ENET delay timeout */ +#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ +#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ + + + +/* function declarations */ +/* main function */ +/* deinitialize the ENET, and reset structure parameters for ENET initialization */ +void enet_deinit(void); +/* configure the parameters which are usually less cared for initialization */ +void enet_initpara_config(enet_option_enum option, uint32_t para); +/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); +/* reset all core internal registers located in CLK_TX and CLK_RX */ +ErrStatus enet_software_reset(void); +/* check receive frame valid and return frame size */ +uint32_t enet_rxframe_size_get(void); +/* initialize the dma tx/rx descriptors's parameters in chain mode */ +void enet_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma tx/rx descriptors's parameters in ring mode */ +void enet_descriptors_ring_init(enet_dmadirection_enum direction); +/* handle current received frame data to application buffer */ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); +/* handle current received frame but without data copy to application buffer */ +#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) +/* handle application buffer data to transmit it */ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); +/* handle current transmit frame but without data copy from application buffer */ +#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) +/* configure the transmit IP frame checksum offload calculation and insertion */ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); +/* ENET Tx and Rx function enable (include MAC and DMA module) */ +void enet_enable(void); +/* ENET Tx and Rx function disable (include MAC and DMA module) */ +void enet_disable(void); +/* configure MAC address */ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); +/* get MAC address */ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); + +/* get the ENET MAC/MSC/PTP/DMA status flag */ +FlagStatus enet_flag_get(enet_flag_enum enet_flag); +/* clear the ENET DMA status flag */ +void enet_flag_clear(enet_flag_clear_enum enet_flag); +/* enable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_enable(enet_int_enum enet_int); +/* disable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_disable(enet_int_enum enet_int); +/* get ENET MAC/MSC/DMA interrupt flag */ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); +/* clear ENET DMA interrupt flag */ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); + +/* MAC function */ +/* ENET Tx function enable (include MAC and DMA module) */ +void enet_tx_enable(void); +/* ENET Tx function disable (include MAC and DMA module) */ +void enet_tx_disable(void); +/* ENET Rx function enable (include MAC and DMA module) */ +void enet_rx_enable(void); +/* ENET Rx function disable (include MAC and DMA module) */ +void enet_rx_disable(void); +/* put registers value into the application buffer */ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); +/* get the enet debug status from the debug register */ +uint32_t enet_debug_status_get(uint32_t mac_debug); +/* enable the MAC address filter */ +void enet_address_filter_enable(enet_macaddress_enum mac_addr); +/* disable the MAC address filter */ +void enet_address_filter_disable(enet_macaddress_enum mac_addr); +/* configure the MAC address filter */ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); +/* PHY interface configuration (configure SMI clock and reset PHY chip) */ +ErrStatus enet_phy_config(void); +/* write to/read from a PHY register */ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); +/* enable the loopback function of phy chip */ +ErrStatus enet_phyloopback_enable(void); +/* disable the loopback function of phy chip */ +ErrStatus enet_phyloopback_disable(void); +/* enable ENET forward feature */ +void enet_forward_feature_enable(uint32_t feature); +/* disable ENET forward feature */ +void enet_forward_feature_disable(uint32_t feature); +/* enable ENET fliter feature */ +void enet_fliter_feature_enable(uint32_t feature); +/* disable ENET fliter feature */ +void enet_fliter_feature_disable(uint32_t feature); + +/* flow control function */ +/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ +ErrStatus enet_pauseframe_generate(void); +/* configure the pause frame detect type */ +void enet_pauseframe_detect_config(uint32_t detect); +/* configure the pause frame parameters */ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); +/* configure the threshold of the flow control(deactive and active threshold) */ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); +/* enable ENET flow control feature */ +void enet_flowcontrol_feature_enable(uint32_t feature); +/* disable ENET flow control feature */ +void enet_flowcontrol_feature_disable(uint32_t feature); + +/* DMA function */ +/* get the dma transmit/receive process state */ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +/* poll the dma transmission/reception enable */ +void enet_dmaprocess_resume(enet_dmadirection_enum direction); +/* check and recover the Rx process */ +void enet_rxprocess_check_recovery(void); +/* flush the ENET transmit fifo, and wait until the flush operation completes */ +ErrStatus enet_txfifo_flush(void); +/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); +/* get the Tx or Rx descriptor information */ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); +/* get the number of missed frames during receiving */ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); + +/* descriptor function */ +/* get the bit flag of ENET dma descriptor */ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); +/* set the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); +/* clear the bit flag of ENET dma tx descriptor */ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); +/* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time); +/* drop current receive frame */ +void enet_rxframe_drop(void); +/* enable DMA feature */ +void enet_dma_feature_enable(uint32_t feature); +/* disable DMA feature */ +void enet_dma_feature_disable(uint32_t feature); + + +/* special enhanced mode function */ +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/* get the bit of extended status flag in ENET DMA descriptor */ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); +/* configure descriptor to work in enhanced mode */ +void enet_desc_select_enhanced_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction); +/* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction); +/* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr)) + +#else + +/* configure descriptor to work in normal mode */ +void enet_desc_select_normal_mode(void); +/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); +/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); +/* handle current received frame but without data copy to application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) +/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); +/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ +#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/* WUM function */ +/* wakeup frame filter register pointer reset */ +void enet_wum_filter_register_pointer_reset(void); +/* set the remote wakeup frame registers */ +void enet_wum_filter_config(uint32_t pdata[]); +/* enable wakeup management features */ +void enet_wum_feature_enable(uint32_t feature); +/* disable wakeup management features */ +void enet_wum_feature_disable(uint32_t feature); + +/* MSC function */ +/* reset the MAC statistics counters */ +void enet_msc_counters_reset(void); +/* enable the MAC statistics counter features */ +void enet_msc_feature_enable(uint32_t feature); +/* disable the MAC statistics counter features */ +void enet_msc_feature_disable(uint32_t feature); +/* configure MAC statistics counters preset mode */ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode); +/* get MAC statistics counter */ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); + +/* PTP function */ +/* change subsecond to nanosecond */ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond); +/* change nanosecond to subsecond */ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond); +/* enable the PTP features */ +void enet_ptp_feature_enable(uint32_t feature); +/* disable the PTP features */ +void enet_ptp_feature_disable(uint32_t feature); +/* configure the PTP timestamp function */ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); +/* configure the PTP system time subsecond increment value */ +void enet_ptp_subsecond_increment_config(uint32_t subsecond); +/* adjusting the PTP clock frequency only in fine update mode */ +void enet_ptp_timestamp_addend_config(uint32_t add); +/* initializing or adding/subtracting to second of the PTP system time */ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); +/* configure the PTP expected target time */ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); +/* get the PTP current system time */ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); +/* configure the PPS output frequency */ +void enet_ptp_pps_output_frequency_config(uint32_t freq); +/* configure and start PTP timestamp counter */ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg); +/* adjust frequency in fine method by configure addend register */ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); +/* update system time in coarse method */ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); +/* set system time in fine method */ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct); +/* get the ptp flag status */ +FlagStatus enet_ptp_flag_get(uint32_t flag); + +/* internal function */ +/* reset the ENET initpara struct, call it before using enet_initpara_config() */ +void enet_initpara_reset(void); + +#endif /* GD32F30X_ENET_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h new file mode 100644 index 0000000000..85acd6d6fa --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h @@ -0,0 +1,440 @@ +/*! + \file gd32f30x_exmc.h + \brief definitions for the EXMC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_EXMC_H +#define GD32F30X_EXMC_H + +#include "gd32f30x.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ + +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */ + +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */ + +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */ + +/* NAND/PC card */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */ + +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */ + +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ + +/* bits definitions */ +/* EXMC_SNCTLx,x=0..3 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ +#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ + +/* EXMC_SNTCFGx,x=0..3 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_SNWTCFGx,x=0..3 */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ + +/* EXMC_NPCTLx,x=1..3 */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ + +/* EXMC_NPINTENx,x=1..3 */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ + +/* EXMC_NPCTCFGx,x=1..3 */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ + +/* EXMC_NPATCFGx,x=1..3 */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ + +/* EXMC_PIOTCFG3 */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ + +/* EXMC_NECCx,x=1,2 */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize struct */ +typedef struct { + uint32_t asyn_access_mode; /*!< asynchronous access mode */ + uint32_t syn_data_latency; /*!< configure the data latency */ + uint32_t syn_clk_division; /*!< configure the clock divide ratio */ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ +} exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize struct */ +typedef struct { + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ + uint32_t extended_mode; /*!< enable or disable the extended mode */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_config; /*!< NWAIT signal configuration */ + uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t burst_mode; /*!< enable or disable the burst mode */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct *read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing + parameters for read if the extended mode is used */ + exmc_norsram_timing_parameter_struct *write_timing; /*!< timing parameters for write when the extended mode is used */ +} exmc_norsram_parameter_struct; + +/* EXMC NAND/PC card timing initialize struct */ +typedef struct { + uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ + uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ + uint32_t waittime; /*!< configure the minimum wait time */ + uint32_t setuptime; /*!< configure the address setup time */ +} exmc_nand_pccard_timing_parameter_struct; + +/* EXMC NAND initialize struct */ +typedef struct { + uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t ecc_size; /*!< the page size for the ECC calculation */ + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ + uint32_t databus_width; /*!< the NAND flash databus width */ + uint32_t wait_feature; /*!< enables or disables the wait feature */ + exmc_nand_pccard_timing_parameter_struct *common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct *attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +} exmc_nand_parameter_struct; + +/* EXMC PC card initialize struct */ +typedef struct { + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ + uint32_t wait_feature; /*!< enables or disables the Wait feature */ + exmc_nand_pccard_timing_parameter_struct *common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct *attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ + exmc_nand_pccard_timing_parameter_struct *io_space_timing; /*!< the timing parameters for NAND flash IO space */ +} exmc_pccard_parameter_struct;; + + +/* EXMC_register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */ + +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */ + +/* CRAM page size */ +#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ +#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ +#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ +#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ +#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* asynchronous access mode */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ + +/* data latency for NOR flash */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ + +/* synchronous clock divide ratio */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ + +/* ECC size */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ + +/* ALE to RE delay */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ + +/* CLE to RE delay */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ + +/* NAND bank memory data bus width */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ + +/* EXMC NOR/SRAM write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */ + +/* EXMC NWAIT signal configuration */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ + +/* EXMC NAND/PC card bank definition */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ + +/* EXMC flag bits */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ + +/* EXMC interrupt enable bits */ +#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ +#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ +#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ + +/* EXMC interrupt flag bits */ +#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ +#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ +#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ + +/* function declarations */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t exmc_norsram_region); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_norsram_parameter_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); +/* CRAM page size configure */ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); +/* EXMC NOR/SRAM bank enable */ +void exmc_norsram_enable(uint32_t exmc_norsram_region); +/* EXMC NOR/SRAM bank disable */ +void exmc_norsram_disable(uint32_t exmc_norsram_region); + + +/* deinitialize EXMC NAND bank */ +void exmc_nand_deinit(uint32_t exmc_nand_bank); +/* initialize EXMC NAND bank */ +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_nand_parameter_init(exmc_nand_parameter_struct *exmc_nand_init_struct); +/* EXMC NAND bank enable */ +void exmc_nand_enable(uint32_t exmc_nand_bank); +/* EXMC NAND bank disable */ +void exmc_nand_disable(uint32_t exmc_nand_bank); +/* enable or disable the EXMC NAND ECC function */ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); +/* get the EXMC ECC value */ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); + +/* deinitialize EXMC PC card bank */ +void exmc_pccard_deinit(void); +/* initialize EXMC PC card bank */ +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct); +/* exmc_pccard_parameter_struct parameter initialize */ +void exmc_pccard_parameter_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct); +/* EXMC PC card bank enable */ +void exmc_pccard_enable(void); +/* EXMC PC card bank disable */ +void exmc_pccard_disable(void); + +/* check EXMC flag is set or not */ +FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag); +/* clear EXMC flag */ +void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag); +/* check EXMC flag is set or not */ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt_source); +/* clear EXMC flag */ +void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt_source); +/* enable EXMC interrupt */ +void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt_source); +/* disable EXMC interrupt */ +void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt_source); + +#endif /* GD32F30X_EXMC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h new file mode 100644 index 0000000000..0666eb00e7 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h @@ -0,0 +1,251 @@ +/*! + \file gd32f30x_exti.h + \brief definitions for the EXTI + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_EXTI_H +#define GD32F30X_EXTI_H + +#include "gd32f30x.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum { + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ +} exti_line_enum; + +/* external interrupt and event */ +typedef enum { + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +} exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum { + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ +} exti_trig_type_enum; + +/* function declarations */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); +/* enable the EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); + +#endif /* GD32F30X_EXTI_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h new file mode 100644 index 0000000000..e08dbe454f --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h @@ -0,0 +1,364 @@ +/*! + \file gd32f30x_fmc.h + \brief definitions for the FMC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_FMC_H +#define GD32F30X_FMC_H + +#include "gd32f30x.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option bytes base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ +#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ +#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ +#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ +#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ +#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ +#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ +#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ +#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ +#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ +#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ + +#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ +#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ +#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ +#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ +#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY0 */ +#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT0 */ +#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL0 */ +#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ +#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ +#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ +#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ +#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR0 */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ +#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + +/* FMC_WP */ +#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ + +/* FMC_KEY1 */ +#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ + +/* FMC_STAT1 */ +#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL1 */ +#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ +#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ +#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ +#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ +#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR1 */ +#define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* define the FMC bit position and its register index offset */ +#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) +#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) +#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) + +/* configuration register */ +#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ +#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ +#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ +#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ +#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ + +/* fmc state */ +typedef enum { + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ +} fmc_state_enum; + +/* FMC interrupt enable */ +typedef enum { + FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ + FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ + FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ + FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ +} fmc_int_enum; + +/* FMC flags */ +typedef enum { + FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ + FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ + FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ + FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ + FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ + FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ + FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ + FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ + FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ +} fmc_flag_enum; + +/* FMC interrupt flags */ +typedef enum { + FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ + FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ + FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ +} fmc_interrupt_flag_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* FMC wait state counter */ +#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + +/* option bytes software/hardware free watch dog timer */ +#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ +#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ + +/* option bytes reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ + +/* option bytes reset or not entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ + +/* option bytes boot bank value */ +#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ +#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ + +#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ + +/* OB_SPC */ +#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ +#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ + +/* OB_USER */ +#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ +#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ + +/* OB_WP0 */ +#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ + +/* OB_WP1 */ +#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ + +/* OB_WP2 */ +#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ + +/* OB_WP3 */ +#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ +#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ +#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ +#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ +#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ +#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ +#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ +#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ +#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ +#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ + +/* FMC timeout */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ + +/* FMC BANK address */ +#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ +#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ +#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* unlock the FMC bank0 operation */ +void fmc_bank0_unlock(void); +/* unlock the FMC bank1 operation */ +void fmc_bank1_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* lock the bank0 FMC operation */ +void fmc_bank0_lock(void); +/* lock the bank1 FMC operation */ +void fmc_bank1_lock(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC erase whole bank0 */ +fmc_state_enum fmc_bank0_erase(void); +/* FMC erase whole bank1 */ +fmc_state_enum fmc_bank1_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* erase the option byte */ +fmc_state_enum ob_erase(void); +/* enable write protect */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); +/* configure the option byte security protection */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* write the FMC option byte */ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); +/* program option bytes data */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get the FMC option byte user */ +uint8_t ob_user_get(void); +/* get OB_DATA in register FMC_OBSTAT */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint32_t ob_write_protection_get(void); +/* get option byte security protection code value */ +FlagStatus ob_spc_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* check flag is set or not */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC flag */ +void fmc_flag_clear(uint32_t flag); +/* get FMC interrupt flag state */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); +/* clear FMC interrupt flag state */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); +/* return the FMC bank0 state */ +fmc_state_enum fmc_bank0_state_get(void); +/* return the FMC bank1 state */ +fmc_state_enum fmc_bank1_state_get(void); +/* check FMC bank0 ready or not */ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); +/* check FMC bank1 ready or not */ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); + +#endif /* GD32F30X_FMC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h new file mode 100644 index 0000000000..b0f4301c35 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h @@ -0,0 +1,104 @@ +/*! + \file gd32f30x_fwdgt.h + \brief definitions for the FWDGT + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_FWDGT_H +#define GD32F30X_FWDGT_H + +#include "gd32f30x.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* function declarations */ +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F30X_FWDGT_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h new file mode 100644 index 0000000000..1326038b23 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h @@ -0,0 +1,532 @@ +/*! + \file gd32f30x_gpio.h + \brief definitions for the GPIO + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_GPIO_H +#define GD32F30X_GPIO_H + +#include "gd32f30x.h" + +/* GPIOx(x=A,B,C,D,E,F,G) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) +#define GPIOF (GPIO_BASE + 0x00001400U) +#define GPIOG (GPIO_BASE + 0x00001800U) + +/* AFIO definitions */ +#define AFIO AFIO_BASE + +/* registers definitions */ +/* GPIO registers definitions */ +#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ +#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ +#define GPIOx_SPD(gpiox) REG32((gpiox) + 0x3CU) /*!< GPIO port bit speed register */ + +/* AFIO registers definitions */ +#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ +#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ +#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ +#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ +#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ +#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ +#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ +#define AFIO_CPSCTL REG32(AFIO + 0x20U) /*!< IO compensation control register */ + +/* bits definitions */ +/* GPIO_CTL0 */ +#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ +#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ +#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ +#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ +#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ +#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ +#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ +#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ +#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ +#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ +#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ +#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ +#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ +#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ +#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ + +/* GPIO_CTL1 */ +#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ +#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ +#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ +#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ +#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ +#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ +#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ +#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ +#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ +#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ +#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ +#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ +#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ +#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ +#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* GPIO_SPD */ +#define GPIO_SPD_SPD0 BIT(0) /*!< pin 0 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD1 BIT(1) /*!< pin 1 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD2 BIT(2) /*!< pin 2 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD3 BIT(3) /*!< pin 3 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD4 BIT(4) /*!< pin 4 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD5 BIT(5) /*!< pin 5 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD6 BIT(6) /*!< pin 6 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD7 BIT(7) /*!< pin 7 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD8 BIT(8) /*!< pin 8 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD9 BIT(9) /*!< pin 9 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD10 BIT(10) /*!< pin 10 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD11 BIT(11) /*!< pin 11 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD12 BIT(12) /*!< pin 12 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD13 BIT(13) /*!< pin 13 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD14 BIT(14) /*!< pin 14 set very high output speed when MDx is 0b11 */ +#define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ + +/* AFIO_EC */ +#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ +#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ +#define AFIO_EC_EOE BIT(7) /*!< event output enable */ + +/* AFIO_PCF0 */ +#ifdef GD32F30X_CL +/* memory map and bit definitions for GD32F30X_CL devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ +#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ +#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ +#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ +#define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ +#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ + +#else +/* memory map and bit definitions for GD32F30X_HD devices and GD32F30X_XD devices */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_REMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ +#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ +#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ +#endif /* GD32F30X_CL */ + +/* AFIO_EXTISS0 */ +#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ +#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ +#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ +#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ + +/* AFIO_EXTISS1 */ +#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ +#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ +#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ +#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ + +/* AFIO_EXTISS2 */ +#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ +#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ +#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ +#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ + +/* AFIO_EXTISS3 */ +#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ +#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ +#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ +#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ + +/* AFIO_PCF1 */ +#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ +#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ +#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ +#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ +#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ +#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ +#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ + +/* AFIO_CPSCTL */ +#define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ +#define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* GPIO mode values set */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) +#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) + +/* GPIO mode definitions */ +#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ +#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ +#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ +#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ +#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ +#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ +#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ +#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ +#define GPIO_OSPEED_MAX ((uint8_t)0x04U) /*!< GPIO very high output speed, max speed more than 50MHz */ + +/* GPIO event output port definitions */ +#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ +#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ +#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ +#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ +#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ + +/* GPIO output port source definitions */ +#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ +#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ +#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ +#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ +#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ +#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ +#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ + +/* GPIO event output pin definitions */ +#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ +#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ +#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ +#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ +#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ +#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ +#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ +#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ +#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ +#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ +#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ +#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ +#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ +#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ +#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ +#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ + +/* GPIO output pin source definitions */ +#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ +#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ +#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ +#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ +#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ +#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ +#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ +#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ +#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ +#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ +#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ +#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ +#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ +#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ +#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ +#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO remap definitions */ +#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ +#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ +#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ +#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ +#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ +#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ +#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ +#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ +#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ +#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ +#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ +#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN partial remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN full remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#endif /* GD32F30X_HD||GD32F30X_XD */ +#if (defined(GD32F30X_CL) || defined(GD32F30X_HD)) +#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping(only for GD32F30X_CL devices and GD32F30X_HD devices) */ +#endif /* GD32F30X_CL||GD32F30X_HD */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U) /*!< ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U) /*!< ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#endif /* GD32F30X_HD||GD32F30X_XD */ +#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ +#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled and SW-DP enabled */ +#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled and SW-DP disabled */ +#ifdef GD32F30X_CL +#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping(only for GD32F30X_CL devices) */ +#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping(only for GD32F30X_CL devices) */ +#define GPIO_ENET_REMAP ((uint32_t)0x00200020U) /*!< ENET remapping(only for GD32F30X_CL devices) */ +#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping(only for GD32F30X_CL devices) */ +#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping(only for GD32F30X_CL devices) */ +#define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) */ +#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U) /*!< ethernet PTP PPS remapping(only for GD32F30X_CL devices) */ +#endif /* GD32F30X_CL */ +#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U) /*!< TIMER8 remapping */ +#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U) /*!< TIMER9 remapping */ +#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U) /*!< TIMER10 remapping */ +#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U) /*!< TIMER12 remapping */ +#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U) /*!< TIMER13 remapping */ +#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ +#define GPIO_CTC_REMAP0 ((uint32_t)0x801B0800U) /*!< CTC remapping(PD15)*/ +#define GPIO_CTC_REMAP1 ((uint32_t)0x801B1000U) /*!< CTC remapping(PF0) */ + +#ifdef GD32F30X_CL +/* ethernet MII or RMII PHY selection */ +#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ +#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ +#endif /* GD32F30X_CL */ + +/* I/O compensation cell enable/disable */ +#define GPIO_COMPENSATION_ENABLE AFIO_CPSCTL_CPS_EN /*!< I/O compensation cell is enable */ +#define GPIO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell is disable */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* reset alternate function I/O(AFIO) */ +void gpio_afio_deinit(void); +#ifdef GD_MBED_USED +/* GPIO parameter initialization */ +void gpio_para_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); +#else +void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); +#endif +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* configure GPIO pin event output */ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); +/* enable GPIO pin event output */ +void gpio_event_output_enable(void); +/* disable GPIO pin event output */ +void gpio_event_output_disable(void); + +/* select GPIO pin exti sources */ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); + +#ifdef GD32F30X_CL +/* select ethernet MII or RMII PHY */ +void gpio_ethernet_phy_select(uint32_t enet_sel); +#endif /* GD32F30X_CL */ + +/* configure GPIO pin remap */ +void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue); + +/* configure the I/O compensation cell */ +void gpio_compensation_config(uint32_t compensation); +/* check the I/O compensation cell is ready or not */ +FlagStatus gpio_compensation_flag_get(void); + +#endif /* GD32F30X_GPIO_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h new file mode 100644 index 0000000000..1ece58a0b5 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h @@ -0,0 +1,364 @@ +/*! + \file gd32f30x_i2c.h + \brief definitions for the I2C + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_I2C_H +#define GD32F30X_I2C_H + +#include "gd32f30x.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ +#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ + +/* I2Cx_FMPCFG */ +#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + +/* constants definitions */ +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* I2C dual-address mode switch */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C flag definitions */ +#define I2C_FLAG_SBSEND BIT(0) /*!< start condition sent out in master mode */ +#define I2C_FLAG_ADDSEND BIT(1) /*!< address is sent in master mode or received and matches in slave mode */ +#define I2C_FLAG_BTC BIT(2) /*!< byte transmission finishes */ +#define I2C_FLAG_ADD10SEND BIT(3) /*!< header of 10-bit address is sent in master mode */ +#define I2C_FLAG_STPDET BIT(4) /*!< etop condition detected in slave mode */ +#define I2C_FLAG_RBNE BIT(6) /*!< I2C_DATA is not Empty during receiving */ +#define I2C_FLAG_TBE BIT(7) /*!< I2C_DATA is empty during transmitting */ +#define I2C_FLAG_BERR BIT(8) /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ +#define I2C_FLAG_LOSTARB BIT(9) /*!< arbitration lost in master mode */ +#define I2C_FLAG_AERR BIT(10) /*!< acknowledge error */ +#define I2C_FLAG_OUERR BIT(11) /*!< over-run or under-run situation occurs in slave mode */ +#define I2C_FLAG_PECERR BIT(12) /*!< PEC error when receiving data */ +#define I2C_FLAG_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_FLAG_SMBALT BIT(15) /*!< SMBus alert status */ +#define I2C_FLAG_MASTER (BIT(0)|BIT(31)) /*!< a flag indicating whether I2C block is in master or slave mode */ +#define I2C_FLAG_I2CBSY (BIT(1)|BIT(31)) /*!< busy flag */ +#define I2C_FLAG_TRS (BIT(2)|BIT(31)) /*!< whether the I2C is a transmitter or a receiver */ +#define I2C_FLAG_RXGC (BIT(4)|BIT(31)) /*!< general call address (00h) received */ +#define I2C_FLAG_DEFSMB (BIT(5)|BIT(31)) /*!< default address of SMBus device */ +#define I2C_FLAG_HSTSMB (BIT(6)|BIT(31)) /*!< SMBus host header detected in slave mode */ +#define I2C_FLAG_DUMOD (BIT(7)|BIT(31)) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + +/* I2C interrupt flags */ +#define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND /*!< start condition sent out in master mode interrupt flag */ +#define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ +#define I2C_INT_FLAG_BTC I2C_FLAG_BTC /*!< byte transmission finishes */ +#define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND /*!< header of 10-bit address is sent in master mode interrupt flag */ +#define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET /*!< stop condition detected in slave mode interrupt flag */ +#define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE /*!< I2C_DATA is not Empty during receiving interrupt flag */ +#define I2C_INT_FLAG_TBE I2C_FLAG_TBE /*!< I2C_DATA is empty during transmitting interrupt flag */ +#define I2C_INT_FLAG_BERR I2C_FLAG_BERR /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ +#define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB /*!< arbitration lost in master mode interrupt flag */ +#define I2C_INT_FLAG_AERR I2C_FLAG_AERR /*!< acknowledge error interrupt flag */ +#define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR /*!< over-run or under-run situation occurs in slave mode interrupt flag */ +#define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR /*!< PEC error when receiving data interrupt flag */ +#define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO /*!< timeout signal in SMBus mode interrupt flag */ +#define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT /*!< SMBus Alert status interrupt flag */ + +/* I2C interrupt enable bit */ +#define I2C_INT_ERR I2C_CTL1_ERRIE /*!< error interrupt enable */ +#define I2C_INT_EV I2C_CTL1_EVIE /*!< event interrupt enable */ +#define I2C_INT_BUF I2C_CTL1_BUFIE /*!< buffer interrupt enable */ + +/* I2C duty cycle in fast mode or fast mode plus */ +#define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14)) +#define I2C_DTCY_2 CKCFG_DTCY(0) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 CKCFG_DTCY(1) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1) /*!< address:10 bits */ + +#ifdef GD_MBED_USED +#define SLAVE10_FIRST_BYTE(addr10) ((0xF0) | (uint8_t)((addr10 & 0x0300)>>7)) +#define SLAVE10_SECOND_BYTE(addr10) ((uint8_t)(addr10 & 0x00FF)) + +typedef enum { + I2C_MODE_NONE = 0x00U, /*!< I2C device is idle */ + I2C_MODE_MASTER = 0x10U, /*!< I2C device is in Master Mode */ + I2C_MODE_SLAVE = 0x20U /*!< I2C device is in Slave Mode */ +} i2c_mode_enum; + +/* I2C state definitions */ +#define I2C_STATE_MSK ((uint32_t)((OP_STATE_BUSY_TX | OP_STATE_BUSY_RX) & (~(uint32_t)OP_STATE_BUSY))) +#define I2C_STATE_NONE ((uint32_t)(I2C_MODE_NONE)) +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((OP_STATE_BUSY_TX & I2C_STATE_MSK) | I2C_MODE_MASTER)) +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((OP_STATE_BUSY_RX & I2C_STATE_MSK) | I2C_MODE_MASTER)) +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((OP_STATE_BUSY_TX & I2C_STATE_MSK) | I2C_MODE_SLAVE)) +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((OP_STATE_BUSY_RX & I2C_STATE_MSK) | I2C_MODE_SLAVE)) + +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_NEXT_FRAME 0x00000002U +#define I2C_FIRST_AND_LAST_FRAME 0x00000004U +#define I2C_LAST_FRAME 0x00000008U +#define I2C_NO_OPTION_FRAME 0xFFFF0000U + +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U + +#define I2C_ERROR_NONE 0x00000000U /*!< no error */ +#define I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define I2C_ERROR_LOSTARB 0x00000002U /*!< LOSTARB error */ +#define I2C_ERROR_AERR 0x00000004U /*!< AERR error */ +#define I2C_ERROR_OUERR 0x00000008U /*!< OUERR error */ +#define I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define I2C_ERROR_TIMEOUT 0x00000020U /*!< timeout Error */ + +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< timeout 25 ms */ +#endif + +/* function declarations */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); +/* SMBus type selection */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master send slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* dual-address mode switch */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); + +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* I2C DMA mode enable */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* flag indicating DMA last transfer */ +void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); + +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag); + +/* I2C PEC calculation on or off */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); +/* I2C whether to transfer PEC value */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* I2C issue alert through SMBA pin */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* I2C ARP protocol in SMBus switch */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); + +#endif /* GD32F30X_I2C_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h new file mode 100644 index 0000000000..1f634a6e4d --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h @@ -0,0 +1,93 @@ +/*! + \file gd32f30x_misc.h + \brief definitions for the MISC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_MISC_H +#define GD32F30X_MISC_H + +#include "gd32f30x.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F30X_MISC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h new file mode 100644 index 0000000000..3f836b4d65 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h @@ -0,0 +1,185 @@ +/*! + \file gd32f30x_pmu.h + \brief definitions for the PMU + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_PMU_H +#define GD32F30X_PMU_H + +#include "gd32f30x.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + +/* PMU high-driver mode switch */ +#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) +#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ + +/* PMU low-driver mode when use low power LDO */ +#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) +#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ + +/* PMU low-driver mode when use normal power LDO */ +#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) +#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ + +/* PMU low power mode ready flag definitions */ +#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ +#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* functions of low-driver mode and high-driver mode in deep-sleep mode */ +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* enable high-driver mode */ +void pmu_highdriver_mode_enable(void); +/* disable high-driver mode */ +void pmu_highdriver_mode_disable(void); +/* enable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_disable(void); +/* in deep-sleep mode, driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); + +/* set PMU mode */ +/* PMU work at sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work at deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work at standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* enable backup domain write */ +void pmu_backup_write_enable(void); +/* disable backup domain write */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag_reset); +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); + +#endif /* GD32F30X_PMU_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h new file mode 100644 index 0000000000..48b4ba96af --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h @@ -0,0 +1,1043 @@ +/*! + \file gd32f30x_rcu.h + \brief definitions for the RCU + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_RCU_H +#define GD32F30X_RCU_H + +#include "gd32f30x.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ +#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ +#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ +#elif defined(GD32F30X_CL) +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ +#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ +#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ +#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* bits definitions */ +/* RCU_CTL */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#elif defined(GD32F30X_CL) +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ +#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ +#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ +#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_CFG0 */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ +#define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ +#elif defined(GD32F30X_CL) +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ +#define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_INT */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#elif defined(GD32F30X_CL) +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ +#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ +#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ +#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ +#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ +#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ +#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ +#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ +#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ +#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ +#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ +#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ +#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#ifndef GD32F30X_CL +#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD +#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ +#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ +#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ +#endif /* GD32F30X_HD */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ +#ifndef GD32F30X_HD +#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ +#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ +#endif /* GD32F30X_HD */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#ifdef GD32F30X_CL +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#endif /* GD32F30X_CL */ +#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ +#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ +#elif defined(GD32F30X_CL) +#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ +#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ +#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ +#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ +#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ +#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ +#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ +#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ +#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ +#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ +#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ +#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#ifndef GD32F30X_CL +#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD +#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ +#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ +#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ +#endif /* GD32F30X_HD */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#ifndef GD32F30X_HD +#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ +#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ +#endif /* GD32F30X_HD */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#ifdef GD32F30X_CL +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#endif /* GD32F30X_CL */ +#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +#ifdef GD32F30X_CL +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ +#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ +#endif /* GD32F30X_CL */ + +/* RCU_CFG1 */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ +#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ +#elif defined(GD32F30X_CL) +#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ +#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ +#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ +#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ +#define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ +#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ +#define RCU_CFG1_PLL2MF_4 BIT(31) /*!< bit 5 of PLL2MF */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ + +/* RCU_ADDCTL */ +#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ +#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ +#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ +#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ + +/* RCU_ADDINT */ +#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ +#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ +#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ + +/* RCU_ADDAPB1RST */ +#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ + +/* RCU_ADDAPB1EN */ +#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ + + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +/* peripherals enable */ +#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ +#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ +#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ + +/* peripherals reset */ +#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ +#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ +#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ +#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ +#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ +#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ + +/* configuration register */ +#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ +#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum { + /* AHB peripherals */ + RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ + RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ + RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ +#elif defined(GD32F30X_CL) + RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ + RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ + RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ + RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ +#ifndef GD32F30X_HD + RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ + RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ +#endif /* GD32F30X_HD */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ +#ifdef GD32F30X_CL + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ +#endif /* GD32F30X_CL */ + RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ + + /* APB2 peripherals */ + RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ + RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ + RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ + RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ +#ifndef GD32F30X_CL + RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD + RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ + RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ + RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ +#endif /* GD32F30X_HD */ +} rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum { + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ +} rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum { + /* AHB peripherals */ +#ifdef GD32F30X_CL + RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ +#endif /* GD32F30X_CL */ + + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ +#ifndef GD32F30X_HD + RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ + RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ +#endif /* GD32F30X_HD */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ +#endif /* GD32F30X_HD and GD32F30X_XD */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ +#ifdef GD32F30X_CL + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ +#endif /* GD32F30X_CL */ + RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< RTC clock reset */ + + /* APB2 peripherals */ + RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ + RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ + RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ + RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ +#ifndef GD32F30X_CL + RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ +#endif /* GD32F30X_CL */ +#ifndef GD32F30X_HD + RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ + RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ + RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ +#endif /* GD32F30X_HD */ +} rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum { + /* clock stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ +#ifdef GD32F30X_CL + RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ + RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ +#endif /* GD32F30X_CL */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ + RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ + /* reset source flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ +} rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ +#ifdef GD32F30X_CL + RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ + RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ +#endif /* GD32F30X_CL */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ + RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ +} rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ +#ifdef GD32F30X_CL + RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ +#endif /* GD32F30X_CL */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ + RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ +} rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum { + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ +#ifdef GD32F30X_CL + RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ + RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ +#endif /* GD32F30X_CL */ + RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ +} rcu_int_enum; + +/* oscillator types */ +typedef enum { + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ + RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ + RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ +#ifdef GD32F30X_CL + RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ + RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ +#endif /* GD32F30X_CL */ +} rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum { + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +} rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC prescaler select */ +#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ +#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ +#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ +#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ +#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ +#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ +#define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/5 */ +#define RCU_CKADC_CKAHB_DIV6 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/6 */ +#define RCU_CKADC_CKAHB_DIV10 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/10 */ +#define RCU_CKADC_CKAHB_DIV20 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/20 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ +#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */ + +/* PLL clock multiplication factor */ +#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ +#define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */ +#define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */ + +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ +#elif defined(GD32F30X_CL) +#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ +#endif /* GD32F30X_HD and GD32F30X_XD */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ +#define RCU_PLL_MUL33 (PLLMF_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 33 */ +#define RCU_PLL_MUL34 (PLLMF_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 34 */ +#define RCU_PLL_MUL35 (PLLMF_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 35 */ +#define RCU_PLL_MUL36 (PLLMF_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 36 */ +#define RCU_PLL_MUL37 (PLLMF_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 37 */ +#define RCU_PLL_MUL38 (PLLMF_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 38 */ +#define RCU_PLL_MUL39 (PLLMF_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 39 */ +#define RCU_PLL_MUL40 (PLLMF_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 40 */ +#define RCU_PLL_MUL41 (PLLMF_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 41 */ +#define RCU_PLL_MUL42 (PLLMF_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 42 */ +#define RCU_PLL_MUL43 (PLLMF_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 43 */ +#define RCU_PLL_MUL44 (PLLMF_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 44 */ +#define RCU_PLL_MUL45 (PLLMF_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 45 */ +#define RCU_PLL_MUL46 (PLLMF_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 46 */ +#define RCU_PLL_MUL47 (PLLMF_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 47 */ +#define RCU_PLL_MUL48 (PLLMF_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 48 */ +#define RCU_PLL_MUL49 (PLLMF_4_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 49 */ +#define RCU_PLL_MUL50 (PLLMF_4_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 50 */ +#define RCU_PLL_MUL51 (PLLMF_4_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 51 */ +#define RCU_PLL_MUL52 (PLLMF_4_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 52 */ +#define RCU_PLL_MUL53 (PLLMF_4_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 53 */ +#define RCU_PLL_MUL54 (PLLMF_4_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 54 */ +#define RCU_PLL_MUL55 (PLLMF_4_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 55 */ +#define RCU_PLL_MUL56 (PLLMF_4_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 56 */ +#define RCU_PLL_MUL57 (PLLMF_4_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 57 */ +#define RCU_PLL_MUL58 (PLLMF_4_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 58 */ +#define RCU_PLL_MUL59 (PLLMF_4_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 59 */ +#define RCU_PLL_MUL60 (PLLMF_4_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 60 */ +#define RCU_PLL_MUL61 (PLLMF_4_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 61 */ +#define RCU_PLL_MUL62 (PLLMF_4_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 62 */ +#define RCU_PLL_MUL63 (PLLMF_4_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 63 */ + +#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) +#define USBPSC_2 RCU_CFG0_USBDPSC_2 +#elif defined(GD32F30X_CL) +#define USBPSC_2 RCU_CFG0_USBFSPSC_2 +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* USBD/USBFS prescaler select */ +#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ +#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ +#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ +#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ +#define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBD/USBFS prescaler select CK_PLL/3.5 */ +#define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBD/USBFS prescaler select CK_PLL/3 */ +#define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBFS prescaler select CK_PLL/4 */ + +/* CKOUT0 Clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ +#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ +#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ +#ifdef GD32F30X_CL +#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ +#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ +#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ +#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ +#endif /* GD32F30X_CL */ + +/* LXTAL drive capability */ +#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) +#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ +#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ +#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ +#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ +#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + +/* PREDV0 division factor */ +#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ +#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ +#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ +#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ +#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ +#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ +#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ +#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ +#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ +#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ +#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ +#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ +#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ +#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ +#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ +#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + +/* PREDV1 division factor */ +#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ +#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ +#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ +#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ +#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ +#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ +#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ +#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ +#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ +#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ +#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ +#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ +#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ +#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ +#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ +#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + +/* PLL1 clock multiplication factor */ +#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ +#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ +#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ +#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ +#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ +#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ +#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ +#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ +#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ +#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + +/* PLL2 clock multiplication factor */ +#define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */ + +#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) +#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ +#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ +#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ +#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ +#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ +#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ +#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ +#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ +#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ +#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ +#define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 18 */ +#define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 19 */ +#define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 21 */ +#define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 22 */ +#define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 23 */ +#define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 24 */ +#define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 25 */ +#define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 26 */ +#define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 27 */ +#define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 28 */ +#define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 29 */ +#define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 30 */ +#define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 31 */ +#define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 32 */ +#define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 40 */ + +#ifdef GD32F30X_CL +/* PREDV0 input clock source selection */ +#define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */ +#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ + +/* I2S1 clock source selection */ +#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ +#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ + +/* I2S2 clock source selection */ +#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ +#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ +#endif /* GD32F30X_CL */ + +/* PLL input clock source selection */ +#define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */ +#define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ + +/* deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ + +/* 48MHz clock selection */ +#define RCU_CK48MSRC_CKPLL ((uint32_t)0x00000000U) /*!< use CK_PLL clock */ +#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< select IRC48M clock */ + +/* function declarations */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP domain */ +void rcu_bkp_reset_enable(void); +/* disable the BKP domain reset */ +void rcu_bkp_reset_disable(void); + +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +/* configure the PLL clock source preselection */ +void rcu_pllpresel_config(uint32_t pll_presel); +#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_div); +#elif defined(GD32F30X_CL) +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); +/* configure the PREDV1 division factor */ +void rcu_predv1_config(uint32_t predv1_div); +/* configure the PLL1 clock */ +void rcu_pll1_config(uint32_t pll_mul); +/* configure the PLL2 clock */ +void rcu_pll2_config(uint32_t pll_mul); +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/* configure the ADC division factor */ +void rcu_adc_clock_config(uint32_t adc_psc); +/* configure the USBD/USBFS prescaler factor */ +void rcu_usb_clock_config(uint32_t usb_psc); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +#ifdef GD32F30X_CL +/* configure the I2S1 clock source selection */ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source); +/* configure the I2S2 clock source selection */ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source); +#endif /* GD32F30X_CL */ +/* configure the CK48M clock selection */ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); + + +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); + +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32F30X_RCU_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h new file mode 100644 index 0000000000..8767b6d140 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h @@ -0,0 +1,136 @@ +/*! + \file gd32f30x_rtc.h + \brief definitions for the RTC + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_RTC_H +#define GD32F30X_RTC_H + +#include "gd32f30x.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ + +/* bits definitions */ +/* RTC_INTEN */ +#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ +#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ +#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ + +/* RTC_CTL */ +#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ +#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ +#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ +#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ +#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ +#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + +/* RTC_PSC */ +#define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ +#define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ + +/* RTC_DIV */ +#define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ +#define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ + +/* RTC_CNT */ +#define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ +#define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ + +/* RTC_ALRM */ +#define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ +#define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ + +/* constants definitions */ +#define RTC_HIGH_VALUE 0x000F0000U /*!< RTC high value */ +#define RTC_LOW_VALUE 0x0000FFFFU /*!< RTC low value */ + +/* RTC interrupt enable or disable definitions */ +#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ +#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ +#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ + +/* RTC flag definitions */ +#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ +#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ + +/* function declarations */ +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); + +/* enter RTC configuration mode */ +void rtc_configuration_mode_enter(void); +/* exit RTC configuration mode */ +void rtc_configuration_mode_exit(void); + +/* wait RTC last write operation finished flag set */ +void rtc_lwoff_wait(void); +/* wait RTC registers synchronized flag set */ +void rtc_register_sync_wait(void); + +/* get RTC counter value */ +uint32_t rtc_counter_get(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); + +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); +/* get RTC divider value */ +uint32_t rtc_divider_get(void); + +/* get RTC flag status */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear RTC flag status */ +void rtc_flag_clear(uint32_t flag); + +#endif /* GD32F30X_RTC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h new file mode 100644 index 0000000000..2bc38ee7c3 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h @@ -0,0 +1,429 @@ +/*! + \file gd32f30x_sdio.h + \brief definitions for the SDIO + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_SDIO_H +#define GD32F30X_SDIO_H + +#include "gd32f30x.h" + +/* SDIO definitions */ +#define SDIO SDIO_BASE + +/* registers definitions */ +#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ +#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ +#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ +#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ +#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ +#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ +#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ +#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ +#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ +#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ +#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ +#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ +#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ +#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ +#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ +#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ +#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ +#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ + +/* bits definitions */ +/* SDIO_PWRCTL */ +#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ + +/* SDIO_CLKCTL */ +#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ +#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ +#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ +#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ +#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ +#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ +#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ + +/* SDIO_CMDAGMT */ +#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ + +/* SDIO_CMDCTL */ +#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ +#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ +#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ +#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ +#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ +#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ +#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ +#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ +#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ + +/* SDIO_DATATO */ +#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ + +/* SDIO_DATALEN */ +#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ + +/* SDIO_DATACTL */ +#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ +#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ +#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ +#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ +#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ +#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ +#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ +#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ +#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ + +/* SDIO_STAT */ +#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ +#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ +#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ +#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ +#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ +#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ +#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ +#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ +#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ +#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ +#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ +#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ +#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ +#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ +#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ +#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ +#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ +#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ +#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ +#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ +#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ +#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ +#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ +#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ + +/* SDIO_INTC */ +#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ +#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ +#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ +#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ +#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ +#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ +#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ +#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ +#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ +#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ +#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ +#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ +#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ + +/* SDIO_INTEN */ +#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ +#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ +#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ +#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ +#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ +#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ +#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ +#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ +#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ +#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ +#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ +#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ +#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ +#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ +#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ +#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ +#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ +#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ +#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ +#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ +#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ +#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ +#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ +#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ + +/* SDIO_FIFO */ +#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ + +/* constants definitions */ +/* SDIO flags */ +#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ +#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ +#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ +#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ +#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ +#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ +#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ +#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ +#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ +#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ +#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ +#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ +#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ +#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ +#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ +#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ +#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ +#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ +#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ +#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ +#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ +#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ +#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ +#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ + +/* SDIO interrupt enable or disable */ +#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ + +/* SDIO power control */ +#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ +#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ + +/* SDIO card bus mode control */ +#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ +#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ +#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ + +/* SDIO_CLK clock edge selection */ +#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ +#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ + +/* clock bypass enable or disable */ +#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */ +#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ + +/* SDIO_CLK clock dynamic switch on/off for power saving */ +#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */ +#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ + +/* SDIO command response type */ +#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ +#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ +#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ + +/* command state machine wait type */ +#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */ +#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ +#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ + +#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */ +#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */ +#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */ +#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ + +/* SDIO data block size */ +#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ +#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ +#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ +#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ +#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ +#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ +#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ +#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ +#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ +#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ +#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ +#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ +#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ +#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ +#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ + +/* SDIO data transfer mode */ +#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */ +#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ + +/* SDIO data transfer direction */ +#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */ +#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ + +/* SDIO read wait type */ +#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */ +#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ + +/* function declarations */ +/* deinitialize the SDIO */ +void sdio_deinit(void); +/* configure the SDIO clock */ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); +/* enable hardware clock control */ +void sdio_hardware_clock_enable(void); +/* disable hardware clock control */ +void sdio_hardware_clock_disable(void); +/* set different SDIO card bus mode */ +void sdio_bus_mode_set(uint32_t bus_mode); +/* set the SDIO power state */ +void sdio_power_state_set(uint32_t power_state); +/* get the SDIO power state */ +uint32_t sdio_power_state_get(void); +/* enable SDIO_CLK clock output */ +void sdio_clock_enable(void); +/* disable SDIO_CLK clock output */ +void sdio_clock_disable(void); + +/* configure the command index, argument, response type, wait type and CSM to send command */ +/* configure the command and response */ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); +/* set the command state machine wait type */ +void sdio_wait_type_set(uint32_t wait_type); +/* enable the CSM(command state machine) */ +void sdio_csm_enable(void); +/* disable the CSM(command state machine) */ +void sdio_csm_disable(void); +/* get the last response command index */ +uint8_t sdio_command_index_get(void); +/* get the response for the last received command */ +uint32_t sdio_response_get(uint32_t responsex); + +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ +/* configure the data timeout, data length and data block size */ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); +/* configure the data transfer mode and direction */ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); +/* enable the DSM(data state machine) for data transfer */ +void sdio_dsm_enable(void); +/* disable the DSM(data state machine) */ +void sdio_dsm_disable(void); +/* write data(one word) to the transmit FIFO */ +void sdio_data_write(uint32_t data); +/* read data(one word) from the receive FIFO */ +uint32_t sdio_data_read(void); +/* get the number of remaining data bytes to be transferred to card */ +uint32_t sdio_data_counter_get(void); +/* get the number of words remaining to be written or read from FIFO */ +uint32_t sdio_fifo_counter_get(void); +/* enable the DMA request for SDIO */ +void sdio_dma_enable(void); +/* disable the DMA request for SDIO */ +void sdio_dma_disable(void); + +/* get the flags state of SDIO */ +FlagStatus sdio_flag_get(uint32_t flag); +/* clear the pending flags of SDIO */ +void sdio_flag_clear(uint32_t flag); +/* enable the SDIO interrupt */ +void sdio_interrupt_enable(uint32_t int_flag); +/* disable the SDIO interrupt */ +void sdio_interrupt_disable(uint32_t int_flag); +/* get the interrupt flags state of SDIO */ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); +/* clear the interrupt pending flags of SDIO */ +void sdio_interrupt_flag_clear(uint32_t int_flag); + +/* enable the read wait mode(SD I/O only) */ +void sdio_readwait_enable(void); +/* disable the read wait mode(SD I/O only) */ +void sdio_readwait_disable(void); +/* enable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_enable(void); +/* disable the function that stop the read wait process(SD I/O only) */ +void sdio_stop_readwait_disable(void); +/* set the read wait type(SD I/O only) */ +void sdio_readwait_type_set(uint32_t readwait_type); +/* enable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_enable(void); +/* disable the SD I/O mode specific operation(SD I/O only) */ +void sdio_operation_disable(void); +/* enable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_enable(void); +/* disable the SD I/O suspend operation(SD I/O only) */ +void sdio_suspend_disable(void); + +/* enable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_enable(void); +/* disable the CE-ATA command(CE-ATA only) */ +void sdio_ceata_command_disable(void); +/* enable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_enable(void); +/* disable the CE-ATA interrupt(CE-ATA only) */ +void sdio_ceata_interrupt_disable(void); +/* enable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_enable(void); +/* disable the CE-ATA command completion signal(CE-ATA only) */ +void sdio_ceata_command_completion_disable(void); + +#endif /* GD32F30X_SDIO_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h new file mode 100644 index 0000000000..e96e7e8fb4 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h @@ -0,0 +1,356 @@ +/*! + \file gd32f30x_spi.h + \brief definitions for the SPI + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_SPI_H +#define GD32F30X_SPI_H + +#include "gd32f30x.h" + +/* SPIx(x=0,1,2) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register(only SPI0) */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCR BITS(0,15) /*!< RX CRC register */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_QCTL(only for SPI0) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct { + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +} spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ + +/* function declarations */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +#ifdef GD_MBED_USED +/* initialize SPI parameter */ +void spi_para_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); +#else +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); +#endif +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); + +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* enable SPI NSS pulse mode */ +void spi_nssp_mode_enable(uint32_t spi_periph); +/* disable SPI NSS pulse mode */ +void spi_nssp_mode_disable(uint32_t spi_periph); + +/* enable quad wire SPI */ +void qspi_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void qspi_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void qspi_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void qspi_read_enable(uint32_t spi_periph); +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_enable(uint32_t spi_periph); +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_disable(uint32_t spi_periph); + +#endif /* GD32F30X_SPI_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h new file mode 100644 index 0000000000..1b02616738 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h @@ -0,0 +1,737 @@ +/*! + \file gd32f30x_timer.h + \brief definitions for the TIMER + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_TIMER_H +#define GD32F30X_TIMER_H + +#include "gd32f30x.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) +#define TIMER7 (TIMER_BASE + 0x00013400U) +#define TIMER8 (TIMER_BASE + 0x00014C00U) +#define TIMER9 (TIMER_BASE + 0x00015000U) +#define TIMER10 (TIMER_BASE + 0x00015400U) +#define TIMER11 (TIMER_BASE + 0x00001800U) +#define TIMER12 (TIMER_BASE + 0x00001C00U) +#define TIMER13 (TIMER_BASE + 0x00002000U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< channel control update DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* TIMER_IRMP */ +#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions*/ +typedef struct { + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint32_t period; /*!< period value */ + uint16_t clockdivision; /*!< clock division value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +} timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct { + uint16_t runoffstate; /*!< run mode off-state */ + uint32_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +} timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct { + uint32_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +} timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct { + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +} timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP ((uint32_t)0x00000001U) /*!< update interrupt */ +#define TIMER_INT_CH0 ((uint32_t)0x00000002U) /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 ((uint32_t)0x00000004U) /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 ((uint32_t)0x00000008U) /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 ((uint32_t)0x00000010U) /*!< channel 3 interrupt */ +#define TIMER_INT_CMT ((uint32_t)0x00000020U) /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG ((uint32_t)0x00000040U) /*!< trigger interrupt */ +#define TIMER_INT_BRK ((uint32_t)0x00000080U) /*!< break interrupt */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ +#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ +#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ +#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ +#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ +#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK + +/* TIMER flag */ +#define TIMER_FLAG_UP ((uint32_t)0x00000001U) /*!< update flag */ +#define TIMER_FLAG_CH0 ((uint32_t)0x00000002U) /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 ((uint32_t)0x00000004U) /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 ((uint32_t)0x00000008U) /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 ((uint32_t)0x00000010U) /*!< channel 3 flag */ +#define TIMER_FLAG_CMT ((uint32_t)0x00000020U) /*!< channel control update flag */ +#define TIMER_FLAG_TRG ((uint32_t)0x00000040U) /*!< trigger flag */ +#define TIMER_FLAG_BRK ((uint32_t)0x00000080U) /*!< break flag */ +#define TIMER_FLAG_CH0O ((uint32_t)0x00000200U) /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O ((uint32_t)0x00000400U) /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O ((uint32_t)0x00000800U) /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O ((uint32_t)0x00001000U) /*!< channel 3 overcapture flag */ + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)0x0100U) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)0x0200U) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)0x0400U) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)0x0800U) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)0x1000U) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)0x2000U) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)0x4000U) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel y(y=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ + +/* channel enable state*/ +#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ + +/* channel complementary output enable state*/ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable. */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge(not for timer1..6) */ + +/* timer input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ + +/* timerx(x=0,1,2,13,14,15,16) write cc register selection */ +#define TIMER_CCSEL_DISABLE ((uint16_t)0x0000U) /*!< write CC register selection disable */ +#define TIMER_CCSEL_ENABLE ((uint16_t)0x0002U) /*!< write CC register selection enable */ + +/* the output value selection */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ + +/* function declarations */ +/* TIMER timebase */ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint8_t update); + +/* TIMER interrupt and flag */ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get timer interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +/* timer DMA and event */ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* timer channel complementary protection */ +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* configure TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* channel capture/compare control shadow register enable */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); + +/* TIMER channel output */ +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); + +/* TIMER configure */ +/* configure TIMER write CHxVAL register selection */ +void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); + +#endif /* GD32F30X_TIMER_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h new file mode 100644 index 0000000000..9438e91456 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h @@ -0,0 +1,454 @@ +/*! + \file gd32f30x_usart.h + \brief definitions for the USART + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_USART_H +#define GD32F30X_USART_H + +#include "gd32f30x.h" + +/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ +#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ +#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ +#define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ + +/* registers definitions */ +#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ +#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ +#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ +#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ +#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ + +/* bits definitions */ +/* USARTx_STAT0 */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_CTL3 */ +#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_STAT1 */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ + +/* USART flags */ +typedef enum { + /* flags in STAT0 register */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in STAT1 register */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ +} usart_flag_enum; + +/* USART interrupt flags */ +typedef enum { + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ + /* interrupt flags in CTL3 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ +} usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum { + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in CTL3 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ +} usart_interrupt_enum; + +/* USART invert configure */ +typedef enum { + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ +} usart_invert_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ + +#ifdef GD_MBED_USED +/* USART error code */ +#define USART_ERROR_CODE_NONE 0U /*!< no error */ +#define USART_ERROR_CODE_PERR BIT(0) /*!< parity error */ +#define USART_ERROR_CODE_NERR BIT(1) /*!< noise error */ +#define USART_ERROR_CODE_FERR BIT(2) /*!< frame error */ +#define USART_ERROR_CODE_ORERR BIT(3) /*!< overrun error */ + +/* USART hardware control configuration */ +#define USART_HWCONTROL_NONE 0U +#define USART_HWCONTROL_RTS USART_RTS_ENABLE +#define USART_HWCONTROL_CTS USART_CTS_ENABLE +#define USART_HWCONTROL_RTS_CTS (USART_RTS_ENABLE | USART_CTS_ENABLE) +#endif + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); + +/* USART normal mode communication */ +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* LIN mode enable */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* LIN mode disable */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen); +/* send break frame */ +void usart_send_break(uint32_t usart_periph); + +/* half-duplex communication */ +/* half-duplex enable */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* half-duplex disable */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* clock enable */ +void usart_synchronous_clock_enable(uint32_t usart_periph); +/* clock disable */ +void usart_synchronous_clock_disable(uint32_t usart_periph); +/* configure usart synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* guard time value configure in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* smartcard mode enable */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* smartcard mode disable */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* NACK enable in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* NACK disable in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* smartcard auto-retry number configure */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* block length configure */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); + +/* flag functions */ +/* get flag in STAT0/STAT1 register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT0/STAT1 register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); + +/* interrupt functions */ +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); +/* clear interrupt flag in STAT0/STAT1 register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); +#endif /* GD32F30x_USART_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h new file mode 100644 index 0000000000..2bd188039a --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h @@ -0,0 +1,88 @@ +/*! + \file gd32f30x_wwdgt.h + \brief definitions for the WWDGT + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_WWDGT_H +#define GD32F30X_WWDGT_H + +#include "gd32f30x.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32F30X_WWDGT_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c new file mode 100644 index 0000000000..63725286ee --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c @@ -0,0 +1,940 @@ +/*! + \file gd32f30x_adc.c + \brief ADC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_adc.h" + +/*! + \brief reset ADC + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_deinit(uint32_t adc_periph) +{ + switch (adc_periph) { + case ADC0: + rcu_periph_reset_enable(RCU_ADC0RST); + rcu_periph_reset_disable(RCU_ADC0RST); + break; + case ADC1: + rcu_periph_reset_enable(RCU_ADC1RST); + rcu_periph_reset_disable(RCU_ADC1RST); + break; +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + case ADC2: + rcu_periph_reset_enable(RCU_ADC2RST); + rcu_periph_reset_disable(RCU_ADC2RST); + break; +#endif + default: + break; + } +} + +/*! + \brief enable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_enable(uint32_t adc_periph) +{ + if (RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_calibration_enable(uint32_t adc_periph) +{ + /* reset the selected ADC1 calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while ((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while ((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { + } +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] resolution: ADC resolution + only one among these parameters can be selected + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief configure ADC discontinuous mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + only one among these parameters can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel ,the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +{ + ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + switch (adc_channel_group) { + case ADC_REGULAR_CHANNEL: + /* config the number of conversions in discontinuous mode */ + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U)); + + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + default: + break; + } +} + +/*! + \brief configure the ADC sync mode + \param[in] mode: ADC mode + only one among these parameters can be selected + \arg ADC_MODE_FREE: all the ADCs work independently + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode + \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode + \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode + \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only + \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only + \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only + \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only + \param[out] none + \retval none +*/ +void adc_mode_config(uint32_t mode) +{ + ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); + ADC_CTL0(ADC0) |= mode; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] function: the function to config + one or more parameters can be selected below + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) +{ + if (newvalue) { + if (0U != (function & ADC_SCAN_MODE)) { + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if (0U != (function & ADC_CONTINUOUS_MODE)) { + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + } else { + if (0U != (function & ADC_SCAN_MODE)) { + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if (0U != (function & ADC_CONTINUOUS_MODE)) { + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] data_alignment: data alignment select + only one parameter can be selected + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) +{ + if (ADC_DATAALIGN_RIGHT != data_alignment) { + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + } else { + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + only one parameter can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +{ + switch (adc_channel_group) { + case ADC_REGULAR_CHANNEL: + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - 1U)); + + break; + case ADC_INSERTED_CHANNEL: + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - 1U)); + + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one among these parameters can be selected + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint32_t rsq, sampt; + + /* ADC regular sequence config */ + if (rank < 6U) { + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * rank))); + rsq |= ((uint32_t)adc_channel << (5U * rank)); + ADC_RSQ2(adc_periph) = rsq; + } else if (rank < 12U) { + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 6U)))); + rsq |= ((uint32_t)adc_channel << (5U * (rank - 6U))); + ADC_RSQ1(adc_periph) = rsq; + } else if (rank < 16U) { + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 12U)))); + rsq |= ((uint32_t)adc_channel << (5U * (rank - 12U))); + ADC_RSQ0(adc_periph) = rsq; + } else { + } + + /* ADC sampling time config */ + if (adc_channel < 10U) { + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * adc_channel))); + sampt |= (uint32_t)(sample_time << (3U * adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + } else if (adc_channel < 18U) { + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (adc_channel - 10U)))); + sampt |= (uint32_t)(sample_time << (3U * (adc_channel - 10U))); + ADC_SAMPT0(adc_periph) = sampt; + } else { + } +} + +/*! + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one among these parameters can be selected + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq, sampt; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank) * 5U))); + isq |= ((uint32_t)adc_channel << (15U - (inserted_length - rank) * 5U)); + ADC_ISQ(adc_periph) = isq; + + /* ADC sampling time config */ + if (adc_channel < 10U) { + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * adc_channel))); + sampt |= (uint32_t) sample_time << (3U * adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + } else if (adc_channel < 18U) { + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (adc_channel - 10U)))); + sampt |= ((uint32_t)sample_time << (3U * (adc_channel - 10U))); + ADC_SAMPT0(adc_periph) = sampt; + } else { + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] inserted_channel : insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset : the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); + num = 3U - (inserted_length - inserted_channel); + + if (num <= 3U) { + /* calculate the offset of the register */ + num = num * 4U; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief enable ADC external trigger + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) +{ + if (newvalue) { + if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; + } + if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; + } + } else { + if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; + } + if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief configure ADC external trigger source + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + only one parameter can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected + for regular channel: + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select + \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select + \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select + \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select + \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11 + \arg ADC2_EXTTRIG_REGULAR_T2_CH0: timer 2 CC0 event select + \arg ADC2_EXTTRIG_REGULAR_T1_CH2: timer 1 CC2 event select + \arg ADC2_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select + \arg ADC2_EXTTRIG_REGULAR_T7_CH0: timer 7 CC0 event select + \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH0: timer 4 CC0 event select + \arg ADC2_EXTTRIG_REGULAR_T4_CH2: timer 4 CC2 event select + \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select + \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select + \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select + \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select + \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select + \arg ADC2_EXTTRIG_INSERTED_T3_CH2: timer 3 CC2 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH1: timer 7 CC1 event select + \arg ADC2_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select + \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: timer 4 TRGO event select + \arg ADC2_EXTTRIG_INSERTED_T4_CH3: timer 4 CC3 event select + \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +{ + switch (adc_channel_group) { + case ADC_REGULAR_CHANNEL: + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: select the channel group + one or more parameters can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; + } + if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(uint32_t adc_periph) +{ + return (uint16_t)(ADC_RDATA(adc_periph)); +} + +/*! + \brief read ADC inserted group data register + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] inserted_channel : insert channel select + only one parameter can be selected + \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch (inserted_channel) { + case ADC_INSERTED_CHANNEL_0: + idata = ADC_IDATA0(adc_periph); + break; + case ADC_INSERTED_CHANNEL_1: + idata = ADC_IDATA1(adc_periph); + break; + case ADC_INSERTED_CHANNEL_2: + idata = ADC_IDATA2(adc_periph); + break; + case ADC_INSERTED_CHANNEL_3: + idata = ADC_IDATA3(adc_periph); + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief read the last ADC0 and ADC1 conversion result data in sync mode + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint32_t adc_sync_mode_convert_value_read(void) +{ + /* return conversion value */ + return ADC_RDATA(ADC0); +} + +/*! + \brief get the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_flag: the adc flag bits + only one parameter can be selected + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) +{ + FlagStatus reval = RESET; + if (ADC_STAT(adc_periph) & adc_flag) { + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag bits + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_flag: the adc flag bits + one or more parameters can be selected + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); +} + +/*! + \brief get the ADC interrupt bits + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc interrupt bits + only oneparameter can be selected + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch (adc_interrupt) { + case ADC_INT_FLAG_WDE: + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if ((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear the ADC flag + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc status flag + one or more parameters can be selected + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) +{ + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); +} + +/*! + \brief enable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc interrupt + one or more parameters can be selected + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + if (0U != (adc_interrupt & ADC_INT_WDE)) { + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + } + + if (0U != (adc_interrupt & ADC_INT_EOC)) { + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + } + + if (0U != (adc_interrupt & ADC_INT_EOIC)) { + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_interrupt: the adc interrupt flag + one or more parameters can be selected + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) +{ + if (0U != (adc_interrupt & ADC_INT_WDE)) { + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; + } + + if (0U != (adc_interrupt & ADC_INT_EOC)) { + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; + } + + if (0U != (adc_interrupt & ADC_INT_EOIC)) { + ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; + } +} + +/*! + \brief configure ADC analog watchdog single channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel: the selected ADC channel + only one among these parameters can be selected + \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + + ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + /* select the group */ + switch (adc_channel_group) { + case ADC_REGULAR_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_watchdog_disable(uint32_t adc_periph) +{ + ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] mode: ADC oversampling mode + only oneparameter can be selected + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only oneparameter can be selected + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only oneparameter can be selected + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) +{ + if (ADC_OVERSAMPLING_ONE_CONVERT == mode) { + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + } else { + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + /* config the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c new file mode 100644 index 0000000000..e2cf2d4879 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c @@ -0,0 +1,327 @@ +/*! + \file gd32f30x_bkp.c + \brief BKP driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_bkp.h" + +#define TAMPER_FLAG_SHIFT ((uint8_t)8U) + +/*! + \brief reset BKP registers + \param[in] none + \param[out] none + \retval none +*/ +void bkp_deinit(void) +{ + /* reset BKP domain register*/ + rcu_bkp_reset_enable(); + rcu_bkp_reset_disable(); +} + +/*! + \brief write BKP data register + \param[in] register_number: refer to bkp_data_register_enum, only one parameter can be selected + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[in] data: the data to be write in BKP data register + \param[out] none + \retval none +*/ +void bkp_write_data(bkp_data_register_enum register_number, uint16_t data) +{ + if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { + BKP_DATA10_41(register_number - 1U) = data; + } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { + BKP_DATA0_9(register_number - 1U) = data; + } else { + /* illegal parameters */ + } +} + +/*! + \brief read BKP data register + \param[in] register_number: refer to bkp_data_register_enum, only one parameter can be selected + \arg BKP_DATA_x(x = 0..41): bkp data register number x + \param[out] none + \retval data of BKP data register +*/ +uint16_t bkp_read_data(bkp_data_register_enum register_number) +{ + uint16_t data = 0U; + + /* get the data from the BKP data register */ + if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { + data = BKP_DATA10_41(register_number - 1U); + } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { + data = BKP_DATA0_9(register_number - 1U); + } else { + /* illegal parameters */ + } + return data; +} + +/*! + \brief enable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; +} + +/*! + \brief disable RTC clock calibration output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; +} + +/*! + \brief enable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_enable(void) +{ + BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; +} + +/*! + \brief disable RTC alarm or second signal output + \param[in] none + \param[out] none + \retval none +*/ +void bkp_rtc_signal_output_disable(void) +{ + BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; +} + +/*! + \brief select RTC output + \param[in] outputsel: RTC output selection + \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output + \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output + \param[out] none + \retval none +*/ +void bkp_rtc_output_select(uint16_t outputsel) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_ROSEL; + ctl |= outputsel; + BKP_OCTL = ctl; +} + +/*! + \brief select RTC clock output + \param[in] clocksel: RTC clock output selection + \arg RTC_CLOCK_DIV_64: RTC clock div 64 + \arg RTC_CLOCK_DIV_1: RTC clock + \param[out] none + \retval none +*/ +void bkp_rtc_clock_output_select(uint16_t clocksel) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_CCOSEL; + ctl |= clocksel; + BKP_OCTL = ctl; +} + +/*! + \brief RTC clock calibration direction + \param[in] direction: RTC clock calibration direction + \arg RTC_CLOCK_SLOWED_DOWN: RTC clock slow down + \arg RTC_CLOCK_SPEED_UP: RTC clock speed up + \param[out] none + \retval none +*/ +void bkp_rtc_clock_calibration_direction(uint16_t direction) +{ + uint16_t ctl = 0U; + + ctl = BKP_OCTL; + ctl &= (uint16_t)~BKP_OCTL_CALDIR; + ctl |= direction; + BKP_OCTL = ctl; +} + +/*! + \brief set RTC clock calibration value + \param[in] value: RTC clock calibration value + \arg 0x00 - 0x7F + \param[out] none + \retval none +*/ +void bkp_rtc_calibration_value_set(uint8_t value) +{ + uint16_t ctl; + + ctl = BKP_OCTL; + ctl &= (uint16_t)OCTL_RCCV(0); + ctl |= (uint16_t)OCTL_RCCV(value); + BKP_OCTL = ctl; +} + +/*! + \brief enable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_enable(void) +{ + BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; +} + +/*! + \brief disable tamper detection + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_detection_disable(void) +{ + BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; +} + +/*! + \brief set tamper pin active level + \param[in] level: tamper active level + \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high + \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low + \param[out] none + \retval none +*/ +void bkp_tamper_active_level_set(uint16_t level) +{ + uint16_t ctl = 0U; + + ctl = BKP_TPCTL; + ctl &= (uint16_t)~BKP_TPCTL_TPAL; + ctl |= level; + BKP_TPCTL = ctl; +} + +/*! + \brief enable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_enable(void) +{ + BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; +} + +/*! + \brief disable tamper interrupt + \param[in] none + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_disable(void) +{ + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; +} + +/*! + \brief get bkp flag state + \param[in] flag + \arg BKP_FLAG_TAMPER: tamper event flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_flag_get(uint16_t flag) +{ + if (RESET != (BKP_TPCS & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear bkp flag state + \param[in] flag + \arg BKP_FLAG_TAMPER: tamper event flag + \param[out] none + \retval none +*/ +void bkp_flag_clear(uint16_t flag) +{ + BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); +} + +/*! + \brief get bkp interrupt flag state + \param[in] flag + \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus bkp_interrupt_flag_get(uint16_t flag) +{ + if (RESET != (BKP_TPCS & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear bkp interrupt flag state + \param[in] flag + \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag + \param[out] none + \retval none +*/ +void bkp_interrupt_flag_clear(uint16_t flag) +{ + BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); +} + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_can.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_can.c new file mode 100644 index 0000000000..ccca161968 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_can.c @@ -0,0 +1,875 @@ +/*! + \file gd32f30x_can.c + \brief CAN driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_can.h" + +/*! + \brief deinitialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_deinit(uint32_t can_periph) +{ +#ifdef GD32F30X_CL + if (CAN0 == can_periph) { + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } else { + rcu_periph_reset_enable(RCU_CAN1RST); + rcu_periph_reset_disable(RCU_CAN1RST); + } +#else + if (CAN0 == can_periph) { + rcu_periph_reset_enable(RCU_CAN0RST); + rcu_periph_reset_disable(RCU_CAN0RST); + } +#endif +} + +/*! + \brief initialize CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0001 - 0x03FF + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +#ifdef GD_MBED_USED +ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) +#else +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) +#endif +{ + uint32_t timeout = CAN_TIMEOUT; + ErrStatus flag = ERROR; + + /* disable sleep mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + /* enable initialize mode */ + CAN_CTL(can_periph) |= CAN_CTL_IWMOD; + /* wait ACK */ + while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)) { + timeout--; + } + /* check initialize working success */ + if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { + flag = ERROR; + } else { + /* set the bit timing register */ + CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ + BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ + BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ + BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ + BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + /* time trigger communication mode */ + if (ENABLE == can_parameter_init->time_triggered) { + CAN_CTL(can_periph) |= CAN_CTL_TTC; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + } + /* automatic bus-off managment */ + if (ENABLE == can_parameter_init->auto_bus_off_recovery) { + CAN_CTL(can_periph) |= CAN_CTL_ABOR; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; + } + /* automatic wakeup mode */ + if (ENABLE == can_parameter_init->auto_wake_up) { + CAN_CTL(can_periph) |= CAN_CTL_AWU; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_AWU; + } + /* automatic retransmission mode */ + if (ENABLE == can_parameter_init->auto_retrans) { + CAN_CTL(can_periph) |= CAN_CTL_ARD; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } + /* receive fifo overwrite mode */ + if (ENABLE == can_parameter_init->rec_fifo_overwrite) { + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; + } + /* transmit fifo order */ + if (ENABLE == can_parameter_init->trans_fifo_order) { + CAN_CTL(can_periph) |= CAN_CTL_TFO; + } else { + CAN_CTL(can_periph) &= ~CAN_CTL_TFO; + } + /* disable initialize mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; + timeout = CAN_TIMEOUT; + /* wait the ACK */ + while ((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)) { + timeout--; + } + /* check exit initialize mode */ + if (CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) { + flag = SUCCESS; + } + } + return flag; +} + +/*! + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) +{ + uint32_t val = 0U; + + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* disable filter */ + CAN_FW(CAN0) &= ~(uint32_t)val; + + /* filter 16 bits */ + if (CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) { + /* set filter 16 bits */ + CAN_FSCFG(CAN0) &= ~(uint32_t)val; + /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + } + /* filter 32 bits */ + if (CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) { + /* set filter 32 bits */ + CAN_FSCFG(CAN0) |= (uint32_t)val; + /* 32 bits list or first 32 bits list */ + CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + /* 32 bits mask or second 32 bits list */ + CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + } + + /* filter mode */ + if (CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) { + /* mask mode */ + CAN_FMCFG(CAN0) &= ~(uint32_t)val; + } else { + /* list mode */ + CAN_FMCFG(CAN0) |= (uint32_t)val; + } + + /* filter FIFO */ + if (CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) { + /* FIFO0 */ + CAN_FAFIFO(CAN0) &= ~(uint32_t)val; + } else { + /* FIFO1 */ + CAN_FAFIFO(CAN0) |= (uint32_t)val; + } + + /* filter working */ + if (ENABLE == can_filter_parameter_init->filter_enable) { + + CAN_FW(CAN0) |= (uint32_t)val; + } + + /* filter lock enable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief set CAN1 fliter start bank number + \param[in] start_bank: CAN1 start bank number + \arg (1..27) + \param[out] none + \retval none +*/ +void can1_filter_start_bank(uint8_t start_bank) +{ + /* filter lock disable */ + CAN_FCTL(CAN0) |= CAN_FCTL_FLD; + /* set CAN1 filter start number */ + CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; + CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); + /* filter lock enaable */ + CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; +} + +/*! + \brief enable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_enable(uint32_t can_periph) +{ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; +#ifdef GD32F30X_CL + if (CAN0 == can_periph) { + dbg_periph_enable(DBG_CAN0_HOLD); + } else { + dbg_periph_enable(DBG_CAN1_HOLD); + } +#else + if (CAN0 == can_periph) { + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief disable CAN debug freeze + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_debug_freeze_disable(uint32_t can_periph) +{ + CAN_CTL(can_periph) |= CAN_CTL_DFZ; +#ifdef GD32F30X_CL + if (CAN0 == can_periph) { + dbg_periph_disable(DBG_CAN0_HOLD); + } else { + dbg_periph_disable(DBG_CAN1_HOLD); + } +#else + if (CAN0 == can_periph) { + dbg_periph_enable(DBG_CAN0_HOLD); + } +#endif +} + +/*! + \brief enable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_enable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* enable the tcc mode */ + CAN_CTL(can_periph) |= CAN_CTL_TTC; + /* enable time stamp */ + for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { + CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; + } +} + +/*! + \brief disable CAN time trigger mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval none +*/ +void can_time_trigger_mode_disable(uint32_t can_periph) +{ + uint8_t mailbox_number; + + /* disable the TCC mode */ + CAN_CTL(can_periph) &= ~CAN_CTL_TTC; + /* reset TSEN bits */ + for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; + } +} + +/*! + \brief transmit CAN message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlenc: 1 - 7 + \arg tx_data[]: 0x00 - 0xFF + \param[out] none + \retval mailbox_number +*/ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) +{ + uint8_t mailbox_number = CAN_MAILBOX0; + + /* select one empty mailbox */ + if (CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) { + mailbox_number = CAN_MAILBOX0; + } else if (CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) { + mailbox_number = CAN_MAILBOX1; + } else if (CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) { + mailbox_number = CAN_MAILBOX2; + } else { + mailbox_number = CAN_NOMAILBOX; + } + if (CAN_NOMAILBOX == mailbox_number) { + return CAN_NOMAILBOX; + } + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if (CAN_FF_STANDARD == transmit_message->tx_ff) { + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + } else { + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC); + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; + + return mailbox_number; +} + +/*! + \brief get CAN transmit state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] mailbox_number + \arg CAN_MAILBOX(x=0,1,2) + \param[out] none + \retval can_transmit_state_enum +*/ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) +{ + can_transmit_state_enum state = CAN_TRANSMIT_FAILED; + uint32_t val = 0U; + + switch (mailbox_number) { + case CAN_MAILBOX0: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); + break; + case CAN_MAILBOX1: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); + break; + case CAN_MAILBOX2: + val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); + break; + default: + val = CAN_TRANSMIT_FAILED; + break; + } + switch (val) { + /* transmit pending */ + case (CAN_STATE_PENDING): + state = CAN_TRANSMIT_PENDING; + break; + /* transmit succeeded */ + case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + state = CAN_TRANSMIT_OK; + break; + case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + state = CAN_TRANSMIT_OK; + break; + case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + state = CAN_TRANSMIT_OK; + break; + default: + state = CAN_TRANSMIT_FAILED; + break; + } + return state; +} + +/*! + \brief stop CAN transmission + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] mailbox_number + only one parameter can be selected which is shown as below: + \arg CAN_MAILBOXx(x=0,1,2) + \param[out] none + \retval none +*/ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +{ + if (CAN_MAILBOX0 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + } else if (CAN_MAILBOX1 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + } else if (CAN_MAILBOX2 == mailbox_number) { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + } else { + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlenc: 1 - 7 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 + \retval none +*/ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) +{ + /* get the frame format */ + receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); + if (CAN_FF_STANDARD == receive_message->rx_ff) { + /* get standard identifier */ + receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + } else { + /* get extended identifier */ + receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + } + + /* get frame type */ + receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); + /* get recevie data length */ + receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + /* filtering index */ + receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + + /* receive data */ + receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + + /* release FIFO */ + if (CAN_FIFO0 == fifo_number) { + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + } else { + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } +} + +/*! + \brief release FIFO0 + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval none +*/ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) +{ + if (CAN_FIFO0 == fifo_number) { + CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; + } else if (CAN_FIFO1 == fifo_number) { + CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; + } else { + /* illegal parameters */ + } +} + +/*! + \brief CAN receive message length + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] fifo_number + \arg CAN_FIFOx(x=0,1) + \param[out] none + \retval message length +*/ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) +{ + uint8_t val = 0U; + + if (CAN_FIFO0 == fifo_number) { + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + } else if (CAN_FIFO1 == fifo_number) { + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); + } else { + /* illegal parameters */ + } + return val; +} + +/*! + \brief set CAN working mode + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] can_working_mode + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) +{ + ErrStatus flag = ERROR; + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + + if (CAN_MODE_INITIALIZE == working_mode) { + /* disable sleep mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); + /* set initialize mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; + /* wait the acknowledge */ + while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { + timeout--; + } + if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else if (CAN_MODE_NORMAL == working_mode) { + /* enter normal mode */ + CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); + /* wait the acknowledge */ + while ((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { + timeout--; + } + if (0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else if (CAN_MODE_SLEEP == working_mode) { + /* disable initialize mode */ + CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); + /* set sleep mode */ + CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; + /* wait the acknowledge */ + while ((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { + timeout--; + } + if (CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + } else { + flag = ERROR; + } + return flag; +} + +/*! + \brief wake up CAN + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus can_wakeup(uint32_t can_periph) +{ + ErrStatus flag = ERROR; + uint32_t timeout = CAN_TIMEOUT; + + /* wakeup */ + CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; + + while ((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) { + timeout--; + } + if (0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { + flag = ERROR; + } else { + flag = SUCCESS; + } + return flag; +} + +/*! + \brief get CAN error type + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval can_error_enum +*/ +can_error_enum can_error_get(uint32_t can_periph) +{ + can_error_enum error; + error = CAN_ERROR_NONE; + + /* get error type */ + error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U); + return error; +} + +/*! + \brief get CAN receive error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval error number +*/ +uint8_t can_receive_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U); + return val; +} + +/*! + \brief get CAN transmit error number + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[out] none + \retval error number +*/ +uint8_t can_transmit_error_number_get(uint32_t can_periph) +{ + uint8_t val; + + val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U); + return val; +} + +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] interrupt + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] interrupt + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + +/*! + \brief get CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) +{ + if (RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN flags, refer to can_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \param[out] none + \retval none +*/ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag) +{ + CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); +} + +/*! + \brief get CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); + if (ret1 && ret2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CAN interrupt flag state + \param[in] can_periph + \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL + \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \param[out] none + \retval none +*/ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) +{ + CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c new file mode 100644 index 0000000000..8740b63b9e --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c @@ -0,0 +1,126 @@ +/*! + \file gd32f30x_crc.c + \brief CRC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_crc.h" + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_DATA = (uint32_t)0xFFFFFFFFU; + CRC_FDATA = (uint32_t)0x00000000U; + CRC_CTL = (uint32_t)CRC_CTL_RST; +} + +/*! + \brief reset data register to the value of initializaiton data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief CRC calculate a 32-bit data + \param[in] sdata: specify 32-bit data + \param[out] none + \retval 32-bit CRC calculate value +*/ +uint32_t crc_single_data_calculate(uint32_t sdata) +{ + CRC_DATA = sdata; + return (CRC_DATA); +} + +/*! + \brief CRC calculate a 32-bit data array + \param[in] array: pointer to an array of 32 bit data words + \param[in] size: size of the array + \param[out] none + \retval 32-bit CRC calculate value +*/ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) +{ + uint32_t index; + for (index = 0U; index < size; index++) { + CRC_DATA = array[index]; + } + return (CRC_DATA); +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c new file mode 100644 index 0000000000..8a74a5289c --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c @@ -0,0 +1,369 @@ +/*! + \file gd32f30x_ctc.c + \brief CTC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_ctc.h" + +#define CTC_FLAG_MASK ((uint32_t)0x00000700U) + +/*! + \brief reset CTC clock trim controller + \param[in] none + \param[out] none + \retval none +*/ +void ctc_deinit(void) +{ + /* reset CTC */ + rcu_periph_reset_enable(RCU_CTCRST); + rcu_periph_reset_disable(RCU_CTCRST); +} + +/*! + \brief configure the IRC48M trim value + \param[in] ctc_trim_value: 8-bit IRC48M trim value + \param[out] none + \retval none +*/ +void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value) +{ + /* clear TRIMVALUE bits */ + CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); + /* set TRIMVALUE bits */ + CTC_CTL0 |= ((uint32_t)ctc_trim_value << 8); +} + +/*! + \brief generate software reference source sync pulse + \param[in] none + \param[out] none + \retval none +*/ +void ctc_software_refsource_pulse_generate(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; +} + +/*! + \brief configure hardware automatically trim mode + \param[in] ctc_hardmode: + \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable + \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable + \param[out] none + \retval none +*/ +void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); + CTC_CTL0 |= (uint32_t)ctc_hardmode; +} + +/*! + \brief enable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_enable(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; +} + +/*! + \brief disable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_disable(void) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); +} + +/*! + \brief configure reference signal source polarity + \param[in] ctc_polarity: + \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge + \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge + \param[out] none + \retval none +*/ +void ctc_refsource_polarity_config(uint32_t ctc_polarity) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); + CTC_CTL1 |= (uint32_t)ctc_polarity; +} + +/*! + \brief select reference signal source + \param[in] ctc_refs: + \arg CTC_REFSOURCE_GPIO: GPIO is selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected + \arg CTC_REFSOURCE_USBSOF: USBSOF is selected + \param[out] none + \retval none +*/ +void ctc_refsource_signal_select(uint32_t ctc_refs) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); + CTC_CTL1 |= (uint32_t)ctc_refs; +} + +/*! + \brief configure reference signal source prescaler + \param[in] ctc_prescaler: + \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided + \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 + \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 + \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 + \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 + \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 + \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 + \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 + \param[out] none + \retval none +*/ +void ctc_refsource_prescaler_config(uint32_t ctc_prescaler) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); + CTC_CTL1 |= (uint32_t)ctc_prescaler; +} + +/*! + \brief configure clock trim base limit value + \param[in] ctc_limit_value: 8-bit clock trim base limit value + \param[out] none + \retval none +*/ +void ctc_clock_limit_value_config(uint8_t ctc_limit_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); + CTC_CTL1 |= (uint32_t)((uint32_t)ctc_limit_value << 16); +} + +/*! + \brief configure CTC counter reload value + \param[in] ctc_reload_value: 16-bit CTC counter reload value + \param[out] none + \retval none +*/ +void ctc_counter_reload_value_config(uint16_t ctc_reload_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); + CTC_CTL1 |= (uint32_t)ctc_reload_value; +} + +/*! + \brief read CTC counter capture value when reference sync pulse occurred + \param[in] none + \param[out] none + \retval the 16-bit CTC counter capture value +*/ +uint16_t ctc_counter_capture_value_read(void) +{ + uint16_t capture_value = 0U; + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> 16); + return (capture_value); +} + +/*! + \brief read CTC trim counter direction when reference sync pulse occurred + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + \arg SET: CTC trim counter direction is down-counting + \arg RESET: CTC trim counter direction is up-counting +*/ +FlagStatus ctc_counter_direction_read(void) +{ + if (RESET != (CTC_STAT & CTC_STAT_REFDIR)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief read CTC counter reload value + \param[in] none + \param[out] none + \retval the 16-bit CTC counter reload value +*/ +uint16_t ctc_counter_reload_value_read(void) +{ + uint16_t reload_value = 0U; + reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); + return (reload_value); +} + +/*! + \brief read the IRC48M trim value + \param[in] none + \param[out] none + \retval the 8-bit IRC48M trim value +*/ +uint8_t ctc_irc48m_trim_value_read(void) +{ + uint8_t trim_value = 0U; + trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> 8); + return (trim_value); +} + +/*! + \brief enable the CTC interrupt + \param[in] ctc_interrupt: CTC interrupt enable + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_enable(uint32_t ctc_interrupt) +{ + CTC_CTL0 |= (uint32_t)ctc_interrupt; +} + +/*! + \brief disable the CTC interrupt + \param[in] ctc_interrupt: CTC interrupt enable source + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_disable(uint32_t ctc_interrupt) +{ + CTC_CTL0 &= (uint32_t)(~ctc_interrupt); +} + +/*! + \brief get CTC interrupt flag + \param[in] ctc_interrupt: the CTC interrupt flag + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt) +{ + uint32_t interrupt = 0U, intenable = 0U; + + if (ctc_interrupt & CTC_FLAG_MASK) { + intenable = CTC_CTL0 & CTC_CTL0_ERRIE; + } else { + intenable = CTC_CTL0 & ctc_interrupt; + } + interrupt = CTC_STAT & ctc_interrupt; + + if (interrupt && intenable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CTC interrupt flag + \param[in] ctc_interrupt: the CTC interrupt flag + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval none +*/ +void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) +{ + if (ctc_interrupt & CTC_FLAG_MASK) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= ctc_interrupt; + } +} + +/*! + \brief get CTC flag + \param[in] ctc_flag: the CTC flag + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_flag_get(uint32_t ctc_flag) +{ + if (RESET != (CTC_STAT & ctc_flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear CTC flag + \param[in] ctc_flag: the CTC flag + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval none +*/ +void ctc_flag_clear(uint32_t ctc_flag) +{ + if (ctc_flag & CTC_FLAG_MASK) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= ctc_flag; + } +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c new file mode 100644 index 0000000000..e803b43676 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c @@ -0,0 +1,533 @@ +/*! + \file gd32f30x_dac.c + \brief DAC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_dac.h" + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_enable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DEN0; + } else { + DAC_CTL |= DAC_CTL_DEN1; + } +} + +/*! + \brief disable DAC + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_disable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DEN0; + } else { + DAC_CTL &= ~DAC_CTL_DEN1; + } +} + +/*! + \brief enable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_enable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DDMAEN0; + } else { + DAC_CTL |= DAC_CTL_DDMAEN1; + } +} + +/*! + \brief disable DAC DMA function + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval none +*/ +void dac_dma_disable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DDMAEN0; + } else { + DAC_CTL &= ~DAC_CTL_DDMAEN1; + } +} + +/*! + \brief enable DAC output buffer + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DBOFF0; + } else { + DAC_CTL &= ~DAC_CTL_DBOFF1; + } +} + +/*! + \brief disable DAC output buffer + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DBOFF0; + } else { + DAC_CTL |= DAC_CTL_DBOFF1; + } +} + +/*! + \brief enable DAC trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_trigger_enable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL |= DAC_CTL_DTEN0; + } else { + DAC_CTL |= DAC_CTL_DTEN1; + } +} + +/*! + \brief disable DAC trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_trigger_disable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DTEN0; + } else { + DAC_CTL &= ~DAC_CTL_DTEN1; + } +} + +/*! + \brief enable DAC software trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \retval none +*/ +void dac_software_trigger_enable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_SWT |= DAC_SWT_SWTR0; + } else { + DAC_SWT |= DAC_SWT_SWTR1; + } +} + +/*! + \brief disable DAC software trigger + \param[in] dac_periph + \arg DACx(x =0,1) + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(uint32_t dac_periph) +{ + if (DAC0 == dac_periph) { + DAC_SWT &= ~DAC_SWT_SWTR0; + } else { + DAC_SWT &= ~DAC_SWT_SWTR1; + } +} + +/*! + \brief set DAC trigger source + \param[in] dac_periph + \arg DACx(x =0,1) + \param[in] triggersource: external triggers of DAC + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F30X_CL) + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F30X_HD and GD32F30X_XD) + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; + } else { + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << 16); + } +} + +/*! + \brief configure DAC wave mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] wave_mode + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DWM0; + DAC_CTL |= wave_mode; + } else { + DAC_CTL &= ~DAC_CTL_DWM1; + DAC_CTL |= wave_mode << 16; + } +} + +/*! + \brief configure DAC wave bit width + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] bit_width + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= bit_width; + } else { + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= bit_width << 16; + } +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] unmask_bits + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= unmask_bits; + } else { + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= unmask_bits << 16; + } +} + +/*! + \brief configure DAC triangle noise mode + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] amplitude + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +{ + if (DAC0 == dac_periph) { + DAC_CTL &= ~DAC_CTL_DWBW0; + DAC_CTL |= amplitude; + } else { + DAC_CTL &= ~DAC_CTL_DWBW1; + DAC_CTL |= amplitude << 16; + } +} + +/*! + \brief get DAC output value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(uint32_t dac_periph) +{ + uint16_t data = 0U; + if (DAC0 == dac_periph) { + data = (uint16_t)DAC0_DO; + } else { + data = (uint16_t)DAC1_DO; + } + return data; +} + +/*! + \brief enable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL |= (ctl); +} + +/*! + \brief disable DAC concurrent mode + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; + DAC_CTL &= (~ctl); +} + +/*! + \brief enable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_enable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT |= (swt); +} + +/*! + \brief disable DAC concurrent software trigger function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_software_trigger_disable(void) +{ + uint32_t swt = 0U; + swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; + DAC_SWT &= (~swt); +} + +/*! + \brief enable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_enable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL &= (~ctl); +} + +/*! + \brief disable DAC concurrent buffer function + \param[in] none + \param[out] none + \retval none +*/ +void dac_concurrent_output_buffer_disable(void) +{ + uint32_t ctl = 0U; + ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; + DAC_CTL |= (ctl); +} + +/*! + \brief set the DAC specified data holding register value + \param[in] dac_periph + \arg DACx(x=0,1) + \param[in] dac_align + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +{ + if (DAC0 == dac_periph) { + switch (dac_align) { + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } + } else { + switch (dac_align) { + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } + } +} + +/*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch (dac_align) { + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << 16) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << 16) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << 8) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c new file mode 100644 index 0000000000..9e9cc88935 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c @@ -0,0 +1,150 @@ +/*! + \file gd32f30x_dbg.c + \brief DBG driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_dbg.h" + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL0 |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL0 &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_CTL0 |= (uint32_t)dbg_periph; +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_CTL0 &= ~(uint32_t)dbg_periph; +} + +/*! + \brief enable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_enable(void) +{ + DBG_CTL0 |= DBG_CTL0_TRACE_IOEN; +} + +/*! + \brief disable trace pin assignment + \param[in] none + \param[out] none + \retval none +*/ +void dbg_trace_pin_disable(void) +{ + DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; +} + +/*! + \brief trace pin mode selection + \param[in] trace_mode: + \arg TRACE_MODE_ASYNC: trace pin used for async mode + \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 + \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 + \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 + \param[out] none + \retval none +*/ +void dbg_trace_pin_mode_set(uint32_t trace_mode) +{ + DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE; + DBG_CTL0 |= trace_mode; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c new file mode 100644 index 0000000000..5eeeadf724 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c @@ -0,0 +1,680 @@ +/*! + \file gd32f30x_dma.c + \brief DMA driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_dma.h" + +#define DMA_WRONG_HANDLE while(1){} + +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); + +/*! + \brief deinitialize DMA a channel registers + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is deinitialized + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + /* disable DMA a channel */ + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel is initialized + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +#ifdef GD_MBED_USED +void dma_para_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct) +#else +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct) +#endif +{ + uint32_t ctl; + + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + /* configure peripheral base address */ + DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width, */ + ctl = DMA_CHCTL(dma_periph, channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority); + DMA_CHCTL(dma_periph, channelx) = ctl; + + /* configure peripheral increasing mode */ + if (DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if (DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc) { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if (DMA_PERIPHERAL_TO_MEMORY == init_struct.direction) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set peripheral base address + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHPADDR(dma_periph, channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set memory base address + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHMADDR(dma_periph, channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to set number + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval uint32_t: the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + return (uint32_t)DMA_CHCNT(dma_periph, channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] priority: priority Level of this channel + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] mwidth: transfer data width of memory + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief configure transfer data size of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] pwidth: transfer data width of peripheral + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(dma_periph, channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(dma_periph, channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] direction: specify the direction of data transfer + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + if (DMA_PERIPHERAL_TO_MEMORY == direction) { + DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + if (RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))) { + reval = SET; + } else { + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch (flag) { + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + default: + DMA_WRONG_HANDLE + } + + if (interrupt_flag && interrupt_enable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to enbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to disbale + one or more parameters can be selected which are shown as below + \arg DMA_INT_FTF: channel full transfer finish interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_ERR: channel error interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { + DMA_WRONG_HANDLE + } + + DMA_CHCTL(dma_periph, channelx) &= ~source; +} + +/*! + \brief check whether peripheral and channels match + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) +{ + ErrStatus val = SUCCESS; + + if (DMA1 == dma_periph) { + if (channelx > DMA_CH4) { + val = ERROR; + } + } + + return val; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c new file mode 100644 index 0000000000..b0b74dadde --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c @@ -0,0 +1,3663 @@ +/*! + \file gd32f30x_enet.c + \brief ENET driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_enet.h" + +#ifdef GD32F30X_CL + +#if defined (__CC_ARM) /*!< ARM compiler */ +__align(4) +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +__align(4) +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +__align(4) +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +__align(4) +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined ( __ICCARM__ ) /*!< IAR compiler */ +#pragma data_alignment=4 +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ +#pragma data_alignment=4 +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ +#pragma data_alignment=4 +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ +#pragma data_alignment=4 +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ + +#elif defined (__GNUC__) /* GNU Compiler */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET transmit buffer */ + +#endif /* __CC_ARM */ + +/* global transmit and receive descriptors pointers */ +enet_descriptors_struct *dma_current_txdesc; +enet_descriptors_struct *dma_current_rxdesc; + +/* structure pointer of ptp descriptor for normal mode */ +enet_descriptors_struct *dma_current_ptp_txdesc = NULL; +enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; + +/* init structure parameters for ENET initialization */ +static enet_initpara_struct enet_initpara = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +static uint32_t enet_unknow_err = 0; +/* array of register offset for debug information get */ +static const uint16_t enet_reg_tab[] = { + 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, + 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, + + 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + + 0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, + 0x104C, 0x1050, 0x1054 +}; + +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + +/*! + \brief deinitialize the ENET, and reset structure parameters for ENET initialization + \param[in] none + \param[out] none + \retval none +*/ +void enet_deinit(void) +{ + rcu_periph_reset_enable(RCU_ENETRST); + rcu_periph_reset_disable(RCU_ENETRST); + enet_initpara_reset(); +} + +/*! + \brief configure the parameters which are usually less cared for initialization + note -- this function must be called before enet_init(), otherwise + configuration will be no effect + \param[in] option: different function option, which is related to several parameters, + only one parameter can be selected which is shown as below, refer to enet_option_enum + \arg FORWARD_OPTION: choose to configure the frame forward related parameters + \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters + \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters + \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters + \arg STORE_OPTION: choose to configure the store forward mode related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg VLAN_OPTION: choose to configure vlan related parameters + \arg FLOWCTL_OPTION: choose to configure flow control related parameters + \arg HASHH_OPTION: choose to configure hash high + \arg HASHL_OPTION: choose to configure hash low + \arg FILTER_OPTION: choose to configure frame filter related parameters + \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters + \arg TIMER_OPTION: choose to configure time counter related parameters + \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below + FORWARD_OPTION related parameters: + - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; + - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; + - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; + - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . + DMABUS_OPTION related parameters: + - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; + - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; + - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; + DMA_MAXBURST_OPTION related parameters: + - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ + ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ + ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ + ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ + ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; + - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ + ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ + ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ + ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ + ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; + - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; + DMA_ARBITRATION_OPTION related parameters: + - ENET_ARBITRATION_RXPRIORTX + - ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ + ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. + STORE_OPTION related parameters: + - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; + - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; + - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ + ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; + - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ + ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ + ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ + ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . + DMA_OPTION related parameters: + - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; + - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE ; + - ENET_ENHANCED_DESCRIPTOR/ ENET_NORMAL_DESCRIPTOR . + VLAN_OPTION related parameters: + - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; + - MAC_VLT_VLTI(regval) . + FLOWCTL_OPTION related parameters: + - MAC_FCTL_PTM(regval) ; + - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; + - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; + - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; + - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . + HASHH_OPTION related parameters: + - 0x0~0xFFFF FFFFU + HASHL_OPTION related parameters: + - 0x0~0xFFFF FFFFU + FILTER_OPTION related parameters: + - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ + ENET_SRC_FILTER_DISABLE ; + - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; + - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ + ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; + - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ + ENET_UNICAST_FILTER_PERFECT ; + - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ + ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . + HALFDUPLEX_OPTION related parameters: + - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; + - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; + - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; + - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ + ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; + - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . + TIMER_OPTION related parameters: + - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; + - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; + INTERFRAMEGAP_OPTION related parameters: + - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ + ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ + ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ + ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . + \param[out] none + \retval none +*/ +void enet_initpara_config(enet_option_enum option, uint32_t para) +{ + switch (option) { + case FORWARD_OPTION: + /* choose to configure forward_frame, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; + enet_initpara.forward_frame = para; + break; + case DMABUS_OPTION: + /* choose to configure dmabus_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; + enet_initpara.dmabus_mode = para; + break; + case DMA_MAXBURST_OPTION: + /* choose to configure dma_maxburst, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; + enet_initpara.dma_maxburst = para; + break; + case DMA_ARBITRATION_OPTION: + /* choose to configure dma_arbitration, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; + enet_initpara.dma_arbitration = para; + break; + case STORE_OPTION: + /* choose to configure store_forward_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)STORE_OPTION; + enet_initpara.store_forward_mode = para; + break; + case DMA_OPTION: + /* choose to configure dma_function, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_OPTION; + +#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE + para &= ~ENET_ENHANCED_DESCRIPTOR; +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + + enet_initpara.dma_function = para; + break; + case VLAN_OPTION: + /* choose to configure vlan_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; + enet_initpara.vlan_config = para; + break; + case FLOWCTL_OPTION: + /* choose to configure flow_control, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; + enet_initpara.flow_control = para; + break; + case HASHH_OPTION: + /* choose to configure hashtable_high, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; + enet_initpara.hashtable_high = para; + break; + case HASHL_OPTION: + /* choose to configure hashtable_low, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; + enet_initpara.hashtable_low = para; + break; + case FILTER_OPTION: + /* choose to configure framesfilter_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; + enet_initpara.framesfilter_mode = para; + break; + case HALFDUPLEX_OPTION: + /* choose to configure halfduplex_param, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; + enet_initpara.halfduplex_param = para; + break; + case TIMER_OPTION: + /* choose to configure timer_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; + enet_initpara.timer_config = para; + break; + case INTERFRAMEGAP_OPTION: + /* choose to configure interframegap, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; + enet_initpara.interframegap = para; + break; + default: + break; + } +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters and the less cared + parameters + \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation + \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex + \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex + \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex + \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex + \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII + \param[in] checksum: IP frame checksum offload function, only one parameter can be selected + which is shown as below, refer to enet_mediamode_enum + \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function + \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function + \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame + with only payload error but no other errors will not be dropped + \param[in] recept: frame filter function, only one parameter can be selected + which is shown as below, refer to enet_frmrecept_enum + \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled + \arg ENET_RECEIVEALL: all received frame are forwarded to application + \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames + \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) +{ + uint32_t reg_value = 0U, reg_temp = 0U, temp = 0U; + uint32_t media_temp = 0U; + uint32_t timeout = 0U; + uint16_t phy_value = 0U; + ErrStatus phy_state = ERROR, enet_state = ERROR; + + /* PHY interface configuration, configure SMI clock and reset PHY chip */ + if (ERROR == enet_phy_config()) { + _ENET_DELAY_(PHY_RESETDELAY); + if (ERROR == enet_phy_config()) { + return enet_state; + } + } + /* initialize ENET peripheral with generally concerned parameters */ + enet_default_init(); + + /* 1st, configure mediamode */ + media_temp = (uint32_t)mediamode; + /* if is PHY auto negotiation */ + if ((uint32_t)ENET_AUTO_NEGOTIATION == media_temp) { + /* wait for PHY_LINKED_STATUS bit be set */ + do { + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_LINKED_STATUS; + timeout++; + } while ((RESET == phy_value) && (timeout < PHY_READ_TO)); + /* return ERROR due to timeout */ + if (PHY_READ_TO == timeout) { + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* enable auto-negotiation */ + phy_value = PHY_AUTONEGOTIATION; + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if (!phy_state) { + /* return ERROR due to write timeout */ + return enet_state; + } + + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ + do { + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_AUTONEGO_COMPLETE; + timeout++; + } while ((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + /* return ERROR due to timeout */ + if (PHY_READ_TO == timeout) { + return enet_state; + } + /* reset timeout counter */ + timeout = 0U; + + /* read the result of the auto-negotiation */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + /* configure the duplex mode of MAC following the auto-negotiation result */ + if ((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { + media_temp = ENET_MODE_FULLDUPLEX; + } else { + media_temp = ENET_MODE_HALFDUPLEX; + } + /* configure the communication speed of MAC following the auto-negotiation result */ + if ((uint16_t)RESET != (phy_value & PHY_SPEED_STATUS)) { + media_temp |= ENET_SPEEDMODE_10M; + } else { + media_temp |= ENET_SPEEDMODE_100M; + } + } else { + phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); + phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if (!phy_state) { + /* return ERROR due to write timeout */ + return enet_state; + } + /* PHY configuration need some time */ + _ENET_DELAY_(PHY_CONFIGDELAY); + } + /* after configuring the PHY, use mediamode to configure registers */ + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM | ENET_MAC_CFG_LBM)); + reg_value |= media_temp; + ENET_MAC_CFG = reg_value; + + + /* 2st, configure checksum */ + if (RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { + ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~ENET_DMA_CTL_DTCERFD; + reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); + ENET_DMA_CTL = reg_value; + } + + /* 3rd, configure recept */ + ENET_MAC_FRMF |= (uint32_t)recept; + + /* 4th, configure different function options */ + /* configure forward_frame related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { + reg_temp = enet_initpara.forward_frame; + + reg_value = ENET_MAC_CFG; + temp = reg_temp; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD)); + temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); + reg_value |= temp; + ENET_MAC_CFG = reg_value; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2); + reg_value |= (temp >> 2); + ENET_DMA_CTL = reg_value; + } + + /* configure dmabus_mode related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { + temp = enet_initpara.dmabus_mode; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ + | ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_maxburst related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { + temp = enet_initpara.dma_maxburst; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RXDP | ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure dma_arbitration related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { + temp = enet_initpara.dma_arbitration; + + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure store_forward_mode related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { + temp = enet_initpara.store_forward_mode; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD | ENET_DMA_CTL_RTHC | ENET_DMA_CTL_TTHC); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + } + + /* configure dma_function related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) { + reg_temp = enet_initpara.dma_function; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF)); + temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + + reg_value = ENET_DMA_BCTL; + temp = reg_temp; + /* configure ENET_DMA_BCTL register */ + reg_value &= (~ENET_DMA_BCTL_DFM); + temp &= ENET_DMA_BCTL_DFM; + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } + + /* configure vlan_config related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) { + reg_temp = enet_initpara.vlan_config; + + reg_value = ENET_MAC_VLT; + /* configure ENET_MAC_VLT register */ + reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); + reg_value |= reg_temp; + ENET_MAC_VLT = reg_value; + } + + /* configure flow_control related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) { + reg_temp = enet_initpara.flow_control; + + reg_value = ENET_MAC_FCTL; + temp = reg_temp; + /* configure ENET_MAC_FCTL register */ + reg_value &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + reg_value |= temp; + ENET_MAC_FCTL = reg_value; + + reg_value = ENET_MAC_FCTH; + temp = reg_temp; + /* configure ENET_MAC_FCTH register */ + reg_value &= ~(ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD) << 8); + reg_value |= (temp >> 8); + ENET_MAC_FCTH = reg_value; + } + + /* configure hashtable_high related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) { + ENET_MAC_HLH = enet_initpara.hashtable_high; + } + + /* configure hashtable_low related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) { + ENET_MAC_HLL = enet_initpara.hashtable_low; + } + + /* configure framesfilter_mode related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) { + reg_temp = enet_initpara.framesfilter_mode; + + reg_value = ENET_MAC_FRMF; + /* configure ENET_MAC_FRMF register */ + reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + reg_value |= reg_temp; + ENET_MAC_FRMF = reg_value; + } + + /* configure halfduplex_param related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) { + reg_temp = enet_initpara.halfduplex_param; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure timer_config related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) { + reg_temp = enet_initpara.timer_config; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + /* configure interframegap related registers */ + if (RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) { + reg_temp = enet_initpara.interframegap; + + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~ENET_MAC_CFG_IGBS; + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } + + enet_state = SUCCESS; + return enet_state; +} + +/*! + \brief reset all core internal registers located in CLK_TX and CLK_RX + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_software_reset(void) +{ + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + uint32_t dma_flag; + + /* reset all core internal registers located in CLK_TX and CLK_RX */ + ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; + + /* wait for reset operation complete */ + do { + dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); + timeout++; + } while ((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + + /* reset operation complete */ + if (RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief check receive frame valid and return frame size + \param[in] none + \param[out] none + \retval size of received frame: 0x0 - 0x3FFF +*/ +uint32_t enet_rxframe_size_get(void) +{ + uint32_t size = 0U; + uint32_t status; + + /* get rdes0 information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + + /* if the desciptor is owned by DMA */ + if ((uint32_t)RESET != (status & ENET_RDES0_DAV)) { + return 0U; + } + + /* if has any error, or the frame uses two or more descriptors */ + if ((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && + ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#else + /* if is an ethernet-type frame, and IP frame payload error occurred */ + if ((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))) { + /* drop current receive frame */ + enet_rxframe_drop(); + + return 1U; + } +#endif + /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ + if ((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))) { + /* get the size of the received data including CRC */ + size = GET_RDES0_FRML(status); + /* substract the CRC size */ + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if ((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + } else { + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; + } + + /* return packet size */ + return size; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode */ + desc_status = ENET_TDES0_TCHM; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for (num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if (num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + dma_current_ptp_rxdesc = NULL; + dma_current_ptp_txdesc = NULL; + + /* configure each descriptor */ + for (num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if (num == (count - 1U)) { + if (ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief handle current received frame data to application buffer + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the received frame data + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + + /* if buffer pointer is null, indicates that users has copied data in application */ + if (NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if ((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status); + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if ((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if (size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for (offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); + } + + } else { + /* return ERROR */ + return ERROR; + } + } + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief handle application buffer data to transmit it + \param[in] buffer: pointer to the frame data to be transmitted, + note -- if the input is NULL, user should handle the data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) +{ + uint32_t offset = 0U; + uint32_t dma_tbu_flag, dma_tu_flag; + + /* the descriptor is busy due to own by the DMA */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if (length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if (NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for (offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } + } + + return SUCCESS; +} + +/*! + \brief configure the transmit IP frame checksum offload calculation and insertion + \param[in] desc: the descriptor pointer which users want to configure + \param[in] checksum: IP frame checksum configuration + only one parameter can be selected which is shown as below + \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled + \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled + \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header + \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated + \param[out] none + \retval none +*/ +void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) +{ + desc->status &= ~ENET_TDES0_CM; + desc->status |= checksum; +} + +/*! + \brief ENET Tx and Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_enable(void) +{ + enet_tx_enable(); + enet_rx_enable(); +} + +/*! + \brief ENET Tx and Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_disable(void) +{ + enet_tx_disable(); + enet_rx_disable(); +} + +/*! + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: set MAC address 0 filter + \arg ENET_MAC_ADDRESS1: set MAC address 1 filter + \arg ENET_MAC_ADDRESS2: set MAC address 2 filter + \arg ENET_MAC_ADDRESS3: set MAC address 3 filter + \param[in] paddr: the buffer pointer which stores the MAC address + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \param[out] none + \retval none +*/ +void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); + REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); +} + +/*! + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS0: get MAC address 0 filter + \arg ENET_MAC_ADDRESS1: get MAC address 1 filter + \arg ENET_MAC_ADDRESS2: get MAC address 2 filter + \arg ENET_MAC_ADDRESS3: get MAC address 3 filter + \param[out] paddr: the buffer pointer which is stored the MAC address + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + \retval none +*/ +void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) +{ + paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); + paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); + paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); + paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); + paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); + paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); +} + +/*! + \brief get the ENET MAC/MSC/PTP/DMA status flag + \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, + only one parameter can be selected which is shown as below + \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_WUM: WUM status flag + \arg ENET_MAC_FLAG_MSC: MSC status flag + \arg ENET_MAC_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag + \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag + \arg ENET_PTP_FLAG_TTM: target time match flag + \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_FLAG_TS: transmit status flag + \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_FLAG_RO: receive overflow status flag + \arg ENET_DMA_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_FLAG_RS: receive status flag + \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_FLAG_ET: early transmit status flag + \arg ENET_DMA_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_FLAG_ER: early receive status flag + \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag + \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag + \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag + \arg ENET_DMA_FLAG_MSC: MSC status flag + \arg ENET_DMA_FLAG_WUM: WUM status flag + \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_flag_get(enet_flag_enum enet_flag) +{ + if (RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the ENET DMA status flag + \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear + \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear + \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear + \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear + \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear + \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear + \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear + \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear + \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear + \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear + \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear + \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear + \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear + \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear + \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \param[out] none + \retval none +*/ +void enet_flag_clear(enet_flag_clear_enum enet_flag) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); +} + +/*! + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_enable(enet_int_enum enet_int) +{ + if (DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_disable(enet_int_enum enet_int) +{ + if (DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_FLAG_WUM: WUM status flag + \arg ENET_MAC_INT_FLAG_MSC: MSC status flag + \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag + \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_INT_FLAG_TS: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS: receive status flag + \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER: early receive status flag + \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_INT_FLAG_MSC: MSC status flag + \arg ENET_DMA_INT_FLAG_WUM: WUM status flag + \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) +{ + if (RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag + \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag + \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag + \param[out] none + \retval none +*/ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); +} + +/*! + \brief ENET Tx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_TEN; + enet_txfifo_flush(); + ENET_DMA_CTL |= ENET_DMA_CTL_STE; +} + +/*! + \brief ENET Tx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_tx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; + enet_txfifo_flush(); + ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; +} + +/*! + \brief ENET Rx function enable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_enable(void) +{ + ENET_MAC_CFG |= ENET_MAC_CFG_REN; + ENET_DMA_CTL |= ENET_DMA_CTL_SRE; +} + +/*! + \brief ENET Rx function disable (include MAC and DMA module) + \param[in] none + \param[out] none + \retval none +*/ +void enet_rx_disable(void) +{ + ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; + ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; +} + +/*! + \brief put registers value into the application buffer + \param[in] type: register type which will be get, refer to enet_registers_type_enum, + only one parameter can be selected which is shown as below + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT + \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL + \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR + \param[in] num: the number of registers that the user want to get + \param[out] preg: the application buffer pointer for storing the register value + \retval none +*/ +void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) +{ + uint32_t offset = 0U, max = 0U, limit = 0U; + + offset = (uint32_t)type; + max = (uint32_t)type + num; + limit = sizeof(enet_reg_tab) / sizeof(uint16_t); + + /* prevent element in this array is out of range */ + if (max > limit) { + max = limit; + } + + for (; offset < max; offset++) { + /* get value of the corresponding register */ + *preg = REG32((ENET) + enet_reg_tab[offset]); + preg++; + } +} + +/*! + \brief get the enet debug status from the debug register + \param[in] mac_debug: enet debug status, + only one parameter can be selected which is shown as below + \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state + \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status + \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation + \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status + \arg ENET_RXFIFO_STATE: RxFIFO state + \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state + \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter + \arg ENET_PAUSE_CONDITION_STATUS: pause condition status + \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status + \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation + \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty + \arg ENET_TXFIFO_FULL: TxFIFO is full + \param[out] none + \retval value of the status users want to get +*/ +uint32_t enet_debug_status_get(uint32_t mac_debug) +{ + uint32_t temp_state = 0U; + + switch (mac_debug) { + case ENET_RX_ASYNCHRONOUS_FIFO_STATE: + temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_STATE: + temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); + break; + case ENET_MAC_TRANSMITTER_STATUS: + temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); + break; + case ENET_TXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); + break; + default: + if (RESET != (ENET_MAC_DBG & mac_debug)) { + temp_state = 0x1U; + } + break; + } + return temp_state; +} + +/*! + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable + \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_enable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter + \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter + \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter + \param[out] none + \retval none +*/ +void enet_address_filter_disable(enet_macaddress_enum mac_addr) +{ + REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; +} + +/*! + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, + only one parameter can be selected which is shown as below + \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter + \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter + \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter + \param[in] addr_mask: select which MAC address bytes will be mask, + one or more parameters can be selected which are shown as below + \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits + \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits + \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits + \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits + \param[in] filter_type: select which MAC address filter type will be selected, + only one parameter can be selected which is shown as below + \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame + \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame + \param[out] none + \retval none +*/ +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) +{ + uint32_t reg; + + /* get the address filter register value which is to be configured */ + reg = REG32(ENET_ADDRH_BASE + mac_addr); + + /* clear and configure the address filter register */ + reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); + reg |= (addr_mask | filter_type); + REG32(ENET_ADDRH_BASE + mac_addr) = reg; +} + +/*! + \brief PHY interface configuration (configure SMI clock and reset PHY chip) + \param[in] none + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_config(void) +{ + uint32_t ahbclk; + uint32_t reg; + uint16_t phy_value; + ErrStatus enet_state = ERROR; + + /* clear the previous MDC clock */ + reg = ENET_MAC_PHY_CTL; + reg &= ~ENET_MAC_PHY_CTL_CLR; + + /* get the HCLK frequency */ + ahbclk = rcu_clock_freq_get(CK_AHB); + + /* configure MDC clock according to HCLK frequency range */ + if (ENET_RANGE(ahbclk, 20000000U, 35000000U)) { + reg |= ENET_MDC_HCLK_DIV16; + } else if (ENET_RANGE(ahbclk, 35000000U, 60000000U)) { + reg |= ENET_MDC_HCLK_DIV26; + } else if (ENET_RANGE(ahbclk, 60000000U, 100000000U)) { + reg |= ENET_MDC_HCLK_DIV42; + } else if ((ENET_RANGE(ahbclk, 100000000U, 120000000U)) || (120000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV62; + } else { + return enet_state; + } + ENET_MAC_PHY_CTL = reg; + + /* reset PHY */ + phy_value = PHY_RESET; + if (ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + return enet_state; + } + /* PHY reset need some time */ + _ENET_DELAY_(ENET_DELAY_TO); + + /* check whether PHY reset is complete */ + if (ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + return enet_state; + } + + /* PHY reset complete */ + if (RESET == (phy_value & PHY_RESET)) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief write to / read from a PHY register + \param[in] direction: only one parameter can be selected which is shown as below + \arg ENET_PHY_WRITE: write data to phy register + \arg ENET_PHY_READ: read data from phy register + \param[in] phy_address: 0x0 - 0x1F + \param[in] phy_reg: 0x0 - 0x1F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) +{ + uint32_t reg, phy_flag; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* configure ENET_MAC_PHY_CTL with write/read operation */ + reg = ENET_MAC_PHY_CTL; + reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + + /* if do the write operation, write value to the register */ + if (ENET_PHY_WRITE == direction) { + ENET_MAC_PHY_DATA = *pvalue; + } + + /* do PHY write/read operation, and wait the operation complete */ + ENET_MAC_PHY_CTL = reg; + do { + phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); + timeout++; + } while ((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + + /* write/read operation complete */ + if (RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) { + enet_state = SUCCESS; + } + + /* if do the read operation, get value from the register */ + if (ENET_PHY_READ == direction) { + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + } + + return enet_state; +} + +/*! + \brief enable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_enable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* enable the PHY loopback mode */ + temp_phy |= PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief disable the loopback function of PHY chip + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_phyloopback_disable(void) +{ + uint16_t temp_phy = 0U; + ErrStatus phy_state = ERROR; + + /* get the PHY configuration to update it */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + /* disable the PHY loopback mode */ + temp_phy &= (uint16_t)~PHY_LOOPBACK; + + /* update the PHY control register with the new configuration */ + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + + return phy_state; +} + +/*! + \brief enable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames + \param[out] none + \retval none +*/ +void enet_forward_feature_enable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG |= mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL |= (mask >> 2); +} + +/*! + \brief disable ENET forward feature + \param[in] feature: the feature of ENET forward mode, + one or more parameters can be selected which are shown as below + \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function + \arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC + \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_forward_feature_disable(uint32_t feature) +{ + uint32_t mask; + + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); + ENET_MAC_CFG &= ~mask; + + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); + ENET_DMA_CTL &= ~(mask >> 2); +} + +/*! + \brief enable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_enable(uint32_t feature) +{ + ENET_MAC_FRMF |= feature; +} + +/*! + \brief disable ENET fliter feature + \param[in] feature: the feature of ENET fliter mode, + one or more parameters can be selected which are shown as below + \arg ENET_SRC_FILTER: filter source address function + \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function + \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function + \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function + \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function + \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function + \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function + \param[out] none + \retval none +*/ +void enet_fliter_feature_disable(uint32_t feature) +{ + ENET_MAC_FRMF &= ~feature; +} + +/*! + \brief generate the pause frame, ENET will send pause frame after enable transmit flow control + this function only use in full-dulex mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state = ERROR; + uint32_t temp = 0U; + + /* in full-duplex mode, must make sure this bit is 0 before writing register */ + temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; + if (RESET == temp) { + ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; + enet_state = SUCCESS; + } + return enet_state; +} + +/*! + \brief configure the pause frame detect type + \param[in] detect: pause frame detect type, + only one parameter can be selected which is shown as below + \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also + use the MAC0 address to detecting pause frame + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + in IEEE802.3 can be detected + \param[out] none + \retval none +*/ +void enet_pauseframe_detect_config(uint32_t detect) +{ + ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; + ENET_MAC_FCTL |= detect; +} + +/*! + \brief configure the pause frame parameters + \param[in] pausetime: pause time in transmit pause control frame + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, + this value must make sure to be less than configured pause time, only one parameter can be + selected which is shown as below + \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times + \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times + \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times + \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times + \param[out] none + \retval none +*/ +void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) +{ + ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); + ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); +} + +/*! + \brief configure the threshold of the flow control(deactive and active threshold) + \param[in] deactive: the threshold of the deactive flow control, this value + should always be less than active flow control value, only one + parameter can be selected which is shown as below + \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[in] active: the threshold of the active flow control, only one parameter + can be selected which is shown as below + \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes + \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes + \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes + \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes + \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes + \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes + \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes + \param[out] none + \retval none +*/ +void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) +{ + ENET_MAC_FCTH = ((deactive | active) >> 8); +} + +/*! + \brief enable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_enable(uint32_t feature) +{ + if (RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { + ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL |= feature; +} + +/*! + \brief disable ENET flow control feature + \param[in] feature: the feature of ENET flow control mode + one or more parameters can be selected which are shown as below + \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function + \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC + \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it + \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) + \param[out] none + \retval none +*/ +void enet_flowcontrol_feature_disable(uint32_t feature) +{ + if (RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { + ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; + } + feature &= ~ENET_ZERO_QUANTA_PAUSE; + ENET_MAC_FCTL &= ~feature; +} + +/*! + \brief get the dma transmit/receive process state + \param[in] direction: choose the direction of dma process which users want to check, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: dma transmit process + \arg ENET_DMA_RX: dma receive process + \param[out] none + \retval state of dma process, the value range shows below: + ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, + ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, + ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, + ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING +*/ +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) +{ + uint32_t reval; + reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); + return reval; +} + +/*! + \brief poll the DMA transmission/reception enable by writing any value to the + ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception + \param[in] direction: choose the direction of DMA process which users want to resume, + refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA transmit process + \arg ENET_DMA_RX: DMA receive process + \param[out] none + \retval none +*/ +void enet_dmaprocess_resume(enet_dmadirection_enum direction) +{ + if (ENET_DMA_TX == direction) { + ENET_DMA_TPEN = 0U; + } else { + ENET_DMA_RPEN = 0U; + } +} + +/*! + \brief check and recover the Rx process + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxprocess_check_recovery(void) +{ + uint32_t status; + + /* get DAV information of current RxDMA descriptor */ + status = dma_current_rxdesc->status; + status &= ENET_RDES0_DAV; + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with + receive descriptor address pointer updated by RxDMA controller */ + if ((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && + (ENET_RDES0_DAV == status)) { + dma_current_rxdesc = (enet_descriptors_struct *)ENET_DMA_CRDADDR; + } +} + +/*! + \brief flush the ENET transmit FIFO, and wait until the flush operation completes + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus enet_txfifo_flush(void) +{ + uint32_t flush_state; + uint32_t timeout = 0U; + ErrStatus enet_state = ERROR; + + /* set the FTF bit for flushing transmit FIFO */ + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + /* wait until the flush operation completes */ + do { + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + timeout++; + } while ((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if (RESET == flush_state) { + enet_state = SUCCESS; + } + + return enet_state; +} + +/*! + \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, + only one parameter can be selected which is shown as below + \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table + \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by + the RxDMA controller + \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller + \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table + \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by + the TxDMA controller + \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller + \param[out] none + \retval address value +*/ +uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) +{ + uint32_t reval = 0U; + + reval = REG32((ENET) + (uint32_t)addr_get); + return reval; +} + +/*! + \brief get the Tx or Rx descriptor information + \param[in] desc: the descriptor pointer which users want to get information + \param[in] info_get: the descriptor information type which is selected, + only one parameter can be selected which is shown as below + \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size + \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size + \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer + \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted + \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame + \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame + \param[out] none + \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter +*/ +uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch (info_get) { + case RXDESC_BUFFER_1_SIZE: + reval = GET_RDES1_RB1S(desc->control_buffer_size); + break; + case RXDESC_BUFFER_2_SIZE: + reval = GET_RDES1_RB2S(desc->control_buffer_size); + break; + case RXDESC_FRAME_LENGTH: + reval = GET_RDES0_FRML(desc->status); + reval = reval - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if ((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))) { + reval = reval + 4U; + } + break; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_COLLISION_COUNT: + reval = GET_TDES0_COCNT(desc->status); + break; + default: + break; + } + return reval; +} + +/*! + \brief get the number of missed frames during receiving + \param[in] none + \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO + \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller + \retval none +*/ +void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) +{ + uint32_t temp_counter = 0U; + + temp_counter = ENET_DMA_MFBOCNT; + *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); + *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); +} + +/*! + \brief get the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_UFE: underflow error + \arg ENET_TDES0_EXD: excessive deferral + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_ECO: excessive collision + \arg ENET_TDES0_LCO: late collision + \arg ENET_TDES0_NCA: no carrier + \arg ENET_TDES0_LCA: loss of carrier + \arg ENET_TDES0_IPPE: IP payload error + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_JT: jabber timeout + \arg ENET_TDES0_ES: error summary + \arg ENET_TDES0_IPHE: IP header error + \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + + \arg ENET_RDES0_PCERR: payload checksum error + \arg ENET_RDES0_EXSV: extended status valid + \arg ENET_RDES0_CERR: CRC error + \arg ENET_RDES0_DBERR: dribble bit error + \arg ENET_RDES0_RERR: receive error + \arg ENET_RDES0_RWDT: receive watchdog timeout + \arg ENET_RDES0_FRMT: frame type + \arg ENET_RDES0_LCO: late collision + \arg ENET_RDES0_IPHERR: IP frame header error + \arg ENET_RDES0_TSV: timestamp valid + \arg ENET_RDES0_LDES: last descriptor + \arg ENET_RDES0_FDES: first descriptor + \arg ENET_RDES0_VTAG: VLAN tag + \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_LERR: length error + \arg ENET_RDES0_SAFF: SA filter fail + \arg ENET_RDES0_DERR: descriptor error + \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_DAFF: destination address filter fail + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + FlagStatus enet_flag = RESET; + + if ((uint32_t)RESET != (desc->status & desc_flag)) { + enet_flag = SET; + } + + return enet_flag; +} + +/*! + \brief set the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to set flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status |= desc_flag; +} + +/*! + \brief clear the bit flag of ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to clear flag + \param[in] desc_flag: the bit flag of ENET DMA descriptor, + only one parameter can be selected which is shown as below + \arg ENET_TDES0_VFRM: VLAN frame + \arg ENET_TDES0_FRMF: frame flushed + \arg ENET_TDES0_TCHM: the second address chained mode + \arg ENET_TDES0_TERM: transmit end of ring mode + \arg ENET_TDES0_TTSEN: transmit timestamp function enable + \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DCRC: disable CRC + \arg ENET_TDES0_FSG: first segment + \arg ENET_TDES0_LSG: last segment + \arg ENET_TDES0_INTC: interrupt on completion + \arg ENET_TDES0_DAV: DAV bit + \arg ENET_RDES0_DAV: descriptor available + \param[out] none + \retval none +*/ +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) +{ + desc->status &= ~desc_flag; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \param[in] desc: the descriptor pointer which users want to configure + \param[out] none + \retval none +*/ +void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc) +{ + desc->control_buffer_size &= ~ENET_RDES1_DINTC; +} + +/*! + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \param[in] desc: the descriptor pointer which users want to configure + \param[in] delay_time: delay a time of 256*delay_time HCLK, this value must be between 0 and 0xFF + \param[out] none + \retval none +*/ +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time) +{ + desc->control_buffer_size |= ENET_RDES1_DINTC; + ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time); +} + +/*! + \brief drop current receive frame + \param[in] none + \param[out] none + \retval none +*/ +void enet_rxframe_drop(void) +{ + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* chained mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + if (NULL != dma_current_ptp_rxdesc) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if (0U != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + } else { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } + + } else { + /* ring mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + if (NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if (NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc++; + } + } + } +} + +/*! + \brief enable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_enable(uint32_t feature) +{ + ENET_DMA_CTL |= feature; +} + +/*! + \brief disable DMA feature + \param[in] feature: the feature of DMA mode, + one or more parameters can be selected which are shown as below + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function + \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function + \param[out] none + \retval none +*/ +void enet_dma_feature_disable(uint32_t feature) +{ + ENET_DMA_CTL &= ~feature; +} + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +/*! + \brief get the bit of extended status flag in ENET DMA descriptor + \param[in] desc: the descriptor pointer which users want to get the extended status flag + \param[in] desc_status: the extended status want to get, + only one parameter can be selected which is shown as below + \arg ENET_RDES4_IPPLDT: IP frame payload type + \arg ENET_RDES4_IPHERR: IP frame header error + \arg ENET_RDES4_IPPLDERR: IP frame payload error + \arg ENET_RDES4_IPCKSB: IP frame checksum bypassed + \arg ENET_RDES4_IPF4: IP frame in version 4 + \arg ENET_RDES4_IPF6: IP frame in version 6 + \arg ENET_RDES4_PTPMT: PTP message type + \arg ENET_RDES4_PTPOEF: PTP on ethernet frame + \arg ENET_RDES4_PTPVF: PTP version format + \param[out] none + \retval value of extended status +*/ +uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) +{ + uint32_t reval = 0xFFFFFFFFU; + + switch (desc_status) { + case ENET_RDES4_IPPLDT: + reval = GET_RDES4_IPPLDT(desc->extended_status); + break; + case ENET_RDES4_PTPMT: + reval = GET_RDES4_PTPMT(desc->extended_status); + break; + default: + if ((uint32_t)RESET != (desc->extended_status & desc_status)) { + reval = 1U; + } else { + reval = 0U; + } + } + + return reval; +} + +/*! + \brief configure descriptor to work in enhanced mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_enhanced_mode(void) +{ + ENET_DMA_BCTL |= ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configuration each descriptor */ + for (num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if (num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + } +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[out] none + \retval none +*/ +void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc; + enet_descriptors_struct *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* set buffer1 size */ + desc_bufsize = ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + } + + /* configure each descriptor */ + for (num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if (num == (count - 1U)) { + if (ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + } +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + uint32_t timeout = 0U; + uint32_t rdes0_tsv_flag; + + /* the descriptor is busy due to own by the DMA */ + if ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if (NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if (((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if ((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if (size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for (offset = 0; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); + } + } else { + return ERROR; + } + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if (NULL != timestamp) { + /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and + write to the RDES6 and RDES7 */ + do { + rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); + timeout++; + } while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if (ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_RDES0_TSV flag */ + dma_current_rxdesc->status &= ~ENET_RDES0_TSV; + /* get the timestamp value of the received frame */ + timestamp[0] = dma_current_rxdesc->timestamp_low; + timestamp[1] = dma_current_rxdesc->timestamp_high; + } + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* Clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0; + } + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0; + uint32_t dma_tbu_flag, dma_tu_flag; + uint32_t tdes0_ttmss_flag; + uint32_t timeout = 0; + + /* the descriptor is busy due to own by the DMA */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if (length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if (NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for (offset = 0; offset < length; offset++) { + (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* Clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if (NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while ((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if (ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->timestamp_low; + timestamp[1] = dma_current_txdesc->timestamp_high; + } + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* chained mode */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + + return SUCCESS; +} + +#else + +/*! + \brief configure descriptor to work in normal mode + \param[in] none + \param[out] none + \retval none +*/ +void enet_desc_select_normal_mode(void) +{ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DFM; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select chain mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive chained mode and set buffer1 size */ + desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for (num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* if is not the last descriptor */ + if (num < (count - 1U)) { + /* configure the next descriptor address */ + desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + only one parameter can be selected which is shown as below + \arg ENET_DMA_TX: DMA Tx descriptors + \arg ENET_DMA_RX: DMA Rx descriptors + \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table + \param[out] none + \retval none +*/ +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +{ + uint32_t num = 0U, count = 0U, maxsize = 0U; + uint32_t desc_status = 0U, desc_bufsize = 0U; + enet_descriptors_struct *desc, *desc_tab; + uint8_t *buf; + + /* configure descriptor skip length */ + ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; + ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); + + /* if want to initialize DMA Tx descriptors */ + if (ENET_DMA_TX == direction) { + /* save a copy of the DMA Tx descriptors */ + desc_tab = txdesc_tab; + buf = &tx_buff[0][0]; + count = ENET_TXBUF_NUM; + maxsize = ENET_TXBUF_SIZE; + + /* select ring mode, and enable transmit timestamp function */ + desc_status = ENET_TDES0_TTSEN; + + /* configure DMA Tx descriptor table address register */ + ENET_DMA_TDTADDR = (uint32_t)desc_tab; + dma_current_txdesc = desc_tab; + dma_current_ptp_txdesc = desc_ptptab; + } else { + /* if want to initialize DMA Rx descriptors */ + /* save a copy of the DMA Rx descriptors */ + desc_tab = rxdesc_tab; + buf = &rx_buff[0][0]; + count = ENET_RXBUF_NUM; + maxsize = ENET_RXBUF_SIZE; + + /* enable receiving */ + desc_status = ENET_RDES0_DAV; + /* select receive ring mode and set buffer1 size */ + desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; + + /* configure DMA Rx descriptor table address register */ + ENET_DMA_RDTADDR = (uint32_t)desc_tab; + dma_current_rxdesc = desc_tab; + dma_current_ptp_rxdesc = desc_ptptab; + } + + /* configure each descriptor */ + for (num = 0U; num < count; num++) { + /* get the pointer to the next descriptor of the descriptor table */ + desc = desc_tab + num; + + /* configure descriptors */ + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + + /* when it is the last descriptor */ + if (num == (count - 1U)) { + if (ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ + desc->status |= ENET_TDES0_TERM; + } else { + /* configure receive end of ring mode */ + desc->control_buffer_size |= ENET_RDES1_RERM; + } + } + /* set desc_ptptab equal to desc_tab */ + (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; + (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; + } + /* when it is the last ptp descriptor, preserve the first descriptor + address of desc_ptptab in ptp descriptor status */ + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; +} + +/*! + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \param[in] bufsize: the size of buffer which is the parameter in function + \param[out] timestamp: pointer to the table which stores the timestamp high and low + \param[out] buffer: pointer to the application buffer + note -- if the input is NULL, user should copy data in application by himself + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +{ + uint32_t offset = 0U, size = 0U; + + /* the descriptor is busy due to own by the DMA */ + if ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has copied data in application */ + if (NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if (((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + /* if is a type frame, and CRC is not included in forwarding frame */ + if ((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if (size > bufsize) { + return ERROR; + } + + /* copy data from Rx buffer to application buffer */ + for (offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); + } + + } else { + return ERROR; + } + } + /* copy timestamp value from Rx descriptor to application array */ + timestamp[0] = dma_current_rxdesc->buffer1_addr; + timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; + + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + /* chained mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if (0U != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + } else { + /* ring mode */ + if ((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with RxDMA descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_rxdesc ++; + } + } + + return SUCCESS; +} + +/*! + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \param[in] buffer: pointer on the application buffer + note -- if the input is NULL, user should copy data in application by himself + \param[in] length: the length of frame data to be transmitted + \param[out] timestamp: pointer to the table which stores the timestamp high and low + note -- if the input is NULL, timestamp is ignored + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +{ + uint32_t offset = 0U, timeout = 0U; + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + + /* the descriptor is busy due to own by the DMA */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + return ERROR; + } + + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + if (length > ENET_MAX_FRAME_SIZE) { + return ERROR; + } + + /* if buffer pointer is null, indicates that users has handled data in application */ + if (NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for (offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } + } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if (NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while ((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if (ENET_DELAY_TO == timeout) { + return ERROR; + } + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->buffer1_addr; + timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* chained mode */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if (0U != dma_current_ptp_txdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } + } else { + /* ring mode */ + if ((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with TxDMA descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; + } + } + return SUCCESS; +} + +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + +/*! + \brief wakeup frame filter register pointer reset + \param[in] none + \param[out] none + \retval none +*/ +void enet_wum_filter_register_pointer_reset(void) +{ + ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; +} + +/*! + \brief set the remote wakeup frame registers + \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) + \param[out] none + \retval none +*/ +void enet_wum_filter_config(uint32_t pdata[]) +{ + uint32_t num = 0U; + + /* configure ENET_MAC_RWFF register */ + for (num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { + ENET_MAC_RWFF = pdata[num]; + } +} + +/*! + \brief enable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_POWER_DOWN: power down mode + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_enable(uint32_t feature) +{ + ENET_MAC_WUM |= feature; +} + +/*! + \brief disable wakeup management features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception + \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception + \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame + \param[out] none + \retval none +*/ +void enet_wum_feature_disable(uint32_t feature) +{ + ENET_MAC_WUM &= (~feature); +} + +/*! + \brief reset the MAC statistics counters + \param[in] none + \param[out] none + \retval none +*/ +void enet_msc_counters_reset(void) +{ + /* reset all counters */ + ENET_MSC_CTL |= ENET_MSC_CTL_CTR; +} + +/*! + \brief enable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_enable(uint32_t feature) +{ + ENET_MSC_CTL |= feature; +} + +/*! + \brief disable the MAC statistics counter features + \param[in] feature: one or more parameters can be selected which are shown as below + \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover + \arg ENET_MSC_RESET_ON_READ: reset on read + \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze + \param[out] none + \retval none +*/ +void enet_msc_feature_disable(uint32_t feature) +{ + ENET_MSC_CTL &= (~feature); +} + +/*! + \brief configure MAC statistics counters preset mode + \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum, + only one parameter can be selected which is shown as below + \arg ENET_MSC_PRESET_NONE: do not preset MSC counter + \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value + \arg ENET_MSC_PRESET_FULL: preset all MSC counters to almost-full(0xFFFF FFF0) value + \param[out] none + \retval none +*/ +void enet_msc_counters_preset_config(enet_msc_preset_enum mode) +{ + ENET_MSC_CTL &= ENET_MSC_PRESET_MASK; + ENET_MSC_CTL |= (uint32_t)mode; +} + +/*! + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, + only one parameter can be selected which is shown as below + \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter + \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter + \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter + \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter + \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter + \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter + \param[out] none + \retval the MSC counter value +*/ +uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) +{ + uint32_t reval; + + reval = REG32((ENET + (uint32_t)counter)); + + return reval; +} + +/*! + \brief change subsecond to nanosecond + \param[in] subsecond: subsecond value + \param[out] none + \retval the nanosecond value +*/ +uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) +{ + uint64_t val = subsecond * 1000000000Ull; + val >>= 31; + return (uint32_t)val; +} + +/*! + \brief change nanosecond to subsecond + \param[in] nanosecond: nanosecond value + \param[out] none + \retval the subsecond value +*/ +uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond) +{ + uint64_t val = nanosecond * 0x80000000Ull; + val /= 1000000000U; + return (uint32_t)val; +} + +/*! + \brief enable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_enable(uint32_t feature) +{ + ENET_PTP_TSCTL |= feature; +} + +/*! + \brief disable the PTP features + \param[in] feature: the feature of ENET PTP mode + one or more parameters can be selected which are shown as below + \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames + \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger + \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot + \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame + \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame + \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame + \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame + \param[out] none + \retval none +*/ +void enet_ptp_feature_disable(uint32_t feature) +{ + ENET_PTP_TSCTL &= ~feature; +} + +/*! + \brief configure the PTP timestamp function + \param[in] func: only one parameter can be selected which is shown as below + \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp + \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp + \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp + \arg ENET_CKNT_PEER_TO_PEER: type of peer-to-peer transparent clock node type for timestamp + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating + \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating + \arg ENET_SUBSECOND_DIGITAL_ROLLOVER: digital rollover mode + \arg ENET_SUBSECOND_BINARY_ROLLOVER: binary rollover mode + \arg ENET_SNOOPING_PTP_VERSION_2: version 2 + \arg ENET_SNOOPING_PTP_VERSION_1: version 1 + \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot + \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, + management and signaling message + \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message + \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) +{ + uint32_t temp_config = 0U, temp_state = 0U; + uint32_t timeout = 0U; + ErrStatus enet_state = SUCCESS; + + switch (func) { + case ENET_CKNT_ORDINARY: + case ENET_CKNT_BOUNDARY: + case ENET_CKNT_END_TO_END: + case ENET_CKNT_PEER_TO_PEER: + ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; + ENET_PTP_TSCTL |= (uint32_t)func; + break; + case ENET_PTP_ADDEND_UPDATE: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + timeout++; + } while ((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if (ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; + } + break; + case ENET_PTP_SYSTIME_UPDATE: + /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ + do { + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + timeout++; + } while ((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if (ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; + } + break; + case ENET_PTP_SYSTIME_INIT: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + timeout++; + } while ((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if (ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; + } + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if (RESET != ((uint32_t)func & BIT(31))) { + ENET_PTP_TSCTL |= temp_config; + } else { + ENET_PTP_TSCTL &= ~temp_config; + } + break; + } + + return enet_state; +} + +/*! + \brief configure system time subsecond increment value + \param[in] subsecond: the value will be added to the subsecond value of system time, + this value must be between 0 and 0xFF + \param[out] none + \retval none +*/ +void enet_ptp_subsecond_increment_config(uint32_t subsecond) +{ + ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); +} + +/*! + \brief adjusting the clock frequency only in fine update mode + \param[in] add: the value will be added to the accumulator register to achieve time synchronization + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_addend_config(uint32_t add) +{ + ENET_PTP_TSADDEND = add; +} + +/*! + \brief initialize or add/subtract to second of the system time + \param[in] sign: timestamp update positive or negative sign, + only one parameter can be selected which is shown as below + \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time + \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time + \param[in] second: initializing or adding/subtracting to second of the system time + \param[in] subsecond: the current subsecond of the system time + with 0.46 ns accuracy if required accuracy is 20 ns + \param[out] none + \retval none +*/ +void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) +{ + ENET_PTP_TSUH = second; + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); +} + +/*! + \brief configure the expected target time + \param[in] second: the expected target second time + \param[in] nanosecond: the expected target nanosecond time (signed) + \param[out] none + \retval none +*/ +void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) +{ + ENET_PTP_ETH = second; + ENET_PTP_ETL = nanosecond; +} + +/*! + \brief get the current system time + \param[in] none + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \retval none +*/ +void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) +{ + uint32_t temp_sec = 0U, temp_subs = 0U; + + /* get the value of sysytem time registers */ + temp_sec = (uint32_t)ENET_PTP_TSH; + temp_subs = (uint32_t)ENET_PTP_TSL; + + /* get sysytem time and construct the enet_ptp_systime_struct structure */ + systime_struct->second = temp_sec; + systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); + systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); + systime_struct->sign = GET_PTP_TSL_STS(temp_subs); +} + +/*! + \brief configure the PPS output frequency + \param[in] freq: PPS output frequency, + only one parameter can be selected which is shown as below + \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency + \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency + \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency + \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency + \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency + \arg ENET_PPSOFC_8192HZ: PPS output 8192Hz frequency + \arg ENET_PPSOFC_16384HZ: PPS output 16384Hz frequency + \arg ENET_PPSOFC_32768HZ: PPS output 32768Hz frequency + \param[out] none + \retval none +*/ +void enet_ptp_pps_output_frequency_config(uint32_t freq) +{ + ENET_PTP_PPSCTL = freq; +} + +/*! + \brief configure and start PTP timestamp counter + \param[in] updatemethod: method for updating + \arg ENET_PTP_FINEMODE: fine correction method + \arg ENET_PTP_COARSEMODE: coarse correction method + \param[in] init_sec: second value for initializing system time + \param[in] init_subsec: subsecond value for initializing system time + \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used) + \param[in] accuracy_cfg: the value to be added to the subsecond value of system time + \param[out] none + \retval none +*/ +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) +{ + /* mask the timestamp trigger interrupt */ + enet_interrupt_disable(ENET_MAC_INT_TMSTIM); + + /* enable timestamp */ + enet_ptp_feature_enable(ENET_ALL_RX_TIMESTAMP | ENET_RXTX_TIMESTAMP); + + /* configure system time subsecond increment based on the PTP clock frequency */ + enet_ptp_subsecond_increment_config(accuracy_cfg); + + if (ENET_PTP_FINEMODE == updatemethod) { + /* fine correction method: configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); + /* wait until update is completed */ + while (SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)) { + } + } + + /* choose the fine correction method */ + enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + +#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE + enet_desc_select_enhanced_mode(); +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ +} + +/*! + \brief adjust frequency in fine method by configure addend register + \param[in] carry_cfg: the value to be added to the accumulator register + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) +{ + /* re-configure the timestamp addend, then update */ + enet_ptp_timestamp_addend_config((uint32_t)carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief update system time in coarse method + \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct) +{ + uint32_t subsecond_val; + uint32_t carry_cfg; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* save the carry_cfg value */ + carry_cfg = ENET_PTP_TSADDEND_TMSA; + + /* update the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); + + /* wait until the update is completed */ + while (SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)) { + } + + /* write back the carry_cfg value, then update */ + enet_ptp_timestamp_addend_config(carry_cfg); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +/*! + \brief set system time in fine method + \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains + parameters of PTP system time + members of the structure and the member values are shown as below: + second: 0x0 - 0xFFFF FFFF + nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 + sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE + \param[out] none + \retval none +*/ +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct) +{ + uint32_t subsecond_val; + + subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); + + /* initialize the system time */ + enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + + /* wait until the system time initialzation finished */ + while (SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)) { + } +} + +/*! + \brief get the ptp flag status + \param[in] flag: ptp flag status to be checked + \arg ENET_PTP_ADDEND_UPDATE: addend register update + \arg ENET_PTP_SYSTIME_UPDATE: timestamp update + \arg ENET_PTP_SYSTIME_INIT: timestamp initialize + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_ptp_flag_get(uint32_t flag) +{ + FlagStatus bitstatus = RESET; + + if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)) { + bitstatus = SET; + } + + return bitstatus; +} + +/*! + \brief reset the ENET initpara struct, call it before using enet_initpara_config() + \param[in] none + \param[out] none + \retval none +*/ +void enet_initpara_reset(void) +{ + enet_initpara.option_enable = 0U; + enet_initpara.forward_frame = 0U; + enet_initpara.dmabus_mode = 0U; + enet_initpara.dma_maxburst = 0U; + enet_initpara.dma_arbitration = 0U; + enet_initpara.store_forward_mode = 0U; + enet_initpara.dma_function = 0U; + enet_initpara.vlan_config = 0U; + enet_initpara.flow_control = 0U; + enet_initpara.hashtable_high = 0U; + enet_initpara.hashtable_low = 0U; + enet_initpara.framesfilter_mode = 0U; + enet_initpara.halfduplex_param = 0U; + enet_initpara.timer_config = 0U; + enet_initpara.interframegap = 0U; +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \param[in] none + \param[out] none + \retval none +*/ +static void enet_default_init(void) +{ + uint32_t reg_value = 0U; + + /* MAC */ + /* configure ENET_MAC_CFG register */ + reg_value = ENET_MAC_CFG; + reg_value &= MAC_CFG_MASK; + reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ + | ENET_SPEEDMODE_10M | ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_TYPEFRAME_CRC_DROP_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; + ENET_MAC_CFG = reg_value; + + /* configure ENET_MAC_FRMF register */ + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE | ENET_DEST_FILTER_INVERSE_DISABLE \ + | ENET_MULTICAST_FILTER_PERFECT | ENET_UNICAST_FILTER_PERFECT \ + | ENET_PCFRM_PREVENT_ALL | ENET_BROADCASTFRAMES_ENABLE \ + | ENET_PROMISCUOUS_DISABLE | ENET_RX_FILTER_ENABLE; + + /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ + ENET_MAC_HLH = 0x0U; + + ENET_MAC_HLL = 0x0U; + + /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ + reg_value = ENET_MAC_FCTL; + reg_value &= MAC_FCTL_MASK; + reg_value |= MAC_FCTL_PTM(0) | ENET_ZERO_QUANTA_PAUSE_DISABLE \ + | ENET_PAUSETIME_MINUS4 | ENET_UNIQUE_PAUSEDETECT \ + | ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE; + ENET_MAC_FCTL = reg_value; + + ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES | ENET_ACTIVE_THRESHOLD_1536BYTES; + + /* configure ENET_MAC_VLT register */ + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0); + + /* DMA */ + /* configure ENET_DMA_CTL register */ + reg_value = ENET_DMA_CTL; + reg_value &= DMA_CTL_MASK; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \ + | ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \ + | ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \ + | ENET_FORWARD_ERRFRAMES_DISABLE | ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ + | ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; + + /* configure ENET_DMA_BCTL register */ + reg_value = ENET_DMA_BCTL; + reg_value &= DMA_BCTL_MASK; + reg_value = ENET_ADDRESS_ALIGN_ENABLE | ENET_ARBITRATION_RXTX_2_1 \ + | ENET_RXDP_32BEAT | ENET_PGBL_32BEAT | ENET_RXTX_DIFFERENT_PGBL \ + | ENET_FIXED_BURST_ENABLE | ENET_MIXED_BURST_DISABLE \ + | ENET_NORMAL_DESCRIPTOR; + ENET_DMA_BCTL = reg_value; +} + +#ifndef USE_DELAY +/*! + \brief insert a delay time + \param[in] ncount: specifies the delay time length + \param[out] none + \param[out] none +*/ +static void enet_delay(uint32_t ncount) +{ + __IO uint32_t delay_time = 0U; + + for (delay_time = ncount; delay_time != 0U; delay_time--) { + } +} +#endif /* USE_DELAY */ + +#endif /* GD32F30X_CL */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c new file mode 100644 index 0000000000..abe212cbf2 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c @@ -0,0 +1,654 @@ +/*! + \file gd32f30x_exmc.c + \brief EXMC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_exmc.h" + +/* EXMC bank0 register reset value */ +#define BANK0_SNCTL_REGION0_RESET ((uint32_t)0x000030DBU) +#define BANK0_SNCTL_REGION1_2_3_RESET ((uint32_t)0x000030D2U) +#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) +#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) + +/* EXMC bank1/2 register reset mask*/ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC bank3 register reset mask*/ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) + +/* EXMC register bit offset */ +#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) +#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) +#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) +#define SNCTL_WREN_OFFSET ((uint32_t)12U) +#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) +#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) +#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) + +#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) +#define SNTCFG_DSET_OFFSET ((uint32_t)8U) +#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) + +#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) +#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) +#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) + +#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) +#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) + +#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) +#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) +#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) + +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) + +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) + +#define INTEN_INTS_OFFSET ((uint32_t)3U) + +/*! + \brief deinitialize EXMC NOR/SRAM region + \param[in] exmc_norsram_region: select the region of bank0 + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_deinit(uint32_t exmc_norsram_region) +{ + /* reset the registers */ + if (EXMC_BANK0_NORSRAM_REGION0 == exmc_norsram_region) { + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET; + } else { + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET; + } + EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; + EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; +} + +/*! + \brief initialize EXMC NOR/SRAM region + \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter + norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 + write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE + asyn_wait: ENABLE or DISABLE + nwait_signal: ENABLE or DISABLE + memory_write: ENABLE or DISABLE + nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING + wrap_burst_mode: ENABLE or DISABLE + nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH + burst_mode: ENABLE or DISABLE + databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR + address_data_mux: ENABLE or DISABLE + read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + write_timing: struct exmc_norsram_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) +{ + uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; + + /* get the register value */ + snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); + + /* clear relative bits */ + snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | + EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | + EXMC_SNCTL_SYNCWR)); + + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET) | + (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD) | + (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET) | + (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT) | + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* nor flash access enable */ + if (EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { + snctl |= (uint32_t)EXMC_SNCTL_NREN; + } + + /* extended mode configure */ + if (ENABLE == exmc_norsram_init_struct->extended_mode) { + snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) | + (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNWTCFG_WAHLD_OFFSET) & EXMC_SNWTCFG_WAHLD) | + (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNWTCFG_WDSET_OFFSET) & EXMC_SNWTCFG_WDSET) | + (((exmc_norsram_init_struct->write_timing->bus_latency - 1U) << SNWTCFG_WBUSLAT_OFFSET) & EXMC_SNWTCFG_WBUSLAT) | + exmc_norsram_init_struct->write_timing->asyn_access_mode; + } else { + snwtcfg = BANK0_SNWTCFG_RESET; + } + + /* configure the registers */ + EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; + EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; + EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; +} + +/*! + \brief initialize the struct exmc_norsram_parameter_struct + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_parameter_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) +{ + /* configure the structure with default value */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; + exmc_norsram_init_struct->burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->wrap_burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->extended_mode = DISABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; + + /* read/write timing configure */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; + exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; + exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; + + /* write timing configure, when extended mode is used */ + exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; +} + +/*! + \brief CRAM page size configure + \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[in] page_size: CRAM page size + \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access + \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes + \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes + \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes + \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes + \param[out] none + \retval none +*/ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) +{ + /* reset the bits */ + EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; + + /* set the CPS bits */ + EXMC_SNCTL(exmc_norsram_region) |= page_size; +} + +/*! + \brief enable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_enable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief disable EXMC NOR/PSRAM bank region + \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[out] none + \retval none +*/ +void exmc_norsram_disable(uint32_t exmc_norsram_region) +{ + EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; +} + +/*! + \brief deinitialize EXMC NAND bank + \param[in] exmc_nand_bank: select the bank of NAND + \arg EXMC_BANKx_NAND(x=1..2) + \param[out] none + \retval none +*/ +void exmc_nand_deinit(uint32_t exmc_nand_bank) +{ + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + EXMC_NPCTL(exmc_nand_bank) = BANK1_2_NPCTL_RESET; + EXMC_NPINTEN(exmc_nand_bank) = BANK1_2_NPINTEN_RESET; + EXMC_NPCTCFG(exmc_nand_bank) = BANK1_2_NPCTCFG_RESET; + EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET; +} + +/*! + \brief initialize EXMC NAND bank + \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter + nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND + ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + ecc_logic: ENABLE or DISABLE + databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct) +{ + uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET) | + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; + EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; + EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; +} + +/*! + \brief initialize the struct exmc_norsram_parameter_struct + \param[in] none + \param[out] the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_nand_parameter_init(exmc_nand_parameter_struct *exmc_nand_init_struct) +{ + /* configure the structure with default value */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xfcU; + exmc_nand_init_struct->common_space_timing->waittime = 0xfcU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xfcU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xfcU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xfcU; +} + +/*! + \brief enable NAND bank + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_enable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable NAND bank + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval none +*/ +void exmc_nand_disable(uint32_t exmc_nand_bank) +{ + EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_NDBKEN); +} + +/*! + \brief enable or disable the EXMC NAND ECC function + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) +{ + if (ENABLE == newvalue) { + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; + } else { + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_ECCEN); + } +} + +/*! + \brief get the EXMC ECC value + \param[in] exmc_nand_bank: specifie the NAND bank + \arg EXMC_BANKx_NAND(x=1,2) + \param[out] none + \retval the error correction code(ECC) value +*/ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) +{ + return (EXMC_NECC(exmc_nand_bank)); +} + +/*! + \brief deinitialize EXMC PC card bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_deinit(void) +{ + /* EXMC_BANK3_PCCARD */ + EXMC_NPCTL3 = BANK3_NPCTL_RESET; + EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; + EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; + EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; + EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; +} + +/*! + \brief initialize EXMC PC card bank + \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter + atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 + ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 + wait_feature: ENABLE or DISABLE + common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + \param[out] none + \retval none +*/ +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) +{ + /* configure the EXMC bank3 PC card control register */ + EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + + /* configure the EXMC bank3 PC card common space timing configuration register */ + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + /* configure the EXMC bank3 PC card attribute space timing configuration register */ + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* configure the EXMC bank3 PC card io space timing configuration register */ + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ); +} + +/*! + \brief initialize the struct exmc_pccard_parameter_struct + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_parameter_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) +{ + /* configure the structure with default value */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + +/*! + \brief enable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_enable(void) +{ + EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; +} + +/*! + \brief disable PC Card Bank + \param[in] none + \param[out] none + \retval none +*/ +void exmc_pccard_disable(void) +{ + EXMC_NPCTL3 &= (~EXMC_NPCTL_NDBKEN); +} + +/*! + \brief check EXMC flag is set or not + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC Card bank + \param[in] flag: specify get which flag + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag) +{ + uint32_t status = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + + if ((status & flag) != (uint32_t)flag) { + /* flag is reset */ + return RESET; + } else { + /* flag is set */ + return SET; + } +} + +/*! + \brief clear EXMC flag + \param[in] exmc_bank: specifie the NAND bank , PCCARD bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] flag: specify get which flag + \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status + \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status + \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status + \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag + \param[out] none + \retval none +*/ +void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= (~flag); +} + +/*! + \brief check EXMC interrupt flag is set or not + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt_source) +{ + uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U; + + /* NAND bank1,bank2 or PC card bank3 */ + status = EXMC_NPINTEN(exmc_bank); + interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); + + interrupt_enable = (status & interrupt_source); + + if ((interrupt_enable) && (interrupt_state)) { + /* interrupt flag is set */ + return SET; + } else { + /* interrupt flag is reset */ + return RESET; + } +} + +/*! + \brief clear EXMC interrupt flag + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); +} + +/*! + \brief enable EXMC interrupt + \param[in] exmc_bank: specifies the NAND bank,PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) |= interrupt_source; +} + +/*! + \brief disable EXMC interrupt + \param[in] exmc_bank: specifies the NAND bank , PC card bank + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \param[in] interrupt_source: specify get which interrupt flag + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt_source) +{ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= (~interrupt_source); +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c new file mode 100644 index 0000000000..718cb111de --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c @@ -0,0 +1,252 @@ +/*! + \file gd32f30x_exti.c + \brief EXTI driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_exti.h" + +/*! + \brief deinitialize the EXTI + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = (uint32_t)0x00000000U; + EXTI_EVEN = (uint32_t)0x00000000U; + EXTI_RTEN = (uint32_t)0x00000000U; + EXTI_FTEN = (uint32_t)0x00000000U; + EXTI_SWIEV = (uint32_t)0x00000000U; +} + +/*! + \brief initialize the EXTI + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch (mode) { + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch (trig_type) { + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI lines flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if (RESET != (EXTI_PD & (uint32_t)linex)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI lines flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if ((RESET != flag_left) && (RESET != flag_right)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI lines pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c new file mode 100644 index 0000000000..7f07e67a4f --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c @@ -0,0 +1,952 @@ +/*! + \file gd32f30x_fmc.c + \brief FMC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_fmc.h" + +/*! + \brief set the wait state counter value + \param[in] wscnt:wait state counter value + \arg WS_WSCNT_0: FMC 0 wait + \arg WS_WSCNT_1: FMC 1 wait + \arg WS_WSCNT_2: FMC 2 wait + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint32_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief unlock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if ((RESET != (FMC_CTL0 & FMC_CTL0_LK))) { + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } + if (FMC_BANK0_SIZE < FMC_SIZE) { + /* write the FMC unlock key */ + if (RESET != (FMC_CTL1 & FMC_CTL1_LK)) { + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } + } +} + +/*! + \brief unlock the FMC bank0 operation + this function can be used for all GD32F30x devices. + for GD32F30x with flash more than 512KB, this function unlocks bank0. + for GD32F30x with flash no more than 512KB and it is equivalent to fmc_unlock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_unlock(void) +{ + if ((RESET != (FMC_CTL0 & FMC_CTL0_LK))) { + /* write the FMC unlock key */ + FMC_KEY0 = UNLOCK_KEY0; + FMC_KEY0 = UNLOCK_KEY1; + } +} + +/*! + \brief unlock the FMC bank1 operation + this function can be used for GD32F30x with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_unlock(void) +{ + if ((RESET != (FMC_CTL1 & FMC_CTL1_LK))) { + /* write the FMC unlock key */ + FMC_KEY1 = UNLOCK_KEY0; + FMC_KEY1 = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit */ + FMC_CTL0 |= FMC_CTL0_LK; + + if (FMC_BANK0_SIZE < FMC_SIZE) { + /* set the LK bit */ + FMC_CTL1 |= FMC_CTL1_LK; + } +} + +/*! + \brief lock the FMC bank0 operation + this function can be used for all GD32F30X devices. + for GD32F30x with flash more than 512KB, this function locks bank0. + for GD32F30x with flash no more than 512KB and it is equivalent to fmc_lock function. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank0_lock(void) +{ + /* set the LK bit*/ + FMC_CTL0 |= FMC_CTL0_LK; +} + +/*! + \brief lock the FMC bank1 operation + this function can be used for GD32F30x with flash more than 512KB. + \param[in] none + \param[out] none + \retval none +*/ +void fmc_bank1_lock(void) +{ + /* set the LK bit*/ + FMC_CTL1 |= FMC_CTL1_LK; +} + +/*! + \brief erase page + \param[in] page_address: the page address to be erased. + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state; + + if (FMC_BANK0_SIZE < FMC_SIZE) { + if (FMC_BANK0_END_ADDRESS > page_address) { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if (FMC_READY == fmc_state) { + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + } else { + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if (FMC_READY == fmc_state) { + FMC_CTL1 |= FMC_CTL1_PER; + FMC_ADDR1 = page_address; + if (FMC_OBSTAT & FMC_OBSTAT_SPC) { + FMC_ADDR0 = page_address; + } + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL1 &= ~FMC_CTL1_PER; + } + } + } else { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* if the last operation is completed, start page erase */ + if (FMC_READY == fmc_state) { + FMC_CTL0 |= FMC_CTL0_PER; + FMC_ADDR0 = page_address; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PER bit */ + FMC_CTL0 &= ~FMC_CTL0_PER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state; + if (FMC_BANK0_SIZE < FMC_SIZE) { + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if (FMC_READY == fmc_state) { + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if (FMC_READY == fmc_state) { + /* start whole chip erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + } else { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* start whole chip erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase bank0 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* start FMC bank0 erase */ + FMC_CTL0 |= FMC_CTL0_MER; + FMC_CTL0 |= FMC_CTL0_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL0 &= ~FMC_CTL0_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief erase bank1 + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_erase(void) +{ + fmc_state_enum fmc_state = FMC_READY; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* start FMC bank1 erase */ + FMC_CTL1 |= FMC_CTL1_MER; + FMC_CTL1 |= FMC_CTL1_START; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the MER bit */ + FMC_CTL1 &= ~FMC_CTL1_MER; + } + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if (FMC_BANK0_SIZE < FMC_SIZE) { + if (FMC_BANK0_END_ADDRESS > address) { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } else { + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + } else { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: halfword to program + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = FMC_READY; + if (FMC_BANK0_SIZE < FMC_SIZE) { + if (FMC_BANK0_END_ADDRESS > address) { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } else { + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL1 |= FMC_CTL1_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL1 &= ~FMC_CTL1_PG; + } + } + } else { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL0 |= FMC_CTL0_PG; + REG16(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the PG bit */ + FMC_CTL0 &= ~FMC_CTL0_PG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) { + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the option byte operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWEN bit */ + FMC_CTL0 &= ~FMC_CTL0_OBWEN; +} + +/*! + \brief erase the FMC option byte + unlock the FMC_CTL0 and option byte before calling this function + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_erase(void) +{ + uint16_t temp_spc = FMC_NSPC; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + /* check the option byte security protection value */ + if (RESET != ob_spc_get()) { + temp_spc = FMC_USPC; + } + + if (FMC_READY == fmc_state) { + + /* start erase the option byte */ + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + /* no security protection */ + OB_SPC = (uint16_t)temp_spc; + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } else { + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable write protection + \param[in] ob_wp: specify sector to be write protected + \arg OB_WPx(x=0..31): write protect specify sector + \arg OB_WP_ALL: write protect all sector + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) +{ + uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; + + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + ob_wp = (uint32_t)(~ob_wp); + temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); + temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); + temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); + temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); + + if (FMC_READY == fmc_state) { + + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + if (0xFFU != temp_wp0) { + OB_WP0 = temp_wp0; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if ((FMC_READY == fmc_state) && (0xFFU != temp_wp1)) { + OB_WP1 = temp_wp1; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if ((FMC_READY == fmc_state) && (0xFFU != temp_wp2)) { + OB_WP2 = temp_wp2; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if ((FMC_READY == fmc_state) && (0xFFU != temp_wp3)) { + OB_WP3 = temp_wp3; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + } + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection + \arg FMC_NSPC: no security protection + \arg FMC_USPC: under security protection + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + FMC_CTL0 |= FMC_CTL0_OBER; + FMC_CTL0 |= FMC_CTL0_START; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + + /* start the option byte program */ + FMC_CTL0 |= FMC_CTL0_OBPG; + + OB_SPC = (uint16_t)ob_spc; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } else { + if (FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL0 &= ~FMC_CTL0_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte + \param[in] ob_fwdgt: option byte watchdog value + \arg OB_FWDGT_SW: software free watchdog + \arg OB_FWDGT_HW: hardware free watchdog + \param[in] ob_deepsleep: option byte deepsleep reset value + \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \param[in] ob_stdby:option byte standby reset value + \arg OB_STDBY_NRST: no reset when entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \param[in] ob_boot: specifies the option byte boot bank value + \arg OB_BOOT_B0: boot from bank0 + \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) +{ + fmc_state_enum fmc_state = FMC_READY; + uint8_t temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the OBPG bit*/ + FMC_CTL0 |= FMC_CTL0_OBPG; + + temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); + OB_USER = (uint16_t)temp; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program option bytes data + \param[in] address: the option bytes address to be programmed + \param[in] data: the byte to be programmed + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_READY == fmc_state) { + /* set the OBPG bit */ + FMC_CTL0 |= FMC_CTL0_OBPG; + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if (FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL0 &= ~FMC_CTL0_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC user option byte + \param[in] none + \param[out] none + \retval the FMC user option byte values +*/ +uint8_t ob_user_get(void) +{ + /* return the FMC user option byte value */ + return (uint8_t)(FMC_OBSTAT >> 2U); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)(FMC_OBSTAT >> 10U); +} + +/*! + \brief get the FMC option byte write protection + \param[in] none + \param[out] none + \retval the FMC write protection option byte value +*/ +uint32_t ob_write_protection_get(void) +{ + /* return the FMC write protection option byte value */ + return FMC_WP; +} + +/*! + \brief get the FMC option byte security protection + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ob_spc_get(void) +{ + FlagStatus spc_state = RESET; + + if (RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)) { + spc_state = SET; + } else { + spc_state = RESET; + } + return spc_state; +} + +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + \arg FMC_INT_BANK0_END: enable FMC end of program interrupt + \arg FMC_INT_BANK0_ERR: enable FMC error interrupt + \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief check flag is set or not + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit + \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t flag) +{ + if (RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the FMC flag + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit + \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit + \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit + \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit + \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit + \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t flag) +{ + FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); +} + +/*! + \brief get FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) +{ + FlagStatus ret1 = RESET; + FlagStatus ret2 = RESET; + + if (FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)) { + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); + } else { + /* get the staus of interrupt flag */ + ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); + /* get the staus of interrupt enale bit */ + ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); + } + + if (ret1 && ret2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear FMC interrupt flag state + \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit + \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit + \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) +{ + FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); +} + +/*! + \brief get the FMC bank0 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if ((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)) { + fmc_state = FMC_BUSY; + } else { + if ((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)) { + fmc_state = FMC_WPERR; + } else { + if ((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))) { + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get the FMC bank1 state + \param[in] none + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if ((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)) { + fmc_state = FMC_BUSY; + } else { + if ((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)) { + fmc_state = FMC_WPERR; + } else { + if ((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)) { + fmc_state = FMC_PGERR; + } + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank0 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_bank0_state_get(); + timeout--; + } while ((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if (FMC_BUSY == fmc_state) { + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC bank1 is ready or not + \param[in] timeout: count of loop + \param[out] none + \retval state of FMC, refer to fmc_state_enum +*/ +fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_bank1_state_get(); + timeout--; + } while ((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if (FMC_BUSY == fmc_state) { + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c new file mode 100644 index 0000000000..b14bc532ab --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c @@ -0,0 +1,145 @@ +/*! + \file gd32f30x_fwdgt.c + \brief FWDGT driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_fwdgt.h" + +/* write value to FWDGT_CTL_CMD bit field */ +#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/*! + \brief disable write access to FWDGT_PSC and FWDGT_RLD + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status) { + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status) { + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if (FWDGT_STAT & flag) { + return SET; + } + + return RESET; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c new file mode 100644 index 0000000000..9ded643ebf --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c @@ -0,0 +1,564 @@ +/*! + \file gd32f30x_gpio.c + \brief GPIO driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_gpio.h" + +#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ +#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ +#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ +#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ +#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ +#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ +#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch (gpio_periph) { + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOE: + /* reset GPIOE */ + rcu_periph_reset_enable(RCU_GPIOERST); + rcu_periph_reset_disable(RCU_GPIOERST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + case GPIOG: + /* reset GPIOG */ + rcu_periph_reset_enable(RCU_GPIOGRST); + rcu_periph_reset_disable(RCU_GPIOGRST); + break; + default: + break; + } +} + +/*! + \brief reset alternate function I/O(AFIO) + \param[in] none + \param[out] none + \retval none +*/ +void gpio_afio_deinit(void) +{ + rcu_periph_reset_enable(RCU_AFRST); + rcu_periph_reset_disable(RCU_AFRST); +} + +/*! + \brief GPIO parameter initialization + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] mode: gpio pin mode + \arg GPIO_MODE_AIN: analog input mode + \arg GPIO_MODE_IN_FLOATING: floating input mode + \arg GPIO_MODE_IPD: pull-down input mode + \arg GPIO_MODE_IPU: pull-up input mode + \arg GPIO_MODE_OUT_OD: GPIO output with open-drain + \arg GPIO_MODE_OUT_PP: GPIO output with push-pull + \arg GPIO_MODE_AF_OD: AFIO output with open-drain + \arg GPIO_MODE_AF_PP: AFIO output with push-pull + \param[in] speed: gpio output max speed value + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_MAX: output max speed more than 50MHz + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +#ifdef GD_MBED_USED +/* GPIO parameter initialization */ +void gpio_para_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) +#else +void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) +#endif +{ + uint16_t i; + uint32_t temp_mode = 0U; + uint32_t reg = 0U; + + /* GPIO mode configuration */ + temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); + + /* GPIO speed configuration */ + if (((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))) { + /* output mode max speed */ + if (GPIO_OSPEED_MAX == (uint32_t)speed) { + temp_mode |= (uint32_t)0x03U; + /* set the corresponding SPD bit */ + GPIOx_SPD(gpio_periph) |= (uint32_t)pin ; + } else { + /* output mode max speed:10MHz,2MHz,50MHz */ + temp_mode |= (uint32_t)speed; + } + } + + /* configure the eight low port pins with GPIO_CTL0 */ + for (i = 0U; i < 8U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL0(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } + } + /* configure the eight high port pins with GPIO_CTL1 */ + for (i = 8U; i < 16U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL1(gpio_periph); + + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(i - 8U); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i - 8U, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } + } +} + +/*! + \brief set GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if (RESET != bit_value) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } else { + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] data: specify the value to be written to the port output data register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval input status of gpio pin: SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if ((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO port input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval input status of gpio all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t)(GPIO_ISTAT(gpio_periph)); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval output status of gpio pin: SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if ((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO port output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[out] none + \retval output status of gpio all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return ((uint16_t)GPIO_OCTL(gpio_periph)); +} + +/*! + \brief lock GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) + \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief configure GPIO pin event output + \param[in] output_port: gpio event output port + \arg GPIO_EVENT_PORT_GPIOA: event output port A + \arg GPIO_EVENT_PORT_GPIOB: event output port B + \arg GPIO_EVENT_PORT_GPIOC: event output port C + \arg GPIO_EVENT_PORT_GPIOD: event output port D + \arg GPIO_EVENT_PORT_GPIOE: event output port E + \param[in] output_pin: GPIO_EVENT_PIN_x(x=0..15) + \param[out] none + \retval none +*/ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) +{ + uint32_t reg = 0U; + reg = AFIO_EC; + + /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ + reg &= (uint32_t)(~(AFIO_EC_PORT | AFIO_EC_PIN)); + + reg |= (uint32_t)((uint32_t)output_port << 0x04U); + reg |= (uint32_t)output_pin; + + AFIO_EC = reg; +} + +/*! + \brief enable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_enable(void) +{ + AFIO_EC |= AFIO_EC_EOE; +} + +/*! + \brief disable GPIO pin event output + \param[in] none + \param[out] none + \retval none +*/ +void gpio_event_output_disable(void) +{ + AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); +} + +/*! + \brief select GPIO pin exti sources + \param[in] output_port: gpio event output port + \arg GPIO_PORT_SOURCE_GPIOA: output port source A + \arg GPIO_PORT_SOURCE_GPIOB: output port source B + \arg GPIO_PORT_SOURCE_GPIOC: output port source C + \arg GPIO_PORT_SOURCE_GPIOD: output port source D + \arg GPIO_PORT_SOURCE_GPIOE: output port source E + \arg GPIO_PORT_SOURCE_GPIOF: output port source F + \arg GPIO_PORT_SOURCE_GPIOG: output port source G + \param[in] output_pin: GPIO_PIN_SOURCE_0(x=0..15) + \param[out] none + \retval none +*/ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) +{ + uint32_t source = 0U; + source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)); + + /* select EXTI sources */ + if (GPIO_PIN_SOURCE_4 > output_pin) { + /* select EXTI0/EXTI1/EXTI2/EXTI3 */ + AFIO_EXTISS0 &= ~source; + AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + } else if (GPIO_PIN_SOURCE_8 > output_pin) { + /* select EXTI4/EXTI5/EXTI6/EXTI7 */ + AFIO_EXTISS1 &= ~source; + AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + } else if (GPIO_PIN_SOURCE_12 > output_pin) { + /* select EXTI8/EXTI9/EXTI10/EXTI11 */ + AFIO_EXTISS2 &= ~source; + AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + } else { + /* select EXTI12/EXTI13/EXTI14/EXTI15 */ + AFIO_EXTISS3 &= ~source; + AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); + } +} + +#ifdef GD32F30X_CL +/*! + \brief select ethernet MII or RMII PHY + \param[in] enet_sel: ethernet MII or RMII PHY selection + \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY + \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY + \param[out] none + \retval none +*/ +void gpio_ethernet_phy_select(uint32_t enet_sel) +{ + /* clear AFIO_PCF0_ENET_PHY_SEL bit */ + AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); + + /* select MII or RMII PHY */ + AFIO_PCF0 |= (uint32_t)enet_sel; +} +#endif /* GD32F30X_CL */ + +/*! + \brief configure GPIO pin remap + \param[in] gpio_remap: select the pin to remap + \arg GPIO_SPI0_REMAP: SPI0 remapping + \arg GPIO_I2C0_REMAP: I2C0 remapping + \arg GPIO_USART0_REMAP: USART0 remapping + \arg GPIO_USART1_REMAP: USART1 remapping + \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping + \arg GPIO_USART2_FULL_REMAP: USART2 full remapping + \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping + \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping + \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping + \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping + \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping + \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping + \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping + \arg GPIO_TIMER3_REMAP: TIMER3 remapping + \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F30X_CL devices) + \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F30X_CL devices) + \arg GPIO_PD01_REMAP: PD01 remapping + \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F30X_CL devices and GD32F30X_HD devices) + \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F30X_CL devices) + \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F30X_CL devices) + \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST + \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled + \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled + \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F30X_CL devices) + \arg GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) + \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F30X_CL devices) + \arg GPIO_TIMER8_REMAP: TIMER8 remapping + \arg GPIO_TIMER9_REMAP: TIMER9 remapping + \arg GPIO_TIMER10_REMAP: TIMER10 remapping + \arg GPIO_TIMER12_REMAP: TIMER12 remapping + \arg GPIO_TIMER13_REMAP: TIMER13 remapping + \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect + \arg GPIO_CTC_REMAP0: CTC remapping(PD15) + \arg GPIO_CTC_REMAP1: CTC remapping(PF0) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue) +{ + uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; + + if (((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)) { + /* get AFIO_PCF1 regiter value */ + temp_reg = AFIO_PCF1; + } else { + /* get AFIO_PCF0 regiter value */ + temp_reg = AFIO_PCF0; + } + + temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U; + remap1 = gpio_remap & LSB_16BIT_MASK; + + /* judge pin remap type */ + if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) { + temp_reg &= PCF_SWJCFG_MASK; + AFIO_PCF0 &= PCF_SWJCFG_MASK; + } else if (PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)) { + remap2 = ((uint32_t)0x03U) << temp_mask; + temp_reg &= ~remap2; + temp_reg |= ~PCF_SWJCFG_MASK; + } else { + temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U) * 0x10U)); + temp_reg |= ~PCF_SWJCFG_MASK; + } + + /* set pin remap value */ + if (DISABLE != newvalue) { + temp_reg |= (remap1 << ((gpio_remap >> 0x15U) * 0x10U)); + } + + if (AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)) { + /* set AFIO_PCF1 regiter value */ + AFIO_PCF1 = temp_reg; + } else { + /* set AFIO_PCF0 regiter value */ + AFIO_PCF0 = temp_reg; + } +} + +/*! + \brief configure the I/O compensation cell + \param[in] compensation: specifies the I/O compensation cell mode + \arg GPIO_COMPENSATION_ENABLE: I/O compensation cell is enabled + \arg GPIO_COMPENSATION_DISABLE: I/O compensation cell is disabled + \param[out] none + \retval none +*/ +void gpio_compensation_config(uint32_t compensation) +{ + uint32_t reg; + reg = AFIO_CPSCTL; + + /* reset the AFIO_CPSCTL_CPS_EN bit and set according to gpio_compensation */ + reg &= ~AFIO_CPSCTL_CPS_EN; + AFIO_CPSCTL = (reg | compensation); +} + +/*! + \brief check the I/O compensation cell is ready or not + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus gpio_compensation_flag_get(void) +{ + if (((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)) { + return SET; + } else { + return RESET; + } +} + + + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c new file mode 100644 index 0000000000..c11638ba5b --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c @@ -0,0 +1,708 @@ +/*! + \file gd32f30x_i2c.c + \brief I2C driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_i2c.h" + +#define I2CCLK_MAX 0x7fU /*!< i2cclk max value */ +#define I2C_FLAG_MASK 0x0000FFFFU /*!< i2c flag mask */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch (i2c_periph) { + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + and fast mode plus (up to 1MHz) + \param[in] dutycyc: duty cycle in fast mode or fast mode plus + \arg I2C_DTCY_2: T_low/T_high=2 + \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1 / 1000000U); + if (freq >= I2CCLK_MAX) { + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if (100000U >= clkspeed) { + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if (risetime >= I2CCLK_MAX) { + I2C_RT(i2c_periph) = I2CCLK_MAX; + } else { + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if (clkc < 0x04U) { + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + } else if (400000U >= clkspeed) { + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if (I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if (0U == (clkc & I2C_CKCFG_CLKC)) { + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + } else { + /* fast mode plus, the maximum SCL rise time is 120ns */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)120U) / (uint32_t)1000U) + (uint32_t)1U); + if (I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + /* enable fast mode */ + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + /* enable I2C fast mode plus */ + I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief SMBus type selection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + \arg I2C_SMBUS_DEVICE: device + \arg I2C_SMBUS_HOST: host + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if (I2C_SMBUS_HOST == type) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + if (I2C_ACK_ENABLE == ack) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } +} + +/*! + \brief I2C POAP position configure + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + /* configure I2C POAP position */ + if (I2C_ACKPOS_NEXT == pos) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } +} + +/*! + \brief master send slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + if (I2C_TRANSMITTER == trandirection) { + addr = addr & I2C_TRANSMITTER; + } else { + addr = addr | I2C_RECEIVER; + } + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief dual-address mode switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dualaddr: + \arg I2C_DUADEN_DISABLE: disable dual-address mode + \arg I2C_DUADEN_ENABLE: enable dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) +{ + if (I2C_DUADEN_ENABLE == dualaddr) { + I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; + } else { + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); + } +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief enable I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable + \param[out] none + \retval none +*/ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief flag indicating DMA last transfer + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled + \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching enable or disable */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_DISSTRC); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief software reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag) +{ + uint32_t reg = 0U; + FlagStatus reval = RESET; + /* get the flag in which register */ + reg = (BIT(31) & flag); + if ((BIT(31) == reg)) { + if ((I2C_STAT1(i2c_periph) & (flag & I2C_FLAG_MASK))) { + reval = SET; + } else { + reval = RESET; + } + } else { + if ((I2C_STAT0(i2c_periph) & (flag & I2C_FLAG_MASK))) { + reval = SET; + } else { + reval = RESET; + } + } + /* return the flag status */ + return reval; +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: flag type + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag) +{ + if (I2C_FLAG_ADDSEND == flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_STAT0(i2c_periph) &= ~(flag); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] inttype: interrupt type + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype) +{ + I2C_CTL1(i2c_periph) |= (inttype); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] inttype: interrupt type + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype) +{ + I2C_CTL1(i2c_periph) &= ~(inttype); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: interrupt flag + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag) +{ + uint32_t evie, errie, bufie; + + evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE; + errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE; + /* check I2C event interrupt enable bit */ + if ((intflag & 0x00ffU) && evie) { + if (intflag & 0x001fU) { + /* check I2C event flags except TBE and RBNE */ + if (intflag & I2C_STAT0(i2c_periph)) { + return SET; + } else { + return RESET; + } + } else { + /* check I2C event flags TBE and RBNE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + if (bufie) { + if (intflag & I2C_STAT0(i2c_periph)) { + return SET; + } else { + return RESET; + } + } else { + return RESET; + } + } + /* check I2C error interrupt enable bit */ + } else if ((intflag & 0xff00U) && errie) { + /* check I2C error flags */ + if (intflag & I2C_STAT0(i2c_periph)) { + return SET; + } else { + return RESET; + } + } else { + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] intflag: interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag) +{ + if (I2C_INT_FLAG_ADDSEND == intflag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_STAT0(i2c_periph) &= ~(intflag); + } +} + +/*! + \brief I2C PEC calculation on or off + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC + \param[out] none + \retval none +*/ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV) >> 8); +} + +/*! + \brief I2C issue alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* issue alert through SMBA pin configure*/ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief enable or disable I2C ARP protocol in SMBus switch + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c new file mode 100644 index 0000000000..db79f1a6e9 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c @@ -0,0 +1,171 @@ +/*! + \file gd32f30x_misc.c + \brief MISC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + /* use the priority group value to get the temp_pre and the temp_sub */ + if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) { + temp_pre = 0U; + temp_sub = 0x4U; + } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) { + temp_pre = 1U; + temp_sub = 0x3U; + } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) { + temp_pre = 2U; + temp_sub = 0x2U; + } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) { + temp_pre = 3U; + temp_sub = 0x1U; + } else if (((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) { + temp_pre = 4U; + temp_sub = 0x0U; + } else { + } + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if (SYSTICK_CLKSOURCE_HCLK == systick_clksource) { + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } else { + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c new file mode 100644 index 0000000000..f3a92af81c --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c @@ -0,0 +1,367 @@ +/*! + \file gd32f30x_pmu.c + \brief PMU driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_pmu.h" + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + \arg PMU_LVDT_0: voltage threshold is 2.1V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage + this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL + \param[in] ldo_output: + \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode + \arg PMU_LDOVS_MID: low-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_HIGH: low-driver mode disable in deep-sleep mode + \param[out] none + \retval none +*/ +void pmu_ldo_output_select(uint32_t ldo_output) +{ + PMU_CTL &= ~PMU_CTL_LDOVS; + PMU_CTL |= ldo_output; +} + +/*! + \brief switch high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] highdr_switch: + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch + \param[out] none + \retval none +*/ +void pmu_highdriver_switch_select(uint32_t highdr_switch) +{ + /* wait for HDRF flag set */ + while (SET != pmu_flag_get(PMU_FLAG_HDRF)) { + } + PMU_CTL &= ~PMU_CTL_HDS; + PMU_CTL |= highdr_switch; +} + +/*! + \brief enable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_LDEN; +} + +/*! + \brief disable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; +} + +/*! + \brief enable high-driver mode + this bit set by software only when IRC16M or HXTAL used as system clock + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_HDEN; +} + +/*! + \brief disable high-driver mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_HDEN; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief driver mode when use low power LDO + \param[in] mode: + \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO + \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_lowpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDLP; + PMU_CTL |= mode; +} + +/*! + \brief driver mode when use normal power LDO + \param[in] mode: + \arg PMU_NORMALDR_NORMALPWR: normal driver when use low power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_normalpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDNP; + PMU_CTL |= mode; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if (WFI_CMD == sleepmodecmd) { + __WFI(); + } else { + __WFE(); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo + \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] deepsleepmodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd) +{ + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* select WFI or WFE command to enter deepsleep mode */ + if (WFI_CMD == deepsleepmodecmd) { + __WFI(); + } else { + __SEV(); + __WFE(); + __WFE(); + } + /* reset sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work at standby mode + \param[in] standbymodecmd: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_standbymode(uint8_t standbymodecmd) +{ + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* select WFI or WFE command to enter standby mode */ + if (WFI_CMD == standbymodecmd) { + __WFI(); + } else { + __WFE(); + } +} + +/*! + \brief clear flag bit + \param[in] flag_reset: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag_reset) +{ + switch (flag_reset) { + case PMU_FLAG_RESET_WAKEUP: + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + break; + case PMU_FLAG_RESET_STANDBY: + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + break; + default : + break; + } +} + +/*! + \brief get flag state + \param[in] flag: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag + \arg PMU_FLAG_HDRF: high-driver ready flag + \arg PMU_FLAG_HDSRF: high-driver switch ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + if (PMU_CS & flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief enable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief enable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(void) +{ + PMU_CS |= PMU_CS_WUPEN; +} + +/*! + \brief disable wakeup pin + \param[in] none + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(void) +{ + PMU_CS &= ~PMU_CS_WUPEN; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c new file mode 100644 index 0000000000..13fadc5c5c --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c @@ -0,0 +1,1301 @@ +/*! + \file gd32f30x_rcu.c + \brief RCU driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_rcu.h" + +/* define clock source */ +#define SEL_IRC8M ((uint16_t)0U) +#define SEL_HXTAL ((uint16_t)1U) +#define SEL_PLL ((uint16_t)2U) + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + rcu_osci_stab_wait(RCU_IRC8M); + + /* reset CFG0 register */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | + RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBDPSC_2); +#elif defined(GD32F30X_CL) + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | + RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | + RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBFSPSC_2); +#endif /* GD32F30X_HD and GD32F30X_XD */ + /* reset CTL register */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + RCU_CTL &= ~RCU_CTL_HXTALBPS; +#ifdef GD32F30X_CL + RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); +#endif /* GD32F30X_CL */ + + /* reset INT and CFG1 register */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + RCU_INT = 0x009f0000U; + RCU_CFG1 &= ~(RCU_CFG1_ADCPSC_3 | RCU_CFG1_PLLPRESEL); +#elif defined(GD32F30X_CL) + RCU_INT = 0x00ff0000U; + RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | + RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL | RCU_CFG1_ADCPSC_3 | + RCU_CFG1_PLLPRESEL | RCU_CFG1_PLL2MF_4); +#endif /* GD32F30X_HD and GD32F30X_XD */ +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF : alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_CTC: CTC clock + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock + \arg RCU_AF: alternate function clock + \arg RCU_CRC: CRC clock + \arg RCU_DMAx (x=0,1): DMA clock + \arg RCU_ENET: ENET clock(CL series available) + \arg RCU_ENETTX: ENETTX clock(CL series available) + \arg RCU_ENETRX: ENETRX clock(CL series available) + \arg RCU_USBD: USBD clock(HD,XD series available) + \arg RCU_USBFS: USBFS clock(CL series available) + \arg RCU_EXMC: EXMC clock + \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_SPIx (x=0,1,2): SPI clock + \arg RCU_USARTx (x=0,1,2): USART clock + \arg RCU_UARTx (x=3,4): UART clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock + \arg RCU_RTC: RTC clock + \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock + \arg RCU_SDIO: SDIO clock(not available for CL series) + \arg RCU_CTC: CTC clock + \arg RCU_BKPI: BKP interface clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC + \arg RCU_CTCRST: reset CTC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports + \arg RCU_AFRST : reset alternate function clock + \arg RCU_ENETRST: reset ENET(CL series available) + \arg RCU_USBDRST: reset USBD(HD,XD series available) + \arg RCU_USBFSRST: reset USBFS(CL series available) + \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1,2): reset USART + \arg RCU_UARTxRST (x=3,4): reset UART + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC + \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC + \arg RCU_CTCRST: reset CTC + \arg RCU_BKPIRST: reset BKPI + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP domain + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP domain reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + reg &= ~RCU_CFG0_SCS; + RCU_CFG0 = (reg | ck_sys); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source + \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source + \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the AHBPSC bits and set according to ck_ahb */ + reg &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (reg | ck_ahb); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB1PSC and set according to ck_apb1 */ + reg &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (reg | ck_apb1); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the APB2PSC and set according to ck_apb2 */ + reg &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (reg | ck_apb2); +} + +/*! + \brief configure the CK_OUT0 clock source + \param[in] ckout0_src: CK_OUT0 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUT0SRC_NONE: no clock selected + \arg RCU_CKOUT0SRC_CKSYS: system clock selected + \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected + \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected + \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected + \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected + \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected + \arg RCU_CKOUT0SRC_EXT1: EXT1 selected + \arg RCU_CKOUT0SRC_CKPLL2: PLL selected + \param[out] none + \retval none +*/ +void rcu_ckout0_config(uint32_t ckout0_src) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* reset the CKOUT0SRC, set according to ckout0_src */ + reg &= ~RCU_CFG0_CKOUT0SEL; + RCU_CFG0 = (reg | ckout0_src); +} + +/*! + \brief configure the main PLL clock + \param[in] pll_src: PLL clock source selection + \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL + \arg RCU_PLLSRC_HXTAL_IRC48M: HXTAL or IRC48M selected as source clock of PLL + \param[in] pll_mul: PLL clock multiplication factor + \arg RCU_PLL_MULx (XD series x = 2..63, CL series x = 2..14, 16..63, 6.5) + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + + /* PLL clock source and multiplication factor configuration */ + reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + reg |= (pll_src | pll_mul); + + RCU_CFG0 = reg; +} + +/*! + \brief configure the PLL clock source preselection + \param[in] pll_presel: PLL clock source preselection + \arg RCU_PLLPRESRC_HXTAL: HXTAL selected as PLL source clock + \arg RCU_PLLPRESRC_IRC48M: CK_PLL selected as PREDV0 input source clock + \param[out] none + \retval none +*/ +void rcu_pllpresel_config(uint32_t pll_presel) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + + /* PLL clock source preselection */ + reg &= ~RCU_CFG1_PLLPRESEL; + reg |= pll_presel; + + RCU_CFG1 = reg; +} + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) +/*! + \brief configure the PREDV0 division factor + \param[in] predv0_div: PREDV0 division factor + \arg RCU_PREDV0_DIVx, x = 1,2 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG0; + /* reset PREDV0 bit */ + reg &= ~RCU_CFG0_PREDV0; + if (RCU_PREDV0_DIV2 == predv0_div) { + /* set the PREDV0 bit */ + reg |= RCU_CFG0_PREDV0; + } + + RCU_CFG0 = reg; +} +#elif defined(GD32F30X_CL) +/*! + \brief configure the PREDV0 division factor and clock source + \param[in] predv0_source: PREDV0 input clock source selection + \arg RCU_PREDV0SRC_HXTAL_IRC48M: HXTAL or IRC48M selected as PREDV0 input source clock + \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock + \param[in] predv0_div: PREDV0 division factor + \arg RCU_PREDV0_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset PREDV0SEL and PREDV0 bits */ + reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); + /* set the PREDV0SEL and PREDV0 division factor */ + reg |= (predv0_source | predv0_div); + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PREDV1 division factor + \param[in] predv1_div: PREDV1 division factor + \arg RCU_PREDV1_DIVx, x = 1..16 + \param[out] none + \retval none +*/ +void rcu_predv1_config(uint32_t predv1_div) +{ + uint32_t reg = 0U; + + reg = RCU_CFG1; + /* reset the PREDV1 bits */ + reg &= ~RCU_CFG1_PREDV1; + /* set the PREDV1 division factor */ + reg |= predv1_div; + + RCU_CFG1 = reg; +} + +/*! + \brief configure the PLL1 clock + \param[in] pll_mul: PLL clock multiplication factor + \arg RCU_PLL1_MULx (x = 8..16, 20) + \param[out] none + \retval none +*/ +void rcu_pll1_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL1MF; + RCU_CFG1 |= pll_mul; +} + +/*! + \brief configure the PLL2 clock + \param[in] pll_mul: PLL clock multiplication factor + \arg RCU_PLL2_MULx (x = 8..16, 18..32, 40) + \param[out] none + \retval none +*/ +void rcu_pll2_config(uint32_t pll_mul) +{ + RCU_CFG1 &= ~RCU_CFG1_PLL2MF; + RCU_CFG1 |= pll_mul; +} +#endif /* GD32F30X_HD and GD32F30X_XD */ + +/*! + \brief configure the ADC prescaler factor + \param[in] adc_psc: ADC prescaler factor + \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 + \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 + \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 + \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 + \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 + \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 + \arg RCU_CKADC_CKAHB_DIV5: ADC prescaler select CK_AHB/5 + \arg RCU_CKADC_CKAHB_DIV6: ADC prescaler select CK_AHB/6 + \arg RCU_CKADC_CKAHB_DIV10: ADC prescaler select CK_AHB/10 + \arg RCU_CKADC_CKAHB_DIV20: ADC prescaler select CK_AHB/20 + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(uint32_t adc_psc) +{ + uint32_t reg0, reg1; + + /* reset the ADCPSC bits */ + reg0 = RCU_CFG0; + reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); + reg1 = RCU_CFG1; + reg1 &= ~RCU_CFG1_ADCPSC_3; + + /* set the ADC prescaler factor */ + switch (adc_psc) { + case RCU_CKADC_CKAPB2_DIV2: + case RCU_CKADC_CKAPB2_DIV4: + case RCU_CKADC_CKAPB2_DIV6: + case RCU_CKADC_CKAPB2_DIV8: + reg0 |= (adc_psc << 14); + break; + + case RCU_CKADC_CKAPB2_DIV12: + case RCU_CKADC_CKAPB2_DIV16: + adc_psc &= ~BIT(2); + reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); + break; + + case RCU_CKADC_CKAHB_DIV5: + case RCU_CKADC_CKAHB_DIV6: + case RCU_CKADC_CKAHB_DIV10: + case RCU_CKADC_CKAHB_DIV20: + adc_psc &= ~BITS(2, 3); + reg0 |= (adc_psc << 14); + reg1 |= RCU_CFG1_ADCPSC_3; + break; + + default: + break; + } + + /* set the register */ + RCU_CFG0 = reg0; + RCU_CFG1 = reg1; +} + +/*! + \brief configure the USBD/USBFS prescaler factor + \param[in] adc_div: USB prescaler factor + \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 + \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 + \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 + \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 + \arg RCU_CKUSB_CKPLL_DIV3: USBD/USBFS prescaler select CK_PLL/3 + \arg RCU_CKUSB_CKPLL_DIV3_5: USBD/USBFS prescaler select CK_PLL/3.5 + \arg RCU_CKUSB_CKPLL_DIV4: USBD/USBFS prescaler select CK_PLL/4 + \param[out] none + \retval none +*/ +void rcu_usb_clock_config(uint32_t usb_psc) +{ + uint32_t reg; + + reg = RCU_CFG0; + + /* configure the USBD/USBFS prescaler factor */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + reg &= ~RCU_CFG0_USBDPSC; +#elif defined(GD32F30X_CL) + reg &= ~RCU_CFG0_USBFSPSC; +#endif /* GD32F30X_HD and GD32F30X_XD */ + + RCU_CFG0 = (reg | usb_psc); +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + uint32_t reg; + + reg = RCU_BDCTL; + /* reset the RTCSRC bits and set according to rtc_clock_source */ + reg &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL = (reg | rtc_clock_source); +} + +#ifdef GD32F30X_CL +/*! + \brief configure the I2S1 clock source selection + \param[in] i2s_clock_source: I2S1 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock + \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock + \param[out] none + \retval none +*/ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S1SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S1SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} + +/*! + \brief configure the I2S2 clock source selection + \param[in] i2s_clock_source: I2S2 clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock + \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock + \param[out] none + \retval none +*/ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source) +{ + uint32_t reg; + + reg = RCU_CFG1; + /* reset the I2S2SEL bit and set according to i2s_clock_source */ + reg &= ~RCU_CFG1_I2S2SEL; + RCU_CFG1 = (reg | i2s_clock_source); +} +#endif /* GD32F30X_CL */ + +/*! + \brief configure the CK48M clock source selection + \param[in] ck48m_clock_source: CK48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CK48MSRC_CKPLL: CK_PLL selected as CK48M source clock + \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock + \param[out] none + \retval none +*/ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the CK48MSEL bit and set according to ck48m_clock_source */ + reg &= ~RCU_ADDCTL_CK48MSEL; + RCU_ADDCTL = (reg | ck48m_clock_source); +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) + \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval none +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + /* get the rcu flag */ + if (RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + /* get the rcu interrupt flag */ + if (RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTAL_LOWDRI: lower driving capability + \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability + \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability + \arg RCU_LXTAL_HIGHDRI: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + uint32_t reg; + + reg = RCU_BDCTL; + + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + reg &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL = (reg | lxtal_dricap); +} + +/*! + \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + + switch (osci) { + /* wait HXTAL stable */ + case RCU_HXTAL: + while ((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { + reval = SUCCESS; + } + break; + + /* wait LXTAL stable */ + case RCU_LXTAL: + while ((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while ((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC48M stable */ + case RCU_IRC48M: + while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { + reval = SUCCESS; + } + break; + +#ifdef GD32F30X_CL + /* wait PLL1 stable */ + case RCU_PLL1_CK: + while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) { + reval = SUCCESS; + } + break; + /* wait PLL2 stable */ + case RCU_PLL2_CK: + while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if (RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) { + reval = SUCCESS; + } + break; +#endif /* GD32F30X_CL */ + + default: + break; + } + + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) + \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) + \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) + \arg RCU_PLL_CK: phase locked loop(PLL) + \arg RCU_PLL1_CK: phase locked loop 1(CL series only) + \arg RCU_PLL2_CK: phase locked loop 2(CL series only) + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch (osci) { + /* enable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg | RCU_CTL_HXTALBPS); + break; + /* enable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F30X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F30X_CL */ + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + + switch (osci) { + /* disable HXTAL to bypass mode */ + case RCU_HXTAL: + reg = RCU_CTL; + RCU_CTL &= ~RCU_CTL_HXTALEN; + RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); + break; + /* disable LXTAL to bypass mode */ + case RCU_LXTAL: + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: +#ifdef GD32F30X_CL + case RCU_PLL1_CK: + case RCU_PLL2_CK: +#endif /* GD32F30X_CL */ + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ + +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL |= RCU_CTL_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL &= ~RCU_CTL_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) +{ + uint32_t reg; + + reg = RCU_CTL; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + reg &= ~RCU_CTL_IRC8MADJ; + RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); +} + +/*! + \brief deep-sleep mode voltage select + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V + \arg RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + dsvol &= RCU_DSV_DSLPVS; + RCU_DSV = dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws, ck_freq = 0U; + uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; + uint32_t pllsel, pllpresel, predv0sel, pllmf, ck_src, idx, clk_exp; +#ifdef GD32F30X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F30X_CL */ + + /* exponent of AHB, APB1 and APB2 clock divider */ + uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch (sws) { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) { + /* PLL clock source is HXTAL or IRC48M */ + pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); + + if (RCU_PLLPRESRC_HXTAL == pllpresel) { + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + } else { + /* PLL clock source is IRC48 */ + ck_src = IRC48M_VALUE; + } + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + /* PREDV0 input source clock divided by 2 */ + if (RCU_CFG0_PREDV0 == predv0sel) { + ck_src = HXTAL_VALUE / 2U; + } +#elif defined(GD32F30X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + /* source clock use PLL1 */ + if (RCU_PREDV0SRC_CKPLL1 == predv0sel) { + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if (17U == pll1mf) { + pll1mf = 20U; + } + ck_src = (ck_src / predv1) * pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F30X_HD and GD32F30X_XD */ + } else { + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE / 2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { + pllmf |= 0x10U; + } + if ((RCU_CFG0 & RCU_CFG0_PLLMF_5)) { + pllmf |= 0x20U; + } + if (pllmf < 15U) { + pllmf += 2U; + } else if ((pllmf >= 15U) && (pllmf <= 62U)) { + pllmf += 1U; + } else { + pllmf = 63U; + } + cksys_freq = ck_src * pllmf; +#ifdef GD32F30X_CL + if (15U == pllmf) { + cksys_freq = ck_src * 6U + ck_src / 2U; + } +#endif /* GD32F30X_CL */ + + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch (clock) { + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + default: + break; + } + return ck_freq; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c new file mode 100644 index 0000000000..501b497015 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c @@ -0,0 +1,228 @@ +/*! + \file gd32f30x_rtc.c + \brief RTC driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_rtc.h" + +/*! + \brief enable RTC interrupt + \param[in] interrupt: specify which interrupt to enbale + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + RTC_INTEN |= interrupt; +} + +/*! + \brief disable RTC interrupt + \param[in] interrupt: specify which interrupt to disbale + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + RTC_INTEN &= ~interrupt; +} + +/*! + \brief enter RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_enter(void) +{ + RTC_CTL |= RTC_CTL_CMF; +} + +/*! + \brief exit RTC configuration mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_configuration_mode_exit(void) +{ + RTC_CTL &= ~RTC_CTL_CMF; +} + +/*! + \brief wait RTC last write operation finished flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_lwoff_wait(void) +{ + /* loop until LWOFF flag is set */ + while (RESET == (RTC_CTL & RTC_CTL_LWOFF)) { + } +} + +/*! + \brief wait RTC registers synchronized flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_register_sync_wait(void) +{ + /* clear RSYNF flag */ + RTC_CTL &= ~RTC_CTL_RSYNF; + /* loop until RSYNF flag is set */ + while (RESET == (RTC_CTL & RTC_CTL_RSYNF)) { + } +} + +/*! + \brief get RTC counter value + \param[in] none + \param[out] none + \retval RTC counter value +*/ +uint32_t rtc_counter_get(void) +{ + uint32_t temp = 0x0U; + temp = RTC_CNTL; + temp |= (RTC_CNTH << 16); + return temp; +} + +/*! + \brief set RTC counter value + \param[in] cnt: RTC counter value + \param[out] none + \retval none +*/ +void rtc_counter_set(uint32_t cnt) +{ + rtc_configuration_mode_enter(); + /* set the RTC counter high bits */ + RTC_CNTH = cnt >> 16; + /* set the RTC counter low bits */ + RTC_CNTL = (cnt & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC prescaler value + \param[in] psc: RTC prescaler value + \param[out] none + \retval none +*/ +void rtc_prescaler_set(uint32_t psc) +{ + rtc_configuration_mode_enter(); + /* set the RTC prescaler high bits */ + RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16; + /* set the RTC prescaler low bits */ + RTC_PSCL = (psc & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief set RTC alarm value + \param[in] alarm: RTC alarm value + \param[out] none + \retval none +*/ +void rtc_alarm_config(uint32_t alarm) +{ + rtc_configuration_mode_enter(); + /* set the alarm high bits */ + RTC_ALRMH = alarm >> 16; + /* set the alarm low bits */ + RTC_ALRML = (alarm & RTC_LOW_VALUE); + rtc_configuration_mode_exit(); +} + +/*! + \brief get RTC divider value + \param[in] none + \param[out] none + \retval RTC divider value +*/ +uint32_t rtc_divider_get(void) +{ + uint32_t temp = 0x00U; + temp = (RTC_DIVH & RTC_DIVH_DIV) << 16; + temp |= RTC_DIVL; + return temp; +} + +/*! + \brief get RTC flag status + \param[in] flag: specify which flag status to get + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_FLAG_LWOF: last write operation finished flag + \param[out] none + \retval SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + if (RESET != (RTC_CTL & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear RTC flag status + \param[in] flag: specify which flag status to clear + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + /* clear RTC flag */ + RTC_CTL &= ~flag; +} + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c new file mode 100644 index 0000000000..689c1f072a --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c @@ -0,0 +1,797 @@ +/*! + \file gd32f30x_sdio.c + \brief SDIO driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_sdio.h" + +#define DEFAULT_RESET_VALUE 0x00000000U + +/*! + \brief deinitialize the SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_deinit(void) +{ + SDIO_PWRCTL = DEFAULT_RESET_VALUE; + SDIO_CLKCTL = DEFAULT_RESET_VALUE; + SDIO_CMDAGMT = DEFAULT_RESET_VALUE; + SDIO_CMDCTL = DEFAULT_RESET_VALUE; + SDIO_DATATO = DEFAULT_RESET_VALUE; + SDIO_DATALEN = DEFAULT_RESET_VALUE; + SDIO_DATACTL = DEFAULT_RESET_VALUE; + SDIO_INTC = DEFAULT_RESET_VALUE; + SDIO_INTEN = DEFAULT_RESET_VALUE; +} + +/*! + \brief configure the SDIO clock + \param[in] clock_edge: SDIO_CLK clock edge + \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK + \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK + \param[in] clock_bypass: clock bypass + \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass + \arg SDIO_CLOCKBYPASS_DISABLE: no bypass + \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle + \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on + \param[in] clock_division: clock division, less than 512 + \param[out] none + \retval none +*/ +void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) +{ + uint32_t clock_config = 0U; + clock_config = SDIO_CLKCTL; + /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ + clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); + /* if the clock division is greater or equal to 256, set the DIV[8] */ + if (clock_division >= 256U) { + clock_config |= SDIO_CLKCTL_DIV8; + clock_division -= 256U; + } + /* configure the SDIO_CLKCTL according to the parameters */ + clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); + SDIO_CLKCTL = clock_config; +} + +/*! + \brief enable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief disable hardware clock control + \param[in] none + \param[out] none + \retval none +*/ +void sdio_hardware_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; +} + +/*! + \brief set different SDIO card bus mode + \param[in] bus_mode: SDIO card bus mode + \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode + \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode + \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode + \param[out] none + \retval none +*/ +void sdio_bus_mode_set(uint32_t bus_mode) +{ + /* reset the SDIO card bus mode bits and set according to bus_mode */ + SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; + SDIO_CLKCTL |= bus_mode; +} + +/*! + \brief set the SDIO power state + \param[in] power_state: SDIO power state + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off + \param[out] none + \retval none +*/ +void sdio_power_state_set(uint32_t power_state) +{ + SDIO_PWRCTL = power_state; +} + +/*! + \brief get the SDIO power state + \param[in] none + \param[out] none + \retval SDIO power state + \arg SDIO_POWER_ON: SDIO power on + \arg SDIO_POWER_OFF: SDIO power off +*/ +uint32_t sdio_power_state_get(void) +{ + return SDIO_PWRCTL; +} + +/*! + \brief enable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_enable(void) +{ + SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; +} + +/*! + \brief disable SDIO_CLK clock output + \param[in] none + \param[out] none + \retval none +*/ +void sdio_clock_disable(void) +{ + SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; +} + +/*! + \brief configure the command and response + \param[in] cmd_index: command index, refer to the related specifications + \param[in] cmd_argument: command argument, refer to the related specifications + \param[in] response_type: response type + \arg SDIO_RESPONSETYPE_NO: no response + \arg SDIO_RESPONSETYPE_SHORT: short response + \arg SDIO_RESPONSETYPE_LONG: long response + \param[out] none + \retval none +*/ +void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) +{ + uint32_t cmd_config = 0U; + /* reset the command index, command argument and response type */ + SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; + SDIO_CMDAGMT = cmd_argument; + cmd_config = SDIO_CMDCTL; + cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); + /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ + cmd_config |= (cmd_index | response_type); + SDIO_CMDCTL = cmd_config; +} + +/*! + \brief set the command state machine wait type + \param[in] wait_type: wait type + \arg SDIO_WAITTYPE_NO: not wait interrupt + \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt + \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer + \param[out] none + \retval none +*/ +void sdio_wait_type_set(uint32_t wait_type) +{ + /* reset INTWAIT and WAITDEND */ + SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); + /* set the wait type according to wait_type */ + SDIO_CMDCTL |= wait_type; +} + +/*! + \brief enable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; +} + +/*! + \brief disable the CSM(command state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_csm_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; +} + +/*! + \brief get the last response command index + \param[in] none + \param[out] none + \retval last response command index +*/ +uint8_t sdio_command_index_get(void) +{ + return (uint8_t)SDIO_RSPCMDIDX; +} + +/*! + \brief get the response for the last received command + \param[in] responsex: SDIO response + \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] + \arg SDIO_RESPONSE1: card response[95:64] + \arg SDIO_RESPONSE2: card response[63:32] + \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 + \param[out] none + \retval response for the last received command +*/ +uint32_t sdio_response_get(uint32_t responsex) +{ + uint32_t resp_content = 0U; + switch (responsex) { + case SDIO_RESPONSE0: + resp_content = SDIO_RESP0; + break; + case SDIO_RESPONSE1: + resp_content = SDIO_RESP1; + break; + case SDIO_RESPONSE2: + resp_content = SDIO_RESP2; + break; + case SDIO_RESPONSE3: + resp_content = SDIO_RESP3; + break; + default: + break; + } + return resp_content; +} + +/*! + \brief configure the data timeout, data length and data block size + \param[in] data_timeout: data timeout period in card bus clock periods + \param[in] data_length: number of data bytes to be transferred + \param[in] data_blocksize: size of data block for block transfer + \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte + \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes + \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes + \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes + \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes + \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes + \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes + \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes + \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes + \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes + \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes + \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes + \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes + \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes + \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes + \param[out] none + \retval none +*/ +void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) +{ + /* reset data timeout, data length and data block size */ + SDIO_DATATO &= ~SDIO_DATATO_DATATO; + SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; + SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; + /* configure the related parameters of data */ + SDIO_DATATO = data_timeout; + SDIO_DATALEN = data_length; + SDIO_DATACTL |= data_blocksize; +} + +/*! + \brief configure the data transfer mode and direction + \param[in] transfer_mode: mode of data transfer + \arg SDIO_TRANSMODE_BLOCK: block transfer + \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer + \param[in] transfer_direction: data transfer direction, read or write + \arg SDIO_TRANSDIRECTION_TOCARD: write data to card + \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card + \param[out] none + \retval none +*/ +void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) +{ + uint32_t data_trans = 0U; + /* reset the data transfer mode, transfer direction and set according to the parameters */ + data_trans = SDIO_DATACTL; + data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); + data_trans |= (transfer_mode | transfer_direction); + SDIO_DATACTL = data_trans; +} + +/*! + \brief enable the DSM(data state machine) for data transfer + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DATAEN; +} + +/*! + \brief disable the DSM(data state machine) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dsm_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; +} + +/*! + \brief write data(one word) to the transmit FIFO + \param[in] data: 32-bit data write to card + \param[out] none + \retval none +*/ +void sdio_data_write(uint32_t data) +{ + SDIO_FIFO = data; +} + +/*! + \brief read data(one word) from the receive FIFO + \param[in] none + \param[out] none + \retval received data +*/ +uint32_t sdio_data_read(void) +{ + return SDIO_FIFO; +} + +/*! + \brief get the number of remaining data bytes to be transferred to card + \param[in] none + \param[out] none + \retval number of remaining data bytes to be transferred +*/ +uint32_t sdio_data_counter_get(void) +{ + return SDIO_DATACNT; +} + +/*! + \brief get the number of words remaining to be written or read from FIFO + \param[in] none + \param[out] none + \retval remaining number of words +*/ +uint32_t sdio_fifo_counter_get(void) +{ + return SDIO_FIFOCNT; +} + +/*! + \brief enable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_DMAEN; +} + +/*! + \brief disable the DMA request for SDIO + \param[in] none + \param[out] none + \retval none +*/ +void sdio_dma_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; +} + +/*! + \brief get the flags state of SDIO + \param[in] flag: flags state of SDIO + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_CMDRUN: command transmission in progress flag + \arg SDIO_FLAG_TXRUN: data transmission in progress flag + \arg SDIO_FLAG_RXRUN: data reception in progress flag + \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO + \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO + \arg SDIO_FLAG_TFF: transmit FIFO is full flag + \arg SDIO_FLAG_RFF: receive FIFO is full flag + \arg SDIO_FLAG_TFE: transmit FIFO is empty flag + \arg SDIO_FLAG_RFE: receive FIFO is empty flag + \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag + \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_flag_get(uint32_t flag) +{ + FlagStatus temp_flag = RESET; + if (RESET != (SDIO_STAT & flag)) { + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the pending flags of SDIO + \param[in] flag: flags state of SDIO + \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_FLAG_DTTMOUT: data timeout flag + \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_flag_clear(uint32_t flag) +{ + SDIO_INTC = flag; +} + +/*! + \brief enable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_enable(uint32_t int_flag) +{ + SDIO_INTEN |= int_flag; +} + +/*! + \brief disable the SDIO interrupt + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_TFH: SDIO TFH interrupt + \arg SDIO_INT_RFH: SDIO RFH interrupt + \arg SDIO_INT_TFF: SDIO TFF interrupt + \arg SDIO_INT_RFF: SDIO RFF interrupt + \arg SDIO_INT_TFE: SDIO TFE interrupt + \arg SDIO_INT_RFE: SDIO RFE interrupt + \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval none +*/ +void sdio_interrupt_disable(uint32_t int_flag) +{ + SDIO_INTEN &= ~int_flag; +} + +/*! + \brief get the interrupt flags state of SDIO + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state = 0U; + state = SDIO_STAT; + if (state & int_flag) { + state = SDIO_INTEN; + /* check whether the corresponding bit in SDIO_INTEN is set or not */ + if (state & int_flag) { + return SET; + } + } + return RESET; +} + +/*! + \brief clear the interrupt pending flags of SDIO + \param[in] int_flag: interrupt flags state of SDIO + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + \param[out] none + \retval none +*/ +void sdio_interrupt_flag_clear(uint32_t int_flag) +{ + SDIO_INTC = int_flag; +} + +/*! + \brief enable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWEN; +} + +/*! + \brief disable the read wait mode(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; +} + +/*! + \brief enable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; +} + +/*! + \brief disable the function that stop the read wait process(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_stop_readwait_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; +} + +/*! + \brief set the read wait type(SD I/O only) + \param[in] readwait_type: SD I/O read wait type + \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK + \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] + \param[out] none + \retval none +*/ +void sdio_readwait_type_set(uint32_t readwait_type) +{ + if (SDIO_READWAITTYPE_CLK == readwait_type) { + SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; + } else { + SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; + } +} + +/*! + \brief enable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_enable(void) +{ + SDIO_DATACTL |= SDIO_DATACTL_IOEN; +} + +/*! + \brief disable the SD I/O mode specific operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_operation_disable(void) +{ + SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; +} + +/*! + \brief enable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief disable the SD I/O suspend operation(SD I/O only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_suspend_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; +} + +/*! + \brief enable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; +} + +/*! + \brief disable the CE-ATA command(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; +} + +/*! + \brief enable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_enable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; +} + +/*! + \brief disable the CE-ATA interrupt(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_interrupt_disable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; +} + +/*! + \brief enable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_enable(void) +{ + SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; +} + +/*! + \brief disable the CE-ATA command completion signal(CE-ATA only) + \param[in] none + \param[out] none + \retval none +*/ +void sdio_ceata_command_completion_disable(void) +{ + SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c new file mode 100644 index 0000000000..318a0c3e8e --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c @@ -0,0 +1,822 @@ +/*! + \file gd32f30x_spi.c + \brief SPI driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_spi.h" + +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ +#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ +#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ +#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch (spi_periph) { + case SPI0: + /* reset SPI0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 and I2S1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + case SPI2: + /* reset SPI2 and I2S2 */ + rcu_periph_reset_enable(RCU_SPI2RST); + rcu_periph_reset_disable(RCU_SPI2RST); + break; + default : + break; + } +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +#ifdef GD_MBED_USED +/* initialize SPI parameter */ +void spi_para_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +#else +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +#endif +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPIx(x=1,2) + \param[in] audiosample: I2S audio sample rate + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + +#ifdef GD32F30X_CL + uint32_t pll2mf_4 = 0U; +#endif /* GD32F30X_CL */ + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = 0x0002U; + +#ifdef GD32F30X_CL + /* get the I2S clock source */ + if (((uint32_t)spi_periph) == SPI1) { + /* I2S1 clock source selection */ + clks = I2S1_CLOCK_SEL; + } else { + /* I2S2 clock source selection */ + clks = I2S2_CLOCK_SEL; + } + + if (0U != (RCU_CFG1 & clks)) { + /* get RCU PLL2 clock multiplication factor */ + clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U); + + pll2mf_4 = RCU_CFG1 & RCU_CFG1_PLL2MF_4; + + if (0U == pll2mf_4) { + if ((clks > 5U) && (clks < 15U)) { + /* multiplier is between 8 and 16 */ + clks += 2U; + } else { + if (15U == clks) { + /* multiplier is 20 */ + clks = 20U; + } + } + } else { + if (clks < 15U) { + /* multiplier is between 18 and 32 */ + clks += 18U; + } else { + if (15U == clks) { + /* multiplier is 40 */ + clks = 40U; + } + } + } + + /* get the PREDV1 value */ + i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U); + /* calculate i2sclock based on PLL2 and PREDV1 */ + i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); + } else { + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + } +#else + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); +#endif /* GD32F30X_CL */ + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if (I2S_MCKOUT_ENABLE == mckout) { + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + } else { + if (I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if ((i2sdiv < 2U) || (i2sdiv > 255U)) { + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] mode: I2S operation mode + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if (SPI_DMA_TRANSMIT == dma) { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + } else { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] dma: SPI DMA mode + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if (SPI_DMA_TRANSMIT == dma) { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + } else { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] frame_format: SPI frame size + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* confige SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] transfer_direction: SPI transfer direction + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if (SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + } else { + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + switch (interrupt) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + switch (interrupt) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] interrupt: SPI/I2S interrupt flag status + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch (interrupt) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR: + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if (reg1 && reg2) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] flag: SPI/I2S flag status + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error interrupt flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if (SPI_STAT(spi_periph) & flag) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief set CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] crc: SPI crc value + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) +{ + if (SPI_CRC_TX == crc) { + return ((uint16_t)(SPI_TCRC(spi_periph))); + } else { + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief enable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nssp_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; +} + +/*! + \brief disable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_nssp_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void qspi_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c new file mode 100644 index 0000000000..ecc2024e19 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c @@ -0,0 +1,1897 @@ +/*! + \file gd32f30x_timer.c + \brief TIMER driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_timer.h" + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch (timer_periph) { + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER3: + /* reset TIMER3 */ + rcu_periph_reset_enable(RCU_TIMER3RST); + rcu_periph_reset_disable(RCU_TIMER3RST); + break; + case TIMER4: + /* reset TIMER4 */ + rcu_periph_reset_enable(RCU_TIMER4RST); + rcu_periph_reset_disable(RCU_TIMER4RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER6: + /* reset TIMER6 */ + rcu_periph_reset_enable(RCU_TIMER6RST); + rcu_periph_reset_disable(RCU_TIMER6RST); + break; + case TIMER7: + /* reset TIMER7 */ + rcu_periph_reset_enable(RCU_TIMER7RST); + rcu_periph_reset_disable(RCU_TIMER7RST); + break; +#ifndef GD32F30X_HD + case TIMER8: + /* reset TIMER8 */ + rcu_periph_reset_enable(RCU_TIMER8RST); + rcu_periph_reset_disable(RCU_TIMER8RST); + break; + case TIMER9: + /* reset TIMER9 */ + rcu_periph_reset_enable(RCU_TIMER9RST); + rcu_periph_reset_disable(RCU_TIMER9RST); + break; + case TIMER10: + /* reset TIMER10 */ + rcu_periph_reset_enable(RCU_TIMER10RST); + rcu_periph_reset_disable(RCU_TIMER10RST); + break; + case TIMER11: + /* reset TIMER11 */ + rcu_periph_reset_enable(RCU_TIMER11RST); + rcu_periph_reset_disable(RCU_TIMER11RST); + break; + case TIMER12: + /* reset TIMER12 */ + rcu_periph_reset_enable(RCU_TIMER12RST); + rcu_periph_reset_disable(RCU_TIMER12RST); + break; + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; +#endif /* GD32F30X_HD */ + default: + break; + } +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if ((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) + || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if ((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; + } + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] aligned: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] prescaler: prescaler value + \param[in] pscreload: prescaler reload mode + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if (TIMER_PSC_RELOAD_NOW == pscreload) { + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] counter: the counter value + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..13) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..8,11) + \param[in] spmode: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode) +{ + if (TIMER_SP_MODE_SINGLE == spmode) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + } else if (TIMER_SP_MODE_REPETITIVE == spmode) { + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + } else { + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..13) + \param[in] update: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint8_t update) +{ + if (TIMER_UPDATE_SRC_REGULAR == update) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + } else if (update == TIMER_UPDATE_SRC_GLOBAL) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + } else { + } +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source enable + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if ((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if (RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) &= (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16) + \param[in] dma: timer DMA source enable + \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: timer DMA source enable + \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] dma_request: channel DMA request source selection + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) +{ + if (TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + } else if (TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + } else { + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: please refer to the following parameters + \param[in] dma_baseaddr: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) + \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) + \param[in] dma_lenth: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) + \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,7) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if (ENABLE == newvalue) { + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + } else { + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief channel capture/compare control shadow register enable + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if (ENABLE == newvalue) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + } else { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] ccuctl: channel control shadow register update control + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) +{ + if (TIMER_UPDATECTL_CCU == ccuctl) { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + } else if (TIMER_UPDATECTL_CCUTRI == ccuctl) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + } else { + } +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + } + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocmode: channel output compare mode + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] pulse: channel output pulse value + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch (channel) { + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocshadow: channel output shadow state + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocfast: channel output fast function + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \arg TIMER_CH_2: TIMER channel2 + \arg TIMER_CH_3: TIMER channel3 + \param[in] occlear: channel output clear function + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] ocpolarity: channel output polarity + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7)) + \param[in] ocnpolarity: channel complementary output polarity + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] state: TIMER channel enable state + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7)) + \param[in] ocnstate: TIMER channel complementary output enable state + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] prescaler: channel input capture prescaler value + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch (channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch (channel) { + case TIMER_CH_0: + count_value = TIMER_CH0CV(timer_periph); + break; + case TIMER_CH_1: + count_value = TIMER_CH1CV(timer_periph); + break; + case TIMER_CH_2: + count_value = TIMER_CH2CV(timer_periph); + break; + case TIMER_CH_3: + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] channel: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + if (TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { + icpolarity = TIMER_IC_POLARITY_FALLING; + } else { + icpolarity = TIMER_IC_POLARITY_RISING; + } + + if (TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { + icselection = TIMER_IC_SELECTION_INDIRECTTI; + } else { + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if (TIMER_CH_0 == channel) { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] hallmode: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode) +{ + if (TIMER_HALLINTERFACE_ENABLE == hallmode) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + } else if (TIMER_HALLINTERFACE_DISABLE == hallmode) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + } else { + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] outrigger: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output + \arg TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] slavemode: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable + \arg TIMER_ENCODER_MODE0: encoder mode 0 + \arg TIMER_ENCODER_MODE1: encoder mode 1 + \arg TIMER_ENCODER_MODE2: encoder mode 2 + \arg TIMER_SLAVE_MODE_RESTART: restart mode + \arg TIMER_SLAVE_MODE_PAUSE: pause mode + \arg TIMER_SLAVE_MODE_EVENT: event mode + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] masterslave: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave) +{ + if (TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + } else if (TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + } else { + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t expolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | expolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] decomode: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] intrigger: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extrigger: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] expolarity: + \arg TIMER_IC_POLARITY_RISING: active low or falling edge active + \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t expolarity, uint32_t extfilter) +{ + if (TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + } else { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph, extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] extprescaler: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t expolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter); + + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[in] extprescaler: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] expolarity: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t expolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, expolarity, extfilter); + + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) + \param[in] ccsel: + \arg TIMER_CCSEL_DISABLE: no effect + \arg TIMER_CCSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if (TIMER_CCSEL_ENABLE == ccsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + } else if (TIMER_CCSEL_DISABLE == ccsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + } else { + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,7) + \param[in] outsel: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if (TIMER_OUTSEL_ENABLE == outsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + } else if (TIMER_OUTSEL_DISABLE == outsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + } else { + } +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c new file mode 100644 index 0000000000..252e6535cc --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c @@ -0,0 +1,899 @@ +/*! + \file gd32f30x_usart.c + \brief USART driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_usart.h" + +/*! + \brief reset USART/UART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch (usart_periph) { + case USART0: + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + case USART2: + rcu_periph_reset_enable(RCU_USART2RST); + rcu_periph_reset_disable(RCU_USART2RST); + break; + case UART3: + rcu_periph_reset_enable(RCU_UART3RST); + rcu_periph_reset_disable(RCU_UART3RST); + break; + case UART4: + rcu_periph_reset_enable(RCU_UART4RST); + rcu_periph_reset_disable(RCU_UART4RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch (usart_periph) { + /* get clock frequency */ + case USART0: + uclk = rcu_clock_freq_get(CK_APB2); + break; + case USART1: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case USART2: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART3: + uclk = rcu_clock_freq_get(CK_APB1); + break; + case UART4: + uclk = rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk + baudval / 2U) / baudval; + intdiv = udiv & 0xfff0U; + fradiv = udiv & 0xfU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] paritycfg: configure USART parity + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg ; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wlen: USART word length configure + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] stblen: USART stop bit configure + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + /* configure USART stop bits */ + USART_CTL1(usart_periph) |= stblen; +} +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] txconfig: enable or disable USART transmitter + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_TEN; + ctl |= txconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] rxconfig: enable or disable USART receiver + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL0(usart_periph); + ctl &= ~USART_CTL0_REN; + ctl |= rxconfig; + /* configure transfer mode */ + USART_CTL0(usart_periph) = ctl; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] msbf: LSB/MSB + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_MSBF); + USART_CTL3(usart_periph) |= msbf; +} + +/*! + \brief configure USART inversion + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] invertpara: refer to enum USART_INVERT_CONFIG + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + /* inverted or not the specified siginal */ + switch (invertpara) { + case USART_DINV_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_DINV; + break; + case USART_TXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_TINV; + break; + case USART_RXPIN_ENABLE: + USART_CTL3(usart_periph) |= USART_CTL3_RINV; + break; + case USART_DINV_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); + break; + case USART_TXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); + break; + case USART_RXPIN_DISABLE: + USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); + break; + default: + break; + } +} + +/*! + \brief enable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) |= USART_CTL3_RTEN; +} + +/*! + \brief disable receiver timeout of USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_RTEN); +} + +/*! + \brief set the receiver timeout threshold of USART + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] rtimeout: 0-0xFFFFFF + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] addr: address of USART/UART + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); +} + +/*! + \brief receiver in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_RWU; +} + +/*! + \brief receiver in active mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] wmethod: two methods be used to enter or exit the mute mode + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mask + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure lin break frame length + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] lblen: lin break frame length + \arg USART_LBLEN_10B: 10 bits + \arg USART_LBLEN_11B: 11 bits + \param[out] none + \retval none +*/ +void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); +} + +/*! + \brief send break frame + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_send_break(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; +} + +/*! + \brief enable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half duplex mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable CK pin in synchronous mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_synchronous_clock_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] clen: CK length + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame + \param[in] cph: clock phase + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + uint32_t ctl = 0U; + + /* read USART_CTL1 register */ + ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + /* set CK length, CK phase, CK polarity */ + ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); + + USART_CTL1(usart_periph) = ctl; +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] guat: guard time value + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +{ + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0,1,2) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] scrtnum: smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); + USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum) << 1)); +} + +/*! + \brief configure block length in Smartcard T=1 reception + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] bl: block length + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] psc: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) +{ + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] irlp: IrDA low-power or normal + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable RTS + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_RTSEN; + ctl |= rtsconfig; + /* configure RTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1,2) + \param[in] hardwareflow: enable or disable CTS + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_CTSEN; + ctl |= ctsconfig; + /* configure CTS */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for reception + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENR; + ctl |= dmacmd; + /* configure DMA reception */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) + \param[in] dmacmd: enable or disable DMA for transmission + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + uint32_t ctl = 0U; + + ctl = USART_CTL2(usart_periph); + ctl &= ~USART_CTL2_DENT; + ctl |= dmacmd; + /* configure DMA transmission */ + USART_CTL2(usart_periph) = ctl; +} + +/*! + \brief get flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one among these parameters can be selected + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if (RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +#ifndef GD_MBED_USED +/*! + \brief clear flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one among these parameters can be selected + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +} +#else +/*! + \brief clear flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART flags, refer to usart_flag_enum + only one among these parameters can be selected + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + if ((BIT(USART_BIT_POS(flag)) & 0x1f) != 0U) { + /* read USART_STAT0 and then read USART_DATA to clear error flag */ + USART_STAT0(usart_periph); + USART_DATA(usart_periph); + } else if ((BIT(USART_BIT_POS(flag)) & 0x1b60) != 0U) { + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); + } +} +#endif + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one among these parameters can be selected + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + only one among these parameters can be selected + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) +{ + USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] int_flag + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag + \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag + \param[out] none + \retval FlagStatus +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if (flagstatus && intenable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear USART interrupt flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) + \param[in] flag: USART interrupt flag + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) +{ + USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c new file mode 100644 index 0000000000..f6ada6a13c --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c @@ -0,0 +1,147 @@ +/*! + \file gd32f30x_wwdgt.c + \brief WWDGT driver + + \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f30x_wwdgt.h" + +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + uint32_t reg = 0U; + + reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); + reg |= CTL_CNT(counter_value); + + WWDGT_CTL = reg; +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + uint32_t reg_cfg = 0U, reg_ctl = 0U; + + /* clear WIN and PSC bits, clear CNT bit */ + reg_cfg = (WWDGT_CFG & (~(WWDGT_CFG_WIN | WWDGT_CFG_PSC))); + reg_ctl = (WWDGT_CTL & (~WWDGT_CTL_CNT)); + + /* configure WIN and PSC bits, configure CNT bit */ + reg_cfg |= CFG_WIN(window); + reg_cfg |= prescaler; + reg_ctl |= CTL_CNT(counter); + + WWDGT_CTL = reg_ctl; + WWDGT_CFG = reg_cfg; +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if (WWDGT_STAT & WWDGT_STAT_EWIF) { + return SET; + } + + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT &= (~WWDGT_STAT_EWIF); +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/PeripheralPins.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/PeripheralPins.h new file mode 100644 index 0000000000..14fe0e8621 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/PeripheralPins.h @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +extern const int GD_GPIO_REMAP[]; +extern const int GD_GPIO_MODE[]; +extern const int GD_GPIO_SPEED[]; + +/* ADC */ +#ifdef DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +/* DAC */ +#ifdef DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +/* I2C */ +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +/* PWM */ +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM[]; +#endif + +/* SERIAL */ +#ifdef DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +#ifdef DEVICE_SERIAL_FC +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif +#endif + +/* SPI */ +#ifdef DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +/* CAN */ +#ifdef DEVICE_CAN +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; +#endif + +#endif diff --git a/TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/PortNames.h similarity index 65% rename from TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h rename to targets/TARGET_GigaDevice/TARGET_GD32F30X/PortNames.h index 41b576d8ea..773bed473d 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/PortNames.h @@ -1,5 +1,7 @@ /* mbed Microcontroller Library - * Copyright (c) 2018-2018 ARM Limited + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,10 +15,22 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef MBED_QSPI_FLASH_CONFIG_H -#define MBED_QSPI_FLASH_CONFIG_H +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H -#include "../../MX25RXX35F_config.h" +#ifdef __cplusplus +extern "C" { +#endif +typedef enum { + PORTA = 0, + PORTB = 1, + PORTC = 2, + PORTD = 3, + PORTE = 4, +} PortName; -#endif // MBED_QSPI_FLASH_CONFIG_H +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralNames.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralNames.h new file mode 100644 index 0000000000..a767aa80b1 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralNames.h @@ -0,0 +1,85 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = (int)ADC0, + ADC_1 = (int)ADC1 +} ADCName; + +typedef enum { + DAC_0 = (int)DAC0, + DAC_1 = (int)DAC1, +} DACName; + +typedef enum { + UART_0 = (int)USART0, + UART_1 = (int)USART1, + UART_2 = (int)USART2, + UART_3 = (int)UART3, + UART_4 = (int)UART4 +} UARTName; + +#define STDIO_UART_TX PORTC_10 +#define STDIO_UART_RX PORTC_11 +#define STDIO_UART UART_2 + +typedef enum { + SPI_0 = (int)SPI0, + SPI_1 = (int)SPI1, + SPI_2 = (int)SPI2 +} SPIName; + +typedef enum { + I2C_0 = (int)I2C0, + I2C_1 = (int)I2C1 +} I2CName; + +typedef enum { + PWM_0 = (int)TIMER0, + PWM_1 = (int)TIMER1, + PWM_2 = (int)TIMER2, + PWM_3 = (int)TIMER3, + PWM_4 = (int)TIMER4, + PWM_5 = (int)TIMER7, + PWM_6 = (int)TIMER8, + PWM_7 = (int)TIMER9, + PWM_8 = (int)TIMER10, + PWM_9 = (int)TIMER11, + PWM_10 = (int)TIMER12, + PWM_11 = (int)TIMER13 +} PWMName; + +typedef enum { + CAN_0 = (int)CAN0, + CAN_1 = (int)CAN1 +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralPins.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralPins.c new file mode 100644 index 0000000000..8ffa5f2717 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralPins.c @@ -0,0 +1,358 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + + +/* void pin_function(PinName pin, int function); + configure the speed, mode,and remap function of pins + the parameter function contains the configuration information,show as below + bit 0:2 gpio mode + bit 3:8 remap + bit 9:10 gpio speed + bit 11:15 adc /timer channel +*/ +const int GD_GPIO_REMAP[] = { + 0x00000000, + GPIO_SPI0_REMAP, /* 1 */ + GPIO_I2C0_REMAP, /* 2 */ + GPIO_USART0_REMAP, /* 3 */ + GPIO_USART1_REMAP, /* 4 */ + GPIO_USART2_PARTIAL_REMAP, /* 5 */ + GPIO_USART2_FULL_REMAP, /* 6 */ + GPIO_TIMER0_PARTIAL_REMAP, /* 7 */ + GPIO_TIMER0_FULL_REMAP, /* 8 */ + GPIO_TIMER1_PARTIAL_REMAP0, /* 9 */ + GPIO_TIMER1_PARTIAL_REMAP1, /* 10 */ + GPIO_TIMER1_FULL_REMAP, /* 11 */ + GPIO_TIMER2_PARTIAL_REMAP, /* 12 */ + GPIO_TIMER2_FULL_REMAP, /* 13 */ + GPIO_TIMER3_REMAP, /* 14 */ + GPIO_PD01_REMAP, /* 15 */ +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + GPIO_CAN_PARTIAL_REMAP, /* 16 */ + GPIO_CAN_FULL_REMAP, /* 17 */ +#else + 0, + 0, +#endif +#if (defined(GD32F30X_CL) || defined(GD32F30X_HD)) + GPIO_TIMER4CH3_IREMAP, /* 18 */ +#else + 0, +#endif + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + GPIO_ADC0_ETRGINS_REMAP, /* 19 */ + GPIO_ADC0_ETRGREG_REMAP, /* 20 */ + GPIO_ADC1_ETRGINS_REMAP, /* 21 */ + GPIO_ADC1_ETRGREG_REMAP, /* 22 */ +#else + 0, + 0, + 0, + 0, +#endif + + GPIO_SWJ_NONJTRST_REMAP, /* 23 */ + GPIO_SWJ_SWDPENABLE_REMAP, /* 24 */ + GPIO_SWJ_DISABLE_REMAP, /* 25 */ + +#if (defined(GD32F30X_CL)) + GPIO_CAN0_PARTIAL_REMAP, /* 26 */ + GPIO_CAN0_FULL_REMAP, /* 27 */ + GPIO_ENET_REMAP, /* 28 */ + GPIO_CAN1_REMAP, /* 29 */ + GPIO_SPI2_REMAP, /* 30 */ + GPIO_TIMER1ITR0_REMAP, /* 31 */ + GPIO_PTP_PPS_REMAP, /* 32 */ +#else + 0, + 0, + 0, + 0, + 0, + 0, + 0, +#endif + + GPIO_TIMER8_REMAP, /* 33 */ + GPIO_TIMER9_REMAP, /* 34 */ + GPIO_TIMER10_REMAP, /* 35 */ + GPIO_TIMER12_REMAP, /* 36 */ + GPIO_TIMER13_REMAP, /* 37 */ + GPIO_EXMC_NADV_REMAP, /* 38 */ + GPIO_CTC_REMAP0, /* 39 */ + GPIO_CTC_REMAP1, /* 40 */ +#if (defined(GD32F30X_CL)) + GPIO_ENET_PHY_MII, /* 41 */ + GPIO_ENET_PHY_RMII, /* 42 */ +#else + 0, + 0, +#endif +}; + +/* GPIO MODE */ +const int GD_GPIO_MODE[] = { + GPIO_MODE_AIN, /* 0 */ + GPIO_MODE_IN_FLOATING, /* 1 */ + GPIO_MODE_IPD, /* 2 */ + GPIO_MODE_IPU, /* 3 */ + GPIO_MODE_OUT_OD, /* 4 */ + GPIO_MODE_OUT_PP, /* 5 */ + GPIO_MODE_AF_OD, /* 6 */ + GPIO_MODE_AF_PP, /* 7 */ +}; + +/* GPIO SPEED */ +const int GD_GPIO_SPEED[] = { + GPIO_OSPEED_50MHZ, /* 0 */ + GPIO_OSPEED_10MHZ, /* 1 */ + GPIO_OSPEED_2MHZ, /* 2 */ +}; + +/* ADC PinMap */ +const PinMap PinMap_ADC[] = { + {PORTA_0, ADC_0, 0 | (0 << 11)}, /* ADC0_IN0 */ + {PORTA_1, ADC_0, 0 | (1 << 11)}, /* ADC0_IN1 */ + {PORTA_2, ADC_0, 0 | (2 << 11)}, /* ADC0_IN2 */ + {PORTA_3, ADC_0, 0 | (3 << 11)}, /* ADC0_IN3 */ + {PORTA_4, ADC_0, 0 | (4 << 11)}, /* ADC0_IN4 */ + {PORTA_5, ADC_0, 0 | (5 << 11)}, /* ADC0_IN5 */ + {PORTA_6, ADC_0, 0 | (6 << 11)}, /* ADC0_IN6 */ + {PORTA_7, ADC_0, 0 | (7 << 11)}, /* ADC0_IN7 */ + {PORTB_0, ADC_0, 0 | (8 << 11)}, /* ADC0_IN8 */ + {PORTB_1, ADC_0, 0 | (9 << 11)}, /* ADC0_IN9 */ + {PORTC_0, ADC_0, 0 | (10 << 11)}, /* ADC0_IN10 */ + {PORTC_1, ADC_0, 0 | (11 << 11)}, /* ADC0_IN11 */ + {PORTC_2, ADC_0, 0 | (12 << 11)}, /* ADC0_IN12 */ + {PORTC_3, ADC_0, 0 | (13 << 11)}, /* ADC0_IN13 */ + {PORTC_4, ADC_0, 0 | (14 << 11)}, /* ADC0_IN14 */ + {PORTC_5, ADC_0, 0 | (15 << 11)}, /* ADC0_IN15 */ + {ADC_TEMP, ADC_0, 0 | (16 << 11)}, /* ADC0_IN16 */ + {ADC_VREF, ADC_0, 0 | (17 << 11)}, /* ADC0_IN17 */ + + {PORTA_0_MUL0, ADC_1, 0 | (0 << 11)}, /* ADC1_IN0 */ + {PORTA_1_MUL0, ADC_1, 0 | (1 << 11)}, /* ADC1_IN1 */ + {PORTA_2_MUL0, ADC_1, 0 | (2 << 11)}, /* ADC1_IN2 */ + {PORTA_3_MUL0, ADC_1, 0 | (3 << 11)}, /* ADC1_IN3 */ + {PORTA_4_MUL0, ADC_1, 0 | (4 << 11)}, /* ADC1_IN4 */ + {PORTA_5_MUL0, ADC_1, 0 | (5 << 11)}, /* ADC1_IN5 */ + {PORTA_6_MUL0, ADC_1, 0 | (6 << 11)}, /* ADC1_IN6 */ + {PORTA_7_MUL0, ADC_1, 0 | (7 << 11)}, /* ADC1_IN7 */ + {PORTB_0_MUL0, ADC_1, 0 | (8 << 11)}, /* ADC1_IN8 */ + {PORTB_1_MUL0, ADC_1, 0 | (9 << 11)}, /* ADC1_IN9 */ + {PORTC_0_MUL0, ADC_1, 0 | (10 << 11)}, /* ADC1_IN10 */ + {PORTC_1_MUL0, ADC_1, 0 | (11 << 11)}, /* ADC1_IN11 */ + {PORTC_2_MUL0, ADC_1, 0 | (12 << 11)}, /* ADC1_IN12 */ + {PORTC_3_MUL0, ADC_1, 0 | (13 << 11)}, /* ADC1_IN13 */ + {PORTC_4_MUL0, ADC_1, 0 | (14 << 11)}, /* ADC1_IN14 */ + {PORTC_5_MUL0, ADC_1, 0 | (15 << 11)}, /* ADC1_IN15 */ + {NC, NC, 0} +}; + +/* DAC PinMap */ +const PinMap PinMap_DAC[] = { + {PORTA_4, DAC_0, 0 | (0 << 11)}, /* DAC_OUT0 */ + {PORTA_5, DAC_0, 0 | (1 << 11)}, /* DAC_OUT1 */ + {NC, NC, 0} +}; + + +/* I2C PinMap */ +const PinMap PinMap_I2C_SDA[] = { + {PORTB_7, I2C_0, 6}, + {PORTB_9, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */ + {PORTB_11, I2C_1, 6}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PORTB_6, I2C_0, 6}, + {PORTB_8, I2C_0, 6 | (2 << 3)}, /* GPIO_I2C0_REMAP */ + {PORTB_10, I2C_1, 6}, + {NC, NC, 0} +}; + +/* PWM PinMap */ +const PinMap PinMap_PWM[] = { + {PORTA_8, PWM_0, 7 | (0 << 11)}, /* TIMER0_CH0 - Default */ + {PORTA_9, PWM_0, 7 | (1 << 11)}, /* TIMER0_CH1 - Default */ + {PORTA_10, PWM_0, 7 | (2 << 11)}, /* TIMER0_CH2 - Default */ + {PORTA_11, PWM_0, 7 | (3 << 11)}, /* TIMER0_CH3 - Default */ + {PORTE_9, PWM_0, 7 | (8 << 3) | (0 << 11)}, /* TIMER0_CH0 - GPIO_TIMER0_FULL_REMAP */ + {PORTE_11, PWM_0, 7 | (8 << 3) | (1 << 11)}, /* TIMER0_CH1 - GPIO_TIMER0_FULL_REMAP */ + {PORTE_13, PWM_0, 7 | (8 << 3) | (2 << 11)}, /* TIMER0_CH2 - GPIO_TIMER0_FULL_REMAP */ + {PORTE_14, PWM_0, 7 | (8 << 3) | (3 << 11)}, /* TIMER0_CH3 - GPIO_TIMER0_FULL_REMAP */ + + {PORTA_0, PWM_1, 7 | (0 << 11)}, /* TIMER1_CH0_ETI - Default */ + {PORTA_1, PWM_1, 7 | (1 << 11)}, /* TIMER1_CH1_ETI - Default */ + {PORTA_2, PWM_1, 7 | (2 << 11)}, /* TIMER1_CH2_ETI - Default */ + {PORTA_3, PWM_1, 7 | (3 << 11)}, /* TIMER1_CH3_ETI - Default */ + {PORTA_15, PWM_1, 7 | (9 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI- GPIO_TIMER1_PARTIAL_REMAP0 */ + {PORTB_3, PWM_1, 7 | (9 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_PARTIAL_REMAP0 */ + {PORTB_10, PWM_1, 7 | (10 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_PARTIAL_REMAP1 */ + {PORTB_11, PWM_1, 7 | (10 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_PARTIAL_REMAP1 */ + {PORTA_15, PWM_1, 7 | (11 << 3) | (0 << 11)}, /* TIMER1_CH0_ETI - GPIO_TIMER1_FULL_REMAP */ + {PORTB_3, PWM_1, 7 | (11 << 3) | (1 << 11)}, /* TIMER1_CH1 - GPIO_TIMER1_FULL_REMAP */ + {PORTB_10, PWM_1, 7 | (11 << 3) | (2 << 11)}, /* TIMER1_CH2 - GPIO_TIMER1_FULL_REMAP */ + {PORTB_11, PWM_1, 7 | (11 << 3) | (3 << 11)}, /* TIMER1_CH3 - GPIO_TIMER1_FULL_REMAP */ + + {PORTA_6, PWM_2, 7 | (0 << 11)}, /* TIMER2_CH0 - Default */ + {PORTA_7, PWM_2, 7 | (1 << 11)}, /* TIMER2_CH1 - Default */ + {PORTB_0, PWM_2, 7 | (2 << 11)}, /* TIMER2_CH2 - Default */ + {PORTB_1, PWM_2, 7 | (3 << 11)}, /* TIMER2_CH3 - Default */ + {PORTB_4, PWM_2, 7 | (12 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_PARTIAL_REMAP */ + {PORTB_5, PWM_2, 7 | (12 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_PARTIAL_REMAP */ + {PORTC_6, PWM_2, 7 | (13 << 3) | (0 << 11)}, /* TIMER2_CH0 - GPIO_TIMER2_FULL_REMAP */ + {PORTC_7, PWM_2, 7 | (13 << 3) | (1 << 11)}, /* TIMER2_CH1 - GPIO_TIMER2_FULL_REMAP */ + {PORTC_8, PWM_2, 7 | (13 << 3) | (2 << 11)}, /* TIMER2_CH2 - GPIO_TIMER2_FULL_REMAP */ + {PORTC_9, PWM_2, 7 | (13 << 3) | (3 << 11)}, /* TIMER2_CH3 - GPIO_TIMER2_FULL_REMAP */ + + {PORTB_6, PWM_3, 7 | (0 << 11)}, /* TIMER3_CH0 - Default */ + {PORTB_7, PWM_3, 7 | (1 << 11)}, /* TIMER3_CH1 - Default */ + {PORTB_8, PWM_3, 7 | (2 << 11)}, /* TIMER3_CH2 - Default */ + {PORTB_9, PWM_3, 7 | (3 << 11)}, /* TIMER3_CH3 - Default */ + {PORTD_12, PWM_3, 7 | (14 << 3) | (0 << 11)}, /* TIMER3_CH0 - GPIO_TIMER3_REMAP */ + {PORTD_13, PWM_3, 7 | (14 << 3) | (1 << 11)}, /* TIMER3_CH1 - GPIO_TIMER3_REMAP */ + {PORTD_14, PWM_3, 7 | (14 << 3) | (2 << 11)}, /* TIMER3_CH2 - GPIO_TIMER3_REMAP */ + {PORTD_15, PWM_3, 7 | (14 << 3) | (3 << 11)}, /* TIMER3_CH3 - GPIO_TIMER3_REMAP */ + + {PORTA_0_MUL0, PWM_4, 7 | (0 << 11)}, /* TIMER4_CH0 - Default */ + {PORTA_1_MUL0, PWM_4, 7 | (1 << 11)}, /* TIMER4_CH1 - Default */ + {PORTA_2_MUL0, PWM_4, 7 | (2 << 11)}, /* TIMER4_CH2 - Default */ + {PORTA_3_MUL0, PWM_4, 7 | (3 << 11)}, /* TIMER4_CH3 - Default */ + + {PORTC_6_MUL0, PWM_5, 7 | (0 << 11)}, /* TIMER7_CH0 - Default */ + {PORTC_7_MUL0, PWM_5, 7 | (1 << 11)}, /* TIMER7_CH1 - Default */ + {PORTC_8_MUL0, PWM_5, 7 | (2 << 11)}, /* TIMER7_CH2 - Default */ + {PORTC_9_MUL0, PWM_5, 7 | (3 << 11)}, /* TIMER7_CH3 - Default */ + + {PORTA_2_MUL1, PWM_6, 7 | (0 << 11)}, /* TIMER8_CH0 - Default */ + {PORTA_3_MUL1, PWM_6, 7 | (1 << 11)}, /* TIMER8_CH1 - Default */ + {PORTE_5, PWM_6, 7 | (33 << 3) | (0 << 11)}, /* TIMER8_CH0 - GPIO_TIMER8_REMAP */ + {PORTE_6, PWM_6, 7 | (33 << 3) | (1 << 11)}, /* TIMER8_CH1 - GPIO_TIMER8_REMAP */ + + {PORTB_8_MUL0, PWM_7, 7 | (0 << 11)}, /* TIMER9_CH0 - Default */ + + {PORTB_9_MUL0, PWM_8, 7 | (0 << 11)}, /* TIMER10_CH0 - Default */ + + {PORTB_14, PWM_9, 7 | (0 << 11)}, /* TIMER11_CH0 - Default */ + {PORTB_15, PWM_9, 7 | (1 << 11)}, /* TIMER11_CH1 - Default */ + + {PORTA_6_MUL0, PWM_10, 7 | (0 << 11)}, /* TIMER12_CH0 - Default */ + + {PORTA_7_MUL0, PWM_11, 7 | (0 << 11)}, /* TIMER13_CH0 - Default */ + + {NC, NC, 0} +}; + +/* USART PinMap */ +const PinMap PinMap_UART_TX[] = { + {PORTA_9, UART_0, 7}, + {PORTB_6, UART_0, 7 | (3 << 3)}, /* GPIO_USART0_TX_REMAP */ + {PORTA_2, UART_1, 7}, + {PORTD_5, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_TX_REMAP */ + {PORTB_10, UART_2, 7}, + {PORTC_10, UART_2, 7 | (5 << 3)}, /* GPIO_USART2_TX_PARTIAL_REMAP */ + {PORTD_8, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_TX_FULL_REMAP */ + {PORTC_10_MUL0, UART_3, 7}, + {PORTC_12, UART_4, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PORTA_10, UART_0, 1}, + {PORTB_7, UART_0, 1 | (3 << 3)}, /* GPIO_USART0_RX_REMAP */ + {PORTA_3, UART_1, 1}, + {PORTD_6, UART_1, 1 | (4 << 3)}, /* GPIO_USART1_RX_REMAP */ + {PORTB_11, UART_2, 1}, + {PORTC_11, UART_2, 1 | (5 << 3)}, /* GPIO_USART2_RX_PARTIAL_REMAP */ + {PORTD_9, UART_2, 1 | (6 << 3)}, /* GPIO_USART2_RX_FULL_REMAP */ + {PORTC_11_MUL0, UART_3, 1}, + {PORTD_2, UART_4, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PORTA_12, UART_0, 7}, + {PORTA_1, UART_1, 7}, + {PORTD_4, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_RTS_REMAP */ + {PORTB_14, UART_2, 7}, + {PORTD_12, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_RTS_FULL_REMAP */ + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PORTA_11, UART_0, 7}, + {PORTA_0, UART_1, 7}, + {PORTD_3, UART_1, 7 | (4 << 3)}, /* GPIO_USART1_CTS_REMAP */ + {PORTB_13, UART_2, 7}, + {PORTD_11, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_CTS_FULL_REMAP */ + {NC, NC, 0} +}; + +/* SPI PinMap */ +const PinMap PinMap_SPI_MOSI[] = { + {PORTA_7, SPI_0, 7}, + {PORTB_5, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_15, SPI_1, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PORTA_6, SPI_0, 7}, + {PORTB_4, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_14, SPI_1, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PORTA_5, SPI_0, 7}, + {PORTB_3, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_13, SPI_1, 7}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PORTA_4, SPI_0, 7}, + {PORTA_15, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */ + {PORTB_12, SPI_1, 7}, + {NC, NC, 0} +}; + +/* CAN PinMap */ +const PinMap PinMap_CAN_RD[] = { + {PORTA_11, CAN_0, 3}, + {PORTB_8, CAN_0, 3 | (26 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */ + {PORTD_0, CAN_0, 3 | (27 << 3)}, /* GPIO_CAN0_FULL_REMAP */ + {PORTB_12, CAN_1, 3}, + {PORTB_5, CAN_1, 3 | (29 << 3)}, /* GPIO_CAN1_REMAP */ + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PORTA_12, CAN_0, 7}, + {PORTB_9, CAN_0, 7 | (26 << 3)}, /* GPIO_CAN0_PARTIAL_REMAP */ + {PORTD_1, CAN_0, 7 | (27 << 3)}, /* GPIO_CAN0_FULL_REMAP */ + {PORTB_13, CAN_1, 7}, + {PORTB_6, CAN_1, 7 | (29 << 3)}, /* GPIO_CAN1_REMAP */ + {NC, NC, 0} +}; + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PinNames.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PinNames.h new file mode 100644 index 0000000000..24e4f4c8ee --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PinNames.h @@ -0,0 +1,254 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Multiplex GPIO flag*/ +typedef enum { + MUL0 = 0x100, + MUL1 = 0x200, + MUL2 = 0x300, + MUL3 = 0x400 +} MULx; + +typedef enum { + PORTA_0 = 0x00, + PORTA_0_MUL0 = PORTA_0 | MUL0, + PORTA_1 = 0x01, + PORTA_1_MUL0 = PORTA_1 | MUL0, + PORTA_2 = 0x02, + PORTA_2_MUL0 = PORTA_2 | MUL0, + PORTA_2_MUL1 = PORTA_2 | MUL1, + PORTA_3 = 0x03, + PORTA_3_MUL0 = PORTA_3 | MUL0, + PORTA_3_MUL1 = PORTA_3 | MUL1, + PORTA_4 = 0x04, + PORTA_4_MUL0 = PORTA_4 | MUL0, + PORTA_5 = 0x05, + PORTA_5_MUL0 = PORTA_5 | MUL0, + PORTA_6 = 0x06, + PORTA_6_MUL0 = PORTA_6 | MUL0, + PORTA_7 = 0x07, + PORTA_7_MUL0 = PORTA_7 | MUL0, + PORTA_8 = 0x08, + PORTA_9 = 0x09, + PORTA_10 = 0x0A, + PORTA_11 = 0x0B, + PORTA_12 = 0x0C, + PORTA_13 = 0x0D, + PORTA_14 = 0x0E, + PORTA_15 = 0x0F, + + PORTB_0 = 0x10, + PORTB_0_MUL0 = PORTB_0 | MUL0, + PORTB_1 = 0x11, + PORTB_1_MUL0 = PORTB_1 | MUL0, + PORTB_2 = 0x12, + PORTB_3 = 0x13, + PORTB_4 = 0x14, + PORTB_5 = 0x15, + PORTB_6 = 0x16, + PORTB_7 = 0x17, + PORTB_8 = 0x18, + PORTB_8_MUL0 = PORTB_8 | MUL0, + PORTB_9 = 0x19, + PORTB_9_MUL0 = PORTB_9 | MUL0, + PORTB_10 = 0x1A, + PORTB_11 = 0x1B, + PORTB_12 = 0x1C, + PORTB_13 = 0x1D, + PORTB_14 = 0x1E, + PORTB_15 = 0x1F, + + PORTC_0 = 0x20, + PORTC_0_MUL0 = PORTC_0 | MUL0, + PORTC_1 = 0x21, + PORTC_1_MUL0 = PORTC_1 | MUL0, + PORTC_2 = 0x22, + PORTC_2_MUL0 = PORTC_2 | MUL0, + PORTC_3 = 0x23, + PORTC_3_MUL0 = PORTC_3 | MUL0, + PORTC_4 = 0x24, + PORTC_4_MUL0 = PORTC_4 | MUL0, + PORTC_5 = 0x25, + PORTC_5_MUL0 = PORTC_5 | MUL0, + PORTC_6 = 0x26, + PORTC_6_MUL0 = PORTC_6 | MUL0, + PORTC_7 = 0x27, + PORTC_7_MUL0 = PORTC_7 | MUL0, + PORTC_8 = 0x28, + PORTC_8_MUL0 = PORTC_8 | MUL0, + PORTC_9 = 0x29, + PORTC_9_MUL0 = PORTC_9 | MUL0, + PORTC_10 = 0x2A, + PORTC_10_MUL0 = PORTC_10 | MUL0, + PORTC_11 = 0x2B, + PORTC_11_MUL0 = PORTC_11 | MUL0, + PORTC_12 = 0x2C, + PORTC_13 = 0x2D, + PORTC_14 = 0x2E, + PORTC_15 = 0x2F, + + PORTD_0 = 0x30, + PORTD_1 = 0x31, + PORTD_2 = 0x32, + PORTD_3 = 0x33, + PORTD_4 = 0x34, + PORTD_5 = 0x35, + PORTD_6 = 0x36, + PORTD_7 = 0x37, + PORTD_8 = 0x38, + PORTD_9 = 0x39, + PORTD_10 = 0x3A, + PORTD_11 = 0x3B, + PORTD_12 = 0x3C, + PORTD_13 = 0x3D, + PORTD_14 = 0x3E, + PORTD_15 = 0x3F, + + PORTE_0 = 0x40, + PORTE_1 = 0x41, + PORTE_2 = 0x42, + PORTE_3 = 0x43, + PORTE_4 = 0x44, + PORTE_5 = 0x45, + PORTE_6 = 0x46, + PORTE_7 = 0x47, + PORTE_8 = 0x48, + PORTE_9 = 0x49, + PORTE_10 = 0x4A, + PORTE_11 = 0x4B, + PORTE_12 = 0x4C, + PORTE_13 = 0x4D, + PORTE_14 = 0x4E, + PORTE_15 = 0x4F, + + /* ADC internal channels */ + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + + + /* Arduino connector namings */ + A0 = PORTC_0, + A1 = PORTC_1, + A2 = PORTC_2, + A3 = PORTC_3, + A4 = PORTA_0, + A5 = PORTB_1, + D0 = PORTA_3, + D1 = PORTA_2, + D2 = PORTE_4, + D3 = PORTD_12, + D4 = PORTB_3, + D5 = PORTC_7, + D6 = PORTB_0, + D7 = PORTB_4, + D8 = PORTD_11, + D9 = PORTE_5, + D10 = PORTA_8, + D11 = PORTB_15, + D12 = PORTB_14, + D13 = PORTB_13, + D14 = PORTB_9, + D15 = PORTB_8, + + LED1 = PORTE_0, + LED2 = PORTE_1, + LED3 = PORTE_6, + + KEY1 = PORTE_2, + KEY2 = PORTE_7, + + BUTTON1 = KEY1, + BUTTON2 = KEY2, + + SERIAL_TX = PORTC_10, + SERIAL_RX = PORTC_11, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + USBFS_VBUS = PORTA_9, + USBFS_DM = PORTA_11, + USBFS_DP = PORTA_12, + + RMII_TX_EN = PORTB_11, + RMII_TXD0 = PORTB_12, + RMII_TXD1 = PORTB_13, + RMII_RXD0 = PORTC_4, + RMII_RXD1 = PORTC_5, + RMII_CRS_DV = PORTA_7, + RMII_MDC = PORTC_1, + RMII_MDIO = PORTA_2, + RMII_INT = PORTB_0, + RMII_REF_CLK = PORTA_1, + + NC = (int)0xFFFFFFFF +} PinName; + +/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE) + BIT[3:0] pin number */ +#define GD_PORT_GET(X) (((uint32_t)(X) >> 4) & 0xF) +#define GD_PIN_GET(X) (((uint32_t)(X) & 0xF)) + +/* Get mode,speed,remap function,channel of GPIO pin */ +#define GD_PIN_MODE_GET(X) (X & 0x07) +#define GD_PIN_SPEED_GET(X) ((X >> 9) & 0x03) +#define GD_PIN_REMAP_GET(X) ((X >> 3) & 0x3F) +#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x1F) + +/* Defines GPIO pin direction */ +typedef enum { + PIN_INPUT = 0, + PIN_OUTPUT +} PinDirection; + +/* Defines mode types of GPIO pin */ +typedef enum { + MODE_AIN = 0, + MODE_IN_FLOATING, + MODE_IPD, + MODE_IPU, + MODE_OUT_OD, + MODE_OUT_PP, + MODE_AF_OD, + MODE_AF_PP, + PullDefault = MODE_IN_FLOATING, + PullUp = MODE_IPU, + PullDown = MODE_IPD, + PullNone = 11 +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct new file mode 100644 index 0000000000..35cb12437b --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct @@ -0,0 +1,27 @@ +#! armcc -E +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ***** + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K) + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150) + RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.S b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.S new file mode 100644 index 0000000000..b389e1775c --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.S @@ -0,0 +1,362 @@ +;/*! +; \file startup_gd32f30x_cl.S +; \brief start up file +; +; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed) +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20010000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +EXMC_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler + + B . + ENDP + + ALIGN + + END diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct new file mode 100644 index 0000000000..35cb12437b --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct @@ -0,0 +1,27 @@ +#! armcc -E +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ***** + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K) + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150) + RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.S b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.S new file mode 100644 index 0000000000..6a900b690b --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.S @@ -0,0 +1,359 @@ +;/*! +; \file startup_gd32f30x_cl.S +; \brief start up file +; +; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed) +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20018000 + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA0_Channel0_IRQHandler [WEAK] + EXPORT DMA0_Channel1_IRQHandler [WEAK] + EXPORT DMA0_Channel2_IRQHandler [WEAK] + EXPORT DMA0_Channel3_IRQHandler [WEAK] + EXPORT DMA0_Channel4_IRQHandler [WEAK] + EXPORT DMA0_Channel5_IRQHandler [WEAK] + EXPORT DMA0_Channel6_IRQHandler [WEAK] + EXPORT ADC0_1_IRQHandler [WEAK] + EXPORT CAN0_TX_IRQHandler [WEAK] + EXPORT CAN0_RX0_IRQHandler [WEAK] + EXPORT CAN0_RX1_IRQHandler [WEAK] + EXPORT CAN0_EWMC_IRQHandler [WEAK] + EXPORT EXTI5_9_IRQHandler [WEAK] + EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] + EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] + EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] + EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] + EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] + EXPORT TIMER7_Channel_IRQHandler [WEAK] + EXPORT EXMC_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT ENET_WKUP_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_EWMC_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA0_Channel0_IRQHandler +DMA0_Channel1_IRQHandler +DMA0_Channel2_IRQHandler +DMA0_Channel3_IRQHandler +DMA0_Channel4_IRQHandler +DMA0_Channel5_IRQHandler +DMA0_Channel6_IRQHandler +ADC0_1_IRQHandler +CAN0_TX_IRQHandler +CAN0_RX0_IRQHandler +CAN0_RX1_IRQHandler +CAN0_EWMC_IRQHandler +EXTI5_9_IRQHandler +TIMER0_BRK_TIMER8_IRQHandler +TIMER0_UP_TIMER9_IRQHandler +TIMER0_TRG_CMT_TIMER10_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +I2C0_EV_IRQHandler +I2C0_ER_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI10_15_IRQHandler +RTC_Alarm_IRQHandler +USBFS_WKUP_IRQHandler +TIMER7_BRK_TIMER11_IRQHandler +TIMER7_UP_TIMER12_IRQHandler +TIMER7_TRG_CMT_TIMER13_IRQHandler +TIMER7_Channel_IRQHandler +EXMC_IRQHandler +TIMER4_IRQHandler +SPI2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +ENET_IRQHandler +ENET_WKUP_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_EWMC_IRQHandler +USBFS_IRQHandler + + B . + ENDP + + ALIGN + + END diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld new file mode 100644 index 0000000000..3f72df037a --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld @@ -0,0 +1,123 @@ +/* specify memory regions */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 96K - 0x150 +} + +/* define output sections */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* initializes stack on the end of block */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.S b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.S new file mode 100644 index 0000000000..1cbccb7f7f --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.S @@ -0,0 +1,413 @@ +;/*! +; \file startup_gd32f30x_cl.S +; \brief start up file +; +; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed) +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +.syntax unified +.cpu cortex-m4 +.fpu softvfp +.thumb + +.global VecTab +.global Default_Handler + +/* start address of the initialization .data */ +.word _sidata +/* start address of the .data section */ +.word _sdata +/* end address of the .data section */ +.word _edata + +/* reset Handler */ + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* copy the data segment into RAM */ + movs r1, #0 + b DataInit + +CopyData: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +DataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyData + +/* system clock intitialization*/ + bl SystemInit +/* static constructors */ +// bl __libc_init_array +/* jump to application's entry point */ +// bl main + bl _start +/* infinite loop */ + b . + + +.size Reset_Handler, .-Reset_Handler + + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +/* infinite loop */ + b . + .size Default_Handler, .-Default_Handler + + .section .isr_vector,"a",%progbits + .type VecTab, %object + .size VecTab, .-VecTab + + +VecTab: + + .word _estack /* Top of Stack */ + .word Reset_Handler /* 1,Reset Handler */ + .word NMI_Handler /* 2,NMI Handler */ + .word HardFault_Handler /* 3,Hard Fault Handler */ + .word MemManage_Handler /* 4,MPU Fault Handler */ + .word BusFault_Handler /* 5,Bus Fault Handler */ + .word UsageFault_Handler /* 6,Usage Fault Handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler /* 11,SVCall Handler */ + .word DebugMon_Handler /* 12,Debug Monitor Handler */ + .word 0 /* Reserved */ + .word PendSV_Handler /* 14,PendSV Handler */ + .word SysTick_Handler /* 15,SysTick Handler */ + /* External Interrupts */ + .word WWDGT_IRQHandler /* 16,Window Watchdog Timer */ + .word LVD_IRQHandler /* 17,LVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* 18,Tamper through EXTI Line detect */ + .word RTC_IRQHandler /* 19,RTC through EXTI Line */ + .word FMC_IRQHandler /* 20,FMC */ + .word RCU_CTC_IRQHandler /* 21,RCU and CTC */ + .word EXTI0_IRQHandler /* 22,EXTI Line 0 */ + .word EXTI1_IRQHandler /* 23,EXTI Line 1 */ + .word EXTI2_IRQHandler /* 24,EXTI Line 2 */ + .word EXTI3_IRQHandler /* 25,EXTI Line 3 */ + .word EXTI4_IRQHandler /* 26,EXTI Line 4 */ + .word DMA0_Channel0_IRQHandler /* 27,DMA0 Channel 0 */ + .word DMA0_Channel1_IRQHandler /* 28,DMA0 Channel 1 */ + .word DMA0_Channel2_IRQHandler /* 29,DMA0 Channel 2 */ + .word DMA0_Channel3_IRQHandler /* 30,DMA0 Channel 3 */ + .word DMA0_Channel4_IRQHandler /* 31,DMA0 Channel 4 */ + .word DMA0_Channel5_IRQHandler /* 32,DMA0 Channel 5 */ + .word DMA0_Channel6_IRQHandler /* 33,DMA0 Channel 6 */ + .word ADC0_1_IRQHandler /* 34,ADC0 and ADC1 */ + .word CAN0_TX_IRQHandler /* 35,CAN0 TX */ + .word CAN0_RX0_IRQHandler /* 36,CAN0 RX0 */ + .word CAN0_RX1_IRQHandler /* 37,CAN0 RX1 */ + .word CAN0_EWMC_IRQHandler /* 38,CAN0 EWMC */ + .word EXTI5_9_IRQHandler /* 39,EXTI5 to EXTI9 */ + .word TIMER0_BRK_TIMER8_IRQHandler /* 40,TIMER0 Break and TIMER8 */ + .word TIMER0_UP_TIMER9_IRQHandler /* 41,TIMER0 Update and TIMER9 */ + .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* 42,TIMER0 Trigger and Commutation and TIMER10 */ + .word TIMER0_Channel_IRQHandler /* 43,TIMER0 Channel Capture Compare */ + .word TIMER1_IRQHandler /* 44,TIMER4 */ + .word TIMER2_IRQHandler /* 45,TIMER2 */ + .word TIMER3_IRQHandler /* 46,TIMER3 */ + .word I2C0_EV_IRQHandler /* 47,I2C0 Event */ + .word I2C0_ER_IRQHandler /* 48,I2C0 Error */ + .word I2C1_EV_IRQHandler /* 49,I2C1 Event */ + .word I2C1_ER_IRQHandler /* 50,I2C1 Error */ + .word SPI0_IRQHandler /* 51,SPI0 */ + .word SPI1_IRQHandler /* 52,SPI1 */ + .word USART0_IRQHandler /* 53,USART0 */ + .word USART1_IRQHandler /* 54,USART1 */ + .word USART2_IRQHandler /* 55,USART2 */ + .word EXTI10_15_IRQHandler /* 56,EXTI10 to EXTI15 */ + .word RTC_Alarm_IRQHandler /* 57,RTC Alarm */ + .word USBFS_WKUP_IRQHandler /* 58,USBFS Wakeup */ + .word TIMER7_BRK_TIMER11_IRQHandler /* 59,TIMER7 Break and TIMER11 */ + .word TIMER7_UP_TIMER12_IRQHandler /* 60:TIMER7 Update and TIMER12 */ + .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* 61:TIMER7 Trigger and Commutation and TIMER13 */ + .word TIMER7_Channel_IRQHandler /* 62,TIMER7 Capture Compare */ + .word 0 /* Reserved */ + .word EXMC_IRQHandler /* 64,EXMC */ + .word 0 /* Reserved */ + .word TIMER4_IRQHandler /* 66,TIMER4 */ + .word SPI2_IRQHandler /* 67,SPI2 */ + .word UART3_IRQHandler /* 68,UART3 */ + .word UART4_IRQHandler /* 69,UART4 */ + .word TIMER5_IRQHandler /* 70,TIMER5 */ + .word TIMER6_IRQHandler /* 71,TIMER6 */ + .word DMA1_Channel0_IRQHandler /* 72,DMA1 Channel0 */ + .word DMA1_Channel1_IRQHandler /* 73,DMA1 Channel1 */ + .word DMA1_Channel2_IRQHandler /* 74,DMA1 Channel2 */ + .word DMA1_Channel3_IRQHandler /* 75,DMA1 Channel3 */ + .word DMA1_Channel4_IRQHandler /* 76,DMA1 Channel4 */ + .word ENET_IRQHandler /* 77,Ethernet */ + .word ENET_WKUP_IRQHandler /* 78,Ethernet Wakeup through EXTI line */ + .word CAN1_TX_IRQHandler /* 79,CAN1 TX */ + .word CAN1_RX0_IRQHandler /* 80,CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* 81,CAN1 RX1 */ + .word CAN1_EWMC_IRQHandler /* 82,CAN1 EWMC */ + .word USBFS_IRQHandler /* 83,USBFS */ + +/* dummy Exception Handlers */ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDGT_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak LVD_IRQHandler + .thumb_set LVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak RCU_CTC_IRQHandler + .thumb_set RCU_CTC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA0_Channel0_IRQHandler + .thumb_set DMA0_Channel0_IRQHandler,Default_Handler + + .weak DMA0_Channel1_IRQHandler + .thumb_set DMA0_Channel1_IRQHandler,Default_Handler + + .weak DMA0_Channel2_IRQHandler + .thumb_set DMA0_Channel2_IRQHandler,Default_Handler + + .weak DMA0_Channel3_IRQHandler + .thumb_set DMA0_Channel3_IRQHandler,Default_Handler + + .weak DMA0_Channel4_IRQHandler + .thumb_set DMA0_Channel4_IRQHandler,Default_Handler + + .weak DMA0_Channel5_IRQHandler + .thumb_set DMA0_Channel5_IRQHandler,Default_Handler + + .weak DMA0_Channel6_IRQHandler + .thumb_set DMA0_Channel6_IRQHandler,Default_Handler + + .weak ADC0_1_IRQHandler + .thumb_set ADC0_1_IRQHandler,Default_Handler + + .weak CAN0_TX_IRQHandler + .thumb_set CAN0_TX_IRQHandler,Default_Handler + + .weak CAN0_RX0_IRQHandler + .thumb_set CAN0_RX0_IRQHandler,Default_Handler + + .weak CAN0_RX1_IRQHandler + .thumb_set CAN0_RX1_IRQHandler,Default_Handler + + .weak CAN0_EWMC_IRQHandler + .thumb_set CAN0_EWMC_IRQHandler,Default_Handler + + .weak EXTI5_9_IRQHandler + .thumb_set EXTI5_9_IRQHandler,Default_Handler + + .weak TIMER0_BRK_TIMER8_IRQHandler + .thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler + + .weak TIMER0_UP_TIMER9_IRQHandler + .thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler + + .weak TIMER0_TRG_CMT_TIMER10_IRQHandler + .thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler + + .weak TIMER0_Channel_IRQHandler + .thumb_set TIMER0_Channel_IRQHandler,Default_Handler + + .weak TIMER1_IRQHandler + .thumb_set TIMER1_IRQHandler,Default_Handler + + .weak TIMER2_IRQHandler + .thumb_set TIMER2_IRQHandler,Default_Handler + + .weak TIMER3_IRQHandler + .thumb_set TIMER3_IRQHandler,Default_Handler + + .weak I2C0_EV_IRQHandler + .thumb_set I2C0_EV_IRQHandler,Default_Handler + + .weak I2C0_ER_IRQHandler + .thumb_set I2C0_ER_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI0_IRQHandler + .thumb_set SPI0_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART0_IRQHandler + .thumb_set USART0_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI10_15_IRQHandler + .thumb_set EXTI10_15_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBFS_WKUP_IRQHandler + .thumb_set USBFS_WKUP_IRQHandler,Default_Handler + + .weak TIMER7_BRK_TIMER11_IRQHandler + .thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler + + .weak TIMER7_UP_TIMER12_IRQHandler + .thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler + + .weak TIMER7_TRG_CMT_TIMER13_IRQHandler + .thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler + + .weak TIMER7_Channel_IRQHandler + .thumb_set TIMER7_Channel_IRQHandler,Default_Handler + + .weak EXMC_IRQHandler + .thumb_set EXMC_IRQHandler,Default_Handler + + .weak TIMER4_IRQHandler + .thumb_set TIMER4_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak TIMER5_IRQHandler + .thumb_set TIMER5_IRQHandler,Default_Handler + + .weak TIMER6_IRQHandler + .thumb_set TIMER6_IRQHandler,Default_Handler + + .weak DMA1_Channel0_IRQHandler + .thumb_set DMA1_Channel0_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak ENET_IRQHandler + .thumb_set ENET_IRQHandler,Default_Handler + + .weak ENET_WKUP_IRQHandler + .thumb_set ENET_WKUP_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_EWMC_IRQHandler + .thumb_set CAN1_EWMC_IRQHandler,Default_Handler + + .weak USBFS_IRQHandler + .thumb_set USBFS_IRQHandler,Default_Handler diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf new file mode 100644 index 0000000000..de026cc1be --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ + +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; } +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000; +define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000150; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x3000; +define symbol __ICFEDIT_size_heap__ = 0x6000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block HEAP, block CSTACK }; \ No newline at end of file diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.S b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.S new file mode 100644 index 0000000000..a5e4b5ac64 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.S @@ -0,0 +1,526 @@ +;/*! +; \file startup_gd32f30x_cl.S +; \brief start up file +; +; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed) +;*/ +; +;/* +; Copyright (c) 2018, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler + DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler + DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect + DCD RTC_IRQHandler ; 19:RTC through EXTI Line + DCD FMC_IRQHandler ; 20:FMC + DCD RCU_CTC_IRQHandler ; 21:RCU and CTC + DCD EXTI0_IRQHandler ; 22:EXTI Line 0 + DCD EXTI1_IRQHandler ; 23:EXTI Line 1 + DCD EXTI2_IRQHandler ; 24:EXTI Line 2 + DCD EXTI3_IRQHandler ; 25:EXTI Line 3 + DCD EXTI4_IRQHandler ; 26:EXTI Line 4 + DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 + DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 + DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 + DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 + DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 + DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 + DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 + DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 + DCD CAN0_TX_IRQHandler ; 35:CAN0 TX + DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 + DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 + DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC + DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 + DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 + DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 + DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 + DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 44:TIMER1 + DCD TIMER2_IRQHandler ; 45:TIMER2 + DCD TIMER3_IRQHandler ; 46:TIMER3 + DCD I2C0_EV_IRQHandler ; 47:I2C0 Event + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD I2C1_EV_IRQHandler ; 49:I2C1 Event + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD SPI0_IRQHandler ; 51:SPI0 + DCD SPI1_IRQHandler ; 52:SPI1 + DCD USART0_IRQHandler ; 53:USART0 + DCD USART1_IRQHandler ; 54:USART1 + DCD USART2_IRQHandler ; 55:USART2 + DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 + DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 + DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 + DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 + DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare + DCD 0 ; 63:Reserved + DCD EXMC_IRQHandler ; 64:EXMC + DCD 0 ; 65:Reserved + DCD TIMER4_IRQHandler ; 66:TIMER4 + DCD SPI2_IRQHandler ; 67:SPI2 + DCD UART3_IRQHandler ; 68:UART3 + DCD UART4_IRQHandler ; 69:UART4 + DCD TIMER5_IRQHandler ; 70:TIMER5 + DCD TIMER6_IRQHandler ; 71:TIMER6 + DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 + DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 + DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 + DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 + DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 + DCD ENET_IRQHandler ; 77:Ethernet + DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line + DCD CAN1_TX_IRQHandler ; 79:CAN1 TX + DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 + DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC + DCD USBFS_IRQHandler ; 83:USBFS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK TAMPER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMPER_IRQHandler + B TAMPER_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_CTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_CTC_IRQHandler + B RCU_CTC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA0_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel0_IRQHandler + B DMA0_Channel0_IRQHandler + + PUBWEAK DMA0_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel1_IRQHandler + B DMA0_Channel1_IRQHandler + + PUBWEAK DMA0_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel2_IRQHandler + B DMA0_Channel2_IRQHandler + + PUBWEAK DMA0_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel3_IRQHandler + B DMA0_Channel3_IRQHandler + + PUBWEAK DMA0_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel4_IRQHandler + B DMA0_Channel4_IRQHandler + + PUBWEAK DMA0_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel5_IRQHandler + B DMA0_Channel5_IRQHandler + + PUBWEAK DMA0_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA0_Channel6_IRQHandler + B DMA0_Channel6_IRQHandler + + PUBWEAK ADC0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_1_IRQHandler + B ADC0_1_IRQHandler + + PUBWEAK CAN0_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_IRQHandler + B CAN0_TX_IRQHandler + + PUBWEAK CAN0_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_IRQHandler + B CAN0_RX0_IRQHandler + + PUBWEAK CAN0_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_IRQHandler + B CAN0_RX1_IRQHandler + + PUBWEAK CAN0_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EWMC_IRQHandler + B CAN0_EWMC_IRQHandler + + PUBWEAK EXTI5_9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_9_IRQHandler + B EXTI5_9_IRQHandler + + PUBWEAK TIMER0_BRK_TIMER8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_TIMER8_IRQHandler + B TIMER0_BRK_TIMER8_IRQHandler + + PUBWEAK TIMER0_UP_TIMER9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_UP_TIMER9_IRQHandler + B TIMER0_UP_TIMER9_IRQHandler + + PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_TRG_CMT_TIMER10_IRQHandler + B TIMER0_TRG_CMT_TIMER10_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI10_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_15_IRQHandler + B EXTI10_15_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK TIMER7_BRK_TIMER11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_BRK_TIMER11_IRQHandler + B TIMER7_BRK_TIMER11_IRQHandler + + PUBWEAK TIMER7_UP_TIMER12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_UP_TIMER12_IRQHandler + B TIMER7_UP_TIMER12_IRQHandler + + PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_TRG_CMT_TIMER13_IRQHandler + B TIMER7_TRG_CMT_TIMER13_IRQHandler + + PUBWEAK TIMER7_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER7_Channel_IRQHandler + B TIMER7_Channel_IRQHandler + + PUBWEAK EXMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXMC_IRQHandler + B EXMC_IRQHandler + + PUBWEAK TIMER4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER4_IRQHandler + B TIMER4_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER6_IRQHandler + B TIMER6_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK ENET_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_IRQHandler + B ENET_IRQHandler + + PUBWEAK ENET_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ENET_WKUP_IRQHandler + B ENET_WKUP_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_EWMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_EWMC_IRQHandler + B CAN1_EWMC_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + END \ No newline at end of file diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis.h new file mode 100644 index 0000000000..c7db9cbf17 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + + Copyright (c) 2018, GigaDevice Semiconductor Inc. All rights reserved. + + SPDX-License-Identifier: BSD-3-Clause + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "gd32f30x.h" +#include "cmsis_nvic.h" + +#endif /* MBED_CMSIS_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis_nvic.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis_nvic.h new file mode 100644 index 0000000000..3cea459539 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis_nvic.h @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 68) /* ARM CORE:16 Vectors; MCU Peripherals:68 Vectors */ +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 + + +#endif /* MBED_CMSIS_NVIC_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x.h new file mode 100644 index 0000000000..6e2ec76ae2 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x.h @@ -0,0 +1,386 @@ +/*! + \file gd32f30x.h + \brief general definitions for GD32F30x + + \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_H +#define GD32F30X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* define GD32F30x */ +#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL) + /* #define GD32F30X_HD */ + /* #define GD32F30X_XD */ + /* #define GD32F30X_CL */ +#endif /* define GD32F30x */ + +#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL) + #error "Please select the target GD32F30x device in gd32f30x.h file" +#endif /* undefine GD32F30x tip */ + + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined HXTAL_VALUE +#ifdef GD32F30X_CL +#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ +#else +#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ +#endif /* HXTAL_VALUE */ +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */ +#if !defined (IRC48M_VALUE) +#define IRC48M_VALUE ((uint32_t)48000000) +#endif /* internal 48MHz RC oscillator value */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* GD32F30x firmware library version number V1.0 */ +#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F30x_STDPERIPH_VERSION_RC)) + +/* configuration of the Cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */ +#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +/* define interrupt number */ +typedef enum IRQn +{ + /* Cortex-M4 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ + RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ + FMC_IRQn = 4, /*!< FMC interrupt */ + RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ + ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ +#ifdef GD32F30X_HD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ + TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ + TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ + TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ + TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ +#endif /* GD32F30X_HD */ + +#ifdef GD32F30X_XD + USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */ + ADC2_IRQn = 47, /*!< ADC2 global interrupt */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + SDIO_IRQn = 49, /*!< SDIO global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ +#endif /* GD32F30X_XD */ + +#ifdef GD32F30X_CL + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */ + TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + SPI0_IRQn = 35, /*!< SPI0 interrupt */ + SPI1_IRQn = 36, /*!< SPI1 interrupt */ + USART0_IRQn = 37, /*!< USART0 interrupt */ + USART1_IRQn = 38, /*!< USART1 interrupt */ + USART2_IRQn = 39, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ + RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */ + EXMC_IRQn = 48, /*!< EXMC global interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 51, /*!< SPI2 global interrupt */ + UART3_IRQn = 52, /*!< UART3 global interrupt */ + UART4_IRQn = 53, /*!< UART4 global interrupt */ + TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ + ENET_IRQn = 61, /*!< ENET global interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS global interrupt */ +#endif /* GD32F30X_CL */ + +} IRQn_Type; + +/* includes */ +#include "core_cm4.h" +#include "system_gd32f30x.h" +#include + +#define GD_MBED_USED + +#ifdef GD_MBED_USED +typedef enum +{ + GD_OK = 0x00U, + GD_ERROR = 0x01U, + GD_BUSY = 0x02U, + GD_TIMEOUT = 0x03U +}gd_status_enum; + +typedef enum +{ + OP_STATE_RESET = 0x00U, + OP_STATE_READY = 0x01U, + OP_STATE_BUSY = 0x02U, + OP_STATE_TIMEOUT = 0x03U, + OP_STATE_ERROR = 0x04U, + OP_STATE_ABORT = 0x05U, + OP_STATE_LISTEN = 0x06U, + + OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */ + OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */ + + OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */ + OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */ + + OP_STATE_BUTT +}operation_state_enum; +#endif + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ +#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ +#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ + +/* advanced peripheral bus 2 memory map */ +#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + +/* advanced high performance bus 1 memory map */ +#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ +#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +/* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32f30x_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x_libopt.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x_libopt.h new file mode 100644 index 0000000000..e9ef7b4b0e --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x_libopt.h @@ -0,0 +1,65 @@ +/*! + \file gd32f30x_libopt.h + \brief library optional for gd32f30x + + \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed) +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F30X_LIBOPT_H +#define GD32F30X_LIBOPT_H + +#include "gd32f30x_rcu.h" +#include "gd32f30x_adc.h" +#include "gd32f30x_can.h" +#include "gd32f30x_crc.h" +#include "gd32f30x_ctc.h" +#include "gd32f30x_dac.h" +#include "gd32f30x_dbg.h" +#include "gd32f30x_dma.h" +#include "gd32f30x_exti.h" +#include "gd32f30x_fmc.h" +#include "gd32f30x_fwdgt.h" +#include "gd32f30x_gpio.h" +#include "gd32f30x_i2c.h" +#include "gd32f30x_pmu.h" +#include "gd32f30x_bkp.h" +#include "gd32f30x_rtc.h" +#include "gd32f30x_sdio.h" +#include "gd32f30x_spi.h" +#include "gd32f30x_timer.h" +#include "gd32f30x_usart.h" +#include "gd32f30x_wwdgt.h" +#include "gd32f30x_misc.h" +#include "gd32f30x_enet.h" +#include "gd32f30x_exmc.h" + +#endif /* GD32F30X_LIBOPT_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/hal_tick.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/hal_tick.h new file mode 100644 index 0000000000..e6cdebe6b4 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/hal_tick.h @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "gd32f30x.h" +#include "cmsis_nvic.h" + +#define TICKER_TIMER TIMER2 +#define TICKER_TIMER_IRQ TIMER2_IRQn +#define TICKER_TIMER_RCU_CLOCK_ENABLE rcu_periph_clock_enable(RCU_TIMER2); +#define TICKER_TIMER_DEBUG_STOP dbg_periph_enable(DBG_TIMER2_HOLD); + +#define TICKER_TIMER_RESET_ENABLE rcu_periph_reset_enable(RCU_TIMER2RST) +#define TICKER_TIMER_RESET_DISABLE rcu_periph_reset_disable(RCU_TIMER2RST) + +/* 16 for 16-bit timer, 32 for 32-bit timer */ +#define TICKER_TIMER_WIDTH_BIT 16 + +/* 0 for CK_APB1, 1 for CK_APB2 */ +#define TICKER_TIMER_CKAPB 1 + +#ifdef __cplusplus +} +#endif + +#endif /* __HAL_TICK_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.c new file mode 100644 index 0000000000..6455a51655 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.c @@ -0,0 +1,987 @@ +/*! + \file system_gd32f30x.c + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + GD32F30x Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f30x.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +/* select a system clock by uncommenting the following line */ +/* use IRC8M */ +//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M) +//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) +//#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000) + +/* use HXTAL(XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */ +//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) +//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) +#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000) + +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_IRC8M +uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M; +static void system_clock_8m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; +static void system_clock_48m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; +static void system_clock_72m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; +static void system_clock_108m_irc8m(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M; +static void system_clock_120m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; +static void system_clock_hxtal(void); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; +static void system_clock_48m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); +#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL; +static void system_clock_120m_hxtal(void); +#endif /* __SYSTEM_CLOCK_IRC8M */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit (void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* reset the RCU clock configuration to the default reset state */ + /* Set IRC8MEN bit */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* Reset CFG0 and CFG1 registers */ + RCU_CFG0 = 0x00000000U; + RCU_CFG1 = 0x00000000U; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* reset HXTALEN, CKMEN and PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x009f0000U; +#elif defined(GD32F30X_CL) + /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ + RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); + /* disable all interrupts */ + RCU_INT = 0x00ff0000U; +#endif + + /* reset HXTALBPS bit */ + RCU_CTL &= ~(RCU_CTL_HXTALBPS); + + /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + system_clock_config(); +} +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_IRC8M + system_clock_8m_irc8m(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) + system_clock_48m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) + system_clock_108m_irc8m(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) + system_clock_120m_irc8m(); + +#elif defined (__SYSTEM_CLOCK_HXTAL) + system_clock_hxtal(); +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) + system_clock_48m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); +#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) + system_clock_120m_hxtal(); +#endif /* __SYSTEM_CLOCK_IRC8M */ +} + +#ifdef __SYSTEM_CLOCK_IRC8M +/*! + \brief configure the system clock to 8M by IRC8M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select IRC8M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; + + /* wait until IRC8M is selected as system clock */ + while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) +/*! + \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + } + while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL12; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL18; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL27; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) +/*! + \brief configure the system clock to 120M by PLL which selects IRC8M as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_irc8m(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable IRC8M */ + RCU_CTL |= RCU_CTL_IRC8MEN; + + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); + }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + while(1){ + } + } + + /* LDO output voltage high mode */ + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* IRC8M is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_HXTAL) +/*! + \brief configure the system clock to HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) +/*! + \brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_48m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL12; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL18; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL27; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} + +#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + } +} +#endif /* __SYSTEM_CLOCK_IRC8M */ + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate (void) +{ + uint32_t sws; + uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src; +#ifdef GD32F30X_CL + uint32_t predv0, predv1, pll1mf; +#endif /* GD32F30X_CL */ + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws){ + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ + pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); + + if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) { + /* PLL clock source is HXTAL or IRC48M */ + pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); + + if(RCU_PLLPRESRC_HXTAL == pllpresel){ + /* PLL clock source is HXTAL */ + ck_src = HXTAL_VALUE; + }else{ + /* PLL clock source is IRC48 */ + ck_src = IRC48M_VALUE; + } + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); + /* PREDV0 input source clock divided by 2 */ + if(RCU_CFG0_PREDV0 == predv0sel){ + ck_src = HXTAL_VALUE/2U; + } +#elif defined(GD32F30X_CL) + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); + /* source clock use PLL1 */ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; + pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; + if(17U == pll1mf){ + pll1mf = 20U; + } + ck_src = (ck_src/predv1)*pll1mf; + } + predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; + ck_src /= predv0; +#endif /* GD32F30X_HD and GD32F30X_XD */ + }else{ + /* PLL clock source is IRC8M/2 */ + ck_src = IRC8M_VALUE/2U; + } + + /* PLL multiplication factor */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + pllmf |= 0x10U; + } + if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){ + pllmf |= 0x20U; + } + + if( pllmf >= 15U){ + pllmf += 1U; + }else{ + pllmf += 2U; + } + if(pllmf > 61U){ + pllmf = 63U; + } + SystemCoreClock = ck_src*pllmf; + #ifdef GD32F30X_CL + if(15U == pllmf){ + SystemCoreClock = ck_src*6U + ck_src/2U; + } + #endif /* GD32F30X_CL */ + + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.h new file mode 100644 index 0000000000..97400790de --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.h @@ -0,0 +1,58 @@ +/*! + \file system_gd32f30x.h + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + GD32F30x Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F30X_H +#define SYSTEM_GD32F30X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit (void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F30X_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/analogin_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/analogin_api.c new file mode 100644 index 0000000000..a23206f712 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/analogin_api.c @@ -0,0 +1,148 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "mbed_error.h" + +#define DEV_ADC_ACCURACY_12BIT 0xFFF +#define DEV_ADC_PRECISION_12TO16(val) ((val << 4)| ((val >> 8) & (uint16_t)0x000F)) + +/** Initialize the analogin peripheral + * + * Configures the pin used by analogin. + * @param obj The analogin object to initialize + * @param pin The analogin pin name + */ +void analogin_init(analogin_t *obj, PinName pin) +{ + uint32_t periph; + + MBED_ASSERT(obj); + + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + uint32_t function = pinmap_function(pin, PinMap_ADC); + MBED_ASSERT(function != (uint32_t)NC); + + obj->channel = GD_PIN_CHANNEL_GET(function); + MBED_ASSERT(obj->channel <= ADC_CHANNEL_17); + + obj->pin = pin; + + if ((ADC_CHANNEL_17 == obj->channel) || (ADC_CHANNEL_16 == obj->channel)) { + /* no need to config port */ + } else { + pinmap_pinout(pin, PinMap_ADC); + } + + + periph = obj->adc; + + /* when pin >= ADC_TEMP, it indicates that the channel has no external pins */ + if (pin < ADC_TEMP) { + pinmap_pinout(pin, PinMap_ADC); + } + + /* ADC clock enable */ + switch (periph) { + case ADC0: + rcu_periph_clock_enable(RCU_ADC0); + break; + + case ADC1: + rcu_periph_clock_enable(RCU_ADC1); + break; +#ifndef GD32F30X_CL + case ADC2: + rcu_periph_clock_enable(RCU_ADC2); + break; +#endif /* GD32F30X_CL */ + } + + /* ADC clock cannot be greater than 42M */ + rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV6); + + /* ADC configuration */ + adc_data_alignment_config(obj->adc, ADC_DATAALIGN_RIGHT); + adc_channel_length_config(obj->adc, ADC_REGULAR_CHANNEL, 1); + adc_special_function_config(obj->adc, ADC_SCAN_MODE, DISABLE); + adc_special_function_config(obj->adc, ADC_CONTINUOUS_MODE, DISABLE); + adc_external_trigger_config(obj->adc, ADC_REGULAR_CHANNEL, ENABLE); + adc_external_trigger_source_config(obj->adc, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE); + + /* ADC enable */ + adc_enable(obj->adc); + adc_calibration_enable(obj->adc); +} + +/** Read the value from analogin pin, represented as an unsigned 16bit value + * + * @param obj The analogin object + * @return An unsigned 16bit value representing the current input voltage + */ +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t reval; + + adc_regular_channel_config(obj->adc, 0, obj->channel, ADC_SAMPLETIME_7POINT5); + + adc_flag_clear(obj->adc, ADC_FLAG_EOC); + /* start Conversion */ + adc_software_trigger_enable(obj->adc, ADC_REGULAR_CHANNEL); + + while (SET != adc_flag_get(obj->adc, ADC_FLAG_EOC)) { + } + /* ADC actual accuracy is 12 bits */ + reval = adc_regular_data_read(obj->adc); + + reval = DEV_ADC_PRECISION_12TO16(reval); + + return reval; +} + +/** Read the input voltage, represented as a float in the range [0.0, 1.0] + * + * @param obj The analogin object + * @return A floating value representing the current input voltage + */ +float analogin_read(analogin_t *obj) +{ + uint16_t reval; + + adc_regular_channel_config(obj->adc, 0, obj->channel, ADC_SAMPLETIME_7POINT5); + + adc_flag_clear(obj->adc, ADC_FLAG_EOC); + /* start Conversion */ + adc_software_trigger_enable(obj->adc, ADC_REGULAR_CHANNEL); + /* wait for conversion to complete */ + while (SET != adc_flag_get(obj->adc, ADC_FLAG_EOC)) { + } + /* ADC actual accuracy is 12 bits */ + reval = adc_regular_data_read(obj->adc); + + return (float)reval * (1.0f / (float)DEV_ADC_ACCURACY_12BIT); +} + +#endif /* DEVICE_ANALOGIN */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/analogout_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/analogout_api.c new file mode 100644 index 0000000000..e37eb6e232 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/analogout_api.c @@ -0,0 +1,160 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogout_api.h" +#include "mbed_assert.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +#define DEV_DAC_ACCURACY_12BIT (0xFFF) // 12 bits +#define DEV_DAC_BITS (12) + +/** Initialize the analogout peripheral + * + * Configures the pin used by analogout. + * @param obj The analogout object to initialize + * @param pin The analogout pin name + */ +void analogout_init(dac_t *obj, PinName pin) +{ + /* get the peripheral name from the pin and assign it to the object */ + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName)NC); + + /* get the pin function and assign the used channel to the object */ + uint32_t function = pinmap_function(pin, PinMap_DAC); + MBED_ASSERT(function != (uint32_t)NC); + + obj->channel = GD_PIN_CHANNEL_GET(function); + MBED_ASSERT(obj->channel <= DAC1); + + /* configure GPIO */ + pinmap_pinout(pin, PinMap_DAC); + + /* save the pin for future use */ + obj->pin = pin; + + /* enable DAC clock */ + rcu_periph_clock_enable(RCU_DAC); + + /* configure DAC */ + dac_wave_mode_config(obj->channel, DAC_WAVE_DISABLE); + dac_trigger_disable(obj->channel); + dac_output_buffer_enable(obj->channel); + analogout_write_u16(obj, 0); +} + +/** Release the analogout object + * + * Note: This is not currently used in the mbed-drivers + * @param obj The analogout object + */ +void analogout_free(dac_t *obj) +{ + /* Reset DAC and disable clock */ + dac_deinit(); + rcu_periph_clock_disable(RCU_DAC); + + /* configure GPIO */ + /* get the pin function and assign the used channel to the object */ + uint32_t function = pinmap_function(obj->pin, PinMap_DAC); + MBED_ASSERT(function != (uint32_t)NC); + + pin_function(obj->pin, function); +} + +/** set the output voltage with specified as a integer + * + * @param obj The analogin object + * @param value The integer-point output voltage to be set + */ +static inline void dev_dac_data_set(dac_t *obj, int value) +{ + dac_data_set(obj->channel, DAC_ALIGN_12B_R, (value & DEV_DAC_ACCURACY_12BIT)); + + dac_enable(obj->channel); + + dac_software_trigger_enable(obj->channel); +} + +/** get the current DAC data + * + * @param obj The analogin object + * @return DAC data + */ +static inline int dev_dac_data_get(dac_t *obj) +{ + return (int)dac_output_value_get(obj->channel); +} + +/** Set the output voltage, specified as a percentage (float) + * + * @param obj The analogin object + * @param value The floating-point output voltage to be set + */ +void analogout_write(dac_t *obj, float value) +{ + if (value < 0.0f) { + /* when the value is less than 0.0, set DAC output date to 0 */ + dev_dac_data_set(obj, 0); + } else if (value > 1.0f) { + /* when the value is more than 1.0, set DAC output date to 0xFFF */ + dev_dac_data_set(obj, (int)DEV_DAC_ACCURACY_12BIT); + } else { + dev_dac_data_set(obj, (int)(value * (float)DEV_DAC_ACCURACY_12BIT)); + } +} + +/** Set the output voltage, specified as unsigned 16-bit + * + * @param obj The analogin object + * @param value The unsigned 16-bit output voltage to be set + */ +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + dev_dac_data_set(obj, value >> (16 - DEV_DAC_BITS)); +} + +/** Read the current voltage value on the pin + * + * @param obj The analogin object + * @return A floating-point value representing the current voltage on the pin, + * measured as a percentage + */ +float analogout_read(dac_t *obj) +{ + uint32_t ret_val = dev_dac_data_get(obj); + return (float)ret_val * (1.0f / (float)DEV_DAC_ACCURACY_12BIT); +} + +/** Read the current voltage value on the pin, as a normalized unsigned 16bit value + * + * @param obj The analogin object + * @return An unsigned 16-bit value representing the current voltage on the pin + */ +uint16_t analogout_read_u16(dac_t *obj) +{ + uint32_t ret_val = dev_dac_data_get(obj); + return (ret_val << 4) | ((ret_val >> 8) & 0x000F); +} + +#endif /* DEVICE_ANALOGOUT */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/can_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/can_api.c new file mode 100644 index 0000000000..b404a05ffd --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/can_api.c @@ -0,0 +1,632 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "can_api.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "mbed_error.h" + +#if DEVICE_CAN + +/* BS1[3:0] + 1 + BS2[2:0] + 1 */ +#define DEV_CAN_BT_SEG_MAX 24 +#define DEV_CAN_BT_SEG_MIN 4 + +/* CAN related register mask */ +#define DEV_CAN_BS1_MASK 0x000F0000 +#define DEV_CAN_BS2_MASK 0x00700000 +#define DEV_CAN_BAUDPSC_MASK 0x000003FF +#define DEV_CAN_SJW_MASK 0x03000000 +/* CAN0 interrupt vector number */ +#define CAN0_IRQ_BASE_NUM 19 + +/* CAN1 interrupt vector number */ +#define CAN1_IRQ_BASE_NUM 63 + +static uint32_t can_irq_ids[2] = {0}; +static can_irq_handler irq_callback; + +/** CAN interrupt handle . + * + * @param can_periph CAN0 or CAN1. + * @param id the CANx index . + */ +static void dev_can_irq_handle(uint32_t periph, int id) +{ + uint32_t flag0 = 0, flag1 = 0, flag2 = 0; + + flag0 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF0); + flag1 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF1); + flag2 = can_interrupt_flag_get(periph, CAN_INT_FLAG_MTF2); + + if (flag0) { + can_flag_clear(periph, CAN_FLAG_MTF0); + } + if (flag1) { + can_flag_clear(periph, CAN_FLAG_MTF1); + } + if (flag2) { + can_flag_clear(periph, CAN_FLAG_MTF2); + } + + /* CAN transmit complete interrupt handle */ + if (flag0 || flag1 || flag2) { + irq_callback(can_irq_ids[id], IRQ_TX); + } + + /* CAN receive complete interrupt handle */ + if (CAN_INTEN_RFNEIE0 == (CAN_INTEN(periph) & CAN_INTEN_RFNEIE0)) { + if (0 != can_receive_message_length_get(periph, CAN_FIFO0)) { + irq_callback(can_irq_ids[id], IRQ_RX); + } + } + + /* CAN error interrupt handle */ + if (SET == can_interrupt_flag_get(periph, CAN_INT_FLAG_ERRIF)) { + /* passive error interrupt handle */ + if (CAN_INTEN_PERRIE == (CAN_INTEN(periph) & CAN_INTEN_PERRIE)) { + if (SET == can_flag_get(periph, CAN_FLAG_PERR)) { + irq_callback(can_irq_ids[id], IRQ_PASSIVE); + } + } + + /* bus-off interrupt handle */ + if (CAN_INTEN_BOIE == (CAN_INTEN(periph) & CAN_INTEN_BOIE)) { + if (SET == can_flag_get(periph, CAN_FLAG_BOERR)) { + irq_callback(can_irq_ids[id], IRQ_BUS); + } + } + + irq_callback(can_irq_ids[id], IRQ_ERROR); + } +} + +/** CAN1 Interrupt Request entry . + * + */ +static void dev_can0_irq_entry(void) +{ + dev_can_irq_handle(CAN0, 0); +} + +/** CAN1 Interrupt Request entry . + * + */ +static void dev_can1_irq_entry(void) +{ + dev_can_irq_handle(CAN1, 1); +} + +/** Config the CAN mode . + * + * @param can_periph CAN0 or CAN1. + * @param mode the mode to be set. + */ +static void dev_can_mode_config(uint32_t can_periph, uint32_t mode) +{ + /* enter the initialization mode, only in initialization mode CAN register can be configured */ + can_working_mode_set(can_periph, CAN_MODE_INITIALIZE); + + CAN_BT(can_periph) &= ~BT_MODE(3); + CAN_BT(can_periph) |= BT_MODE(mode); + + /* enter the normal mode */ + can_working_mode_set(can_periph, CAN_MODE_NORMAL); +} + +/** Config the interrupt . + * + * @param can_periph CAN0 or CAN1. + * @param interrupt The interrupt type. + * @param enable enable or disable. + */ +static void dev_can_interrupt_config(uint32_t can_periph, uint32_t interrupt, uint32_t enable) +{ + if (enable) { + can_interrupt_enable(can_periph, interrupt); + } else { + can_interrupt_disable(can_periph, interrupt); + } +} + +/* This table can be used to calculate bit time +The first value is bit segment 1(BS1[3:0]), the second is bit segment 2(BS2[2:0]) */ +static const int sampling_points[23][2] = { + {0x0, 0x0}, /* 2, 50% */ + {0x1, 0x0}, /* 3, 67% */ + {0x2, 0x0}, /* 4, 75% */ + {0x3, 0x0}, /* 5, 80% */ + {0x3, 0x1}, /* 6, 67% */ + {0x4, 0x1}, /* 7, 71% */ + {0x5, 0x1}, /* 8, 75% */ + {0x6, 0x1}, /* 9, 78% */ + {0x6, 0x2}, /* 10, 70% */ + {0x7, 0x2}, /* 11, 73% */ + {0x8, 0x2}, /* 12, 75% */ + {0x9, 0x2}, /* 13, 77% */ + {0x9, 0x3}, /* 14, 71% */ + {0xA, 0x3}, /* 15, 73% */ + {0xB, 0x3}, /* 16, 75% */ + {0xC, 0x3}, /* 17, 76% */ + {0xD, 0x3}, /* 18, 78% */ + {0xD, 0x4}, /* 19, 74% */ + {0xE, 0x4}, /* 20, 75% */ + {0xF, 0x4}, /* 21, 76% */ + {0xF, 0x5}, /* 22, 73% */ + {0xF, 0x6}, /* 23, 70% */ + {0xF, 0x7}, /* 24, 67% */ +}; + +/** Set the baudrate. + * + * @param freq The frequency value to be set. + * + * @returns + * CAN_BT register value + */ +static unsigned int dev_can_baudrate_set(int freq) +{ + uint32_t reval; + uint16_t baud_psc; + uint16_t baud_psc_max; + uint32_t temp; + uint32_t bt_reg_config; + uint8_t flag; + int bits; + + flag = 0; + + /* computes the value that the CAN_BT register needs to be configured */ + /* (BAUDPSC[9:0] + 1) * ((BS1[3:0] + 1) + (BS2[2:0] + 1) + SJW(always 1)) */ + bt_reg_config = (rcu_clock_freq_get(CK_APB1) / freq); + /* BAUDPSC[9:0] minimum value */ + baud_psc = bt_reg_config / DEV_CAN_BT_SEG_MAX; + /* BAUDPSC[9:0] maximum value */ + baud_psc_max = bt_reg_config / DEV_CAN_BT_SEG_MIN; + + while ((!flag) && (baud_psc < baud_psc_max)) { + baud_psc++; + for (bits = 22; bits > 0; bits--) { + temp = (bits + 3) * (baud_psc + 1); + if (temp == bt_reg_config) { + flag = 1; + break; + } + } + } + + if (flag) { + reval = ((sampling_points[bits][1] << 20) & DEV_CAN_BS2_MASK) + | ((sampling_points[bits][0] << 16) & DEV_CAN_BS1_MASK) + | ((1 << 24) & DEV_CAN_SJW_MASK) + | ((baud_psc << 0) & DEV_CAN_BAUDPSC_MASK); + } else { + /* CAN_BT register reset value */ + reval = 0x01230000; + } + + return reval; +} + +/** init the CAN frequency. + * + * @param rd receive pin. + * @param td transmit pin. + * @param hz The bus frequency in hertz. + */ +void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) +{ + CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); + CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); + obj->can = (CANName)pinmap_merge(can_rd, can_td); + + MBED_ASSERT((int)obj->can != NC); + + if (obj->can == CAN_0) { + rcu_periph_clock_enable(RCU_CAN0); + can_deinit(obj->can); + obj->index = 0; + } else if (obj->can == CAN_1) { + rcu_periph_clock_enable(RCU_CAN0); + rcu_periph_clock_enable(RCU_CAN1); + can_deinit(obj->can); + obj->index = 1; + } else { + return; + } + + /* Configure the CAN pins */ + pinmap_pinout(rd, PinMap_CAN_RD); + pinmap_pinout(td, PinMap_CAN_TD); + if (rd != NC) { + pin_mode(rd, PullUp); + } + if (td != NC) { + pin_mode(td, PullUp); + } + + dev_can_mode_config(obj->can, CAN_NORMAL_MODE); + + can_frequency(obj, hz); + + if (obj->can == CAN_0) { + can_filter(obj, 0, 0, CANStandard, 0); + } else { + can_filter(obj, 0, 0, CANStandard, 14); + } +} + +/** init the CAN. + * + */ +void can_init(can_t *obj, PinName rd, PinName td) +{ + can_init_freq(obj, rd, td, 500000); +} + +/** disable CAN. + * + */ +void can_free(can_t *obj) +{ + can_deinit(obj->can); + + if (obj->can == CAN0) { + rcu_periph_clock_disable(RCU_CAN0); + } + + if (obj->can == CAN1) { + rcu_periph_clock_disable(RCU_CAN1); + } +} + +/** Set the frequency of the CAN interface. + * + * @param hz The bus frequency in hertz. + * + * @returns + * 1 if successful, + * 0 otherwise + */ +int can_frequency(can_t *obj, int hz) +{ + int reval; + + /* The maximum baud rate support to 1M */ + if (hz <= 1000000) { + if (SUCCESS == can_working_mode_set(obj->can, CAN_MODE_INITIALIZE)) { + CAN_BT(obj->can) = dev_can_baudrate_set(hz); + } else { + error("the configuration of can frequency is out of range \r\n"); + } + + if (SUCCESS == can_working_mode_set(obj->can, CAN_MODE_NORMAL)) { + reval = 1; + } else { + reval = 0; + } + } + + return reval; +} + +/** init the interrupt. + * + * @param handler the interrupt callback. + * @param id the CANx index. + */ +void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +{ + irq_callback = handler; + can_irq_ids[obj->index] = id; +} + +/** disable the interrupt. + * + */ +void can_irq_free(can_t *obj) +{ + if (CAN0 == obj->can) { + can_interrupt_disable(obj->can, CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 | \ + CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); + } + + if (CAN1 == obj->can) { + can_interrupt_disable(obj->can, CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 | \ + CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); + } + + can_irq_ids[obj->index] = 0; +} + +/** Set the interrupt handle. + * + * @param type The interrupt type. + * @param enable enable or disable. + */ +void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) +{ + uint32_t irq_num; + uint32_t vector = 0; + + if (obj->can == CAN_0) { + vector = (uint32_t)dev_can0_irq_entry; + irq_num = CAN0_IRQ_BASE_NUM; + } + + else if (obj->can == CAN_1) { + vector = (uint32_t)dev_can1_irq_entry; + irq_num = CAN1_IRQ_BASE_NUM; + } + + switch (type) { + case IRQ_RX: + dev_can_interrupt_config(obj->can, CAN_INT_RFNE0, enable); + break; + case IRQ_TX: + dev_can_interrupt_config(obj->can, CAN_INT_TME, enable); + irq_num += 1; + break; + case IRQ_ERROR: + dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_ERRN, enable); + irq_num += 3; + break; + case IRQ_PASSIVE: + dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_PERR, enable); + irq_num += 3; + break; + case IRQ_BUS: + dev_can_interrupt_config(obj->can, CAN_INT_ERR | CAN_INT_BO, enable); + irq_num += 3; + break; + default: + return; + } + + NVIC_SetVector((IRQn_Type)irq_num, vector); + NVIC_EnableIRQ((IRQn_Type)irq_num); +} + +/** Write a CANMessage to the bus. + * + * @param msg The CANMessage to write. + * + * @returns + * 0 if write failed, + * 1 if write was successful + */ +int can_write(can_t *obj, CAN_Message msg, int cc) +{ + can_trasnmit_message_struct transmit_message; + uint32_t i; + + /* configure frame type: data or remote */ + if (CANData == msg.type) { + transmit_message.tx_ft = CAN_FT_DATA; + } else if (CANRemote == msg.type) { + transmit_message.tx_ft = CAN_FT_REMOTE; + } else { + error("frame type of transmit message is invalid \r\n"); + } + + /* configure frame format: standard or extended */ + if (CANStandard == msg.format) { + transmit_message.tx_ff = CAN_FF_STANDARD; + transmit_message.tx_sfid = msg.id; + } else if (CANExtended == msg.format) { + transmit_message.tx_ff = CAN_FF_EXTENDED; + transmit_message.tx_efid = msg.id; + } else { + error("frame format of transmit message is invalid \r\n"); + } + + transmit_message.tx_dlen = msg.len; + + for (i = 0; i < msg.len; i++) { + transmit_message.tx_data[i] = msg.data[i]; + } + + can_message_transmit(obj->can, &transmit_message); + + return 1; +} + +/** Read a CANMessage from the bus. + * + * @param msg A CANMessage to read to. + * @param handle message filter handle (0 for any message). + * + * @returns + * 0 if no message arrived, + * 1 if message arrived + */ +int can_read(can_t *obj, CAN_Message *msg, int handle) +{ + uint8_t i; + uint8_t fifo_number; + + fifo_number = (uint8_t)handle; + can_receive_message_struct receive_message; + + /* if the frame is not received, retrun 0 */ + if (0 == can_receive_message_length_get(obj->can, CAN_FIFO0)) { + return 0; + } + + can_message_receive(obj->can, fifo_number, &receive_message); + + if (receive_message.rx_ff == CAN_RFIFOMI_FF) { + msg->format = CANExtended; + } else { + msg->format = CANStandard; + } + + if (0 == msg->format) { + msg->id = (uint32_t)0x000007FF & (receive_message.rx_sfid); + } else { + msg->id = (uint32_t)0x1FFFFFFF & (receive_message.rx_efid); + } + + if (receive_message.rx_ft == CAN_RFIFOMI_FT) { + msg->type = CANRemote; + } else { + msg->type = CANData; + } + + msg->len = (uint8_t)receive_message.rx_dlen; + + for (i = 0; i < msg->len; i++) { + msg->data[i] = (uint8_t)receive_message.rx_data[i]; + } + /* If the frame is received successfully, retrun 1 */ + return 1; +} + +/** Reset CAN interface. + * + * To use after error overflow. + */ +void can_reset(can_t *obj) +{ + can_deinit(obj->can); +} + +/** Detects read errors - Used to detect read overflow errors. + * + * @returns number of read errors + */ +unsigned char can_rderror(can_t *obj) +{ + return can_receive_error_number_get(obj->can); +} + +/** Detects write errors - Used to detect write overflow errors. + * + * @returns number of write errors + */ +unsigned char can_tderror(can_t *obj) +{ + return can_transmit_error_number_get(obj->can); +} + +/** Puts or removes the CAN interface into silent monitoring mode. + * + * @param silent boolean indicating whether to go into silent mode or not. + */ +void can_monitor(can_t *obj, int silent) +{ + if (silent) { + dev_can_mode_config(obj->can, CAN_SILENT_MODE); + } else { + dev_can_mode_config(obj->can, CAN_NORMAL_MODE); + } +} + +/** Change CAN operation to the specified mode. + * + * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest). + * + * @returns + * 0 if mode change failed or unsupported, + * 1 if mode change was successful + */ +int can_mode(can_t *obj, CanMode mode) +{ + switch (mode) { + case MODE_NORMAL: + dev_can_mode_config(obj->can, CAN_NORMAL_MODE); + break; + case MODE_SILENT: + dev_can_mode_config(obj->can, CAN_SILENT_MODE); + break; + case MODE_TEST_GLOBAL: + case MODE_TEST_LOCAL: + dev_can_mode_config(obj->can, CAN_LOOPBACK_MODE); + break; + case MODE_TEST_SILENT: + dev_can_mode_config(obj->can, CAN_SILENT_LOOPBACK_MODE); + break; + default: + return 0; + } + + return 1; +} + +/** Filter out incomming messages. + * + * @param id the id to filter on. + * @param mask the mask applied to the id. + * @param format format to filter on (Default CANAny). + * @param handle message filter handle (Optional). + * + * @returns + * 0 if filter change failed or unsupported, + * new filter handle if successful + */ +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) +{ + can_filter_parameter_struct can_filter; + + can_filter.filter_number = handle; + can_filter.filter_mode = CAN_FILTERMODE_MASK; + can_filter.filter_bits = CAN_FILTERBITS_32BIT; + can_filter.filter_fifo_number = CAN_FIFO0; + can_filter.filter_enable = ENABLE; + + switch (format) { + case CANStandard: + /* configure SFID[10:0] */ + can_filter.filter_list_high = id << 5; + can_filter.filter_list_low = 0x0; + /* configure SFID[10:0] mask */ + can_filter.filter_mask_high = mask << 5; + /* both data and remote frames can be received */ + can_filter.filter_mask_low = 0x0; + + break; + + case CANExtended: + /* configure EFID[28:13] */ + can_filter.filter_list_high = id >> 13; + /* configure EFID[12:0] and frame format bit set */ + can_filter.filter_list_low = (0x00FF & (id << 3)) | (1 << 2); + /* configure EFID[28:13] mask */ + can_filter.filter_mask_high = mask >> 13; + /* configure EFID[12:0] and frame format bit mask */ + /* both data and remote frames can be received */ + can_filter.filter_mask_low = (0x00FF & (mask << 3)) | (1 << 2); + + break; + + case CANAny: + error("CANAny mode is not supported \r\n"); + return 0; + + default: + error("parameter is not supported \r\n"); + return 0; + } + + can_filter_init(&can_filter); + can1_filter_start_bank(handle); + + return handle; +} + +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/device.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/device.h new file mode 100644 index 0000000000..ceedbdd746 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/device.h @@ -0,0 +1,27 @@ +/* The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. */ +/* Check the 'features' section of the target description in 'targets.json' for more details. */ +/* mbed Microcontroller Library +* Copyright (c) 2006-2018 ARM Limited +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif /* MBED_DEVICE_H */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/flash_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/flash_api.c new file mode 100644 index 0000000000..d1c07b5ad9 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/flash_api.c @@ -0,0 +1,205 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include "cmsis.h" + +#define FLASH_SIZE (uint32_t)(FMC_SIZE * 1024) +#define FLASH_BANK0_PAGE_SIZE (0x800) +#define FLASH_BANK1_PAGE_SIZE (0x1000) +#define FLASH_BANK0_END_ADDR (0x0807FFFF) +#define FLASH_BANK1_END_ADDR (0x080FFFFF) +#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE) - 1 +#define WORD_SIZE (4U) + +/* unlock the main FLASH operation + * + * @return 0 for success, -1 for error +*/ +static int32_t flash_unlock(void) +{ + fmc_unlock(); + if (RESET != ((FMC_CTL0 & FMC_CTL0_LK) || (FMC_CTL1 & FMC_CTL1_LK))) { + return -1; + } + return 0; +} + +/* lock the main FLASH operation + * + * @return 0 for success, -1 for error +*/ +static int32_t flash_lock(void) +{ + fmc_lock(); + if (RESET == ((FMC_CTL0 & FMC_CTL0_LK) && (FMC_CTL1 & FMC_CTL1_LK))) { + return -1; + } + return 0; +} + +/** Initialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +/** Uninitialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + int32_t flash_state = 0; + flash_unlock(); + + /* clear FLASH flag */ + fmc_flag_clear(FMC_FLAG_BANK0_END); + fmc_flag_clear(FMC_FLAG_BANK0_WPERR); + fmc_flag_clear(FMC_FLAG_BANK0_PGERR); + + /* make sure the address is a right page address */ + if (FMC_READY != fmc_page_erase(address)) { + flash_state = -1; + } + + flash_lock(); + return flash_state; +} + +/** Program pages starting at defined address + * + * The pages should not cross multiple sectors. + * This function does not do any check for address alignments or if size is aligned to a page size. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + uint32_t *p_data; + p_data = (uint32_t *)data; + uint32_t num = 0; + int32_t flash_state = 0; + flash_unlock(); + + /* clear FLASH flag */ + fmc_flag_clear(FMC_FLAG_BANK0_END); + fmc_flag_clear(FMC_FLAG_BANK0_WPERR); + fmc_flag_clear(FMC_FLAG_BANK0_PGERR); + + if (size % 4) { + num = size / 4 + 1; + } else { + num = size / 4; + } + for (uint32_t i = 0; i < num; i++) { + + if (FMC_READY != fmc_word_program(address, *(p_data + i))) { + flash_state = -1; + break; + } + address += 4; + } + flash_lock(); + return flash_state; +} + +/** Get sector size + * + * @param obj The flash object + * @param address The sector starting address + * @return The size of a sector + */ +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + uint32_t sector_size = 0; + if ((FLASH_BASE <= address) && (FLASH_BANK0_END_ADDR >= address)) { + sector_size = FLASH_BANK0_PAGE_SIZE; + } else if ((FLASH_BANK0_END_ADDR < address) && (FLASH_END_ADDR >= address)) { + sector_size = FLASH_BANK1_PAGE_SIZE; + } else { + return MBED_FLASH_INVALID_SIZE; + } + return sector_size; +} + +/** Get page size + * + * The page size defines the writable page size + * @param obj The flash object + * @return The size of a page + */ +uint32_t flash_get_page_size(const flash_t *obj) +{ + return WORD_SIZE; +} + +/** Get start address for the flash region + * + * @param obj The flash object + * @return The start address for the flash region + */ +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FLASH_BASE; +} + +/** Get the flash region size + * + * @param obj The flash object + * @return The flash region size + */ +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_SIZE; +} + +/** Get the flash erase value + * + * @param obj The flash object + * @return The flash erase value + */ +uint8_t flash_get_erase_value(const flash_t *obj) +{ + return 0xFF; +} + +#endif /* DEVICE_FLASH */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_api.c new file mode 100644 index 0000000000..18d4f148e0 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_api.c @@ -0,0 +1,151 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gd32f30x_gpio.h" +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +extern const int GD_GPIO_REMAP[]; +extern const int GD_GPIO_SPEED[]; +extern const int GD_GPIO_MODE[]; + +/* Enable GPIO clock and return GPIO base address */ +uint32_t gpio_clock_enable(uint32_t port_idx) +{ + uint32_t gpio_add = 0; + switch (port_idx) { + case PORTA: + gpio_add = GPIOA; + rcu_periph_clock_enable(RCU_GPIOA); + break; + case PORTB: + gpio_add = GPIOB; + rcu_periph_clock_enable(RCU_GPIOB); + break; + case PORTC: + gpio_add = GPIOC; + rcu_periph_clock_enable(RCU_GPIOC); + break; + case PORTD: + gpio_add = GPIOD; + rcu_periph_clock_enable(RCU_GPIOD); + break; + case PORTE: + gpio_add = GPIOE; + rcu_periph_clock_enable(RCU_GPIOE); + break; + default: + error("port number not exist"); + break; + } + return gpio_add; +} + +/** Set the given pin as GPIO + * + * @param pin The pin to be set as GPIO + * @return The GPIO port mask for this pin + */ +uint32_t gpio_set(PinName pin) +{ + + MBED_ASSERT(pin != (PinName)NC); + pin_function(pin, MODE_IN_FLOATING); + /* return pin mask */ + return (uint32_t)(1 << ((uint32_t)pin & 0xF)); +} + +/** Initialize the GPIO pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin to initialize + */ +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + /* fill struct parameter for future use */ + uint32_t port_index = GD_PORT_GET(pin); + uint32_t gpio = gpio_clock_enable(port_index); + obj->mask = gpio_set(pin); + obj->gpio_periph = gpio; +} + +/** Set the input pin mode + * + * @param obj The GPIO object + * @param mode The pin mode to be set + */ +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->pin, mode); +} + +/** Set the output value + * + * @param obj The GPIO object + * @param value The value to be set + */ +void gpio_write(gpio_t *obj, int value) +{ + /* set or reset GPIO pin */ + if (value) { + GPIO_BOP(obj->gpio_periph) = (1 << (uint32_t)GD_PIN_GET(obj->pin)); + } else { + GPIO_BC(obj->gpio_periph) = (1 << (uint32_t)GD_PIN_GET(obj->pin)); + } +} + +/** Read the input value + * + * @param obj The GPIO object + * @return An integer value 1 or 0 + */ +int gpio_read(gpio_t *obj) +{ + /* return state of GPIO pin */ + return ((GPIO_ISTAT(obj->gpio_periph) & obj->mask) ? 1 : 0); +} + +/* Checks if gpio object is connected (pin was not initialized with NC) + * @param pin The pin to be set as GPIO + * @return 0 if port is initialized with NC + **/ +int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != (PinName)NC; +} + +/** Set the pin direction + * + * @param obj The GPIO object + * @param direction The pin direction to be set + */ +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + + /* config GPIO pin as input or output */ + if (direction == PIN_INPUT) { + gpio_para_init(obj->gpio_periph, GD_GPIO_MODE[MODE_IN_FLOATING], GD_GPIO_SPEED[0], (1 << (uint32_t)GD_PIN_GET(obj->pin))); + } else { + gpio_para_init(obj->gpio_periph, GD_GPIO_MODE[MODE_OUT_PP], GD_GPIO_SPEED[0], (1 << (uint32_t)GD_PIN_GET(obj->pin))); + } +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_irq_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_irq_api.c new file mode 100644 index 0000000000..c48633977e --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_irq_api.c @@ -0,0 +1,330 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define EDGE_NONE (0) +#define EDGE_RISE (1) +#define EDGE_FALL (2) + +extern uint32_t gpio_clock_enable(uint32_t port_idx); +static gpio_irq_handler irq_handler; + +typedef struct { + uint32_t exti_idx; + uint32_t exti_gpiox; /* base address of gpio */ + uint32_t exti_pinx; /* pin number */ +} gpio_exti_info_struct; + +/* EXTI0...EXTI15 */ +static gpio_exti_info_struct exti_info_array[16] = {0}; + +/** handle EXTI interrupt in EXTI0 to EXTI15 + + * @param irq_index the line of EXTI(0~15) + */ +static void exti_handle_interrupt(uint32_t irq_index) +{ + gpio_exti_info_struct *gpio_exti = &exti_info_array[irq_index]; + + /* get the port and pin of EXTI */ + uint32_t gpio = (uint32_t)(gpio_exti->exti_gpiox); + uint32_t pin = (uint32_t)(1 << (gpio_exti->exti_pinx)); + + /* clear interrupt flag */ + if (exti_interrupt_flag_get((exti_line_enum)pin) != RESET) { + exti_interrupt_flag_clear((exti_line_enum)pin); + /* check which edge has generated the irq */ + if ((GPIO_ISTAT(gpio) & pin) == 0) { + irq_handler(gpio_exti->exti_idx, IRQ_FALL); + } else { + irq_handler(gpio_exti->exti_idx, IRQ_RISE); + } + } + +} + +/* EXTI0 interrupt handler */ +static void gpio_irq_exti0(void) +{ + exti_handle_interrupt(0); +} +/* EXTI1 interrupt handler */ +static void gpio_irq_exti1(void) +{ + exti_handle_interrupt(1); +} +/* EXTI2 interrupt handler */ +static void gpio_irq_exti2(void) +{ + exti_handle_interrupt(2); +} +/* EXTI3 interrupt handler */ +static void gpio_irq_exti3(void) +{ + exti_handle_interrupt(3); +} +/* EXTI4 interrupt handler */ +static void gpio_irq_exti4(void) +{ + exti_handle_interrupt(4); +} +/* EXTI5 interrupt handler */ +static void gpio_irq_exti5(void) +{ + exti_handle_interrupt(5); +} +/* EXTI6 interrupt handler */ +static void gpio_irq_exti6(void) +{ + exti_handle_interrupt(6); +} +/* EXTI7 interrupt handler */ +static void gpio_irq_exti7(void) +{ + exti_handle_interrupt(7); +} +/* EXTI8 interrupt handler */ +static void gpio_irq_exti8(void) +{ + exti_handle_interrupt(8); +} +/* EXTI9 interrupt handler */ +static void gpio_irq_exti9(void) +{ + exti_handle_interrupt(9); +} +/* EXTI10 interrupt handler */ +static void gpio_irq_exti10(void) +{ + exti_handle_interrupt(10); +} +/* EXTI11 interrupt handler */ +static void gpio_irq_exti11(void) +{ + exti_handle_interrupt(11); +} +/* EXTI12 interrupt handler */ +static void gpio_irq_exti12(void) +{ + exti_handle_interrupt(12); +} +/* EXTI13 interrupt handler */ +static void gpio_irq_exti13(void) +{ + exti_handle_interrupt(13); +} +/* EXTI14 interrupt handler */ +static void gpio_irq_exti14(void) +{ + exti_handle_interrupt(14); +} +/* EXTI15 interrupt handler */ +static void gpio_irq_exti15(void) +{ + exti_handle_interrupt(15); +} + +/** Initialize the GPIO IRQ pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin name + * @param handler The handler to be attached to GPIO IRQ + * @param id The object ID (id != 0, 0 is reserved) + * @return -1 if pin is NC, 0 otherwise + */ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint32_t vector = 0; + gpio_exti_info_struct *gpio_exti; + if (pin == NC) { + return -1; + } + + /* Enable AF Clock */ + rcu_periph_clock_enable(RCU_AF); + + uint32_t port_index = GD_PORT_GET(pin); + uint32_t pin_index = GD_PIN_GET(pin); + /* Enable GPIO clock */ + uint32_t gpio_add = gpio_clock_enable(port_index); + + /* fill EXTI information according to pin_index . + eg. use PORTE_9 as EXTI interrupt, the irq type is EXTI5_9_IRQn */ + if (pin_index == 0) { + vector = (uint32_t)&gpio_irq_exti0; + obj->irq_index = 0; + obj->irq_n = EXTI0_IRQn; + } else if (pin_index == 1) { + vector = (uint32_t)&gpio_irq_exti1; + obj->irq_index = 1; + obj->irq_n = EXTI1_IRQn; + } else if (pin_index == 2) { + vector = (uint32_t)&gpio_irq_exti2; + obj->irq_index = 2; + obj->irq_n = EXTI2_IRQn; + } else if (pin_index == 3) { + vector = (uint32_t)&gpio_irq_exti3; + obj->irq_index = 3; + obj->irq_n = EXTI3_IRQn; + } else if (pin_index == 4) { + vector = (uint32_t)&gpio_irq_exti4; + obj->irq_index = 4; + obj->irq_n = EXTI4_IRQn; + } else if (pin_index == 5) { + vector = (uint32_t)&gpio_irq_exti5; + obj->irq_index = 5; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 6) { + vector = (uint32_t)&gpio_irq_exti6; + obj->irq_index = 6; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 7) { + vector = (uint32_t)&gpio_irq_exti7; + obj->irq_index = 7; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 8) { + vector = (uint32_t)&gpio_irq_exti8; + obj->irq_index = 8; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 9) { + vector = (uint32_t)&gpio_irq_exti9; + obj->irq_index = 9; + obj->irq_n = EXTI5_9_IRQn; + } else if (pin_index == 10) { + vector = (uint32_t)&gpio_irq_exti10; + obj->irq_index = 10; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 11) { + vector = (uint32_t)&gpio_irq_exti11; + obj->irq_index = 11; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 12) { + vector = (uint32_t)&gpio_irq_exti12; + obj->irq_index = 12; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 13) { + vector = (uint32_t)&gpio_irq_exti13; + obj->irq_index = 13; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 14) { + vector = (uint32_t)&gpio_irq_exti14; + obj->irq_index = 14; + obj->irq_n = EXTI10_15_IRQn; + } else if (pin_index == 15) { + vector = (uint32_t)&gpio_irq_exti15; + obj->irq_index = 15; + obj->irq_n = EXTI10_15_IRQn; + } else { + error("pin not supported for interrupt in.\n"); + return -1; + } + + /* Save informations for future use */ + obj->event = EDGE_NONE; + obj->pin = pin; + + gpio_exti = &exti_info_array[obj->irq_index]; + gpio_exti->exti_idx = id; + gpio_exti->exti_gpiox = gpio_add; + gpio_exti->exti_pinx = pin_index; + + irq_handler = handler; + + /* Enable EXTI interrupt */ + NVIC_SetVector(obj->irq_n, vector); + gpio_irq_enable(obj); + + return 0; +} + +/** Release the GPIO IRQ PIN + * + * @param obj The gpio object + */ +void gpio_irq_free(gpio_irq_t *obj) +{ + gpio_exti_info_struct *gpio_exti = &exti_info_array[obj->irq_index]; + + /* Disable EXTI interrupt */ + gpio_irq_disable(obj); + /* Reset struct of exti information */ + gpio_exti->exti_idx = 0; + gpio_exti->exti_gpiox = 0; + gpio_exti->exti_pinx = 0; +} + +/** Enable/disable pin IRQ event + * + * @param obj The GPIO object + * @param event The GPIO IRQ event + * @param enable The enable flag + */ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + if (event == IRQ_RISE) { + if (enable) { + exti_init((exti_line_enum)(1 << GD_PIN_GET(obj->pin)), EXTI_INTERRUPT, EXTI_TRIG_RISING); + /* Clear interrupt enable bit, rising/falling bit */ + } else { + EXTI_INTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_RTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_FTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + } + } + if (event == IRQ_FALL) { + if (enable) { + exti_init((exti_line_enum)(1 << (GD_PIN_GET(obj->pin))), EXTI_INTERRUPT, EXTI_TRIG_FALLING); + /* Clear interrupt enable bit, rising/falling bit */ + } else { + EXTI_INTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_RTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + EXTI_FTEN &= ~(uint32_t)(exti_line_enum)(1 << GD_PIN_GET(obj->pin)); + } + } +} + +/** Enable GPIO IRQ + * + * This is target dependent, as it might enable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_enable(gpio_irq_t *obj) +{ + /* Select EXTI Source */ + gpio_exti_source_select(GD_PORT_GET(obj->pin), GD_PIN_GET(obj->pin)); + exti_interrupt_enable((exti_line_enum)(1 << GD_PIN_GET(obj->pin))); + NVIC_EnableIRQ(obj->irq_n); +} + +/** Disable GPIO IRQ + * + * This is target dependent, as it might disable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_disable(gpio_irq_t *obj) +{ + /* Clear EXTI line configuration */ + exti_interrupt_disable((exti_line_enum)(1 << GD_PIN_GET(obj->pin))); + NVIC_DisableIRQ(obj->irq_n); + NVIC_ClearPendingIRQ(obj->irq_n); + obj->event = EDGE_NONE; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/i2c_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/i2c_api.c new file mode 100644 index 0000000000..d7fb82c7e2 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/i2c_api.c @@ -0,0 +1,655 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#if DEVICE_I2C_ASYNCH +#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) +#else +#define I2C_S(obj) (struct i2c_s *) (obj) +#endif + +#define BUSY_TIMEOUT ((SystemCoreClock / obj_s->freq) * 2 * 10) +#define FLAG_TIMEOUT (0x1000U) + +/** Reset I2C peripheral by hardware method. Most of the implementation enable RCU reset. + * + * @param obj The I2C object + */ +static void i2c_hw_reset(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + switch (obj_s->i2c) { + case I2C_0: + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + + case I2C_1: + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + } +} + +/** Initialize the I2C peripheral. It sets the default parameters for I2C + * peripheral, and configures its specifieds pins. + * + * @param obj The I2C object + * @param sda The sda pin + * @param scl The scl pin + */ +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + struct i2c_s *obj_s = I2C_S(obj); + + /* find the I2C by pins */ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + + obj_s->sda = sda; + obj_s->scl = scl; + obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT(obj_s->i2c != (I2CName)NC); + + switch (obj_s->i2c) { + case I2C_0: + /* enable I2C0 clock and configure the pins of I2C0 */ + obj_s->index = 0; + rcu_periph_clock_enable(RCU_I2C0); + + break; + + case I2C_1: + /* enable I2C1 clock and configure the pins of I2C1 */ + obj_s->index = 1; + rcu_periph_clock_enable(RCU_I2C1); + + break; + + default: + break; + } + + /* configure the pins of I2C */ + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + /* 100 KHz as the default I2C frequence */ + i2c_frequency(obj, 100000); + + obj_s->state = (operation_state_enum)I2C_STATE_NONE; + obj_s->previous_state_mode = I2C_STATE_NONE; + obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; + +#if DEVICE_I2CSLAVE + /* I2C master by default */ + obj_s->slave = 0; +#endif +} + +/** Configure the I2C frequency + * + * @param obj The I2C object + * @param hz Frequency in Hz + */ +void i2c_frequency(i2c_t *obj, int hz) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = BUSY_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) && (--timeout != 0)); + + /* reset to clear pending flags */ + i2c_hw_reset(obj); + + /* disable I2C peripheral */ + i2c_disable(obj_s->i2c); + + /* configure I2C frequence */ + i2c_clock_config(obj_s->i2c, hz, I2C_DTCY_2); + + /* configure I2C address mode and slave address */ + i2c_mode_addr_config(obj_s->i2c, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0); + + /* enable I2C peripheral */ + i2c_enable(obj_s->i2c); +} + +/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop() + * + * @param obj The I2C object + */ +void i2c_reset(i2c_t *obj) +{ + i2c_stop(obj); +} + +/** Send START command + * + * @param obj The I2C object + */ +int i2c_start(i2c_t *obj) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + /* clear I2C_FLAG_AERR Flag */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_AERR); + + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { + if ((timeout--) == 0) { + return (int)GD_BUSY; + } + } + + /* ensure the i2c has been stopped */ + timeout = FLAG_TIMEOUT; + while ((I2C_CTL0(obj_s->i2c) & I2C_CTL0_STOP) == I2C_CTL0_STOP) { + if ((timeout--) == 0) { + return (int)GD_ERROR; + } + } + + /* generate a START condition */ + i2c_start_on_bus(obj_s->i2c); + + /* ensure the i2c has been started successfully */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { + if ((timeout--) == 0) { + return (int)GD_ERROR; + } + } + + return (int)GD_OK; +} + +/** Send STOP command + * + * @param obj The I2C object + */ +int i2c_stop(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + /* generate a STOP condition */ + i2c_stop_on_bus(obj_s->i2c); + + /* wait for STOP bit reset */ + while ((I2C_CTL0(obj_s->i2c) & I2C_CTL0_STOP)); + + return 0; +} + +/** Read one byte + * + * @param obj The I2C object + * @param last Acknoledge + * @return The read byte + */ +int i2c_byte_read(i2c_t *obj, int last) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + if (last) { + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + } else { + /* enable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + } + + /* wait until the byte is received */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)) == RESET) { + if ((timeout--) == 0) { + return -1; + } + } + + return (int)I2C_DATA(obj_s->i2c); +} + +/** Write one byte + * + * @param obj The I2C object + * @param data Byte to be written + * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout. + */ +int i2c_byte_write(i2c_t *obj, int data) +{ + int timeout; + struct i2c_s *obj_s = I2C_S(obj); + + I2C_DATA(obj_s->i2c) = (uint8_t)data; + + /* wait until the byte is transmitted */ + timeout = FLAG_TIMEOUT; + while (((i2c_flag_get(obj_s->i2c, I2C_FLAG_TBE)) == RESET) && + ((i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)) == RESET)) { + if ((timeout--) == 0) { + return 2; + } + } + + return 1; +} + +/** Blocking reading data + * + * @param obj The I2C object + * @param address 7-bit address (last bit is 1) + * @param data The buffer for receiving + * @param length Number of bytes to read + * @param stop Stop to be generated after the transfer is done + * @return Number of read bytes + */ +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + struct i2c_s *obj_s = I2C_S(obj); + uint32_t count = 0U; + int timeout = 0; + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || + obj_s->global_trans_option == I2C_LAST_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_FIRST_FRAME; + } + } else if (obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->global_trans_option == I2C_NEXT_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_NEXT_FRAME; + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME) { + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->previous_state_mode != I2C_STATE_MASTER_BUSY_RX) { + /* generate a START condition */ + i2c_start_on_bus(obj_s->i2c); + + /* ensure the i2c has been started successfully */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + + /* send slave address */ + i2c_master_addressing(obj_s->i2c, address, I2C_RECEIVER); + + if (1 == length) { + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + /* send a stop condition to I2C bus*/ + } else if (2 == length) { + /* send a NACK for the next data byte which will be received into the shift register */ + i2c_ackpos_config(obj_s->i2c, I2C_ACKPOS_NEXT); + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + } else { + /* enable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + } + + /* wait until I2C_FLAG_ADDSEND flag is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + } + + /* clear ADDSEND */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + } + + obj_s->state = (operation_state_enum)I2C_STATE_MASTER_BUSY_RX; + + for (count = 0; count < length; count++) { + if (length > 2 && count == length - 3) { + while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)); + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + } else if (2 == length && count == 0) { + while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_BTC)); + } + + while (RESET == i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)); + data[count] = i2c_data_receive(obj_s->i2c); + } + + obj_s->previous_state_mode = obj_s->state; + + /* if not sequential read, then send stop */ + if (stop) { + i2c_stop(obj); + } + + return count; +} + +/** Blocking sending data + * + * @param obj The I2C object + * @param address 7-bit address (last bit is 0) + * @param data The buffer for sending + * @param length Number of bytes to write + * @param stop Stop to be generated after the transfer is done + * @return + * zero or non-zero - Number of written bytes + * negative - I2C_ERROR_XXX status + */ +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + struct i2c_s *obj_s = I2C_S(obj); + gd_status_enum status = GD_OK; + uint32_t count = 0; + int timeout = 0; + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || + obj_s->global_trans_option == I2C_LAST_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_FIRST_AND_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_FIRST_FRAME; + } + } else if (obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->global_trans_option == I2C_NEXT_FRAME) { + if (stop) { + obj_s->global_trans_option = I2C_LAST_FRAME; + } else { + obj_s->global_trans_option = I2C_NEXT_FRAME; + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME) { + /* wait until I2C_FLAG_I2CBSY flag is reset */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_I2CBSY)) == SET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + } + + if (obj_s->global_trans_option == I2C_FIRST_AND_LAST_FRAME || obj_s->global_trans_option == I2C_FIRST_FRAME || + obj_s->previous_state_mode != I2C_STATE_MASTER_BUSY_TX) { + /* generate a START condition */ + i2c_start_on_bus(obj_s->i2c); + + /* ensure the i2c has been started successfully */ + timeout = FLAG_TIMEOUT; + while ((i2c_flag_get(obj_s->i2c, I2C_FLAG_SBSEND)) == RESET) { + if ((timeout--) == 0) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + } + + /* send slave address */ + i2c_master_addressing(obj_s->i2c, address, I2C_TRANSMITTER); + + /* wait until I2C_FLAG_ADDSEND flag is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + } + + /* clear ADDSEND */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + } + + obj_s->state = (operation_state_enum)I2C_STATE_MASTER_BUSY_TX; + + for (count = 0; count < length; count++) { + status = (gd_status_enum)i2c_byte_write(obj, data[count]); + if (status != 1) { + i2c_stop(obj); + return count; + } + } + + obj_s->previous_state_mode = obj_s->state; + + /* if not sequential write, then send stop */ + if (stop) { + i2c_stop(obj); + } + + return count; +} + +#if DEVICE_I2CSLAVE + +/** Configure I2C address. + * @param obj The I2C object + * @param idx Currently not used + * @param address The address to be set + * @param mask Currently not used + */ +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + struct i2c_s *obj_s = I2C_S(obj); + + /* disable I2C peripheral */ + i2c_disable(obj_s->i2c); + /* I2C clock configure */ + i2c_clock_config(obj_s->i2c, 100000, I2C_DTCY_2); + /* I2C address configure */ + i2c_mode_addr_config(obj_s->i2c, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, address); + /* enable I2C0 */ + i2c_enable(obj_s->i2c); + /* enable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); +} + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive + * @return non-zero if a value is available + */ +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + struct i2c_s *obj_s = I2C_S(obj); + + if (enable_slave) { + obj_s->slave = 1; + } else { + obj_s->slave = 0; + } +} + +/* the same as the definition in I2CSlave.h class I2CSlave */ +#define NoData 0 /* the slave has not been addressed */ +#define ReadAddressed 1 /* the master has requested a read from this slave (slave as transmitter) */ +#define WriteGeneral 2 /* the master is writing to all slave */ +#define WriteAddressed 3 /* the master is writing to this slave (slave as receiver) */ + +/** Check to see if the I2C slave has been addressed. + * @param obj The I2C object + * @return The status - 1 - read addresses, 2 - write to all slaves, + * 3 write addressed, 0 - the slave has not been addressed + */ +int i2c_slave_receive(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + int ret = NoData; + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + + if (i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + if (i2c_flag_get(obj_s->i2c, I2C_FLAG_RXGC)) { + ret = WriteGeneral; + } + + if (i2c_flag_get(obj_s->i2c, I2C_FLAG_TRS)) { + ret = ReadAddressed; + } else { + ret = WriteAddressed; + } + } + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + + return (ret); +} + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param data The buffer for receiving + * @param length Number of bytes to read + * @return non-zero if a value is available + */ +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + struct i2c_s *obj_s = I2C_S(obj); + int count = 0; + int timeout = 0; + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + + /* wait until ADDSEND bit is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + /* clear ADDSEND bit */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + + while (0 < length) { + /* wait until the RBNE bit is set */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_RBNE)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + *data = i2c_data_receive(obj_s->i2c); + data++; + length--; + count++; + } + /* wait until the STPDET bit is set */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_STPDET)) { + timeout++; + if (timeout > 100) { + return count; + } + } + /* clear the STPDET bit */ + i2c_enable(obj_s->i2c); + + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + + return count; +} + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @param data The buffer for sending + * @param length Number of bytes to write + * @return non-zero if a value is available + */ +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + struct i2c_s *obj_s = I2C_S(obj); + int count = 0; + int timeout = 0; + + i2c_ack_config(obj_s->i2c, I2C_ACK_ENABLE); + /* wait until ADDSEND bit is set */ + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_ADDSEND)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + /* clear ADDSEND bit */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_ADDSEND); + while (length > 0) { + /* wait until the TBE bit is set */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_TBE)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + i2c_data_transmit(obj_s->i2c, *data); + data++; + length--; + count++; + } + /* the master doesn't acknowledge for the last byte */ + timeout = 0; + while (!i2c_flag_get(obj_s->i2c, I2C_FLAG_AERR)) { + timeout++; + if (timeout > 100000) { + return -1; + } + } + /* clear the bit of AERR */ + i2c_flag_clear(obj_s->i2c, I2C_FLAG_AERR); + /* disable acknowledge */ + i2c_ack_config(obj_s->i2c, I2C_ACK_DISABLE); + + return count; +} +#endif /* DEVICE_I2CSLAVE */ + +#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/mbed_overrides.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/mbed_overrides.c new file mode 100644 index 0000000000..82aac5e422 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/mbed_overrides.c @@ -0,0 +1,156 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gd32f30x.h" +#include "cmsis.h" +#include "hal_tick.h" + +int mbed_sdk_inited = 0; + +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +#if TICKER_TIMER_WIDTH_BIT == 16 +extern void ticker_16bits_timer_init(void); +#else +extern void ticker_32bits_timer_init(void); +#endif + +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while (1) { + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) { + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while (0U == (PMU_CS & PMU_CS_HDRF)) { + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while (0U == (PMU_CS & PMU_CS_HDSRF)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +/** + * SDK hook for running code before ctors or OS + * + * This is a weak function which can be overridden by a target's + * SDK to allow code to run after ram is initialized but before + * the OS has been started or constructors have run. + * + * Preconditions: + * - Ram is initialized + * - NVIC is setup + */ +/** + * This function is called after RAM initialization and before main. + */ +void mbed_sdk_init() +{ + /* Update the SystemCoreClock */ + SystemCoreClockUpdate(); + nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0); + + /* configure 1ms tick */ +#if TICKER_TIMER_WIDTH_BIT == 16 + ticker_16bits_timer_init(); +#else + ticker_32bits_timer_init(); +#endif + + system_clock_120m_hxtal(); + + SystemCoreClockUpdate(); + + mbed_sdk_inited = 1; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/objects.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/objects.h new file mode 100644 index 0000000000..f2ed68a521 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/objects.h @@ -0,0 +1,183 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct gpio_s gpio_t; + +struct gpio_s { + uint32_t mask; + PinName pin; + __IO uint32_t gpio_periph; +}; + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +#if DEVICE_ANALOGOUT +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; +#endif + +struct can_s { + CANName can; + int index; +}; + +struct pwmout_s { + PWMName pwm; + uint32_t cnt_unit; + uint8_t ch; +}; + +struct serial_s { + /* basic information */ + UARTName uart; + int index; + PinName pin_tx; + PinName pin_rx; + + /* configure information */ + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + + /* operating parameters */ + uint16_t rx_size; + uint8_t *tx_buffer_ptr; + uint8_t *rx_buffer_ptr; + __IO uint16_t tx_count; + __IO uint16_t rx_count; + + __IO uint32_t error_code; + __IO operation_state_enum tx_state; + __IO operation_state_enum rx_state; + +#if DEVICE_SERIAL_ASYNCH + uint32_t events; +#endif +#if DEVICE_SERIAL_FC + uint32_t hw_flow_ctl; + PinName pin_rts; + PinName pin_cts; +#endif +}; + +struct spi_s { + spi_parameter_struct spi_struct; + IRQn_Type spi_irq; + SPIName spi; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + /* basic information */ + I2CName i2c; + uint8_t index; + PinName sda; + PinName scl; + int i2c_inited; /* flag used to indicate whether the i2c has been initialized */ + + /* configure information */ + int freq; /* i2c frequence */ + uint32_t addr_bit_mode; /* 7 bits or 10 bits */ + uint32_t slave_addr0; + uint32_t slave_addr1; + uint16_t transfer_size; + uint8_t *buffer_pointer; + + /* operating parameters */ + __IO operation_state_enum state; + __IO i2c_mode_enum mode; + __IO uint32_t previous_state_mode; + __IO uint32_t i2c_target_dev_addr; + __IO uint32_t event_count; + __IO uint32_t transfer_count; + __IO uint32_t transfer_option; + __IO uint32_t error_code; + + /* I2C DMA information */ + uint32_t tx_dma_periph; + dma_channel_enum tx_dma_channel; + uint32_t rx_dma_periph; + dma_channel_enum rx_dma_channel; + + IRQn_Type event_i2cIRQ; + IRQn_Type error_i2cIRQ; + uint32_t global_trans_option; + volatile uint8_t event; + +#if DEVICE_I2CSLAVE + uint8_t slave; + volatile uint8_t pending_slave_tx_master_rx; + volatile uint8_t pending_slave_rx_maxter_tx; +#endif + +#if DEVICE_I2C_ASYNCH + uint32_t address; + uint8_t stop; + uint8_t available_events; +#endif + +}; +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/pinmap.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/pinmap.c new file mode 100644 index 0000000000..eeed668420 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/pinmap.c @@ -0,0 +1,135 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" +#include "mbed_error.h" + +extern uint32_t gpio_clock_enable(uint32_t port_idx); + +extern const int GD_GPIO_REMAP[]; +extern const int GD_GPIO_MODE[]; +extern const int GD_GPIO_SPEED[]; + +static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin); + +/** Configure pin (mode, speed, reamp function ) + * + * @param pin gpio pin name + * @param function gpio pin mode, speed, remap function + */ +void pin_function(PinName pin, int function) +{ + MBED_ASSERT(pin != (PinName)NC); + + uint32_t mode = GD_PIN_MODE_GET(function); + uint32_t remap = GD_PIN_REMAP_GET(function); + uint32_t speed = GD_PIN_SPEED_GET(function); + uint32_t port = GD_PORT_GET(pin); + uint32_t gd_pin = 1 << GD_PIN_GET(pin); + + uint32_t gpio = gpio_clock_enable(port); + gpio_para_init(gpio, GD_GPIO_MODE[mode], GD_GPIO_SPEED[speed], gd_pin); + + if (remap != 0) { + rcu_periph_clock_enable(RCU_AF); + gpio_pin_remap_config(GD_GPIO_REMAP[remap], ENABLE); + } +} + +/** Only configure pin mode + * + * @param pin gpio pin name + * @param function gpio pin mode + */ +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t port = GD_PORT_GET(pin); + uint32_t gd_pin = 1 << GD_PIN_GET(pin); + + uint32_t gpio = gpio_clock_enable(port); + if (mode != PullNone) { + gpio_mode_set(gpio, GD_GPIO_MODE[mode], gd_pin); + } +} + +/** configure gpio pin mode + * + * @param gpio_periph gpio port name + * @param mode gpio pin mode + * @param pin gpio pin number + */ +static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin) +{ + uint16_t i; + uint32_t temp_mode = 0U; + uint32_t reg = 0U; + + /* GPIO mode configuration */ + temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); + + /* configure the eight low port pins with GPIO_CTL0 */ + for (i = 0U; i < 8U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL0(gpio_periph); + + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } + } + /* configure the eight high port pins with GPIO_CTL1 */ + for (i = 8U; i < 16U; i++) { + if ((1U << i) & pin) { + reg = GPIO_CTL1(gpio_periph); + + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(i - 8U, temp_mode); + + /* set IPD or IPU */ + if (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (uint32_t)pin; + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } + } + + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } + } +} + + diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/port_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/port_api.c new file mode 100644 index 0000000000..75f959be15 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/port_api.c @@ -0,0 +1,120 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +extern uint32_t gpio_clock_enable(uint32_t port_idx); + +/** Get the pin name from the port's pin number + * + * @param port The port name + * @param pin_n The pin number within the specified port + * @return The pin name for the port's pin number + * BIT[7:4] port number + BIT[3:0] pin number + */ +PinName port_pin(PortName port, int pin_n) +{ + return (PinName)(pin_n + (port << 4)); +} + +/** Initilize the port + * + * @param obj The port object to initialize + * @param port The port name + * @param mask The bitmask to identify which bits in the port should be included (0 - ignore) + * @param dir The port direction + */ +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint32_t port_index = (uint32_t)port; + uint32_t gpio = gpio_clock_enable(port_index); + + obj->port = port; + obj->mask = mask; + obj->direction = dir; + obj->reg_in = &GPIO_ISTAT(gpio); + obj->reg_out = &GPIO_OCTL(gpio); + + port_dir(obj, dir); +} + +/** Set port direction (in/out) + * + * @param obj The port object + * @param dir The port direction to be set + */ +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + obj->direction = dir; + for (i = 0; i < 16; i++) { + if (obj->mask & (1 << i)) { + if (dir == PIN_OUTPUT) { + pin_function(port_pin(obj->port, i), MODE_OUT_PP); + } else { + pin_function(port_pin(obj->port, i), MODE_IN_FLOATING); + } + } + } +} + +/** Set the input port mode + * + * @param obj The port object + * @param mode THe port mode to be set + */ +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + for (i = 0; i < 16; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +/** Write value to the port + * + * @param obj The port object + * @param value The value to be set + */ +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +/** Read the current value on the port + * + * @param obj The port object + * @return An integer with each bit corresponding to an associated port pin setting + */ +int port_read(port_t *obj) +{ + if (obj->direction == PIN_OUTPUT) { + return (*obj->reg_out & obj->mask); + } else { + return (*obj->reg_in & obj->mask); + } +} + +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/pwmout_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/pwmout_api.c new file mode 100644 index 0000000000..af380c2974 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/pwmout_api.c @@ -0,0 +1,299 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +#define DEV_PWMOUT_APB_MASK 0x00010000U +#define DEV_PWMOUT_APB1 0U +#define DEV_PWMOUT_APB2 1U + +static uint32_t timer_get_clock(uint32_t timer_periph); + +static void dev_pwmout_init(pwmout_t *obj) +{ + timer_oc_parameter_struct timer_ocintpara; + timer_parameter_struct timer_initpara; + + MBED_ASSERT(obj); + uint32_t periph = obj->pwm; + + switch (periph) { + case TIMER0: + rcu_periph_clock_enable(RCU_TIMER0); + break; + + case TIMER1: + rcu_periph_clock_enable(RCU_TIMER1); + break; + + case TIMER2: + rcu_periph_clock_enable(RCU_TIMER2); + break; + + case TIMER3: + rcu_periph_clock_enable(RCU_TIMER3); + break; + + case TIMER4: + rcu_periph_clock_enable(RCU_TIMER4); + break; + + case TIMER7: + rcu_periph_clock_enable(RCU_TIMER7); + break; + case TIMER8: + rcu_periph_clock_enable(RCU_TIMER8); + break; + + case TIMER9: + rcu_periph_clock_enable(RCU_TIMER9); + break; + + case TIMER10: + rcu_periph_clock_enable(RCU_TIMER10); + break; + + case TIMER11: + rcu_periph_clock_enable(RCU_TIMER11); + break; + + case TIMER12: + rcu_periph_clock_enable(RCU_TIMER12); + break; + + case TIMER13: + rcu_periph_clock_enable(RCU_TIMER13); + break; + } + /* configure TIMER base function */ + timer_initpara.prescaler = 119; + timer_initpara.period = 9999; + timer_initpara.clockdivision = 0; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + + timer_init(obj->pwm, &timer_initpara); + + /* configure TIMER channel output function */ + timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_ocintpara.outputnstate = TIMER_CCXN_ENABLE; + timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_HIGH; + timer_channel_output_config(obj->pwm, obj->ch, &timer_ocintpara); + timer_channel_output_mode_config(obj->pwm, obj->ch, TIMER_OC_MODE_PWM0); + timer_channel_output_fast_config(obj->pwm, obj->ch, TIMER_OC_FAST_DISABLE); + + timer_primary_output_config(obj->pwm, ENABLE); +} + +static uint8_t dev_pwmout_apb_check(uint32_t periph) +{ + uint8_t reval = DEV_PWMOUT_APB1; + + /* check peripherals belongs to APB1 or APB2 */ + if (DEV_PWMOUT_APB_MASK == (periph & DEV_PWMOUT_APB_MASK)) { + reval = DEV_PWMOUT_APB2; + } + + return reval; +} + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + + obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(obj->pwm != (PWMName)NC); + + uint32_t function = pinmap_function(pin, PinMap_PWM); + MBED_ASSERT(function != (uint32_t)NC); + obj->ch = GD_PIN_CHANNEL_GET(function); + /* Peripheral initialization */ + dev_pwmout_init(obj); + /* pin function initialization */ + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t *obj) +{ + timer_channel_output_state_config(obj->pwm, obj->ch, TIMER_CCX_DISABLE); +} + +void pwmout_write(pwmout_t *obj, float value) +{ + uint16_t period; + uint16_t pulse; + + timer_disable(obj->pwm); + /* overflow protection */ + if (value < (float)0.0) { + value = 0.0; + } else if (value > (float)1.0) { + value = 1.0; + } + + period = TIMER_CAR(obj->pwm); + pulse = (uint16_t)(period * value); + + timer_channel_output_pulse_value_config(obj->pwm, obj->ch, pulse); + + timer_enable(obj->pwm); +} + +float pwmout_read(pwmout_t *obj) +{ + float value = 0; + uint16_t period; + uint16_t pulse; + + period = TIMER_CAR(obj->pwm); + + switch (obj->ch) { + case TIMER_CH_0: + pulse = TIMER_CH0CV(obj->pwm); + break; + + case TIMER_CH_1: + pulse = TIMER_CH1CV(obj->pwm); + break; + + case TIMER_CH_2: + pulse = TIMER_CH2CV(obj->pwm); + break; + + case TIMER_CH_3: + pulse = TIMER_CH3CV(obj->pwm); + break; + + default: + error("Error: pwm channel error! \r\n"); + } + + /* calculated waveform duty ratio */ + value = (float)(pulse) / (float)(period); + + if (value > (float)1.0) { + value = (float)1.0; + } + + return value; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +void pwmout_period_us(pwmout_t *obj, int us) +{ + + uint32_t ultemp = 0; + uint32_t timer_clk = 0; + uint32_t period = us - 1; + uint32_t prescaler; + float duty_ratio; + + duty_ratio = pwmout_read(obj); + + timer_disable(obj->pwm); + + timer_clk = timer_get_clock(obj->pwm); + + ultemp = (timer_clk / 1000000); + prescaler = ultemp; + obj->cnt_unit = 1; + + while (period > 0xFFFF) { + obj->cnt_unit = obj->cnt_unit << 1; + period = period >> 1; + prescaler = ultemp * obj->cnt_unit; + } + + if (prescaler > 0xFFFF) { + error("Error: TIMER prescaler value is overflow \r\n"); + } + + timer_autoreload_value_config(obj->pwm, period); + timer_prescaler_config(obj->pwm, prescaler - 1, TIMER_PSC_RELOAD_NOW); + + ultemp = duty_ratio * us; + + pwmout_pulsewidth_us(obj, ultemp); + + timer_enable(obj->pwm); +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + uint32_t pulse; + uint32_t period; + + period = TIMER_CAR(obj->pwm); + pulse = us / obj->cnt_unit; + + if (pulse > period) { + pulse = period; + } + + timer_channel_output_pulse_value_config(obj->pwm, obj->ch, pulse); +} + +static uint32_t timer_get_clock(uint32_t timer_periph) +{ + uint32_t timerclk; + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || (TIMER10 == timer_periph)) { + /* get the current APB2 TIMER clock source */ + if (RCU_APB2_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB2PSC)) { + timerclk = rcu_clock_freq_get(CK_APB2); + } else { + timerclk = rcu_clock_freq_get(CK_APB2) * 2; + } + } else { + /* get the current APB1 TIMER clock source */ + if (RCU_APB1_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB1PSC)) { + timerclk = rcu_clock_freq_get(CK_APB1); + } else { + timerclk = rcu_clock_freq_get(CK_APB1) * 2; + } + } + + return timerclk; +} diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/rtc_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/rtc_api.c new file mode 100644 index 0000000000..cd42dedcde --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/rtc_api.c @@ -0,0 +1,112 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_RTC + +#include "rtc_api.h" + +static uint8_t rtc_init_flag = 0; + +/** Initialize the RTC peripheral + * + * Powerup the RTC in perpetration for access. This function must be called + * before any other RTC functions ares called. This does not change the state + * of the RTC. It just enables access to it. + * + * @note This function is safe to call repeatedly - Tested by ::rtc_init_test + */ +void rtc_init(void) +{ + /* make sure RTC only init once */ + if (rtc_init_flag) { + return; + } + rtc_init_flag = 1; + + /* enable PMU and BKPI clocks */ + rcu_periph_clock_enable(RCU_BKPI); + rcu_periph_clock_enable(RCU_PMU); + /* allow access to BKP domain */ + pmu_backup_write_enable(); + /* enable LXTAL */ + rcu_osci_on(RCU_LXTAL); + /* wait till LXTAL is ready */ + rcu_osci_stab_wait(RCU_LXTAL); + /* select RCU_LXTAL as RTC clock source */ + rcu_rtc_clock_config(RCU_RTCSRC_LXTAL); + /* enable RTC Clock */ + rcu_periph_clock_enable(RCU_RTC); + /* wait for RTC registers synchronization */ + rtc_register_sync_wait(); + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); + /* set RTC prescaler: set RTC period to 1s */ + rtc_prescaler_set(32767); + /* wait until last write operation on RTC registers has finished */ + rtc_lwoff_wait(); +} + +/** Deinitialize RTC + * + * Powerdown the RTC in preparation for sleep, powerdown or reset. That should only + * affect the CPU domain and not the time keeping logic. + * After this function is called no other RTC functions should be called + * except for ::rtc_init. + */ +void rtc_free(void) +{ +} + +/** Check if the RTC has the time set and is counting + * + * @retval 0 The time reported by the RTC is not valid + * @retval 1 The time has been set the RTC is counting + */ +int rtc_isenabled(void) +{ + if (RESET == (RTC_CTL & RTC_CTL_RSYNF)) { + return 0; + } else { + return 1; + } +} + +/** Get the current time from the RTC peripheral + * + * @return The current time in seconds + * + * @note Some RTCs are not synchronized with the main clock. If + * this is the case with your RTC then you must read the RTC time + * in a loop to prevent reading the wrong time due to a glitch. + * The test ::rtc_glitch_test is intended to catch this bug. + */ +time_t rtc_read(void) +{ + return (rtc_counter_get()); +} + +/** Write the current time in seconds to the RTC peripheral + * + * @param t The current time to be set in seconds. + */ +void rtc_write(time_t t) +{ + rtc_counter_set((uint32_t)t); + rtc_lwoff_wait(); +} + +#endif /* DEVICE_RTC */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c new file mode 100644 index 0000000000..a8eea2f229 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c @@ -0,0 +1,1080 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include +#include "PeripheralPins.h" + +#define USART_NUM (5) + +static uint32_t serial_irq_ids[USART_NUM] = {0}; +static rcu_periph_enum usart_clk[USART_NUM] = {RCU_USART0, RCU_USART1, RCU_USART2, RCU_UART3, RCU_UART4}; +static IRQn_Type usart_irq_n[USART_NUM] = {USART0_IRQn, USART1_IRQn, USART2_IRQn, UART3_IRQn, UART4_IRQn}; + +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +#if DEVICE_SERIAL_ASYNCH +#define GET_SERIAL_S(obj) (&((obj)->serial)) +#else +#define GET_SERIAL_S(obj) (obj) +#endif /* DEVICE_SERIAL_ASYNCH */ + +/** Initialize the USART peripheral. + * + * @param obj_s The serial object + */ +static void usart_init(struct serial_s *obj_s) +{ + if (obj_s->index >= USART_NUM) { + return; + } + + /* USART configuration */ + usart_deinit(obj_s->uart); + usart_word_length_set(obj_s->uart, obj_s->databits); + usart_baudrate_set(obj_s->uart, obj_s->baudrate); + usart_stop_bit_set(obj_s->uart, obj_s->stopbits); + usart_parity_config(obj_s->uart, obj_s->parity); +#if DEVICE_SERIAL_FC + if (obj_s->hw_flow_ctl == USART_HWCONTROL_NONE) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_DISABLE); + } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_RTS) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_ENABLE); + } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_CTS) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_ENABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_DISABLE); + } else if (obj_s->hw_flow_ctl == USART_HWCONTROL_RTS_CTS) { + usart_hardware_flow_cts_config(obj_s->uart, USART_CTS_ENABLE); + usart_hardware_flow_rts_config(obj_s->uart, USART_RTS_ENABLE); + } +#endif /* DEVICE_SERIAL_FC */ + usart_receive_config(obj_s->uart, USART_RECEIVE_ENABLE); + usart_transmit_config(obj_s->uart, USART_TRANSMIT_ENABLE); + usart_enable(obj_s->uart); +} + +/** Initialize the serial peripheral. It sets the default parameters for serial + * peripheral, and configures its specifieds pins. + * + * @param obj The serial object + * @param tx The TX pin name + * @param rx The RX pin name + */ +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + + p_obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT(p_obj->uart != (UARTName)NC); + + /* enable UART peripheral clock */ + if (p_obj->uart == UART_0) { + p_obj->index = 0; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_1) { + p_obj->index = 1; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_2) { + p_obj->index = 2; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_3) { + p_obj->index = 3; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } else if (p_obj->uart == UART_4) { + p_obj->index = 4; + rcu_periph_clock_enable(usart_clk[p_obj->index]); + } + + /* configurte the pins */ + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + /* default UART parameters */ + p_obj->baudrate = 9600U; + p_obj->databits = USART_WL_8BIT; + p_obj->stopbits = USART_STB_1BIT; + p_obj->parity = USART_PM_NONE; + +#if DEVICE_SERIAL_FC + p_obj->hw_flow_ctl = USART_HWCONTROL_NONE; +#endif /* DEVICE_SERIAL_FC */ + + p_obj->pin_tx = tx; + p_obj->pin_rx = rx; + + p_obj->tx_state = OP_STATE_BUSY; + p_obj->rx_state = OP_STATE_BUSY; + + usart_init(p_obj); + + p_obj->tx_state = OP_STATE_READY; + p_obj->rx_state = OP_STATE_READY; + + if (p_obj->uart == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +/** Release the serial peripheral, not currently invoked. It requires further + * resource management. + * + * @param obj The serial object + */ +void serial_free(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + rcu_periph_enum rcu_periph = usart_clk[p_obj->index]; + + /* reset USART and disable clock */ + usart_deinit(p_obj->uart); + rcu_periph_clock_disable(rcu_periph); + + serial_irq_ids[p_obj->index] = 0; + + /* reset the GPIO state */ + pin_function(p_obj->pin_tx, MODE_IN_FLOATING); + pin_function(p_obj->pin_rx, MODE_IN_FLOATING); +} + +/** Configure the baud rate + * + * @param obj The serial object + * @param baudrate The baud rate to be configured + */ +void serial_baud(serial_t *obj, int baudrate) +{ + uint16_t uen_flag = 0U; + struct serial_s *p_obj = GET_SERIAL_S(obj); + + /* store the UEN flag */ + uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; + + /* disable the USART clock first */ + usart_disable(p_obj->uart); + + usart_baudrate_set(p_obj->uart, baudrate); + + p_obj->baudrate = baudrate; + + /* restore the UEN flag */ + if (RESET != uen_flag) { + usart_enable(p_obj->uart); + } +} + +/** Configure the format. Set the number of bits, parity and the number of stop bits + * + * @param obj The serial object + * @param data_bits The number of data bits + * @param parity The parity + * @param stop_bits The number of stop bits + */ +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint16_t uen_flag = 0U; + struct serial_s *p_obj = GET_SERIAL_S(obj); + + /* store the UEN flag */ + uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; + + /* disable the UART clock first */ + usart_disable(p_obj->uart); + + /* configurate the UART parity */ + switch (parity) { + case ParityOdd: + p_obj->parity = USART_PM_ODD; + usart_parity_config(p_obj->uart, USART_PM_ODD); + break; + + case ParityEven: + p_obj->parity = USART_PM_EVEN; + usart_parity_config(p_obj->uart, USART_PM_EVEN); + break; + + case ParityForced0: + case ParityForced1: + default: + p_obj->parity = USART_PM_NONE; + usart_parity_config(p_obj->uart, USART_PM_NONE); + break; + } + + if (p_obj->parity == USART_PM_NONE) { + if (data_bits == 9) { + usart_word_length_set(p_obj->uart, USART_WL_9BIT); + } else if (data_bits == 8) { + usart_word_length_set(p_obj->uart, USART_WL_8BIT); + } else if (data_bits == 7) { + return; + } + } else { + if (data_bits == 9) { + return; + } else if (data_bits == 8) { + usart_word_length_set(p_obj->uart, USART_WL_9BIT); + } else if (data_bits == 7) { + usart_word_length_set(p_obj->uart, USART_WL_8BIT); + } + } + + if (stop_bits == 2) { + usart_stop_bit_set(p_obj->uart, USART_STB_2BIT); + } else { + usart_stop_bit_set(p_obj->uart, USART_STB_1BIT); + } + + /* restore the UEN flag */ + if (RESET != uen_flag) { + usart_enable(p_obj->uart); + } +} + +/** The serial interrupt handler registration + * + * @param obj The serial object + * @param handler The interrupt handler which will be invoked when the interrupt fires + * @param id The SerialBase object + */ +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + irq_handler = handler; + serial_irq_ids[p_obj->index] = id; +} + +/** This function handles USART interrupt handler + * + * @param usart_index The index of UART + * @param usart_periph The UART peripheral + */ +static void usart_irq(int usart_index, uint32_t usart_periph) +{ + if (serial_irq_ids[usart_index] != 0) { + if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_TC) != RESET) { + usart_interrupt_flag_clear(usart_periph, USART_FLAG_TC); + irq_handler(serial_irq_ids[usart_index], TxIrq); + } + + if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_RBNE) != RESET) { + usart_interrupt_flag_clear(usart_periph, USART_FLAG_RBNE); + irq_handler(serial_irq_ids[usart_index], RxIrq); + } + + if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_ERR_ORERR) != RESET) { + usart_interrupt_flag_clear(usart_periph, USART_FLAG_ORERR); + } + } +} + +/** This function handles USART0 interrupt handler + * + */ +static void usart0_irq(void) +{ + usart_irq(0, USART0); +} + +/** This function handles USART1 interrupt handler + * + */ +static void usart1_irq(void) +{ + usart_irq(1, USART1); +} + +/** This function handles USART2 interrupt handler + * + */ +static void usart2_irq(void) +{ + usart_irq(2, USART2); +} + +/** This function handles USART3 interrupt handler + * + */ +static void uart3_irq(void) +{ + usart_irq(3, UART3); +} + +/** This function handles USART4 interrupt handler + * + */ +static void uart4_irq(void) +{ + usart_irq(4, UART4); +} + +/** Configure serial interrupt. This function is used for word-approach + * + * @param obj The serial object + * @param irq The serial IRQ type (RX or TX) + * @param enable Set to non-zero to enable events, or zero to disable them + */ +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + + if (p_obj->uart == USART0) { + irq_n = USART0_IRQn; + vector = (uint32_t)&usart0_irq; + } else if (p_obj->uart == USART1) { + irq_n = USART1_IRQn; + vector = (uint32_t)&usart1_irq; + } else if (p_obj->uart == USART2) { + irq_n = USART2_IRQn; + vector = (uint32_t)&usart2_irq; + } else if (p_obj->uart == UART3) { + irq_n = UART3_IRQn; + vector = (uint32_t)&uart3_irq; + } else if (p_obj->uart == UART4) { + irq_n = UART4_IRQn; + vector = (uint32_t)&uart4_irq; + } + + if (enable) { + if (irq == RxIrq) { + /* Rx IRQ */ + usart_interrupt_enable(p_obj->uart, USART_INT_RBNE); + } else { + /* Tx IRQ */ + usart_interrupt_enable(p_obj->uart, USART_INT_TBE); + } + + NVIC_SetVector(irq_n, vector); + NVIC_EnableIRQ(irq_n); + } else { + if (irq == RxIrq) { + /* Rx IRQ */ + usart_interrupt_disable(p_obj->uart, USART_INT_RBNE); + } else { + /* Tx IRQ */ + usart_interrupt_disable(p_obj->uart, USART_INT_TBE); + } + } +} + +/** Get character. This is a blocking call, waiting for a character + * + * @param obj The serial object + */ +int serial_getc(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + while (!serial_readable(obj)); + return (int)(usart_data_receive(p_obj->uart) & BITS(0, 7 + (p_obj->databits >> 12))); +} + +/** Send a character. This is a blocking call, waiting for a peripheral to be available + * for writing + * + * @param obj The serial object + * @param c The character to be sent + */ +void serial_putc(serial_t *obj, int c) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + while (!serial_writable(obj)); + usart_data_transmit(p_obj->uart, (int)((c) & BITS(0, 7 + (p_obj->databits >> 12)))); +} + +/** Check if the serial peripheral is readable + * + * @param obj The serial object + * @return Non-zero value if a character can be read, 0 if nothing to read + */ +int serial_readable(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return (usart_flag_get(p_obj->uart, USART_FLAG_RBNE) != RESET) ? 1 : 0; +} + +/** Check if the serial peripheral is writable + * + * @param obj The serial object + * @return Non-zero value if a character can be written, 0 otherwise. + */ +int serial_writable(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return (usart_flag_get(p_obj->uart, USART_FLAG_TBE) != RESET) ? 1 : 0; +} + +/** Clear the serial peripheral + * + * @param obj The serial object + */ +void serial_clear(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + p_obj->tx_count = 0U; + p_obj->rx_count = 0U; +} + +/** Set the break + * + * @param obj The serial object + */ +void serial_break_set(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + usart_send_break(p_obj->uart); +} + +/** Clear the break + * + * @param obj The serial object + */ +void serial_break_clear(serial_t *obj) +{ + /* do nothing */ +} + +/** Configure the TX pin for UART function. + * + * @param tx The pin name used for TX + */ +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +#if DEVICE_SERIAL_ASYNCH +/** + * Enable the serial events + * + * @param obj The serial object + * @param event The events to be configured + */ +static void serial_event_enable(serial_t *obj, int event) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + p_obj->events |= event; + +} + +/** + * Disable the serial events + * + * @param obj The serial object + * @param event The events to be configured + */ +static void serial_event_disable(serial_t *obj, int event) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + p_obj->events &= ~event; +} + +/** + * Preprocess the USART tx interrupt + * + * @param obj_s The serial object + * @param pData Pointer to tx buffer + * @param Size Size of tx buffer + * @return Returns the status + */ +gd_status_enum usart_tx_interrupt_preprocess(struct serial_s *obj_s, uint8_t *pData, uint16_t Size) +{ + if (obj_s->tx_state == OP_STATE_READY) { + if ((pData == NULL) || (Size == 0U)) { + return GD_ERROR; + } + + obj_s->tx_buffer_ptr = pData; + obj_s->tx_count = Size; + obj_s->error_code = USART_ERROR_CODE_NONE; + obj_s->tx_state = OP_STATE_BUSY_TX; + + usart_interrupt_enable(obj_s->uart, USART_INT_TBE); + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** + * Preprocess the USART rx interrupt + * + * @param obj_s The serial object + * @param pData Pointer to rx buffer + * @param Size Size of rx buffer + * @return Returns the status + */ +gd_status_enum usart_rx_interrupt_preprocess(struct serial_s *obj_s, uint8_t *pData, uint16_t Size) +{ + if (obj_s->rx_state == OP_STATE_READY) { + if ((pData == NULL) || (Size == 0U)) { + return GD_ERROR; + } + + obj_s->rx_buffer_ptr = pData; + obj_s->rx_size = Size; + obj_s->rx_count = Size; + obj_s->error_code = USART_ERROR_CODE_NONE; + obj_s->rx_state = OP_STATE_BUSY_RX; + + usart_interrupt_enable(obj_s->uart, USART_INT_PERR); + usart_interrupt_enable(obj_s->uart, USART_INT_ERR); + usart_interrupt_enable(obj_s->uart, USART_INT_RBNE); + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** Begin asynchronous TX transfer. The used buffer is specified in the serial object, + * tx_buff + * + * @param obj The serial object + * @param tx The transmit buffer + * @param tx_length The number of bytes to transmit + * @param tx_width Deprecated argument + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param hint A suggestion for how to use DMA with this transfer + * @return Returns number of data transfered, otherwise returns 0 + */ +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + IRQn_Type irq = usart_irq_n[p_obj->index]; + + if ((tx_length == 0) || (tx_width != 8)) { + return 0; + } + + if (serial_tx_active(obj)) { + /* some transmit is in progress */ + return 0; + } + + obj->tx_buff.buffer = (void *)tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + + /* disable all events first */ + serial_event_disable(obj, SERIAL_EVENT_TX_ALL); + /* enable the specific event */ + serial_event_enable(obj, event); + + /* enable interrupt */ + /* clear pending IRQ */ + NVIC_ClearPendingIRQ(irq); + /* disable the IRQ first */ + NVIC_DisableIRQ(irq); + /* set the priority and vector */ + NVIC_SetPriority(irq, 1); + NVIC_SetVector(irq, (uint32_t)handler); + /* enable IRQ */ + NVIC_EnableIRQ(irq); + + if (usart_tx_interrupt_preprocess(p_obj, (uint8_t *)tx, tx_length) != GD_OK) { + return 0; + } + + return tx_length; +} + +/** Begin asynchronous RX transfer (enable interrupt for data collecting) + * The used buffer is specified in the serial object - rx_buff + * + * @param obj The serial object + * @param rx The receive buffer + * @param rx_length The number of bytes to receive + * @param rx_width Deprecated argument + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param handler The serial handler + * @param char_match A character in range 0-254 to be matched + * @param hint A suggestion for how to use DMA with this transfer + */ +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + IRQn_Type irq = usart_irq_n[p_obj->index]; + + if ((rx_length == 0) || (rx_width != 8)) { + return; + } + + /* disable all events first */ + serial_event_disable(obj, SERIAL_EVENT_RX_ALL); + /* enable the specific event */ + serial_event_enable(obj, event); + + obj->char_match = char_match; + + if (serial_rx_active(obj)) { + /* some reception is in progress */ + return; + } + + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + + /* enable interrupt */ + /* clear pending IRQ */ + NVIC_ClearPendingIRQ(irq); + /* disable the IRQ first */ + NVIC_DisableIRQ(irq); + /* set the priority(higher than Tx) and vector */ + NVIC_SetPriority(irq, 0); + NVIC_SetVector(irq, (uint32_t)handler); + /* enable IRQ */ + NVIC_EnableIRQ(irq); + + usart_rx_interrupt_preprocess(p_obj, (uint8_t *)rx, rx_length); +} + +/** Attempts to determine if the serial peripheral is already in use for TX + * + * @param obj The serial object + * @return Non-zero if the RX transaction is ongoing, 0 otherwise + */ +uint8_t serial_tx_active(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return ((p_obj->tx_state == OP_STATE_BUSY_TX) ? 1 : 0); +} + +/** Attempts to determine if the serial peripheral is already in use for RX + * + * @param obj The serial object + * @return Non-zero if the RX transaction is ongoing, 0 otherwise + */ +uint8_t serial_rx_active(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + return ((p_obj->rx_state == OP_STATE_BUSY_RX) ? 1 : 0); +} + +/** Handle the serial rx interrupt + * + * @param obj_s The serial object + * @return Returns the status + */ +static gd_status_enum usart_rx_interrupt(struct serial_s *obj_s) +{ + uint16_t *temp; + + if (obj_s->rx_state == OP_STATE_BUSY_RX) { + if (obj_s->databits == USART_WL_9BIT) { + temp = (uint16_t *) obj_s->rx_buffer_ptr; + if (obj_s->parity == USART_PM_NONE) { + /* 9-bit data, none parity bit */ + *temp = (uint16_t)(USART_DATA(obj_s->uart) & (uint16_t)0x01FF); + obj_s->rx_buffer_ptr += 2U; + } else { + /* 9-bit data, with parity bit */ + *temp = (uint16_t)(USART_DATA(obj_s->uart) & (uint16_t)0x00FF); + obj_s->rx_buffer_ptr += 1U; + } + } else { + if (obj_s->parity == USART_PM_NONE) { + /* 8-bit data, none parity bit */ + *obj_s->rx_buffer_ptr++ = (uint8_t)(USART_DATA(obj_s->uart) & (uint8_t)0x00FF); + } else { + /* 8-bit data, with parity bit */ + *obj_s->rx_buffer_ptr++ = (uint8_t)(USART_DATA(obj_s->uart) & (uint8_t)0x007F); + } + } + + if (--obj_s->rx_count == 0U) { + usart_interrupt_disable(obj_s->uart, USART_INT_RBNE); + usart_interrupt_disable(obj_s->uart, USART_INT_PERR); + usart_interrupt_disable(obj_s->uart, USART_INT_ERR); + + obj_s->rx_state = OP_STATE_READY; + } + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** Handle the serial tx interrupt + * + * @param obj_s The serial object + * @return Returns the status + */ +static gd_status_enum usart_tx_interrupt(struct serial_s *obj_s) +{ + uint16_t *temp; + + if (obj_s->tx_state == OP_STATE_BUSY_TX) { + if (obj_s->databits == USART_WL_9BIT) { + temp = (uint16_t *) obj_s->tx_buffer_ptr; + USART_DATA(obj_s->uart) = (uint16_t)(*temp & (uint16_t)0x01FF); + if (obj_s->parity == USART_PM_NONE) { + obj_s->tx_buffer_ptr += 2U; + } else { + obj_s->tx_buffer_ptr += 1U; + } + } else { + USART_DATA(obj_s->uart) = (uint8_t)(*obj_s->tx_buffer_ptr++ & (uint8_t)0x00FF); + } + + if (--obj_s->tx_count == 0U) { + /* disable USART_INT_TBE interrupt */ + usart_interrupt_disable(obj_s->uart, USART_INT_TBE); + + /* enable USART_INT_TC interrupt */ + usart_interrupt_enable(obj_s->uart, USART_INT_TC); + } + + return GD_OK; + } else { + return GD_BUSY; + } +} + +/** Handle the serial tx complete interrupt + * + * @param obj_s The serial object + */ +void usart_tx_complete_interrupt(struct serial_s *obj_s) +{ + usart_interrupt_disable(obj_s->uart, USART_INT_TC); + + obj_s->tx_state = OP_STATE_READY; +} + +/** Handle all the serial interrupt request + * + * @param obj_s The serial object + */ +void usart_irq_handler(struct serial_s *obj_s) +{ + uint32_t err_flags = 0U; + + /* no error occurs */ + err_flags = (USART_STAT0(obj_s->uart) & (uint32_t)(USART_FLAG_PERR | USART_FLAG_FERR | USART_FLAG_ORERR | USART_FLAG_NERR)); + if (err_flags == RESET) { + /* check whether USART is in receiver mode or not */ + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_RBNE) != RESET) { + usart_rx_interrupt(obj_s); + + return; + } + } + + /* some errors occur */ + if ((err_flags != RESET) && + (((USART_CTL2(obj_s->uart) & USART_INT_ERR) != RESET) || + ((USART_CTL0(obj_s->uart) & (USART_INT_RBNE | USART_INT_PERR)) != RESET))) { + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_PERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_PERR; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_ERR_NERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_NERR; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_ERR_FERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_FERR; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_ERR_ORERR) != RESET) { + obj_s->error_code |= USART_ERROR_CODE_ORERR; + } + + if (obj_s->error_code != USART_ERROR_CODE_NONE) { + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_RBNE) != RESET) { + usart_rx_interrupt(obj_s); + } + } + + return; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_TBE) != RESET) { + usart_tx_interrupt(obj_s); + return; + } + + if (usart_interrupt_flag_get(obj_s->uart, USART_INT_FLAG_TC) != RESET) { + usart_tx_complete_interrupt(obj_s); + return; + } +} + +/** The asynchronous TX and RX handler. + * + * @param obj The serial object + * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0 + */ +int serial_irq_handler_asynch(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + volatile uint8_t i = 0; + volatile int return_val = 0; + uint8_t *p_buf = (uint8_t *)(obj->rx_buff.buffer); + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_PERR) != RESET) { + usart_interrupt_flag_clear(p_obj->uart, USART_INT_FLAG_PERR); + return_val |= (SERIAL_EVENT_RX_PARITY_ERROR & p_obj->events); + p_obj->error_code |= USART_ERROR_CODE_PERR; + } + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_ERR_FERR) != RESET) { + usart_interrupt_flag_clear(p_obj->uart, USART_INT_FLAG_ERR_FERR); + return_val |= (SERIAL_EVENT_RX_FRAMING_ERROR & p_obj->events); + p_obj->error_code |= USART_ERROR_CODE_FERR; + } + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_ERR_ORERR) != RESET) { + usart_interrupt_flag_clear(p_obj->uart, USART_INT_FLAG_ERR_ORERR); + return_val |= (SERIAL_EVENT_RX_OVERRUN_ERROR & p_obj->events); + p_obj->error_code |= USART_ERROR_CODE_ORERR; + } + + if (return_val & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR | + SERIAL_EVENT_RX_OVERRUN_ERROR)) { + return return_val; + } + + if (usart_interrupt_flag_get(p_obj->uart, USART_INT_FLAG_TC) != RESET) { + if ((p_obj->events & SERIAL_EVENT_TX_COMPLETE) != 0) { + return_val |= (SERIAL_EVENT_TX_COMPLETE & p_obj->events); + } + } + + usart_irq_handler(p_obj); + + if (p_obj->rx_size != 0) { + obj->rx_buff.pos = p_obj->rx_size - p_obj->rx_count; + } + + if ((p_obj->rx_count == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { + return_val |= (SERIAL_EVENT_RX_COMPLETE & p_obj->events); + } + + if (p_obj->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { + if (p_buf != NULL) { + for (i = 0; i < obj->rx_buff.pos; i++) { + if (p_buf[i] == obj->char_match) { + obj->rx_buff.pos = i; + return_val |= (SERIAL_EVENT_RX_CHARACTER_MATCH & p_obj->events); + serial_rx_abort_asynch(obj); + break; + } + } + } + } + + return return_val; +} + +/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and + * flushes the TX hardware buffer if TX FIFO is used + * + * @param obj The serial object + */ +void serial_tx_abort_asynch(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + usart_interrupt_disable(p_obj->uart, USART_INT_TC); + usart_interrupt_disable(p_obj->uart, USART_INT_TBE); + + usart_flag_clear(p_obj->uart, USART_FLAG_TC); + + p_obj->tx_count = 0; + p_obj->tx_state = OP_STATE_READY; +} + +/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and + * flushes the RX hardware buffer if RX FIFO is used + * + * @param obj The serial object + */ +void serial_rx_abort_asynch(serial_t *obj) +{ + struct serial_s *p_obj = GET_SERIAL_S(obj); + + /* disable interrupts */ + usart_interrupt_disable(p_obj->uart, USART_INT_RBNE); + usart_interrupt_disable(p_obj->uart, USART_INT_PERR); + usart_interrupt_disable(p_obj->uart, USART_INT_ERR); + + /* clear USART_FLAG_RBNE flag */ + usart_flag_clear(p_obj->uart, USART_FLAG_RBNE); + + /* clear errors flag */ + usart_flag_clear(p_obj->uart, USART_FLAG_PERR); + usart_flag_clear(p_obj->uart, USART_FLAG_FERR); + usart_flag_clear(p_obj->uart, USART_FLAG_ORERR); + /* clear RBNE flag */ + USART_DATA(p_obj->uart); + + /* reset rx transfer count */ + p_obj->rx_count = 0; + + /* reset rx state */ + p_obj->rx_state = OP_STATE_READY; +} + +#endif /* DEVICE_SERIAL_ASYNCH */ + +#if DEVICE_SERIAL_FC +/** Configure the serial for the flow control. It sets flow control in the hardware + * if a serial peripheral supports it, otherwise software emulation is used. + * + * @param obj The serial object + * @param type The type of the flow control. Look at the available FlowControl types. + * @param rxflow The TX pin name + * @param txflow The RX pin name + */ +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + uint16_t uen_flag = 0U; + struct serial_s *p_obj = GET_SERIAL_S(obj); + /* store the UEN flag */ + uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; + + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + + p_obj->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); + MBED_ASSERT(p_obj->uart != (UARTName)NC); + + /* disable USART to modify CTS/RTS configuration */ + usart_disable(p_obj->uart); + + if (type == FlowControlNone) { + p_obj->hw_flow_ctl = USART_HWCONTROL_NONE; + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); + } + + if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName)NC); + p_obj->hw_flow_ctl = USART_HWCONTROL_RTS; + p_obj->pin_rts = rxflow; + pinmap_pinout(rxflow, PinMap_UART_RTS); + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); + } + + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName)NC); + p_obj->hw_flow_ctl = USART_HWCONTROL_CTS; + p_obj->pin_cts = txflow; + pinmap_pinout(txflow, PinMap_UART_CTS); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); + } + + if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_rts != (UARTName)NC); + MBED_ASSERT(uart_cts != (UARTName)NC); + p_obj->hw_flow_ctl = USART_HWCONTROL_RTS_CTS; + p_obj->pin_rts = rxflow; + p_obj->pin_cts = txflow; + pinmap_pinout(txflow, PinMap_UART_CTS); + pinmap_pinout(rxflow, PinMap_UART_RTS); + usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); + usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); + } + + /* restore the UEN flag */ + if (RESET != uen_flag) { + usart_enable(p_obj->uart); + } +} + +#endif /* DEVICE_SERIAL_FC */ + +#if DEVICE_SLEEP +/** Check whether the serial is in busy state + * + * @return 0: all the serial is free to use, 1: some serial is in busy in transfer + */ +int serial_busy_state_check(void) +{ +#if defined(USART0) + if ((USART_CTL0(USART0) & USART_CTL0_UEN) && !(USART_STAT0(USART0) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(USART1) + if ((USART_CTL0(USART1) & USART_CTL0_UEN) && !(USART_STAT0(USART1) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(USART2) + if ((USART_CTL0(USART2) & USART_CTL0_UEN) && !(USART_STAT0(USART2) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(UART3) + if ((USART_CTL0(UART3) & USART_CTL0_UEN) && !(USART_STAT0(UART3) & USART_STAT0_TC)) { + return 1; + } +#endif + +#if defined(UART4) + if ((USART_CTL0(UART4) & USART_CTL0_UEN) && !(USART_STAT0(UART4) & USART_STAT0_TC)) { + return 1; + } +#endif + + /* no serial is in busy state */ + return 0; +} +#endif /* DEVICE_SLEEP */ + +#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/sleep.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/sleep.c new file mode 100644 index 0000000000..05a0c97f3b --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/sleep.c @@ -0,0 +1,177 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_SLEEP + +#include "sleep_api.h" +#include "us_ticker_api.h" +#include "mbed_critical.h" +#include "mbed_error.h" + +extern void ticker_timer_data_save(void); +extern void ticker_timer_data_restore(void); +extern int serial_busy_state_check(void); + +/*! + \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_120m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while (1) { + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/1 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + +#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) + /* select HXTAL/2 as clock source */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); + + /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= RCU_PLL_MUL30; + +#elif defined(GD32F30X_CL) + /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); + + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); + RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); + + /* enable PLL1 */ + RCU_CTL |= RCU_CTL_PLL1EN; + /* wait till PLL1 is ready */ + while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) { + } +#endif /* GD32F30X_HD and GD32F30X_XD */ + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { + } + + /* enable the high-drive to extend the clock frequency to 120 MHz */ + PMU_CTL |= PMU_CTL_HDEN; + while (0U == (PMU_CS & PMU_CS_HDRF)) { + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while (0U == (PMU_CS & PMU_CS_HDSRF)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + + +/** Send the microcontroller to sleep + * + * The processor is setup ready for sleep, and sent to sleep. In this mode, the + * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates + * dynamic power used by the processor, memory systems and buses. The processor, peripheral and + * memory state are maintained, and the peripherals continue to work and can generate interrupts. + * + * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. + * + * The wake-up time shall be less than 10 us. + * + */ +void hal_sleep(void) +{ + /* Disable Interrupts */ + core_util_critical_section_enter(); + + /* Enter SLEEP mode */ + pmu_to_sleepmode(WFI_CMD); + + /* Enable Interrupts */ + core_util_critical_section_exit(); +} + + +/** Send the microcontroller to deep sleep + * + * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode + * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks. + * All state is still maintained. + * + * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer. + * + * The wake-up time shall be less than 10 ms. + */ +void hal_deepsleep(void) +{ + if (0 != serial_busy_state_check()) { + return; + } + + /* Disable Interrupts */ + core_util_critical_section_enter(); + + ticker_timer_data_save(); + + /* Enter DEEP SLEEP mode */ + rcu_periph_clock_enable(RCU_PMU); + pmu_to_deepsleepmode(PMU_LDO_NORMAL, WFI_CMD); + + /* Reconfigure the PLL after weak up */ + system_clock_120m_hxtal(); + + ticker_timer_data_restore(); + + /* Enable Interrupts */ + core_util_critical_section_exit(); +} + +#endif /* DEVICE_SLEEP */ diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/spi_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/spi_api.c new file mode 100644 index 0000000000..469d2376aa --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/spi_api.c @@ -0,0 +1,374 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "spi_api.h" + +#if DEVICE_SPI +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#define SPI_S(obj) (( struct spi_s *)(obj)) + +/** Get the frequency of SPI clock source + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] spi_freq The SPI clock source freguency + * @param[in] obj The SPI object + */ +static int dev_spi_clock_source_frequency_get(spi_t *obj) +{ + int spi_freq = 0; + struct spi_s *spiobj = SPI_S(obj); + + switch ((int)spiobj->spi) { + case SPI0: + /* clock source is APB2 */ + spi_freq = rcu_clock_freq_get(CK_APB2); + break; + case SPI1: + /* clock source is APB1 */ + spi_freq = rcu_clock_freq_get(CK_APB1); + break; + case SPI2: + /* clock source is APB1 */ + spi_freq = rcu_clock_freq_get(CK_APB1); + break; + default: + error("SPI clock source frequency get error"); + break; + } + return spi_freq; +} + +/** Initialize the SPI structure + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + */ +static void dev_spi_struct_init(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + + spi_disable(spiobj->spi); + spi_para_init(spiobj->spi, &obj->spi_struct); + spi_enable(spiobj->spi); +} + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + * @param[in] mosi The pin to use for MOSI + * @param[in] miso The pin to use for MISO + * @param[in] sclk The pin to use for SCLK + * @param[in] ssel The pin to use for SSEL + */ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + struct spi_s *spiobj = SPI_S(obj); + + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + /* return SPIName according to PinName */ + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT(spiobj->spi != (SPIName)NC); + + /* Set iqr type */ + if (spiobj->spi == SPI0) { + rcu_periph_clock_enable(RCU_SPI0); + spiobj->spi_irq = SPI0_IRQn; + } + if (spiobj->spi == SPI1) { + rcu_periph_clock_enable(RCU_SPI1); + spiobj->spi_irq = SPI1_IRQn; + } + if (spiobj->spi == SPI2) { + rcu_periph_clock_enable(RCU_SPI2); + spiobj->spi_irq = SPI2_IRQn; + } + + /* config GPIO mode of SPI pins */ + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + spiobj->pin_miso = miso; + spiobj->pin_mosi = mosi; + spiobj->pin_sclk = sclk; + spiobj->pin_ssel = ssel; + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + spiobj->spi_struct.nss = SPI_NSS_HARD; + } else { + spiobj->spi_struct.nss = SPI_NSS_SOFT; + } + + /* Default values */ + spiobj->spi_struct.device_mode = SPI_MASTER; + spiobj->spi_struct.prescale = SPI_PSC_256; + spiobj->spi_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spiobj->spi_struct.frame_size = SPI_FRAMESIZE_8BIT; + spiobj->spi_struct.endian = SPI_ENDIAN_MSB; + + dev_spi_struct_init(obj); +} + +/** Release a SPI object + * + * TODO: spi_free is currently unimplemented + * This will require reference counting at the C++ level to be safe + * + * Return the pins owned by the SPI object to their reset state + * Disable the SPI peripheral + * Disable the SPI clock + * @param[in] obj The SPI object to deinitialize + */ +void spi_free(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_disable(spiobj->spi); + + /* Disable and deinit SPI */ + if (spiobj->spi == SPI0) { + spi_i2s_deinit(SPI0); + rcu_periph_clock_disable(RCU_SPI0); + } + if (spiobj->spi == SPI1) { + spi_i2s_deinit(SPI1); + rcu_periph_clock_disable(RCU_SPI1); + } + if (spiobj->spi == SPI2) { + spi_i2s_deinit(SPI2); + rcu_periph_clock_disable(RCU_SPI2); + } + /* Deinit GPIO mode of SPI pins */ + pin_function(spiobj->pin_miso, MODE_IN_FLOATING); + pin_function(spiobj->pin_mosi, MODE_IN_FLOATING); + pin_function(spiobj->pin_sclk, MODE_IN_FLOATING); + if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { + pin_function(spiobj->pin_ssel, MODE_IN_FLOATING); + } +} + +/** Configure the SPI format + * + * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. + * The default bit order is MSB. + * @param[in,out] obj The SPI object to configure + * @param[in] bits The number of bits per frame + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] slave Zero for master mode or non-zero for slave mode + */ +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + struct spi_s *spiobj = SPI_S(obj); + + spiobj->spi_struct.frame_size = (bits == 16) ? SPI_FRAMESIZE_16BIT : SPI_FRAMESIZE_8BIT; + /* Config polarity and phase of SPI */ + switch (mode) { + case 0: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + break; + case 1: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; + break; + case 2: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; + break; + default: + spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; + + break; + } + + if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { + spiobj->spi_struct.nss = SPI_NSS_HARD; + spi_nss_output_enable(spiobj->spi); + } + /* Select SPI as master or slave */ + spiobj->spi_struct.device_mode = (slave) ? SPI_SLAVE : SPI_MASTER; + + dev_spi_struct_init(obj); +} + +static const uint16_t baudrate_prescaler_table[] = {SPI_PSC_2, + SPI_PSC_4, + SPI_PSC_8, + SPI_PSC_16, + SPI_PSC_32, + SPI_PSC_64, + SPI_PSC_128, + SPI_PSC_256 + }; + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + */ +void spi_frequency(spi_t *obj, int hz) +{ + struct spi_s *spiobj = SPI_S(obj); + int spi_hz = 0; + uint8_t prescaler_rank = 0; + uint8_t last_index = (sizeof(baudrate_prescaler_table) / sizeof(baudrate_prescaler_table[0])) - 1; + + spi_hz = dev_spi_clock_source_frequency_get(obj) / 2; + + /* Config SPI prescaler according to input frequency*/ + while ((spi_hz > hz) && (prescaler_rank < last_index)) { + spi_hz = spi_hz / 2; + prescaler_rank++; + } + + spiobj->spi_struct.prescale = baudrate_prescaler_table[prescaler_rank]; + dev_spi_struct_init(obj); +} + +/** Write a block out in master mode and receive a value + * + * The total number of bytes sent and received will be the maximum of + * tx_length and rx_length. The bytes written will be padded with the + * value 0xff. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx_buffer Pointer to the byte-array of data to write to the device + * @param[in] tx_length Number of bytes to write, may be zero + * @param[in] rx_buffer Pointer to the byte-array of data to read from the device + * @param[in] rx_length Number of bytes to read, may be zero + * @param[in] write_fill Default data transmitted while performing a read + * @returns + * The number of bytes written and read from the device. This is + * maximum of tx_length and rx_length. + */ +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +/** Write a byte out in master mode and receive a value + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return Returns the value received during send + */ +int spi_master_write(spi_t *obj, int value) +{ + int count = 0; + struct spi_s *spiobj = SPI_S(obj); + + /* wait the SPI transmit buffer is empty */ + while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)) && (count++ < 1000)); + if (count >= 1000) { + return -1; + } else { + spi_i2s_data_transmit(spiobj->spi, value); + } + + count = 0; + /* wait the SPI receive buffer is not empty */ + while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); + if (count >= 1000) { + return -1; + } else { + return spi_i2s_data_receive(spiobj->spi); + } +} + +/** Check if a value is available to read + * + * @param[in] obj The SPI peripheral to check + * @return non-zero if a value is available + */ +int spi_slave_receive(spi_t *obj) +{ + int status; + struct spi_s *spiobj = SPI_S(obj); + /* check whether or not the SPI receive buffer is empty */ + status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE) != RESET) ? 1 : 0); + return status; +} + +/** Get a received value out of the SPI receive buffer in slave mode + * + * Blocks until a value is available + * @param[in] obj The SPI peripheral to read + * @return The value received + */ +int spi_slave_read(spi_t *obj) +{ + int count = 0; + struct spi_s *spiobj = SPI_S(obj); + /* wait the SPI receive buffer is not empty */ + while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); + if (count >= 1000) { + return -1; + } else { + return spi_i2s_data_receive(spiobj->spi); + } +} + +/** Write a value to the SPI peripheral in slave mode + * + * Blocks until the SPI peripheral can be written to + * @param[in] obj The SPI peripheral to write + * @param[in] value The value to write + */ +void spi_slave_write(spi_t *obj, int value) +{ + struct spi_s *spiobj = SPI_S(obj); + /* wait the SPI transmit buffer is empty */ + while (RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)); + spi_i2s_data_transmit(spiobj->spi, value); +} + +/** Checks if the specified SPI peripheral is in use + * + * @param[in] obj The SPI peripheral to check + * @return non-zero if the peripheral is currently transmitting + */ +int spi_busy(spi_t *obj) +{ + int status; + struct spi_s *spiobj = SPI_S(obj); + /* check whether or not the SPI is busy */ + status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TRANS) != RESET) ? 1 : 0); + return status; +} + +#endif diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/us_ticker.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/us_ticker.c new file mode 100644 index 0000000000..ae7b017306 --- /dev/null +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/us_ticker.c @@ -0,0 +1,388 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 GigaDevice Semiconductor Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gd32f30x.h" +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "hal_tick.h" + +#if TICKER_TIMER_WIDTH_BIT == 16 +uint32_t time_before; +uint32_t total_elapsed_time; +#endif + +/* this variable is set to 1 at the end of mbed_sdk_init function. +the ticker_read_us() function must not be called until the mbed_sdk_init is terminated */ +extern int mbed_sdk_inited; +uint32_t ticker_timer_cnt; +uint32_t ticker_timer_ch0cv; +uint32_t ticker_timer_dmainten; + +void ticker_timer_init(void); +#if TICKER_TIMER_WIDTH_BIT == 16 +void ticker_16bits_timer_init(void); +#else +void ticker_32bits_timer_init(void); +#endif +void ticker_timer_irq_handler(void); +/* get TIMER clock */ +static uint32_t timer_get_clock(uint32_t timer_periph); +uint32_t ticker_tick_get(void); +void ticker_timer_data_save(void); +void ticker_timer_data_save(void); +void ticker_timer_data_restore(void); + +void ticker_timer_init(void) +{ +#if TICKER_TIMER_WIDTH_BIT == 16 + ticker_16bits_timer_init(); +#else + ticker_32bits_timer_init(); +#endif +} + +/** get tick + * + * @return the tick + */ +uint32_t ticker_tick_get(void) +{ +#if TICKER_TIMER_WIDTH_BIT == 16 + uint32_t new_time; + if (mbed_sdk_inited) { + /* Apply the latest time recorded just before the sdk is inited */ + new_time = ticker_read_us(get_us_ticker_data()) + time_before; + time_before = 0; + return (new_time / 1000); + } else { + /* Prevent small values from subtracting large ones + example: + 0x0010-0xFFEE=FFFF0022 , (0xFFFF-0xFFEE+0x10+1=0x22,1 mean CNT=0 tick) + FFFF0022 & 0xFFFF = 0022 + */ + new_time = us_ticker_read(); + total_elapsed_time += (new_time - time_before) & 0xFFFF; + time_before = new_time; + return (total_elapsed_time / 1000); + } +#else // 32-bit timer + if (mbed_sdk_inited) { + return (ticker_read_us(get_us_ticker_data()) / 1000); + } else { + return (us_ticker_read() / 1000); + } +#endif +} + +/** Get frequency and counter bits of this ticker. + */ +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + 1000000, + TICKER_TIMER_WIDTH_BIT + }; + return &info; +} + + + +/* config for 32bits TIMER */ +#if TICKER_TIMER_WIDTH_BIT == 16 +/** config the interrupt handler + */ +void ticker_timer_irq_handler(void) +{ + if (SET == timer_interrupt_flag_get(TICKER_TIMER, TIMER_INT_FLAG_CH0)) { + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + us_ticker_irq_handler(); + } +} + +/** initialize the TIMER + */ +void ticker_16bits_timer_init(void) +{ + timer_parameter_struct timer_initpara; + uint32_t timer_clk = timer_get_clock(TICKER_TIMER); + + /* enable ticker timer clock */ + TICKER_TIMER_RCU_CLOCK_ENABLE; + + /* reset ticker timer peripheral */ + TICKER_TIMER_RESET_ENABLE; + TICKER_TIMER_RESET_DISABLE; + + /* TICKER_TIMER configuration */ + timer_initpara.prescaler = (uint32_t)(timer_clk / 1000000) - 1;; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 0xFFFF; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TICKER_TIMER, &timer_initpara); + + /* auto-reload preload disable */ + timer_auto_reload_shadow_disable(TICKER_TIMER); + + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); + + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, ENABLE); + + timer_enable(TICKER_TIMER); + + /* Output compare channel 0 interrupt for mbed timeout */ + NVIC_SetVector(TICKER_TIMER_IRQ, (uint32_t)ticker_timer_irq_handler); + NVIC_EnableIRQ(TICKER_TIMER_IRQ); + + /* if define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json or other file, + hold the TICKER_TIMER counter for debug when core halted + */ +#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TICKER_TIMER_DEBUG_STOP) + TICKER_TIMER_DEBUG_STOP; +#endif + + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); + + /* used by ticker_tick_get() */ + time_before = 0; + total_elapsed_time = 0; +} +/* config for 32bits TIMER */ +#else +/** config the interrupt handler + */ +void ticker_timer_irq_handler(void) +{ + if (SET == timer_interrupt_flag_get(TICKER_TIMER, TIMER_INT_FLAG_CH0)) { + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + us_ticker_irq_handler(); + } +} + +/** initialize the TIMER + */ +void ticker_32bits_timer_init(void) +{ + timer_parameter_struct timer_initpara; + uint32_t timer_clk = timer_get_clock(TICKER_TIMER); + + /* enable ticker timer clock */ + TICKER_TIMER_RCU_CLOCK_ENABLE; + + /* reset ticker timer peripheral */ + TICKER_TIMER_RESET_ENABLE; + TICKER_TIMER_RESET_DISABLE; + + /* TICKER_TIMER configuration */ + timer_initpara.prescaler = (uint32_t)(timer_clk / 1000000) - 1;; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 0xFFFFFFFF; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(TICKER_TIMER, &timer_initpara); + + /* auto-reload preload disable */ + timer_auto_reload_shadow_disable(TICKER_TIMER); + + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); + + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, ENABLE); + + timer_enable(TICKER_TIMER); + + /* Output compare channel 0 interrupt for mbed timeout */ + NVIC_SetVector(TICKER_TIMER_IRQ, (uint32_t)ticker_timer_irq_handler); + NVIC_EnableIRQ(TICKER_TIMER_IRQ); + + /* if define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json or other file, + hold the TICKER_TIMER counter for debug when core halted + */ +#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TICKER_TIMER_DEBUG_STOP) + TICKER_TIMER_DEBUG_STOP; +#endif + + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); +} + +#endif /* 16-bit/32-bit timer init */ + +/** Initialize the ticker + * + * Initialize or re-initialize the ticker. This resets all the + * clocking and prescaler registers, along with disabling + * the compare interrupt. + * + * @note Initialization properties tested by ::ticker_init_test + */ +void us_ticker_init(void) +{ + /* TIMER is already initialized in ticker_timer_init() */ + /* disable the TIMER interrupt */ + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_ENABLE); + + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, ENABLE); + + timer_enable(TICKER_TIMER); + +} + +/** Read the current counter + * + * Read the current counter value without performing frequency conversions. + * If no rollover has occurred, the seconds passed since us_ticker_init() + * was called can be found by dividing the ticks returned by this function + * by the frequency returned by ::us_ticker_get_info. + * + * @return The current timer's counter value in ticks + */ +uint32_t us_ticker_read() +{ + /* read TIMER counter value */ + uint32_t count_value = 0U; + count_value = TIMER_CNT(TICKER_TIMER); + return (count_value); +} + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in ticks to be set + * + * @note no special handling needs to be done for times in the past + * as the common timer code will detect this and call + * us_ticker_fire_interrupt() if this is the case + * + * @note calling this function with timestamp of more than the supported + * number of bits returned by ::us_ticker_get_info results in undefined + * behavior. + */ +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + /* configure TIMER channel output pulse value.Only set this value when you interrupt disabled */ + timer_channel_output_pulse_value_config(TICKER_TIMER, TIMER_CH_0, (uint32_t)timestamp); + /* clear TIMER interrupt flag,enable the TIMER interrupt */ + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + timer_interrupt_enable(TICKER_TIMER, TIMER_INT_CH0); +} + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + */ +void us_ticker_fire_interrupt(void) +{ + /* clear TIMER interrupt flag */ + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); + /* channel 0 capture or compare event generation immediately,so CH0IF set for interrupt */ + timer_event_software_generate(TICKER_TIMER, TIMER_EVENT_SRC_CH0G); + /* enable the TIMER interrupt */ + timer_interrupt_enable(TICKER_TIMER, TIMER_INT_CH0); +} + +/** Disable us ticker interrupt + */ +void us_ticker_disable_interrupt(void) +{ + /* disable the TIMER interrupt */ + timer_interrupt_disable(TICKER_TIMER, TIMER_INT_CH0); +} + +/** Clear us ticker interrupt + * note: must be called with interrupts disabled function + */ +void us_ticker_clear_interrupt(void) +{ + /* clear TIMER interrupt flag */ + timer_interrupt_flag_clear(TICKER_TIMER, TIMER_INT_FLAG_CH0); +} + +/** save ticker TIMER data when MCU go to deepsleep +*/ +void ticker_timer_data_save(void) +{ + ticker_timer_cnt = TIMER_CNT(TICKER_TIMER); + ticker_timer_ch0cv = TIMER_CH0CV(TICKER_TIMER); + ticker_timer_dmainten = TIMER_DMAINTEN(TICKER_TIMER); +} + +/** restore ticker TIMER data when MCU go out deepsleep +*/ +void ticker_timer_data_restore(void) +{ + TIMER_CNT(TICKER_TIMER) = ticker_timer_cnt; + TIMER_CH0CV(TICKER_TIMER) = ticker_timer_ch0cv; + TIMER_DMAINTEN(TICKER_TIMER) = ticker_timer_dmainten; +} + +/** Deinitialize the us ticker + * + * Powerdown the us ticker in preparation for sleep, powerdown, or reset. + * + * After this function is called, no other ticker functions should be called + * except us_ticker_init(), calling any function other than init is undefined. + * + * @note This function stops the ticker from counting. + */ +void us_ticker_free(void) +{ + /* configure TIMER channel enable state */ + timer_channel_output_state_config(TICKER_TIMER, TIMER_CH_0, TIMER_CCX_DISABLE); + /* configure TIMER primary output function */ + timer_primary_output_config(TICKER_TIMER, DISABLE); + /* disable a TIMER */ + timer_disable(TICKER_TIMER); + + us_ticker_disable_interrupt(); +} + +/** get TIMER clock + * @param timer_dev: TIMER device information structrue + the structure is not necessary to be reconfigured after structrue initialization, + the structure parameters altering is automatically configured by core + * @return TIMER clock +*/ +static uint32_t timer_get_clock(uint32_t timer_periph) +{ + uint32_t timerclk; + + if ((TIMER0 == timer_periph) || (TIMER7 == timer_periph) || + (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || (TIMER10 == timer_periph)) { + /* get the current APB2 TIMER clock source */ + if (RCU_APB2_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB2PSC)) { + timerclk = rcu_clock_freq_get(CK_APB2); + } else { + timerclk = rcu_clock_freq_get(CK_APB2) * 2; + } + } else { + /* get the current APB1 TIMER clock source */ + if (RCU_APB1_CKAHB_DIV1 == (RCU_CFG0 & RCU_CFG0_APB1PSC)) { + timerclk = rcu_clock_freq_get(CK_APB1); + } else { + timerclk = rcu_clock_freq_get(CK_APB1) * 2; + } + } + + return timerclk; +} diff --git a/targets/TARGET_GigaDevice/mbed_rtx.h b/targets/TARGET_GigaDevice/mbed_rtx.h new file mode 100644 index 0000000000..4734405de6 --- /dev/null +++ b/targets/TARGET_GigaDevice/mbed_rtx.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2009-2018 ARM Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#include + +#if defined(TARGET_GD32F307VG) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20018000UL) +#endif + +#endif + +#if defined(TARGET_GD32E103VB) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20008000UL) +#endif + +#endif + +#if defined(TARGET_GD32F450ZI) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20070000UL) +#endif + +#endif + +#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS)) +extern uint32_t __StackLimit[]; +extern uint32_t __StackTop[]; +extern uint32_t __end__[]; +extern uint32_t __HeapLimit[]; +#define HEAP_START ((unsigned char*)__end__) +#define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) +#define ISR_STACK_START ((unsigned char*)__StackLimit) +#define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) +#endif + +#endif /* MBED_MBED_RTX_H */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/PinNames.h new file mode 100644 index 0000000000..5078e98cee --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/PinNames.h @@ -0,0 +1,150 @@ +/******************************************************************************** + * \copyright + * \copyright + * Copyright 2018-2018, ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + *******************************************************************************/ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + P0_31 = p31, + + LED1 = p25, + LED2 = p26, + LED3 = p27, + + AIN0 = p2, + AIN1 = p3, + AIN2 = p4, + + GP0 = p19, + GP1 = p20, + GP2 = p28, + GP3 = p29, + GP4 = p30, + GP5 = p31, // LCD-A0 + GP6 = p5, // LCD-RESET + GP7 = p6, // LCD-CS + GP8 = p7, + + RX_PIN_NUMBER = p12, + TX_PIN_NUMBER = p11, + CTS_PIN_NUMBER = p9, + RTS_PIN_NUMBER = p8, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + STDIO_UART_TX = TX_PIN_NUMBER, + STDIO_UART_RX = RX_PIN_NUMBER, + STDIO_UART_CTS = CTS_PIN_NUMBER, + STDIO_UART_RTS = RTS_PIN_NUMBER, + + SPI_MOSI = p16, + SPI_MISO = p17, + SPI_SCK = p18, + SPI_CS = p10, + + USER_BUTTON = GP0, + + I2C_SDA = p14, + I2C_SCL = p15, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/device.h new file mode 100644 index 0000000000..bffb79b9b5 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/device.h @@ -0,0 +1,13 @@ +/******************************************************************************** + * \copyright + * \copyright + * Copyright 2018-2018, ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + *******************************************************************************/ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c index 81d79303e5..dbfd41f749 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c @@ -251,9 +251,6 @@ static void nordic_nrf5_uart_callback_handler(uint32_t instance) */ static void nordic_nrf5_uart_event_handler_endtx(int instance) { - /* Disable ENDTX event again. */ - nrf_uarte_int_disable(nordic_nrf5_uart_register[instance], NRF_UARTE_INT_ENDTX_MASK); - /* Release mutex. As the owner this call is safe. */ nordic_nrf5_uart_state[instance].tx_in_progress = 0; @@ -277,9 +274,6 @@ static void nordic_nrf5_uart_event_handler_endtx(int instance) #if DEVICE_SERIAL_ASYNCH static void nordic_nrf5_uart_event_handler_endtx_asynch(int instance) { - /* Disable ENDTX interrupt. */ - nrf_uarte_int_disable(nordic_nrf5_uart_register[instance], NRF_UARTE_INT_ENDTX_MASK); - /* Set Tx done and reset Tx mode to be not asynchronous. */ nordic_nrf5_uart_state[instance].tx_in_progress = 0; nordic_nrf5_uart_state[instance].tx_asynch = false; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/qspi_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/qspi_api.c index 222f812018..73b2cd757c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/qspi_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/qspi_api.c @@ -53,7 +53,6 @@ TODO - dummy cycles */ -#define MBED_HAL_QSPI_HZ_TO_CONFIG(hz) ((32000000/(hz))-1) #define MBED_HAL_QSPI_MAX_FREQ 32000000UL // NRF supported R/W opcodes @@ -68,10 +67,15 @@ TODO #define PP4O_opcode 0x32 #define PP4IO_opcode 0x38 +#define SCK_DELAY 0x05 +#define WORD_MASK 0x03 + static nrf_drv_qspi_config_t config; // Private helper function to track initialization static ret_code_t _qspi_drv_init(void); +// Private helper function to set NRF frequency divider +nrf_qspi_frequency_t nrf_frequency(int hz); qspi_status_t qspi_prepare_command(qspi_t *obj, const qspi_command_t *command, bool write) { @@ -207,8 +211,8 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN config.pins.io3_pin = (uint32_t)io3; config.irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY; - config.phy_if.sck_freq = (nrf_qspi_frequency_t)MBED_HAL_QSPI_HZ_TO_CONFIG(hz); - config.phy_if.sck_delay = 0x05; + config.phy_if.sck_freq = nrf_frequency(hz); + config.phy_if.sck_delay = SCK_DELAY; config.phy_if.dpmen = false; config.phy_if.spi_mode = mode == 0 ? NRF_QSPI_MODE_0 : NRF_QSPI_MODE_1; @@ -232,8 +236,8 @@ qspi_status_t qspi_free(qspi_t *obj) qspi_status_t qspi_frequency(qspi_t *obj, int hz) { - config.phy_if.sck_freq = (nrf_qspi_frequency_t)MBED_HAL_QSPI_HZ_TO_CONFIG(hz); - + config.phy_if.sck_freq = nrf_frequency(hz); + // use sync version, no handler ret_code_t ret = _qspi_drv_init(); if (ret == NRF_SUCCESS ) { @@ -247,6 +251,11 @@ qspi_status_t qspi_frequency(qspi_t *obj, int hz) qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length) { + // length needs to be rounded up to the next WORD (4 bytes) + if ((*length & WORD_MASK) > 0) { + return QSPI_STATUS_INVALID_PARAMETER; + } + qspi_status_t status = qspi_prepare_command(obj, command, true); if (status != QSPI_STATUS_OK) { return status; @@ -263,6 +272,11 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length) { + // length needs to be rounded up to the next WORD (4 bytes) + if ((*length & WORD_MASK) > 0) { + return QSPI_STATUS_INVALID_PARAMETER; + } + qspi_status_t status = qspi_prepare_command(obj, command, false); if (status != QSPI_STATUS_OK) { return status; @@ -344,6 +358,48 @@ static ret_code_t _qspi_drv_init(void) return ret; } +// Private helper to set NRF frequency divider +nrf_qspi_frequency_t nrf_frequency(int hz) +{ + nrf_qspi_frequency_t freq = NRF_QSPI_FREQ_32MDIV16; + + // Convert hz to closest NRF frequency divider + if (hz < 2130000) + freq = NRF_QSPI_FREQ_32MDIV16; // 2.0 MHz, minimum supported frequency + else if (hz < 2290000) + freq = NRF_QSPI_FREQ_32MDIV15; // 2.13 MHz + else if (hz < 2460000) + freq = NRF_QSPI_FREQ_32MDIV14; // 2.29 MHz + else if (hz < 2660000) + freq = NRF_QSPI_FREQ_32MDIV13; // 2.46 Mhz + else if (hz < 2900000) + freq = NRF_QSPI_FREQ_32MDIV12; // 2.66 MHz + else if (hz < 3200000) + freq = NRF_QSPI_FREQ_32MDIV11; // 2.9 MHz + else if (hz < 3550000) + freq = NRF_QSPI_FREQ_32MDIV10; // 3.2 MHz + else if (hz < 4000000) + freq = NRF_QSPI_FREQ_32MDIV9; // 3.55 MHz + else if (hz < 4570000) + freq = NRF_QSPI_FREQ_32MDIV8; // 4.0 MHz + else if (hz < 5330000) + freq = NRF_QSPI_FREQ_32MDIV7; // 4.57 MHz + else if (hz < 6400000) + freq = NRF_QSPI_FREQ_32MDIV6; // 5.33 MHz + else if (hz < 8000000) + freq = NRF_QSPI_FREQ_32MDIV5; // 6.4 MHz + else if (hz < 10600000) + freq = NRF_QSPI_FREQ_32MDIV4; // 8.0 MHz + else if (hz < 16000000) + freq = NRF_QSPI_FREQ_32MDIV3; // 10.6 MHz + else if (hz < 32000000) + freq = NRF_QSPI_FREQ_32MDIV2; // 16 MHz + else + freq = NRF_QSPI_FREQ_32MDIV1; // 32 MHz + + return freq; +} + #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralNames.h index e56c403a12..29442b8ace 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralNames.h @@ -124,6 +124,16 @@ typedef enum { } ADCName; +typedef enum { +#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 7)) + DAC_0_0 = (int) NU_MODNAME(DAC0_BASE + NS_OFFSET, 0, 0), + DAC_1_0 = (int) NU_MODNAME(DAC1_BASE + NS_OFFSET, 1, 0) +#else + DAC_0_0 = (int) NU_MODNAME(DAC0_BASE, 0, 0), + DAC_1_0 = (int) NU_MODNAME(DAC1_BASE, 1, 0) +#endif +} DACName; + typedef enum { #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1<<16)) diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.c index 330d14d86c..c9c3c89973 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.c +++ b/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.c @@ -172,6 +172,15 @@ const PinMap PinMap_ADC[] = { {NC, NC, 0} }; +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PB_12, DAC_0_0, SYS_GPB_MFPH_PB12MFP_DAC0_OUT}, + {PB_13, DAC_1_0, SYS_GPB_MFPH_PB13MFP_DAC1_OUT}, + + {NC, NC, 0} +}; + //*** I2C *** const PinMap PinMap_I2C_SDA[] = { diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.h index 1f2eb94dee..0e6d9a30b1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.h +++ b/targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.h @@ -32,6 +32,10 @@ extern const PinMap PinMap_GPIO[]; extern const PinMap PinMap_ADC[]; +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + //*** I2C *** extern const PinMap PinMap_I2C_SDA[]; diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M2351/analogout_api.c new file mode 100644 index 0000000000..d54d0f628b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2351/analogout_api.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2018, Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" + +/* Maximum DAC modules */ +#define NU_DACMOD_MAXNUM 2 +/* Maximum DAC channels per module */ +#define NU_DACCHN_MAXNUM 1 + +static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM]; + +static const struct nu_modinit_s dac_modinit_tab[] = { + {DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL}, + {DAC_1_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Module-level setup from here */ + + /* DAC0/DAC1 are designed to share the same RESET/clock/IRQ for group + * function. So we: + * + * 1. Go to setup flow (analogout_init()) only when none of DAC0/DAC1 + * channels are activated. + * 2. Go to windup flow (analogout_free()) only when all DAC0/DAC1 + * channels are deactivated. + */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + /* Reset IP + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); + + /* Select IP clock source and clock divider + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); + + /* The conversion settling time is 8us when 12-bit input code transition from + * lowest code (0x000) to highest code (0xFFF). */ + DAC_SetDelayTime(dac_base, 8); + + /* Configure DAT data format to left-aligned + * Effective 12-bits are aligned to left of 16-bit DAC_DAT. */ + DAC_ENABLE_LEFT_ALIGN(dac_base); + } + + /* Channel-level setup from here: */ + + /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ + DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); + + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + + /* Mark channel allocated */ + dac_modinit_mask[modidx] |= 1 << chn; +} + +void analogout_free(dac_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Channel-level windup from here */ + + /* Mark channel free */ + dac_modinit_mask[modidx] &= ~(1 << modidx); + + /* Close channel */ + DAC_Close(dac_base, chn); + + /* Module-level windup from here: */ + + /* See analogout_init() for reason */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(modinit->clkidx); + } +} + +void analogout_write(dac_t *obj, float value) +{ + if (value <= 0.0f) { + analogout_write_u16(obj, 0); + } else if (value >= 1.0f) { + analogout_write_u16(obj, 0xFFFF); + } else { + analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF))); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + DAC_WRITE_DATA(dac_base, chn, value); + + /* Clear the DAC conversion complete finish flag for safe */ + DAC_CLR_INT_FLAG(dac_base, chn); + + /* Start A/D conversion */ + DAC_START_CONV(dac_base); + + /* Wait for completed */ + while (DAC_IS_BUSY(dac_base, chn)); +} + +float analogout_read(dac_t *obj) +{ + uint32_t value = analogout_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + uint16_t dat12_4 = DAC_READ_DATA(dac_base, chn); + /* Just 12 bits are effective. Convert to 16 bits. + * + * dat12_4 : b11b10b9b8 b7b6b5b4 b3b2b1b0 0000 + * dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + */ + uint16_t dat16 = (dat12_4 & 0xFFF0) | (dat12_4 >> 12); + + return dat16; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct index f78f2487f6..71332995ea 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct @@ -41,6 +41,10 @@ #define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S) #endif +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + #else #ifndef MBED_APP_START @@ -59,6 +63,10 @@ #define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S #endif +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + #endif /* Requirements for NSC location @@ -70,15 +78,6 @@ */ #define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE) -/* Initial/ISR stack size */ -#if (! defined(NU_INITIAL_STACK_SIZE)) -#if defined(DOMAIN_NS) && DOMAIN_NS -#define NU_INITIAL_STACK_SIZE 0x800 -#else -#define NU_INITIAL_STACK_SIZE 0x800 -#endif -#endif - #if defined(DOMAIN_NS) && DOMAIN_NS LR_IROM1 MBED_APP_START @@ -91,7 +90,7 @@ LR_IROM1 MBED_APP_START .ANY (+RO) } - ARM_LIB_STACK MBED_RAM_APP_START EMPTY NU_INITIAL_STACK_SIZE + ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE { } @@ -129,7 +128,7 @@ LR_IROM1 MBED_APP_START .ANY (+RO) } - ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct index f78f2487f6..71332995ea 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct @@ -41,6 +41,10 @@ #define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S) #endif +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + #else #ifndef MBED_APP_START @@ -59,6 +63,10 @@ #define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S #endif +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + #endif /* Requirements for NSC location @@ -70,15 +78,6 @@ */ #define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE) -/* Initial/ISR stack size */ -#if (! defined(NU_INITIAL_STACK_SIZE)) -#if defined(DOMAIN_NS) && DOMAIN_NS -#define NU_INITIAL_STACK_SIZE 0x800 -#else -#define NU_INITIAL_STACK_SIZE 0x800 -#endif -#endif - #if defined(DOMAIN_NS) && DOMAIN_NS LR_IROM1 MBED_APP_START @@ -91,7 +90,7 @@ LR_IROM1 MBED_APP_START .ANY (+RO) } - ARM_LIB_STACK MBED_RAM_APP_START EMPTY NU_INITIAL_STACK_SIZE + ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE { } @@ -129,7 +128,7 @@ LR_IROM1 MBED_APP_START .ANY (+RO) } - ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld index 21dd0c2fda..d1e9d67305 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld @@ -28,46 +28,50 @@ #if defined(DOMAIN_NS) && DOMAIN_NS #ifndef MBED_APP_START -#define MBED_APP_START (0x10000000 + MBED_ROM_START + MBED_ROM_SIZE_S) +#define MBED_APP_START (0x10000000 + MBED_ROM_START + MBED_ROM_SIZE_S) #endif #ifndef MBED_APP_SIZE -#define MBED_APP_SIZE (MBED_ROM_SIZE - MBED_ROM_SIZE_S) +#define MBED_APP_SIZE (MBED_ROM_SIZE - MBED_ROM_SIZE_S) #endif #ifndef MBED_RAM_APP_START -#define MBED_RAM_APP_START (0x10000000 + MBED_RAM_START + MBED_RAM_SIZE_S) +#define MBED_RAM_APP_START (0x10000000 + MBED_RAM_START + MBED_RAM_SIZE_S) #endif #ifndef MBED_RAM_APP_SIZE -#define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S) +#define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S) +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 #endif #else #ifndef MBED_APP_START -#define MBED_APP_START MBED_ROM_START +#define MBED_APP_START MBED_ROM_START #endif #ifndef MBED_APP_SIZE -#define MBED_APP_SIZE MBED_ROM_SIZE_S +#define MBED_APP_SIZE MBED_ROM_SIZE_S #endif #ifndef MBED_RAM_APP_START -#define MBED_RAM_APP_START MBED_RAM_START +#define MBED_RAM_APP_START MBED_RAM_START #endif #ifndef MBED_RAM_APP_SIZE -#define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S +#define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S +#endif + +#ifndef MBED_BOOT_STACK_SIZE +#define MBED_BOOT_STACK_SIZE 0x400 #endif #endif -#if defined(DOMAIN_NS) && DOMAIN_NS -StackSize = 0x800; -#else -StackSize = 0x800; -#endif +StackSize = MBED_BOOT_STACK_SIZE; /* Requirements for NSC location * diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf index 059f2f4388..6ee617cfa0 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf +++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf @@ -33,6 +33,10 @@ if (isdefinedsymbol(DOMAIN_NS)) { define symbol MBED_RAM_APP_SIZE = (MBED_RAM_SIZE - MBED_RAM_SIZE_S); } + if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; + } + /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ @@ -42,7 +46,7 @@ if (isdefinedsymbol(DOMAIN_NS)) { define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1; /*-Sizes-*/ - define symbol __ICFEDIT_size_cstack__ = 0x800; + define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __ICFEDIT_size_heap__ = 0x8000; } else { @@ -63,6 +67,10 @@ if (isdefinedsymbol(DOMAIN_NS)) { define symbol MBED_RAM_APP_SIZE = MBED_RAM_SIZE_S; } + if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; + } + /* Requirements for NSC location * * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. @@ -87,7 +95,7 @@ if (isdefinedsymbol(DOMAIN_NS)) { define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1; /*-Sizes-*/ - define symbol __ICFEDIT_size_cstack__ = 0x800; + define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __ICFEDIT_size_heap__ = 0x4000; } diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/objects.h b/targets/TARGET_NUVOTON/TARGET_M2351/objects.h index 0959ef25fa..8e55dc6bf0 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M2351/objects.h @@ -44,10 +44,12 @@ struct analogin_s { ADCName adc; }; +struct dac_s { + DACName dac; +}; + struct serial_s { UARTName uart; - PinName pin_tx; - PinName pin_rx; uint32_t baudrate; uint32_t databits; diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M2351/serial_api.c index 534791c9d1..d6ad1afdda 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2351/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M2351/serial_api.c @@ -200,39 +200,45 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; if (! var->ref_cnt) { - do { - /* Reset module - * - * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. - */ - SYS_ResetModule_S(modinit->rsetidx); + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); - /* Select IP clock source - * - * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. - */ - CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); - - /* Enable IP clock - * - * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. - */ - CLK_EnableModuleClock_S(modinit->clkidx); + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - } while (0); + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); - obj->serial.pin_tx = tx; - obj->serial.pin_rx = rx; + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); } var->ref_cnt ++; - // Configure the UART module and set its baudrate - serial_baud(obj, 9600); - // Configure data bits, parity, and stop bits - serial_format(obj, 8, ParityNone, 1); - obj->serial.vec = var->vec; obj->serial.irq_en = 0; @@ -244,10 +250,12 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; #endif - // For stdio management - if (obj->serial.uart == STDIO_UART) { + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); } if (var->ref_cnt) { @@ -296,7 +304,9 @@ void serial_free(serial_t *obj) var->obj = NULL; } - if (obj->serial.uart == STDIO_UART) { + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 0; } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M451/PeripheralNames.h index 7988f18af5..511482ea73 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/PeripheralNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/PeripheralNames.h @@ -65,6 +65,10 @@ typedef enum { ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15) } ADCName; +typedef enum { + DAC_0_0 = (int) NU_MODNAME(DAC_BASE, 0, 0) +} DACName; + typedef enum { UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), diff --git a/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.c index e236cffb11..084e847486 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.c @@ -158,6 +158,14 @@ const PinMap PinMap_ADC[] = { {NC, NC, 0} }; +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PB_0, DAC_0_0, SYS_GPB_MFPL_PB0MFP_DAC}, + + {NC, NC, 0} +}; + //*** I2C *** const PinMap PinMap_I2C_SDA[] = { diff --git a/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.h index 1f2eb94dee..0e6d9a30b1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/PeripheralPins.h @@ -32,6 +32,10 @@ extern const PinMap PinMap_GPIO[]; extern const PinMap PinMap_ADC[]; +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + //*** I2C *** extern const PinMap PinMap_I2C_SDA[]; diff --git a/targets/TARGET_NUVOTON/TARGET_M451/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M451/analogout_api.c new file mode 100644 index 0000000000..f89467079d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M451/analogout_api.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2018, Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" + +/* Maximum DAC modules */ +#define NU_DACMOD_MAXNUM 1 +/* Maximum DAC channels per module */ +#define NU_DACCHN_MAXNUM 1 + +static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM]; + +static const struct nu_modinit_s dac_modinit_tab[] = { + {DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Module-level setup from here */ + + if (! dac_modinit_mask[modidx]) { + /* Reset IP */ + SYS_ResetModule(modinit->rsetidx); + + /* Select IP clock source and clock divider */ + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock */ + CLK_EnableModuleClock(modinit->clkidx); + + /* The conversion settling time is 8us when 12-bit input code transition from + * lowest code (0x000) to highest code (0xFFF). */ + DAC_SetDelayTime(dac_base, 8); + + /* Configure DAT data format to left-aligned + * Effective 12-bits are aligned to left of 16-bit DAC_DAT. */ + DAC_ENABLE_LEFT_ALIGN(dac_base); + } + + /* Channel-level setup from here: */ + + /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ + DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); + + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + + /* Mark channel allocated */ + dac_modinit_mask[modidx] |= 1 << chn; +} + +void analogout_free(dac_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Channel-level windup from here */ + + /* Mark channel free */ + dac_modinit_mask[modidx] &= ~(1 << modidx); + + /* Close channel */ + DAC_Close(dac_base, chn); + + /* Module-level windup from here: */ + + if (! dac_modinit_mask[modidx]) { + + /* Disable IP clock */ + CLK_DisableModuleClock(modinit->clkidx); + } +} + +void analogout_write(dac_t *obj, float value) +{ + if (value <= 0.0f) { + analogout_write_u16(obj, 0); + } else if (value >= 1.0f) { + analogout_write_u16(obj, 0xFFFF); + } else { + analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF))); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + DAC_WRITE_DATA(dac_base, chn, value); + + /* Clear the DAC conversion complete finish flag for safe */ + DAC_CLR_INT_FLAG(dac_base, chn); + + /* Start A/D conversion */ + DAC_START_CONV(dac_base); + + /* Wait for completed */ + while (DAC_IS_BUSY(dac_base, chn)); +} + +float analogout_read(dac_t *obj) +{ + uint32_t value = analogout_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + uint16_t dat12_4 = DAC_READ_DATA(dac_base, chn); + /* Just 12 bits are effective. Convert to 16 bits. + * + * dat12_4 : b11b10b9b8 b7b6b5b4 b3b2b1b0 0000 + * dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + */ + uint16_t dat16 = (dat12_4 & 0xFFF0) | (dat12_4 >> 12); + + return dat16; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct index d2ab59a21b..4986982ab6 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct @@ -8,6 +8,10 @@ #define MBED_APP_SIZE 0x00040000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address *(RESET, +First) @@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 64)) { ; Reserve for vectors + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 64)) { ; Reserve for vectors } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct index d2ab59a21b..f642e2379b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct @@ -8,6 +8,10 @@ #define MBED_APP_SIZE 0x00040000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address *(RESET, +First) @@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } - - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 64)) { ; Reserve for vectors + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 64)) { ; Reserve for vectors } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld index 39189a632f..a3d13705fc 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld @@ -10,7 +10,11 @@ #define MBED_APP_SIZE 0x00040000 #endif -StackSize = 0x800; +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +StackSize = MBED_BOOT_STACK_SIZE; MEMORY { diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf index 588f1e02db..46c5c91e2a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf @@ -3,6 +3,7 @@ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00040000; } +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ @@ -11,7 +12,7 @@ define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20008000 - 1; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __ICFEDIT_size_heap__ = 0x4000; /**** End of ICF editor section. ###ICF###*/ diff --git a/targets/TARGET_NUVOTON/TARGET_M451/objects.h b/targets/TARGET_NUVOTON/TARGET_M451/objects.h index 9c633835d9..9b08ce6558 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/objects.h @@ -48,10 +48,12 @@ struct analogin_s { //PinName pin; }; +struct dac_s { + DACName dac; +}; + struct serial_s { UARTName uart; - PinName pin_tx; - PinName pin_rx; uint32_t baudrate; uint32_t databits; diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c index 3eb5efa34d..ec557a43e6 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c @@ -172,7 +172,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) if (! var->ref_cnt) { // Reset this module SYS_ResetModule(modinit->rsetidx); - + // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock @@ -180,17 +180,25 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); - - obj->serial.pin_tx = tx; - obj->serial.pin_rx = rx; + + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); } var->ref_cnt ++; - - // Configure the UART module and set its baudrate - serial_baud(obj, 9600); - // Configure data bits, parity, and stop bits - serial_format(obj, 8, ParityNone, 1); - + obj->serial.vec = var->vec; obj->serial.irq_en = 0; @@ -202,12 +210,14 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; #endif - // For stdio management - if (obj->serial.uart == STDIO_UART) { + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); } - + if (var->ref_cnt) { // Mark this module to be inited. int i = modinit - uart_modinit_tab; @@ -248,11 +258,13 @@ void serial_free(serial_t *obj) if (var->obj == obj) { var->obj = NULL; } - - if (obj->serial.uart == STDIO_UART) { + + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 0; } - + if (! var->ref_cnt) { // Mark this module to be deinited. int i = modinit - uart_modinit_tab; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h index 0cd1cb1d9a..67e3521200 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h @@ -67,6 +67,11 @@ typedef enum { ADC_0_15 = (int) NU_MODNAME(EADC_BASE, 0, 15) } ADCName; +typedef enum { + DAC_0_0 = (int) NU_MODNAME(DAC0_BASE, 0, 0), + DAC_1_0 = (int) NU_MODNAME(DAC1_BASE, 1, 0) +} DACName; + typedef enum { UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), diff --git a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.c index ef35df7682..e9966cce40 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.c @@ -39,6 +39,15 @@ const PinMap PinMap_ADC[] = { {NC, NC, 0} }; +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PB_12, DAC_0_0, SYS_GPB_MFPH_PB12MFP_DAC0_OUT}, + {PB_13, DAC_1_0, SYS_GPB_MFPH_PB13MFP_DAC1_OUT}, + + {NC, NC, 0} +}; + //*** I2C *** const PinMap PinMap_I2C_SDA[] = { diff --git a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.h index 1f2eb94dee..0e6d9a30b1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralPins.h @@ -32,6 +32,10 @@ extern const PinMap PinMap_GPIO[]; extern const PinMap PinMap_ADC[]; +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + //*** I2C *** extern const PinMap PinMap_I2C_SDA[]; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M480/analogout_api.c new file mode 100644 index 0000000000..1e57e94121 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M480/analogout_api.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2018, Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" + +/* Maximum DAC modules */ +#define NU_DACMOD_MAXNUM 2 +/* Maximum DAC channels per module */ +#define NU_DACCHN_MAXNUM 1 + +static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM]; + +static const struct nu_modinit_s dac_modinit_tab[] = { + {DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL}, + {DAC_1_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Module-level setup from here */ + + /* DAC0/DAC1 are designed to share the same RESET/clock/IRQ for group + * function. So we: + * + * 1. Go to setup flow (analogout_init()) only when none of DAC0/DAC1 + * channels are activated. + * 2. Go to windup flow (analogout_free()) only when all DAC0/DAC1 + * channels are deactivated. + */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + /* Reset IP */ + SYS_ResetModule(modinit->rsetidx); + + /* Select IP clock source and clock divider */ + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock */ + CLK_EnableModuleClock(modinit->clkidx); + + /* The conversion settling time is 8us when 12-bit input code transition from + * lowest code (0x000) to highest code (0xFFF). */ + DAC_SetDelayTime(dac_base, 8); + + /* Configure DAT data format to left-aligned + * Effective 12-bits are aligned to left of 16-bit DAC_DAT. */ + DAC_ENABLE_LEFT_ALIGN(dac_base); + } + + /* Channel-level setup from here: */ + + /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ + DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); + + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + + /* Mark channel allocated */ + dac_modinit_mask[modidx] |= 1 << chn; +} + +void analogout_free(dac_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Channel-level windup from here */ + + /* Mark channel free */ + dac_modinit_mask[modidx] &= ~(1 << modidx); + + /* Close channel */ + DAC_Close(dac_base, chn); + + /* Module-level windup from here: */ + + /* See analogout_init() for reason */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + + /* Disable IP clock */ + CLK_DisableModuleClock(modinit->clkidx); + } +} + +void analogout_write(dac_t *obj, float value) +{ + if (value <= 0.0f) { + analogout_write_u16(obj, 0); + } else if (value >= 1.0f) { + analogout_write_u16(obj, 0xFFFF); + } else { + analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF))); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + DAC_WRITE_DATA(dac_base, chn, value); + + /* Clear the DAC conversion complete finish flag for safe */ + DAC_CLR_INT_FLAG(dac_base, chn); + + /* Start A/D conversion */ + DAC_START_CONV(dac_base); + + /* Wait for completed */ + while (DAC_IS_BUSY(dac_base, chn)); +} + +float analogout_read(dac_t *obj) +{ + uint32_t value = analogout_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + uint16_t dat12_4 = DAC_READ_DATA(dac_base, chn); + /* Just 12 bits are effective. Convert to 16 bits. + * + * dat12_4 : b11b10b9b8 b7b6b5b4 b3b2b1b0 0000 + * dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + */ + uint16_t dat16 = (dat12_4 & 0xFFF0) | (dat12_4 >> 12); + + return dat16; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp similarity index 78% rename from targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c rename to targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp index 87af3a9271..36292622b5 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.cpp @@ -19,26 +19,48 @@ #include "mbed_assert.h" #include "mbed_critical.h" #include "mbed_error.h" +#include "cmsis_os2.h" +#include "mbed_rtos_storage.h" +#include #include #include "nu_modutil.h" #include "nu_bitutil.h" #include "crypto-misc.h" +#include "SingletonPtr.h" +#include "Mutex.h" + +/* Consideration for choosing proper synchronization mechanism + * + * 1. We choose mutex to synchronize access to crypto non-SHA AC. We can guarantee: + * (1) No deadlock + * We just lock mutex for a short sequence of operations rather than the whole lifetime + * of crypto context. + * (2) No priority inversion + * Mutex supports priority inheritance and it is enabled. + * 2. We choose atomic flag to synchronize access to crypto SHA AC. We can guarantee: + * (1) No deadlock + * With SHA AC not supporting context save & restore, we provide SHA S/W fallback when + * SHA AC is not available. + * (2) No biting CPU + * Same reason as above. + */ + +/* Mutex for crypto AES AC management */ +static SingletonPtr crypto_aes_mutex; + +/* Mutex for crypto DES AC management */ +static SingletonPtr crypto_des_mutex; + +/* Mutex for crypto ECC AC management */ +static SingletonPtr crypto_ecc_mutex; + +/* Atomic flag for crypto SHA AC management */ +static core_util_atomic_flag crypto_sha_atomic_flag = CORE_UTIL_ATOMIC_FLAG_INIT; -/* Track if AES H/W is available */ -static uint16_t crypto_aes_avail = 1; -/* Track if DES H/W is available */ -static uint16_t crypto_des_avail = 1; -/* Track if SHA H/W is available */ -static uint16_t crypto_sha_avail = 1; -/* Track if ECC H/W is available */ -static uint16_t crypto_ecc_avail = 1; /* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ static uint16_t crypto_init_counter = 0U; -static bool crypto_submodule_acquire(uint16_t *submodule_avail); -static void crypto_submodule_release(uint16_t *submodule_avail); - /* Crypto done flags */ #define CRYPTO_DONE_OK BIT0 /* Done with OK */ #define CRYPTO_DONE_ERR BIT1 /* Done with error */ @@ -119,44 +141,52 @@ void crypto_zeroize32(uint32_t *v, size_t n) } } -bool crypto_aes_acquire(void) +void crypto_aes_acquire(void) { - return crypto_submodule_acquire(&crypto_aes_avail); + /* Don't check return code of Mutex::lock(void) + * + * This function treats RTOS errors as fatal system errors, so it can only return osOK. + * Use of the return value is deprecated, as the return is expected to become void in + * the future. + */ + crypto_aes_mutex->lock(); } void crypto_aes_release(void) { - crypto_submodule_release(&crypto_aes_avail); + crypto_aes_mutex->unlock(); } -bool crypto_des_acquire(void) +void crypto_des_acquire(void) { - return crypto_submodule_acquire(&crypto_des_avail); + /* Don't check return code of Mutex::lock(void) */ + crypto_des_mutex->lock(); } void crypto_des_release(void) { - crypto_submodule_release(&crypto_des_avail); + crypto_des_mutex->unlock(); } -bool crypto_sha_acquire(void) +void crypto_ecc_acquire(void) { - return crypto_submodule_acquire(&crypto_sha_avail); -} - -void crypto_sha_release(void) -{ - crypto_submodule_release(&crypto_sha_avail); -} - -bool crypto_ecc_acquire(void) -{ - return crypto_submodule_acquire(&crypto_ecc_avail); + /* Don't check return code of Mutex::lock(void) */ + crypto_ecc_mutex->lock(); } void crypto_ecc_release(void) { - crypto_submodule_release(&crypto_ecc_avail); + crypto_ecc_mutex->unlock(); +} + +bool crypto_sha_try_acquire(void) +{ + return !core_util_atomic_flag_test_and_set(&crypto_sha_atomic_flag); +} + +void crypto_sha_release(void) +{ + core_util_atomic_flag_clear(&crypto_sha_atomic_flag); } void crypto_prng_prestart(void) @@ -240,18 +270,6 @@ bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const vo return overlap; } -static bool crypto_submodule_acquire(uint16_t *submodule_avail) -{ - uint16_t expectedCurrentValue = 1; - return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0); -} - -static void crypto_submodule_release(uint16_t *submodule_avail) -{ - uint16_t expectedCurrentValue = 0; - while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); -} - static void crypto_submodule_prestart(volatile uint16_t *submodule_done) { *submodule_done = 0; @@ -285,7 +303,7 @@ static bool crypto_submodule_wait(volatile uint16_t *submodule_done) } /* Crypto interrupt handler */ -void CRYPTO_IRQHandler() +extern "C" void CRYPTO_IRQHandler() { uint32_t intsts; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h index 9aa1ff8121..15c377a48a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h @@ -32,26 +32,33 @@ void crypto_uninit(void); void crypto_zeroize(void *v, size_t n); void crypto_zeroize32(uint32_t *v, size_t n); -/* Acquire/release ownership of AES H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_aes_acquire(void); +/* Acquire/release ownership of crypto sub-module + * + * \note "acquire" is blocking until ownership is acquired + * + * \note "acquire"/"release" must be paired. + * + * \note Recursive "acquire" is allowed because the underlying synchronization + * primitive mutex supports it. + */ +void crypto_aes_acquire(void); void crypto_aes_release(void); - -/* Acquire/release ownership of DES H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_des_acquire(void); +void crypto_des_acquire(void); void crypto_des_release(void); - -/* Acquire/release ownership of SHA H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_sha_acquire(void); -void crypto_sha_release(void); - -/* Acquire/release ownership of ECC H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_ecc_acquire(void); +void crypto_ecc_acquire(void); void crypto_ecc_release(void); +/* Acquire/release ownership of crypto sub-module + * + * \return false if crytpo sub-module is held by another thread or + * another mbedtls context. + * true if successful + * + * \note Successful "try_acquire" and "release" must be paired. + */ +bool crypto_sha_try_acquire(void); +void crypto_sha_release(void); + /* Flow control between crypto/xxx start and crypto/xxx ISR * * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct index d81caeb2a8..7396955d3b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct @@ -8,17 +8,14 @@ #define MBED_APP_SIZE 0x00080000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + + #define SPIM_CCM_START 0x20020000 #define SPIM_CCM_END 0x20028000 -#define MBED_RAM_START 0x20000000 -#define MBED_RAM_SIZE 0x20000 -#define MBED_STACK_RAM_START (MBED_RAM_START) -#define MBED_STACK_RAM_SIZE 0x800 -#define MBED_VECTTABLE_RAM_START (MBED_STACK_RAM_START + MBED_STACK_RAM_SIZE) -#define MBED_VECTTABLE_RAM_SIZE (4*(16 + 96)) -#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) -#define MBED_CRASH_REPORT_RAM_SIZE 0x100 LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address @@ -26,15 +23,19 @@ LR_IROM1 MBED_APP_START { *(InRoot$$Sections) .ANY (+RO) } - - - ARM_LIB_STACK MBED_STACK_RAM_START EMPTY MBED_STACK_RAM_SIZE { + + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { + } + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 96)) { ; Reserve for vectors } - ER_IRAMVEC MBED_VECTTABLE_RAM_START EMPTY MBED_VECTTABLE_RAM_SIZE { ; Reserve for vectors - } - - RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; Reserve for crash data storage + RW_m_crash_data AlignExpr(+0, 0x100) EMPTY 0x100 { ; Reserve for crash data storage } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/M487.sct b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/M487.sct index d81caeb2a8..7396955d3b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/M487.sct +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_STD/M487.sct @@ -8,17 +8,14 @@ #define MBED_APP_SIZE 0x00080000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + + #define SPIM_CCM_START 0x20020000 #define SPIM_CCM_END 0x20028000 -#define MBED_RAM_START 0x20000000 -#define MBED_RAM_SIZE 0x20000 -#define MBED_STACK_RAM_START (MBED_RAM_START) -#define MBED_STACK_RAM_SIZE 0x800 -#define MBED_VECTTABLE_RAM_START (MBED_STACK_RAM_START + MBED_STACK_RAM_SIZE) -#define MBED_VECTTABLE_RAM_SIZE (4*(16 + 96)) -#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) -#define MBED_CRASH_REPORT_RAM_SIZE 0x100 LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address @@ -26,15 +23,19 @@ LR_IROM1 MBED_APP_START { *(InRoot$$Sections) .ANY (+RO) } - - - ARM_LIB_STACK MBED_STACK_RAM_START EMPTY MBED_STACK_RAM_SIZE { + + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { + } + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 96)) { ; Reserve for vectors } - ER_IRAMVEC MBED_VECTTABLE_RAM_START EMPTY MBED_VECTTABLE_RAM_SIZE { ; Reserve for vectors - } - - RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; Reserve for crash data storage + RW_m_crash_data AlignExpr(+0, 0x100) EMPTY 0x100 { ; Reserve for crash data storage } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/M487.ld b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/M487.ld index c1336b909c..ff6b07dabc 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/M487.ld +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_GCC_ARM/M487.ld @@ -10,8 +10,12 @@ #define MBED_APP_SIZE 0x00080000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + M_CRASH_DATA_RAM_SIZE = 0x100; -StackSize = 0x800; +StackSize = MBED_BOOT_STACK_SIZE; SPIM_CCM_START = 0x20020000; SPIM_CCM_END = 0x20028000; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_IAR/M487.icf b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_IAR/M487.icf index 05376f3712..3efed8ee84 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_IAR/M487.icf +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_IAR/M487.icf @@ -3,6 +3,7 @@ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; } +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ @@ -11,7 +12,7 @@ define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20028000 - 1; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __ICFEDIT_size_crash_data__ = 0x100; define symbol __ICFEDIT_size_intvec__ = (4 * (16 + 96)); define symbol __ICFEDIT_size_heap__ = 0x10000; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/objects.h b/targets/TARGET_NUVOTON/TARGET_M480/objects.h index e3d24534d8..069bef397c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/objects.h @@ -48,10 +48,12 @@ struct analogin_s { //PinName pin; }; +struct dac_s { + DACName dac; +}; + struct serial_s { UARTName uart; - PinName pin_tx; - PinName pin_rx; uint32_t baudrate; uint32_t databits; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c index dcb24294d1..356ebcb599 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c @@ -200,29 +200,35 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; if (! var->ref_cnt) { - do { - // Reset this module - SYS_ResetModule(modinit->rsetidx); + // Reset this module + SYS_ResetModule(modinit->rsetidx); - // Select IP clock source - CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); - // Enable IP clock - CLK_EnableModuleClock(modinit->clkidx); + // Select IP clock source + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - } while (0); + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); - obj->serial.pin_tx = tx; - obj->serial.pin_rx = rx; + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); } var->ref_cnt ++; - // Configure the UART module and set its baudrate - serial_baud(obj, 9600); - // Configure data bits, parity, and stop bits - serial_format(obj, 8, ParityNone, 1); - obj->serial.vec = var->vec; obj->serial.irq_en = 0; @@ -234,10 +240,12 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; #endif - // For stdio management - if (obj->serial.uart == STDIO_UART) { + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); } if (var->ref_cnt) { @@ -283,7 +291,9 @@ void serial_free(serial_t *obj) var->obj = NULL; } - if (obj->serial.uart == STDIO_UART) { + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 0; } diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralNames.h index 1463866444..60f57d63b7 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralNames.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralNames.h @@ -61,6 +61,11 @@ typedef enum { ADC_0_11 = (int) NU_MODNAME(ADC_BASE, 0, 11), } ADCName; +typedef enum { + DAC_0_0 = (int) NU_MODNAME(DAC_BASE, 0, 0), + DAC_0_1 = (int) NU_MODNAME(DAC_BASE, 0, 1) +} DACName; + typedef enum { UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.c index e66e3e2453..b8f7caad94 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.c @@ -35,6 +35,15 @@ const PinMap PinMap_ADC[] = { {NC, NC, 0} }; +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PC_6, DAC_0_0, SYS_PC_L_MFP_PC6_MFP_DA_OUT0}, + {PC_7, DAC_0_1, SYS_PC_L_MFP_PC7_MFP_DA_OUT1}, + + {NC, NC, 0} +}; + //*** I2C *** const PinMap PinMap_I2C_SDA[] = { diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.h index a3018b5a40..f7e23d0e7b 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/PeripheralPins.h @@ -34,6 +34,10 @@ extern const PinMap PinMap_GPIO[]; extern const PinMap PinMap_ADC[]; +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + //*** I2C *** extern const PinMap PinMap_I2C_SDA[]; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/analogout_api.c new file mode 100644 index 0000000000..a1e332888b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/analogout_api.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2018, Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" + +/* Maximum DAC modules */ +#define NU_DACMOD_MAXNUM 1 +/* Maximum DAC channels per module */ +#define NU_DACCHN_MAXNUM 2 + +static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM]; + +static const struct nu_modinit_s dac_modinit_tab[] = { + {DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL}, + {DAC_0_1, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Module-level setup from here */ + + if (! dac_modinit_mask[modidx]) { + /* Reset IP */ + SYS_ResetModule(modinit->rsetidx); + + /* Select IP clock source and clock divider */ + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock */ + CLK_EnableModuleClock(modinit->clkidx); + + /* Configure conversion settling time + * + * DAC_Open() is per-channel, but its implementation involves per-module configuration of + * conversion settling time. Even so, we still use it for default conversion settling time + * rather than call per-module DAC_SetDelayTime(). This is to accommodate BSP driver. + * + * To configure conversion settling time separately to e.g. 8us, we would call: + * + * DAC_SetDelayTime(dac_base, CLK_GetHCLKFreq() * 8 / 1000000); + */ + } + + /* Channel-level setup from here: */ + + /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ + DAC_Open(dac_base, chn, DAC_WRITE_DAT_TRIGGER); + + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + + /* Mark channel allocated */ + dac_modinit_mask[modidx] |= 1 << chn; +} + +void analogout_free(dac_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Channel-level windup from here */ + + /* Mark channel free */ + dac_modinit_mask[modidx] &= ~(1 << modidx); + + /* Close channel */ + DAC_Close(dac_base, chn); + + /* Module-level windup from here: */ + + if (! dac_modinit_mask[modidx]) { + + /* Disable IP clock */ + CLK_DisableModuleClock(modinit->clkidx); + } +} + +void analogout_write(dac_t *obj, float value) +{ + if (value <= 0.0f) { + analogout_write_u16(obj, 0); + } else if (value >= 1.0f) { + analogout_write_u16(obj, 0xFFFF); + } else { + analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF))); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* Convert 16 bits to effective 12 bits by dropping 4 LSB bits. */ + DAC_WRITE_DATA(dac_base, chn, value >> 4); + + /* Wait for completed */ + while (DAC_IS_BUSY(dac_base, chn)); +} + +float analogout_read(dac_t *obj) +{ + uint32_t value = analogout_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + uint16_t dat12 = chn ? dac_base->DATA1 : dac_base->DATA0; + dat12 = (dat12 & DAC_DATA_DACData_Msk) >> DAC_DATA_DACData_Pos; + /* Just 12 bits are effective. Convert to 16 bits. + * + * dat12 : 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0 + * dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + */ + uint16_t dat16 = (dat12 << 4) | (dat12 >> 8); + + return dat16; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct index 2cdd8c2fdb..97f76f6675 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct @@ -1,3 +1,8 @@ +#! armcc -E + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif LR_IROM1 0x00000000 { ER_IROM1 0x00000000 { ; load address = execution address @@ -7,7 +12,7 @@ LR_IROM1 0x00000000 { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/NANO130.sct b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/NANO130.sct index 2cdd8c2fdb..97f76f6675 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/NANO130.sct +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_STD/NANO130.sct @@ -1,3 +1,8 @@ +#! armcc -E + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif LR_IROM1 0x00000000 { ER_IROM1 0x00000000 { ; load address = execution address @@ -7,7 +12,7 @@ LR_IROM1 0x00000000 { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/NANO130.ld b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/NANO130.ld index 6dd4a15dd1..a919b7c869 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/NANO130.ld +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_GCC_ARM/NANO130.ld @@ -2,7 +2,11 @@ * Nuvoton NANO130 GCC linker script file */ -StackSize = 0x600; +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +StackSize = MBED_BOOT_STACK_SIZE; MEMORY { diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf index 7fb8481140..405970ed4c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_IAR/NANO130.icf @@ -1,6 +1,7 @@ /*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x00000000; /*-Memory Regions-*/ @@ -9,7 +10,7 @@ define symbol __ICFEDIT_region_ROM_end__ = 0x00020000 - 1; define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20004000 - 1; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __ICFEDIT_size_heap__ = 0xC00; /**** End of ICF editor section. ###ICF###*/ diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/objects.h b/targets/TARGET_NUVOTON/TARGET_NANO100/objects.h index 12476fd7c1..1ecf15f8fc 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/objects.h @@ -44,10 +44,12 @@ struct analogin_s { ADCName adc; }; +struct dac_s { + DACName dac; +}; + struct serial_s { UARTName uart; - PinName pin_tx; - PinName pin_rx; uint32_t baudrate; uint32_t databits; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c index 216f34d4bb..447d8fb5d8 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c @@ -137,7 +137,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) if (! var->ref_cnt) { // Reset this module SYS_ResetModule(modinit->rsetidx); - + // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock @@ -145,20 +145,28 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); - - obj->serial.pin_tx = tx; - obj->serial.pin_rx = rx; + + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); } var->ref_cnt ++; - - // Configure the UART module and set its baudrate - serial_baud(obj, 9600); - // Configure data bits, parity, and stop bits - serial_format(obj, 8, ParityNone, 1); - + obj->serial.vec = var->vec; obj->serial.irq_en = 0; - + #if DEVICE_SERIAL_ASYNCH obj->serial.dma_usage_tx = DMA_USAGE_NEVER; obj->serial.dma_usage_rx = DMA_USAGE_NEVER; @@ -167,12 +175,14 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; #endif - // For stdio management - if (obj->serial.uart == STDIO_UART) { + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); } - + if (var->ref_cnt) { // Mark this module to be inited. int i = modinit - uart_modinit_tab; @@ -213,11 +223,13 @@ void serial_free(serial_t *obj) if (var->obj == obj) { var->obj = NULL; } - - if (obj->serial.uart == STDIO_UART) { + + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 0; } - + if (! var->ref_cnt) { // Mark this module to be deinited. int i = modinit - uart_modinit_tab; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp similarity index 77% rename from targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c rename to targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp index c9cdc1098e..6653e37b4f 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.cpp @@ -19,24 +19,45 @@ #include "mbed_assert.h" #include "mbed_critical.h" #include "mbed_error.h" +#include "cmsis_os2.h" +#include "mbed_rtos_storage.h" +#include #include #include "nu_modutil.h" #include "nu_bitutil.h" #include "crypto-misc.h" +#include "SingletonPtr.h" +#include "Mutex.h" + +/* Consideration for choosing proper synchronization mechanism + * + * 1. We choose mutex to synchronize access to crypto non-SHA AC. We can guarantee: + * (1) No deadlock + * We just lock mutex for a short sequence of operations rather than the whole lifetime + * of crypto context. + * (2) No priority inversion + * Mutex supports priority inheritance and it is enabled. + * 2. We choose atomic flag to synchronize access to crypto SHA AC. We can guarantee: + * (1) No deadlock + * With SHA AC not supporting context save & restore, we provide SHA S/W fallback when + * SHA AC is not available. + * (2) No biting CPU + * Same reason as above. + */ + +/* Mutex for crypto AES AC management */ +static SingletonPtr crypto_aes_mutex; + +/* Mutex for crypto DES AC management */ +static SingletonPtr crypto_des_mutex; + +/* Atomic flag for crypto SHA AC management */ +static core_util_atomic_flag crypto_sha_atomic_flag = CORE_UTIL_ATOMIC_FLAG_INIT; -/* Track if AES H/W is available */ -static uint16_t crypto_aes_avail = 1; -/* Track if DES H/W is available */ -static uint16_t crypto_des_avail = 1; -/* Track if SHA H/W is available */ -static uint16_t crypto_sha_avail = 1; /* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ static uint16_t crypto_init_counter = 0U; -static bool crypto_submodule_acquire(uint16_t *submodule_avail); -static void crypto_submodule_release(uint16_t *submodule_avail); - /* Crypto done flags */ #define CRYPTO_DONE_OK BIT0 /* Done with OK */ #define CRYPTO_DONE_ERR BIT1 /* Done with error */ @@ -106,34 +127,41 @@ void crypto_zeroize(void *v, size_t n) } } -bool crypto_aes_acquire(void) +void crypto_aes_acquire(void) { - return crypto_submodule_acquire(&crypto_aes_avail); + /* Don't check return code of Mutex::lock(void) + * + * This function treats RTOS errors as fatal system errors, so it can only return osOK. + * Use of the return value is deprecated, as the return is expected to become void in + * the future. + */ + crypto_aes_mutex->lock(); } void crypto_aes_release(void) { - crypto_submodule_release(&crypto_aes_avail); + crypto_aes_mutex->unlock(); } -bool crypto_des_acquire(void) +void crypto_des_acquire(void) { - return crypto_submodule_acquire(&crypto_des_avail); + /* Don't check return code of Mutex::lock(void) */ + crypto_des_mutex->lock(); } void crypto_des_release(void) { - crypto_submodule_release(&crypto_des_avail); + crypto_des_mutex->unlock(); } -bool crypto_sha_acquire(void) +bool crypto_sha_try_acquire(void) { - return crypto_submodule_acquire(&crypto_sha_avail); + return !core_util_atomic_flag_test_and_set(&crypto_sha_atomic_flag); } void crypto_sha_release(void) { - crypto_submodule_release(&crypto_sha_avail); + core_util_atomic_flag_clear(&crypto_sha_atomic_flag); } void crypto_prng_prestart(void) @@ -207,18 +235,6 @@ bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const vo return overlap; } -static bool crypto_submodule_acquire(uint16_t *submodule_avail) -{ - uint16_t expectedCurrentValue = 1; - return core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 0); -} - -static void crypto_submodule_release(uint16_t *submodule_avail) -{ - uint16_t expectedCurrentValue = 0; - while (! core_util_atomic_cas_u16(submodule_avail, &expectedCurrentValue, 1)); -} - static void crypto_submodule_prestart(volatile uint16_t *submodule_done) { *submodule_done = 0; @@ -252,7 +268,7 @@ static bool crypto_submodule_wait(volatile uint16_t *submodule_done) } /* Crypto interrupt handler */ -void CRYPTO_IRQHandler() +extern "C" void CRYPTO_IRQHandler() { uint32_t intsts; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h index f2cc89797f..09b5726658 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h @@ -31,19 +31,29 @@ void crypto_uninit(void); * Implementation that should never be optimized out by the compiler */ void crypto_zeroize(void *v, size_t n); -/* Acquire/release ownership of AES H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_aes_acquire(void); +/* Acquire/release ownership of crypto sub-module + * + * \note "acquire" is blocking until ownership is acquired + * + * \note "acquire"/"release" must be paired. + * + * \note Recursive "acquire" is allowed because the underlying synchronization + * primitive mutex supports it. + */ +void crypto_aes_acquire(void); void crypto_aes_release(void); - -/* Acquire/release ownership of DES H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_des_acquire(void); +void crypto_des_acquire(void); void crypto_des_release(void); -/* Acquire/release ownership of SHA H/W */ -/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ -bool crypto_sha_acquire(void); +/* Acquire/release ownership of crypto sub-module + * + * \return false if crytpo sub-module is held by another thread or + * another mbedtls context. + * true if successful + * + * \note Successful "try_acquire" and "release" must be paired. + */ +bool crypto_sha_try_acquire(void); void crypto_sha_release(void); /* Flow control between crypto/xxx start and crypto/xxx ISR diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.c index 2262de8dfa..790c9405d6 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.c @@ -75,6 +75,8 @@ void CLK_PowerDown(void) SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWKDLY_Msk ); __WFI(); + __DSB(); + __ISB(); } /** @@ -92,6 +94,8 @@ void CLK_Idle(void) /* Chip enter idle mode after CPU run WFI instruction */ __WFI(); + __DSB(); + __ISB(); } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct index 1f2e2c6ce5..599051ecf6 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct @@ -8,6 +8,10 @@ #define MBED_APP_SIZE 0x00080000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address *(RESET, +First) @@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } - - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 1024) EMPTY (4*(16 + 142)) { ; Reserve for vectors } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct index 6a05f0468f..da85bc834d 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct @@ -8,6 +8,10 @@ #define MBED_APP_SIZE 0x00080000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address *(RESET, +First) @@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } - - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 1024) EMPTY (4*(16 + 142)) { ; Reserve for vectors } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct index d2c38ebf5c..6c81632bc0 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_SUPPORTED/NUC472.sct @@ -8,6 +8,10 @@ #define MBED_APP_SIZE 0x00080000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address *(RESET, +First) @@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } - - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 1024) EMPTY (4*(16 + 142)) { ; Reserve for vectors } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct index 6a05f0468f..da85bc834d 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct @@ -8,6 +8,10 @@ #define MBED_APP_SIZE 0x00080000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + LR_IROM1 MBED_APP_START { ER_IROM1 MBED_APP_START { ; load address = execution address *(RESET, +First) @@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START { } - ARM_LIB_STACK 0x20000000 EMPTY 0x800 { + ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE { } - - ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 1024) EMPTY (4*(16 + 142)) { ; Reserve for vectors } RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld index 14a75161da..73c54b5707 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_SUPPORTED/NUC472.ld @@ -10,7 +10,11 @@ #define MBED_APP_SIZE 0x00080000 #endif -StackSize = 0x800; +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +StackSize = MBED_BOOT_STACK_SIZE; MEMORY { diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld index 5c9c3a0af6..e11e7e5b59 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/TARGET_NU_XRAM_UNSUPPORTED/NUC472.ld @@ -9,8 +9,12 @@ #if !defined(MBED_APP_SIZE) #define MBED_APP_SIZE 0x00080000 #endif - -StackSize = 0x800; + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +StackSize = MBED_BOOT_STACK_SIZE; MEMORY { diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf index d82e9459c5..82b687f75a 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_SUPPORTED/NUC472_442.icf @@ -3,6 +3,7 @@ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; } +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ @@ -13,7 +14,7 @@ define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000 - 1; define symbol __ICFEDIT_region_XRAM_start__ = 0x60000000; define symbol __ICFEDIT_region_XRAM_end__ = 0x60100000 - 1; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __ICFEDIT_size_heap__ = 0xC0000; /**** End of ICF editor section. ###ICF###*/ diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf index 0aae6f9b30..7f47046795 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/TARGET_NU_XRAM_UNSUPPORTED/NUC472_442.icf @@ -3,6 +3,7 @@ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00080000; } +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ @@ -11,7 +12,7 @@ define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000 - 1; /*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __ICFEDIT_size_heap__ = 0x8000; /**** End of ICF editor section. ###ICF###*/ diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/objects.h b/targets/TARGET_NUVOTON/TARGET_NUC472/objects.h index da3db2d54b..d5cb22da83 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/objects.h @@ -50,8 +50,6 @@ struct analogin_s { struct serial_s { UARTName uart; - PinName pin_tx; - PinName pin_rx; uint32_t baudrate; uint32_t databits; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c index fa6240a39f..002f23ef48 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c @@ -202,7 +202,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) if (! var->ref_cnt) { // Reset this module SYS_ResetModule(modinit->rsetidx); - + // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock @@ -210,17 +210,25 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); - - obj->serial.pin_tx = tx; - obj->serial.pin_rx = rx; + + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); } var->ref_cnt ++; - - // Configure the UART module and set its baudrate - serial_baud(obj, 9600); - // Configure data bits, parity, and stop bits - serial_format(obj, 8, ParityNone, 1); - + obj->serial.vec = var->vec; obj->serial.irq_en = 0; @@ -232,12 +240,14 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; #endif - // For stdio management - if (obj->serial.uart == STDIO_UART) { + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); } - + if (var->ref_cnt) { // Mark this module to be inited. int i = modinit - uart_modinit_tab; @@ -278,11 +288,13 @@ void serial_free(serial_t *obj) if (var->obj == obj) { var->obj = NULL; } - - if (obj->serial.uart == STDIO_UART) { + + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); stdio_uart_inited = 0; } - + if (! var->ref_cnt) { // Mark this module to be deinited. int i = modinit - uart_modinit_tab; diff --git a/targets/TARGET_NUVOTON/mbed_rtx.h b/targets/TARGET_NUVOTON/mbed_rtx.h index 1b4e2b4986..137e4c1a24 100644 --- a/targets/TARGET_NUVOTON/mbed_rtx.h +++ b/targets/TARGET_NUVOTON/mbed_rtx.h @@ -45,13 +45,6 @@ #error "no toolchain defined" #endif -#if defined(TARGET_NANO100) -#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE -#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE -#endif -#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072 -#endif - #endif // TARGET_NUVOTON #endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp index fbbe1e9a20..07a3e54b76 100644 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp +++ b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp @@ -168,6 +168,4 @@ AFTER_VECTORS void DebugMon_Handler (void) {} AFTER_VECTORS void PendSV_Handler (void) {} AFTER_VECTORS void SysTick_Handler (void) {} AFTER_VECTORS void IntDefaultHandler (void) {} - -int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;} } diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld deleted file mode 100644 index fc2e202684..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld +++ /dev/null @@ -1,237 +0,0 @@ -/*Based on following file*/ -/* - * GENERATED FILE - DO NOT EDIT - * (c) Code Red Technologies Ltd, 2008-13 - * (c) NXP Semiconductors 2013-2014 - * Generated linker script file for LPC11U68 - * Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] )) - * By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014 - */ -GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) - -MEMORY -{ - /* Define each memory region */ - MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */ - Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */ - Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */ - Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */ - - -} - /* Define a symbol for the top of each memory region */ - __top_MFlash256 = 0x0 + 0x40000; - __top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100; - __top_Ram1_2 = 0x20000000 + 0x800; - __top_Ram2USB_2 = 0x20004000 + 0x800; - -ENTRY(ResetISR) - -SECTIONS -{ - - /* MAIN TEXT SECTION */ - .text : ALIGN(8) - { - FILL(0xff) - KEEP(*(.isr_vector)) - *(.text.ResetISR) - *(.text.SystemInit) - - /* Global Section Table */ - . = ALIGN(8) ; - __section_table_start = .; - __data_section_table = .; - LONG(LOADADDR(.data)); - LONG( ADDR(.data)); - LONG( SIZEOF(.data)); - LONG(LOADADDR(.data_RAM2)); - LONG( ADDR(.data_RAM2)); - LONG( SIZEOF(.data_RAM2)); - LONG(LOADADDR(.data_RAM3)); - LONG( ADDR(.data_RAM3)); - LONG( SIZEOF(.data_RAM3)); - __data_section_table_end = .; - __bss_section_table = .; - LONG( ADDR(.bss)); - LONG( SIZEOF(.bss)); - LONG( ADDR(.bss_RAM2)); - LONG( SIZEOF(.bss_RAM2)); - LONG( ADDR(.bss_RAM3)); - LONG( SIZEOF(.bss_RAM3)); - __bss_section_table_end = .; - __section_table_end = . ; - /* End of Global Section Table */ - - - *(.after_vectors*) - - *(.text*) - *(.rodata .rodata.*) - . = ALIGN(8); - - /* C++ constructors etc */ - . = ALIGN(8); - KEEP(*(.init)) - - . = ALIGN(8); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(8); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - KEEP(*(.fini)); - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > MFlash256 - - /* - * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. - */ - .ARM.extab : ALIGN(8) - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > MFlash256 - __exidx_start = .; - - .ARM.exidx : ALIGN(8) - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > MFlash256 - __exidx_end = .; - - _etext = .; - - /* possible MTB section for Ram1_2 */ - .mtb_buffer_RAM2 (NOLOAD) : - { - KEEP(*(.mtb.$RAM2*)) - KEEP(*(.mtb.$RAM1_2*)) - } > Ram1_2 - - /* DATA section for Ram1_2 */ - .data_RAM2 : ALIGN(8) - { - FILL(0xff) - *(.ramfunc.$RAM2) - *(.ramfunc.$Ram1_2) - *(.data.$RAM2*) - *(.data.$Ram1_2*) - . = ALIGN(8) ; - } > Ram1_2 AT>MFlash256 - /* possible MTB section for Ram2USB_2 */ - .mtb_buffer_RAM3 (NOLOAD) : - { - KEEP(*(.mtb.$RAM3*)) - KEEP(*(.mtb.$RAM2USB_2*)) - } > Ram2USB_2 - - /* DATA section for Ram2USB_2 */ - .data_RAM3 : ALIGN(8) - { - FILL(0xff) - *(.ramfunc.$RAM3) - *(.ramfunc.$Ram2USB_2) - *(.data.$RAM3*) - *(.data.$Ram2USB_2*) - . = ALIGN(8) ; - } > Ram2USB_2 AT>MFlash256 - - /* MAIN DATA SECTION */ - - /* Default MTB section */ - .mtb_buffer_default (NOLOAD) : - { - KEEP(*(.mtb*)) - } > Ram0_32 - - .uninit_RESERVED : ALIGN(8) - { - KEEP(*(.bss.$RESERVED*)) - . = ALIGN(8) ; - _end_uninit_RESERVED = .; - } > Ram0_32 - - - /* Main DATA section (Ram0_32) */ - .data : ALIGN(8) - { - FILL(0xff) - _data = . ; - *(vtable) - *(.ramfunc*) - *(.data*) - . = ALIGN(8) ; - _edata = . ; - } > Ram0_32 AT>MFlash256 - - /* BSS section for Ram1_2 */ - .bss_RAM2 : ALIGN(8) - { - *(.bss.$RAM2*) - *(.bss.$Ram1_2*) - . = ALIGN(8) ; - } > Ram1_2 - /* BSS section for Ram2USB_2 */ - .bss_RAM3 : ALIGN(8) - { - *(.bss.$RAM3*) - *(.bss.$Ram2USB_2*) - . = ALIGN(8) ; - } > Ram2USB_2 - - /* MAIN BSS SECTION */ - .bss : ALIGN(8) - { - _bss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8) ; - _ebss = .; - PROVIDE(end = .); - __end__ = .; - } > Ram0_32 - - /* NOINIT section for Ram1_2 */ - .noinit_RAM2 (NOLOAD) : ALIGN(8) - { - *(.noinit.$RAM2*) - *(.noinit.$Ram1_2*) - . = ALIGN(8) ; - } > Ram1_2 - /* NOINIT section for Ram2USB_2 */ - .noinit_RAM3 (NOLOAD) : ALIGN(8) - { - *(.noinit.$RAM3*) - *(.noinit.$Ram2USB_2*) - . = ALIGN(8) ; - } > Ram2USB_2 - - /* DEFAULT NOINIT SECTION */ - .noinit (NOLOAD): ALIGN(8) - { - _noinit = .; - *(.noinit*) - . = ALIGN(8) ; - _end_noinit = .; - } > Ram0_32 - - PROVIDE(_pvHeapStart = .); - PROVIDE(_vStackTop = __top_Ram0_32 - 0); -} diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.S b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.S deleted file mode 100644 index bbbf1e946d..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.S +++ /dev/null @@ -1,93 +0,0 @@ -//***************************************************************************** -// aeabi_romdiv_patch.s -// - Provides "patch" versions of the aeabi integer divide functions to -// replace the standard ones pulled in from the C library, which vector -// integer divides onto the rom division functions contained in -// specific NXP MCUs such as LPC11Uxx and LPC12xx. -// - Note that this patching will only occur if "__USE_ROMDIVIDE" is -// defined for the project build for both the compiler and assembler. -//***************************************************************************** -// -// Copyright(C) NXP Semiconductors, 2013 -// All rights reserved. -// -// Software that is described herein is for illustrative purposes only -// which provides customers with programming information regarding the -// LPC products. This software is supplied "AS IS" without any warranties of -// any kind, and NXP Semiconductors and its licensor disclaim any and -// all warranties, express or implied, including all implied warranties of -// merchantability, fitness for a particular purpose and non-infringement of -// intellectual property rights. NXP Semiconductors assumes no responsibility -// or liability for the use of the software, conveys no license or rights under any -// patent, copyright, mask work right, or any other intellectual property rights in -// or to any products. NXP Semiconductors reserves the right to make changes -// in the software without notification. NXP Semiconductors also makes no -// representation or warranty that such application will be suitable for the -// specified use without further testing or modification. -// -// Permission to use, copy, modify, and distribute this software and its -// documentation is hereby granted, under NXP Semiconductors' and its -// licensor's relevant copyrights in the software, without fee, provided that it -// is used in conjunction with NXP Semiconductors microcontrollers. This -// copyright, permission, and disclaimer notice must appear in all copies of -// this code. -//***************************************************************************** -#if defined(__USE_ROMDIVIDE) - -// Note that the romdivide "divmod" functions are not actually called from -// the below code, as these functions are actually just wrappers to the -// main romdivide "div" functions which push the quotient and remainder onto -// the stack, so as to be compatible with the way that C returns structures. -// -// This is not needed for the aeabi "divmod" functions, as the compiler -// automatically generates code that handles the return values being passed -// back in registers when it generates inline calls to __aeabi_idivmod and -// __aeabi_uidivmod routines. - - .syntax unified - .text - -// ========= __aeabi_idiv & __aeabi_idivmod ========= - .align 2 - .section .text.__aeabi_idiv - - .global __aeabi_idiv - .set __aeabi_idivmod, __aeabi_idiv // make __aeabi_uidivmod an alias - .global __aeabi_idivmod - .global pDivRom_idiv // pointer to the romdivide 'idiv' functione - .func - .thumb_func - .type __aeabi_idiv, %function - -__aeabi_idiv: - push {r4, lr} - ldr r3, =pDivRom_idiv - ldr r3, [r3, #0] // Load address of function - blx r3 // Call divide function - pop {r4, pc} - - .endfunc - -// ======== __aeabi_uidiv & __aeabi_uidivmod ======== - .align 2 - - .section .text.__aeabi_uidiv - - .global __aeabi_uidiv - .set __aeabi_uidivmod, __aeabi_uidiv // make __aeabi_uidivmod an alias - .global __aeabi_uidivmod - .global pDivRom_uidiv // pointer to the romdivide 'uidiv' function - .func - .thumb_func - .type __aeabi_uidiv, %function - -__aeabi_uidiv: - push {r4, lr} - ldr r3, =pDivRom_uidiv - ldr r3, [r3, #0] // Load address of function - blx r3 // Call divide function - pop {r4, pc} - - .endfunc - -#endif // (__USE_ROMDIVIDE) diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c deleted file mode 100644 index 089a4f5dc3..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c +++ /dev/null @@ -1,85 +0,0 @@ -//***************************************************************************** -// +--+ -// | ++----+ -// +-++ | -// | | -// +-+--+ | -// | +--+--+ -// +----+ Copyright (c) 2013 Code Red Technologies Ltd. -// -// mtb.c -// -// Optionally defines an array to be used as a buffer for Micro Trace -// Buffer (MTB) instruction trace on Cortex-M0+ parts -// -// Version : 130502 -// -// Software License Agreement -// -// The software is owned by Code Red Technologies and/or its suppliers, and is -// protected under applicable copyright laws. All rights are reserved. Any -// use in violation of the foregoing restrictions may subject the user to criminal -// sanctions under applicable laws, as well as to civil liability for the breach -// of the terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT -// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH -// CODE RED TECHNOLOGIES LTD. -// -//***************************************************************************** - -/******************************************************************* - * Symbols controlling behavior of this code... - * - * __MTB_DISABLE - * If this symbol is defined, then the buffer array for the MTB - * will not be created. - * - * __MTB_BUFFER_SIZE - * Symbol specifying the sizer of the buffer array for the MTB. - * This must be a power of 2 in size, and fit into the available - * RAM. The MTB buffer will also be aligned to its 'size' - * boundary and be placed at the start of a RAM bank (which - * should ensure minimal or zero padding due to alignment). - * - * __MTB_RAM_BANK - * Allows MTB Buffer to be placed into specific RAM bank. When - * this is not defined, the "default" (first if there are - * several) RAM bank is used. - *******************************************************************/ - -// Ignore with none Code Red tools -#if defined (__CODE_RED) - -// Allow MTB to be removed by setting a define (via command line) -#if !defined (__MTB_DISABLE) - - // Allow for MTB buffer size being set by define set via command line - // Otherwise provide small default buffer - #if !defined (__MTB_BUFFER_SIZE) - #define __MTB_BUFFER_SIZE 128 - #endif - - // Check that buffer size requested is >0 bytes in size - #if (__MTB_BUFFER_SIZE > 0) - // Pull in MTB related macros - #include - - // Check if MYTB buffer is to be placed in specific RAM bank - #if defined(__MTB_RAM_BANK) - // Place MTB buffer into explicit bank of RAM - __CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK); - #else - // Place MTB buffer into 'default' bank of RAM - __CR_MTB_BUFFER(__MTB_BUFFER_SIZE); - - #endif // defined(__MTB_RAM_BANK) - - #endif // (__MTB_BUFFER_SIZE > 0) - -#endif // !defined (__MTB_DISABLE) - -#endif // defined (__CODE_RED) diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp b/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp deleted file mode 100644 index 6faa114bc2..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp +++ /dev/null @@ -1,195 +0,0 @@ -extern "C" { - -#include "LPC11U6x.h" -#define WEAK __attribute__ ((weak)) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) -#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void); - -// Patch the AEABI integer divide functions to use MCU's romdivide library -#ifdef __USE_ROMDIVIDE -// Location in memory that holds the address of the ROM Driver table -#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8)) -// Variables to store addresses of idiv and udiv functions within MCU ROM -unsigned int *pDivRom_idiv; -unsigned int *pDivRom_uidiv; -#endif - - -extern unsigned int __data_section_table; -extern unsigned int __data_section_table_end; -extern unsigned int __bss_section_table; -extern unsigned int __bss_section_table_end; - - -extern void __libc_init_array(void); -extern int main(void); -extern void _vStackTop(void); -extern void (* const g_pfnVectors[])(void); - - void ResetISR(void); -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -WEAK void SVC_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); -WEAK void IntDefaultHandler(void); - -void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler); -void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler); -void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler); -void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler); -void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler); -void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler); -void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler); -void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler); -void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler); -void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler); -void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler); -void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler); -void USART0_IRQHandler (void) ALIAS(IntDefaultHandler); -void USB_IRQHandler (void) ALIAS(IntDefaultHandler); -void USB_FIQHandler (void) ALIAS(IntDefaultHandler); -void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler); -void RTC_IRQHandler (void) ALIAS(IntDefaultHandler); -void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler); -void FMC_IRQHandler (void) ALIAS(IntDefaultHandler); -void DMA_IRQHandler (void) ALIAS(IntDefaultHandler); -void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler); -void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler); - -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = { - // Core Level - CM0 - &_vStackTop, // The initial stack pointer - ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - 0, // Reserved - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - // Chip Level - LPC11U68 - PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0 - PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1 - PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2 - PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3 - PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4 - PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5 - PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6 - PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7 - GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt - GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt - I2C1_IRQHandler, // 10 - I2C1 - USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt - USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt - SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt - SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt - I2C0_IRQHandler, // 15 - I2C0 - TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0) - TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1) - TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0) - TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1) - SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt - USART0_IRQHandler, // 21 - USART0 - USB_IRQHandler, // 22 - USB IRQ - USB_FIQHandler, // 23 - USB FIQ - ADCA_IRQHandler, // 24 - ADC A(A/D Converter) - RTC_IRQHandler, // 25 - Real Time CLock interrpt - BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt - FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller - DMA_IRQHandler, // 28 - DMA interrupt - ADCB_IRQHandler, // 24 - ADC B (A/D Converter) - USBWakeup_IRQHandler, // 30 - USB wake-up interrupt - 0, // 31 - Reserved -}; -/* End Vector */ - -AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++; -} - -AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0; -} - - -/* Reset entry point*/ -extern "C" void software_init_hook(void); -extern "C" void pre_main(void) __attribute__((weak)); - -AFTER_VECTORS void ResetISR(void) { - unsigned int LoadAddr, ExeAddr, SectionLen; - unsigned int *SectionTableAddr; - - SectionTableAddr = &__data_section_table; - - while (SectionTableAddr < &__data_section_table_end) { - LoadAddr = *SectionTableAddr++; - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - data_init(LoadAddr, ExeAddr, SectionLen); - } - while (SectionTableAddr < &__bss_section_table_end) { - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - bss_init(ExeAddr, SectionLen); - } - - // Patch the AEABI integer divide functions to use MCU's romdivide library -#ifdef __USE_ROMDIVIDE - // Get address of Integer division routines function table in ROM - unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4]; - // Get addresses of integer divide routines in ROM - // These address are then used by the code in aeabi_romdiv_patch.s - pDivRom_idiv = (unsigned int *)div_ptr[0]; - pDivRom_uidiv = (unsigned int *)div_ptr[1]; -#endif - - - SystemInit(); - if (pre_main) { // give control to the RTOS - software_init_hook(); // this will also call __libc_init_array - } - else { // for BareMetal (non-RTOS) build - __libc_init_array(); - main(); - } - while (1) {;} -} - -AFTER_VECTORS void NMI_Handler (void) {} -AFTER_VECTORS void HardFault_Handler (void) {} -AFTER_VECTORS void MemManage_Handler (void) {} -AFTER_VECTORS void BusFault_Handler (void) {} -AFTER_VECTORS void UsageFault_Handler(void) {} -AFTER_VECTORS void SVC_Handler (void) {} -AFTER_VECTORS void DebugMon_Handler (void) {} -AFTER_VECTORS void PendSV_Handler (void) {} -AFTER_VECTORS void SysTick_Handler (void) {} -AFTER_VECTORS void IntDefaultHandler (void) {} - -int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;} -} diff --git a/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/LPC1549.ld b/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/LPC1549.ld index aaf665bff0..49c146f426 100644 --- a/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/LPC1549.ld +++ b/targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_ARM/LPC1549.ld @@ -145,7 +145,7 @@ SECTIONS /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(Ram0_16) + LENGTH(Ram0_16); + __StackTop = ORIGIN(Ram0_16) + LENGTH(Ram0_16) + LENGTH(Ram1_16) + LENGTH(Ram2_4); __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c index 1184778bb8..e186e8f94e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c @@ -166,13 +166,13 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b /****************************************************************************** * INTERRUPTS HANDLING ******************************************************************************/ -static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) +static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_not_empty, uint32_t index) { if (serial_irq_ids[index] != 0) { if (transmit_empty) irq_handler(serial_irq_ids[index], TxIrq); - if (receive_full) + if (receive_not_empty) irq_handler(serial_irq_ids[index], RxIrq); } } @@ -180,56 +180,56 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint void uart0_irq() { uint32_t status_flags = USART0->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 0); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 0); } void uart1_irq() { uint32_t status_flags = USART1->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 1); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 1); } void uart2_irq() { uint32_t status_flags = USART2->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 2); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 2); } void uart3_irq() { uint32_t status_flags = USART3->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 3); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 3); } void uart4_irq() { uint32_t status_flags = USART4->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 4); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 4); } void uart5_irq() { uint32_t status_flags = USART5->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 5); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 5); } void uart6_irq() { uint32_t status_flags = USART6->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 6); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 6); } void uart7_irq() { uint32_t status_flags = USART7->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 7); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 7); } #if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U) void uart8_irq() { uint32_t status_flags = USART8->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 8); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 8); } #endif @@ -237,7 +237,7 @@ void uart8_irq() void uart9_irq() { uint32_t status_flags = USART9->FIFOSTAT; - uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 9); + uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoNotEmptyFlag), 9); } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/qspi_device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/qspi_device.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/qspi_device.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/qspi_device.h diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp index c44551aea6..433f0d8afd 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp +++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp @@ -104,29 +104,38 @@ RTWInterface::~RTWInterface() */ nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) { - if (!ssid) { + _security = security; + // Check if ssid is empty + if (!ssid) { return NSAPI_ERROR_PARAMETER; } - switch (security) { - case NSAPI_SECURITY_WPA: - case NSAPI_SECURITY_WPA2: - case NSAPI_SECURITY_WPA_WPA2: - case NSAPI_SECURITY_WEP: - if ((strlen(pass) < 8) || (strlen(pass) > 63)) { // 802.11 password 8-63 characters - return NSAPI_ERROR_PARAMETER; - } - break; - case NSAPI_SECURITY_NONE: - break; - default: - return NSAPI_ERROR_PARAMETER; + // Check if ssid is too long + int ssid_length = strlen(ssid); + + if (ssid_length > 0 && ssid_length <= SSID_MAX_LENGTH) { + memset(_ssid, 0, sizeof(_ssid)); + strncpy(_ssid, ssid, sizeof(_ssid)); + } else { + return NSAPI_ERROR_PARAMETER; } - strncpy(_ssid, ssid, 255); - strncpy(_pass, pass, 255); - _security = security; - + // Check if it is an open access point + if (_security != NSAPI_SECURITY_NONE) { + // Check if passphase is empty + if (!pass) { + return NSAPI_ERROR_PARAMETER; + } + // Check if passphase too long + if (strlen(pass) >= PASSPHRASE_MIN_LENGTH && strlen(pass) <= PASSPHRASE_MAX_LENGTH ) { + memset(_pass, 0, sizeof(_pass)); + strncpy(_pass, pass, sizeof(_pass)); + } else { + return NSAPI_ERROR_PARAMETER; + } + } else { // It is an open access point + memset(_pass, 0, sizeof(_pass)); + } return NSAPI_ERROR_OK; } @@ -135,11 +144,15 @@ nsapi_error_t RTWInterface::connect() int ret; rtw_security_t sec; - if (!_ssid || (!_pass && _security != NSAPI_SECURITY_NONE)) { - printf("Invalid credentials\r\n"); - return NSAPI_ERROR_PARAMETER; + // Check if the ssid is empty + if (strlen(_ssid) == 0) { + return NSAPI_ERROR_NO_SSID; } - + // Check the security is empty and the passphase is valid + if ((_security != NSAPI_SECURITY_NONE) && (strlen(_pass) < PASSPHRASE_MIN_LENGTH)) { + return NSAPI_ERROR_PARAMETER; + } + // Based on security type set, adapt to Ameba SDK format switch (_security) { case NSAPI_SECURITY_WPA: case NSAPI_SECURITY_WPA2: @@ -155,22 +168,24 @@ nsapi_error_t RTWInterface::connect() default: return NSAPI_ERROR_PARAMETER; } - + // Check if channel number is valid if (_channel > 0 && _channel < 14) { uint8_t pscan_config = PSCAN_ENABLE; - wifi_set_pscan_chan(&_channel, &pscan_config, 1); + wifi_set_pscan_chan(&_channel, &pscan_config, 1); // Indicate which channel will be scanned } - - ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL); + ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL); // Join a WiFi network + // Check if the WiFi is connected. Return RTW_SUCCESS for succeful; Return RTW_ERROR for error if (ret != RTW_SUCCESS) { - printf("failed: %d\r\n", ret); - return NSAPI_ERROR_NO_CONNECTION; + if(_ssid == "NULL"){ + return NSAPI_ERROR_PARAMETER; + } + else{ + printf("failed: %d\r\n", ret); + return NSAPI_ERROR_NO_CONNECTION; + } } - rtw_emac.wlan_emac_link_change(true); - ret = EMACInterface::connect(); - return ret; } @@ -200,7 +215,7 @@ nsapi_error_t RTWInterface::scan(WiFiAccessPoint *res, unsigned count) nsapi_error_t RTWInterface::set_channel(uint8_t channel) { _channel = channel; - return NSAPI_ERROR_OK; + return NSAPI_ERROR_UNSUPPORTED; } int8_t RTWInterface::get_rssi() @@ -215,8 +230,11 @@ int8_t RTWInterface::get_rssi() nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel) { - set_credentials(ssid, pass, security); set_channel(channel); + int err = set_credentials(ssid, pass, security); + if(err) { + return err; + } return connect(); } diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h index be3ab00d40..5a79782072 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h @@ -112,5 +112,8 @@ protected: char _pass[256]; nsapi_security_t _security; uint8_t _channel; + static const int SSID_MAX_LENGTH = 32; //The longest ssid + static const int PASSPHRASE_MAX_LENGTH = 63; //The longest passphrase + static const int PASSPHRASE_MIN_LENGTH = 8; // The shortest passphrase }; #endif diff --git a/targets/TARGET_STM/README.md b/targets/TARGET_STM/README.md new file mode 100644 index 0000000000..c3e4f457d0 --- /dev/null +++ b/targets/TARGET_STM/README.md @@ -0,0 +1,23 @@ +## README for mbed-os STM32 targets + +### MBED Wiki pages + +https://os.mbed.com/teams/ST/wiki/ + +### STM32 Cube + +https://www.st.com/en/embedded-software/stm32cube-mcu-packages.html + +This table summarizes the STM32Cube versions currently used : + +| STM32 Serie | Cube version | +|-------------|--------------| +| F0 | 1.9.0 | +| F1 | 1.6.1 | +| F2 | 1.6.0 | +| F3 | 1.9.0 | +| F4 | 1.19.0 | +| F7 | 1.10.0 | +| L0 | 1.10.0 | +| L1 | 1.8.1 | +| L4 | 1.11.0 | diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h index dd1c54f632..453d5065e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rtc.h @@ -43,6 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal_def.h" +#include "stm32f0xx_ll_rtc.h" /** @addtogroup STM32F0xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32cubef1.html b/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32cubef1.html deleted file mode 100644 index b439fe6356..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32cubef1.html +++ /dev/null @@ -1,1736 +0,0 @@ - - - - - - - - -Release Notes for STM32CubeF1 Firmware Package - -
-


-

-
- - - - - - -
- - - - - - -
-

Release -Notes for STM32CubeF1 Firmware Package

-

Copyright 2017 -STMicroelectronics

-

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-

 

- - - - - - - - - -
-

-STMCube is an STMicroelectronics original initiative to ease developers -life by reducing development efforts, time and cost. -STM32Cube covers STM32 portfolio.
-
-

-STM32Cube Version 1.x includes:
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    -
      -
    • The -STM32CubeMX, a graphical software configuration tool that allows to -generate C initialization code using graphical wizards.
      • -
    • A -comprehensive embedded software platform, delivered per series (such as -STM32CubeF1 for STM32F1 series)
      • -
        -
      • The -STM32Cube HAL, an STM32 abstraction layer embedded software, ensuring -maximized portability across STM32 portfolio
        • -
      -
        -
      • A -consistent set of middleware components such as RTOS, USB, TCP/IP, -Graphics
        • -
      -
    -
-
All -embedded software utilities come with a full set of examples.
-
-
-
    -
  • The -STM32Cube firmware solution offers a straightforward API with a modular -architecture, making it simple to fine tune custom applications and -scalable to -fit most requirements
    • -
-     
-         
-
-
    -
  • -

    The -HAL -(Hardware Abstraction Layer) drivers provided within this -package supports -the following STM32F100xx - STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx -Series.

    -
    • -
  • The -STM32CubeF1 firmware package comes with an updater utility, STM32CubeUpdater, -that can be configured for automatic -or on-demand checks for new firmware package updates (new -releases or/and patches).
    • -
-
    -
  • For quick getting started with the -STM32CubeF1 firmware package, refer to UM1847 and you can -download firmware updates and all the latest documentation from www.st.com/stm32cube
    • -
  • Below -links to -the most useful documents
    -
    • Latest release of STM32CubeF1 Firmware package.
    • UM1847: Getting started with STM32CubeF1 for STM32F1 Series.
    • UM1853: STM32CubeF1 Nucleo demonstration firmware.
    • UM1850: Description of STM32F1xx HAL drivers.
    • UM1734: STM32Cube USB Device library.
    • UM1720: STM32Cube USB host library.
    • UM1721: Developing Applications on STM32Cube with FatFs.
    • UM1722: Developing Applications on STM32Cube with RTOS.
    • UM1713: Developing applications on STM32Cube with LwIP TCP/IP stack.
    • UM1709: STM32Cube Ethernet IAP example.
- - -

Update -History

-

V1.6.1 / 09-March-2018

Main Changes

  • Patch release to fix issues in GPIO, RCC, SMARTCARD, I2C and Generic HAL/LL drivers

Contents

V1.6.0 / 12-May-2017

Main Changes

  • General update to fix known defects and several implementations enhancement
  • \HAL
    • stm32f1xx_hal_conf_template.h fix typo: update to refer to stm32f1xx_hal_mmc.h instead of  stm32f4xx_hal_mmc.h
    • stm32f1xx_hal_mmc.c add missing () to fix compilation warning detected with SW4STM32 when extra feature is enabled.
    • stm32f1xx_ll_system.h: fix typo in LL_DBGMCU_APB1_GRP1_I2C1_STOP and LL_DBGMCU_APB1_GRP1_I2C2_STOP literals definition
  • \Projects
    • General updates to be compliant with Linux platforms
  • For the complete list of changes, please refer to the release notes of each firmware component

Contents


Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain v7.80.4
  • RealView -Microcontroller Development Kit (MDK-ARM) toolchain V5.23 
  • Atollic -TrueSTUDIO STM32 (TrueSTUDIO) toolchain V5.5.2
  • System -Workbench for STM32 (SW4STM32) toolchain V1.13

Supported -Devices and EVAL boards

-
  • STM32F1xx -Value, Access, USB, Performance, OTG & Ethernet Lines
  • STM3210E-Eval -board RevD
  • STM3210C-Eval -board RevC
  • STM32VL-Discovery -board RevC
  • STM32F1xx-Nucleo -board RevC
-
- -

Known -Limitations
-

-
  • SW4STM32 projects aren't provided for STM32VL-Discovery board because it embeds STLinv1 version that is not hardware supported by SW4STM32 toolchain.

V1.5.0 / 14-April-2017

Main Changes

  • Add Low Layer drivers under Drivers\STM32F1xx_HAL_Driver
    • Low Layer drivers allow performance and memory footprint optimization
      • Low -Layer drivers APIs provide register level programming: they require -deep knowledge of peripherals described in STM32F1xx Reference Manuals
      • Low Layer drivers are available for: ADC, Cortex, -CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, PWR, RCC, RNG, RTC, -SPI, TIM, USART, WWDG peripherals and additionnal Low Level Bus, System -and Utilities APIs. 
      • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f1xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f1xx_ll_ppp.h file must be included in user code.
      • Refer to UM1847 for Low Layer presentation and UM1850 for API list
  • General update to fix known defects and several implementations enhancement
  • \HAL
    • Add Low Layer drivers under Drivers\STM32F1xx_HAL_Driver
    • Add new MMC HAL driver
    • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
      • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C,FMPI2C, QSPI (referenced as PPP here below) drivers
        • Add PPP error management during DMA process. This requires the following updates on user application:
          • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
          • In stm32f1xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
          • Add customize the Error Callback API: HAL_PPP_ErrorCallback()
      • HAL SD driver:
        • Overall rework of the driver for a more efficient implementation
          • Modify initialization API and structures
          • Modify Read / Write sequences: separate transfer process and SD Cards state management 
          • Adding interrupt mode for Read / Write operations
          • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
        • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
      • HAL NAND driver:
        • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
        • Add new HAL_NAND_ConfigDevice API
      • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
        • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
        • Remove -HAL CEC receive interrupt process function HAL_CEC_Receive_IT() -and enable the "receive"  mode during the Init phase
        • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
        • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
        • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
        • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
        • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
      • HAL IWDG driver: rework overall driver for better implementation
        • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
      • HAL WWDG driver: rework overall driver for better implementation
        • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs 
        • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
  • \CMSIS
    • Fix known defects and several implementation enhancement
    • General update to support Low layer drivers (LL)
  • \Middleware
    • Update STemWin Library V5.32 with a new build with EWARM V7.80
    • Upgrade to use new version of LwIP V2.0.0
      • Note:  Applications based on previous version LwIP V1.4.1 -require update to cope with the upgrade to the currently used V2.0.0. -For details please refer to its Release Note and to the updated LwIP -applications provided by this firmware package.
    • Update to new version of FreeRTOS V9.0.0
    • Update FatFS to implement changes on sd_diskio.c file to be aligned with HAL SD driver and BSP drivers API changes.
  • \Projects
    • General updates to fix known defects and enhancements implementation
    • Add Low Layer examples and MIX examples on the STM32F103RB-Nucleo, STM32F10E-EVAL boards
    • Update overall projects to be aligned with latest version of HAL, BSP and Middleware drivers
    • Add HAL_TimeBase RTC examples on all the supported boards
    • Add I2C_TwoBoards_RestartAdvComIT and  I2C_TwoBoards_RestartComIT Examples
  • For the complete list of changes, please refer to the release notes of each firmware component

Contents


Development Toolchains and Compilers

  • IAR Embedded Workbench for ARM (EWARM) toolchain v7.80.4
  • RealView -Microcontroller Development Kit (MDK-ARM) toolchain V5.23 
  • Atollic -TrueSTUDIO STM32 (TrueSTUDIO) toolchain V5.5.2
  • System -Workbench for STM32 (SW4STM32) toolchain V1.13

Supported -Devices and EVAL boards

-
  • STM32F1xx -Value, Access, USB, Performance, OTG & Ethernet Lines
  • STM3210E-Eval -board RevD
  • STM3210C-Eval -board RevC
  • STM32VL-Discovery -board RevC
  • STM32F1xx-Nucleo -board RevC
-
- -

Known -Limitations
-

-
  • None

V1.4.0 / 29-April-2016

-

Main -Changes

-
  • Maintenance release to fix known defects and several enhancements -implementation.
  • HAL
    • HAL RCC
      • Add suffix U for defines equals to 0xFFFFFFFF (fix MISRA error 10.6)
      • Optimization of HAL_RCC_ClockConfig().
      • Replace aAPBAHBPrescTable by APBPrescTable and AHBPrescTable defined inside system_stm32f1xx.c.
      • When using HAL_RCC_OscConfig -to activate LSE, if LSE is already ON, it remains in its state ON. -Previously, it was turned OFF then ON in all cases.
      • The backup domain is no more reset when changing the RTC clock source from reset value.
      • Correct strange behavior in HAL_RCCEx_PeriphCLKConfig.
    • HAL UART
      • Correct the macro UART_BRR_SAMPLING16
    • HAL SMARTCARD
      • Correct the macro SMARTCARD_BRR
    • HAL IRDA
      • Correct the macro IRDA_BRR
      • EIE bit is no more activated in transmit (this bit only triggers errors in reception)
      • EIE bit is reset at the end of the reception.
    • HAL DMA
      • Add macro __HAL_DMA_GET_COUNTER to get the number of remaining data units in the current channel.
    • HAL FSMC
      • Adapt FSMC_NAND_Init behavior to the others STM32 series by reseting the bit FSMC_PCRx_PBKEN.
  • CMSIS
    • Add _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value). 
      • The previous naming are kept for backward compatibility.
    • Add APBPrescTable constant to list APB prescalers values.
  • BSP -STM32F1xx_Nucleo
    • Add support for 4 Gb sd cards.
  • BSP -STM3210E_EVAL
    • Set the NVIC priority to the lowest possible to not interfere with user settings.
  • BSP -STM3210C_EVAL
    • Set the NVIC priority to the lowest possible to not interfere with user settings.
  • Middlewares
    • Update to FreeRTOS -V8.2.3.
    • Update to STM32 USB Device Library V2.4.2
  • Others
    • Add latest version of STM32CubeUpdater (V4.10.0).
- - -
-

Development -Toolchains and Compilers

-
  • IAR Embedded -Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
  • RealView -Microcontroller Development Kit (MDK-ARM) toolchain V5.17 + ST-LINK
  • Atollic -TrueSTUDIO STM32 (TrueSTUDIO) toolchain V5.1.1 + ST-LINK
  • System -Workbench for STM32 (SW4STM32) toolchain V1.5.0 + ST-LINK
-
- -

Supported -Devices and EVAL boards

-
  • STM32F1xx -Value, Access, USB, Performance, OTG & Ethernet Lines
  • STM3210E-Eval -board RevD
  • STM3210C-Eval -board RevC
  • STM32VL-Discovery -board RevC
  • STM32F1xx-Nucleo -board RevC
-
- -

Known -Limitations
-

-
  • None

V1.3.1 / 11-January-2016

-

Main -Changes

-
  • Patch release to fix issue in HAL driver:
    • Remove the #if defined(USE_HAL_LEGACY) condition to include Legacy/stm32_hal_legacy.h by default, in stm32f1xx_hal_def.h.

Contents

V1.3.0 -/ 18-December-2015

- -

Main -Changes

-
  • Maintenance release to fix known defects and several enhancements -implementation.
  • HAL
    • Insure that do {} while(0)  are used in in multi statement macros. (hal eth and pcd)
    • Manage simultaneous errors in IRQHandler. (hal uart, smartcard, usart and uart)
    • To -ensure the full compatibility of the GPIO interfaces across all the -STM32 families, the gpio speed definition have been renamed:
      • GPIO_SPEED_LOW to GPIO_SPEED_FREQ_LOW
      • GPIO_SPEED_MEDIUM to GPIO_SPEED_FREQ_MEDIUM
      • GPIO_SPEED_HIGH to GPIO_SPEED_FREQ_HIGH
      • aliases are created to keep backward compatibility
    • Reduce the default timeout value for the startup of the HSE form 5s to 100ms.
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers.
  • CMSIS
    • Align bit name across all STM32 families (EXTI, WWDG) and keeping backward compatibility with aliases.
  • Middlewares
    • Update to CMSIS V4.5.
  • Projects
    • Update all Keil project from Keil V4 to Keil V5.
    • Update all SW4STM32 projects to version 1.5.0.
  • Others
    • Add latest version of STM32CubeUpdater (V4.10.0).
- - -
-

Development -Toolchains and Compilers

-
  • IAR Embedded -Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
  • RealView -Microcontroller Development Kit (MDK-ARM) toolchain V5.17 + ST-LINK
  • Atollic -TrueSTUDIO STM32 (TrueSTUDIO) toolchain V5.1.1 + ST-LINK
  • System -Workbench for STM32 (SW4STM32) toolchain V1.5.0 + ST-LINK
-
- -

Supported -Devices and EVAL boards

-
  • STM32F1xx -Value, Access, USB, Performance, OTG & Ethernet Lines
  • STM3210E-Eval -board RevD
  • STM3210C-Eval -board RevC
  • STM32VL-Discovery -board RevC
  • STM32F1xx-Nucleo -board RevC
-
- -

Known -Limitations
-

-
  • None

V1.2.0 -/ 31-July-2015

- -

Main -Changes

-
    -
  • Maintenance release.
    • -
  • Fix known defects and several enhancements -implementation.
    • -
  • \Projects
    • -
      -
    • Adding new projects to introduce the FreeRTOS -V8.2.1
      • -
        -
      • FreeRTOS_SignalFromISR (thread signaling from -an interrupt)
        • -
      • FreeRTOS_Signal (thread signaling)
        • -
      • FreeRTOS_Mail (mail queues)
        • -
      -
    • Adding -new application IAP for STM3210E_EVAL board.
      -
      • -
    -
  • \FatFs
    • -
      -
    • Upgrade to -use FatFs R0.11.
      • -
    • Add new APIs -FATFS_LinkDriverEx() and FATFS_UnLinkDriverEx() to manage USB Key Disk -having
      -     multi-lun capability. These -APIs are equivalent to FATFS_LinkDriver() and FATFS_UnLinkDriver()
      -     with "lun" parameter set to 0.
      • -
    • ff_conf.h: -add new define "_USE_BUFF_WO_ALIGNMENT".
      • -
    • Important -note:
      -      For application code -based on previous FatFs version; when moving to R0.11
      -      the changes that -need to be done is to update ffconf.h file, taking
      -      ffconf_template.h -file as reference.
      • -
    -
  • \STM32 USB Host and STM32 USB Device Library
    • -
      -
    • This new versions implements only bug fixes -with minor enhancements, it doesn’t impact neither the APIs nor the -behavior of applications developed so far.
      • -
    -
  • \STemWin
    • -
      -
    • Upgrade -to use SEGGER emWin version V5.28, for more -details about the -changes in this version refer to "Revision History" section in STemWin528.pdf document
      • -
    -
  • \FreeRTOS
    • -
      -
    • No changes in file naming/set of sources -files.
      • -
    • Align -Port.c for CM7, CM4 and CM3  to M0  regarding -function -“vPortSuppressTicksAndSleep : Same implementation for CM7, CM4 and CM3 -as CM0
      • -
    • Macros “configPRE_SLEEP_PROCESSING” and - “configPOST_SLEEP_PROCESSING are now passing the parameter -ulExpectedIdleTime by pointer
      • -
    • Adding implementation for APIs “osSignalSet” -and “osSignalWait”.
      • -
    • API changes on CMSIS-RTOS (osDelayUntil()).
      • -
    • Internal enhancements and bug fixes.
      • -
    -
- - -
    -
      -
    • CMSIS-DSP -V1.4.5
      • -
    -
- -
    -
      -
    • CMSIS-RTOS -V1.02 (unchanged)
      • -
    -
- -

Contents

- - - -
-

Development -Toolchains and Compilers

-
    -
  • IAR Embedded -Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
    • -
  • RealView -Microcontroller Development Kit (MDK-ARM) toolchain V5.10 + ST-LINK
    • -
      -
    • Important -note: some of MDK-ARM projects were -created with previous version like v4.73. If you are using -MDK-ARM v5.10 (and later) you have to install a legacy patch to be able -to open projects built with v4.73, here is the download link
      • -
    -
  • Atollic -TrueSTUDIO STM32 (TrueSTUDIO) toolchain V5.1.1 + ST-LINK
    • -
  • System -Workbench for STM32 (SW4STM32) toolchain V1.2.0 + ST-LINK
    • -
-
- -

Supported -Devices and EVAL boards

-
    -
  • STM32F1xx -Value, Access, USB, Performance, OTG & Ethernet Lines
    • -
  • STM3210E-Eval -board RevD
    • -
  • STM3210C-Eval -board RevC
    • -
  • STM32VL-Discovery -board RevC
    • -
  • STM32F1xx-Nucleo -board RevC
    • -
-
- -

Known -Limitations
-

-
    -
  • None
    • -
-

V1.1.0 -/ 05-June-2015

-

Main -Changes -

-
    -
  • Add support of System Workbench -for STM32 (SW4STM32) toolchain
    • -
-
    -
  • \HAL
    -
    • -
      -
    • No -changes
      • -
    -
  • \Middlewares
    -
    • -
      -
    • No -changes
      • -
    -
  • \BSP
    -
    • -
      -
    • No -changes
      • -
    -
  • \Projects
    -
    • -
      -
    • Add projects for SW4STM32 toolchain
      • -
    -
-

Contents

- - - - - -

Development -Toolchains and Compilers

-
    -
  • IAR Embedded -Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
    • -
  • RealView -Microcontroller Development Kit (MDK-ARM) toolchain V5.10 + ST-LINK
    • -
  • Atollic -TrueSTUDIO STM32 (TrueSTUDIO) toolchain V5.1.1 + ST-LINK
    • -
  • System -Workbench for STM32 (SW4STM32) toolchain V1.2.0 + ST-LINK
    • -
    -     -
-

Supported -Devices and EVAL boards

-
    -
  • STM32F1xx -Value, Access, USB, Performance, OTG & Ethernet Lines
    • -
  • STM3210E-Eval -board RevD
    • -
  • STM3210C-Eval -board RevC
    • -
  • STM32VL-Discovery -board RevC
    • -
  • STM32F1xx-Nucleo -board RevC
    • -
-
- -

Known -Limitations
-

-
    -
  • None
    • -
-

V1.0.0 -/ 17-December-2014

-

Main -Changes

-
    -
  • First -official release of STM32CubeF1 (STM32Cube for STM32F1 Series)
    • -
-

-

Contents

- - - - - -
-

STM32Cube_FW_F1 - Projects (details)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-

Board

-		 -

Examples

-		 -

Applications

-		 -

Demonstration

-
-

STM3210E-EVAL

-		 -

30

-		 -

8

-		 -

N/A

-
-

STM3210C-EVAL

-		 -

17

-		 -

19

-		 -

N/A

-
-

STM32VL-Discovery

-		 -

16

-		 -

N/A

-		 -

N/A

-
-

NUCLEO-F103RB

-		 -

24

-		 -

3

-		 -

1

-
-
- -

Development -Toolchains and Compilers

-
    -
  • IAR Embedded -Workbench for ARM (EWARM) toolchain V7.20 + ST-LINK
    • -
  • RealView -Microcontroller Development Kit (MDK-ARM) toolchain V5.10 + ST-LINK
    • -
  • Atollic -TrueSTUDIO STM32 (TrueSTUDIO) toolchain V5.1.1 + ST-LINK
    • -
    -     -
-

Supported -Devices and EVAL boards

-
    -
  • STM32F1xx -Value, Access, USB, Performance, OTG & Ethernet Lines
    • -
  • STM3210E-Eval -board RevD
    • -
  • STM3210C-Eval -board RevC
    • -
  • STM32VL-Discovery -board RevC
    • -
  • STM32F1xx-Nucleo -board RevC
    • -
-
- -

Known -Limitations
-

-
    -
  • None
    • -
- -

License

-

Licensed -under MCD-ST Liberty SW License Agreement V2, (the "License"); You may -not use this package -except in compliance with the License. You may obtain a copy of the -License at:
-
-

- -
-Unless -required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS,
-WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See -the License for the specific language governing permissions and -limitations under the License. -
-
-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32
-

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html b/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html deleted file mode 100644 index 0c01dc529c..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html +++ /dev/null @@ -1,1518 +0,0 @@ - - - - - - - - - - - - - -Release Notes for STM32F1xx HAL Drivers - - - - - - - - - - -
- -

 

- -
- - - - - -
- - - - - - - -
-

Back to Release page

-
-

Release Notes for STM32F1xx HAL Drivers

-

Copyright - 2016 STMicroelectronics

-

-
-

 

- - - - -
-

Update History

- -

V1.1.2 / 09-March-2018

  • General updates to fix known defects and enhancements implementation
  • Remove Date and version from header files
  • HAL Generic update
    • stm32f1xx_hal_def.h file changes:
      • Update UNUSED() macro implementation to avoid GCC warning
        • The warning is detected when the UNUSED() macro is called from C++ file
      • Update __weak and __packed defined values for ARM compiler
      • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
      • Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type
    • stm32f1xx_hal.c/.h file changes:
      • Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms:
        • Add the following APIs:  
          • HAL_GetTickPrio(): Returns a tick priority
          • HAL_SetTickFreq(): Sets new tick frequency
          • HAL_GetTickFreq(): Returns tick frequency
        • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and
          1KHz (default)
    • stm32f1xx_hal_conf_template.h file changes:
      • Fix wrong defined value of LSI
  • HAL GPIO update
    • Rework AFIO remap macros to avoid issue with Read-modify-write sequence on AFIO_MAPR register
  • HAL I2C update
    • Fix wrong check of data size in HAL_I2C_Slave Receive() API
    • Add a check on the minimum allowed PCLK1 frequency in HAL_I2C_Init() API
    • Fix I2C_SPEED_FAST() and I2C_SPEED_STANDARD() speed calculation macros to not let I2C SCL to go beyond
      400KHz in some conditions
  • HAL RCC update
    • Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
      • Be able to return HAL/LL status
      • Add checks for HSI, PLL and PLLI2S  ready before modifying RCC CFGR registers
      • Clear all interrupt flags
      • Initialize systick interrupt period
    • Update HAL_RCC_GetSysClockFreq() to avoid risk of rounding error which may leads to a wrong returned value. 

  • HAL SMARTCARD update
    • Update data processing in HAL smartcard transmit/receive processes(Polling/IT) to fix memory corruption issue.
  • LL GPIO update
    • Fix wrong management of GPIO pin position in LL_GPIO_Init() API when configuring GPIOx_CRH register
    • Fix wrong check conditions on GPIO mode in LL_GPIO_Init() API
  • LL I2C update
    • Rename -IS_I2C_CLOCK_SPEED() and IS_I2C_DUTY_CYCLE() respectively to -IS_LL_I2C_CLOCK_SPEED() and IS_LL_I2C_DUTY_CYCLE() to avoid -incompatible macros redefinition.
  • LL RCC update 
    • Add LL_RCC_PLL_SetMainSource() macro to configure PLL main clock source

V1.1.1 / 12-May-2017

  • General updates to fix known defects and enhancements implementation
  • HAL Generic update
    • stm32f1xx_hal_conf_template.h fix typo: update to refer to stm32f1xx_hal_mmc.h instead of  stm32f4xx_hal_mmc.h
  • LL SYSTEM update
    • LL_DBGMCU_APB1_GRP1_I2C1_STOP and LL_DBGMCU_APB1_GRP1_I2C2_STOP literals are retarget to an available literals
    • LL_DBGMCU_APB1_GRP1_RTC_STOP literal is not available for all STM32F1 devices
  • HAL MMC update
    • Add missing () to fix compilation warning detected with SW4STM32 when extra feature is enabled.
  • HAL I2C update
    • Update -HAL I2C processes to manage correctly the I2C state to allow the -possibility to call HAL_I2C_Master_Sequential_Receive_IT() followed by -a call HAL_I2C_Master_Sequential_Transmit_IT()

V1.1.0 / 14-April-2017

  • Add Low Layer drivers allowing performance and footprint optimization
    • Low -Layer drivers APIs provide register level programming: require deep -knowledge of peripherals described in STM32F1xx Reference Manuals
    • Low -Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, PWR, RCC, RTC, SPI, TIM, -USART, WWDG peripherals and additionnal Low Level Bus, System and -Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f1xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f1xx_ll_ppp.h file must be included in user code.
  • Add new HAL MMC driver
  • General updates to fix known defects and enhancements implementation
  • - -Enhance HAL delay and time base implementation:
    • Add -new drivers stm32f1xx_hal_timebase_rtc_alarm_template.c and -stm32f1xx_hal_timebase_tim_template.c which override the native -HAL time base functions (defined as weak) to either use the RTC/TIM as time -base tick source. For more details about the usage of these drivers, -please refer to HAL\HAL_TimeBase_RTC  and HAL\HAL_TimeBase_TIM examples and FreeRTOS-based applications
  • Fix extra warnings with GCC compiler
  • HAL drivers clean up: update 'uint32_t' cast with 'U'
  • Update to used the new defined Bit_Pos CMSIS defines insetad of POSITION_VAL() macro
  • Update HAL -weak empty callbacks to prevent unused argument compilation warnings with some -compilers by calling the following line: -
    • UNUSED(hppp);
  • STM32Fxxx_User_Manual.chm files regenerated for HAL V1.1.0
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C (referenced as PPP here below) drivers
      • Add PPP error management during DMA process. This requires the following updates on user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f1xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add customize the Error Callback API: HAL_PPP_ErrorCallback()
    • HAL SD driver:
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
    • HAL NAND driver:
      • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • Add new HAL_NAND_ConfigDevice API
    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove -HAL CEC receive interrupt process function HAL_CEC_Receive_IT() -and enable the "receive"  mode during the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • HAL IWDG driver: rework overall driver for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: rework overall driver for better implementation
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs 
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
  • HAL GENERIC update
    • Modifiy default HAL_Delay implementation to guarantee minimum delay 
    • stm32f1xx_hal_conf_template.h
      • Add new define LSI_VALUE
      • Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled.
  • HAL CORTEX update
    • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f4xx_hal_cortex.h to stm32f4xx_hal_cortex.c
    • Clear the whole MPU control register in HAL_MPU_Disable() API
  • HAL FLASH update
    • HAL_FLASH_OB_Launch(): fix static code analyzer warning: The removed code will not execute under any circumstances
  • HAL GPIO update
    • Update IS_GPIO_PIN() macro implementation to be more safe
    • Update remap macros implementation to use CLEAR_BIT()/SET_BIT() macros instead of  MODIFY_REG() macro.
  • HAL RCC update
    • Update LSI workaround delay to use CPU cycles instead of systick
    • Move LSI_VALUE define from RCC HAL driver to stm32f1xx_hal_conf.h file
    • Adjust defined PLL MUL values in aPLLMULFactorTable[]
  • HAL ADC update
    • HAL_ADCEx_MultiModeStart_DMA()  and HAL_ADCEx_MultiModeStop_DMA() API's update to fix code static analyzer warning: Redundant Condition / Unreachable Computation
  • HAL DMA update
    • HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst 
    • Global driver code optimization to reduce memory footprint 
    • New APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() to register/unregister the different possible callbacks identified by enum typedef HAL_DMA_CallbackIDTypeDef
    • Add new Error Codes: HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED
  • HAL USART update
    • Add Transfer abort functions and callbacks

    • DMA Receive process; the code -has been updated to clear the USART OVR flag before enabling DMA receive request.

    • Update HAL_USART_IRQHandler() to add a check on interrupt source before managing the error 
  • - -HAL UART update -
    • Several update on HAL UART driver to implement the new UART state machine: 
      • Add new field in UART_HandleTypeDef structure: "rxState", UART state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": UART state information related to global Handle management and Tx Operations
      • Update UART process to manage the new UART states.
      • Update __HAL_UART_RESET_HANDLE_STATE() macro -to handle the new UART state parameters (gState, rxState)
    • Add Transfer abort functions and callbacks
    • Update HAL_UART_IRQHandler() to add a check on interrupt source before managing the error 

    • DMA Receive process; the code -has been updated to clear the USART OVR flag before enabling DMA receive request.

- - - - -
  • - -HAL IRDA update -
    • Several update on HAL IRDA driver to implement the new UART state machine: 
      • Add new field in IRDA_HandleTypeDef structure: "rxState", IRDA state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": IRDA state information related to global Handle management and Tx Operations
      • Update IRDA process to manage the new UART states.
      • Update __HAL_IRDA_RESET_HANDLE_STATE() macro -to handle the new IRDA state parameters (gState, rxState)
    • Removal of IRDA_TIMEOUT_VALUE define
    • Add Transfer abort functions and callbacks
    • Update HAL_IRDA_IRQHandler() to add a check on interrupt source before managing the error 

    • DMA Receive process; the code -has been updated to clear the USART OVR flag before enabling DMA receive request.

  • - -HAL SMARTCARD update -
    • Several update on HAL SMARTCARD driver to implement the new UART state machine: 
      • Add new field in SMARTCARD_HandleTypeDef structure: "rxState", SMARTCARDstate information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": SMARTCARDstate information related to global Handle management and Tx Operations
      • Update SMARTCARD process to manage the new UART states.
      • Update __HAL_SMARTCARD_RESET_HANDLE_STATE() macro -to handle the new SMARTCARD state parameters (gState, rxState)
    • Add Transfer abort functions and callbacks
    • Update HAL_SMARTCARD_IRQHandler() to add a check on interrupt source before managing the error 

    • DMA Receive process; the code -has been updated to clear the USART OVR flag before enabling DMA receive request.

  • HAL CAN update
    • Add - management of overrun error. 
    • Allow - possibility to receive messages from the 2 RX FIFOs in parallel via - interrupt.
    • Fix message - lost issue with specific sequence of transmit requests.
    • Handle - transmission failure with error callback, when NART is enabled.
    • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when - timeout is reached
  • HAL TIM update
    • Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state. 
    • Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption.
    • Update Input Capture polarity by removing non-supported "TIM_INPUTCHANNELPOLARITY_BOTHEDGE" define.
    • Update HAL_TIM_ConfigOCrefClear() API by removing the usage of non-existant SMCR OCCS bit.
    • Add -"AutoReloadPreload" field to TIM_Base_InitTypeDef structure and -corresponding macros __HAL_TIM_ENABLE_OCxPRELOAD() and -__HAL_TIM_DISABLE_OCxPRELOAD() .
    • Update TIM_Base_SetConfig() API to set the auto-reload preload.
  • HAL I2C update
    • Update -HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending -extra bytes at the end of the transmit processes
    • Update - HAL_I2C_Mem_Read() API to fix wrong check on misused parameter Size
    • Update - I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to - enhance Master sequential reception process.
  • HAL SPI update
    • Major Update to improve performance in - polling/interrupt mode to reach max frequency:
      • Polling mode :
        • Replace use of - SPI_WaitOnFlagUnitTimeout() funnction by "if" statement to - check on RXNE/TXE flage while transferring data.
        • Use API data pointer instead of SPI - handle data pointer.
      • Use a Goto implementation instead of - "if..else" statements
      • Interrupt mode
        • Minimize access on SPI registers.
        • Split the SPI modes into dedicated - static functions to minimize checking statements under - HAL_IRQHandler():
          • 1lines/2lines modes
          • 8 bit/ 16 bits data formats
          • CRC calculation enabled/disabled.
      • Remove waiting loop under ISR when - closing  the communication.
      • All modes:  
        • Adding switch USE_SPI_CRC to minimize - number of statements when CRC calculation is disabled.
        • Update Timeout management to check on - global process.
        • Update Error code management in all - processes.
    • Add note to the max frequencies reached in - all modes.
    • Add note about Master Receive mode - restrictions :
    • Master Receive mode restriction:
      -       (#) In Master unidirectional receive-only - mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
      -           bidirectional - receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
      -           does not initiate - a new transfer the following procedure has to be respected:
      -           (##) - HAL_SPI_DeInit()
      -           (##) - HAL_SPI_Init()
    • Add transfer abort APIs and - associated callbacks in interrupt mode
      • HAL_SPI_Abort()
      • HAL_SPI_Abort_IT()
      • HAL_SPI_AbortCpltCallback()
  • - -HAL CEC update
    • Overall driver rework with break of compatibility with HAL V1.0.5
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
      • Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC state information related to global Handle management and Tx Operations
      • Update CEC process to manage the new CEC states.
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
-
  • HAL I2S update
    • Update I2S Transmit/Receive polling process to manage Overrun and Underrun errors
    • HAL I2S driver ovall clean-up and optimization
    • HAL_I2S_Init() API updated to
      • Fix wrong I2S clock calculation when PCM mode is used.
      • Return state HAL_I2S_ERROR_PRESCALER when the I2S clock is wrongly configured
  • HAL NAND update
    • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
    • Add new HAL_NAND_ConfigDevice API
-
  • HAL USB PCD update
    • Flush all TX FIFOs on USB Reset
    • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's
  • LL USB update
    • Enable DMA Burst mode for USB OTG HS
    • Fix SD card detection issue
  • LL SDMMC update
    • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions

V1.0.5 / 06-December-2016

- - - - - - - - - - - - - - - - - - - - -

Main -Changes

-
  • General updates to fix mainly known I2C defects and enhancements implementation
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.0.4
    • HAL I2C driver:
      • Add  I2C  error management during DMA process. This requires the following updates on user application:
        • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
        • In stm32f1xx_it.c file, I2C _IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
        • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the I2C end of transfer interrupt in the DMA transfer process. This requires the following updates on user application:
        • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
        • In stm32f1xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
      • I2C -transfer processes IT update: NACK during addressing phase is managed -through I2C Error interrupt instead of HAL state
  • HAL I2C update
    • Add support of I2C repeated start feature:
      • With the following new API's
        • HAL_I2C_Master_Sequential_Transmit_IT()
        • HAL_I2C_Master_Sequential_Receive_IT()
        • HAL_I2C_Master_Abort_IT()
        • HAL_I2C_Slave_Sequential_Transmit_IT()
        • HAL_I2C_Slave_Sequential_Receive_IT()
        • HAL_I2C_EnableListen_IT()
        • HAL_I2C_DisableListen_IT()
      • Add -new user callbacks:
        • HAL_I2C_ListenCpltCallback()
        • HAL_I2C_AddrCallback()
    • - -

      IRQ handler optimization: read -registers status only once

    • I2C addressing phase is updated to be managed using interrupt instead of polling
      • Add new static functions to manage I2C SB, ADDR and ADD10 flags
    • I2C IT transfer processes update: NACK during addressing phase is managed through I2C Error interrupt instead of HAL state
    • Update to generate STOP condition when a acknowledge failure error is detected 
    • Update I2C_WaitOnFlagUntilTimeout() to manage the NACK feature.
    • Update  I2C transmission process to support the case data size equal 0
    • Update Polling management:
      • The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Add the management of Abort service: Abort DMA transfer through interrupt
      • In the case of Master Abort IT transfer usage:
        • Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process
        • A new abort state is defined in the HAL_I2C_StateTypeDef structure
    • Add -the management of I2C peripheral errors, ACK failure and STOP condition -detection during DMA process. This requires the following updates on -user application:
      • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
      • In stm32f1xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
      • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
    • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the I2C end of transfer interrupt in the DMA transfer process. This requires the following updates on user application:
      • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
      • In stm32f1xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
    • Add a check if the I2C is already enabled at start of all I2C API's.

    • Update I2C API's (Polling, IT, DMA interfaces) to use hi2c->XferSize and hi2c->XferCount instead of size 
      parameter to help user to get information of counter in case of error

  • HAL DMA update
    • Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context
      • The new registered Abort callback is called when DMA transfer abortion is completed
  • HAL ETH update
    • Remove ETH MAC debug register defines
  • HAL DAC update
    • Clean up: remove the following literals that aren't used 
      • DAC_WAVE_NOISE
      • DAC_WAVE_TRIANGLE

V1.0.4 / 29-April-2016

- - - - - - - - - - - - - - - - - - - - -

Main -Changes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

  • General updates to fix known defects and enhancements implementation.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • HAL RCC
    • Add suffix U for defines equals to 0xFFFFFFFF (fix MISRA error 10.6)
    • Optimization of HAL_RCC_ClockConfig().
    • Replace aAPBAHBPrescTable by APBPrescTable and AHBPrescTable defined inside system_stm32f1xx.c.
    • When using HAL_RCC_OscConfig -to activate LSE, if LSE is already ON, it remains in its state ON. -Previously, it was turned OFF then ON in all cases.
    • The backup domain is no more reset when changing the RTC clock source from reset value.
    • Correct strange behavior in HAL_RCCEx_PeriphCLKConfig.
  • HAL UART
    • Correct the macro UART_BRR_SAMPLING16
  • HAL SMARTCARD
    • Correct the macro SMARTCARD_BRR
  • HAL IRDA
    • Correct the macro IRDA_BRR
    • EIE bit is no more activated in transmit (this bit only triggers errors in reception)
    • EIE bit is reset at the end of the reception.
  • HAL DMA
    • Add macro __HAL_DMA_GET_COUNTER to get the number of remaining data units in the current channel.
  • HAL FSMC
    • Adapt FSMC_NAND_Init behavior to the others STM32 series by reseting the bit FSMC_PCRx_PBKEN.

V1.0.3 / 11-January-2016

- - - - - - - - - - - - - - - - - - - - -

Main -Changes

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • Remove the #if defined(USE_HAL_LEGACY) condition to include Legacy/stm32_hal_legacy.h by default, in stm32f1xx_hal_def.h.

V1.0.2 / 18-December-2015

- - - - - - - - - - - - - - - - - - - - -

Main -Changes

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • General updates to fix known defects and enhancements implementation.
  • HAL generic
    • Insure that do {} while(0)  are used in in multi statement macros. (hal eth and pcd)
    • Manage simultaneous errors in IRQHandler. (hal uart, smartcard, usart and uart)
    • To -ensure the full compatibility of the GPIO interfaces across all the -STM32 families, the gpio speed definition have been renamed:
      • GPIO_SPEED_LOW to GPIO_SPEED_FREQ_LOW
      • GPIO_SPEED_MEDIUM to GPIO_SPEED_FREQ_MEDIUM
      • GPIO_SPEED_HIGH to GPIO_SPEED_FREQ_HIGH
      • aliases are created to keep backward compatibility
    • Reduce the default timeout value for the startup of the HSE form 5s to 100ms.
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers.
  • HAL ADC
    • Remove useless state HAL_ADC_STATE_REG_OVR and HAL_ADC_STATE_REG_EOSMP.
    • Add an error case if init is done with both continuous and discontinuous modes.
    • HAL_ADC_PollForEvent returns HAL_TIMEOUT if a timeout occurs instead of HAL_ERROR.
    • Trigger the assert_param of  the number of discontinuous conversion only if the discontinuous mode is enabled.
    • Enhance the check for ScanConvMode in HAL_ADC_Init.
  • HAL CAN
    • Clear the ERRI bit in HAL_CAN_IRQHandler.
  • HAL CORTEX
    • Remove the macro __HAL_CORTEX_SYSTICKCLK_CONFIG as duplicated by HAL_SYSTICK_CLKSourceConfig.
      • Create an alias to HAL_SYSTICK_CLKSourceConfig for backward compatibility.
  • HAL FLASH
    • The -parameter ReturnValue of HAL_FLASH_EndOfOperationCallback, in the case -of Pages Erase, now take the value of 0xFFFFFFFF if all the selected -pages have been erased.
    • Add a new interface HAL_FLASHEx_OBGetUserData to get the option byte user data.
  • HAL GPIO
    • Remove a useless assert_param on the pull mode in HAL_GPIO_Init.
  • HAL I2C
    • Correct issue at reception of 2 bytes using memory polling and IT interface.
    • Correct a wrong management of the AF flag.
  • HAL RCC
    • Reduce the timeout of HSI, LSI and PLL to be closer to HW specifications:
      • HSI_TIMEOUT_VALUE reduced from 100ms to 2ms
      • LSI_TIMEOUT_VALUE reduced from 100ms to 2ms
      • PLL_TIMEOUT_VALUE reduced from 100ms to 2ms
  • HAL SD
    • Correct wrong calculation of the capacity for High Capacity cards.
  • HAL SPI
    • Remove incorrect reset of DMA parameter in HAL_SPI_Receive_DMA and HAL_SPI_Transmit_DMA.
  • HAL TIM
    • Remove useless assert_param.
    • Rewrite the assert_param when setting clock source.
  • HAL UART
    • Manage the case of reception of a character while the driver is not expecting one. This was causing a crash of the driver.
  • LL USB
    • Remove the NoVbusSensing feature from driver. (feature not present on STM32F1xx)

V1.0.1 / 31-July-2015

- - - - - - - - - - - - - - - - - - - - -

Main -Changes

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • General updates to fix known defects and enhancements implementation.
  • HAL generic
    • stm32f1xx_hal_def.h
      • Update NULL definition to -fix C++ compilation issue.
  • HAL ADC
    • Optimization of macro __HAL_ADC_CLEAR_FLAG.
    • ADC poll for conversion now return error status in case of ADC-DMA mode.
    • ADC polling functions now return HAL_TIMEOUT (or HAL_ERROR in case of configuration error).
    • Removing field NbrOfConversionRank of ADC_HandleTypeDef. This field was useless on STM32F1xx.
    • Improving the ADC state machine.
  • HAL CAN
    • Field Data of CanRxMsgTypeDef and CanTxMsgTypeDef is changed from uint32_t to uint8_t.
  • HAL Cortex
    • Add MPU APIs in Cortex HAL driver.
  • HAL CRC
    • Correcting a wrong definition of __HAL_CRC_SET_IDR macro.
  • HAL DAC
    • HAL_IS_BIT_SET is nowused properly in HAL_DAC_Start.
    • Add 2 defines: DAC_WAVEGENERATION_NOISE and DAC_WAVEGENERATION_TRIANGLE.
    • HAL_DAC_Stop now disable DAC software conversion.
  • HAL DMA
    • Minor typographic updates.
  • HAL ETH
    • ETH_MAC_READCONTROLLER_FLUSHING: Removing a space in the middle of the name.
    • Removing some duplicated macros.
  • HAL FLASH
    • FLASH_OB_GetRDP -returns uint32_t instead of FlagStatus. (internal function). This -permit a more coherent use for HAL_FLASHEx_OBGetConfig -and HAL_FLASHEx_OBProgram.
    • Correct an issue making impossible to set Flash read protection level1 and  level2.
    • The activation of backup domain in RCC is systematic.
  • HAL I2C
    • Correct an issue depending of APB/I2C frequency which was preventing the STOP bit to be cleared.
      • The POS bit is now cleared at the beginning of each I2C API.
      • The POS bit is no more cleared near STOP generation.
  • HAL I2S
    • HAL_I2S_Transmit() API is updated to keep the check on busy flag only for the slave.
  • HAL NAND
    • Review __ARRAY_ADDRESS macro and adapt tests to detect bad blocks
  • HAL RCC
    • In HAL_RCCEx_PeriphCLKConfig, Reset backup domain only if RTC clock source has been changed.
    • Update of HAL_RCC_OscConfig functionto correctly check LSEState.
    • Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.
    • New HAL RCC macro to configure the SYSCLK clock source: __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__).
    • Adding macro: __HAL_RCC_MCO_CONFIG.
    • For some RPN, the prediv source management in HAL_RCC_OscConfig function was not used.
  • HAL RTC
    • CMSIS mask definition used instead of hardcoded values.
  • HAL SMARTCARD
    • Improve documentation
  • HAL TIM
    • All STM32F101xx and STM32F102xx defines were missing in the file stm32f1xx_hal_tim_ex.h.
    • The assert on trigger polarity for TI1F_ED is removed.
  • HAL USB
    • Correct issue preventing USB Device double-buffering mode for IN endpoints to correctly behave.
    • Correct a bad configuration of Turnaround Time.
    • Correct USB_FlushTxFifo function which was leading to a GRSTCTL register corruption.
    • Replaced -the access to  USB_OTG_HCCHAR_CHDIS and USB_OTG_HCCHAR_CHENA -from a sequencial access to a simultaneous access.

V1.0.0 / 15-December-2014

Main -Changes

-
  • First Official release of STM32F1xx HAL -Drivers for all STM32F1 devices.
  • This -release is in line with STM32Cube -Firmware specification Rev1.0 document 

License

-
-
-Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
    -     -
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Release Notes for STM32F2xx HAL Drivers

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Copyright - 2017 STMicroelectronics

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Update History

V1.2.1 / 14-April-2017

Main -Changes

- -
  • General updates -to fix known defects and enhancements implementation
  • HAL CONF Template update
    • Add support for HAL MMC driver. 
  • HAL CAN update
    • Add - management of overrun error. 
    • Allow - possibility to receive messages from the 2 RX FIFOs in parallel via - interrupt.
    • Fix message - lost issue with specific sequence of transmit requests.
    • Handle - transmission failure with error callback, when NART is enabled.
    • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when - timeout is reached

V1.2.0 / 17-March-2017

Main -Changes

- -
  • Add Low Layer drivers allowing performance and footprint optimization
    • Low -Layer drivers APIs provide register level programming: require deep -knowledge of peripherals described in STM32F2xx Reference Manuals
    • Low -Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, PWR, RCC, RNG, RTC, SPI, TIM, -USART, WWDG peripherals and additionnal Low Level Bus, System and -Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f2xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f2xx_ll_ppp.h file must be included in user code.
  • General updates to fix known defects and enhancements implementation
  • Fix extra warnings with GCC compiler
  • HAL drivers clean up: remove double casting 'uint32_t' and 'U'
  • Add new HAL MMC driver
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • HAL SD update
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
    • HAL NAND update
      • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • Add new HAL_NAND_ConfigDevice API
  • HAL update
    • Modifiy default HAL_Delay implementation to guarantee minimum delay
    • Add HAL_GetUID API : returns the unique device identifier
  • HAL Cortex update
    • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f2xx_hal_cortex.h to stm32f2xx_hal_cortex.c
    • Clear the whole MPU control register in HAL_MPU_Disable() API
  • HAL FLASH update
    • IS_FLASH_ADDRESS() macro update to support OTP range
    • FLASH_Program_DoubleWord(): Replace 64-bit accesses with 2 double-words operations
  • HAL GPIO update
    • Update IS_GPIO_PIN() macro implementation to be more safe
  • HAL RCC update
    • Update IS_RCC_PLLQ_VALUE() macro implementation: the minimum accepted value is 2 instead of 4
    • Update to refer to AHBPrescTable[] and APBPrescTable[] tables defined in system_stm32f2xx.c file instead of APBAHBPrescTable[] table.
  • HAL DMA update
    • HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst 
  • HAL UART/USART/IrDA/SMARTCARD (referenced as PPP here below) 

    • DMA Receive process; the code -has been updated to clear the PPP OVR flag before enabling DMA receive request.

    • Add transfer abort APIs and associated callbacks : 
      • HAL_PPP_Abort()
      • HAL_PPP_AbortTransmit()
      • HAL_PPP_AbortReceive()
      • HAL_PPP_Abort_IT()
      • HAL_PPP_AbortTransmit_IT()
      • HAL_PPP_AbortReceive_IT()
      • HAL_PPP_AbortCpltCallback()
      • HAL_PPP_AbortTransmitCpltCallback()
      • HAL_PPP_AbortReceiveCpltCallback()
  • HAL CAN update
    • Remove Lock mechanism from HAL_CAN_Transmit_IT() and HAL_CAN_Receive_IT() processes
    • HAL CAN driver optimization
  • HAL TIM update

    • Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state. 

    • Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption.
  • HAL I2C update
    • Update -HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending -extra bytes at the end of the transmit processes
    • Update - HAL_I2C_Mem_Read() API to fix wrong check on misused parameter Size
    • Update - I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to - enhance Master sequential reception process.
  • HAL SPI update
    • Add transfer abort APIs and associated callbacks in interrupt mode
      • HAL_SPI_Abort()
      • HAL_SPI_Abort_IT()
      • HAL_SPI_AbortCpltCallback()
-
  • HAL USB PCD update
    • Flush all TX FIFOs on USB Reset
    • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's
  • LL USB update
    • Enable DMA Burst mode for USB OTG HS
    • Fix SD card detection issue
  • LL SDMMC update
    • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions

V1.1.3 / 29-June-2016

- -

Main Changes

- - - - - - -
  • General updates to fix known defects and enhancements implementation
  • Enhance HAL delay and time base implementation:
    • Add -new drivers stm32f2xx_hal_timebase_tim_template.c, -stm32f2xx_hal_timebase_rtc_alarm_template.c and -stm32f2xx_hal_timebase_rtc_wakeup_template.c which override the native -HAL time base functions (defined as weak) to either use the TIM or the -RTC as time base tick source. For more details about the usage of these -drivers, please refer to HAL\HAL_TimeBase examples and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.1.2
    • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C (referenced as PPP here below) drivers
      • Add PPP error management during DMA process. This requires the following updates on user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f2xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
    • HAL I2C driver:
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in theDMA transfer process. This requires the following updates on user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f2xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
      • I2C -transfer processes IT update: NACK during addressing phase is managed -through I2C Error interrupt instead of HAL state
    • HAL IWDG driver: rework overall driver for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: rework overall driver for better implementation
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs 
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef -*hwwdg, uint32_t counter)  function and API  by removing the - "counter" parameter
  • HAL Generic update
    • stm32f2xx_hal_conf_template.h
      • Optimize HSE Startup Timeout value from 5000ms to 100 ms
      • Add new define LSE_STARTUP_TIMEOUT
      • Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled.
    • Update HAL drivers to support MISRA C 2004 rule 10.6
    • Add new template driver to configure timebase using TIMER :
      • stm32f2xx_hal_timebase_tim_template.c
  • HAL CAN update
    • Update HAL_CAN_Transmit() and HAL_CAN_Transmit_IT() functions to unlock process when all Mailboxes are busy
  • HAL DCMI update
    • Rename DCMI_DMAConvCplt to DCMI_DMAXferCplt
    • Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral
    • Add new timeout implementation based on cpu cycles for DCMI stop
    • Add HAL_DCMI_Suspend() function to suspend DCMI capture
    • Add HAL_DCMI_Resume() function to resume capture after DCMI suspend
    • Update lock mechanism for DCMI process
    • Update HAL_DCMI_IRQHandler() function to
      • Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
      • Optimize code by using direct register read
  • HAL DMA update
    • Add -new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to -register/unregister the different callbacks identified by the enum -typedef HAL_DMA_CallbackIDTypeDef
    • Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context
      • The new registered Abort callback is called when DMA transfer abortion is completed
    • Add the check of compatibility between FIFO threshold level and size of the memory burst in the HAL_DMA_Init() API
    • Add new Error Codes: HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED
    • Remove all DMA states related to MEM0/MEM1 in HAL_DMA_StateTypeDef
  • HAL ETH update
    • Removal of ETH MAC debug register defines
  • HAL HCD update
    • Update HCD_Port_IRQHandler() to unmask disconnect IT only when the port is disable
  • HAL I2C update
    • Add support of I2C repeated start feature:
      • With the following new API's
        • HAL_I2C_Master_Sequential_Transmit_IT()
        • HAL_I2C_Master_Sequential_Receive_IT()
        • HAL_I2C_Master_Abort_IT()
        • HAL_I2C_Slave_Sequential_Transmit_IT()
        • HAL_I2C_Slave_Sequential_Receive_IT()
        • HAL_I2C_EnableListen_IT()
        • HAL_I2C_DisableListen_IT()
      • Add new user callbacks:
        • HAL_I2C_ListenCpltCallback()
        • HAL_I2C_AddrCallback()
    • Update to generate STOP condition when a acknowledge failure error is detected
    • Several update on HAL I2C driver to implement the new I2C state machine: 
      • Add new API to get the I2C mode: HAL_I2C_GetMode()
      • Update I2C process to manage the new I2C states.
    • Fix wrong behaviour in single byte transmission 
    • Update I2C_WaitOnFlagUntilTimeout() to manage the NACK feature.
    • Update  I2C transmission process to support the case data size equal 0
    • Update Polling management:
      • The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Add the management of Abort service: Abort DMA transfer through interrupt
      • In the case of Master Abort IT transfer usage:
        • Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process
        • A new abort state is defined in the HAL_I2C_StateTypeDef structure
    • Add -the management of I2C peripheral errors, ACK failure and STOP condition -detection during DMA process. This requires the following updates on -user application:
      • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
      • In stm32f2xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
      • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
    • NACK error during addressing phase is returned through interrupt instead of previously through I2C transfer API's
    • I2C addressing phase is updated to be managed using interrupt instead of polling (Only for HAL I2C driver)
      • Add new static functions to manage I2C SB, ADDR and ADD10 flags
  • HAL IRDA update
    • Several update on HAL IRDA driver to implement the new UART state machine: 
      • Add new field in IRDA_HandleTypeDef structure: "rxState", IRDA state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": IRDA state information related to global Handle management and Tx Operations
      • Update IRDA process to manage the new UART states.
      • Update __HAL_IRDA_RESET_HANDLE_STATE() macro to handle the new IRDA state parameters (gState, rxState)
    • Removal of IRDA_TIMEOUT_VALUE define
    • Update IRDA_BRR() Macro to fix wrong baudrate calculation
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of IRDA peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the IRDA IRQ in HAL_IRDA_MspInit() function
        • In stm32f2xx_it.c file, IRDA_IRQHandler() function: add a call to HAL_IRDA_IRQHandler() function
        • Add and customize the Error Callback API: HAL_IRDA_ErrorCallback()
  • HAL IWDG update
    • Overall rework of the driver for a more efficient implementation
      • Remove the following APIs:
        • HAL_IWDG_Start()
        • HAL_IWDG_MspInit()
        • HAL_IWDG_GetState()
      • Update implementation:
        • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter
        • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
      • Refer to the following example to identify the changes: IWDG_Example
  • HAL NOR update
    • Update NOR_ADDR_SHIFT macro implementation
  • HAL PCD update
    • Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value
  • HAL  RCC update
    • Add new default define value for HSI calibration "RCC_HSICALIBRATION_DEFAULT"
    • Optimize Internal oscillators and PLL startup timeout 
    • Update -to avoid the disable for HSE/LSE oscillators before setting the new RCC -HSE/LSE configuration and add the following notes in -HAL_RCC_OscConfig() API description:
     -              -          * @note   -Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 
    -            -             -*             -supported by this API. User should request a transition to LSE Off 
    -            -             -*             first -and then LSE On or LSE Bypass. 
    -            -             * -@note   Transition HSE Bypass to HSE On and HSE On to HSE -Bypass are not 
    -            -             -*             -supported by this API. User should request a transition to HSE Off 
    -            -             -*             first -and then HSE On or HSE Bypass.
    • Optimize the HAL_RCC_ClockConfig() API implementation
    • Update HAL_RCC_ClockConfig() function to adjust the SystemCoreClock
    • HAL_RCCEx_PeriphCLKConfig() API: update to fix the RTC clock configuration issue
  • HAL RTC update 
    • Add new timeout implementation based on cpu cycles for ALRAWF, ALRBWF and WUTWF flags
  • HAL SMARTCARD update
    • Several update on HAL SMARTCARD driver to implement the new UART state machine: 
      • Add new field in SMARTCARD_HandleTypeDef structure: "rxState", SMARTCARDstate information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": SMARTCARDstate information related to global Handle management and Tx Operations
      • Update SMARTCARD process to manage the new UART states.
      • Update __HAL_SMARTCARD_RESET_HANDLE_STATE() macro to handle the new SMARTCARD state parameters (gState, rxState)
    • Update SMARTCARD_BRR() macro to fix wrong baudrate calculation
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of SMARTCARD peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the SMARTCARD IRQ in HAL_SMARTCARD_MspInit() function
        • In stm32f2xx_it.c file, SMARTCARD_IRQHandler() function: add a call to HAL_SMARTCARD_IRQHandler() function
        • Add and customize the Error Callback API: HAL_SMARTCARD_ErrorCallback()
  • HAL SPI update
    • Major Update to improve performance in polling/interrupt mode to reach max frequency:
      • Polling mode:
        • Replace use of SPI_WaitOnFlagUnitTimeout() funnction by "if" statement to check on RXNE/TXE flage while transferring data
        • Use API data pointer instead of SPI handle data pointer
        • Use a Goto implementation instead of "if..else" statements
      • Interrupt mode:
        • Minimize access on SPI registers
        •  Split the SPI modes into dedicated static functions to minimize checking statements under HAL_IRQHandler():
          • 1lines/2lines modes
          • 8 bit/ 16 bits data formats
          • CRC calculation enabled/disabled
        • Remove waiting loop under ISR when closing - the communication
      • All modes
        • Adding switch USE_SPI_CRC to minimize number of -statements when CRC calculation is disabled
        • Update Timeout management to check on global -process
        • Update Error code management in all processes
    • Update DMA process:
      • Add the management of SPI peripheral errors during DMA process. This requires the following updates in the user application:
        • Configure and enable the SPI IRQ in HAL_SPI_MspInit() function
        • In stm32f2xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function
        • Add and customize the Error Callback API: HAL_SPI_ErrorCallback()
        • Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA
  • HAL UART update
    • Several update on HAL UART driver to implement the new UART state machine: 
      • Add new field in UART_HandleTypeDef structure: "rxState", UART state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": UART state information related to global Handle management and Tx Operations
      • Update UART process to manage the new UART states.
      • Update __HAL_UART_RESET_HANDLE_STATE() macro to handle the new UART state parameters (gState, rxState)
    • Update UART_BRR_SAMPLING16() and UART_BRR_SAMPLING8() Macros to fix wrong baudrate calculation.
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of UART peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the UART IRQ in HAL_UART_MspInit() function
        • In stm32f2xx_it.c file, UART_IRQHandler() function: add a call to HAL_UART_IRQHandler() function
        • Add and customize the Error Callback API: HAL_UART_ErrorCallback()
  • HAL USART update
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of USART peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the USART IRQ in HAL_USART_MspInit() function
        • In stm32f2xx_it.c file, USART_IRQHandler() function: add a call to HAL_USART_IRQHandler() function
        • Add and customize the Error Callback API: HAL_USART_ErrorCallback()
  • HAL WWDG update 
    • Overall rework of the driver for more efficient implementation
      • Remove the following APIs:
        • HAL_WWDG_Start()
        • HAL_WWDG_Start_IT()
        • HAL_WWDG_MspDeInit()
        • HAL_WWDG_GetState()
      • Update implementation:
        • HAL_WWDG_Init()
          • A new parameter in the Init structure: EWIMode
        • HAL_WWDG_MspInit()
        • HAL_WWDG_Refresh() 
          • This function insures the reload of the counter
          • The "counter" parameter has been removed
        • HAL_WWDG_IRQHandler()
        • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback()
    • Refer to the following example to identify the changes: WWDG_Example

V1.1.2 / 11-December-2015

-

Main -Changes

  • HAL RCC update
    • Fix -compilation errors with the  __HAL_RCC_DAC_IS_CLK_DISABLED(), -__HAL_RCC_CRYP_IS_CLK_DISABLED() and __HAL_RCC_HASH_IS_CLK_DISABLED() -macros
  • HAL ETH update 
    • Update HAL_ETH_Init() function to add timeout on the Software reset management

V1.1.1 / 20-November-2015

Main Changes

- - - - - - -
  • General updates to fix known defects and enhancements implementation
  • One change done on the HAL CRYP requires an update on the application code based on HAL V1.1.0
    • Update HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData parameters
  • HAL generic update
    • Update -HAL weak empty callbacks to prevent unused argument compilation -warnings with some compilers by calling the following line:
      • UNUSED(hppp);
    • HSE_STARTUP_TIMEOUT constant has been corrected in stm32f2xx_hal_conf_template.h file, its value changed from 5000 to 100. 
-
  • HAL CORTEX update
    • Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
  • HAL HASH update
    • Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef
    • Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef
  • HAL RCC update
    • Add new macros __HAL_RCC_PPP_IS_CLK_ENABLED() to check on Clock enable/disable status
    • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG
  • HAL FLASH update
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset  ICRST bit in the ACR register after setting it.
  • -

    HAL CRYP update

    • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
  • HAL TIM update
    • Update HAL_TIM_ConfigClockSource() API to check only the required parameters
  • HAL NAND update
    • Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access
  • HAL CAN update
    • Update to use "=" instead of "|=" to clear flags in the MSR, TSR, RF0R and RF1R registers
  • HAL PCD update
    • Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation
  • LL FSMC update
    • Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters

V1.1.0 / 09-October-2015

Main Changes

  • Maintenance release to fix known defects and enhancements implementation
  • Macros and literals renaming to ensure compatibles across STM32 series, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy
  • Add *.chm UM for all drivers
  • Update drivers to be C++ compliant
  • Several update on source code formatting, for better UM generation (i.e. Doxygen tags updated)
  • Four changes done on the HAL requires an update on the application code based on HAL V1.0.1
    • LSI_VALUE constant has been corrected in stm32f2xx_hal_conf.h file, its value changed from 40 KHz to 32 KHz
    • UART, USART, IRDA and SMARTCARD (referenced as PPP here below) drivers: in DMA transmit process, the code has been updated to avoid waiting on TC flag under DMA ISR, PPP TC interrupt is used instead. Below the update to be done on user application:
      • Configure and enable the USART IRQ in HAL_PPP_MspInit() function
      • In stm32f2xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
    • CRYP driver updated to support multi instance,so user must ensure that the new parameter Instance is initialized in his application(CRYPHandle.Instance = CRYP) 
    • HASH IT process: update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
  • HAL generic update
    • stm32f2xx_hal_def.h
      • Remove NULL definition and add include for stdio.h
      • Add UNUSED() macro

      • Add a new define __NOINLINE to be used for the no inline code independent from tool chain

    • stm32f2xx_hal_conf_template.h
      • Add a new define for LSI default value LSI_VALUE
      • Add a new define for LSE default value LSE_VALUE
      • Add a new define for Tick interrupt priority TICK_INT_PRIORITY (needed for the enhanced time base implementation)
    • Enhance HAL delay and time base implementation
      -
      • Systick -timer is used by default as source of time base, but user can -eventually implement his proper time base source (a general purpose -timer for example or other time source)
      • Functions -affecting time base configurations are declared as __Weak to make -override possible in case of other implementations in user file, for -more details please refer to HAL_TimeBase example
    • Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="
    • Fix -on Timeout management, Timeout value set to 0 passed to API -automatically exits the function after checking the flag without any -wait
    • Common update for the following communication peripherals: SPI, UART, USART and IRDA
      • Add DMA circular mode support
      • Remove lock from recursive process
    • Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state
    • Add a new attribute for functions executed from internal SRAM and depending from Compiler implementation
    • When USE_RTOS == 1 (in stm32f2xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty
    • Miscellaneous comments and formatting update
    • Update all macros and literals naming to be upper case
    • ErrorCode parameter in PPP_HandleTypeDef structure updated to uint32_t instead of enum HAL_PPP_ErrorTypeDef
    • Remove the unused FLAG and IT assert macros
    • stm32f2xx_hal_ppp.c
      • HAL_PPP_Init(): update to force the HAL_PPP_STATE_RESET before calling the HAL_PPP_MspInit()
    • Important Note: aliases has been added for any API naming change, to keep compatibility with previous version
  • HAL ADC update
    • ADC HAL state -machine update to use bit fields instead of enum:
      • HAL_ADC_StateTypeDef enum fields are replaced by respective defines
    • Add new literal: ADC_SOFTWARE_START to be used as possible value for the ExternalTrigConv parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode.
    • IS_ADC_CHANNEL() macro update to don't assert stop the ADC_CHANNEL_TEMPSENSOR value
    • HAL_ADC_PollForConversion(): -update to manage particular case when ADC configured in DMA mode and -ADC sequencer with several ranks and polling for end of each conversion
    • HAL_ADC_Start()/HAL_ADC_Start_IT() /HAL_ADC_Start_DMA() update:
      • unlock the process before starting the ADC software conversion.
      • Optimize the ADC stabilization delays
    • __HAL_ADC_GET_IT_SOURCE() update macro implementation
    • Add more details in 'How to use this driver' section
    • Add -new literal: ADC_INJECTED_SOFTWARE_START to be used as possible value -for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef -structure to select the ADC software trigger mode.
  • HAL DAC update
    • Enhance the DMA channel - configuration when used with DAC

    • HAL_DAC_ConfigChannel(): update the access to the DAC peripheral registers via the hdac handle instance

    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and DAC_FLAG_DMAUDR2
    • HAL_DACEx_NoiseWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration
    • HAL_DACEx_TriangleWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration

    • Add new macro to check if the specified DAC interrupt source is enabled or disabled

      • __HAL_DAC_GET_IT_SOURCE()
    • HAL_DACEx_TriangleWaveGeneration() update to use DAC CR bit mask definition
    • HAL_DACEx_NoiseWaveGeneration() update to use DAC CR bit mask definition
  • HAL CAN update

    • Unlock the CAN process when communication error occurred

    • CanTxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
    • CanRxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
  • HAL CORTEX update
    • Add new macro IS_NVIC_DEVICE_IRQ() to check on negative values of IRQn parameter
    • Add specific API for MPU management
      • add MPU_Region_InitTypeDef structure
      • add new function HAL_MPU_ConfigRegion()

  • HAL CRYP update

    • HAL_CRYP_DESECB_Decrypt_DMA(): fix the inverted pPlainData and pCypherData parameters issue
    • Add restriction for the CCM Encrypt/Decrypt API's that only DataType equal to 8bits is supported
    • Update to manage multi instance:
      • Add new parameter Instance in the CRYP_HandleTypeDef Handle structure.
      • Add new parameter in all HAL CRYP macros
        • example: __HAL_CRYP_ENABLE()  updated by __HAL_CRYP_ENABLE(__HANDLE__)

  • HAL DCMI update

    • HAL_DCMI_ConfigCROP(): Invert assert macros to check Y0 and Ysize parameters

  • HAL DMA update

    • Overall driver update for code optimization
      • add StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef structure
      • add DMA_Base_Registers private structure
      • add static function DMA_CalcBaseAndBitshift()
      • update HAL_DMA_Init() function to use the new added static function
      • update HAL_DMA_DeInit() function to optimize clear flag operations
      • update HAL_DMA_Start_IT() function to optimize interrupts enable
      • update HAL_DMA_PollForTransfer() function to optimize check on flags
      • update HAL_DMA_IRQHandler() function to optimize interrupt flag management
    • Fix in HAL_DMA_PollForTransfer() to:
      • set DMA error code in case of HAL_ERROR status
        -
      • set HAL Unlock before DMA state update

    • HAL_DMA_Init(): Update to clear the DBM bit in the SxCR register before setting the new configuration

    • DMA_SetConfig(): add to clear the DBM bit in the SxCR register

  • HAL FLASH update

    • update HAL_FLASH_Program_IT() function by removing the pending flag clear
    • update HAL_FLASH_IRQHandler() function to improve erase operation procedure
    • update FLASH_WaitForLastOperation() function by checking on end of operation flag
    • Add "HAL_" prefix in the defined values for the FLASH error code
      • Example: FLASH_ERROR_PGP renamed by HAL_FLASH_ERROR_PGP
    • Clear the Flash ErrorCode in the FLASH_WaitForLastOperation() function
    • Update FLASH_SetErrorCode() function to use "|=" operant to update the Flash ErrorCode parameter in the FLASH handle
    • IS_FLASH_ADDRESS(): Update the macro check using '<=' condition instead of '<'
    • IS_OPTIONBYTE(): Update the macro check using '<=' condition instead of '<'
    • Add "FLASH_" prefix in the defined values of FLASH Type Program parameter
      • Example: TYPEPROGRAM_BYTE renamed by FLASH_TYPEPROGRAM_BYTE
    • Add "FLASH_" prefix in the defined values of FLASH Type Erase parameter
      • Example: TYPEERASE_SECTORS renamed by FLASH_TYPEERASE_SECTORS
    • Add "FLASH_" prefix in the defined values of FLASH Voltage Range parameter
      • Example: VOLTAGE_RANGE_1 renamed by FLASH_VOLTAGE_RANGE_1
    • Add "OB_" prefix in the defined values of FLASH WRP State parameter
      • Example: WRPSTATE_ENABLE renamed by OB_WRPSTATE_ENABLE
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset  ICRST bit in the ACR register after setting it.
    • __HAL_FLASH_DATA_CACHE_RESET() macro: update to reset  DCRST bit in the ACR register after setting it.
    • FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus
    •  __HAL_FLASH_GET_LATENCY() new macro add to get the flash latency

  • HAL ETH update

    • Update HAL_ETH_GetReceivedFrame_IT() function to return HAL_ERROR if the received packet is not complete
    • Use HAL_Delay() instead of counting loop
      -
    •  __HAL_ETH_MAC_CLEAR_FLAG() macro is removed: the MACSR register is read only
    • Add the following macros used to - Wake up the device from STOP mode by Ethernet event :
      • __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()
      • __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()
      • __HAL_ETH_WAKEUP_EXTI_GET_FLAG()
      • __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()
      • __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EGDE_TRIGGER()
      • __HAL_ETH_WAKE_EXTI_ENABLE_FALLING_EGDE_TRIGGER()
      • __HAL_ETH_WAKE_EXTI_ENABLE_FALLINGRISING_TRIGGER()
-
    • Rename literals
      • ETH_PROMISCIOUSMODE_ENABLE by ETH_PROMISCUOUS_MODE_ENABLE
      • ETH_PROMISCIOUSMODE_DISABLE by ETH_PROMISCUOUS_MODE_DISABLE
    • Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
    • Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)

  • HAL PWR update

    • HAL_PWR_ConfigPVD(): add clear of the EXTI trigger before new configuration
      -
    • Fix -in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which -need to be cleared at application level before to call this function
    • HAL_PWR_EnterSLEEPMode()
      • Remove disable and enable of SysTick Timer
      • Update to clear SLEEPDEEP bit of Cortex System Control Register (SCB->SCR) before entering in sleep mode
      • Update -usage of __WFE() in low power entry function: if there is a pending -event, calling __WFE() will not enter the CortexM3 core to sleep mode. -The solution is to made the call below; the first __WFE() is always -ignored and clears the event if one was already pending, the second is -always applied
        -
-
__SEV()
- __WFE()
- __WFE()
-
    • Add new macro for software event generation __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
    • Remove -the following defines form Generic driver and add them under extension -driver because they are only used within extension functions.
    • CR_FPDS_BB: used within HAL_PWREx_EnableFlashPowerDown() function
    • CSR_BRE_BB: used within HAL_PWREx_EnableBkUpReg() function
    • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register
      • HAL_PWR_DisableSleepOnExit()
      • HAL_PWR_EnableSleepOnExit()
      • HAL_PWR_EnableSEVOnPend()
      • HAL_PWR_DisableSEVOnPend()
    • HAL_PWR_EnterSLEEPMode()
      • Update to clear the CORTEX SLEEPDEEP bit of SCR register before entering in sleep mode

    • Add new PVD configuration modes

      • PWR_PVD_MODE_NORMAL
      • PWR_PVD_MODE_EVENT_RISING 
      • PWR_PVD_MODE_EVENT_FALLING
      • PWR_PVD_MODE_EVENT_RISING_FALLING

    • Add new macros to manage PVD Trigger

      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
      • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
      • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()

    • PVD macros:

      • Remove the __EXTILINE__ parameter
      • Update to use prefix "__HAL_PWR_PVD_" instead of  prefix "__HAL_PVD"
    • Rename HAL_PWR_PVDConfig() function by HAL_PWR_ConfigPVD()
  • HAL GPIO update
    • Rename GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW
    • Rename GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM
    • Rename GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH
    • Rename GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH
    • Add a new macro - __HAL_GPIO_EXTI_GENERATE_SWIT() to manage the generation of software interrupt - on selected EXTI line
    • HAL_GPIO_Init(): -use temporary variable when modifying the registers, to avoid -unexpected transition in the GPIO pin configuration
      -
    • Remove IS_GET_GPIO_PIN macro
    • Add a new function HAL_GPIO_LockPin()
    • Update the following HAL GPIO macros description: rename EXTI_Linex by GPIO_PIN_x
      • __HAL_GPIO_EXTI_CLEAR_IT()
      • __HAL_GPIO_EXTI_GET_IT()
      • __HAL_GPIO_EXTI_CLEAR_FLAG()
      • __HAL_GPIO_EXTI_GET_FLAG()

    • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call to the CMSIS assert macro to check GPIO instance: IS_GPIO_ALL_INSTANCE() 

    • Rename __HAL_GET_GPIO_SOURCE() by GPIO_GET_INDEX() and move this later to file stm32f2xx_hal_gpio_ex.h
    • HAL_GPIO_DeInit(): -Update to check if GPIO Pin x is already used in EXTI mode on -another GPIO Port before De-Initialize the EXTI registers
  • HAL HASH update
    • HAL_HASH_MD5_Start_IT(): fix input address management issue
    • HAL_HASH_MODE_Start_IT() (MODE stands for MD5 and SHA1) updates:
      • Fix processing fail for small input buffers
      • Update -to unlock the process and call return HAL_OK at the end of HASH -processing to avoid incorrectly repeating software
      • Update to properly manage the HashITCounter
      • Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
    • __HAL_HASH_GET_FLAG() update to  check the right register when the DINNE flag  is selected
    • HAL_HASH_SHA1_Accumulate() updates:
      • Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. 
      • Add the following note in API description
 * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
  • HAL RCC update
    • HAL_RCCEx_PeriphCLKConfig() updates:
      • Update -the LSE check condition after backup domain reset: update to -check LSE ready flag when LSE oscillator is already enabled -instead of check on LSE oscillator only when LSE is used as RTC clock -source
    • In HAL_RCC_ClockConfig() - function: update the AHB clock divider before clock switch to new source
    • Allow to calibrate the HSI when it is used as system clock source
      -
    • Reorganize the RCC macros to make them more clear
    • Rename the following Macros
      • __PPP_CLK_ENABLE()  by __HAL_RCC_PPP_CLK_ENABLE()
      • __PPP_CLK_DISABLE()  by __HAL_RCC_PPP_CLK_DISABLE()
      • __PPP_FORCE_RESET()  by __HAL_RCC_PPP_FORCE_RESET()
      • __PPP_RELEASE_RESET()  by __HAL_RCC_PPP_RELEASE_RESET()
      • __PPP_CLK_SLEEP_ENABLE() by __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
      • __PPP_CLK_SLEEP_DISABLE() by __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
    • Add description of RCC known Limitations
    • HAL_RCC_OscConfig() fix issues: 
      • Remove the disable of HSE oscillator when HSE_BYPASS is used as system clock source or as PPL clock source
      • Add a check on HSERDY flag when HSE_BYPASS is selected as new state for HSE oscillator.
    • Rename __HAL_RCC_I2SCLK() by __HAL_RCC_I2S_Config()
    • __HAL_RCC_PPP_CLK_ENABLE(): Implement workaround to cover RCC limitation regarding peripheral enable delay
    • HAL_RCC_OscConfig() fix issues: 
      • Add a check on LSERDY flag when LSE_BYPASS is selected as new state for LSE oscillator.
    • __HAL_RCC_HSE_CONFIG()  macro: add the comment below:
 * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. 
 *         -User should request a transition to HSE Off first and then HSE On or -HSE Bypass.
    • __HAL_RCC_LSE_CONFIG()  macro: add the comment below:
  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
  -*         User should request a -transition to LSE Off first and then LSE On or LSE Bypass.
    • Add the following new macros for PLL source and PLLM selection :
      • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
      • __HAL_RCC_PLL_PLLM_CONFIG()
    • Add __HAL_RCC_SYSCLK_CONFIG() new macro to configure the system clock source (SYSCLK)
    • __HAL_RCC_GET_SYSCLK_SOURCE() updates:
      • Add new RCC Literals:
        • RCC_SYSCLKSOURCE_STATUS_HSI
        • RCC_SYSCLKSOURCE_STATUS_HSE
        • RCC_SYSCLKSOURCE_STATUS_PLLCLK
      •  Update macro description to refer to the literals above

  • HAL I2S update

    • HAL_I2S_Init(): add check on I2S instance using CMSIS macro IS_I2S_ALL_INSTANCE() 
    • HAL_I2S_IRQHandler() update for compliancy w/ C++
    • Add use of tmpreg variable in __HAL_I2S_CLEAR_OVRFLAG() and __HAL_I2S_CLEAR_UDRFLAG() macro for compliancy with C++
    • HAL_I2S_GetError(): update to return uint32_t instead of HAL_I2S_ErrorTypeDef enumeration
    • HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode

  • HAL I2C update

    • I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR.
    • Update busy flag Timeout value
    • I2C Master Receive Processes update to disable ACK before generate the STOP 
    • Update to clear the POS bit in the CR1 register at the begging of all the HAL I2C  processes
    • Add use of tmpreg variable in __HAL_I2C_CLEAR_ADDRFLAG() and __HAL_I2C_CLEAR_STOPFLAG() macro for compliancy with C++
  • HAL IrDA update
    • Add specific macros -to manage the flags cleared only by a software sequence -
      • __HAL_IRDA_CLEAR_PEFLAG() -
      • __HAL_ IRDA -_CLEAR_FEFLAG() -
      • __HAL_ IRDA -_CLEAR_NEFLAG() -
      • __HAL_ IRDA -_CLEAR_OREFLAG() -
      • __HAL_ IRDA -_CLEAR_IDLEFLAG()
      -
    • Add several -enhancements without affecting the driver functionalities -
      • Remove the check on -RXNE set after reading the Data in the DR register
        -
      • Update HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC
      -
    • Add the following -APIs used within DMA process -
      • HAL_StatusTypeDef -HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
      -
      • HAL_StatusTypeDef -HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); -
      • HAL_StatusTypeDef -HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); -
      • void -HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -
      • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef -*hirda);
    • DMA -transmit process; the code has been updated to avoid waiting on TC flag -under DMA ISR, IrDA TC interrupt is used instead. Below the update to -be done on user application:
      • Configure and enable the USART IRQ in HAL_IRDA_MspInit() function
      • In stm32f2xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_IRDA_IRQHandler() function
    • IT -transmit process; the code has been updated to avoid waiting on TC flag -under IRDA ISR, IrDA TC interrupt is used instead. No impact on user -application
    • Rename Macros: add prefix "__HAL"
      • __IRDA_ENABLE() by __HAL_IRDA_ENABLE()
      • __IRDA_DISABLE() by __HAL_IRDA_DISABLE()
    • Add new user macros to manage the sample method feature
      • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
    • HAL_IRDA_Transmit_IT(): update to remove the enable of the parity error interrupt
    • Add use of tmpreg variable in __HAL_IRDA_CLEAR_PEFLAG() macro for compliancy with C++
    • HAL_IRDA_Transmit_DMA() update to follow the right procedure "Transmission using DMA"  in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request

  • HAL SPI update

    • SPI interface is -used in synchronous polling mode: at high clock rates like SPI prescaler 2 and -4, calling
      HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT
    • HAL_SPI_TransmitReceive_DMA() does not clean -up the TX DMA, so any subsequent SPI calls return the DMA error
    • HAL_SPI_Transmit_DMA() is failing when data -size is equal to 1 byte
       -
    • Add the following -APIs used within the DMA process
-
      • HAL_StatusTypeDef -HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
      • HAL_StatusTypeDef -HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
      • HAL_StatusTypeDef -HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
      • void -HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
      • void -HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
      • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef -*hspi);

    • HAL_SPI_TransmitReceive_DMA() update to remove the  DMA Tx Error Callback initialization when SPI RxOnly mode is selected
    • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" warning with TrueSTUDIO.
    • Rename Literals: remove "D" from "DISABLED" and "ENABLED"
      • SPI_TIMODE_DISABLED by SPI_TIMODE_DISABLE
      • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
      • SPI_CRCCALCULATION_DISABLED by  SPI_CRCCALCULATION_DISABLE
      • SPI_CRCCALCULATION_ENABLED by  SPI_CRCCALCULATION_ENABLE
    • Add -use of tmpreg variable in __HAL_SPI_CLEAR_MODFFLAG(), -__HAL_SPI_CLEAR_FREFLAG() and __HAL_SPI_CLEAR_OVRFLAG() macros for compliancy with C++
    • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TransmitReceive_DMA() update to unlock the process before enabling the SPI peripheral
    • HAL_SPI_Transmit_DMA() update to manage correctly the DMA TX stream in SPI Full duplex mode
    • Section SPI_Exported_Functions_Group2 update to remove duplication in *.chm UM
    • Fix the wrong definition of HAL_SPI_ERROR_FLAG literal
  • HAL CRC update
    • These macros are added to read/write the CRC IDR register: __HAL_CRC_SET_IDR() and __HAL_CRC_GET_IDR()
    • __HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG()

  • HAL LL SDMMC update

    • Use of CMSIS constants instead of magic values
      -
    • Miscellaneous update in functions internal coding

    • IS_SDIO_ALL_INSTANCE()  macro moved to CMSIS files

  • HAL NAND update
    • Fix issue of macros returning wrong address for NAND blocks
    • Fix issue for read/write NAND page/spare area
    • Rename NAND Address structure to NAND_AddressTypeDef instead of NAND_AddressTypedef
    • Update the used algorithm of these functions
      • HAL_NAND_Read_Page()
      • HAL_NAND_Write_Page()
      • HAL_NAND_Read_SpareArea()
      • HAL_NAND_Write_SpareArea()

    • HAL_NAND_Write_Page(): move initialization of tickstart before while loop

    • HAL_NAND_Erase_Block(): add whait until NAND status is ready before exiting this function
  • HAL NOR update
    • Add the NOR address - bank macro used within the API
    • Update NOR API - implementation to avoid the use of NOR address bank hard coded
    • NOR Status literals renamed
      • NOR_SUCCESS by HAL_NOR_STATUS_SUCCESS
      • NOR_ONGOING by HAL_NOR_STATUS_ONGOING
      • NOR_ERROR by HAL_NOR_STATUS_ERROR
      • NOR_TIMEOUT by HAL_NOR_STATUS_TIMEOUT

    • HAL_NOR_GetStatus() update to fix Timeout issue and exit from waiting loop when timeout occurred

  • HAL PCCARD update
    • Rename PCCARD Address structure to HAL_PCCARD_StatusTypeDef instead of CF_StatusTypedef
    • PCCARD Status literals renamed
      • CF_SUCCESS by HAL_PCCARD_STATUS_SUCCESS
      • CF_ONGOING by HAL_PCCARD_STATUS_ONGOING
      • CF_ERROR by HAL_PCCARD_STATUS_ERROR
      • CF_TIMEOUT by HAL_PCCARD_STATUS_TIMEOUT
    • Update "CF" by "PCCARD" in functions, literals and macros
  • HAL HCD update
    • HCD_StateTypeDef structure members renamed
    • These macro are renamed
      • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__)    by __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
      • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) 
        -
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  by __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) 
    • Update to use local variable in USB Host channel re-activation
  • HAL PCD update
    • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() renamed into HAL_PCDEx_SetTxFiFo() and HAL_PCDEx_SetRxFiFo() and moved to the extension files stm32f2xx_hal_pcd_ex.h/.c
      -
    • PCD_StateTypeDef structure members renamed
    • Fix incorrect masking of TxFIFOEmpty
      -
    • stm32f2xx_ll_usb.c: fix issue in HS mode
      -
    • New macros added
      -
      • __HAL_PCD_IS_PHY_SUSPENDED()
      • __HAL_USB_HS_EXTI_GENERATE_SWIT()
      • __HAL_USB_FS_EXTI_GENERATE_SWIT()
    • These macro are renamed
      • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__)    by __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
      • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) 
        -
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  by __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) 
        -
      • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) by __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
      • __HAL_PCD_GATE_CLOCK(__HANDLE__) by __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
    • Rename functions
      • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
      • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
    • Rename literals
      • USB_FS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
      • USB_FS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
      • USB_FS_EXTI_TRIGGER_BOTH_EDGE() by USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
      • USB_HS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
      • USB_HS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
      • USB_HS_EXTI_TRIGGER_BOTH_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
      • USB_HS_EXTI_LINE_WAKEUP by USB_OTG_HS_WAKEUP_EXTI_LINE
      • USB_FS_EXTI_LINE_WAKEUP by USB_OTG_FS_WAKEUP_EXTI_LINE
    • Rename USB EXTI macros (FS, HS referenced as SUBBLOCK here below)
      • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT()  by  __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
      • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
      • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
      • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
      • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
      • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()
    • HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time                                       
  • HAL RNG update
    • Add new functions

      • HAL_RNG_GenerateRandomNumber(): to generate a 32-bits random number, return random value in argument and return HAL status.

      • HAL_RNG_GenerateRandomNumber_IT(): to  start generation of the 32-bits random number, user should call the HAL_RNG_ReadLastRandomNumber() function under the HAL_RNG_ReadyCallback() to get the generated random value.

      • HAL_RNG_ReadLastRandomNumber(): to return the last random value stored in the RNG handle

    • HAL_RNG_GetRandomNumber(): return value update (obsolete), replaced by HAL_RNG_GenerateRandomNumber()

    • HAL_RNG_GetRandomNumber_IT(): wrong implementation (obsolete), replaced by HAL_RNG_GenerateRandomNumber_IT()

    • __HAL_RNG_CLEAR_FLAG() macro (obsolete), replaced by new __HAL_RNG_CLEAR_IT() macro

    • Add new define for RNG ready interrupt:  RNG_IT_DRDY
  • HAL RTC update
    • Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag
    • HAL_RTC_GetTime() and HAL_RTC_GetDate(): add the comment below
  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
  * Reading RTC current time locks the values in calendar shadow registers until Current date is read. 
    • Rename literals: add prefix "__HAL"
      • FORMAT_BIN by RTC_FORMAT_BIN
      • FORMAT_BCD by RTC_FORMAT_BCD
    • Rename macros (ALARM, WAKEUPTIMER and TIMESTAMP referenced as SUBBLOCK here below)
      • __HAL_RTC_EXTI_ENABLE_IT() by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
      • __HAL_RTC_EXTI_DISABLE_IT() by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()

      • __HAL_RTC_EXTI_CLEAR_FLAG() by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()

      • __HAL_RTC_EXTI_GENERATE_SWIT() by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
    • Add new macros (ALARM, WAKEUPTIMER and TAMPER_TIMESTAMP referenced as SUBBLOCK here below)
      • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
      •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
      •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
      •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
    • Update to use CMSIS mask definition instead of hardcoded values (EXTI_IMR_IM17, EXTI_IMR_IM19..)
    • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro: fix implementation issue
    • __HAL_RTC_ALARM_GET_IT(), -__HAL_RTC_ALARM_CLEAR_FLAG(), __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), -__HAL_RTC_TIMESTAMP_CLEAR_FLAG() and __HAL_RTC_TAMPER_CLEAR_FLAG() -macros implementation changed: remove unused cast
    • IS_RTC_TAMPER() macro: update to use literal instead of hardcoded value 
    • Update to define hardware independent literals names:
      • Rename RTC_TAMPERPIN_PC13 by  RTC_TAMPERPIN_DEFAULT
      • Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1
      • Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1
      • Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT
      • Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1
      • Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1
  • HAL SD update
    • Rename SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
    • SD_PowerON() updated to add 1ms required power up waiting time before starting the SD initialization sequence
    • SD_DMA_RxCplt()/SD_DMA_TxCplt(): add a call to HAL_DMA_Abort()
    • HAL_SD_ReadBlocks() update to set the defined DATA_BLOCK_SIZE as SDIO DataBlockSize parameter
    • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() update to call the HAL_DMA_Start_IT() function withDMA Datalength set to BlockSize/4  as the DMA is configured in word 
  • HAL SMARTCARD update 
    • Add specific macros -to manage the flags cleared only by a software sequence -
      • __HAL_SMARTCARD_CLEAR_PEFLAG() -
      -
      • __HAL_SMARTCARD_CLEAR_FEFLAG() -
      -
      • __HAL_SMARTCARD_CLEAR_NEFLAG() -
      -
      • __HAL_SMARTCARD_CLEAR_OREFLAG() -
      -
      • __HAL_SMARTCARD_CLEAR_IDLEFLAG() -
      -
    • Add several -enhancements without affecting the driver functionalities -
      • Add a new state -HAL_SMARTCARD_STATE_BUSY_TX_RX and all -processes has been updated accordingly
      -
      • Update -HAL_SMARTCARD_Transmit_IT() to enable -SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC -
    • DMA -transmit process; the code has been updated to avoid waiting on TC flag -under DMA ISR, SMARTCARD TC interrupt is used instead. Below the update -to be done on user application:
      • Configure and enable the USART IRQ in HAL_SAMRTCARD_MspInit() function
      • In stm32f2xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_SMARTCARD_IRQHandler() function
    • IT transmit process; the code has been updated to avoid waiting on TC flag under SMARTCARD ISR, SMARTCARD TC interrupt is used instead. No impact on user application
    • Rename macros: add prefix "__HAL"
      • __SMARTCARD_ENABLE() by __HAL_SMARTCARD_ENABLE()
      • __SMARTCARD_DISABLE() by __HAL_SMARTCARD_DISABLE()
      • __SMARTCARD_ENABLE_IT() by __HAL_SMARTCARD_ENABLE_IT()
      • __SMARTCARD_DISABLE_IT() by __HAL_SMARTCARD_DISABLE_IT()
      • __SMARTCARD_DMA_REQUEST_ENABLE() by __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
      • __SMARTCARD_DMA_REQUEST_DISABLE() by __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
    • Rename literals: remove "D" from "DISABLED" and "ENABLED"
      • SMARTCARD_NACK_ENABLED by SMARTCARD_NACK_ENABLE
      • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
    • Add new user macros to manage the sample method feature
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
    • Add use of tmpreg variable in __HAL_SMARTCARD_CLEAR_PEFLAG() macro for compliancy with C++
    • HAL_SMARTCARD_Transmit_DMA() update to follow the right procedure "Transmission using DMA"  in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
      • HAL_SMARTCARD_Transmit_IT() update to force the disable for the ERR interrupt to avoid the OVR interrupt
      • HAL_SMARTCARD_IRQHandler() update check condition for transmission end
      • Clean up: remove the following literals that aren't used in smartcard mode
        • SMARTCARD_PARITY_NONE
        • SMARTCARD_WORDLENGTH_8B
        • SMARTCARD_STOPBITS_1
        • SMARTCADR_STOPBITS_2
  • HAL TIM update
    • HAL_TIM_IRQHandler(): update to check the input capture channel 3 and 4 in CCMR2 instead of CCMR1
    • __HAL_TIM_SET_PRESCALER() updated to use '=' instead of '|='
      -
    • Add the - following macro in TIM HAL driver
      • __HAL_TIM_GET_COMPARE()
      • __HAL_TIM_GET_COUNTER()
      • __HAL_TIM_GET_AUTORELOAD()
      • __HAL_TIM_GET_CLOCKDIVISION()
      • __HAL_TIM_GET_ICPRESCALER()
    • Add TIM_CHANNEL_ALL as possible value for all Encoder Start/Stop APIs Description
    • HAL_TIM_OC_ConfigChannel() remove call to IS_TIM_FAST_STATE() assert macro
    • HAL_TIM_PWM_ConfigChannel() add a call to IS_TIM_FAST_STATE() assert macro to check the OCFastMode parameter
    • TIM_DMADelayPulseCplt() Update to set the TIM Channel before to call  HAL_TIM_PWM_PulseFinishedCallback()
    • TIM_DMACaptureCplt() update to set the TIM Channel before to call  HAL_TIM_IC_CaptureCallback()
    • HAL_TIM_IC_ConfigChannel() update to fix Timer CCMR1 register corruption when setting ICFilter parameter
    • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() update to abort the DMA transfer for the specific TIM channel
    • Add new function for TIM Slave configuration in IT mode: HAL_TIM_SlaveConfigSynchronization_IT() 
    • HAL_TIMEx_ConfigBreakDeadTime() add an assert check on Break & DeadTime parameters values
    • HAL_TIMEx_OCN_Start_IT() add the enable of Break Interrupt for all output modes
    • Add new macros to ENABLE/DISABLE URS bit in TIM CR1 register:
      • __HAL_TIM_URS_ENABLE()
      • __HAL_TIM_URS_DISABLE()
    • Add new macro for TIM Edge modification: __HAL_TIM_SET_CAPTUREPOLARITY()
  • HAL UART update
    • Add new macros to control CTS and RTS
       -
    • Add specific macros -to manage the flags cleared only by a software sequence -
      • __HAL_UART_CLEAR_PEFLAG() -
      -
      • __HAL_UART_CLEAR_FEFLAG() -
      -
      • __HAL_UART_CLEAR_NEFLAG() -
      -
      • __HAL_UART_CLEAR_OREFLAG() -
      • __HAL_UART_CLEAR_IDLEFLAG() -
      -
    • Remove the check on -RXNE set after reading the Data in the DR register -

    • Add IS_UART_LIN_WORD_LENGTH() and IS_UART_LIN_OVERSAMPLING()  macros: to check respectively WordLength and OverSampling parameters in LIN mode

    • DMA -transmit process; the code has been updated to avoid waiting on TC flag -under DMA ISR, UART TC interrupt is used instead. Below the update to -be done on user application:

      • Configure and enable the USART IRQ in HAL_UART_MspInit() function
      • In stm32f2xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_UART_IRQHandler() function
    • IT transmit process; the code has been updated to avoid waiting on TC flag under UART ISR, UART TC interrupt is used instead. No impact on user application
    • Rename macros:
      • __HAL_UART_ONEBIT_ENABLE() by __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_UART_ONEBIT_DISABLE() by __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
    • Rename literals:
      • UART_WAKEUPMETHODE_IDLELINE by UART_WAKEUPMETHOD_IDLELINE
      • UART_WAKEUPMETHODE_ADDRESSMARK by UART_WAKEUPMETHOD_ADDRESSMARK
    • Add use of tmpreg variable in __HAL_UART_CLEAR_PEFLAG() macro for compliancy with C++
    • HAL_UART_Transmit_DMA() update to follow the right procedure "Transmission using DMA" in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
  • HAL USART update
    • Add specific macros -to manage the flags cleared only by a software sequence -
      • __HAL_USART_CLEAR_PEFLAG() -
      -
      • __HAL_USART_CLEAR_FEFLAG() -
      -
      • __HAL_USART_CLEAR_NEFLAG() -
      -
      • __HAL_USART_CLEAR_OREFLAG() -
      -
      • __HAL_USART_CLEAR_IDLEFLAG()
      -
    • Update -HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC

    • DMA -transmit process; the code has been updated to avoid waiting on TC flag -under DMA ISR, USART TC interrupt is used instead. Below the update to -be done on user application:

      • Configure and enable the USART IRQ in HAL_USART_MspInit() function
      • In stm32f2xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_USART_IRQHandler() function
    • IT transmit process; the code has been updated to avoid waiting on TC flag under USART ISR, USART TC interrupt is used instead. No impact on user application
    • HAL_USART_Init() update to enable the USART oversampling by 8 by default in order to reach max USART frequencies
    • USART_DMAReceiveCplt() update to set the new USART state after checking on the old state
    • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() update to follow the right procedure "Transmission using DMA"  in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
    • Rename macros:
      • __USART_ENABLE() by __HAL_USART_ENABLE()
      • __USART_DISABLE() by __HAL_USART_DISABLE()
      • __USART_ENABLE_IT() by __HAL_USART_ENABLE_IT()
      • __USART_DISABLE_IT() by __HAL_USART_DISABLE_IT()
    • Rename literals: remove "D" from "DISABLED" and "ENABLED"
      • USART_CLOCK_DISABLED by USART_CLOCK_DISABLE
      • USART_CLOCK_ENABLED by USART_CLOCK_ENABLE
      • USARTNACK_ENABLED by USART_NACK_ENABLE
      • USARTNACK_DISABLED by USART_NACK_DISABLE
    • Add new user macros to manage the sample method feature
      • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
    • Add use of tmpreg variable in __HAL_USART_CLEAR_PEFLAG() macro for compliancy with C++
    • HAL_USART_Init() fix USART baud rate configuration issue: USART baud rate is twice Higher than expected
  • HAL WWDG update
    • Update macro parameters to use underscore: __XXX__
    • Use of CMSIS constants instead of magic values
      -
    • Use MODIFY_REG macro in HAL_WWDG_Init()
    • Add IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() and HAL_WWDG_DeInit()
    • Add new parameter in __HAL_WWDG_ENABLE_IT() macro
    • Add new macros to manage WWDG IT & correction:
      • __HAL_WWDG_DISABLE()
      • __HAL_WWDG_DISABLE_IT()
      • __HAL_WWDG_GET_IT()
      • __HAL_WWDG_GET_IT_SOURCE()
  • HAL IWDG update
    • Use WRITE_REG instead of SET_BIT for all IWDG macros
    • __HAL_IWDG_CLEAR_FLAG removed: no IWDG flag cleared by access to SR register
    • Use MODIFY_REG macro in HAL_IWDG_Init()
    • Add IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()
    • Rename the defined IWDG keys: 
      • KR_KEY_RELOAD by IWDG_KEY_RELOAD
      • KR_KEY_ENABLE by IWDG_KEY_ENABLE
      • KR_KEY_EWA by IWDG_KEY_WRITE_ACCESS_ENABLE
      • KR_KEY_DWA by IWDG_KEY_WRITE_ACCESS_DISABLE
    •  Add new macro: __HAL_IWDG_RESET_HANDLE_STATE()
    • Update IWDG_ENABLE_WRITE_ACCESS() and IWDG_DISABLE_WRITE_ACCESS() as private macro
  • HAL LL FSMC update
    • Add WriteFifo and PageSize fields in the FSMC_NORSRAM_InitTypeDef structure
    • Update FSMC_NORSRAM_Init(), FSMC_NORSRAM_DeInit() and FSMC_NORSRAM_Extended_Timing_Init() functions
  • HAL LL USB update
    • Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation
    • USB_FlushTxFifo API: update to flush all Tx FIFO
    • Update to use local variable in USB Host channel re-activation

V1.0.1 / 25-March-2014

  • Patch release : moved macros related to RNG from hal_rcc_ex.h to hal_rcc.h as RNG is present in all versions of the STM32F2

V1.0.0 / 07-March-2014

Main Changes

  • First official release

License

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Redistribution and use in source and -binary forms, with or without modification, are permitted provided that the -following conditions are met:
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  2. Redistributions in binary form must -reproduce the above copyright notice, this list of conditions and the following -disclaimer in the -documentation and/or other materials provided with the distribution. -
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be used to -endorse or promote products derived
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For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

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- -
- - \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc.h index 9254a299d0..9fd6fe337c 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rtc.h @@ -45,6 +45,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f2xx_hal_def.h" +#include "stm32f2xx_ll_rtc.h" /** @addtogroup STM32F2xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/Release_Notes_stm32f3xx_hal.html b/targets/TARGET_STM/TARGET_STM32F3/device/Release_Notes_stm32f3xx_hal.html deleted file mode 100644 index f941bfc071..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F3/device/Release_Notes_stm32f3xx_hal.html +++ /dev/null @@ -1,1036 +0,0 @@ - - - - - - - - -Release Notes for STM32F3xx HAL Drivers - - - - - -
-

 

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Back to Release page

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Release -Notes for STM32F3xx HAL Drivers

-

Copyright -2014 STMicroelectronics

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-

Update History

-

V1.4.0 -/ 16-December-2016

Main changes -

  • Maintenance release to fix known defects and -enhancements implementation

HAL Drivers changes

  • - -Enhance HAL delay and time base implementation:
    • Add -new templates -stm32f0xx_hal_timebase_rtc_alarm_template.c, stm32f0xx_hal_timebase_rtc_wakeup_template.c -and stm32f0xx_hal_timebase_tim_template.c which can be used to override -the native -HAL time base functions (defined as weak) to use either RTC or -Timer as time -base tick source. For more details about the usage of these drivers, -please refer to HAL\HAL_TimeBase examples and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.3.0
    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove -HAL CEC receive interrupt process function HAL_CEC_Receive_IT() -and enable the "receive"  mode during the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • HAL TIM driver : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure

  • HAL Generic
    • Update HAL Driver compliancy with:
      • MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type)
  • HAL CEC
    • Overall driver rework with break of compatibility with HAL V1.3.0
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
      • Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC state information related to global Handle management and Tx Operations
      • Update CEC process to manage the new CEC states.
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
  • HAL UART/USART/IRDA/SMARTCARD
    • IRQ Handler global optimization 
    • New abort API: HAL_PPP_Abort(), HAL_PPP_Abort_IT()
    • Add error management in case of DMA transfer through - HAL_DMA_Abort_IT() and DMA XferAbortCallback()
    • Polling management update:
      • The user Timeout value must be estimated for the overall process -duration
  • HAL SPI
    • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency
      • Polling mode:
        • Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data
      •  Interrupt mode:
        • Minimize access on SPI registers
      • All modes:
        • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
        • Update timeout management to check on global processes
        • Update error code management in all processes
    • Fix regression in polling mode:
      • Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()
    • Fix regression in interrupt mode:
      • Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()
      • Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()
    • Prevent data packing mode -in reception for STM32F302xC, STM32F303xC, STM32F373xC, STM32F358xx, STM32F378xx
    • Add check of DMA handle definition before calling HAL_SPI_Receive_DMA, HAL_SPI_Transmit_DMA, HAL_SPI_TransmitReceive_DMA
    • Updated HAL Driver compliancy with MISRA C 2004 rules:
      • MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself).
      • MISRA C 2004 rule 14.8 (statement forming the body of a switch, while, do while or for statement shall be a compound statement).
  • HAL DMA
    • Global - driver code optimization to reduce memory footprint 
    • Add - new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to - register/unregister the different callbacks identified by the enum - typedef HAL_DMA_CallbackIDTypeDef
    • Add - new Error Code HAL_DMA_ERROR_NOT_SUPPORTED
    • Remove - DMA HAL_DMA_STATE_READY_HALF & HAL_DMA_STATE_ERROR states in - HAL_DMA_StateTypeDef
  • HAL I2C
    • Disable I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init()
    • Move I2C_NO_OPTION_FRAME in private section
    • Update IS_I2C_FASTMODEPLUS macro. Add I2C_FMP_NOT_SUPPORTED definition
    • Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)
    • Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer
    • On slave, reset LISTEN_TX state in case of direction change
    • Remove GCC warnings
  • HAL TIM
    • API update : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure in order to set ARPE -bit from TIMx_CR1 register
    • New -API : add 2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and  -__HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit -from TIMx_CCMR1, TIMx_CCMR2 and TIMx_CCMR3 registers
    • Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()
    • Add TIM1 ETR remap enums for STM32F334xx devices
    • HAL_TIMEx_RemapConfig() prototype changed for STM32F334x8 device
    • Remove -TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4 managment for STM32F373xC and STM32F378xx devices
    • API update : Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() function to disable MOE bit without condition
  • HAL SMBUS
    • Remove useless XferSize field initialisation in  HAL_SMBUS_Slave_Transmit_IT()
    • Add -support of Zone read/write feature thanks to new XferOptions parameter -values SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, -SMBUS_OTHER_AND_LAST_FRAME_NO_PEC and -SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC
  • HAL - PCD 
    • Updated HAL Driver compliancy with MISRA C 2004 rules : (10.3, 105)
      • MISRA C 2004 rule 10.3 (illegal explicit conversion from underlying MISRA type "unsigned int" to "uint32_t *").
      • MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).
      • MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).
  • HAL PWR
    • Rename PWR_CR register defines to be aligned with STM32F3xx Reference Manual : SDADCxEN ==> ENSDx
  • HAL RCC
    • Rename RCC_CFGR register defines to be aligned with STM32F3xx Reference Manual : SDADCPRE ==> SDPRE
  • HAL CORTEX
    • Update HAL_MPU_Disable() to clear the whole control register. Also remove STATIC INLINE and move function to c file
  • HAL CAN
    • Add __HAL_UNLOCK() call when all mailboxes are busy
    • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when timeout is reached
  • HAL ADC
    • Add ADC_EXTERNALTRIGINJECCONV_T2_CC1 and ADC_EXTERNALTRIGINJECCONV_T2_TRGO definitions
-

LL Drivers changes

  • LL COMP
    • Creation of generic defines for defines specific to COMP instances
    • Modify definition of LL_COMP_OUTPUT_TIM4_IC2_COMP4, LL_COMP_OUTPUT_TIM4_IC3_COMP5 and LL_COMP_OUTPUT_TIM4_IC4_COMP6 literals
    • Rename -LL_COMP_OUTPUT_TIM1_IC4_COMP2 and LL_COMP_OUTPUT_TIM1_IC4_COMP1_2 in -LL_COMP_OUTPUT_TIM2_IC4_COMP2 and LL_COMP_OUTPUT_TIM2_IC4_COMP1_2
    • Correct COMP inputs definition
  • LL EXTI
    • Move -LL_EXTI_LINE_18, LL_EXTI_LINE_33, LL_EXTI_LINE_34, LL_EXTI_LINE_35, -LL_EXTI_LINE_36, LL_EXTI_LINE_37, LL_EXTI_LINE_38 and LL_EXTI_LINE_39 -defines under compilation switch (availability depends on devices)
  • LL PWR
    • Rename PWR_CR register defines to be aligned with STM32F3xx Reference Manual : SDADCxEN ==> ENSDx
  • LL RCC
    • Rename RCC_CFGR register defines to be aligned with STM32F3xx Reference Manual : SDADCPRE ==> SDPRE
  • LL SYSTEM
    • Add LL_SYSCFG_EnableIT_FPU_xxx functions
    • Replace -LL_SYSCFG_TIM18_RMP_DMA2_CH4 and LL_SYSCFG_TIM18_RMP_DMA1_CH4 by -LL_SYSCFG_TIM18_RMP_DMA2_CH5 and LL_SYSCFG_TIM18_RMP_DMA1_CH5
  • LL GPIO
    • Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F3xx serie)
  • LL_TIM
    • Rename -LL_TIM_TIM16_TI1_RMP defines : LL_TIM_TIM16_TI1_RMP_GPIO, -LL_TIM_TIM16_TI1_RMP_RTC, LL_TIM_TIM16_TI1_RMP_HSE_32, -LL_TIM_TIM16_TI1_RMP_MCO
    • Remove -TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4 managment for STM32F373xC and STM32F378xx devices
    • Move -LL_TIM_OCREF_CLR_INT_OCREF_CLR and LL_TIM_OCREF_CLR_INT_ETR -defines under compilation switch (availability depends on devices)
    • New APIs to insure BDTR register initialization in a single write operation 
      • LL_TIM_BDTR_StructInit()
      • LL_TIM_BDTR_Init()
  • LL USART
    • Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions
  • LL HRTIM
    • Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions
    • Add shift operation in HRTIM_TIM_SetCompareMode()
  • LL_I2C
    • Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions

V1.3.0 -/ 12-Sept-2014

Main -Changes

- - - -
  • First official -release of STM32F3xx HAL drivers for STM32F303xE, -STM32F302xE and STM32F398xx -devices.
  • HAL generic update
    • Add support of new - devices STM32F302xE and STM32F398xx in STM32F3xx HAL drivers
  • HAL ADC
    • Empty weak function - return HAL_ERROR
    • Misra error - corrections
  • HAL CORTEX
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    • Macro IS_SYSTICK_CLKSOURCE - renamed IS_SYSTICK_CLK_SOURCE
  • HAL DAC
    • Empty weak function - return HAL_ERROR
  • HAL IWDG
    • Minor updates (HAL coding rules)
  • HAL PCD
    • Changed IN/OUT - EndPoint parameter array size (PCD Handle Structure)
  • HAL RCC
    • RCC_MCOSOURCE_PLLCLK_DIV1 - define added to RCC_MCO_Clock_Source defgroup for the following devices: STM32F302xE, - STM32F303xE, STM32F398xx, STM32F303x8, STM32F328xx, STM32F301x8, STM32F302x8 - and STM32F318xx
  • HAL SPI
    • Removed HAL_ - prefix from static function names
  • HAL TIM
    • Checked - DeadTime value in debug mode
    • Add new macros __HAL_TIM_URS_ENABLE() and __HAL_TIM_URS_DISABLE()
  • HAL WWDG
    • Minor updates (HAL coding - rules)
    • Added macro __HAL_WWDG_CLEAR_IT()
    • Use MODIFY_REG() macro to set Prescaler, Window and Counter registers within  HAL_WWDG_Init() 
- - - - - - - - - -

V1.1.0RC2 -/ 25-August-2014

Main -Changes

- - - - - - - - -
  • HAL generic update
    • General improvement of - Doxygen Tags for CHM UM generation
    • Add support of new - devices STM32F303xE in STM32F3xx HAL driver
  • HAL update (for STM32F303xE)
    • Add new defines for ADC - trigger remapping (HAL_REMAPADCTRIGGER_x)
    • Add new defines for CCM - RAM page write protection (up to 16 pages can be write protected)
    • Add new macro IS_HAL_REMAPADCTRIGGER()
    • Updated macro IS_HAL_SYSCFG_WP_PAGE - ()
    • Add new macros to - freeze/unfreeze TIM20 in debug mode: __HAL_FREEZE_TIM20_DBGMCU() and __HAL_UNFREEZE_TIM20_DBGMCU()
    • Add new macro to remap - the FMC banks 1 and 2 at 0x00000000 : __HAL_FMC_BANK()
    • Add new macros to - enable/disable ADC trigger remapping: __HAL_REMAPADCTRIGGER_ENABLE() and __HAL_REMAPADCTRIGGER_DISABLE()
  • HAL ADC update (for STM32F303xE)
    • Add new defines for TIM20 - related ADC external triggers for regular groups (ADC_EXTERNALTRIGCONV_T20_x)
    • Add new defines for TIM20 - related ADC external triggers for injected groups (ADC_EXTERNALTRIGINJECCONV_T20_x)
    • Updated macro __HAL_ADC_CFGR_EXTSEL() to take into account TIM20 related ADC - triggers for regular channels
    • Updated macro __HAL_ADC_JSQR_JEXTSEL() to take into account TIM20 related ADC - triggers for injected channels
  • HAL COMP update
    • Defect correction:
      • Missing assert param IS_COMP_TRIGGERMODE
    • STM32F303xE:
      • Add new defines for comparator output redirection: COMP_OUTPUT_TIM20BKIN, - COMP_OUTPUT_TIM20BKIN2, COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 and COMP_OUTPUT_TIM20OCREFCLR
  • HAL FLASH update (for STM32F303xE)
- - - - - - -
    • Add -new defines for write protection of pages 32 to 61 and 62-263 (OB_WRP_PAGESxxTOyy)
- -
  • HAL GPIO update (for STM32F303xE)
- -
    • Add -new defines for TIM20 and FMC related AF: GPIO_AF2_TIM20, GPIO_AF3_TIM20, GPIO_AF6_TIM20 and -GPIO_AF12_FMC
- -
  • HAL IRDA update
- -
    • TC enabled and TXE disabled at the end of TX in IT -mode
- -
  • HAL HAL NAND (STM32F303xE specific)
- -
    • FMC: generic -firmware to drive NAND memories mounted as external device
- -
  • HAL NOR (STM32F303xE specific)
- -
    • FMC: generic -firmware to drive NOR memories mounted as external device
- -
  • HAL PCCARD (STM32F303xE specific)
- -
    • FMC: generic -firmware to drive PCCARD memories mounted as external device
- -
  • HAL PCD update 
- -
    • Add -new macros __HAL_USB_EXTI_GET_FLAG() , __HAL_USB_EXTI_CLEAR_FLAG(), __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER(), -__HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER() and _HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER()
- -
  • HAL PWR update 
- -
    • PVD feature need falling/rising Event modes
      • Rename  defines: 
        • PWR_MODE_EVT to PWR_PVD_MODE_NORMAL
        • PWR_MODE_IT_RISING to PWR_PVD_MODE_IT_RISING
        • PWR_MODE_IT_FALLING to PWR_PVD_MODE_IT_FALLING
        • PWR_MODE_IT_RISING_FALLING to PWR_PVD_MODE_IT_RISING_FALLING
        • PWR_MODE_IT_RISING to PWR_PVD_MODE_IT_RISING
      • Add new - defines: PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING and - PWR_PVD_MODE_EVENT_RISING_FALLING
      • Changed - __HAL_PVD_EXTI_ENABLE_IT() macro  - definition: __EXTILINE__ argument no longer needed - (PWR_EXTI_LINE_PVD is used implicitly)
      • Changed - __HAL_PVD_EXTI_DISABLE_IT() macro definition: __EXTILINE__ argument no - longer needed (PWR_EXTI_LINE_PVD is used implicitly)
      • Changed - __HAL_PVD_EXTI_GET_FLAG () macro definition: __EXTILINE__ argument no - longer needed (PWR_EXTI_LINE_PVD is used implicitly)
      • Changed - _HAL_PVD_EXTI_CLEAR_FLAG () macro definition: __EXTILINE__ argument no - longer needed (PWR_EXTI_LINE_PVD is used implicitly)
      • Add -new macros __HAL_PWR_PVD_EXTI_ENABLE_EVENT(), -__HAL_PWR_PVD_EXTI_DISABLE_EVENT(),  -__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(), -__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() and -__HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER()
- - - - - -
  • HAL RCC update (for STM32F303xE)
    • RCC_OcsInitTypeDef and RCC_PLLInitTypeDef definitions are now product dependent: 
      • STM32F303xE:
        • Added PREDIV field to RCC_PLLInitTypeDef: used to set the - desired pre-division factor whatever the PLL clock source is (HSI or HSE).
        • Removed field HSEPredivValue from RCC_OscInitTypeDef (replaced by PREDIV field in RCC_PLLInitTypeDef)
      • Other F3 products: no change in RCC_OcsInitTypeDef and RCC_PLLInitTypeDef definitions
    • Add new definition of RCC_PeriphCLKInitTypeDef  to fit STM32F303xE  clock selection capabilities (e.g select TIM20 - clock source)
    • Add new defines to select the pre-division factor (RCC_PREDIV_DIVx)
    • Add new defines to set TIM20 clock source (RCC_PERIPHCLK_TIM20, RCC_TIM20CLK_HCLK and - RCC_TIM20CLK_PLLCLK)
    • Add new defnes to set TIM3 & TIM4 clock source  (RCC_PERIPHCLK_TIM34, RCC_TIM34CLK_HCLK, RCC_TIM34CLK_PCLK)
    • Add FMC related macros: __FMC_CLK_ENABLE(), __FMC_CLK_DISABLE(), __FMC_FORCE_RESET() and __FMC_RELEASE_RESET()
    • Add GPIO port G related macros: __GPIOG_CLK_ENABLE(), __GPIOG_CLK_DISABLE(), - __ GPIOG _FORCE_RESET() and __GPIOG _RELEASE_RESET()
    • Add GPIO port H related macros:_ __GPIOH_CLK_ENABLE(), __GPIOH_CLK_DISABLE(), - __FMC_ GPIOH _RESET() and __GPIOH _RELEASE_RESET()
    • Add SPI4 related macros:  __SPI4_CLK_ENABLE(), - __SPI4_CLK_DISABLE(), __ SPI4_FORCE_RESET() and __SPI4_RELEASE_RESET()
    • Add TIM20 related macros: __TIM20_CLK_ENABLE(), __TIM20_CLK_DISABLE(), -__ TIM20_FORCE_RESET() and __TIM20_RELEASE_RESET(), __HAL_RCC_TIM20_CONFIG() , __HAL_RCC_GET_TIM20_SOURCE()
    • Add new macro to set/get the clock source of TIM3 & TIM4: __HAL_RCC_TIM34_CONFIG() and  __HAL_RCC_GET_TIM34_SOURCE()
  • HAL SMARTCARD -update
    • Change SMARTCARD_AdvFeatureConfig() -from exported to static private function
    • TC enabled and TXE disabled at the end of TX in IT -mode
- - - -

- -
  • HAL SMBUS update
    • Fix wrong State after a PEC failed
    • Fix slave acknowledge issue

- -
  • HAL SPI update
    • Fix CodeSonar warning: unreachable Call in -SPI_CloseRxTx_ISR()

- -
  • HAL SRAM (STM32F303xE specific)
    • FMC: generic -firmware to drive SRAM memories mounted as external device
- - - -
  • HAL TIM update (for STM32F303xE)
    • Add -defines to set TIM20 option register (link from analog watchdog and TIM20 ETR)
  • HAL UART update
    • TC enabled and TXE disabled at the end of TX in IT -mode
  • HAL USART update
    • TC enabled and TXE disabled at the end of TX in IT -mode

V1.0.1 -/ 18-June-2014

Main -Changes

-
  • - - - - - - - -

    HAL generic update

    • Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="
    • Fix -on Timeout management, Timeout value set to 0 passed to API -automatically exits the function after checking the flag without any -wait.
    • Add -new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.
  • - - - - - - - -

    HAL ADC update

    • Rename defines:
      • ADC_EXTERNALTRIGCONV_Ext_IT11 to ADC_EXTERNALTRIGCONV_EXT_IT11
      • ADC_EXTERNALTRIGCONV_Ext_IT12 to ADC_EXTERNALTRIGCONV_EXT_IT12
    • Fix define ADC_SOFTWARE_START
    • Update external trigger defines to remove HRTIM triggers for STM32F328xx and TIM8 triggers for STM32F302xC
    • Add ADC1_2_EXTERNALTRIG_T4_CC4 for STM32F303x8 and STM32F328xx

  • HAL CEC update

    • Process no more locked during the transmission in interrupt mode. 

  • HAL COMP update

    • Fix on 32-bit register COMP CSR accesses for STM32F373xC and STM32F378xx devices.
    • Add new defines for STM32F373xC and STM32F378xx comparators: 
COMP_OUTPUT_TIM3IC1, -COMP_OUTPUT_TIM3OCREFCLR, COMP_OUTPUT_TIM2IC4 and -COMP_OUTPUT_TIM2OCREFCLR 
instead of previous defines 
COMP_OUTPUT_COMP1_TIM3IC1, -COMP_OUTPUT_COMP1_TIM3OCREFCLR, COMP_OUTPUT_COMP1_TIM2IC4,  -COMP_OUTPUT_COMP1_TIM2OCREFCLR,
COMP_OUTPUT_COMP2_TIM3IC1, COMP_OUTPUT_COMP2_TIM3OCREFCLR, COMP_OUTPUT_COMP2_TIM2IC4,  COMP_OUTPUT_COMP2_TIM2OCREFCLR.

  • HAL DMA update

    • Fix in HAL_DMA_PollForTransfer() to set error code HAL_DMA_ERROR_TE in case of HAL_ERROR status 

  • HAL GPIO update

    • Fix GPIO_AF5_SPI1 define instead of GPIO_AF5_SPI1 for STM32F303x8 device. 
  • - - - - - - - -

    HAL HRTIM update

    • HRTIM peripheral not available for STM32F328xx device.
    • Fix macros __HAL_HRTIM_CLEAR_FLAG, __HAL_HRTIM_MASTER_CLEAR_FLAG and __HAL_HRTIM_TIMER_CLEAR_FLAG
  • - - - - - - - -

    HAL I2C update

    • Add -management of NACK event in Master transmitter mode and Slave -transmitter/receiver modes (only in polling mode), in that case the -current transfer is stopped.

  • HAL IRDA update

    • Add new enum typedef IRDA_ClockSourceTypeDef
    • Add new macro __HAL_IRDA_GETCLOCKSOURCE
    • Change in HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • - - - - - - - -

    HAL OPAMP update

    • __SYSCFG_CLK_ENABLE() is now handled internally in HAL_OPAMP_Init() and no more in user HAL_OPAMP_MspInit().
  • -

    HAL PCD update

    -
    • -

      Add new macro __HAL_USB_EXTI_GENERATE_SWIT

      -

  • HAL PWR update

    • Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function

  • HAL RCC update

    • Change for STM32F303x8, STM32F334x8 and STM32F328xx devices:
      • Add missing macro __DAC2_FORCE_RESET
      • Rename RCC_USART1CLKSOURCE_PCLK2 into RCC_USART1CLKSOURCE_PCLK1
    • Remove HRTIM1 peripheral and clocking macros for STM32F328xx device.
    • Fix HSI Calibration issue when selected as SYSCLK
  • - - - - - - - -

    HAL SMARTCARD update

    • Change in HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.
    • Process no more locked during the transmission in interrupt mode.

  • HAL SMBUS update

    • Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack

  • HAL TIM update

    • Fix macro __HAL_TIM_PRESCALER

  • HAL TSC update

    • Fix define TSC_ACQ_MODE_SYNCHRO
  • - - - - - - - -

    HAL UART update

    • Change in HAL_LIN_Init() parameter BreakDetectLength to uint32_t
    • Change in HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
  • - - - - - - - -

    HAL USART update

    • Change USART_InitTypeDef fields to uint32_t type
    • Rename __USART_ENABLE and __USART_DISABLE macros to respectively __HAL_USART_ENABLE and __HAL_USART_DISABLE
    • Change in HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC.
    • Process no more locked during the transmission in interrupt mode.
    • Change in HAL_USART_TransmitReceive_DMA() to manage DMA half transfer mode
 

V1.0.0 -/ 06-May-2014

-

Main -Changes

-
  • First official -release of STM32F3xx HAL drivers for STM32F301x6/x8, -STM32F302x6/x8, STM32F302xB/xC, -STM32F303x6/x8, STM32F373xB/xC, -STM32F334x4/x6/x8, STM32F318xx, STM32F328xx, STM32F358xx and STM32F378xx -devices.

License

-Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
    -     -
-        from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -
-
-
-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.h index c909e94c39..a256fb7337 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.h @@ -43,6 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" +#include "stm32f3xx_ll_rtc.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c index 60b2bb5ce8..05468ac47e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c @@ -352,30 +352,19 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 - {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 - {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS - {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 - {PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 {PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 {NC, NC, 0} }; @@ -388,7 +377,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h index df39a64b23..9bdac54021 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h @@ -307,14 +307,6 @@ typedef enum { SYS_WKUP2 = PC_0, SYS_WKUP3 = PC_1, - /**** QSPI pins ****/ - QSPI1_IO0 = PD_11, - QSPI1_IO1 = PD_12, - QSPI1_IO2 = PE_2, - QSPI1_IO3 = PD_13, - QSPI1_SCK = PB_2, - QSPI1_CSN = PB_6, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c index 4cb8f81aff..8efdba5ad0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c @@ -404,30 +404,19 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_A1 - {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to SD_CMD - {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to DFSDM2_DATIN1 {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to ARD_D4 - {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to ARD_A5 - {PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to LED2_GREEN {PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to SD_D0 {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to SD_D1 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to SD_D2 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to SD_D3 {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to PSRAM_A16 [IS66WV51216EBLL_A16] {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to PSRAM_A17 [IS66WV51216EBLL_A17] {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3] {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2] - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to LCD_PSRAM_D4 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to LCD_PSRAM_D5 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to LCD_PSRAM_D6 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to LCD_PSRAM_D7 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D0 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D1 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0] {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1] {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S] -// {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 // Connected to STDIO_UART_RX -// {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 // Connected to STDIO_UART_TX {NC, NC, 0} }; @@ -440,7 +429,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to ARD_D4 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to SD_D3 {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c index c36385da88..385186b4df 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c @@ -404,30 +404,19 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 - {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 - {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS - {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 - {PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 {PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 {NC, NC, 0} }; @@ -440,7 +429,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h index 98e511481d..1fba180f55 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h @@ -306,14 +306,6 @@ typedef enum { SYS_WKUP2 = PC_0, SYS_WKUP3 = PC_1, - /**** QSPI pins ****/ - QSPI1_IO0 = PD_11, - QSPI1_IO1 = PD_12, - QSPI1_IO2 = PE_2, - QSPI1_IO3 = PD_13, - QSPI1_SCK = PB_2, - QSPI1_CSN = PB_6, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c index 02edcc0e60..88481e47e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c @@ -30,7 +30,7 @@ **/ #include "stm32f4xx.h" - +#include "nvic_addr.h" #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config @@ -56,6 +56,10 @@ uint8_t SetSysClock_PLL_HSI(void); */ void SystemInit(void) { + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; @@ -79,6 +83,13 @@ void SystemInit(void) SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + } /** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c index 02edcc0e60..88481e47e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c @@ -30,7 +30,7 @@ **/ #include "stm32f4xx.h" - +#include "nvic_addr.h" #include "mbed_error.h" // clock source is selected with CLOCK_SOURCE in json config @@ -56,6 +56,10 @@ uint8_t SetSysClock_PLL_HSI(void); */ void SystemInit(void) { + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; @@ -79,6 +83,13 @@ void SystemInit(void) SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + } /** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S index 9362d09722..6e6104b04a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S @@ -168,15 +168,9 @@ __Vectors_Size EQU __Vectors_End - __Vectors ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] - IMPORT SystemInitPre - IMPORT HAL_InitPre IMPORT SystemInit IMPORT __main - LDR R0, =SystemInitPre - BLX R0 - LDR R0, =HAL_InitPre - BLX R0 LDR R0, =SystemInit BLX R0 LDR R0, =__main diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct index 7dedde2cae..c40a1b035a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct @@ -45,7 +45,7 @@ #define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) #define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) -; 2 MB FLASH (0x200000) + 192 KB SRAM (0x30000) +; 2 MB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address @@ -61,6 +61,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE) { ; RW data .ANY (+RW +ZI) } - + + RW_IRAM2 (0x10000000) (0x10000) { ; RW data + .ANY (+RW +ZI) + } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld index e22e74708d..b3bb639dd7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld @@ -1,11 +1,3 @@ -M_VECTOR_RAM_SIZE = 0x400; - -/* With the RTOS in use, this does not affect the main stack size. The size of - * the stack where main runs is determined via the RTOS. */ -STACK_SIZE = 0x400; - -HEAP_SIZE = 0x6000; - #if !defined(MBED_APP_START) #define MBED_APP_START 0x08000000 #endif @@ -16,13 +8,13 @@ HEAP_SIZE = 0x6000; M_CRASH_DATA_RAM_SIZE = 0x100; -/* Specify the memory areas */ +/* Linker script to configure memory regions. */ +/* 0x1AC resevered for vectors; 8-byte aligned = 0x1B0 (0x1AC + 0x4)*/ MEMORY -{ - VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x400 - FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 - CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192k +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + RAM (rwx) : ORIGIN = 0x200001B0, LENGTH = 192k - (0x1AC+0x4) } /* Linker script to place sections and symbol values. Should be used together @@ -56,18 +48,10 @@ ENTRY(Reset_Handler) SECTIONS { - .isr_vector : - { - __vector_table = .; - KEEP(*(.isr_vector)) - . = ALIGN(8); - } > VECTORS - .text : { - + KEEP(*(.isr_vector)) *(.text*) - KEEP(*(.init)) KEEP(*(.fini)) @@ -96,7 +80,6 @@ SECTIONS } > FLASH __exidx_start = .; - .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) @@ -105,17 +88,6 @@ SECTIONS __etext = .; _sidata = .; - - .interrupts_ram : - { - . = ALIGN(8); - __VECTOR_RAM__ = .; - __interrupts_ram_start__ = .; /* Create a global symbol at data start */ - *(.m_interrupts_ram) /* This is a user defined section */ - . += M_VECTOR_RAM_SIZE; - . = ALIGN(8); - __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > RAM .crash_data_ram : { @@ -127,12 +99,10 @@ SECTIONS . += M_CRASH_DATA_RAM_SIZE; . = ALIGN(8); __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > RAM + } > RAM - .data : + .data : AT (__etext) { - PROVIDE( __etext = LOADADDR(.data) ); - __data_start__ = .; _sdata = .; *(vtable) @@ -165,23 +135,9 @@ SECTIONS __data_end__ = .; _edata = .; - } > RAM AT > FLASH - - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; } > RAM - .bss (NOLOAD): + .bss : { . = ALIGN(8); __bss_start__ = .; @@ -193,18 +149,29 @@ SECTIONS _ebss = .; } > RAM - .heap (NOLOAD): + .heap (COPY): { __end__ = .; end = __end__; - . += HEAP_SIZE; + *(.heap*) __HeapLimit = .; } > RAM + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __stack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; - - ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap") + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S index f0b0be02d4..d43725c822 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S @@ -74,10 +74,10 @@ defined in linker script */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function -Reset_Handler: - ldr sp, =__stack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit @@ -106,8 +106,6 @@ LoopFillZerobss: bcc FillZerobss /* Call the clock system intitialization function.*/ - bl SystemInitPre - bl HAL_InitPre bl SystemInit /* Call static constructors */ //bl __libc_init_array @@ -142,10 +140,10 @@ Infinite_Loop: *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word __stack + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack .word Reset_Handler .word NMI_Handler @@ -212,7 +210,7 @@ g_pfnVectors: .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ + .word FMC_IRQHandler /* FMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ @@ -252,8 +250,8 @@ g_pfnVectors: .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC_IRQHandler */ - .word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S index 85bc4368bc..339ddc9656 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S @@ -61,8 +61,6 @@ SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start - EXTERN SystemInitPre - EXTERN HAL_InitPre EXTERN SystemInit PUBLIC __vector_table @@ -188,10 +186,6 @@ __vector_table SECTION .text:CODE:REORDER:NOROOT(2) Reset_Handler - LDR R0, =SystemInitPre - BLX R0 - LDR R0, =HAL_InitPre - BLX R0 LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start @@ -648,13 +642,13 @@ FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) + SECTION .text:CODE:REORDER:NOROOT(1) UART7_IRQHandler B UART7_IRQHandler PUBWEAK UART8_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -UART8_IRQHandler +UART8_IRQHandler B UART8_IRQHandler PUBWEAK SPI4_IRQHandler @@ -664,7 +658,7 @@ SPI4_IRQHandler PUBWEAK SPI5_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -SPI5_IRQHandler +SPI5_IRQHandler B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf index 3dc9c9aca3..f62d3892c6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf @@ -17,16 +17,16 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; /*-Sizes-*/ -/*Heap 64K and stack 4K */ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_heap__ = 0x10000; +/*Heap 89kB and stack 1kB */ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x15C00; /**** End of ICF editor section. ###ICF###*/ define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; /* Define Crash Data Symbols */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c index 0e981e7764..0c2110186c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c @@ -49,6 +49,9 @@ const PinMap PinMap_ADC[] = { }; const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h index 2f9f84c09c..3e7b07f08d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h @@ -130,13 +130,22 @@ typedef enum { D13 = PE_2, // SCK D14 = PB_7, // SDA D15 = PB_6, // SCL + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + // Internal LED1 = PE_3, // Red / Mode LED2 = PE_4, // Green / Switch-1 LED3 = PE_1, // Blue LED4 = PE_7, // A definition is required by the mbed platform RTC test code, this is the Ethernet connector yellow LED LED_RED = LED1, + LED_GREEN = LED2, + LED_BLUE = LED3, SW0 = PC_13, // Switch-0 + BUTTON1 = SW0, // Standardized button names // Arduino header I2C I2C_SDA = D14, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h index c61f4dd431..40df4a1e51 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h @@ -88,20 +88,20 @@ typedef enum { P_A2 = NC, P_A3 = NC, P_A4 = NC, - P_A5 = PC_2, // UART-DTR - P_A6 = PF_2, // Switch-0 - P_A7 = PE_0, // Red, Mode - P_A8 = PB_6, // Green, Switch-1 - P_A9 = PB_8, // Blue - P_A10 = PA_11, // UART-CTS - P_A11 = PA_9, // UART-TXD - P_A12 = PA_12, // UART-RTS - P_A13 = PA_10, // UART-RXD - P_A14 = PD_9, // GPIO-0 - P_A15 = PD_8, // GPIO-1 - P_A16 = PD_11, // GPIO-2 - P_A17 = PD_12, // GPIO-3 - P_A18 = PA_3, // UART-DSR + P_A5 = PC_2, + P_A6 = PF_2, + P_A7 = PE_0, + P_A8 = PB_6, + P_A9 = PB_8, + P_A10 = PA_11, + P_A11 = PA_9, + P_A12 = PA_12, + P_A13 = PA_10, + P_A14 = PD_9, + P_A15 = PD_8, + P_A16 = PD_11, + P_A17 = PD_12, + P_A18 = PA_3, // PortB P_B1 = NC, P_B2 = NC, @@ -116,38 +116,38 @@ typedef enum { P_C2 = NC, P_C3 = NC, P_C4 = NC, - P_C5 = PG_4, // SPI-IRQ - P_C6 = PE_13, // SPI-MISO + P_C5 = PG_4, + P_C6 = PE_13, P_C7 = NC, - P_C8 = PE_12, // Res + P_C8 = PE_12, P_C9 = NC, - P_C10 = PE_14, // SPI-MOSI - P_C11 = PE_11, // SPI-CS0 - P_C12 = PE_9, // Res - P_C13 = PF_6, // GPIO-4 - P_C14 = PC_1, // RMII-MDC - P_C15 = PA_2, // RMII-MDIO - P_C16 = PF_7, // GPIO-7 - P_C17 = PF_1, // I2C-SCL - P_C18 = PF_0, // I2C-SDA + P_C10 = PE_14, + P_C11 = PE_11, + P_C12 = PE_9, + P_C13 = PF_6, + P_C14 = PC_1, + P_C15 = PA_2, + P_C16 = PF_7, + P_C17 = PF_1, + P_C18 = PF_0, // PortD - P_D1 = PB_12, // RMII-TXD0 - P_D2 = PB_13, // RMII-TXD1 - P_D3 = PB_11, // RMII-TXEN - P_D4 = PA_7, // RMII-CRSDV - P_D5 = PC_4, // RMII-RXD0 - P_D6 = PC_5, // RMII-RXD1 + P_D1 = PB_12, + P_D2 = PB_13, + P_D3 = PB_11, + P_D4 = PA_7, + P_D5 = PC_4, + P_D6 = PC_5, P_D7 = NC, - P_D8 = PA_1, // RMII-REFCLK + P_D8 = PA_1, // TestPads - P_TP5 = PB_4, // NTRST - P_TP7 = PA_13, // TMS SWDIO - P_TP8 = PA_15, // TDI - P_TP9 = PA_14, // TCK SWCLK - P_TP10 = PB_3, // TDO + P_TP5 = PB_4, + P_TP7 = PA_13, + P_TP8 = PA_15, + P_TP9 = PA_14, + P_TP10 = PB_3, //P_TP11, // BOOT0 - // Internal + // Mbed pins LED_RED = PE_0, LED_GREEN = PB_6, LED_BLUE = PB_8, @@ -157,11 +157,9 @@ typedef enum { LED3 = LED_BLUE, SW1 = PF_2, - SW2 = PG_4, // Standardized button names BUTTON1 = SW1, - BUTTON2 = SW2, I2C_SDA = PF_0, I2C_SCL = PF_1, @@ -169,8 +167,9 @@ typedef enum { SPI0_MOSI = PE_14, SPI0_MISO = PE_13, SPI0_SCK = PE_12, - SPI0_CS = PE_11, - SPI1_CS = PE_9, + SPI0_CS = PE_11, //CS for SPI Flash on MCB + SPI1_CS = PE_9, //CS for LCD on MTB + SPI2_CS = PG_4, //CS for SD card on MTB SPI_MOSI = SPI0_MOSI, SPI_MISO = SPI0_MISO, @@ -216,7 +215,7 @@ typedef enum { MISO1 = P_C6, SCK1 = SPI_SCK, GP0 = BUTTON1, - GP1 = SPI_CS, + GP1 = P_C11, AIN0 = P_C13, AIN1 = P_A18, AIN2 = P_A5, @@ -226,9 +225,9 @@ typedef enum { GP10 = NC, RTS = NC, CTS = NC, - GP7 = P_C12, - GP6 = P_A12, - GP5 = P_A10, + GP7 = P_C12, //LCD CS on MTB + GP6 = P_A12, //LCD Reset on MTB + GP5 = P_A10, //LCD A0 on MTB GP4 = P_A17, TX2 = NC, RX2 = NC, @@ -238,7 +237,7 @@ typedef enum { MISO2 = NC, SCK2 = NC, GP3 = P_A16, - GP2 = P_C5, + GP2 = P_C5, //CS for SD Card on MTB PWM2 = LED_GREEN, PWM1 = LED_BLUE, PWM0 = LED_RED, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h index 0b6a7f8103..ad1011aebe 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h @@ -259,7 +259,7 @@ typedef enum { LED2 = PB_7, // Blue LED3 = PB_14, // Red LED4 = PB_0, - LED_RED = LED2, + LED_RED = LED3, USER_BUTTON = PC_13, // Standardized button names BUTTON1 = USER_BUTTON, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c index bbc9a292ed..88481e47e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c @@ -17,20 +17,15 @@ /** * This file configures the system clock as follows: *----------------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (CLOCK_SOURCE_USB=1) | 3- USE_PLL_HSI (CLOCK_SOURCE_USB=1) - * | (external 8 MHz clock) | (internal 16 MHz clock) - * | 2- USE_PLL_HSE_XTAL | - * | (external 8 MHz xtal) | + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1 + * | 3- USE_PLL_HSI (internal 16 MHz clock) | *----------------------------------------------------------------------------------- - * SYSCLK(MHz) | 180 (168) - *----------------------------------------------------------------------------------- - * AHBCLK (MHz) | 180 (168) - *----------------------------------------------------------------------------------- - * APB1CLK (MHz) | 45 (42) - *----------------------------------------------------------------------------------- - * APB2CLK (MHz) | 90 (84) - *----------------------------------------------------------------------------------- - * USB capable (48 MHz) | YES (HSI calibration needed) + * SYSCLK(MHz) | 180 | 168 + * AHBCLK (MHz) | 180 | 168 + * APB1CLK (MHz) | 45 | 42 + * APB2CLK (MHz) | 90 | 84 + * USB capable (48 MHz) | NO | YES (HSI calibration needed) *----------------------------------------------------------------------------------- **/ @@ -40,7 +35,7 @@ // clock source is selected with CLOCK_SOURCE in json config #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) #define USE_PLL_HSI 0x2 // Use HSI internal clock #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) @@ -51,6 +46,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass); uint8_t SetSysClock_PLL_HSI(void); #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + /** * @brief Setup the microcontroller system * Initialize the FPU setting, vector table location and External memory diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct index 0ca3edf060..c40a1b035a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/stm32f439xx.sct @@ -57,7 +57,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data } - ; Total: 107 vectors = 428 bytes(0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM + ; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE) { ; RW data .ANY (+RW +ZI) } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld index fb42b7b72e..b3bb639dd7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld @@ -21,7 +21,7 @@ MEMORY * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S index e773cef9e9..78d2e6e189 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S @@ -254,8 +254,6 @@ Infinite_Loop: .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ - - /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. @@ -567,7 +565,3 @@ Infinite_Loop: - - - - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h index 2248d9f774..daa6e974b9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/flash_data.h @@ -38,7 +38,7 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ -/* Flash Size */ +/* FLASH SIZE */ #define FLASH_SIZE (uint32_t) 0x200000 /* Base address of the Flash sectors Bank 1 */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c index bfb40065cf..39ff3d170e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c @@ -317,7 +317,6 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {NC, NC, 0} }; @@ -328,6 +327,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c index 91dee64454..c75466ab2d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PeripheralPins.c @@ -388,22 +388,15 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 {NC, NC, 0} }; @@ -415,7 +408,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h index cecd65dc63..eb1d885320 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h @@ -325,14 +325,6 @@ typedef enum { SYS_WKUP0 = PA_0, SYS_WKUP1 = PC_13, - /**** QSPI pins ****/ - QSPI1_IO0 = PD_11, - QSPI1_IO1 = PD_12, - QSPI1_IO2 = PE_2, - QSPI1_IO3 = PD_13, - QSPI1_SCK = PB_2, - QSPI1_CSN = PB_6, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c index 8d2e24426d..2196ceb671 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c @@ -397,23 +397,14 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { // {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to uSD_D1 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to uSD_D2 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3 {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to MIC_CK [MP34DT01TR_CLK] {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to AUDIO_RST [CS43L22_RESET] - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to D4 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to D5 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to D6 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to D7 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3] {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2] {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0] {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1] - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 // Connected to USART6_RX - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 // Connected to ARDUINO USART6_TX - {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO0 // Connected to SDCKE0 [MT48LC4M32B2B5-6A_CKE] - {PH_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO1 // Connected to SDNE0 [MT48LC4M32B2B5-6A_CS] {NC, NC, 0} }; @@ -426,6 +417,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S] // {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3 {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c index 534c6852d6..bf966f9a2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c @@ -186,10 +186,7 @@ HAL_StatusTypeDef HAL_Init(void) #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ -/* MBED : moved to HAL_InitPre() */ -#if !defined (TARGET_STM32F429xI) HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); -#endif /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h index 8744804d6b..2a7282a3ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h @@ -43,6 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" +#include "stm32f4xx_ll_rtc.h" /** @addtogroup STM32F4xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c b/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c deleted file mode 100644 index 59380cfa96..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2015-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "stm32f4xx_hal.h" - -HAL_StatusTypeDef HAL_InitPre(void); - -HAL_StatusTypeDef HAL_InitPre(void) -{ - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Return function status */ - return HAL_OK; -} diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c index 9781b7dd46..86c1cbc5f3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c @@ -414,23 +414,14 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_NCS [N25Q128A13EF840E_S] {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SDMMC1_D1 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to SDMMC_D2 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to SDMMC_D3 {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0] {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_D1 [N25Q128A13EF840E_DQ1] {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_D3 [N25Q128A13EF840E_DQ3] {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2] - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to FMC_D4 [MT48LC4M32B2B5-6A_DQ4] - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_D5 [MT48LC4M32B2B5-6A_DQ5] - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to FMC_D6 [MT48LC4M32B2B5-6A_DQ6] - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to FMC_D7 [MT48LC4M32B2B5-6A_DQ7] {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ARDUINO A5 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ARDUINO A4 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to ARDUINO A3 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to ARDUINO A2 - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to DCMI_VSYNC - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to NC2 - {PH_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_SDNE0 [MT48LC4M32B2B5-6A_CS] {NC, NC, 0} }; @@ -441,6 +432,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_NCS [N25Q128A13EF840E_S] - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to SDMMC_D3 {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c index 3d8218d176..20188135fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c @@ -386,21 +386,14 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 {NC, NC, 0} }; @@ -411,6 +404,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h index cb79aa44c7..74f94f7894 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h @@ -354,14 +354,6 @@ typedef enum { SYS_WKUP3 = PC_1, SYS_WKUP4 = PC_13, - /**** QSPI pins ****/ - QSPI_FLASH1_IO0 = PD_11, - QSPI_FLASH1_IO1 = PD_12, - QSPI_FLASH1_IO2 = PE_2, - QSPI_FLASH1_IO3 = PD_13, - QSPI_FLASH1_SCK = PB_2, - QSPI_FLASH1_CSN = PB_6, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c index 3d8218d176..20188135fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c @@ -386,21 +386,14 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 {NC, NC, 0} }; @@ -411,6 +404,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h index eb4d1e37c8..74f94f7894 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h @@ -354,14 +354,6 @@ typedef enum { SYS_WKUP3 = PC_1, SYS_WKUP4 = PC_13, - /**** QSPI pins ****/ - QSPI1_IO0 = PD_11, - QSPI1_IO1 = PD_12, - QSPI1_IO2 = PE_2, - QSPI1_IO3 = PD_13, - QSPI1_SCK = PB_2, - QSPI1_CSN = PB_6, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c index c11e39acbd..88c88a4b1b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c @@ -427,21 +427,14 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 {NC, NC, 0} }; @@ -454,6 +447,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h index 46225b1c03..89e4a8596f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h @@ -359,14 +359,6 @@ typedef enum { SYS_WKUP3 = PC_1, SYS_WKUP4 = PC_13, - /**** QSPI pins ****/ - QSPI1_IO0 = PD_11, - QSPI1_IO1 = PD_12, - QSPI1_IO2 = PE_2, - QSPI1_IO3 = PD_13, - QSPI1_SCK = PB_2, - QSPI1_CSN = PB_6, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c index 6c2ac77d70..3db7c5d471 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c @@ -459,23 +459,14 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to ULPI_D3 [USB3320C-EZK_D3] {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_D0 [N25Q128A13EF840E_DQ0] {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_D1 [MT25QL512ABB1EW9_DQ1] - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to DFSDM_DATIN5 [TP5] {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SPDIF_TX [TP20] {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to AUDIO_SCL [WM8994ECS/R_SCLK] {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_D3 [N25Q128A13EF840E_DQ3] {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_D2 [N25Q128A13EF840E_DQ2] - {PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to FMC_D4 [MT48LC4M32B2B5-6A_DQ4] - {PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_D5 [MT48LC4M32B2B5-6A_DQ5] - {PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to FMC_D6 [MT48LC4M32B2B5-6A_DQ6] - {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to FMC_D7 [MT48LC4M32B2B5-6A_DQ7] {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D3/PWM {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D6/PWM {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to ARDUINO A3 {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to ARDUINO A2 - {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to uSD_D0 - {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to RMII_TXD1 [LAN8742A-CZ-TR_TXD1] - {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to FMC_SDCKE0 [MT48LC4M32B2B5-6A_CKE] - {PH_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to FMC_SDNE0 [MT48LC4M32B2B5-6A_CS] {NC, NC, 0} }; @@ -488,6 +479,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_NCS [N25Q128A13EF840E_S] {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to ULPI_D3 [USB3320C-EZK_D3] - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to DFSDM_DATIN5 [TP5] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h index 2894691118..2e538dcf5b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h @@ -58,6 +58,16 @@ struct trng_s { RNG_HandleTypeDef handle; }; +struct qspi_s { + QSPI_HandleTypeDef handle; + PinName io0; + PinName io1; + PinName io2; + PinName io3; + PinName sclk; + PinName ssel; +}; + #include "common_objects.h" #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html b/targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html deleted file mode 100644 index aab71f9608..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html +++ /dev/null @@ -1,1096 +0,0 @@ - - - - - - - - -Release Notes for STM32F7xx HAL Drivers - - - - - -
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Release -Notes for STM32F7xx HAL Drivers

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Copyright -2017 STMicroelectronics

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 The hardware -abstraction layer (HAL) provides low level drivers and the hardware -interfacing methods to interact with upper layer (application, -libraries and stacks).  It includes a complete set of ready-to-use -APIs, that are feature-oriented instead of IP-Oriented to simplify user -application development.

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Update History

V1.2.5 / 02-February-2018

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Main -Changes

  • General updates to fix known defects and enhancements implementation
  • HAL update
    • Add new macro to get variable aligned on 32-bytes, required for cache maintenance purpose
    • Update UNUSED() macro implementation to avoid GCC warning
      • The warning is detected when the UNUSED() macro is called from C++ file
  • HAL SAI update
    • Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue
  • HAL PWR update
    • Update -HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode() APIs to ensure -that all instructions finished before entering STOP mode.
  • HAL HCD update
    • Add new callback to be used to handle usb device connection/disconnection
      • HAL_HCD_PortEnabled_Callback()
      • HAL_HCD_PortDisabled_Callback()
    • Update to prevent reactivate host interrrupt channel

V1.2.4 / 22-December-2017

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Main -Changes

  • General updates to fix known defects and enhancements implementation
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • Rework of HAL CAN driver (compatibility break) 
      • A -new HAL CAN driver has been redesigned with new APIs, to bypass -limitations on CAN Tx/Rx FIFO management present with previous HAL CAN -driver version.
      • The -new HAL CAN driver is the recommended version. It is located as usual -in Drivers/STM32F7xx_HAL_Driver/Src and -Drivers/STM32f7xx_HAL_Driver/Inc folders. It can be enabled through -switch HAL_CAN_MODULE_ENABLED in stm32f7xx_hal_conf.h
      • The -legacy HAL CAN driver is also present in the release in -Drivers/STM32F7xx_HAL_Driver/Src/Legacy and -Drivers/STM32F7xx_HAL_Driver/Inc/Legacy folders for software -compatibility reasons. Its usage is not recommended as deprecated. It -can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in -stm32f7xx_hal_conf.h
  • HAL update
    • Update HAL driver to allow user to change systick period to 1ms , 10 ms or 100 ms :
      • Add the following API's :  
        • HAL_GetTickPrio() : Returns a tick priority.
        • HAL_SetTickFreq() : Sets new tick frequency.
        • HAL_GetTickFreq() : Returns tick frequency.
      • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies : 10 Hz , 100 Hz and 1KHz (default).
  • HAL CAN update
    • Fields of CAN_InitTypeDef structure are reworked:
      • SJW -to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to -TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to -AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to -TransmitFifoPriority
    • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's
    • HAL_CAN_Transmit() -is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then -HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
    • HAL_CAN_Transmit_IT() -is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then -HAL_CAN_AddTxMessage() for place Tx request.
    • HAL_CAN_Receive() -is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until -reception, then HAL_CAN_GetRxMessage()
      to get Rx message.
    • HAL_CAN_Receive_IT() -is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then -HAL_CAN_GetRxMessage()
       in the receivecallback to get Rx message
    • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
    • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
    • HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
    • More complete "How to use the new driver" is detailed in the driver header section itself.
  • HAL RCC update
      • Add new LL macro
        • LL_RCC_PLL_SetMainSource() - allowing to configure PLL clock source
      • Add new HAL macros
        • __HAL_RCC_GET_RTC_SOURCE() - allowing to get the RTC clock source
        • __HAL_RCC_GET_RTC_HSE_PRESCALER() - allowing to get the HSE clock divider for RTC peripheral
      • Ensure reset of CIR and CSR - registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions
      • Update HAL_RCC_GetSysClockFreq() - to avoid risk of rounding error which may leads to a wrong returned - value. 
      • Update HAL_RCC_DeInit() -  and LL_RCC_DeInit() APIs to
        • Be able to return HAL/LL - status
        • Add checks for HSI, PLL and - PLLI2S  ready before modifying RCC CFGR registers
        • Clear all interrupt flags
        • Initialize systick interrupt - period
  • HAL DMA update
    • Add clean of callbacks in HAL_DMA_DeInit() API
    • Fix wrong DMA_FLAG_FEIFO_4 and DMA_FLAGDMAEIFO_4 defines values 
  • HAL I2C update
    • Update Interface APIs headers to remove confusing message about device address
    • Update I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
    • Update I2C_TransferConfig() to fix wrong bit management
  • LL USART update
    • Add assert macros to check USART BaudRate register
  • HAL ETH update
    • Do{..} While(0) insured in multi statement macros :
      • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() 
      • __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()
  • HAL FLASH update
    • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
  • HAL GPIO update
    • Add missing define of GPIO_PIN_2 in GPIOK_PIN_AVAILABLE list
  • HAL PCD update
    • Do{..} While(0)  insured in multi statement macros
  • LL UTILS update
    • stm32f7xx_ll_utils.h : Update LL_GetPackageType command to return uint32_t instead of uint16_t
  • HAL TIM update
    • stm32f7xx_hal_tim_ex.c : Update HAL_TIMEx_ConfigBreakDeadTime API to avoid to block timer behavior when
      remains in the state HAL_TIM_STATE_BUSY.
    •  stm32f7xx_hal_tim.h : 
      • Fix __HAL_TIM_SET_PRESCALER() macro
      • Fix typos in some exported macros description 
  • LL FMC update
    • HAL_SDRAM_SendCommand() API: Remove the timeout check
  • HAL NAND update
    • Fix wrong check for NAND status
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V1.2.3 / 25-August-2017

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Main -Changes

  • General updates -to fix known defects and enhancements implementation
  • Remove Date and Version from header files
  • Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the POSITION_VAL() macro
  • HAL CAN update
    • Add missing unlock in HAL_CAN_Receive_IT() process
  • HAL DCMI update
    • HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback()
  • HAL DFSDM update
    • Fix cast issue on APIs that return signed integer value (uint32_t) 
  • HAL DMA update
    • HAL DMA driver clean-up: remove non referenced callback APIs: HAL_DMA_CleanCallbacks()
  • HAL FLASH update
    • FLASH_Program_DoubleWord() API: Replace 64-bit accesses with 2 double words operations
  • HAL Generic update
    • Update assert_param() macro definition to be in line with stm32_ll_utils.c driver
  • HAL GPIO update
    • GPIOK_PIN_AVAILABLE() assert macro update to allow possibility to configure GPIO_PIN_2
  • HAL LTDC update
    • Rename HAL_LTDC_LineEvenCallback() API to HAL_LTDC_LineEventCallback()
  • HAL PCD update
    • Update HAL_PCD_IRQHandler() API to fix transfer issues when USB HS is used with DMA enabled
  • HAL RCC update
    • Update HAL_RCC_GetOscConfig() API to:
      • set PLLR in the RCC_OscInitStruct
      • check on null pointer
    • Update HAL_RCC_ClockConfig() API to:
      • check on null pointer
      • optimize code size by updating the handling method of the SWS bits
      • update -to use  __HAL_FLASH_GET_LATENCY() flash macro instead of using -direct register access to LATENCY bits in FLASH ACR register.
  • HAL SAI update
    • Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI
  • HAL TIM update
    • Update HAL_TIMEx_ConfigBreakInput() API to support BKINP/BKIN2P polarity bits.
  • LL DMA update
    • Update -SET_BIT() access to LIFCR and HIFCR registers by WRITE_REG() to avoid -read access that is not allowed when clearing DMA flags
  • LL I2C update
    • Update LL_I2C_Init() API to avoid enabling own address1 when OwnAddress1 parameter value in the I2C_InitStruct is equal to 0.
  • LL TIM update
    • Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in CR1 register instead of setting it.
    • Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in CR1 register instead of clearing it.
  • LL USB update
    • Update USB_EP0StartXfer() API to fix transfer issues when USB HS is used with DMA enabled

V1.2.2 / 14-April-2017

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Main -Changes

  • General updates -to fix known defects and enhancements implementation
  • HAL CAN update
    • Add - management of overrun error. 
    • Allow - possibility to receive messages from the 2 RX FIFOs in parallel via - interrupt.
    • Fix message - lost issue with specific sequence of transmit requests.
    • Handle - transmission failure with error callback, when NART is enabled.
    • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when - timeout is reached

V1.2.1 / 24-March-2017

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Main -Changes

  • Update CHM UserManuals to support LL drivers
  • General updates -to fix known defects and enhancements implementation
  • HAL DMA update
    • Update HAL_DMA_Init() function to adjust the compatibility check between FIFO threshold and burst configuration
  • HAL MMC update
    • Update HAL_MMC_InitCard() function with proper initialization sequence adding a delay after MMC clock enable
    • Update MMC_DMAError() function ignore DMA FIFO error as not impacting the data transfer
  • HAL SD update
    • Update HAL_SD_InitCard() function with proper initialization sequence adding a delay after SD clock enable
    • Update SD_DMAError() function ignore DMA FIFO error as not impacting the data transfer
  • HAL NAND update
    • Update HAL_NAND_Address_Inc() function implementation for proper plane number check
  • LL SDMMC update
    • Update SDMMC_DATATIMEOUT value with appropriate value needed by reading and writing operations of SD and MMC cards
  • LL RTC update
    • LL_RTC_TIME_Get() and LL_RTC_DATE_Get() inline macros optimization
  • LL ADC update
    • Fix wrong ADC group injected sequence configuration
      • LL_ADC_INJ_SetSequencerRanks() -and LL_ADC_INJ_GetSequencerRanks() API's update to take in -consideration the ADC number of conversions
      • Update the defined values for ADC group injected seqencer ranks 

V1.2.0 / 30-December-2016

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Main -Changes

  • Official release to add the support of STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx devices
  • Add Low Layer drivers allowing performance and footprint optimization
    • Low -Layer drivers APIs provide register level programming: require deep -knowledge of peripherals described in STM32F7xx Reference Manuals
    • Low -Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, -DMA2D, EXTI, GPIO, I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM, -USART, WWDG peripherals and additionnal Low Level Bus, System and -Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f7xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f7xx_ll_ppp.h file must be included in user code.
  • General updates -to fix known defects and enhancements implementation
  • Add new HAL MMC and SMBUS drivers
  • HAL Cortex update
    • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f7xx_hal_cortex.h to stm32f7xx_hal_cortex.c
    • Clear the whole MPU control register in HAL_MPU_Disable() API
  • HAL CRYP update
    • Add support of AES
  • HAL DMA update
    • Add a check on DMA stream instance in HAL_DMA_DeInit() API
  • HAL ETH update 
    • Fix wrong definitions in driver header file stm32f7_hal_eth.h
  • HAL FLASH update
    • Support OTP program operation
    • Add the support of PCROP feature
    • Update the clearing of error flags
  • HAL I2C update
    • Align driver source code with other STM32 families
  • HAL JPEG update 
    • Update the output data management when HAL_JPEG_Pause() is performed during the last data sending
  • HAL RCC update
    • Enable PWR only if necessary for LSE configuration in HAL_RCC_OscConfig() API
    • Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1
    • Rename RCC_DFSDM1CLKSOURCE_PCLK define to RCC_DFSDM1CLKSOURCE_PCLK2
  • HAL SPI update
    • Clear RX FIFO at the end of each transaction
  • HAL UART update
    • Remove USART_CR2_LINEN bit clearing when initializing in synchronous mode
  • HAL USB update
    • Add support of embedded USB PHY Controller
    • Add support of Battery Charging Detector (BCD) feature
  • LL SDMMC update
    • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions
  • LL USB update
    • Update PENA bit clearing in OTG_HPRT0 register
  • The following changes done on the HAL drivers require an update on the -application code based on older HAL versions
    • HAL SD update
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
    • HAL TIM update
      • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure
      • Refer to the TIM examples to identify the changes 
    • HAL NAND update
      • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • Add new HAL_NAND_ConfigDevice API

V1.1.1 / 01-July-2016

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Main -Changes

  • HAL DMA update 
    • Update HAL_DMA_PollForTransfer() function implementation to avoid early TIMEOUT error.
  • HAL JPEG update
    • Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth
  • HAL SPI update
    • Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication

V1.1.0 / 22-April-2016

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Main -Changes

  • Official release to add the support of STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx devices
  • General updates -to fix known defects and enhancements implementation
  • Add new HAL drivers for DFSDM, DSI, JPEG and MDIOS peripherals
  • Enhance HAL delay and timebase implementation
    • Add new -drivers stm32f7xx_hal_timebase_tim_template.c, stm32f7xx_hal_timebase_rtc_alarm_template.c and -stm32f7xx_hal_timebase_rtc_wakeup_template.c which override the native HAL time -base functions (defined as weak) to either use the TIM or the RTC as time base tick source. For -more details about the usage of these drivers, please refer to HAL\HAL_TimeBase -examples and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the -application code based on HAL V1.0.4
    • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C, QSPI (referenced as PPP here below) drivers
      • Add PPP error management during DMA process. This requires the following updates on user application:
        • Configure and enable -the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f7xx_it.c file, -PPP_IRQHandler() -function: add a call to -HAL_PPP_IRQHandler() function -
        • Add and customize -the Error Callback API: HAL_PPP_ErrorCallback()
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    • HAL I2C (referenced as PPP here below) drivers: -
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in the DMA transfer process. This requires the following updates on user application:
        • Configure and enable -the PPP IRQ in HAL_PPP_MspInit() function
      -
        • In stm32f7xx_it.c file, -PPP_IRQHandler() -function: add a call to -HAL_PPP_IRQHandler() function
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    • HAL IWDG driver: rework overall driver for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: rework overall driver for better implementation -
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), -HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs  -
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
    • HAL QSPI driver:  Enhance the DMA transmit process by using PPP TC interrupt instead of waiting on TC flag under DMA ISR. This requires the following updates on user application:
      • Configure and enable -the QSPI IRQ in HAL_QSPI_MspInit() function
      • In stm32f7xx_it.c file, QSPI_IRQHandler() -function: add a call to -HAL_QSPI_IRQHandler() function
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    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive() -
      • Remove -HAL CEC receive interrupt process function HAL_CEC_Receive_IT() -and enable the "receive"  mode during the Init phase -
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
         -
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and -HAL_CEC_ChangeRxBuffer() -
      • Remove the 'InitiatorAddress' field from the CEC_InitTypeDef -structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function -
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function -
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to -CEC_InitTypeDef structure
  • HAL CAN update 
    • Add the support of CAN3
  • HAL CEC update
    • Overall driver rework with break of compatibility with HAL -V1.0.4
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
-
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase -
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and -HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' field from the CEC_InitTypeDef -structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to -CEC_InitTypeDef structure
-
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in -CEC_HandleTypeDef structure to provide the CEC -state -information related to Rx Operations
      • Rename "state" -field in CEC_HandleTypeDef structure to "gstate": CEC state information -related to global Handle management and Tx Operations -
      • Update CEC process -to manage the new CEC states. -
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC -state parameters (gState, rxState)
  • HAL DMA update 
    • Add -new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to -register/unregister the different callbacks identified by -the enum typedef HAL_DMA_CallbackIDTypeDef
    • Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context
      • The new registered Abort callback is called when DMA transfer abortion is completed
    • Add the check of -compatibility between FIFO threshold level and size of the memory burst in the -HAL_DMA_Init() API -
    • Add new Error Codes: -HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and -HAL_DMA_ERROR_NOT_SUPPORTED
    • Remove all DMA states -related to MEM0/MEM1 in HAL_DMA_StateTypeDef
  • HAL DMA2D update 
    • Update the -HAL_DMA2D_DeInit() function to: -
      • Abort transfer in case -of ongoing DMA2D transfer
      -
      • Reset DMA2D control -registers
    • Update -HAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer
    • Optimize -HAL_DMA2D_IRQHandler() by reading status registers only once -
    • Update -HAL_DMA2D_ProgramLineEvent() function to: -
      • Return HAL error state -in case of wrong line value
      -
      • Enable line interrupt -after setting the line watermark configuration
    • Add new HAL_DMA2D_CLUTLoad() and HAL_DMA2D_CLUTLoad_IT() -functions to start DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Abort() -function to abort the DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Suspend() -function to suspend the DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Resume() -function to resume the DMA2D CLUT loading
    • Add new DMA2D dead time -management:
      • HAL_DMA2D_EnableDeadTime() -function to enable DMA2D dead time feature
      • HAL_DMA2D_DisableDeadTime() -function to disable DMA2D dead time feature
      • HAL_DMA2D_ConfigDeadTime() -function to configure dead time
    • Update the name of -DMA2D Input/Output color mode defines to be more clear for user (DMA2D_INPUT_XXX -for input layers Colors, DMA2D_OUTPUT_XXX for output framebuffer -Colors)
- -
  • HAL DCMI update 
    • Rename DCMI_DMAConvCplt -to DCMI_DMAXferCplt -
    • Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral -
    • Add new timeout -implementation based on cpu cycles for DCMI stop -
    • Add HAL_DCMI_Suspend() -function to suspend DCMI capture -
    • Add HAL_DCMI_Resume() -function to resume capture after DCMI suspend -
    • Update lock mechanism -for DCMI process -
    • Update HAL_DCMI_IRQHandler() function to: -
      • Add error management in -case DMA errors through XferAbortCallback() and -HAL_DMA_Abort_IT()
      -
      • Optimize code by using -direct register read
    • Move -the content of the stm32f7xx_hal_dcmi_ex.c/.h files to common driver -files (the extension files are kept empty for projects compatibility -reason)
  • HAL FLASH update 
    • Add the support of Dual BANK feature
    • Add __HAL_FLASH_CALC_BOOT_BASE_ADR() macro to calculate the FLASH Boot Base Adress
    • Move Flash total sector define to CMSIS header files
  • HAL FMC update
    • Update FMC_NORSRAM_Init() to remove the Burst access mode configuration
    • Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks
  • HAL HCD update
    • Update HCD_Port_IRQHandler() to be compliant with new Time base implementation
  • HAL -I2C update -
    • Add the support of I2C fast mode plus (FM+)
    • Update Polling management:
      • The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    -
    • Add the management of Abort service: Abort DMA transfer through interrupt
      • In the case of Master Abort IT transfer usage:
        • Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process
        • A new abort state is defined in the HAL_I2C_StateTypeDef structure
    -
    • Add the management of I2C peripheral errors, ACK -failure and STOP condition detection during DMA process. This requires the following updates -on user application:
      • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
      • In stm32f7xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
      • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
      • Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API
    • Add the support of I2C repeated start feature: -
      • With the following new APIs
      -
        • HAL_I2C_Master_Sequential_Transmit_IT() -
        • HAL_I2C_Master_Sequential_Receive_IT() -
        • HAL_I2C_Master_Abort_IT() -
        • HAL_I2C_Slave_Sequential_Transmit_IT() -
        • HAL_I2C_Slave_Sequential_Receive_IT() -
        • HAL_I2C_EnableListen_IT() -
        • HAL_I2C_DisableListen_IT()
      -
      • Add new user callbacks:
      -
        • HAL_I2C_ListenCpltCallback()
        • HAL_I2C_AddrCallback()
      -
    • Several -updates on HAL I2C driver to implement the new I2C state machine: -
      • Add new API to get the I2C mode: -HAL_I2C_GetMode() -
      • Update I2C process to -manage the new I2C states
    -
  • HAL IWDG update
    • Overall rework of the driver for a more efficient implementation
      • Remove the following APIs:
        • HAL_IWDG_Start()
        • HAL_IWDG_MspInit()
        • HAL_IWDG_GetState()
      • Update implementation:
        • HAL_IWDG_Init() : this function insures the configuration and the start of the IWDG counter
        • HAL_IWDG_Refresh() : this function insures the reload of the IWDG counter
      • Refer to the following example to identify the changes: IWDG_Example
  • HAL LPTIM update
    • Update HAL_LPTIM_TimeOut_Start_IT() and HAL_LPTIM_Counter_Start_IT( ) APIs -to configure WakeUp Timer EXTI interrupt to be able to wakeup MCU from low power -mode by pressing the EXTI line -
    • Update HAL_LPTIM_TimeOut_Stop_IT() and HAL_LPTIM_Counter_Stop_IT( ) APIs to -disable WakeUp Timer EXTI interrupt
  • HAL LTDC update
    • Update -HAL_LTDC_IRQHandler() to manage the case of reload interrupt
    • Add LTDC extension driver needed with DSI
    • Add HAL_LTDC_SetPitch() function for pitch reconfiguration
    • Add new callback API -HAL_LTDC_ReloadEventCallback() -
    • Add HAL_LTDC_Reload() -to configure LTDC reload feature -
    • Add new No Reload LTDC -variant APIs
       -
      • HAL_LTDC_ConfigLayer_NoReload() -to configure the LTDC Layer according to the specified without reloading -
      • HAL_LTDC_SetWindowSize_NoReload() -to set the LTDC window size without reloading -
      • HAL_LTDC_SetWindowPosition_NoReload() -to set the LTDC window position without reloading -
      • HAL_LTDC_SetPixelFormat_NoReload() -to reconfigure the pixel format without reloading -
      • HAL_LTDC_SetAlpha_NoReload() -to reconfigure the layer alpha value without reloading -
      • HAL_LTDC_SetAddress_NoReload() -to reconfigure the frame buffer Address without reloading -
      • HAL_LTDC_SetPitch_NoReload() -to reconfigure the pitch for specific cases -
      • HAL_LTDC_ConfigColorKeying_NoReload() -to configure the color keying without reloading -
      • HAL_LTDC_EnableColorKeying_NoReload() -to enable the color keying without reloading -
      • HAL_LTDC_DisableColorKeying_NoReload() -to disable the color keying without reloading -
      • HAL_LTDC_EnableCLUT_NoReload() -to enable the color lookup table without reloading -
      • HAL_LTDC_DisableCLUT_NoReload() -to disable the color lookup table without -reloading
      • Note: -Variant functions with _NoReload post fix allows to set the LTDC -configuration/settings without immediate reload. This is useful in case -when the program requires to modify several LTDC settings (on one or -both layers) then applying (reload) these settings in one shot by -calling the function HAL_LTDC_Reload
-
  • HAL NOR update
    • Update NOR_ADDR_SHIFT macro implementation
  • HAL PCD update
    • Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value
  • HAL QSPI update
    • Update to manage QSPI error management during DMA process
    • Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR
    • These two improvements require the following updates on user application:
      • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
      • In stm32f7xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
      • Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()
    • Add -the management of non-blocking transfer abort service: HAL_QSPI_Abort_IT(). In -this case the user must:
      • Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process
      • A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase
    • Polling management update:
      • The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative. 
    • Refer to the following examples, which describe the changes:
      • QSPI_ReadWrite_DMA
      • QSPI_MemoryMapped
      • QSPI_ExecuteInPlace
    • Add two new APIs for the QSPI fifo threshold: -
      • HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of -the QSPI -
      • HAL_QSPI_GetFifoThreshold(): give the current FIFO -threshold
      -
    • Fix wrong data size management in HAL_QSPI_Receive_DMA()
  • HAL RCC update
    • Update HAL_RCC_PeriphCLKConfig() function to adjust the SystemCoreClock
    • Optimize HAL_RCC_ClockConfig() function code
    • Optimize internal oscillators and PLL startup times
  • HAL RTC update 
    • Update HAL_RTC_GetTime() with proper 'SubSeconds' and 'SecondFraction' management
  • HAL SAI update 
    • Update SAI state in case of TIMEOUT error within the HAL_SAI_Transmit() / HAL_SAI_Receive() -
    • Update HAL_SAI_IRQHandler: -
      • Add error management in -case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT() -
      • Add error management in -case of IT
    • Move -SAI_BlockSynchroConfig() and SAI_GetInputClock() functions to -stm32f7xx_hal_sai.c/.h files (extension files are kept empty for -projects compatibility reason)
-
  • HAL SPDIFRX update
    • Overall driver update for wait on flag management optimization
  • HAL SPI update
    • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency
      • Polling mode: -
        • Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" -statement to check on RXNE/TXE flage while transferring -data
-
      •  Interrupt mode:
        • Minimize access on SPI registers -
      • All modes:
        • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
        • Update timeout management to check on global processes
        • Update error code management in all processes
    • Update DMA process: -
      • Add the management of SPI peripheral errors during DMA process. This requires the following updates in -the user application:
        • Configure and enable the SPI IRQ in HAL_SPI_MspInit() function
        • In stm32f7xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function
        • Add and customize the Error Callback API: HAL_SPI_ErrorCallback()
        • Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA
      -
  • HAL TIM update 
    • Update HAL_TIM_ConfigOCrefClear() function for proper configuration of the SMCR register
    • Add new function HAL_TIMEx_ConfigBreakInput() to configure the break input source
  • HAL UART, USART, SMARTCARD and IRDA (referenced as PPP here below) update -
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of PPP peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
  • HAL WWDG update 
    • Overall rework of the driver for more efficient implementation
      • Remove the following APIs:
        • HAL_WWDG_Start()
        • HAL_WWDG_Start_IT()
        • HAL_WWDG_MspDeInit()
        • HAL_WWDG_GetState()
      • Update implementation:
        • HAL_WWDG_Init()
          • A new parameter in the Init Structure: EWIMode
        • HAL_WWDG_MspInit()
        • HAL_WWDG_Refresh() 
          • This function insures the reload of the counter
          • The "counter" parameter has been removed
        • HAL_WWDG_IRQHandler()
        • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()
    • Refer to the following example to identify the changes: WWDG_Example

V1.0.4 / 09-December-2015

-

Main -Changes

  • HAL Generic update
    • Update HAL -weak empty callbacks to prevent unused argument compilation warnings with some -compilers by calling the following line: -
      • UNUSED(hppp);
  • HAL ETH update 
    • Update HAL_ETH_Init() function to add timeout on the Software reset management

V1.0.3 / 13-November-2015

-

Main -Changes

  • General updates -to fix known defects and enhancements implementation
  • One change done on the HAL CRYP requires an update on -the application code based on HAL V1.0.2 -
    • Update -HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData -parameters
  • HAL Generic update
    • Update HAL -weak empty callbacks to prevent unused argument compilation warnings with some -compilers by calling the following line: -
      • UNUSED(hppp);
    • Remove references to STM32CubeMX and MicroXplorer from stm32f7xx_hal_msp_template.c file
  • HAL ADC update
    • Replace ADC_CHANNEL_TEMPSENSOR definition from ADC_CHANNEL_16 to ADC_CHANNEL_18  
    • Update HAL ADC driver state machine for code efficiency
    • Add new literal: ADC_INJECTED_SOFTWARE_START to be used as possible -value for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef -structure to select the ADC software trigger mode.
  • HAL CORTEX update -
    • Remove duplication -for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
  • HAL CRYP update
    • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
  • HAL FLASH update
    • Update OB_IWDG_STOP_ACTIVE definition
    • Update OB_RDP_LEVEL_x definition by proper values
    • Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration
  • HAL RCC update
    • update values for LSE Drive capability defines
    • update PLLN min value 50 instead of 100
    • add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider
    • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG 
    • Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration
  • HAL SAI update
    • update for proper management of the external synchronization input selection
      • update of HAL_SAI_Init () funciton
      • update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups
    • update SAI_SLOTACTIVE_X  defines values
    • update HAL_SAI_Init() function for proper companding mode management
    • update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers
    • update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size
    • update HAL_SAI_EnableRxMuteMode() function for proper mute management
    • update SAI_InitPCM() function to support 24bits configuration
  • HAL SD update
    • update HAL_SD_Get_CardInfo() to properly support high capacity cards
  • HAL SPDIFRX update
    • update SPDIFRX_DMARxCplt() function implementation to check on circular mode before disabling the DMA
  • HAL TIM update
    • Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check
  • HAL UART update
    • Update __HAL_UART_CLEAR_IT macro for proper functionning 
  • ll FMC update
    • add FMC_PAGE_SIZE_512 define
  • ll SDMMC update
    • update SDMMC_SetSDMMCReadWaitMode() function for proper functionning

V1.0.2 / 21-September-2015

-

Main -Changes

  • HAL Generic update
    • stm32f7xx_hal.conf_template.h: update HSE_STARTUP_TIMEOUT
    • stm32f7xx_hal_def.h: update the quotation marks used in #error"USE_RTOS should be 0 in the current HAL release"
  • HAL DMA update
    • Overall -driver update for code optimization
      • add -StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef -structure -
      • add -DMA_Base_Registers private structure -
      • add static function -DMA_CalcBaseAndBitshift() -
      • update -HAL_DMA_Init() function to use the new added static function -
      • update -HAL_DMA_DeInit() function to optimize clear flag operations -
      • update -HAL_DMA_Start_IT() function to optimize interrupts enable -
      • update -HAL_DMA_PollForTransfer() function to optimize check on flags -
      • update -HAL_DMA_IRQHandler() function to optimize interrupt flag management
  • HAL ETH update
    • remove duplicated macro IS_ETH_RX_MODE()
  • HAL GPIO update
    • Rename -GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW -
    • Rename -GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM -
    • Rename -GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH -
    • Rename -GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH
  • HAL HASH update
    • Rename -HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef -
    • Rename -HAL_HASH_PhaseTypeDef to HAL_HASHPhaseTypeDef
  • HAL RCC update
    • update values for LSE Drive capability defines
    • update PLLN/PLLI2SN/PLLSAI VCO min value 100MHz instead of 192MHz
    • add __HAL_RCC_MCO1_CONFIG() and __HAL_RCC_MCO2_CONFIG() macros
    • update HAL_RCCEx_PeriphCLKConfig() function to reset the Backup domain only if the RTC Clock source selection is modified 
  • HAL TIM update
    • update the implementation of __HAL_TIM_SET_COMPARE() macro
    • remove useless assert() in HAL_TIM_PWM_ConfigChannel(), TIM_OC2_SetConfig() and HAL_TIM_PWM_ConfigChannel() functions
  • HAL CAN update
    • add the clear flag ERRI bit in HAL_CAN_IRQHandler()
  • HAL I2S update
    • update I2S HAL_I2S_Transmit() API to keep the check on busy flag only for the slave
  • HAL QSPI update
    • Add __HAL_QSPI_CLEAR_FLAG() before QSPI_Config()
  • HAL UART update
    • Remove -enabling of ERR IT source and PE source from HAL_UART_Transmit_IT() and -remove the corresponding disabling ERR/PE IT from UART_EndTransmit_IT()
  • HAL PCD update 
    • Clean status phase received interrupt when DMA mode enabled 
  • HAL HCD update
    • Update to use local -variable in USB Host channel re-activation
  • ll FMC update
    • update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE
    • remove return HAL_ERROR from FMC_SDRAM_SendCommand() function

V1.0.1 / 25-June-2015

-

Main -Changes

  • General updates -to fix known defects and enhancements implementation
  • HAL CRC update
    • update __HAL_CRC_SET_IDR() macro implementation to use WRITE_REG() instead of MODIFY_REG()
  • HAL CEC update
    • update timeout management in HAL_CEC_Transmit() and HAL_CEC_Receive() functions
  • HAL Cortex update
    • update HAL_MPU_ConfigRegion() function to be misra compliant
  • HAL ETH update
    • Remove -duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros
    • Remove -illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
    • Update -ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and -READING_STATUS)
  • HAL FLASH update
    • update FLASH_OB_GetRDP() function to return uint8_t  instead of FlagStatus
    • update OB_RDP_LEVELx definition
    • add __HAL_FLASH_GET_LATENCY() macro
  • HAL HASH update
    • update -HASH_DMAXferCplt() and HASHEx_DMAXferCplt() functions to properly -configure the number of valid bits in last word of the message
    • update HAL_HASH_SHA1_Accumulate() function to check on the length of the input buffer
    • update -HAL_HASH_MODE_Start_IT() functions (Mode stands for MD5, SHA1, SHA224 and SHA256 ) to :
      • Fix processing -fail for small input buffers -
      • to unlock -the process and call return HAL_OK at the end of HASH processing to avoid -incorrect repeating software -
      • properly to manage -the HashITCounter efficiency -
      • Update to call the -HAL_HASH_InCpltCallback() at the end of the complete buffer instead -of -every each 512 bits
    • update HASH_IT_DINI and HASH_IT_DCI definition
    • update __HAL_HASH_GET_FLAG() macro definition
  • HAL I2S update
    • update HAL_I2S_Transmit() function to ensure the waiting on Busy flag in case of slave mode selection
  • HAL RTC update
    • update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on WUTWF flag
    • rename RTC_TIMESTAMPPIN_PI8 define to RTC_TIMESTAMPPIN_POS1
    • rename RTC_TIMESTAMPPIN_PC1 define to RTC_TIMESTAMPPIN_POS2
    • update __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG() macro definition
    • update __HAL_RTC_TAMPER_GET_IT() macro definition
    • update __HAL_RTC_TAMPER_CLEAR_FLAG() macro definition
    • update __HAL_RTC_TIMESTAMP_CLEAR_FLAG() macro definition
    • update __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro definition
    • add RTC_TAMPCR_TAMPXE and RTC_TAMPCR_TAMPXIE defines
  • HAL SMARTCARD update
    • add SMARTCARD_FLAG_IDLE, SMARTCARD_IT_IDLE and  SMARTCARD_CLEAR_IDLEF defines
  • HAL UART update
    • update HAL_UART_DMAResume() function to clear overrun flag before resuming the Rx transfer
    • update UART_FLAG_SBKF definition
  • HAL USART update
    • update HAL_USART_DMAResume() function to clear overrun flag before resuming the Rx transfer
  • LL FMC update
    • update NAND timing maximum values
  • LL USB update -
    • USB_FlushTxFifo API: -update to flush all Tx FIFO -
    • Update to use local -variable in USB Host channel re-activation
- -

V1.0.0 / 12-May-2015

-

Main -Changes

  • First official release for STM32F756xx/746xx/745xx -devices
- -

License

-
-
Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
    -
  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
    2. -
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
    3. -
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived
    -
    4. -
-       -from this software without specific prior written permission.
-
-THIS -SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGE.
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-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32

-
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-
- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h index 00504a4ca9..5acd12a040 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h @@ -43,6 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#include "stm32f7xx_ll_rtc.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/Release_Notes_stm32l0xx_hal.html b/targets/TARGET_STM/TARGET_STM32L0/device/Release_Notes_stm32l0xx_hal.html deleted file mode 100644 index d5e838120d..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/device/Release_Notes_stm32l0xx_hal.html +++ /dev/null @@ -1,1413 +0,0 @@ - - - - - -Release Notes for STM32L0xx HAL Drivers - - - - - - - - - -
-

 

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Back to Release page

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Release -Notes for STM32L0xx HAL Drivers

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Copyright -2016 STMicroelectronics

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Update History

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V1.7.0 / 31-May-2016

- -
Main -Changes
- -
  • Maintenance release to fix known defects.
-
  • HAL/LL COMP update
    • Added -missing definition for COMP_INPUT_PLUS_IO6 and -LL_COMP_INPUT_PLUS_IO6, supported by STM32L0 Category1 (STM32L011xx, -STM32L021xx).
    • Removed COMP_INVERTINGINPUT_IO3 definition.
    • Renamed COMP_INVERTINGINPUT_IO2 to COMP_INPUT_MINUS_DAC1_CH2.
    • The EXTI set-up is now managed by HAL_COMP_Init() function, using updated definitions of -COMP_TRIGGERMODE_xxx.
      Therefore, the functions  HAL_COMP_Start_IT() and HAH_COMP_Stop_IT() have been removed.
      In any mode, the application must use HAL_COMP_Start() and HAL_COMP_Stop().
      • For information, this update was already available in V1.6.0.
  • HAL RTC update
    • Updated HAL_RTCEx_SetWakeUpTimer_IT() function by adding clear of Wake-Up flag before enabling the interrupt.
  • HAL LCD update
    • Corrected SYSCFG LCD External Capacitors definitions.
    • Added new __HAL_SYSCFG_VLCD_CAPA_CONFIG() macro to configure the VLCD Decoupling capacitance connection.
    • Added new __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() macro to return the decoupling of LCD capacitance
      configured by user.
    • Added LCD Voltage output buffer enable macro definitions.

V1.6.0/ 15-April-2016

- -
Main -Changes
- -
  • First official release supporting the Low Level drivers for the STM32L0xx family: 
    • Low -Layer drivers APIs provide register level programming: they require -deep knowledge of peripherals described in STM32L0xx Reference Manual.
    • Low -Layer drivers are available for: ADC, COMP, CORTEX, CRC, CRS,DAC, DMA, -EXTI, GPIO, I2C, IWDG, LPTIM, LPUART, PWR, RCC, RNG, RTC, SPI, TIM, -USART, WWDG peripherals and additional Low Level Bus, System and -Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l0xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l0xx_ll_ppp.h file must be included in user code.

  • Updates of the HAL : 
    • HAL_SYSCFG_EnableVREFINT() and HAL_SYSCFG_DisableVREFINT() functions and HAL_VREFINT_Cmd macro suppressed since VREFINT is managed by the system.
    • Several updates on dedicated HAL as specified in the list below. The major changes concerns HAL_COMP and HAL_UART.


List of HAL updates or corrections provided by this release:
  • HAL update
    • Change the way the APB AHB prescaler table is defined inside the HAL.
    • Change the variable 'uwTick' from 'static' to 'global'.
    • Compliancy with MISRA C 2004 rule 10.6 (A "U" suffix shall be applied to all constants of unsigned type)
    • Compliancy -with MISRA C 2004 rule 16.4. (The identifiers used in the declaration -and definition of a function shall be identical) 
  • HAL COMP update
    • Major rework on the lock and on the state machine associated to the COMP HAL.
    • Optimization of several functions and uniformization of the driver within the whole STM32 family.
  • HAL CRYPT update
    • Correct the usage of several compilation switches related to STM32L081xx.
  • HAL DMA update
    • Add the following macro : HAL_DMA_GET_COUNTER.
  • HAL FLASH update
    • Update the two following macros : __HAL_FLASH_PREFETCH_BUFFER_ENABLE and __HAL_FLASH_PREFETCH_BUFFER_DISABLE.
  • HAL IRDA update
    • Improve management of the EIE bits for Tx and Rx transfers.
  • HAL I2C update
    • Allow I2C transmission with data size equal to 0.
    • Add new macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE.
  • HAL LPTIM update
    • Update of the LPTIM driver in order to support the exti line 23.
  • HAL UART update
    • Improve UART state machine behavior in case of interrupts.
    • Update the macros -UART_DIV_SAMPLING8 and UART_DIV_SAMPLING16 to correct UART baudrate calculation
    • Add an RXDATA flush request inside the UART_Receive_IT function when the RxState is not in reception state.
  • HAL RCC update
    • Correct the setup of the global variable 'SystemCoreClock'. 
    • Update of the CRS interrupt sources.
    • Renamed RCC_CRS_SYNCWARM  into RCC_CRS_SYNCWARN and renamed RCC_CRS_TRIMOV into RCC_CRS_TRIMOVF.

V1.5.0/ 8-January-2016

- -
Main -Changes
- -
  •  Updates of the HAL : 

    -    - Compliancy with MISRA coding rules (MISRA C 2004 rule 10.5 except for hal_pcd.c file and MISRA C 2004 rule 5.3)    . 
    - Several functions inside the HAL have been updated in order to prevent unused argument compilation warnings.
    - The startup timeout value for many clocks (as HSE, HSI, LSI, MSI, PLL) have been updated     to -reach a more accurate value (alignement to the Datasheet).
    - -The macro __HAL_CORTEX_SYSTICKCLK_CONFIG(..) has been removed -since this service is already covered by the function -HAL_SYSTICK_CLKSourceConfig().
    - Several updates on dedicated HAL as specified in the list below :

    List of HAL updates or corrections provided by this release:

  • HAL update
    • Update -the SYSCFG_BOOT_SYSTEMFLASH definition. (SYSCFG_BOOT_SYSTEMFLASH is now -equal to SYSCFG_CFGR1_BOOT_MODE_0 instead of -SYSCFG_CFGR1_MEM_MODE_0) 
    • The HSE_STARTUP_TIMEOUT is now equal to 100 instead of 5000.
  • HAL I2C update
    • Update the HAL_I2C_Slave_Receive function. Store last data received when requested.
    • Improvement of the HAL_I2C_MasterReceive function. Error management update. (HAL_ERROR detection versus HAL_TIMEOUT)
    • Improvement -of the I2C_MasterTransmit_ISR function. Adding of several -error checks, unlock of the process when requested.
    • Improvement -of the I2C_MasterReceive_DMA function. Adding of several -error checks and abort DMA when requested.
  • HAL UART update
    • Update the check of parameters inside the function HAL_LIN_SendBreak().
    • Correction -of an error present on the V1.4.0 release. On the V1.4.0 release, the -clock used inside the function USART_SetConfig(..) was never set.
  • HAL DMA update
    • Update the DMA_handler structure in order to be MISRA-C 2004 rule 5.3 compliant.
  • HAL SPI update
    • Update the SPI_handler structure in order to be MISRA-C 2004 rule 5.3 compliant.
  • HAL RCC update
    • Update support of RCC_MC03 when requested.
      • -
    • Update support of dynamic HSE prescaler configuration for LCD/RTC peripherals.
      • -
    • Some updates inside the HAL_RCC_ClockConfig function.
    • Some -updates inside the HAL_RCC_MCOConfig function. The enabling of the MCO -clocks (__MC01_CLK_ENABLE() or __MCO2_CLK_ENABLE()) is done separately -depending on the MCO selected.
    • The function HAL_RCCEx_GetPeriphCLKFreq() has been reworked.
    • The -function HAL_RCCEx_PeriphCLKConfig() has been updated. A new error is -now detected when trying to update the HSE divider dynamically.
      • -
  • HAL TSC update
    • Several updates inside the HAL_TSC_Start function and HAL_TSC_Init function. Check of input parameters
  • HAL ADC update
    • The channel 16 (ADC_CHANNEL_16) is not available on all devices.
  • HAL CORTEX
    • The -macro __HAL_CORTEX_SYSTICKCLK_CONFIG(..) has been removed since this -service is already covered by the function -HAL_SYSTICK_CLKSourceConfig().
  • HAL FLASH update
    • The -restriction which was present on V1.4.0 and linked to the OPTVERR -bit usage on STM32L031xx and STM32L041xx has been removed. This is due -to the fact that the new STM32L031xx/STM32L041xx devices supports now this feature. On the first revision of the STM32L031xx/STM32L031xx devices (RevID =   0x1000 retrieved via HAL_GetREVID()), the OPTVERR -bit was not functional. The OPTVERR (Option valid error bit) is set by -hardware when, during an Option byte loading, there was a mismatch for -one or more configurations.

V1.4.0/ 16-October-2015

-
-
Main -Changes
- -
  •  Support -of STM32L011xx and STM32L021xx -series

    -     -On STM32L011xx/    STM32L021xx, compared to STM32L07xxx/STM32L08xxx, some of the main differences are listed hereafter :
    -- SRAM size set to 2KB (instead of 20KB)
    -- Flash size set to 16KB (instead of 192KB)
    -- GPIO available :A,B,C (instead of A,B,C,D,E,H)
    -- Timers available : TIM2,TIM21,LPTIM1 (instead of -TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)

  • Minor updates of the HAL : 

    List of HAL updates or corrections provided by this release:

  • HAL COMP update
    • Update of the non inverting inputs available on the whole L0 family. 
  • HAL RCC update
    • Usage of a common PLLMulTable[] defined in system_stm32l0xx.c.
    • Update in the definition of the different tampers.
    • Minor renaming of several macros.
  • HAL TIMER update
    • Handle lock initialization in all TIM init functions.
  • HAL LCD update
    • Add support of new MuxSegment field inside the init structure.
  • HAL DMA update
    • Alignment of the different channels within the L0 family.

V1.3.0/ 09-September-2015


-
Main -Changes
-
    -
  • Major update of the  -HAL API : 
    -
    -     -- -all MACROs and LITERALs values have been reworked to align all STM32 Families as much as possible
    -- Important information -: A stm32_hal_legacy.h file has been added to the FW package in order to support -the old MACROs and LITERAL values used in the previous versions of -customer applications. (this file is automatically included, from HAL/Inc/Legacy)
    -- In HAL MACROs definitions : do { } while(0) have been used in multi statement macros -
    • -
-
    -
  • -Support -of STM32L031xx and STM32L041xx -series

    -     -On STM32L031xx/    STM32L041xx, compared to STM32L07xxx/STM32L08xxx, the main differences are as follow :
    -- SRAM size set to 8KB (instead of 20KB)
    -- Flash size set to 32KB (instead of 192KB)
    -- GPIO available :A,B,C,H (instead of A,B,C,D,E,H)
    -- Timers available : TIM2,TIM21,TIM22,LPTIM1 (instead of -TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)

    List of HAL updates or corrections provided by this release:


  • HAL ADC update
    • ADC assert param needs to be more specific for discontinuous mode, nb of discont conversions
    • ADC external trigger definition is not complete Flag EOS should not be reset in HAL_ADC_GetValue()
    • ADC poll for event must return timeout instead of error
    • ADC state machine update - States with bitfields are now used for a more accurate status 
    • ADC run in LPrun mode needs SYSCFG buffers enabled
    • ADC_CLOCK_SYNC_PCLK_DIVx was not correct
    • Remove WaitLoopIndex at the beginning of the function HAL_ADC_Enable
    • ADC parameter "ADC_SOFTWARE_START" for compatibility with other STM32 devices
    • ADC poll for conversion must return error status in case of ADC-DMA mode
    • ADC identical error code returned generates confusion
    • Issue observed with ADC start simultaneous commands
    • The HAl_Delay() is not required when ADVREGEN is set
    • [STM32L07xxx/STM32L08xxx] ADC Interface modification : ADC_Init structure update
    • [STM32L07xxx/STM32L08xxx] ADC Interface modification LowPowerAutoOff is now LowPowerAutoPowerOff
    • ADC_Enable does not support the LowPowerAutoOff function
  • HAL COMP update
    • COMP_TRIGGERMODE_NONE missing in stm32l0xx_hal_comp.h
    • COMP wrong implementation of the macro : IS_COMP_WINDOWMODE_INSTANCE
    • Misplaced user callback at HAL_COMP_IRQHandler
    • EXTI Usage model update - add MACROs __HAL_COMP_COMPx_EXTI_GENERATE_SWIT()
    • HAL COMP update in HAL_COMP_Lock() to handle state change and prevent C++ compilation error
    • Add the LPTIM Comparator connection
  • HAL Cortex update
    • [MISRA] bitwise operators ~ and << (MISRA C 2004 rule 10.5)
    • Cortex The function HAL_NVIC_GetPriority(IRQn_Type IRQn) was missing
    • Cortex HAL_NVIC_DisableIRQ()/HAL_NVIC_EnableIRQ() Add a check on negative parameter values
  • HAL CRC update
    • __HAL_CRC_SET_IDR macro improvement
    • CRC wrong definition of __HAL_CRC_SET_IDR macro
    • Uncorrect CRC functions naming, portability failing, out of topic comments
    • Useless Assignment in  stm32l0xx_hal_crc.c detected by CodeSonar
  • HAL DAC update
    • Missing define for DAC Trigger (010: Timer 3 CH3 event)
    • Complete DAC update as per HAL_API_Reference
    • DAC HAL_DAC_Stop_DMA() code clean up
    • HAL_DAC_ConfigChannel: use "hdac->Instance->XXX" instead of "DAC->XXX"
    • No -reset of previous bits WAVEx / MAMPx before setting values in -HAL_DACEx_NoiseWaveGenerate & HAL_DACEx_TriangleWaveGenerate
  • HAL DMA update
    • The description of __HAL_DMA_GET_IT_SOURCE() was incorrect
  • HAL FLASH update
    • FLASH Missing macro __HAL_FLASH_GET_LATENCY
    • FLASH_WaitForLastOperation issue
    • FLASH_Program_IT unlock() issue
    • FLASH Crash during HAL_FLASHEx_HalfPageProgram and HAL_FLASHEx_ProgramParallelHalfPage
    • FLASH Ramfunc error management
    • FLASH IS_OPTIONBYTE(VALUE) is not correct if all options are selected
    • HAL_FLASH Otpion Byte "BootConfig" and "BOOTBit1Config"
    • FLASH SPRMOD option bit is impacted by FLASH_OB_RDPConfig()
    • __HAL_FLASH_GET_FLAG was not functional
  • HAL GPIO update
    • GPIO  The Clear of the External Interrupt is not properly done
    • GPIO GPIO_SPEED LITERALS renaming
    • GPIO_AF for LPTIM is no more compatible with HAL L0 V1.1
    • GPIO AF2 defines for RTC should be aligned for all L0 devices
    • GPIO AF defines for LPTIM1 should be the same for all devices.
    • GPIO Bug at EXTi register GPIO config in HAL_GPIO_Init() function
    • GPIO GPIO_AF5_I2S3ext Update the defined name to be more generic 
    • GPIO Protect init from impossible AF configuration
    • GPIO interrupt mode is not reset
    • GPIO Check of the Pin availability according to the GPIO in use
    • GPIO rework GPIO_GET_SOURCE
    • [STM32L07xxx/STM32L08xxx] GPIO updates (HAL driver and associated validation test prg)
    • The GET_GPIO_SOURCE() macro is wrongly implemented
    • GPIO alternate functions defined in stm32l0xx_hal_gpio_ex.h not aligned with the spec
    • GPIO private Macro __HAL_GET_GPIO_SOURCE must be renamed GET_GPIO_SOURCE
  • HAL I2C update
    • New SYSCFG Define MACROs to manage FM+ on GPIOs
    • NACK is not treated during wait on flag treatment
  • HAL I2S update
    • I2S HAL_I2S_Transmit() API update to keep the check on busy flag only for the slave
    • I2S busy flag issue 
    • I2S Management of the bit ASTREN for the I2S various modes
  • HAL LCD update
    • LCD HD field initialization of LCD_FCR register is missing in HAL_LCD_init() function
  • HAL LPUART  update
    • HAL _DIV_LPUART macro possible value saturation 
    • LPUART CR3 register bit 11 must be kept at reset value.
  • HAL PWR update
    • Cortex SCR SLEEPONEXIT and SEVONPEND bits management
    • PWR PVD feature need falling/rising Event modes
    • PWR REGLPF and VOSF polling request
  • HAL RCC update
    • RCC Bug in HAL_RCC_GetSysClockFreq
    • Missing RCC IRQ handler for LSE CSS interrupt
    • Missing external macro __HAL_RCC_MCO_CONFIG
    • RCC Enable automatically backup domain
    • In HAL_RCCEx_PeriphCLKConfig, Reset backup domain only if RTC clock source has been changed
    • RCC update LSE_CONFIG to remove transaction LSE On to LSE Bypass
    • Issue on MSI setting
    • Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass
    • Rename HSI48_TIMEOUT_VALUE into RCC_HSI_TIMEOUT_VALUE
    • Add defines for RCC_System_Clock_Source_Status
    • New HAL RCC macro to configure the SYSCLK clock source
    • Wrong calculation of sysclk in case of PLL clocked by HSI_Div4
    • RCC_CRSStatusTypeDef must be typed uint32_t
    • RCC Implement workaround to cover RCC limitation regarding Peripheral enable delay
    • RCC issue in HAL_RCC_OscConfig when RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS
    • RCC Check if need to add interface HAL_RCCEx_GetPeriphCLKFreq
    • RCC Add a comment in the How to use section to mention the Peripheral enable delay
    • RCC Some values in MSIRangeTable are wrong
    • RCC missing macros to easily Enable/Disable HSI48(RC) clock for RNG analog config
    • RCC HSERDY must be checked even in HSE_BYPASS mode
    • RCC Improve HAL_RCC_OscCOnfig() function
  • HAL RNG update
    • RNG Type inconsistency of value returned by HAL_RNG_GetRandomNumber() and HAL_RNG_GetRandomNumber_IT() functions.
    • RNG Process lock and array of random numbers generation in interrupt mode
    • RNG Incorrect DRDY flag resetting
    • RNG Incorrect interrupt mode random number generation
    • RNG Incorrect TimeOut handling in polling mode random number generation
  • HAL RTC update
    • RTC macro __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG erroneous definition
    • RTC alignment of different HAL_RTC_XXIRQHandler() implementations 
    • RTC Bits Mask literals to be used in macro definition 
    • RTC macro __HAL_RTC_TAMPER_GET_IT() issue in param: __INTERRUPT__ @arg list
    • RTC wrong description of the subsecond item of RTC_TimeTypeDef structure in the header file
    • RTC WUTWF is not reliable
    • HAL_RTC_GetTime function does not return the actual  subfraction
    • [STM32L031xx/STM32L041xx] RTC macros renaming for RTC_OUTPUT_REMAP_XX and RTC_TIMESTAMPPIN_XX
    • Enhance @note describing the use of HAL RTC APIs 
  • HAL SPI update
    • SPI HAL_SPI_TransmitReceive_DMA() Remove DMA Tx Callback in case of RxOnly mode 
    • SPI HandleTypeDef.ErrorCode must be typed uint32_t
    • Warnings with True Studio IDE (tempreg variable not used)
  • HAL TIM update
    • TIM problem to use ETR as OCrefClear source
    • TIM Wrong remaping of the TIM2_ETR
    • TIM register BDTR does not exist
    • The assert on trigger polarity for TI1F_ED should be removed
    • TIM Add macros to ENABLE/DISABLE URS bit in TIM CR1 register
    • TIM HAL_TIM_OC_ConfigChannel() / HAL_TIM_PWM_ConfigChannel() Missed/Unused assert param to be added/removed
    • TIM Remove HAL_TIM_SlaveConfigSynchronization_DMA() from HAL_TIM API
    • TIM Trigger DMA request should be activated when working with a slave mode
    • TIM Timer Register Corruption using HAL_TIM_IC_ConfigChannel
    • TIM DMA transfer should be aborted when stopping a DMA burst
    • Add "TIM_CHANNEL_ALL" as an argument for all Encoder Start/Stop process in the comment section
    • HAL_TIM_DMADelayPulseCplt callback missing information
    • HAL_TIM_DMACaptureCplt callback missing information
    • TIM Trigger DMA request should be activated when working with a slave mode
    • TIM Trigger interrupt should be activated when working with a slave mode
    • __HAL_TIM_PRESCALER() shall be corrected: use '=' instead of '|='
  • HAL UART/USART update
    • UART Incorrect UART speed setting on HSI clock
    • Wrong Baud Rate calculation in case of OVER8
    • UART missing closing bracket in header file
    • UART Circular mode when transmitting data not well supported
    • UART/LPUART number of stop bits to correct
    • USART Incorrect number of stop bits definition
    • UART  HAL_UART_IRQHandler function not clearing correctly the interrupt flags
    • USART Setting of BRR register bit3:0 not inline with RM when OVER8 sampling mode is used
    • UART UART_WaitOnFlagUntilTimeout should not assign UART handle state to HAL_UART_STATE_TIMEOUT
    • USART Wrong values used as parameter of __HAL_USART_CLEAR_IT() in HAL_USART_IRQHandler()
    • USART BRR setting is wrong compared to Baudrate value
    • USART HAL_USART_Init() update to reach max frequencies (enable oversampling by 8)
    • USART USART_DMAReceiveCplt() Update to set the USART state after performing the test on it
    • UART The code associated to several macros need to be completed
    • USART UART DMA implementation issue: missed clear the TC bit in the SR
    • Wrong USART_IT_CM defined value
    • Issue with Lin mode data length
    • Wrong description for Interrupt mode IO operation within HAL UART driver
    • Change UART_DMATransmitCplt- new implementation to remove WaitOnFlag in ISR
    • Change UART TX-IT implementation to remove WaitOnFlag in ISR
    • The IS_UART_OVERSAMPLING(SAMPLING) is not called in UART_SetConfig()
    • HAL UART enhancement: remove the check on RXNE flag after reading the DR register
    • UART/USART/IRDA/SMARTCARD transmit process enhancement to use TXE instead of TC
    • Add MACRO to UART HAL to control CTS and RTS from the customer application
  • HAL PCD update
    • HAL_PCD_EP_Transmit() not functional
    • HAL PCD clear flag macros configuration
    • Bad IN/OUT EndPoint parameter array size
    • HAL PCD miss #define for ep0_mps parameter
    • USB HAL PCD missing #define PCD_SPEED_HIGH

V1.2.0 -/ 06-Feb-2015

-
Main -Changes
-
    -
  • HAL -has -been updated to support the STM32L071xx  STM32L072xx -STM32L073xx STM32L082xx STM32L083xx series
    • -
  • HAL Flash update
    -
    • -
      -
    • Flash -:  192K Dual Bank 
      • -
    -
  • HAL TIM update -: 
    • -
      -
    • Four -new instances  : TIM3, TIM7, TIM21, TIM22
      • -
    -
  • HAL USART update :
    • -
      -
    • Two -new instances : USART 4, USART 5
      • -
    -
  • HAL I2C update :
    • -
      -
    • One -new instance I2C3
      • -
    -
  • HAL GPIO update :
    • -
      -
    • GPIO -Port E
      • -
    -
  • HAL DAC update :
    • -
      -
    • A -second channel has been introduced
      • -
    -
  • HAL FIREWALL -introduction
    -
    • -
  • All -other HAL IPs -have also been updated in the context of the overall HAL alignment -effort of all the STM32 family
    • -
  • More -than 120 corrections have been implemented since the previous V1.1.0 -delivery
    -
    • -
  • Known limitations :
    • -
      -
    • Introduced -a FW patch to deactivate the HW SPI-V2.3 correction in case of I2S PCM -Short mode usage (Please refer to the STM32L073xx Errata Sheet for more -details). In this use case, we come back to the HW SPI 2.2 behavior -which is correct for the I2S PCM short mode
      • -
    -
-

V1.1.0 -/ 18-June-2014

-

Main -Changes

-
    -
  • - -

    HAL generic update
    -

    -
    • -
      -
    • Fix -flag clear procedure: use atomic write operation "=" -instead -of ready-modify-write operation "|=" or "&="
      • -
    • Fix -on Timeout management, Timeout value set to 0 passed to API -automatically exits the function after checking the flag without any -wait
      -
      • -
    • Common -update for -the following communication peripherals: SPI, UART, USART and IRDA -
      • -
        -
      • Add -DMA circular mode support
        -
        • -
      -
        -
      • Remove -lock from recursive process
        -
        • -
      -
    • Add -new macro __HAL_RESET_HANDLE_STATE to reset a given handle state
      • -
    -
      -
    • When -USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not -defined instead of being defined empty
      • -
    • Use -__IO const instead of -__I, to avoid any compilation issue when __cplusplus switch is defined
      • -
    • Add -new functions for the DBGMCU module
      • -
        -
      • HAL_EnableDBGSleepMode()
        • -
      • HAL_DisableDBGSleepMode()
        • -
      • HAL_EnableDBGStopMode()
        • -
      • HAL_DisableDBGStopMode()
        • -
      • HAL_EnableDBGStandbyMode()
        • -
      • HAL_DisableDBGStandbyMode()
        • -
      -
    • Miscellaneous -comments update
      • -
    -
  • - -

    HAL FLASH update

    -
      -
    • Add -new functions: HAL_FLASHEx_OB_SelectPCROP() -and HAL_FLASHEx_OB_DeSelectPCROP()
      • -
    • Some -functions was renamed and moved to the extension files -(stm32l0xx_hal_flash_ex.h/.c)
      -
      • -
        -
      • Rename -FLASH_HalfPageProgram() -into HAL_FLASHEx_HalfPageProgram()
        • -
      -
        -
      • Rename -FLASH_EnableRunPowerDown() -into HAL_FLASHEx_EnableRunPowerDown()
        • -
      -
        -
      • Rename -FLASH_DisableRunPowerDown() -into HAL_FLASHEx_DisableRunPowerDown()
        • -
      -
        -
      • Rename -all -HAL_DATA_EEPROMEx_xxx() functions into HAL_FLASHEx_DATAEEPROM_xxx()
        • -
      -
        -
      • Note: -aliases has been added to keep compatibility with previous version
        • -
      -
    -
    -
    • -
  • HAL GPIO update
    -
    • -
      -
    • Remove -IS_GET_GPIO_PIN -macro
      • -
    • Add -a new function HAL_GPIO_LockPin()
      • -
    • Private -Macro __HAL_GET_GPIO_SOURCE -renamed into GET_GPIO_SOURCE -
      -
      • -
    -
  • - -

    HAL DMA update
    -

    -
    • -
      -
    • Fix -in HAL_DMA_PollForTransfer() -to set error code HAL_DMA_ERROR_TE -in case of HAL_ERROR status
      • -
    -
-
- -
    -
  • HAL PWR update
    -
    • -
      -
    • HAL_PWR_PVDConfig(): -add clear of the EXTI trigger before new configuration
      -
      • -
    • Fix -in HAL_PWR_EnterSTANDBYMode() -to not clear Wakeup flag (WUF), which need to be cleared at application -level before to call this function
      -
      • -
    -
  • - -

    HAL RCC update
    -

    -
    • -
      -
    • Allow -to calibrate the HSI when it is used as system clock source
      -
      • -
    • Fix -implementation of IS_RCC_OSCILLATORTYPE() -macro
      -
      • -
    -
  • - -

    HAL ADC update
    -

    -
    • -
      -
    • Update -ADC internal channels mapping: TEMPSENSOR connected to ADC_CHANNEL_18 -and VLCD mapped to ADC_CHANNEL_16
      -
      • -
    • Skip -polling for ADRDY flag when Low Power Auto Off mode is enabled
      -
      • -
    -
  • - -

    HAL COMP update
    -

    -
      -
    • Add -LPTIMConnection -field in the COMP_InitTypeDef -structure.
      • -
    • Add -new defines: COMP_LPTIMCONNECTION_DISABLED, -COMP_LPTIMCONNECTION_ENABLED
      • -
    • Add -new macro IS_COMP_LPTIMCONNECTION
      • -
    -
    • -
  • - -

    HAL LPTIM update
    -

    -
    • -
      -
    • Add -CKPOL configuration -for encoder mode
      • -
    -
  • - -

    HAL WWDG update
    -

    -
    • -
      -
    • Miscellaneous -minor update on the source code
      • -
    -
  • - -

    HAL IWDG update
    -

    -
    • -
      -
    • Miscellaneous -minor update on the source code
      • -
    -
  • - -

    HAL CRC update
    -

    -
      -
    • Some -functions was renamed and moved to the extension files -(stm32l0xx_hal_crc_ex.h/.c)
      • -
        -
      • HAL_CRC_Input_Data_Reverse() -renamed into HAL_CRCEx_Input_Data_Reverse()
        • -
      -
        -
      • HAL_CRC_Output_Data_Reverse() -renamed into HAL_CRCEx_Output_Data_Reverse()
        • -
      -
        -
      • Note: -aliases has been added to keep compatibility with previous version
        • -
      -
    -
    • -
  • - -

    HAL CRYP update
    -

    -
      -
    • HAL_CRYP_ComputationCpltCallback() -renamed -into HAL_CRYPEx_ComputationCpltCallback() -and moved -to the extension files (stm32l0xx_hal_cryp_ex.h/.c)
      • -
    • Note: -alias has been added to keep compatibility with previous version
      • -
    -
    • -
  • - -

    HAL I2C update
    -

    -
    • -
      -
    • Add -management of NACK event in Master transmitter mode and Slave -transmitter/receiver modes (only in polling mode), in that case the -current transfer is stopped.
      • -
    -
  • - -

    HAL SMBUS update

    -
    • -
      -
    • Add -a new function: HAL_SMBUS_DisableListen_IT()
      -
      • -
    • Add -aliases for the following functions
      -
      • -
        -
      • #define -HAL_SMBUS_Slave_Listen_IT             -HAL_SMBUS_EnableListen_IT
        • -
      • #define -HAL_SMBUS_SlaveAddrCallback         -HAL_SMBUS_AddrCallback
        • -
      • #define -HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
        • -
      -
    • Add -alias HAL_SMBUS_STATE_SLAVE_LISTEN -for the constant HAL_SMBUS_STATE_LISTEN
      • -
    -
  • - -

    HAL UART update

    -
      -
    • HAL_UART_WakeupCallback() renamed -into HAL_UART_WakeupCallback() -and moved -to the extension files (stm32l0xx_hal_cryp_ex.h/.c)
      • -
    • -Add -new macros to control CTS and RTS
      -
      • -
    • Add -specific macros to manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_UART_CLEAR_PEFLAG()
        • -
      -
        -
      • __HAL_UART_CLEAR_FEFLAG()
        • -
      -
        -
      • __HAL_UART_CLEAR_NEFLAG()
        • -
      -
        -
      • __HAL_UART_CLEAR_OREFLAG()
        • -
      • __HAL_UART_CLEAR_IDLEFLAG()
        • -
      -
    • Add -several enhancements without affecting the driver functionalities
      • -
        -
      • Remove -the check on RXNE set after reading the Data in the DR register
        • -
      -
        -
      • Update -the transmit processes to use TXE instead of TC
        • -
      • Update -HAL_UART_Transmit_IT() -to enable UART_IT_TXE -instead of UART_IT_TC
        • -
      -
    -
    • -
  • - -

    HAL USART update
    -

    -
    • -
      -
    • Add -specific macros to manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_USART_CLEAR_PEFLAG()
        • -
      -
        -
      • __HAL_USART_CLEAR_FEFLAG()
        • -
      -
        -
      • __HAL_USART_CLEAR_NEFLAG()
        • -
      -
        -
      • __HAL_USART_CLEAR_OREFLAG()
        • -
      -
        -
      • __HAL_USART_CLEAR_IDLEFLAG()
        • -
      -
    • Update -HAL_USART_Transmit_IT() -to enable USART_IT_TXE -instead of USART_IT_TC
      • -
    -
  • - -

    HAL IRDA update
    -

    -
      -
    • Add -specific macros to manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_IRDA_CLEAR_PEFLAG()
        • -
      • __HAL_ -IRDA _CLEAR_FEFLAG()
        • -
      • __HAL_ -IRDA _CLEAR_NEFLAG()
        • -
      • __HAL_ -IRDA _CLEAR_OREFLAG()
        • -
      • __HAL_ IRDA _CLEAR_IDLEFLAG()
        • -
      -
    • Add -several enhancements without affecting the driver functionalities
      • -
        -
      • Remove -the check on RXNE set after reading the Data in the DR register
        -
        • -
      • Update -HAL_IRDA_Transmit_IT() -to enable IRDA_IT_TXE -instead of IRDA_IT_TC
        • -
      -
    • Add -the following APIs used within DMA process
      • -
        -
      • HAL_StatusTypeDef -HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
        • -
      -
        -
      • HAL_StatusTypeDef -HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
        • -
      • HAL_StatusTypeDef -HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
        • -
      • void -HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
        • -
      • void -HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
        • -
      -
    -
    • -
  • - -

    HAL SMARTCARD update
    -

    -
    • -
      -
    • Add -specific macros to manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_SMARTCARD_CLEAR_PEFLAG()
        • -
      -
        -
      • __HAL_SMARTCARD_CLEAR_FEFLAG()
        • -
      -
        -
      • __HAL_SMARTCARD_CLEAR_NEFLAG()
        • -
      -
        -
      • __HAL_SMARTCARD_CLEAR_OREFLAG()
        • -
      -
        -
      • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
        • -
      -
    • Add -several enhancements without affecting the driver functionalities
      • -
        -
      • Add -a new state HAL_SMARTCARD_STATE_BUSY_TX_RX -and all processes has been updated accordingly
        • -
      -
        -
      • Update -HAL_SMARTCARD_Transmit_IT() -to enable SMARTCARD_IT_TXE -instead of SMARTCARD_IT_TC
        • -
      -
    -
-
- -
    -
  • HAL SPI update
    • -
      -
    • Bugs -fix
      • -
        -
      • SPI -interface is used in synchronous polling mode: at high clock rates like -SPI prescaler 2 and 4, calling
        -HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT
        • -
      • HAL_SPI_TransmitReceive_DMA() -does not clean up the TX DMA, so any subsequent SPI calls return the -DMA error
        • -
      • HAL_SPI_Transmit_DMA() -is failing when data size is equal to 1 byte
        • -
      -
    • Add -the following APIs used within the DMA process
      • -
    -
      -
        -
      • HAL_StatusTypeDef -HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
        • -
      -
        -
      • HAL_StatusTypeDef -HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
        • -
      -
        -
      • HAL_StatusTypeDef -HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
        • -
      -
        -
      • void -HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • -
      -
        -
      • void -HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • -
      -
        -
      • void -HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • -
      -
    -
  • - -

    HAL TSC update

    -
    • -
      -
    • - -

      Fix -value of the constant TSC_ACQ_MODE_SYNCHRO

      -
      • -
    -
  • - -

    HAL PCD update

    -
    • -
      -
    • - -

      Add -new macro __HAL_USB_EXTI_GENERATE_SWIT()

      -
      • -
    -
-

V1.0.0 -/ 22-April-2014

-

Main -Changes

-First -official release.
- -

License

-
-
Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
    -
  1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
    2. -
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
    3. -
  3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived
    -
    4. -
-       -from this software without specific prior written permission.
-
-THIS -SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGE.
-
- -
-
-

For -complete documentation on STM32 Microcontrollers visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h index 597d1f70f9..037d6fa059 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rtc.h @@ -43,6 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" +#include "stm32l0xx_ll_rtc.h" /** @addtogroup STM32L0xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/Release_Notes_stm32l1xx_hal.html b/targets/TARGET_STM/TARGET_STM32L1/device/Release_Notes_stm32l1xx_hal.html deleted file mode 100644 index fa0f5c64ff..0000000000 --- a/targets/TARGET_STM/TARGET_STM32L1/device/Release_Notes_stm32l1xx_hal.html +++ /dev/null @@ -1,1004 +0,0 @@ - - - - - - - - -Release Notes for STM32L1xx HAL Drivers - -
-

 

-
- - - - -
- - - - - - - -
-

Back to Release page

-
-

Release Notes for STM32L1xx HAL Drivers

-

Copyright -2016 STMicroelectronics

-

-
-

 

- - - - -
-

Update History

V1.2.0 / 01-July-2016

- -

Main Changes

  • First official release supporting the Low Level drivers for the STM32L1xx family: 
    • Low -Layer drivers APIs provide register level programming: they require -deep knowledge of peripherals described in STM32L1xx Reference Manual.
    • Low -Layer drivers are available for: ADC, COMP, CORTEX, CRC, DAC, DMA, -EXTI, GPIO, I2C, IWDG, OPAMP, PWR, RCC, RTC, SPI, TIM, -USART, WWDG peripherals and additional Low Level Bus, System and -Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l1xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l1xx_ll_ppp.h file must be included in user code.

List of HAL updates or corrections provided by this release:

  • Generic updates:
    • Update HAL drivers to apply MISRA C 2004 rule 10.6.
    • uwTick must be global and not static to allow overwrite of HAL_IncTick()
  • ADC:
    • Clear -the bit OVR (overrun) in addition to EOC (end of conversion) -inside HAL_ADC_Start, HAL_ADC_Start_IT and HAL_ADC_Start_DMA.
  • CRC:
    • HAL_CRC_DeInit() resets CRC_IDR register to reset value.
  • DMA:
    • Add function HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma).
      • This function aborts the DMA Transfer in Interrupt mode.
    • Add macro __HAL_DMA_GET_COUNTER
      • This macro permits to get the number of remaining data units in the current DMAy Channelx transfer.
    • Global driver code optimization to reduce memory footprint 
  • FLASH:
    • Correct -MISRA 10.3 Error[Pm069]: if identifiers are given for any of the -parameters, then the identifiers used in the declaration and definition -shall be identical (MISRA C 2004 rule 16.4).
  • GPIO:
    • IS_GPIO_PIN is more robust.
  • I2C:
    • WaitOnFlag is optimized to effectively last until the expected timeout of a transfer.
    • Optimisation of the IRQHandler.
    • Rework DMA end process and I2C error management during DMA transfer.
    • HAL_I2C_Master_Transmit_DMA now returns an error in case of communication error.
    • Add support for repeated start feature.
  • IWDG:
    • New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() -and HAL_IWDG_GetState() APIs
      • API functions are: 
        • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG -counter
        • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
      • Refer to the following example to identify the changes: IWDG_Example
  • PWR:
    • Add new interface HAL_FLASHEx_GetError.
    • Add constant FLASH_SIZE.
    • Use suffix U for all the defines.
    • HAL_PWREx_DisableLowPowerRunMode now returns HAL_StatusTypeDef instead of void.
    • SB and ADDR are now managed in interrupt mode, not in polling.
    • Add DMA abort treatment
  • RCC:
    • Rework the correction from V1.1.3:
      • Backup domain are no more reseted when RTC clock source is changed from reset value.
  • RTC:
    • Updated HAL_RTCEx_SetWakeUpTimer_IT() function by adding clear of Wake-Up flag before enabling the interrupt.
  • SPI:
    • Correct MISRA 5.2 "tmpreg" variable shall not be used inside MACRO.
    • In the SPI_HandleTypeDef structure, RxXferCount and TxXferCount are now __IO.
    • Clear the OVR flag before a new transfer.
  • TIMER:
    • Correct the description of the function HAL_TIM_PWM_Start_IT.
      • The parameter Channel mentions the channel to be enabled and not the one to be disabled.
  • WWDG:
    • New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() -and HAL_WWDG_GetState() APIs
      • Update HAL_WWDG_Refresh() API to remove counter parameter
      • New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt
      • API -functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), -HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()

V1.1.3 / 04-March-2016

- -

Main Changes

  • Maintenance release to fix known defects and enhancements implementation.
  • Generic update:
    • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers.
    • Improve the update of the SystemCoreClock variable within the HAL Driver.
    • Split aAPBAHBPrescTable into aAHBPrescTable and aAPBPrescTable.
    • Reduce HSE_STARTUP_TIMEOUT from 5s to 100ms.
    • Reduce MSI_TIMEOUT_VALUE from 100ms to 2ms.
    • Reduce HSI_TIMEOUT_VALUE from 100ms to 2ms.
    • Reduce LSI_TIMEOUT_VALUE from 100ms to 2ms.
    • Reduce PLL_TIMEOUT_VALUE from 100ms to 2ms.
  • CORTEX:
    • __HAL_CORTEX_SYSTICKCLK_CONFIG is now deprecated. Prefer using HAL_SYSTICK_CLKSourceConfig function.
  • FLASH:
    • Correct issue preventing Cat.1 devices to write data in EEPROM.
  • I2C:
    • Add NACK management during wait on flag treatment.
    • Update the state machine.
    • It is now possible to use the I2C transmission with a data size of 0.
  • RCC:
    • Optimize HAL_RCC_ClockConfig.
    • LSEON is reset only if required inside HAL_RCC_OscConfig.
    • RCC HSE pre-scaler reconfiguration for LCD/RTC peripherical is now possible.
    • Backup domain are no more reseted when RTC clock source is changed from reset value.
  • SMARTCARD:
    • Update description of GuardTime and Prescaler fields in SMARTCARD_InitTypeDef structure.
  • UART:
    • HAL_LIN_SendBreak() now use IS_UART_LIN_INSTANCE instead of IS_UART_INSTANCE.
    • Correct the UART_BRR_SAMPLING8 macro in the case of cary handling.

V1.1.2 / 09-October-2015

- -

Main Changes

  • Maintenance release to fix known defects and enhancements implementation.
  • ADC:
    • The ADC internal macro "IS_ADC_RANGE" is modified to take into account the ADC resolution.
    • The function HAL_ADC_PollForEvent, in case of timeout, returns HAL_TIMEOUT instead of HAL_ERROR.
    • HAL_ADC_Init -set the ADC handle in state HAL_ADC_ERROR_INTERNAL if the user try to -initialize the ADC in DiscontinuousConvMode and ContinuousConvMode -simultaneously, which is not possible.
    • Enhance the check for ScanConvMode in HAL_ADC_Init.
  • Cortex:
    • Corrected Misra error (MISRA C 2004 rule 10.5).
  • CRC:
    • Corrected the macro __HAL_CRC_SET_IDR.
  • GPIO:
    • corrected the macro GPIO_GET_INDEX.
    • To insure the same naming accross all STM32 families (F4, F2, F0, F1, L1 etc):
      • Replacing GPIO_SPEED_VERY_LOW by GPIO_SPEED_FREQ_LOW.
      • Replacing GPIO_SPEED_LOW by GPIO_SPEED_FREQ_MEDIUM.
      • Replacing GPIO_SPEED_MEDIUM by GPIO_SPEED_FREQ_HIGH.
      • Replacing GPIO_SPEED_HIGH by GPIO_SPEED_FREQ_VERY_HIGH.
  • IRDA:
    • Corrected the HAL_IRDA_IRQHandler which was preventing to handle 2 simultaneous errors.
  • I2C:
    • Corrected an issue where the STOP bit was not cleared after reading data depending on APB/I2C frequency.
  • I2S:
    • HAL_I2S_Transmit() is updated to keep the check on busy flag only for the slave.
  • PCD
    • Corrected issue when using USB Device double-buffering mode for IN endpoints.
    • do{ ... } while(0) is used for multi statement macros.
  • PWR:
    • Corrected Misra error (MISRA C 2004 rule 14.3).
  • RCC:
    • In HAL_RCCEx_PeriphCLKConfig, the reset of the backup domain occurs only if the RTC clock source has been changed.
    • __HAL_RCC_HSE_CONFIG is updated to remove the transition from RCC_HSE_ON to RCC_HSE_BYPASS.
    • Adding the macro __HAL_RCC_MCO1_CONFIG to configure the MCO clock.
    • Adding the macros and function to handle LSE CSS interrupt.
    • Corrected an error in HAL_RCC_GetSysClockFreq when the PLL is used as system clock. An incorrect sysclockfreq was returned.
  • RTC:
    • RTC_TimeTypeDef.SecondFraction -field is added to specifies the range or granularity of Sub Second -register content.This field will be used only by HAL_RTC_GetTime -function.
    • HAL_RTC_GetTime is updated to take into account the new field RTC_TimeTypeDef.SecondFraction.
    • Corrected error in __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG macro.
    • Add additionnal checks on WUTWF flag in HAL_RTCEx_SetWakeUpTimer_IT.
    • do{ ... } while(0) is used for multi statement macros.
  • USART:
    • Corrected the HAL_USART_IRQHandler which was preventing to handle 2 simultaneous errors.
  • UART:
    • Removed -the activation of  ERR IT  from HAL_UART_Transmit_IT() which -was leading to HAL_UART_IRQ_Handler wrong behavior.
    • Corrected the HAL_UART_IRQHandler which was preventing to handle 2 simultaneous errors.
  • SMARTCARD:
    • Corrected the HAL_SMARTCARD_IRQHandler which was preventing to handle 2 simultaneous errors.

V1.1.1 / 31-March-2015

- -

Main Changes

  • Include path changes for compilation under Unix environment.
  • Update drivers to be C++ compliant.

Interface Changes

  • CORTEX : 
    • Added interface to access MPU features (refer to stm32l1xx_hal_cortex.h)
  • CRYP : 
    • Added Instance field in CRYP_HandleTypeDef.
      • HAL CRYP driver - updated to support multi instance, so user must ensure that the new - parameter Instance is initialized in his application(CRYPHandle.Instance - = CRYP)
  • FLASH : 
    • Changing field name of NOR_CFITypeDef (CFI1X changed to CFI1_X)
  • PCD :
    • HAL_PCD_ActiveRemoteWakeup renamed HAL_PCD_ActivateRemoteWakeup
    • HAL_PCD_DeActiveRemoteWakeup renamed to HAL_PCD_DeActivateRemoteWakeup
  • PWR :
    • HAL_PWR_PVDConfig renamed HAL_PWR_ConfigPVD
    • Added new interfaces:
  • void HAL_PWR_EnableSleepOnExit(void);
  • void HAL_PWR_DisableSleepOnExit(void);
  • void HAL_PWR_EnableSEVOnPend(void);
  • void HAL_PWR_DisableSEVOnPend(void);
  • void HAL_PWR_EnableSleepOnExit(void);
  • uint32_t HAL_PWREx_GetVoltageRange(void);
  • RCC :
    • HAL_RCC_CCSCallback renamed to HAL_RCC_CSSCallback
    • Adding HAL_RCCEx_GetPeriphCLKFreq interface.
  • PCD: 
    • HAL_PCD_ActiveRemoteWakeup renamed HAL_PCD_ActivateRemoteWakeup
    • HAL_PCD_DeActiveRemoteWakeup renamed to HAL_PCD_DeActivateRemoteWakeup
  • SMARTCARD: 
    • Removal of HAL_SMARTCARD_ReInit interface.
  • SPI: 
    • HAL_SPI_GetError now returns a uint32_t instead of HAL_SPI_ErrorTypeDef.
  • TIMER: 
    • Adding interface HAL_TIM_SlaveConfigSynchronization_IT
  • UART: 
    • The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.
  • USART: 
    • The field ErrorCode of UART_HandleTypeDef is changed from HAL_UART_ErrorTypeDef to uint32_t.

V1.1.0 / 16-January-2015

- -

Main Changes

- - - - - - -
    -
  • Add support of new STM32L1 eXtended devices - STM32l151xDX, STM32l152xDX & STM32l62xDX
  • HAL generic : Add eXtended Devices switchs when needed 
    • STM32L151xDX has same features than STM32L151xE
    • STM32L152xDX has same features than STM32L152xE
    • STM32L162xDX has same features than STM32L162xE
  • HAL FLASH : 
    • add support of new STM32L1 Devices (same as other HAL)
    • stm32l1xx_hal_flash_ex.c -: Specific treatment done in  HAL_FLASHEx_Erase & -HAL_FLASHEx_Erase_IT as memory is not continuous between 2 banks, user -should perform pages erase by bank only

V1.0.0 / 05-September-2014

- -

Main Changes

- - - - - - -
  • First official release
- - - - - - -

License

-
-
-Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
    -     -
-        from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -
-
- -
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For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

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- \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.h index 3b9b08ac5c..231511cc0c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.h @@ -43,6 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l1xx_hal_def.h" +#include "stm32l1xx_ll_rtc.h" /** @addtogroup STM32L1xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h index 54301edf3b..c7842cff3a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h @@ -159,15 +159,6 @@ typedef enum { SYS_WKUP1 = PA_0, SYS_WKUP4 = PA_2, - /**** QSPI pins ****/ - QSPI1_IO0 = PB_1, - QSPI1_IO1 = PB_0, - QSPI1_IO2 = PA_7, - QSPI1_IO3 = PA_6, - QSPI1_SCK = PA_3, - QSPI1_CSN = PA_2, - - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h index 93a019ca94..9cc9fcf3de 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h @@ -236,14 +236,6 @@ typedef enum { SYS_WKUP2 = PC_13, SYS_WKUP4 = PA_2, - /**** QSPI pins ****/ - QSPI1_IO0 = PB_1, - QSPI1_IO1 = PB_0, - QSPI1_IO2 = PA_7, - QSPI1_IO3 = PA_6, - QSPI1_SCK = PB_10, - QSPI1_CSN = PB_11, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h index 3a80beb4c8..aac6e58d1a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h @@ -258,21 +258,13 @@ typedef enum { SYS_WKUP4 = PA_2, SYS_WKUP5 = PC_5, - /**** QSPI pins ****/ - QSPI1_IO0 = PE_12, - QSPI1_IO1 = PE_13, - QSPI1_IO2 = PE_14, - QSPI1_IO3 = PE_15, - QSPI1_SCK = PE_10, - QSPI1_CSN = PE_11, - /**** QSPI FLASH pins ****/ - QSPI_FLASH1_IO0 = QSPI1_IO0, - QSPI_FLASH1_IO1 = QSPI1_IO1, - QSPI_FLASH1_IO2 = QSPI1_IO2, - QSPI_FLASH1_IO3 = QSPI1_IO3, - QSPI_FLASH1_SCK = QSPI1_SCK, - QSPI_FLASH1_CSN = QSPI1_CSN, + QSPI_FLASH1_IO0 = PE_12, + QSPI_FLASH1_IO1 = PE_13, + QSPI_FLASH1_IO2 = PE_14, + QSPI_FLASH1_IO3 = PE_15, + QSPI_FLASH1_SCK = PE_10, + QSPI_FLASH1_CSN = PE_11, // Not connected NC = (int)0xFFFFFFFF diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h index 2300627c5b..eca82d5fdc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralNames.h @@ -84,7 +84,7 @@ typedef enum { } CANName; typedef enum { - QSPI_1 = (int)QSPI_BASE + QSPI_1 = (int)QSPI_R_BASE } QSPIName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h index 2300627c5b..eca82d5fdc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralNames.h @@ -84,7 +84,7 @@ typedef enum { } CANName; typedef enum { - QSPI_1 = (int)QSPI_BASE + QSPI_1 = (int)QSPI_R_BASE } QSPIName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h index a2d80f0942..870ef09dda 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h @@ -86,7 +86,7 @@ typedef enum { } CANName; typedef enum { - QSPI_1 = (int)QSPI_BASE + QSPI_1 = (int)QSPI_R_BASE } QSPIName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c index 6b99293215..f387c292dc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c @@ -431,23 +431,11 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 [MX25R6435FM2IL0_SIO1] {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 [MX25R6435FM2IL0_SIO0] {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [MX25R6435FM2IL0_CS] - {PC_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to ADCx_IN2 - {PC_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to DF_CKOUT - {PC_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to ARD_A2 - {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to ARD_A0 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3 - {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS - {PD_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to OE [OE_IS66WV51216EBLL] - {PD_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to WE [WE_IS66WV51216EBLL] -// {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_IO1 // Connected to STDIO_UART_RX -// {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 // Connected to STDIO_UART_RX - {PD_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 // Connected to LCD_NE {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to D8 [D8_IS66WV51216EBLL] {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to D9 [D9_IS66WV51216EBLL] {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to D10 [D10_IS66WV51216EBLL] {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to D11 [D11_IS66WV51216EBLL] {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to D12 [D12_IS66WV51216EBLL] - {PH_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, // QUADSPI_BK2_IO0 // Connected to STMOD_INT {NC, NC, 0} }; @@ -462,8 +450,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { // {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to STDIO_UART_TX {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [MX25R6435FM2IL0_CS] - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS // Connected to uSD_D3 - {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to D8 [D8_IS66WV51216EBLL] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h index b60b0ec151..d1eaefc41e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h @@ -346,8 +346,8 @@ typedef enum { QSPI_FLASH1_IO1 = PB_0, QSPI_FLASH1_IO2 = PA_7, QSPI_FLASH1_IO3 = PA_6, - QSPI_FLASH1_SCK = PB_11, - QSPI_FLASH1_CSN = PA_3, + QSPI_FLASH1_SCK = PA_3, + QSPI_FLASH1_CSN = PB_11, // Not connected NC = (int)0xFFFFFFFF diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h index 73046c23d4..e0bbc501e0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h @@ -86,7 +86,7 @@ typedef enum { } CANName; typedef enum { - QSPI_1 = (int)QSPI_BASE + QSPI_1 = (int)QSPI_R_BASE } QSPIName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c index 0c36de6fe9..b9144f054f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c @@ -419,17 +419,6 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Only STM32L496ZG, not STM32L496ZG-P - {PC_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 - {PC_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 - {PC_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 - {PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS - {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS - {PD_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 - {PD_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 - {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_IO1 - {PD_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 - {PD_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 @@ -453,8 +442,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Only STM32L496ZG, not STM32L496ZG-P - {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // QUADSPI_BK2_NCS - {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_NCS {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h index 9a85d7bdb0..e828b5e57e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h @@ -317,14 +317,6 @@ typedef enum { SYS_WKUP4 = PA_2, SYS_WKUP5 = PC_5, - /**** QSPI pins ****/ - QSPI1_IO0 = PE_12, - QSPI1_IO1 = PB_0, - QSPI1_IO2 = PE_14, - QSPI1_IO3 = PE_15, - QSPI1_SCK = PB_10, - QSPI1_CSN = PA_2, - // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h index ece5f1679f..cd0f1a783c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h @@ -58,6 +58,16 @@ struct trng_s { RNG_HandleTypeDef handle; }; +struct qspi_s { + QSPI_HandleTypeDef handle; + PinName io0; + PinName io1; + PinName io2; + PinName io3; + PinName sclk; + PinName ssel; +}; + #include "common_objects.h" #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h index ed269a98ca..25f40e0447 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rtc.h @@ -43,6 +43,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l4xx_hal_def.h" +#include "stm32l4xx_ll_rtc.h" /** @addtogroup STM32L4xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index aee7229eb0..d8704faa56 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -38,6 +38,10 @@ #include "lp_ticker_api.h" #include "mbed_error.h" +#if !defined(LPTICKER_DELAY_TICKS) || (LPTICKER_DELAY_TICKS < 3) +#warning "lpticker_delay_ticks value should be set to 3" +#endif + LPTIM_HandleTypeDef LptimHandle; const ticker_info_t *lp_ticker_get_info() @@ -135,10 +139,10 @@ void lp_ticker_init(void) LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; -#if (TARGET_STM32L4) +#if defined (LPTIM_INPUT1SOURCE_GPIO) /* STM32L4 */ LptimHandle.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO; LptimHandle.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO; -#endif /* TARGET_STM32L4 */ +#endif /* LPTIM_INPUT1SOURCE_GPIO */ if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK) { error("HAL_LPTIM_Init ERROR\n"); @@ -147,7 +151,7 @@ void lp_ticker_init(void) NVIC_SetVector(LPTIM1_IRQn, (uint32_t)LPTIM1_IRQHandler); -#if !(TARGET_STM32L4) +#if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT) /* EXTI lines are not configured by default */ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); @@ -155,6 +159,12 @@ void lp_ticker_init(void) __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPM); HAL_LPTIM_Counter_Start(&LptimHandle, 0xFFFF); + + /* Need to write a compare value in order to get LPTIM_FLAG_CMPOK in set_interrupt */ + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK); + __HAL_LPTIM_COMPARE_SET(&LptimHandle, 0); + while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) { + } } static void LPTIM1_IRQHandler(void) @@ -180,7 +190,8 @@ static void LPTIM1_IRQHandler(void) } } -#if !(TARGET_STM32L4) +#if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG) + /* EXTI lines are not configured by default */ __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); #endif } @@ -201,12 +212,12 @@ void lp_ticker_set_interrupt(timestamp_t timestamp) LptimHandle.Instance = LPTIM1; irq_handler = (void (*)(void))lp_ticker_irq_handler; - __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK); - __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp); /* CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed */ /* Any successive write before the CMPOK flag be set, will lead to unpredictable results */ - while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) { - } + /* LPTICKER_DELAY_TICKS value prevents OS to call this set interrupt function before CMPOK */ + MBED_ASSERT(__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == SET); + __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK); + __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp); lp_ticker_clear_interrupt(); diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 4166cef34e..71c61a28c2 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -32,7 +32,7 @@ int mbed_sdk_inited = 0; // This function is called after RAM initialization and before main. void mbed_sdk_init() { -#if TARGET_STM32F7 +#if defined(__ICACHE_PRESENT) /* STM32F7 */ // The mbed_sdk_init can be called either during cold boot or during // application boot after bootloader has been executed. // In case the bootloader has already enabled the cache, @@ -43,7 +43,7 @@ void mbed_sdk_init() if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) == 0) { // If DCache is disabled SCB_EnableDCache(); } -#endif /* TARGET_STM32F7 */ +#endif /* __ICACHE_PRESENT */ // Update the SystemCoreClock variable. SystemCoreClockUpdate(); diff --git a/targets/TARGET_STM/pwmout_api.c b/targets/TARGET_STM/pwmout_api.c index e94b0628b4..621607a4c8 100644 --- a/targets/TARGET_STM/pwmout_api.c +++ b/targets/TARGET_STM/pwmout_api.c @@ -182,7 +182,7 @@ void pwmout_write(pwmout_t *obj, float value) value = 1.0; } - obj->pulse = (uint32_t)((float)obj->period * value); + obj->pulse = (uint32_t)((float)obj->period * value + 0.5); // Configure channels sConfig.OCMode = TIM_OCMODE_PWM1; diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index da8570c026..937dee12d5 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -192,11 +192,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN obj->ssel = ssel; pinmap_pinout(ssel, PinMap_QSPI_SSEL); - if (HAL_QSPI_Init(&obj->handle) != HAL_OK) { - return QSPI_STATUS_ERROR; - } - qspi_frequency(obj, hz); - return QSPI_STATUS_OK; + return qspi_frequency(obj, hz); } qspi_status_t qspi_free(qspi_t *obj) @@ -228,18 +224,29 @@ qspi_status_t qspi_frequency(qspi_t *obj, int hz) { qspi_status_t status = QSPI_STATUS_OK; - // HCLK drives QSPI + /* HCLK drives QSPI. QSPI clock depends on prescaler value: + * 0: Freq = HCLK + * 1: Freq = HCLK/2 + * ... + * 255: Freq = HCLK/256 (minimum value) + */ + int div = HAL_RCC_GetHCLKFreq() / hz; - if (div > 256 || div < 1) { - status = QSPI_STATUS_INVALID_PARAMETER; - return status; + if (div > 255) { + div = 255; + } + else { + if ((HAL_RCC_GetHCLKFreq() % hz) == 0) { + div = div - 1; + } } - obj->handle.Init.ClockPrescaler = div - 1; + obj->handle.Init.ClockPrescaler = div; if (HAL_QSPI_Init(&obj->handle) != HAL_OK) { status = QSPI_STATUS_ERROR; } + return status; } @@ -253,11 +260,11 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { status = QSPI_STATUS_ERROR; - return status; } - - if (HAL_QSPI_Transmit(&obj->handle, (uint8_t *)data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - status = QSPI_STATUS_ERROR; + else { + if (HAL_QSPI_Transmit(&obj->handle, (uint8_t *)data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + status = QSPI_STATUS_ERROR; + } } return status; @@ -273,11 +280,11 @@ qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { status = QSPI_STATUS_ERROR; - return status; } - - if (HAL_QSPI_Receive(&obj->handle, data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - status = QSPI_STATUS_ERROR; + else { + if (HAL_QSPI_Receive(&obj->handle, data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + status = QSPI_STATUS_ERROR; + } } return status; diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 7895a4c5f9..e28a311b84 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -93,6 +93,10 @@ void rtc_init(void) // Enable RTC __HAL_RCC_RTC_ENABLE(); +#if defined __HAL_RCC_RTCAPB_CLK_ENABLE /* part of STM32L4 */ + __HAL_RCC_RTCAPB_CLK_ENABLE(); +#endif /* __HAL_RCC_RTCAPB_CLK_ENABLE */ + RtcHandle.Instance = RTC; RtcHandle.State = HAL_RTC_STATE_RESET; @@ -105,6 +109,12 @@ void rtc_init(void) RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; +#if defined (RTC_OUTPUT_REMAP_NONE) + RtcHandle.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; +#endif /* defined (RTC_OUTPUT_REMAP_NONE) */ +#if defined (RTC_OUTPUT_PULLUP_NONE) + RtcHandle.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; +#endif /* defined (RTC_OUTPUT_PULLUP_NONE) */ #endif /* TARGET_STM32F1 */ if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { @@ -257,11 +267,11 @@ void rtc_write(time_t t) int rtc_isenabled(void) { -#if !(TARGET_STM32F1) - return ((RTC->ISR & RTC_ISR_INITS) == RTC_ISR_INITS); -#else /* TARGET_STM32F1 */ +#if defined (RTC_FLAG_INITS) /* all STM32 except STM32F1 */ + return LL_RTC_IsActiveFlag_INITS(RTC); +#else /* RTC_FLAG_INITS */ /* TARGET_STM32F1 */ return ((RTC->CRL & RTC_CRL_RSF) == RTC_CRL_RSF); -#endif /* TARGET_STM32F1 */ +#endif /* RTC_FLAG_INITS */ } @@ -296,7 +306,9 @@ static void RTC_IRQHandler(void) } } +#ifdef __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); +#endif } uint32_t rtc_read_lp(void) @@ -341,25 +353,60 @@ uint32_t rtc_read_lp(void) void rtc_set_wake_up_timer(timestamp_t timestamp) { + /* RTC periodic auto wake up timer is used + * This WakeUpTimer is loaded to an init value => WakeUpCounter + * then timer starts counting down (even in low-power modes) + * When it reaches 0, the WUTF flag is set in the RTC_ISR register + */ uint32_t WakeUpCounter; - uint32_t current_lp_time; + uint32_t WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV4; - current_lp_time = rtc_read_lp(); + core_util_critical_section_enter(); + /* MBED API gives the timestamp value to set + * WakeUpCounter is then the delta between timestamp and the current tick (LPTICKER_counter) + * If the current tick preceeds timestamp value, max U32 is added + */ + uint32_t current_lp_time = rtc_read_lp(); if (timestamp < current_lp_time) { WakeUpCounter = 0xFFFFFFFF - current_lp_time + timestamp; } else { WakeUpCounter = timestamp - current_lp_time; } + /* RTC WakeUpCounter is 16 bits + * Corresponding time value depends on WakeUpClock + * - RTC clock divided by 4 : max WakeUpCounter value is 8s (precision around 122 us) + * - RTC clock divided by 8 : max WakeUpCounter value is 16s (precision around 244 us) + * - RTC clock divided by 16 : max WakeUpCounter value is 32s (precision around 488 us) + * - 1 Hz internal clock 16b : max WakeUpCounter value is 18h (precision 1 s) + * - 1 Hz internal clock 17b : max WakeUpCounter value is 36h (precision 1 s) + */ if (WakeUpCounter > 0xFFFF) { - WakeUpCounter = 0xFFFF; + WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV8; + WakeUpCounter = WakeUpCounter / 2; + + if (WakeUpCounter > 0xFFFF) { + WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV16; + WakeUpCounter = WakeUpCounter / 2; + + if (WakeUpCounter > 0xFFFF) { + /* Tick value needs to be translated in seconds : TICK * 16 (previous div16 value) / RTC clock (32768) */ + WakeUpClock = RTC_WAKEUPCLOCK_CK_SPRE_16BITS; + WakeUpCounter = WakeUpCounter / 2048; + + if (WakeUpCounter > 0xFFFF) { + /* In this case 2^16 is added to the 16-bit counter value */ + WakeUpClock = RTC_WAKEUPCLOCK_CK_SPRE_17BITS; + WakeUpCounter = WakeUpCounter - 0x10000; + } + } + } } - core_util_critical_section_enter(); RtcHandle.Instance = RTC; HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle); - if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, WakeUpCounter, RTC_WAKEUPCLOCK_RTCCLK_DIV4) != HAL_OK) { + if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, WakeUpCounter, WakeUpClock) != HAL_OK) { error("rtc_set_wake_up_timer init error\n"); } diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index 99dc8a6216..28235e486a 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -51,56 +51,38 @@ static void wait_loop(uint32_t timeout) } -// On L4 platforms we've seen unstable PLL CLK configuraiton -// when DEEP SLEEP exits just few µs after being entered -// So we need to force MSI usage before setting clocks again static void ForcePeriphOutofDeepSleep(void) { uint32_t pFLatency = 0; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; -#if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */ /* Get the Clocks configuration according to the internal RCC registers */ HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency); - // Select HSI ss system clock source as a first step -#ifdef RCC_CLOCKTYPE_PCLK2 - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; -#else - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK - | RCC_CLOCKTYPE_PCLK1); -#endif - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) { - error("clock issue\r\n"); - } -#else /* HSI used on others */ - /* Get the Clocks configuration according to the internal RCC registers */ - HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency); - - /**Initializes the CPU, AHB and APB busses clocks - */ #ifdef RCC_CLOCKTYPE_PCLK2 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; -#else +#else /* RCC_CLOCKTYPE_PCLK2 */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1); -#endif +#endif /* RCC_CLOCKTYPE_PCLK2 */ + +#if defined (RCC_SYSCLKSOURCE_MSI) /* STM32Lx */ + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; +#else /* defined RCC_SYSCLKSOURCE_MSI */ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; +#endif /* defined RCC_SYSCLKSOURCE_MSI */ + + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) { - error("clock issue"); + error("ForcePeriphOutofDeepSleep clock issue\r\n"); } -#endif // TARGET_STM32L4 } + static void ForceOscOutofDeepSleep(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -111,39 +93,24 @@ static void ForceOscOutofDeepSleep(void) /* Get the Oscillators configuration according to the internal RCC registers */ HAL_RCC_GetOscConfig(&RCC_OscInitStruct); -#if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */ - /**Initializes the CPU, AHB and APB busses clocks - */ +#if defined (RCC_SYSCLKSOURCE_MSI) /* STM32Lx */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; // Intermediate freq, 1MHz range RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("clock issue\r\n"); - } -#else /* HSI used on others */ - /**Initializes the CPU, AHB and APB busses clocks - */ +#else /* defined RCC_SYSCLKSOURCE_MSI */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = 16; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; +#endif /* defined RCC_SYSCLKSOURCE_MSI */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("clock issue"); + error("ForceOscOutofDeepSleep clock issue\r\n"); } -#endif // TARGET_STM32L4 } -/* The content of this function has been split into 2 separate functions - so that the involved structures are not allocated on the stack in parallel. - This will reduce the maximum stack usage in case on non-optimized / debug - compilers settings */ -static void ForceClockOutofDeepSleep(void) -{ - ForceOscOutofDeepSleep(); - ForcePeriphOutofDeepSleep(); -} void hal_sleep(void) { @@ -151,7 +118,7 @@ void hal_sleep(void) core_util_critical_section_enter(); // Request to enter SLEEP mode -#if TARGET_STM32L4 +#ifdef PWR_CR1_LPR // State Transitions (see 5.3 Low-power modes, Fig. 13): // * (opt): Low Power Run (LPR) Mode -> Run Mode // * Run Mode -> Sleep @@ -160,7 +127,7 @@ void hal_sleep(void) // * (opt): Run Mode -> Low Power Run Mode // [5.4.1 Power control register 1 (PWR_CR1)] - // LPR: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). + // LPR: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). int lowPowerMode = PWR->CR1 & PWR_CR1_LPR; if (lowPowerMode) { HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); @@ -186,7 +153,7 @@ void hal_deepsleep(void) * This is tracked in mbed issue 4408. * For now, we're checking all Serial HW FIFO. If any transfer is ongoing * we're not entering deep sleep and returning immediately. */ - if(serial_is_tx_ongoing()) { + if (serial_is_tx_ongoing()) { return; } @@ -196,7 +163,7 @@ void hal_deepsleep(void) save_timer_ctx(); // Request to enter STOP mode with regulator in low power mode -#if TARGET_STM32L4 +#ifdef PWR_CR1_LPMS_STOP2 /* STM32L4 */ int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED(); int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR; @@ -215,16 +182,21 @@ void hal_deepsleep(void) if (!pwrClockEnabled) { __HAL_RCC_PWR_CLK_DISABLE(); } -#else /* TARGET_STM32L4 */ +#else /* PWR_CR1_LPMS_STOP2 */ HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); -#endif /* TARGET_STM32L4 */ +#endif /* PWR_CR1_LPMS_STOP2 */ /* Prevent HAL_GetTick() from using ticker_read_us() to read the * us_ticker timestamp until the us_ticker context is restored. */ mbed_sdk_inited = 0; - // Verify Clock Out of Deep Sleep - ForceClockOutofDeepSleep(); + /* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered + * So we need to force clock init out of Deep Sleep. + * This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel. + * This will reduce the maximum stack usage in case on non-optimized / debug compilers settings + */ + ForceOscOutofDeepSleep(); + ForcePeriphOutofDeepSleep(); // After wake-up from STOP reconfigure the PLL SetSysClock(); diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c index f85dae2bd7..75aabafbb3 100644 --- a/targets/TARGET_STM/trng_api.c +++ b/targets/TARGET_STM/trng_api.c @@ -37,13 +37,19 @@ void trng_init(trng_t *obj) error("Only 1 RNG instance supported\r\n"); } -#if defined(TARGET_STM32L4) +#if defined(RCC_PERIPHCLK_RNG) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; /*Select PLLQ output as RNG clock source */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_MSI; +#else PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); +#endif + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + error("RNG clock configuration error\n"); + } #endif /* RNG Peripheral clock enable */ diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h new file mode 100644 index 0000000000..f9c8c5377a --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/PeripheralNames.h @@ -0,0 +1,163 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + SERIAL_2, + SERIAL_3, + SERIAL_4, + SERIAL_5, + INVALID_SERIAL = (int)NC +} UARTName; + +typedef enum { + ADC_AINA00 = 0, + ADC_AINA01, + ADC_AINA02, + ADC_AINA03, + ADC_AINA04, + ADC_AINA05, + ADC_AINA06, + ADC_AINA07, + ADC_AINA08, + ADC_AINA09, + ADC_AINA10, + ADC_AINA11, + ADC_AINA12, + ADC_AINA13, + ADC_AINA14, + ADC_AINA15, + ADC_AINA16, + ADC_AINA17, + ADC_AINA18, + ADC_AINA19, + ADC_AINA20, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + DAC_A0 = 0, + DAC_A1, + INVALID_DAC = (int)NC +} DACName; + +typedef enum { + SPI_0 = 0, + SPI_1, + SPI_2, + SPI_3, + SPI_4, + INVALID_SPI = (int)NC +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + GPIO_IRQ_00 = 0, + GPIO_IRQ_01, + GPIO_IRQ_02, + GPIO_IRQ_03, + GPIO_IRQ_04, + GPIO_IRQ_05, + GPIO_IRQ_06, + GPIO_IRQ_07, + GPIO_IRQ_08, + GPIO_IRQ_09, + GPIO_IRQ_10, + GPIO_IRQ_11, + GPIO_IRQ_12, + GPIO_IRQ_13, + GPIO_IRQ_14, + GPIO_IRQ_15, + GPIO_IRQ_16, + GPIO_IRQ_17_18, + GPIO_IRQ_19_22, + GPIO_IRQ_23_26, + GPIO_IRQ_27_28, + GPIO_IRQ_29, + GPIO_IRQ_30_31, + INVALID_GPIO_IRQ = (int)NC +} gpio_irqname; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART SERIAL_1 + +#define MBED_SPI0 PA1, PA2, PA0, PA4 +#define MBED_SPI1 PB3, PB4, PB2, PB5 +#define MBED_SPI2 PT3, PT4, PT2, PT1 +#define MBED_SPI3 PP4, PP3, PP5, PP6 +#define MBED_SPI4 PH5, PH6, PH4, PH0 + +#define MBED_UART0 PA1, PA2 +#define MBED_UART1 PJ1, PJ2 +#define MBED_UART2 PB2, PB3 +#define MBED_UART3 PA7, PA6 +#define MBED_UART4 PC4, PC5 +#define MBED_UART5 PN2, PN3 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 PC1, PC0 +#define MBED_I2C1 PA5, PA4 +#define MBED_I2C2 PL1, PL0 +#define MBED_I2C3 PT0, PT1 + +#define MBED_ANALOGIN0 A0 +#define MBED_ANALOGIN1 A1 +#define MBED_ANALOGIN2 A2 +#define MBED_ANALOGIN3 A3 +#define MBED_ANALOGIN4 A4 +#define MBED_ANALOGIN5 A5 + +#define MBED_PWMOUT0 PB0 +#define MBED_PWMOUT1 PC0 +#define MBED_PWMOUT2 PJ0 +#define MBED_PWMOUT3 PK2 +#define MBED_PWMOUT4 PN0 +#define MBED_PWMOUT5 PL5 +#define MBED_PWMOUT6 PG2 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h new file mode 100644 index 0000000000..adf4ee610f --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/PinNames.h @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0x1F) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) + +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) +#define PIN_DIR(X) ((X) & 0xffff) + +#define GPIO_NUM (15U) // total number of gpio +#define FRMAX (7U) +#define RESER (8U - (FRMAX)) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM3HQ Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, + PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, + PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, + PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, + PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, + PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, + PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, + PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, PT6, PT7, + PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, + PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, + + // Other mbed Pin Names + LED1 = PK4, + LED2 = PK5, + LED3 = PK6, + LED4 = PK7, + + // External data bus Pin Names + D0 = PV7, + D1 = PV6, + D2 = PC4, + D3 = PK2, + D4 = PC3, + D5 = PJ0, + D6 = PN0, + D7 = PL6, + D8 = PT0, + D9 = PP0, + D10 = PT1, + D11 = PT3, + D12 = PT4, + D13 = PT2, + D14 = PA5, + D15 = PA4, + + // Analogue out pins + A0 = PF2, + A1 = PF3, + A2 = PF4, + A3 = PF5, + A4 = PF6, + A5 = PF7, + + DAC0 = PG0, + DAC1 = PG1, + + // DAP_UART + USBTX = PJ1, + USBRX = PJ2, + MBEDIF_TXD = USBTX, + MBEDIF_RXD = USBRX, + + // Switches + SW1 = PV0, + SW2 = PV1, + SW3 = PV2, + SW4 = PV3, + + // I2C pins + SDA = D14, + SCL = D15, + I2C_SDA = SDA, + I2C_SCL = SCL, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault +} PinMode; + +typedef enum { + DISABLE = 0, + ENABLE +} FunctionalState; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h b/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h new file mode 100644 index 0000000000..84bcf0b3da --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/PortNames.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ, + PortK, + PortL, + PortM, + PortN, + PortP, + PortR, + PortT, + PortU, + PortV +} PortName; + +#define IS_GPIO_PORT(param) ((param) <= PortV) // parameter checking for port number + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c new file mode 100644 index 0000000000..1d08a76abd --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/analogin_api.c @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "gpio_include.h" + +static const PinMap PinMap_ADC[] = { + {PD0, ADC_AINA00, PIN_DATA(0, 0)}, + {PD1, ADC_AINA01, PIN_DATA(0, 0)}, + {PD2, ADC_AINA02, PIN_DATA(0, 0)}, + {PD3, ADC_AINA03, PIN_DATA(0, 0)}, + {PE0, ADC_AINA04, PIN_DATA(0, 0)}, + {PE1, ADC_AINA05, PIN_DATA(0, 0)}, + {PE2, ADC_AINA06, PIN_DATA(0, 0)}, + {PE3, ADC_AINA07, PIN_DATA(0, 0)}, + {PE4, ADC_AINA08, PIN_DATA(0, 0)}, + {PE5, ADC_AINA09, PIN_DATA(0, 0)}, + {PE6, ADC_AINA10, PIN_DATA(0, 0)}, + {PF0, ADC_AINA11, PIN_DATA(0, 0)}, + {PF1, ADC_AINA12, PIN_DATA(0, 0)}, + {PF2, ADC_AINA13, PIN_DATA(0, 0)}, + {PF3, ADC_AINA14, PIN_DATA(0, 0)}, + {PF4, ADC_AINA15, PIN_DATA(0, 0)}, + {PF5, ADC_AINA16, PIN_DATA(0, 0)}, + {PF6, ADC_AINA17, PIN_DATA(0, 0)}, + {PF7, ADC_AINA18, PIN_DATA(0, 0)}, + {PD4, ADC_AINA19, PIN_DATA(0, 0)}, + {PD5, ADC_AINA20, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +/** + * [analogin_init] + * @param obj + * @param pin + * @description Initialize analog input + */ +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + // Assert that ADC channel is valid + MBED_ASSERT(obj->adc != (ADCName)NC); + obj->obj = TSB_ADA; + // ADC CG Fsys Enable + TSB_CG_FSYSENB_IPENB15 = ENABLE; + // ADC Clock Enable + TSB_CG_SPCLKEN_ADCKEN = ENABLE; + // Set pin function as ADC + pinmap_pinout(pin, PinMap_ADC); + // Set sample hold time and pre-scale clock + obj->obj->CLK = (ADC_SCLK_1 | ADC_SAMPLING_PERIOD_3V); + obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); + obj->obj->MOD1 = ADC_MOD1_AVDD5_3V; + obj->obj->MOD2 = ADC_MOD2_TMPM3Hx; +} + +/** + * [analogin_read_u16] + * @param obj + * @return An unsigned short in the range [0x00, 0x0FFF] + * @description Read the ADC input + */ +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t ADCResultValue = 0; + uint32_t ADCResultStored = 0; + + // Wait at least 3us to ensure the voltage is stable + wait_us(300); + // ADC configuration for data Conversion + obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); + obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE + | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); + // Wait until AD conversion complete + while( (obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE); + // Wait for register to update with convert value + wait_us(30); + // Convert result + ADCResultStored = (obj->obj->REG0 | obj->adc); + if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { + ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4); + } + return ADCResultValue; +} + +/** + * [analogin_read] + * @param obj + * @return A float in the range [0.0, 1.0] + * @description Read the ADC input + */ +float analogin_read(analogin_t *obj) +{ + uint16_t value = analogin_read_u16(obj); + return ((float)(value * (1.0f / (float)ADC_12BIT_RANGE))); +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c new file mode 100644 index 0000000000..2abc75b8f6 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/analogout_api.c @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogout_api.h" +#include "PeripheralNames.h" +#include "mbed_wait_api.h" +#include "pinmap.h" + +#define DAC_START ((uint32_t)0x00000001) +#define DAC_STOP ((uint32_t)0x00000000) + +static const PinMap PinMap_DAC[] = { + {DAC0, DAC_A0, PIN_DATA(0, 3)}, + {DAC1, DAC_A1, PIN_DATA(0, 3)}, + {NC, NC, 0} +}; + +static void analogout_start(dac_t *obj) +{ + obj->handler->CTL = DAC_START; // Supply Vref and enable DAC +} + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module + MBED_ASSERT(obj->dac != (DACName)NC); + + pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC + TSB_CG_FSYSENA_IPENA06 = ENABLE; + if (obj->dac == DAC_A0) { // Compute handler + obj->handler = TSB_DA0; + TSB_CG_FSYSENB_IPENB17 = ENABLE; + } else { + if (obj->dac == DAC_A1) { + obj->handler = TSB_DA1; + TSB_CG_FSYSENB_IPENB18 = ENABLE; + } else { + obj->handler = NULL; + } + } + obj->handler->CTL = DAC_STOP; +} + +void analogout_free(dac_t *obj) +{ + obj->handler->CTL = DAC_STOP; +} + +void analogout_write(dac_t *obj, float value) +{ + uint8_t outputcode; + + analogout_start(obj); + + if (value < 0.0f) { + value = 0.0f; + } else { + if (value >= 1.0f) { + value = 1.0f; + } + } + outputcode = (uint8_t)(value * 255.0f); + obj->handler->REG = outputcode; + wait_ms(3); +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + analogout_start(obj); + obj->handler->REG = (uint8_t)(value & 0xFF); + wait_ms(3); +} + +float analogout_read(dac_t *obj) +{ + float result; + uint32_t value = 0; + + value = ((obj->handler->REG) & (0xFF)); + result = ((float)value / 255.0f); + + return result; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + uint16_t value = 0; + + value = (uint16_t)((obj->handler->REG) & (0xFF)); + + return value; +} diff --git a/TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_F413ZH/flash_config.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device.h similarity index 71% rename from TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_F413ZH/flash_config.h rename to targets/TARGET_TT/TARGET_TT_M3HQ/device.h index 67d8c317d6..ff9910ab57 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_F413ZH/flash_config.h +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - * Copyright (c) 2018-2018 ARM Limited - * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at @@ -13,10 +13,11 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef MBED_QSPI_FLASH_CONFIG_H -#define MBED_QSPI_FLASH_CONFIG_H +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H -#include "../../N25Q128A_config.h" +#define DEVICE_ID_LENGTH 32 +#include "objects.h" -#endif // MBED_QSPI_FLASH_CONFIG_H +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h new file mode 100644 index 0000000000..0aaef3e355 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TMPM3HQ.h @@ -0,0 +1,4539 @@ +/** + ******************************************************************************* + * @file TMPM3HQ.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM3HQ' Device Series + * @version V1.0.0.1 + * $Date:: 2017-12-27 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM3HQ + * @{ + */ + +#ifndef __TMPM3HQ_H__ +#define __TMPM3HQ_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** TMPM3HQ Specific Interrupt Numbers *******************************************************************/ + INT00_IRQn = 0, /*!< Interrupt Pin 00 */ + INT01_IRQn = 1, /*!< Interrupt Pin 01 */ + INT02_IRQn = 2, /*!< Interrupt Pin 02 */ + INT03_IRQn = 3, /*!< Interrupt Pin 03 */ + INT04_IRQn = 4, /*!< Interrupt Pin 04 */ + INT05_IRQn = 5, /*!< Interrupt Pin 05 */ + INT06_IRQn = 6, /*!< Interrupt Pin 06 */ + INT07_IRQn = 7, /*!< Interrupt Pin 07 */ + INT08_IRQn = 8, /*!< Interrupt Pin 08 */ + INT09_IRQn = 9, /*!< Interrupt Pin 09 */ + INT10_IRQn = 10, /*!< Interrupt Pin 10 */ + INT11_IRQn = 11, /*!< Interrupt Pin 11 */ + INT12_IRQn = 12, /*!< Interrupt Pin 12 */ + INT13_IRQn = 13, /*!< Interrupt Pin 13 */ + INT14_IRQn = 14, /*!< Interrupt Pin 14 */ + INT15_IRQn = 15, /*!< Interrupt Pin 15 */ + INT16_IRQn = 16, /*!< Interrupt Pin 16 */ + INT17_18_IRQn = 17, /*!< Interrupt Pin 17_18 */ + INT19_22_IRQn = 18, /*!< Interrupt Pin 19_22 */ + INT23_26_IRQn = 19, /*!< Interrupt Pin 23_26 */ + INT27_28_IRQn = 20, /*!< Interrupt Pin 27_28 */ + INT29_IRQn = 21, /*!< Interrupt Pin 29 */ + INT30_31_IRQn = 22, /*!< Interrupt Pin 30_31 */ + INTEMG0_IRQn = 23, /*!< PMD0 EMG interrupt */ + INTOVV0_IRQn = 24, /*!< PMD0 OVV interrupt */ + INTPMD0_IRQn = 25, /*!< PMD0 interrupt */ + INTENC00_IRQn = 26, /*!< Encoder 0 interrupt 0 */ + INTENC01_IRQn = 27, /*!< Encoder 0 interrupt 1 */ + INTADAPDA_IRQn = 28, /*!< ADC conversion triggered by PMD is finished A */ + INTADAPDB_IRQn = 29, /*!< ADC conversion triggered by PMD is finished B */ + INTADACP0_IRQn = 30, /*!< ADC conversion monitoring function interrupt 0 */ + INTADACP1_IRQn = 31, /*!< ADC conversion monitoring function interrupt 1 */ + INTADATRG_IRQn = 32, /*!< ADC conversion triggered by General purpose is finished */ + INTADASGL_IRQn = 33, /*!< ADC conversion triggered by Single program is finished */ + INTADACNT_IRQn = 34, /*!< ADC conversion triggered by Continuity program is finished */ + INTT0RX_IRQn = 35, /*!< TSPI/SIO reception (channel 0) */ + INTT0TX_IRQn = 36, /*!< TSPI/SIO transmit (channel 0) */ + INTT0ERR_IRQn = 37, /*!< TSPI/SIO error (channel 0) */ + INTT1RX_IRQn = 38, /*!< TSPI/SIO reception (channel 1) */ + INTT1TX_IRQn = 39, /*!< TSPI/SIO transmit (channel 1) */ + INTT1ERR_IRQn = 40, /*!< TSPI/SIO error (channel 1) */ + INTT2RX_IRQn = 41, /*!< TSPI/SIO reception (channel 2) */ + INTT2TX_IRQn = 42, /*!< TSPI/SIO transmit (channel 2) */ + INTT2ERR_IRQn = 43, /*!< TSPI/SIO error (channel 2) */ + INTT3RX_IRQn = 44, /*!< TSPI/SIO reception (channel 3) */ + INTT3TX_IRQn = 45, /*!< TSPI/SIO transmit (channel 3) */ + INTT3ERR_IRQn = 46, /*!< TSPI/SIO error (channel 3) */ + INTT4RX_IRQn = 47, /*!< TSPI/SIO reception (channel 4) */ + INTT4TX_IRQn = 48, /*!< TSPI/SIO transmit (channel 4) */ + INTT4ERR_IRQn = 49, /*!< TSPI/SIO error (channel 4) */ + INTI2CWUP_IRQn = 50, /*!< Serial bus interface (WakeUp) interrupt (channel 0) */ + INTI2C0_IRQn = 51, /*!< I2C0 transmission and reception interrupt */ + INTI2C0AL_IRQn = 52, /*!< I2C0 arbitration lost interrupt */ + INTI2C0BF_IRQn = 53, /*!< I2C0 bus free interrupt */ + INTI2C0NA_IRQn = 54, /*!< I2C0 no ack interrupt */ + INTI2C1_IRQn = 55, /*!< I2C1 transmission and reception interrupt */ + INTI2C1AL_IRQn = 56, /*!< I2C1 arbitration lost interrupt */ + INTI2C1BF_IRQn = 57, /*!< I2C1 bus free interrupt */ + INTI2C1NA_IRQn = 58, /*!< I2C1 no ack interrupt */ + INTI2C2_IRQn = 59, /*!< I2C2 transmission and reception interrupt */ + INTI2C2AL_IRQn = 60, /*!< I2C2 arbitration lost interrupt */ + INTI2C2BF_IRQn = 61, /*!< I2C2 bus free interrupt */ + INTI2C2NA_IRQn = 62, /*!< I2C2 no ack interrupt */ + INTI2C3_IRQn = 63, /*!< I2C3 transmission and reception interrupt */ + INTI2C3AL_IRQn = 64, /*!< I2C3 arbitration lost interrupt */ + INTI2C3BF_IRQn = 65, /*!< I2C3 bus free interrupt */ + INTI2C3NA_IRQn = 66, /*!< I2C3 no ack interrupt */ + INTUART0RX_IRQn = 67, /*!< UART reception (channel 0) */ + INTUART0TX_IRQn = 68, /*!< UART transmit (channel 0) */ + INTUART0ERR_IRQn = 69, /*!< UART error (channel 0) */ + INTUART1RX_IRQn = 70, /*!< UART reception (channel 1) */ + INTUART1TX_IRQn = 71, /*!< UART transmit (channel 1) */ + INTUART1ERR_IRQn = 72, /*!< UART error (channel 1) */ + INTUART2RX_IRQn = 73, /*!< UART reception (channel 2) */ + INTUART2TX_IRQn = 74, /*!< UART transmit (channel 2) */ + INTUART2ERR_IRQn = 75, /*!< UART error (channel 2) */ + INTUART3RX_IRQn = 76, /*!< UART reception (channel 3) */ + INTUART3TX_IRQn = 77, /*!< UART transmit (channel 3) */ + INTUART3ERR_IRQn = 78, /*!< UART error (channel 3) */ + INTUART4RX_IRQn = 79, /*!< UART reception (channel 4) */ + INTUART4TX_IRQn = 80, /*!< UART transmit (channel 4) */ + INTUART4ERR_IRQn = 81, /*!< UART error (channel 4) */ + INTUART5RX_IRQn = 82, /*!< UART reception (channel 5) */ + INTUART5TX_IRQn = 83, /*!< UART transmit (channel 5) */ + INTUART5ERR_IRQn = 84, /*!< UART error (channel 5) */ + INTT32A00A_IRQn = 85, /*!< 32bit T32A00A compare match detection 0 / Over flow / under flow*/ + INTT32A00ACAP0_IRQn = 86, /*!< 32bit T32A00A input capture 0 */ + INTT32A00ACAP1_IRQn = 87, /*!< 32bit T32A00A input capture 1 */ + INTT32A00B_IRQn = 88, /*!< 32bit T32A00B compare match detection 0 / Over flow / under flow*/ + INTT32A00BCAP0_IRQn = 89, /*!< 32bit T32A00B input capture 0 */ + INTT32A00BCAP1_IRQn = 90, /*!< 32bit T32A00B input capture 1 */ + INTT32A00C_IRQn = 91, /*!< 32bit T32A00C compare match detection 0 / Over flow / under flow*/ + INTT32A00CCAP0_IRQn = 92, /*!< 32bit T32A00C input capture 0 */ + INTT32A00CCAP1_IRQn = 93, /*!< 32bit T32A00C input capture 1 */ + INTT32A01A_IRQn = 94, /*!< 32bit T32A01A compare match detection 0 / Over flow / under flow*/ + INTT32A01ACAP0_IRQn = 95, /*!< 32bit T32A01A input capture 0 */ + INTT32A01ACAP1_IRQn = 96, /*!< 32bit T32A01A input capture 1 */ + INTT32A01B_IRQn = 97, /*!< 32bit T32A01B compare match detection 0 / Over flow / under flow*/ + INTT32A01BCAP0_IRQn = 98, /*!< 32bit T32A01B input capture 0 */ + INTT32A01BCAP1_IRQn = 99, /*!< 32bit T32A01B input capture 1 */ + INTT32A01C_IRQn = 100, /*!< 32bit T32A01C compare match detection 0 / Over flow / under flow*/ + INTT32A01CCAP0_IRQn = 101, /*!< 32bit T32A01C input capture 0 */ + INTT32A01CCAP1_IRQn = 102, /*!< 32bit T32A01C input capture 1 */ + INTT32A02A_IRQn = 103, /*!< 32bit T32A02A compare match detection 0 / Over flow / under flow*/ + INTT32A02ACAP0_IRQn = 104, /*!< 32bit T32A02A input capture 0 */ + INTT32A02ACAP1_IRQn = 105, /*!< 32bit T32A02A input capture 1 */ + INTT32A02B_IRQn = 106, /*!< 32bit T32A02B compare match detection 0 / Over flow / under flow*/ + INTT32A02BCAP0_IRQn = 107, /*!< 32bit T32A02B input capture 0 */ + INTT32A02BCAP1_IRQn = 108, /*!< 32bit T32A02B input capture 1 */ + INTT32A02C_IRQn = 109, /*!< 32bit T32A02C compare match detection 0 / Over flow / under flow*/ + INTT32A02CCAP0_IRQn = 110, /*!< 32bit T32A02C input capture 0 */ + INTT32A02CCAP1_IRQn = 111, /*!< 32bit T32A02C input capture 1 */ + INTT32A03A_IRQn = 112, /*!< 32bit T32A03A compare match detection 0 / Over flow / under flow*/ + INTT32A03ACAP0_IRQn = 113, /*!< 32bit T32A03A input capture 0 */ + INTT32A03ACAP1_IRQn = 114, /*!< 32bit T32A03A input capture 1 */ + INTT32A03B_IRQn = 115, /*!< 32bit T32A03B compare match detection 0 / Over flow / under flow*/ + INTT32A03BCAP0_IRQn = 116, /*!< 32bit T32A03B input capture 0 */ + INTT32A03BCAP1_IRQn = 117, /*!< 32bit T32A03B input capture 1 */ + INTT32A03C_IRQn = 118, /*!< 32bit T32A03C compare match detection 0 / Over flow / under flow*/ + INTT32A03CCAP0_IRQn = 119, /*!< 32bit T32A03C input capture 0 */ + INTT32A03CCAP1_IRQn = 120, /*!< 32bit T32A03C input capture 1 */ + INTT32A04A_IRQn = 121, /*!< 32bit T32A04A compare match detection 0 / Over flow / under flow*/ + INTT32A04ACAP0_IRQn = 122, /*!< 32bit T32A04A input capture 0 */ + INTT32A04ACAP1_IRQn = 123, /*!< 32bit T32A04A input capture 1 */ + INTT32A04B_IRQn = 124, /*!< 32bit T32A04B compare match detection 0 / Over flow / under flow*/ + INTT32A04BCAP0_IRQn = 125, /*!< 32bit T32A04B input capture 0 */ + INTT32A04BCAP1_IRQn = 126, /*!< 32bit T32A04B input capture 1 */ + INTT32A04C_IRQn = 127, /*!< 32bit T32A04C compare match detection 0 / Over flow / under flow*/ + INTT32A04CCAP0_IRQn = 128, /*!< 32bit T32A04C input capture 0 */ + INTT32A04CCAP1_IRQn = 129, /*!< 32bit T32A04C input capture 1 */ + INTT32A05A_IRQn = 130, /*!< 32bit T32A05A compare match detection 0 / Over flow / under flow*/ + INTT32A05ACAP0_IRQn = 131, /*!< 32bit T32A05A input capture 0 */ + INTT32A05ACAP1_IRQn = 132, /*!< 32bit T32A05A input capture 1 */ + INTT32A05B_IRQn = 133, /*!< 32bit T32A05B compare match detection 0 / Over flow / under flow*/ + INTT32A05BCAP0_IRQn = 134, /*!< 32bit T32A05B input capture 0 */ + INTT32A05BCAP1_IRQn = 135, /*!< 32bit T32A05B input capture 1 */ + INTT32A05C_IRQn = 136, /*!< 32bit T32A05C compare match detection 0 / Over flow / under flow*/ + INTT32A05CCAP0_IRQn = 137, /*!< 32bit T32A05C input capture 0 */ + INTT32A05CCAP1_IRQn = 138, /*!< 32bit T32A05C input capture 1 */ + INTT32A06A_IRQn = 139, /*!< 32bit T32A06A compare match detection 0 / Over flow / under flow*/ + INTT32A06ACAP0_IRQn = 140, /*!< 32bit T32A06A input capture 0 */ + INTT32A06ACAP1_IRQn = 141, /*!< 32bit T32A06A input capture 1 */ + INTT32A06B_IRQn = 142, /*!< 32bit T32A06B compare match detection 0 / Over flow / under flow*/ + INTT32A06BCAP0_IRQn = 143, /*!< 32bit T32A06B input capture 0 */ + INTT32A06BCAP1_IRQn = 144, /*!< 32bit T32A06B input capture 1 */ + INTT32A06C_IRQn = 145, /*!< 32bit T32A06C compare match detection 0 / Over flow / under flow*/ + INTT32A06CCAP0_IRQn = 146, /*!< 32bit T32A06C input capture 0 */ + INTT32A06CCAP1_IRQn = 147, /*!< 32bit T32A06C input capture 1 */ + INTT32A07A_IRQn = 148, /*!< 32bit T32A07A compare match detection 0 / Over flow / under flow*/ + INTT32A07ACAP0_IRQn = 149, /*!< 32bit T32A07A input capture 0 */ + INTT32A07ACAP1_IRQn = 150, /*!< 32bit T32A07A input capture 1 */ + INTT32A07B_IRQn = 151, /*!< 32bit T32A07B compare match detection 0 / Over flow / under flow*/ + INTT32A07BCAP0_IRQn = 152, /*!< 32bit T32A07B input capture 0 */ + INTT32A07BCAP1_IRQn = 153, /*!< 32bit T32A07B input capture 1 */ + INTT32A07C_IRQn = 154, /*!< 32bit T32A07C compare match detection 0 / Over flow / under flow*/ + INTT32A07CCAP0_IRQn = 155, /*!< 32bit T32A07C input capture 0 */ + INTT32A07CCAP1_IRQn = 156, /*!< 32bit T32A07C input capture 1 */ + INTPARI_IRQn = 157, /*!< RAM parity interrupt */ + INTDMAATC_IRQn = 158, /*!< DMAA end of transfer */ + INTDMAAERR_IRQn = 159, /*!< DMAA transfer error */ + INTDMABTC_IRQn = 160, /*!< DMAB end of transfer */ + INTDMABERR_IRQn = 161, /*!< DMAB transfer error */ + INTRTC_IRQn = 162, /*!< Real time clock interrupt */ + INTRMC0_IRQn = 163, /*!< Remote control reception interrupt */ + INTFLCRDY_IRQn = 164, /*!< Code FLASH Ready interrupt */ + INTFLDRDY_IRQn = 165 /*!< Data FLASH Ready interrupt */ +} IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_TMPM3HQ.h" /* TMPM3HQ System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief Interrupt control A Register + */ +typedef struct +{ + __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(A) 00 */ + uint8_t RESERVED0[31]; + __IO uint8_t IMC00; /*!< Interrupu Mode Control Register(A) 00 */ + __IO uint8_t IMC01; /*!< Interrupu Mode Control Register(A) 01 */ + __IO uint8_t IMC02; /*!< Interrupu Mode Control Register(A) 02 */ + __IO uint8_t IMC03; /*!< Interrupu Mode Control Register(A) 03 */ + uint8_t RESERVED1[12]; + __IO uint8_t IMC16; /*!< Interrupu Mode Control Register(A) 16 */ + __IO uint8_t IMC17; /*!< Interrupu Mode Control Register(A) 17 */ +} TSB_IA_TypeDef; + +/** + * @brief Reset LOSC Management register + */ +typedef struct +{ + __IO uint8_t LOSCCR; /*!< Low OSC Control Register */ + __IO uint8_t SHTDNOP; /*!< Power Shut Down Control Register */ + __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ + __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ + uint8_t RESERVED0[11]; + __IO uint8_t PROTECT; /*!< Protect Register */ +} TSB_RLM_TypeDef; + +/** + * @brief I2C Wakeup control register + */ +typedef struct +{ + __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ + __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ + __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ + __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ +} TSB_I2CS_TypeDef; + +/** + * @brief LVD0 + */ +typedef struct +{ + __IO uint8_t CR; /*!< LVD Control register */ +} TSB_LVD_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __I uint32_t STATUS; /*!< DMA Status Register */ + __O uint32_t CFG; /*!< DMA Configuration Register */ + __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ + __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base +Pointer Register*/ + uint32_t RESERVED0; + __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ + __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ + __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ + __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ + __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ + __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ + __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ + __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ + __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ + __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ + __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ + uint32_t RESERVED1[3]; + __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ +} TSB_DMA_TypeDef; + +/** + * @brief Digital analog converter (DAC) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DAC Control Register */ + __IO uint32_t REG; /*!< DAC output Register */ +} TSB_DA_TypeDef; + +/** + * @brief Serial Interface (TSPI) + */ +typedef struct +{ + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + uint32_t RESERVED0[57]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ +} TSB_TSPI_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief I2C + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< I2C Data Buffer Register */ + __IO uint32_t AR; /*!< I2C Bus address Register */ +union { + __O uint32_t CR2; /*!< I2C Control Register 2 */ + __I uint32_t SR; /*!< I2C Status Register */ + }; + __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ + __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ + __IO uint32_t ST; /*!< I2C Interrupt Register */ + __IO uint32_t OP; /*!< I2C Optiononal Function register */ + __I uint32_t PM; /*!< I2C Bus Monitor register */ + __IO uint32_t AR2; /*!< I2C Second Slave address register */ +} TSB_I2C_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t CR0; /*!< AD Control Register 0 */ + __IO uint32_t CR1; /*!< AD Control Register 1 */ + __I uint32_t ST; /*!< AD Status Register */ + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ + __IO uint32_t MOD3; /*!< AD Mode Control Register 3 */ + __IO uint32_t CMPEN; /*!< AD Monitoring interrupt permission register */ + __IO uint32_t CMPCR0; /*!< AD Monitoring Setting Register 0 */ + __IO uint32_t CMPCR1; /*!< AD Monitoring Setting Register 1 */ + __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ + __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ + uint32_t RESERVED0[3]; + __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ + __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ + __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ + __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ + __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ + __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ + __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ + __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ + __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ + __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ + __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ + __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ + __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ + __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ + __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ + __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ + __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ + __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ + __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ + __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ + __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register*/ + uint32_t RESERVED1[3]; + __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ + __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ + __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ + __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ + __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ + __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ + __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ + __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ + __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ + __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ + __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ + __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ + __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ + __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ + __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ + __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ + __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ + __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ + __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ + __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ + __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ + __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ + __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ + __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ + __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ + __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ + __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ + __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ + __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ + __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ + __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ + __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ + uint32_t RESERVED2[8]; + __I uint32_t REG0; /*!< AD AD Conversion Result Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ + __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ + __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ + __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ + __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ + __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ + __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ + __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ + __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ + __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ + __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ + __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ + __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ + __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ + __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ + __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ + __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ +} TSB_AD_TypeDef; + +/** + * @brief T32A + */ +typedef struct +{ + __IO uint32_t MOD; /*!< T32A Mode Register */ + uint32_t RESERVED0[15]; + __IO uint32_t RUNA; /*!< T32A Run Register A */ + __IO uint32_t CRA; /*!< T32A Counter control Register A */ + __IO uint32_t CAPCRA; /*!< T32A Capture control Register A */ + __IO uint32_t OUTCRA0; /*!< T32A Output control Register A0 */ + __IO uint32_t OUTCRA1; /*!< T32A Output control Register A1 */ + __IO uint32_t STA; /*!< T32A Status Register A */ + __IO uint32_t IMA; /*!< T32A Interrupt mask Register A */ + __I uint32_t TMRA; /*!< T32A Counter capture Register A */ + __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ + __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ + __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ + __I uint32_t CAPA0; /*!< T32A Timer capturer A0 */ + __I uint32_t CAPA1; /*!< T32A Timer capturer A1 */ + __IO uint32_t DMAA; /*!< T32A DMA Request Enabl eRegister A */ + uint32_t RESERVED1[2]; + __IO uint32_t RUNB; /*!< T32A Run Register B */ + __IO uint32_t CRB; /*!< T32A Counter control Register B */ + __IO uint32_t CAPCRB; /*!< T32A Capture control Register B */ + __IO uint32_t OUTCRB0; /*!< T32A Output control Register B0 */ + __IO uint32_t OUTCRB1; /*!< T32A Output control Register B1 */ + __IO uint32_t STB; /*!< T32A Status Register B */ + __IO uint32_t IMB; /*!< T32A Interrupt mask Register B */ + __I uint32_t TMRB; /*!< T32A Counter capture Register B */ + __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ + __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ + __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ + __I uint32_t CAPB0; /*!< T32A Timer capturer B0 */ + __I uint32_t CAPB1; /*!< T32A Timer capturer B1 */ + __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ + uint32_t RESERVED2[2]; + __IO uint32_t RUNC; /*!< T32A Run Register C */ + __IO uint32_t CRC; /*!< T32A Counter control Register C */ + __IO uint32_t CAPCRC; /*!< T32A Capture control Register C */ + __IO uint32_t OUTCRC0; /*!< T32A Output control Register C0 */ + __IO uint32_t OUTCRC1; /*!< T32A Output control Register C1 */ + __IO uint32_t STC; /*!< T32A Status Register C */ + __IO uint32_t IMC; /*!< T32A Interrupt mask Register C */ + __I uint32_t TMRC; /*!< T32A Counter capture Register C */ + __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ + __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ + __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ + __I uint32_t CAPC0; /*!< T32A Timer capturer C0 */ + __I uint32_t CAPC1; /*!< T32A Timer capturer C1 */ + __IO uint32_t DMAC; /*!< T32A DMA Request Enabl eRegister C */ + __IO uint32_t PLSCR; /*!< T32A Pulse count control register */ +} TSB_T32A_TypeDef; + +/** + * @brief UART + */ +typedef struct +{ + __IO uint32_t SWRST; /*!< UART Software reset register */ + __IO uint32_t CR0; /*!< UART Control register 0 */ + __IO uint32_t CR1; /*!< UART Control register 1 */ + __IO uint32_t CLK; /*!< UART Clock Control register */ + __IO uint32_t BRD; /*!< UART Baud rate register */ + __IO uint32_t TRANS; /*!< UART Transfer enable register */ + __IO uint32_t DR; /*!< UART Data register */ + __IO uint32_t SR; /*!< UART Status register */ + __IO uint32_t FIFOCLR; /*!< UART FIFO Clear register */ + __IO uint32_t ERR; /*!< UART Error register */ +} TSB_UART_TypeDef; + +/** + * @brief SIWD + */ +typedef struct +{ + __IO uint32_t PRO; /*!< SIWD Protect register */ + __IO uint32_t EN; /*!< SIWD Enable register */ + __O uint32_t CR; /*!< SIWD Control register */ + __IO uint32_t MOD; /*!< SIWD Mode register */ + __I uint32_t MONI; /*!< SIWD Monitor register */ + __IO uint32_t OSCCR; /*!< SIWD Oscillation control register */ +} TSB_SIWD_TypeDef; + +/** + * @brief DNF + */ +typedef struct +{ + __IO uint32_t CKCR; /*!< DNF clock Control register */ + __IO uint32_t ENCR; /*!< DNF Enable register */ +} TSB_DNF_TypeDef; + +/** + * @brief TRGSEL + */ +typedef struct +{ + __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ + __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ + __IO uint32_t CR2; /*!< TSEL Control register 2 */ + __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ + __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ + __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ + __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ + __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ + __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ + __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ + __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ + __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ + __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ + __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ + __IO uint32_t CR14; /*!< TRGSEL Control register 14 */ + __IO uint32_t CR15; /*!< TRGSEL Control register 15 */ +} TSB_TSEL_TypeDef; + +/** + * @brief RAM Parity + */ +typedef struct +{ + __IO uint32_t CTL; /*!< RAMM Parity control register */ + __I uint32_t ST; /*!< RAMM Parity status register */ + __O uint32_t CLR; /*!< RAMM Parity status clear register */ + __I uint32_t EAD0; /*!< RAMM Parity Error address register 0 */ + __I uint32_t EAD1; /*!< RAMM Parity Error address register 1 */ + __I uint32_t EAD2; /*!< RAMM Parity Error address register 2 */ + __I uint32_t EAD3; /*!< RAMM Parity Error address register 3 */ +} TSB_RPAR_TypeDef; + +/** + * @brief CRC + */ +typedef struct +{ + __IO uint32_t DIN; /*!< CRC input data register */ + uint32_t RESERVED0[4]; + __IO uint32_t TYP; /*!< CRC data type register */ + uint32_t RESERVED1[5]; + __IO uint32_t CLC; /*!< CRC calculation result register */ +} TSB_CRC_TypeDef; + +/** + * @brief CMP + */ +typedef struct +{ + __IO uint32_t CTRLA; /*!< CMP control register A */ +} TSB_CMP_TypeDef; + +/** + * @brief Port A + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PA Data Register */ + __IO uint32_t CR; /*!< PA Control Register */ + __IO uint32_t FR1; /*!< PA Function Register 1 */ + __IO uint32_t FR2; /*!< PA Function Register 2 */ + __IO uint32_t FR3; /*!< PA Function Register 3 */ + __IO uint32_t FR4; /*!< PA Function Register 4 */ + __IO uint32_t FR5; /*!< PA Function Register 5 */ + __IO uint32_t FR6; /*!< PA Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< PA Open Drain Control Register */ + __IO uint32_t PUP; /*!< PA Pull-up Control Register */ + __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PA Input Enable Control Register */ +} TSB_PA_TypeDef; + +/** + * @brief Port B + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PB Data Register */ + __IO uint32_t CR; /*!< PB Control Register */ + __IO uint32_t FR1; /*!< PB Function Register 1 */ + __IO uint32_t FR2; /*!< PB Function Register 2 */ + __IO uint32_t FR3; /*!< PB Function Register 3 */ + __IO uint32_t FR4; /*!< PB Function Register 4 */ + __IO uint32_t FR5; /*!< PB Function Register 5 */ + __IO uint32_t FR6; /*!< PB Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< PB Open Drain Control Register */ + __IO uint32_t PUP; /*!< PB Pull-up Control Register */ + __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PB Input Enable Control Register */ +} TSB_PB_TypeDef; + +/** + * @brief Port C + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PC Data Register */ + __IO uint32_t CR; /*!< PC Control Register */ + __IO uint32_t FR1; /*!< PC Function Register 1 */ + __IO uint32_t FR2; /*!< PC Function Register 2 */ + __IO uint32_t FR3; /*!< PC Function Register 3 */ + __IO uint32_t FR4; /*!< PC Function Register 4 */ + __IO uint32_t FR5; /*!< PC Function Register 5 */ + uint32_t RESERVED0[3]; + __IO uint32_t OD; /*!< PC Open Drain Control Register */ + __IO uint32_t PUP; /*!< PC Pull-up Control Register */ + __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PC Input Enable Control Register */ +} TSB_PC_TypeDef; + +/** + * @brief Port D + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PD Data Register */ + __IO uint32_t CR; /*!< PD Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PD Open Drain Control Register */ + __IO uint32_t PUP; /*!< PD Pull-up Control Register */ + __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PD Input Enable Control Register */ +} TSB_PD_TypeDef; + +/** + * @brief Port E + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PE Data Register */ + __IO uint32_t CR; /*!< PE Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PE Open Drain Control Register */ + __IO uint32_t PUP; /*!< PE Pull-up Control Register */ + __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PE Input Enable Control Register */ +} TSB_PE_TypeDef; + +/** + * @brief Port F + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PF Data Register */ + __IO uint32_t CR; /*!< PF Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PF Open Drain Control Register */ + __IO uint32_t PUP; /*!< PF Pull-up Control Register */ + __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PF Input Enable Control Register */ +} TSB_PF_TypeDef; + +/** + * @brief Port G + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PG Data Register */ + __IO uint32_t CR; /*!< PG Control Register */ + __IO uint32_t FR1; /*!< PG Function Register 1 */ + __IO uint32_t FR2; /*!< PG Function Register 2 */ + __IO uint32_t FR3; /*!< PG Function Register 3 */ + __IO uint32_t FR4; /*!< PG Function Register 4 */ + uint32_t RESERVED0[4]; + __IO uint32_t OD; /*!< PG Open Drain Control Register */ + __IO uint32_t PUP; /*!< PG Pull-up Control Register */ + __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PG Input Enable Control Register */ +} TSB_PG_TypeDef; + +/** + * @brief Port H + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PH Data Register */ + __IO uint32_t CR; /*!< PH Control Register */ + __IO uint32_t FR1; /*!< PH Function Register 1 */ + uint32_t RESERVED0[7]; + __IO uint32_t OD; /*!< PH Open Drain Control Register */ + __IO uint32_t PUP; /*!< PH Pull-up Control Register */ + __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PH Input Enable Control Register */ +} TSB_PH_TypeDef; + +/** + * @brief Port J + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PJ Data Register */ + __IO uint32_t CR; /*!< PJ Control Register */ + __IO uint32_t FR1; /*!< PJ Function Register 1 */ + __IO uint32_t FR2; /*!< PJ Function Register 2 */ + __IO uint32_t FR3; /*!< PJ Function Register 3 */ + __IO uint32_t FR4; /*!< PJ Function Register 4 */ + __IO uint32_t FR5; /*!< PJ Function Register 5 */ + uint32_t RESERVED0[3]; + __IO uint32_t OD; /*!< PJ Open Drain Control Register */ + __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ + __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PJ Input Enable Control Register */ +} TSB_PJ_TypeDef; + +/** + * @brief Port K + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PK Data Register */ + __IO uint32_t CR; /*!< PK Control Register */ + __IO uint32_t FR1; /*!< PK Function Register 1 */ + __IO uint32_t FR2; /*!< PK Function Register 2 */ + __IO uint32_t FR3; /*!< PK Function Register 3 */ + __IO uint32_t FR4; /*!< PK Function Register 4 */ + __IO uint32_t FR5; /*!< PK Function Register 5 */ + uint32_t RESERVED0[3]; + __IO uint32_t OD; /*!< PK Open Drain Control Register */ + __IO uint32_t PUP; /*!< PK Pull-up Control Register */ + __IO uint32_t PDN; /*!< PK Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PK Input Enable Control Register */ +} TSB_PK_TypeDef; + +/** + * @brief Port L + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PL Data Register */ + __IO uint32_t CR; /*!< PL Control Register */ + __IO uint32_t FR1; /*!< PL Function Register 1 */ + __IO uint32_t FR2; /*!< PL Function Register 2 */ + __IO uint32_t FR3; /*!< PL Function Register 3 */ + __IO uint32_t FR4; /*!< PL Function Register 4 */ + __IO uint32_t FR5; /*!< PL Function Register 4 */ + uint32_t RESERVED0[3]; + __IO uint32_t OD; /*!< PL Open Drain Control Register */ + __IO uint32_t PUP; /*!< PL Pull-up Control Register */ + __IO uint32_t PDN; /*!< PL Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PL Input Enable Control Register */ +} TSB_PL_TypeDef; + +/** + * @brief Port M + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PM Data Register */ + __IO uint32_t CR; /*!< PM Control Register */ + __IO uint32_t FR1; /*!< PM Function Register 1 */ + __IO uint32_t FR2; /*!< PM Function Register 2 */ + __IO uint32_t FR3; /*!< PM Function Register 3 */ + __IO uint32_t FR4; /*!< PM Function Register 4 */ + __IO uint32_t FR5; /*!< PM Function Register 5 */ + __IO uint32_t FR6; /*!< PM Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< PM Open Drain Control Register */ + __IO uint32_t PUP; /*!< PM Pull-up Control Register */ + __IO uint32_t PDN; /*!< PM Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PM Input Enable Control Register */ +} TSB_PM_TypeDef; + +/** + * @brief Port N + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PN Data Register */ + __IO uint32_t CR; /*!< PN Control Register */ + __IO uint32_t FR1; /*!< PN Function Register 1 */ + __IO uint32_t FR2; /*!< PN Function Register 2 */ + __IO uint32_t FR3; /*!< PN Function Register 3 */ + __IO uint32_t FR4; /*!< PN Function Register 4 */ + __IO uint32_t FR5; /*!< PN Function Register 5 */ + uint32_t RESERVED0[3]; + __IO uint32_t OD; /*!< PN Open Drain Control Register */ + __IO uint32_t PUP; /*!< PN Pull-up Control Register */ + __IO uint32_t PDN; /*!< PN Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PN Input Enable Control Register */ +} TSB_PN_TypeDef; + +/** + * @brief Port P + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PP Data Register */ + __IO uint32_t CR; /*!< PP Control Register */ + __IO uint32_t FR1; /*!< PP Function Register 1 */ + __IO uint32_t FR2; /*!< PP Function Register 2 */ + __IO uint32_t FR3; /*!< PP Function Register 3 */ + __IO uint32_t FR4; /*!< PP Function Register 4 */ + uint32_t RESERVED0[4]; + __IO uint32_t OD; /*!< PP Open Drain Control Register */ + __IO uint32_t PUP; /*!< PP Pull-up Control Register */ + __IO uint32_t PDN; /*!< PP Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PP Input Enable Control Register */ +} TSB_PP_TypeDef; + +/** + * @brief Port R + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PR Data Register */ + __IO uint32_t CR; /*!< PR Control Register */ + uint32_t RESERVED0[2]; + __IO uint32_t FR3; /*!< PR Function Register 3 */ + __IO uint32_t FR4; /*!< PR Function Register 4 */ + uint32_t RESERVED1[4]; + __IO uint32_t OD; /*!< PR Open Drain Control Register */ + __IO uint32_t PUP; /*!< PR Pull-up Control Register */ + __IO uint32_t PDN; /*!< PR Pull-Down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< PR Input Enable Control Register */ +} TSB_PR_TypeDef; + +/** + * @brief Port T + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PT Data Register */ + __IO uint32_t CR; /*!< PT Control Register */ + __IO uint32_t FR1; /*!< PT Function Register 1 */ + __IO uint32_t FR2; /*!< PT Function Register 2 */ + __IO uint32_t FR3; /*!< PT Function Register 3 */ + __IO uint32_t FR4; /*!< PT Function Register 4 */ + uint32_t RESERVED0[4]; + __IO uint32_t OD; /*!< PT Open Drain Control Register */ + __IO uint32_t PUP; /*!< PT Pull-up Control Register */ + __IO uint32_t PDN; /*!< PT Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PT Input Enable Control Register */ +} TSB_PT_TypeDef; + +/** + * @brief Port U + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PU Data Register */ + __IO uint32_t CR; /*!< PU Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PU Open Drain Control Register */ + __IO uint32_t PUP; /*!< PU Pull-up Control Register */ + __IO uint32_t PDN; /*!< PU Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PU Input Enable Control Register */ +} TSB_PU_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t DATA; /*!< PV Data Register */ + __IO uint32_t CR; /*!< PV Control Register */ + __IO uint32_t FR1; /*!< PV Function Register 1 */ + __IO uint32_t FR2; /*!< PV Function Register 2 */ + uint32_t RESERVED0[6]; + __IO uint32_t OD; /*!< PV Open Drain Control Register */ + __IO uint32_t PUP; /*!< PV Pull-up Control Register */ + __IO uint32_t PDN; /*!< PV Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PV Input Enable Control Register */ +} TSB_PV_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint8_t SECR; /*!< RTC Sec setting register */ + __IO uint8_t MINR; /*!< RTC Min settging register */ + __IO uint8_t HOURR; /*!< RTC Hour setting register */ + uint8_t RESERVED0; + __IO uint8_t DAYR; /*!< RTC Day setting register */ + __IO uint8_t DATER; /*!< RTC Date setting register */ + __IO uint8_t MONTHR; /*!< RTC Month settging register PAGE0 */ + __IO uint8_t YEARR; /*!< RTC Year setting register PAGE0 */ + __IO uint8_t PAGER; /*!< RTC Page register */ + uint8_t RESERVED1[3]; + __IO uint8_t RESTR; /*!< RTC Reset register */ + uint8_t RESERVED2; + __IO uint8_t PROTECT; /*!< RTC protect register */ + __IO uint8_t ADJCTL; /*!< RTC clock adjust control register */ + __IO uint8_t ADJDAT; /*!< RTC clock adjust data register */ + __IO uint8_t ADJSIGN; /*!< RTC clock adjust sign register */ +} TSB_RTC_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t EN; /*!< RMC Enable Register */ + __IO uint32_t REN; /*!< RMC Receive Enable Register */ + __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ + __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ + __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ + __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ + __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ + __I uint32_t RSTAT; /*!< RMC Receive Status Register */ + __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ + __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ + __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ + __IO uint32_t FSSEL; /*!< RMC Frequency Selection Register */ +} TSB_RMC_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t CR1; /*!< OFD Control Register 1 */ + __IO uint32_t CR2; /*!< OFD Control Register 2 */ + __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ + __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ + __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ + __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ + __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ + __I uint32_t STAT; /*!< OFD Status Register */ + __IO uint32_t MON; /*!< OFD External high frequency oscillaion clock monitor register */ +} TSB_OFD_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t PROTECT; /*!< CG Protect Register */ + __IO uint32_t OSCCR; /*!< CG Oscillation Control Register */ + __IO uint32_t SYSCR; /*!< CG System clock control register */ + __IO uint32_t STBYCR; /*!< CG Standby Control Register */ + __IO uint32_t SCOCR; /*!< CG SCOUT Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t PLL0SEL; /*!< CG PLL select register for fsys */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< CG Warmup register for HOSC */ + __IO uint32_t WUPLCR; /*!< CG Low-speed oscillation warm-up register */ + uint32_t RESERVED2[6]; + __IO uint32_t FSYSENA; /*!< CG output control register A for fsys clock */ + __IO uint32_t FSYSENB; /*!< CG output control register B for fsys clock */ + __IO uint32_t FCEN; /*!< CG output control register for fc clock */ + __IO uint32_t SPCLKEN; /*!< CG Output control register for ADC AND TRACE CLOCK*/ +} TSB_CG_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t OSCPRO; /*!< TRM Protect register */ + __IO uint32_t OSCEN; /*!< TRM Enable register */ + __I uint32_t OSCINIT; /*!< TRM Initial trimming level monitor register */ + __IO uint32_t OSCSET; /*!< TRM Trimming level setting register */ +} TSB_TRM_TypeDef; + +/** + * @brief Interrupt control register B + */ +typedef struct +{ + uint8_t RESERVED0[16]; + __IO uint8_t NIC00; /*!< Non makeable Interrupt Control(B) 00 */ + uint8_t RESERVED1[79]; + __IO uint8_t IMC000; /*!< Interrupu Mode Control Register(B) 000 */ + __IO uint8_t IMC001; /*!< Interrupu Mode Control Register(B) 001 */ + __IO uint8_t IMC002; /*!< Interrupu Mode Control Register(B) 002 */ + __IO uint8_t IMC003; /*!< Interrupu Mode Control Register(B) 003 */ + __IO uint8_t IMC004; /*!< Interrupu Mode Control Register(B) 004 */ + __IO uint8_t IMC005; /*!< Interrupu Mode Control Register(B) 005 */ + __IO uint8_t IMC006; /*!< Interrupu Mode Control Register(B) 006 */ + __IO uint8_t IMC007; /*!< Interrupu Mode Control Register(B) 007 */ + __IO uint8_t IMC008; /*!< Interrupu Mode Control Register(B) 008 */ + __IO uint8_t IMC009; /*!< Interrupu Mode Control Register(B) 009 */ + __IO uint8_t IMC010; /*!< Interrupu Mode Control Register(B) 010 */ + __IO uint8_t IMC011; /*!< Interrupu Mode Control Register(B) 011 */ + __IO uint8_t IMC012; /*!< Interrupu Mode Control Register(B) 012 */ + __IO uint8_t IMC013; /*!< Interrupu Mode Control Register(B) 013 */ + __IO uint8_t IMC014; /*!< Interrupu Mode Control Register(B) 014 */ + __IO uint8_t IMC015; /*!< Interrupu Mode Control Register(B) 015 */ + __IO uint8_t IMC016; /*!< Interrupu Mode Control Register(B) 016 */ + __IO uint8_t IMC017; /*!< Interrupu Mode Control Register(B) 017 */ + __IO uint8_t IMC018; /*!< Interrupu Mode Control Register(B) 018 */ + __IO uint8_t IMC019; /*!< Interrupu Mode Control Register(B) 019 */ + __IO uint8_t IMC020; /*!< Interrupu Mode Control Register(B) 020 */ + __IO uint8_t IMC021; /*!< Interrupu Mode Control Register(B) 021 */ + __IO uint8_t IMC022; /*!< Interrupu Mode Control Register(B) 022 */ + __IO uint8_t IMC023; /*!< Interrupu Mode Control Register(B) 023 */ + __IO uint8_t IMC024; /*!< Interrupu Mode Control Register(B) 024 */ + __IO uint8_t IMC025; /*!< Interrupu Mode Control Register(B) 025 */ + __IO uint8_t IMC026; /*!< Interrupu Mode Control Register(B) 026 */ + __IO uint8_t IMC027; /*!< Interrupu Mode Control Register(B) 027 */ + __IO uint8_t IMC028; /*!< Interrupu Mode Control Register(B) 028 */ + __IO uint8_t IMC029; /*!< Interrupu Mode Control Register(B) 029 */ + __IO uint8_t IMC030; /*!< Interrupu Mode Control Register(B) 030 */ + __IO uint8_t IMC031; /*!< Interrupu Mode Control Register(B) 031 */ + __IO uint8_t IMC032; /*!< Interrupu Mode Control Register(B) 032 */ + __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ + __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ + __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ + __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ + __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ + __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ + __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ + __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ + __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ + __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ + __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ + __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ + __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ + __IO uint8_t IMC046; /*!< Interrupt Mode Control Register(B) 046 */ + __IO uint8_t IMC047; /*!< Interrupt Mode Control Register(B) 047 */ + __IO uint8_t IMC048; /*!< Interrupt Mode Control Register(B) 048 */ + __IO uint8_t IMC049; /*!< Interrupt Mode Control Register(B) 049 */ + __IO uint8_t IMC050; /*!< Interrupt Mode Control Register(B) 050 */ + __IO uint8_t IMC051; /*!< Interrupt Mode Control Register(B) 051 */ + __IO uint8_t IMC052; /*!< Interrupt Mode Control Register(B) 052 */ + __IO uint8_t IMC053; /*!< Interrupt Mode Control Register(B) 053 */ + __IO uint8_t IMC054; /*!< Interrupt Mode Control Register(B) 054 */ + __IO uint8_t IMC055; /*!< Interrupt Mode Control Register(B) 055 */ + __IO uint8_t IMC056; /*!< Interrupt Mode Control Register(B) 056 */ + __IO uint8_t IMC057; /*!< Interrupt Mode Control Register(B) 057 */ + __IO uint8_t IMC058; /*!< Interrupt Mode Control Register(B) 058 */ + __IO uint8_t IMC059; /*!< Interrupt Mode Control Register(B) 059 */ + __IO uint8_t IMC060; /*!< Interrupt Mode Control Register(B) 060 */ + __IO uint8_t IMC061; /*!< Interrupt Mode Control Register(B) 061 */ + __IO uint8_t IMC062; /*!< Interrupt Mode Control Register(B) 062 */ + __IO uint8_t IMC063; /*!< Interrupt Mode Control Register(B) 063 */ + __IO uint8_t IMC064; /*!< Interrupt Mode Control Register(B) 064 */ + __IO uint8_t IMC065; /*!< Interrupt Mode Control Register(B) 065 */ + __IO uint8_t IMC066; /*!< Interrupu Mode Control Register(B) 066 */ + __IO uint8_t IMC067; /*!< Interrupu Mode Control Register(B) 067 */ + __IO uint8_t IMC068; /*!< Interrupu Mode Control Register(B) 068 */ + __IO uint8_t IMC069; /*!< Interrupu Mode Control Register(B) 069 */ + __IO uint8_t IMC070; /*!< Interrupu Mode Control Register(B) 070 */ + __IO uint8_t IMC071; /*!< Interrupu Mode Control Register(B) 071 */ + __IO uint8_t IMC072; /*!< Interrupu Mode Control Register(B) 072 */ + __IO uint8_t IMC073; /*!< Interrupu Mode Control Register(B) 073 */ + __IO uint8_t IMC074; /*!< Interrupu Mode Control Register(B) 074 */ + __IO uint8_t IMC075; /*!< Interrupu Mode Control Register(B) 075 */ + __IO uint8_t IMC076; /*!< Interrupu Mode Control Register(B) 076 */ + __IO uint8_t IMC077; /*!< Interrupu Mode Control Register(B) 077 */ + __IO uint8_t IMC078; /*!< Interrupu Mode Control Register(B) 078 */ + __IO uint8_t IMC079; /*!< Interrupu Mode Control Register(B) 079 */ + __IO uint8_t IMC080; /*!< Interrupu Mode Control Register(B) 080 */ + __IO uint8_t IMC081; /*!< Interrupu Mode Control Register(B) 081 */ + __IO uint8_t IMC082; /*!< Interrupu Mode Control Register(B) 082 */ + __IO uint8_t IMC083; /*!< Interrupu Mode Control Register(B) 083 */ + __IO uint8_t IMC084; /*!< Interrupu Mode Control Register(B) 084 */ + __IO uint8_t IMC085; /*!< Interrupu Mode Control Register(B) 085 */ + __IO uint8_t IMC086; /*!< Interrupu Mode Control Register(B) 086 */ + __IO uint8_t IMC087; /*!< Interrupu Mode Control Register(B) 087 */ + __IO uint8_t IMC088; /*!< Interrupu Mode Control Register(B) 088 */ + __IO uint8_t IMC089; /*!< Interrupu Mode Control Register(B) 089 */ + __IO uint8_t IMC090; /*!< Interrupu Mode Control Register(B) 090 */ + __IO uint8_t IMC091; /*!< Interrupu Mode Control Register(B) 091 */ + __IO uint8_t IMC092; /*!< Interrupu Mode Control Register(B) 092 */ + __IO uint8_t IMC093; /*!< Interrupu Mode Control Register(B) 093 */ + __IO uint8_t IMC094; /*!< Interrupu Mode Control Register(B) 094 */ +} TSB_IB_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __I uint32_t FLGNMI; /*!< Interrupt Monitor Flag 0 */ + __I uint32_t FLG1; /*!< Interrupt Monitor Flag 1 */ + uint32_t RESERVED0; + __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 */ + __I uint32_t FLG4; /*!< NMI Interrupt Monitor Flag 4 */ + __I uint32_t FLG5; /*!< NMI Interrupt Monitor Flag 5 */ +} TSB_IMN_TypeDef; + +/** + * @brief + */ +typedef struct +{ + __IO uint32_t MDEN; /*!< PMD Enable Register */ + __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ + __IO uint32_t MDCR; /*!< PMD Control Register */ + __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ + __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ + __IO uint32_t RATE; /*!< PWM Frequency Register */ + __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ + __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ + __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ + uint32_t RESERVED0; + __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ + __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ + __O uint32_t EMGREL; /*!< PMD EMG Release Register */ + __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ + __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ + __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ + __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ + __IO uint32_t DTR; /*!< PMD Dead Time Register */ + __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ + __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ + __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ + __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ + __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ + __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ + __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ + __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ + __IO uint32_t VPWMPH; /*!< Phase difference setting of the V-phase PWM */ + __IO uint32_t WPWMPH; /*!< Phase difference setting of the W-phase PWM */ + __IO uint32_t MBUFCR; /*!< Update timing of the triple buffer */ + uint32_t RESERVED1; + __IO uint32_t DBGOUTCR; /*!< Debug output control */ +} TSB_PMD_TypeDef; + +/** + * @brief Encoder Input (ENC) + */ +typedef struct +{ + __IO uint32_t TNCR; /*!< ENC Control Register */ + __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ + __IO uint32_t INT; /*!< ENC INT Compare Register */ + __IO uint32_t CNT; /*!< ENC Counter/Capture Register */ + __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ + __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ + __I uint32_t STS; /*!< ENC Status Register */ + __IO uint32_t INPCR; /*!< ENC Input Process Cntrol Register */ + __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ + __I uint32_t INPMON; /*!< ENC Input Moniter Register */ + __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ + __IO uint32_t INTCR; /*!< ENC Interrupt Reqyest Control Register */ + __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ +} TSB_EN_TypeDef; + +/** + * @brief + */ +typedef struct +{ + uint32_t RESERVED0[4]; + __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ + __IO uint32_t SSR; /*!< Flash Security Status Register */ + __O uint32_t KCR; /*!< Flash Key Code Register */ + uint32_t RESERVED1; + __IO uint32_t SR0; /*!< Flash Status Register 0 */ + uint32_t RESERVED2[3]; + __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ + __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ + uint32_t RESERVED3[4]; + __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ + uint32_t RESERVED4; + __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ + __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ + uint32_t RESERVED5[4]; + __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ + uint32_t RESERVED6[37]; + __I uint32_t SR1; /*!< Flash Status Register 1 */ + __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ + uint32_t RESERVED7[14]; + __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ + uint32_t RESERVED8; + __IO uint32_t CR; /*!< Flash Control Register */ + __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ + __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ + uint32_t RESERVED9; + __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ +} TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) +#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) +#define TSB_I2CS_BASE (PERI_BASE + 0x003E800UL) +#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) +#define TSB_DMAA_BASE (PERI_BASE + 0x004C000UL) +#define TSB_DMAB_BASE (PERI_BASE + 0x004D000UL) +#define TSB_DA0_BASE (PERI_BASE + 0x0054000UL) +#define TSB_DA1_BASE (PERI_BASE + 0x0055000UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) +#define TSB_TSPI1_BASE (PERI_BASE + 0x0099000UL) +#define TSB_TSPI2_BASE (PERI_BASE + 0x009A000UL) +#define TSB_TSPI3_BASE (PERI_BASE + 0x009B000UL) +#define TSB_TSPI4_BASE (PERI_BASE + 0x009C000UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) +#define TSB_I2C2_BASE (PERI_BASE + 0x00A2000UL) +#define TSB_I2C3_BASE (PERI_BASE + 0x00A3000UL) +#define TSB_ADA_BASE (PERI_BASE + 0x00B8800UL) +#define TSB_T32A0_BASE (PERI_BASE + 0x00BA000UL) +#define TSB_T32A1_BASE (PERI_BASE + 0x00BA100UL) +#define TSB_T32A2_BASE (PERI_BASE + 0x00BA200UL) +#define TSB_T32A3_BASE (PERI_BASE + 0x00BA300UL) +#define TSB_T32A4_BASE (PERI_BASE + 0x00BA400UL) +#define TSB_T32A5_BASE (PERI_BASE + 0x00BA500UL) +#define TSB_T32A6_BASE (PERI_BASE + 0x00BA600UL) +#define TSB_T32A7_BASE (PERI_BASE + 0x00BA700UL) +#define TSB_UART0_BASE (PERI_BASE + 0x00BB000UL) +#define TSB_UART1_BASE (PERI_BASE + 0x00BB100UL) +#define TSB_UART2_BASE (PERI_BASE + 0x00BB200UL) +#define TSB_UART3_BASE (PERI_BASE + 0x00BB300UL) +#define TSB_UART4_BASE (PERI_BASE + 0x00BBD00UL) +#define TSB_UART5_BASE (PERI_BASE + 0x00BBE00UL) +#define TSB_SIWD0_BASE (PERI_BASE + 0x00BB400UL) +#define TSB_DNFA_BASE (PERI_BASE + 0x00BB600UL) +#define TSB_DNFB_BASE (PERI_BASE + 0x00BB700UL) +#define TSB_TSEL0_BASE (PERI_BASE + 0x00BB800UL) +#define TSB_TSEL1_BASE (PERI_BASE + 0x00BB900UL) +#define TSB_RPAR_BASE (PERI_BASE + 0x00BBB00UL) +#define TSB_CRC_BASE (PERI_BASE + 0x00BBC00UL) +#define TSB_CMP_BASE (PERI_BASE + 0x00BC100UL) +#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) +#define TSB_PK_BASE (PERI_BASE + 0x00C0900UL) +#define TSB_PL_BASE (PERI_BASE + 0x00C0A00UL) +#define TSB_PM_BASE (PERI_BASE + 0x00C0B00UL) +#define TSB_PN_BASE (PERI_BASE + 0x00C0C00UL) +#define TSB_PP_BASE (PERI_BASE + 0x00C0D00UL) +#define TSB_PR_BASE (PERI_BASE + 0x00C0E00UL) +#define TSB_PT_BASE (PERI_BASE + 0x00C0F00UL) +#define TSB_PU_BASE (PERI_BASE + 0x00C1000UL) +#define TSB_PV_BASE (PERI_BASE + 0x00C1100UL) +#define TSB_RTC_BASE (PERI_BASE + 0x00CC000UL) +#define TSB_RMC0_BASE (PERI_BASE + 0x00E7000UL) +#define TSB_OFD_BASE (PERI_BASE + 0x00F1000UL) +#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) +#define TSB_TRM_BASE (PERI_BASE + 0x00F3200UL) +#define TSB_IB_BASE (PERI_BASE + 0x00F4E00UL) +#define TSB_IMN_BASE (PERI_BASE + 0x00F4F00UL) +#define TSB_PMD0_BASE (PERI_BASE + 0x00F6000UL) +#define TSB_EN0_BASE (PERI_BASE + 0x00F7000UL) +#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) + + +/* Peripheral declaration */ +#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) +#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) +#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) +#define TSB_DMAB (( TSB_DMA_TypeDef *) TSB_DMAB_BASE) +#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) +#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) +#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) +#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) +#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) +#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) +#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) +#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) +#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) +#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) +#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) +#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) +#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) +#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) +#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) +#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) +#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) +#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) +#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) +#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) +#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) +#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) +#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) +#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) +#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) +#define TSB_TSEL1 (( TSB_TSEL_TypeDef *) TSB_TSEL1_BASE) +#define TSB_RPAR (( TSB_RPAR_TypeDef *) TSB_RPAR_BASE) +#define TSB_CRC (( TSB_CRC_TypeDef *) TSB_CRC_BASE) +#define TSB_CMP (( TSB_CMP_TypeDef *) TSB_CMP_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) +#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) +#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) +#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) +#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) +#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) +#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) +#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) +#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) +#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) +#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) +#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) +#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) +#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) +#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) +#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + + + + + +/* DMA Controller */ +#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) +#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) +#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) + +#define TSB_DMAB_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAB->STATUS,0))) +#define TSB_DMAB_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAB->CFG,0))) +#define TSB_DMAB_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAB->ERRCLR,0))) + + +/* Digital analog converter (DAC) */ +#define TSB_DA0_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CTL,0))) + +#define TSB_DA1_CTL_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CTL,0))) + + +/* Serial Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,16))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) +#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) +#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) +#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) +#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) + +#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) +#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) +#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) +#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) +#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) +#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) +#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) +#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) +#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) +#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) +#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) +#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) +#define TSB_TSPI1_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,16))) +#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) +#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) +#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) +#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) +#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) +#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) +#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) +#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) +#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) +#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) +#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) +#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) +#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) +#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) +#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) +#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) +#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) +#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) +#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) +#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) +#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) +#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) +#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) +#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) +#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) + +#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) +#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) +#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) +#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) +#define TSB_TSPI2_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) +#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) +#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) +#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) +#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) +#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) +#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) +#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) +#define TSB_TSPI2_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,16))) +#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) +#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) +#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) +#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) +#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) +#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) +#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) +#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) +#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) +#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) +#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) +#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) +#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) +#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) +#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) +#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) +#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) +#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) +#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) +#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) +#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) +#define TSB_TSPI2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,0))) +#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) +#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) +#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) + +#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) +#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) +#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) +#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) +#define TSB_TSPI3_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) +#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) +#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) +#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) +#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) +#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) +#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) +#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) +#define TSB_TSPI3_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,16))) +#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) +#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) +#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) +#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) +#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) +#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) +#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) +#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) +#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) +#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) +#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) +#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) +#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) +#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) +#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) +#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) +#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) +#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) +#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) +#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) +#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) +#define TSB_TSPI3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,0))) +#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) +#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) +#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) + +#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) +#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) +#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) +#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) +#define TSB_TSPI4_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) +#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) +#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) +#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) +#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) +#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) +#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) +#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) +#define TSB_TSPI4_CR2_RXDLY (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,16))) +#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) +#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) +#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) +#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) +#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) +#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) +#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) +#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) +#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) +#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) +#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) +#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) +#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) +#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) +#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) +#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) +#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) +#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) +#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) +#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) +#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) +#define TSB_TSPI4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,0))) +#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) +#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) +#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) + + +/* I2C */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + +#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) +#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) +#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) +#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) +#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) +#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) +#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) +#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) +#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) +#define TSB_I2C2_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) +#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) +#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) +#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) +#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) +#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) +#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) +#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) +#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) +#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) +#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) +#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) +#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) +#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) +#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) +#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) +#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) +#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) +#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) +#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) +#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) +#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) +#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) +#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) +#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) +#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) +#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) +#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) +#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) + +#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) +#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) +#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) +#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) +#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) +#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) +#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) +#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) +#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) +#define TSB_I2C3_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) +#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) +#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) +#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) +#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) +#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) +#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) +#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) +#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) +#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) +#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) +#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) +#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) +#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) +#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) +#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) +#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) +#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) +#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) +#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) +#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) +#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) +#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) +#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) +#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) +#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) +#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) +#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) +#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) + + +/* ADC */ +#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) +#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) +#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) +#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) +#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) +#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) +#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) +#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) +#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) +#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) +#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) +#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) +#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) +#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) +#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) +#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) +#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) +#define TSB_ADA_CMPCR0_COMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) +#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) +#define TSB_ADA_CMPCR1_COMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) +#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) +#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) +#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) +#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) +#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) +#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) +#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) +#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) +#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) +#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) +#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) +#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) +#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) +#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) +#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) +#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) +#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) +#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) +#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) +#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) +#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) +#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) +#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) +#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) +#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) +#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) +#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) +#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) +#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) +#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) +#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) +#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) +#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) +#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) +#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) +#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) +#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) +#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) +#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) +#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) +#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) +#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) +#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) +#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) +#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) +#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) +#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) +#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) +#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) +#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) +#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) +#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) +#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) +#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) +#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) +#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) +#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) +#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) +#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) +#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) +#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) +#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) +#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) +#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) +#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) +#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) +#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) +#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) +#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) +#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) +#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) +#define TSB_ADA_REG0_ADOVR_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) +#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) +#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) +#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) +#define TSB_ADA_REG1_ADOVR_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) +#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) +#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) +#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) +#define TSB_ADA_REG2_ADOVR_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) +#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) +#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) +#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) +#define TSB_ADA_REG3_ADOVR_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) +#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) +#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) +#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) +#define TSB_ADA_REG4_ADOVR_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) +#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) +#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) +#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) +#define TSB_ADA_REG5_ADOVR_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) +#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) +#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) +#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) +#define TSB_ADA_REG6_ADOVR_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) +#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) +#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) +#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) +#define TSB_ADA_REG7_ADOVR_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) +#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) +#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) +#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) +#define TSB_ADA_REG8_ADOVR_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) +#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) +#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) +#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) +#define TSB_ADA_REG9_ADOVR_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) +#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) +#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) +#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) +#define TSB_ADA_REG10_ADOVR_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) +#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) +#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) +#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) +#define TSB_ADA_REG11_ADOVR_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) +#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) +#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) +#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) +#define TSB_ADA_REG12_ADOVR_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) +#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) +#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) +#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) +#define TSB_ADA_REG13_ADOVR_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) +#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) +#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) +#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) +#define TSB_ADA_REG14_ADOVR_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) +#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) +#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) +#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) +#define TSB_ADA_REG15_ADOVR_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) +#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) +#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) +#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) +#define TSB_ADA_REG16_ADOVR_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) +#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) +#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) +#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) +#define TSB_ADA_REG17_ADOVR_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) +#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) +#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) +#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) +#define TSB_ADA_REG18_ADOVR_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) +#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) +#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) +#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) +#define TSB_ADA_REG19_ADOVR_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) +#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) +#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) +#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) +#define TSB_ADA_REG20_ADOVR_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) +#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) +#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) +#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) +#define TSB_ADA_REG21_ADOVR_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) +#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) +#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) +#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) +#define TSB_ADA_REG22_ADOVR_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) +#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) +#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) +#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) +#define TSB_ADA_REG23_ADOVR_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) + + +/* T32A */ +#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) +#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) +#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) +#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) +#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) +#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) +#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) +#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) +#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) +#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) +#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) +#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) +#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) +#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) +#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) +#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) +#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) +#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) +#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) +#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) +#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) +#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) +#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) +#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) +#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) +#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) +#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) +#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) +#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) +#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) +#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) +#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) +#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) +#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) +#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) +#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) +#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) +#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) +#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) +#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) +#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) +#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) +#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) +#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) +#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) +#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) +#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) +#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) +#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) +#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) +#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) +#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) +#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) +#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) + +#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) +#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) +#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) +#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) +#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) +#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) +#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) +#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) +#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) +#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) +#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) +#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) +#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) +#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) +#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) +#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) +#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) +#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) +#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) +#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) +#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) +#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) +#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) +#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) +#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) +#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) +#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) +#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) +#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) +#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) +#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) +#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) +#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) +#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) +#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) +#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) +#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) +#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) +#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) +#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) +#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) +#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) +#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) +#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) +#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) +#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) +#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) +#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) +#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) +#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) +#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) +#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) +#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) +#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) + +#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) +#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) +#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) +#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) +#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) +#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) +#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) +#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) +#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) +#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) +#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) +#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) +#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) +#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) +#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) +#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) +#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) +#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) +#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) +#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) +#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) +#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) +#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) +#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) +#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) +#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) +#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) +#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) +#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) +#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) +#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) +#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) +#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) +#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) +#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) +#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) +#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) +#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) +#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) +#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) +#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) +#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) +#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) +#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) +#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) +#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) +#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) +#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) +#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) +#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) +#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) +#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) +#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) +#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) + +#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) +#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) +#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) +#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) +#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) +#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) +#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) +#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) +#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) +#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) +#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) +#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) +#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) +#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) +#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) +#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) +#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) +#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) +#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) +#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) +#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) +#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) +#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) +#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) +#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) +#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) +#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) +#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) +#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) +#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) +#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) +#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) +#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) +#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) +#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) +#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) +#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) +#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) +#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) +#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) +#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) +#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) +#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) +#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) +#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) +#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) +#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) +#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) +#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) +#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) +#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) +#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) +#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) +#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) + +#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) +#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) +#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) +#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) +#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) +#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) +#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) +#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) +#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) +#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) +#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) +#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) +#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) +#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) +#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) +#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) +#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) +#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) +#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) +#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) +#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) +#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) +#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) +#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) +#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) +#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) +#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) +#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) +#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) +#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) +#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) +#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) +#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) +#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) +#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) +#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) +#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) +#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) +#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) +#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) +#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) +#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) +#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) +#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) +#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) +#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) +#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) +#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) +#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) +#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) +#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) +#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) +#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) +#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) + +#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) +#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) +#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) +#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) +#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) +#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) +#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) +#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) +#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) +#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) +#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) +#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) +#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) +#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) +#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) +#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) +#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) +#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) +#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) +#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) +#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) +#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) +#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) +#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) +#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) +#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) +#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) +#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) +#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) +#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) +#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) +#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) +#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) +#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) +#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) +#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) +#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) +#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) +#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) +#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) +#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) +#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) +#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) +#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) +#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) +#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) +#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) +#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) +#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) +#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) +#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) +#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) +#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) +#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) + +#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) +#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) +#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) +#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) +#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) +#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) +#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) +#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) +#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) +#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) +#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) +#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) +#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) +#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) +#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) +#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) +#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) +#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) +#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) +#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) +#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) +#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) +#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) +#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) +#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) +#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) +#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) +#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) +#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) +#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) +#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) +#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) +#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) +#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) +#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) +#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) +#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) +#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) +#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) +#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) +#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) +#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) +#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) +#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) +#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) +#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) +#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) +#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) +#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) +#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) +#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) +#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) +#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) +#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) + +#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) +#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) +#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) +#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) +#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) +#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) +#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) +#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) +#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) +#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) +#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) +#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) +#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) +#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) +#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) +#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) +#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) +#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) +#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) +#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) +#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) +#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) +#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) +#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) +#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) +#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) +#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) +#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) +#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) +#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) +#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) +#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) +#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) +#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) +#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) +#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) +#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) +#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) +#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) +#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) +#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) +#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) +#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) +#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) +#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) +#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) +#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) +#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) +#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) +#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) +#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) +#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) +#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) +#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) + + +/* UART */ +#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) +#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) +#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) +#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) +#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) +#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) +#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) +#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) +#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) +#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) +#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) +#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) +#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) +#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) +#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) +#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) +#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) +#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) +#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) +#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) +#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) +#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) +#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) +#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) +#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) +#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) +#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) +#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) +#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) +#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) +#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) +#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) +#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) +#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) +#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) +#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) +#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) +#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) +#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) +#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) +#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) +#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) + +#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) +#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) +#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) +#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) +#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) +#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) +#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) +#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) +#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) +#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) +#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) +#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) +#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) +#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) +#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) +#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) +#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) +#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) +#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) +#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) +#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) +#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) +#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) +#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) +#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) +#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) +#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) +#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) +#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) +#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) +#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) +#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) +#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) +#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) +#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) +#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) +#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) +#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) +#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) +#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) +#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) +#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) + +#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) +#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) +#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) +#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) +#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) +#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) +#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) +#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) +#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) +#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) +#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) +#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) +#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) +#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) +#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) +#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) +#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) +#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) +#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) +#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) +#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) +#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) +#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) +#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) +#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) +#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) +#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) +#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) +#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) +#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) +#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) +#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) +#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) +#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) +#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) +#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) +#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) +#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) +#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) +#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) +#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) +#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) + +#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) +#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) +#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) +#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) +#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) +#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) +#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) +#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) +#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) +#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) +#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) +#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) +#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) +#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) +#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) +#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) +#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) +#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) +#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) +#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) +#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) +#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) +#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) +#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) +#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) +#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) +#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) +#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) +#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) +#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) +#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) +#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) +#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) +#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) +#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) +#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) +#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) +#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) +#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) +#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) +#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) +#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) + +#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) +#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) +#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) +#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) +#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) +#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) +#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) +#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) +#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) +#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) +#define TSB_UART4_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,16))) +#define TSB_UART4_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,17))) +#define TSB_UART4_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,18))) +#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) +#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) +#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) +#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) +#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) +#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) +#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) +#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) +#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) +#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) +#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) +#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) +#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) +#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) +#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) +#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) +#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) +#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) +#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) +#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) +#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) +#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) +#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) +#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) +#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) +#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) +#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) +#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) +#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) + +#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) +#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) +#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) +#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) +#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) +#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) +#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) +#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) +#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) +#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) +#define TSB_UART5_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,16))) +#define TSB_UART5_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,17))) +#define TSB_UART5_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,18))) +#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) +#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) +#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) +#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) +#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) +#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) +#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) +#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) +#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) +#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) +#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) +#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) +#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) +#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) +#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) +#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) +#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) +#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) +#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) +#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) +#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) +#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) +#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) +#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) +#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) +#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) +#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) +#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) +#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) + + +/* SIWD */ +#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) +#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) +#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) +#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) +#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) + + +/* DNF */ +#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) +#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) +#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) +#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) +#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) +#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) +#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) +#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) +#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) +#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) +#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) +#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) +#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) +#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) +#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) +#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) + +#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) +#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) +#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) +#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) +#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) +#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) +#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) +#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) +#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) +#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) +#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) +#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) +#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) +#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) +#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) +#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) + + +/* TRGSEL */ +#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) +#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) +#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) +#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) +#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) +#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) +#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) +#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) +#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) +#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) +#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) +#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) +#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) +#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) +#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) +#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) +#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) +#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) +#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) +#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) +#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) +#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) +#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) +#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) +#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) +#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) +#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) +#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) +#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) +#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) +#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) +#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) +#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) +#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) +#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) +#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) +#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) +#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) +#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) +#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) +#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) +#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) +#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) +#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) +#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) +#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) +#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) +#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) +#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) +#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) +#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) +#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) +#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) +#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) +#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) +#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) +#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) +#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) +#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) +#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) +#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) +#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) +#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) +#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) +#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) +#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) +#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) +#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) +#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) +#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) +#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) +#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) +#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) +#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) +#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) +#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) +#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) +#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) +#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) +#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) +#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) +#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) +#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) +#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) +#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) +#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) +#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) +#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) +#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) +#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) +#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) +#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) +#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) +#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) +#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) +#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) +#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) +#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) +#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) +#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) +#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) +#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) +#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) +#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) +#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) +#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) +#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) +#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) +#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) +#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) +#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) +#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) +#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) +#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) +#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) +#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) +#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) +#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) +#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) +#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) +#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) +#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) +#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) +#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) +#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) +#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) +#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) +#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) +#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) +#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) +#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) +#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) +#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) +#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) +#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) +#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) +#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) +#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) +#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) +#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) +#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) +#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) +#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) +#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) +#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) +#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) +#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) +#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) +#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) +#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) +#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) +#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) +#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) +#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) +#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) +#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) +#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) +#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) +#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) +#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) +#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) +#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) +#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) +#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) +#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) +#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) +#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) +#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) +#define TSB_TSEL0_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,0))) +#define TSB_TSEL0_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,1))) +#define TSB_TSEL0_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,2))) +#define TSB_TSEL0_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,8))) +#define TSB_TSEL0_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,9))) +#define TSB_TSEL0_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,10))) +#define TSB_TSEL0_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,16))) +#define TSB_TSEL0_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,17))) +#define TSB_TSEL0_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,18))) +#define TSB_TSEL0_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,24))) +#define TSB_TSEL0_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,25))) +#define TSB_TSEL0_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,26))) +#define TSB_TSEL0_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,0))) +#define TSB_TSEL0_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,1))) +#define TSB_TSEL0_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,2))) +#define TSB_TSEL0_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,8))) +#define TSB_TSEL0_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,9))) +#define TSB_TSEL0_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,10))) +#define TSB_TSEL0_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,16))) +#define TSB_TSEL0_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,17))) +#define TSB_TSEL0_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,18))) +#define TSB_TSEL0_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,24))) +#define TSB_TSEL0_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,25))) +#define TSB_TSEL0_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR15,26))) + +#define TSB_TSEL1_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,0))) +#define TSB_TSEL1_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,1))) +#define TSB_TSEL1_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,2))) +#define TSB_TSEL1_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,8))) +#define TSB_TSEL1_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,9))) +#define TSB_TSEL1_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,10))) +#define TSB_TSEL1_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,16))) +#define TSB_TSEL1_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,17))) +#define TSB_TSEL1_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,18))) +#define TSB_TSEL1_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,24))) +#define TSB_TSEL1_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,25))) +#define TSB_TSEL1_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR0,26))) +#define TSB_TSEL1_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,0))) +#define TSB_TSEL1_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,1))) +#define TSB_TSEL1_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,2))) +#define TSB_TSEL1_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,8))) +#define TSB_TSEL1_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,9))) +#define TSB_TSEL1_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,10))) +#define TSB_TSEL1_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,16))) +#define TSB_TSEL1_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,17))) +#define TSB_TSEL1_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,18))) +#define TSB_TSEL1_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,24))) +#define TSB_TSEL1_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,25))) +#define TSB_TSEL1_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR1,26))) +#define TSB_TSEL1_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,0))) +#define TSB_TSEL1_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,1))) +#define TSB_TSEL1_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,2))) +#define TSB_TSEL1_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,8))) +#define TSB_TSEL1_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,9))) +#define TSB_TSEL1_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,10))) +#define TSB_TSEL1_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,16))) +#define TSB_TSEL1_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,17))) +#define TSB_TSEL1_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,18))) +#define TSB_TSEL1_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,24))) +#define TSB_TSEL1_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,25))) +#define TSB_TSEL1_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR2,26))) +#define TSB_TSEL1_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,0))) +#define TSB_TSEL1_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,1))) +#define TSB_TSEL1_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,2))) +#define TSB_TSEL1_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,8))) +#define TSB_TSEL1_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,9))) +#define TSB_TSEL1_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,10))) +#define TSB_TSEL1_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,16))) +#define TSB_TSEL1_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,17))) +#define TSB_TSEL1_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,18))) +#define TSB_TSEL1_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,24))) +#define TSB_TSEL1_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,25))) +#define TSB_TSEL1_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR3,26))) +#define TSB_TSEL1_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,0))) +#define TSB_TSEL1_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,1))) +#define TSB_TSEL1_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,2))) +#define TSB_TSEL1_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,8))) +#define TSB_TSEL1_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,9))) +#define TSB_TSEL1_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,10))) +#define TSB_TSEL1_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,16))) +#define TSB_TSEL1_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,17))) +#define TSB_TSEL1_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,18))) +#define TSB_TSEL1_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,24))) +#define TSB_TSEL1_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,25))) +#define TSB_TSEL1_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR4,26))) +#define TSB_TSEL1_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,0))) +#define TSB_TSEL1_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,1))) +#define TSB_TSEL1_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,2))) +#define TSB_TSEL1_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,8))) +#define TSB_TSEL1_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,9))) +#define TSB_TSEL1_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,10))) +#define TSB_TSEL1_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,16))) +#define TSB_TSEL1_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,17))) +#define TSB_TSEL1_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,18))) +#define TSB_TSEL1_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,24))) +#define TSB_TSEL1_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,25))) +#define TSB_TSEL1_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR5,26))) +#define TSB_TSEL1_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,0))) +#define TSB_TSEL1_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,1))) +#define TSB_TSEL1_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,2))) +#define TSB_TSEL1_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,8))) +#define TSB_TSEL1_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,9))) +#define TSB_TSEL1_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,10))) +#define TSB_TSEL1_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,16))) +#define TSB_TSEL1_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,17))) +#define TSB_TSEL1_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,18))) +#define TSB_TSEL1_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,24))) +#define TSB_TSEL1_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,25))) +#define TSB_TSEL1_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR6,26))) +#define TSB_TSEL1_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,0))) +#define TSB_TSEL1_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,1))) +#define TSB_TSEL1_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,2))) +#define TSB_TSEL1_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,8))) +#define TSB_TSEL1_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,9))) +#define TSB_TSEL1_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,10))) +#define TSB_TSEL1_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,16))) +#define TSB_TSEL1_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,17))) +#define TSB_TSEL1_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,18))) +#define TSB_TSEL1_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,24))) +#define TSB_TSEL1_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,25))) +#define TSB_TSEL1_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR7,26))) +#define TSB_TSEL1_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,0))) +#define TSB_TSEL1_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,1))) +#define TSB_TSEL1_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,2))) +#define TSB_TSEL1_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,8))) +#define TSB_TSEL1_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,9))) +#define TSB_TSEL1_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,10))) +#define TSB_TSEL1_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,16))) +#define TSB_TSEL1_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,17))) +#define TSB_TSEL1_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,18))) +#define TSB_TSEL1_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,24))) +#define TSB_TSEL1_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,25))) +#define TSB_TSEL1_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR8,26))) +#define TSB_TSEL1_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,0))) +#define TSB_TSEL1_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,1))) +#define TSB_TSEL1_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,2))) +#define TSB_TSEL1_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,8))) +#define TSB_TSEL1_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,9))) +#define TSB_TSEL1_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,10))) +#define TSB_TSEL1_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,16))) +#define TSB_TSEL1_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,17))) +#define TSB_TSEL1_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,18))) +#define TSB_TSEL1_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,24))) +#define TSB_TSEL1_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,25))) +#define TSB_TSEL1_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR9,26))) +#define TSB_TSEL1_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,0))) +#define TSB_TSEL1_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,1))) +#define TSB_TSEL1_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,2))) +#define TSB_TSEL1_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,8))) +#define TSB_TSEL1_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,9))) +#define TSB_TSEL1_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,10))) +#define TSB_TSEL1_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,16))) +#define TSB_TSEL1_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,17))) +#define TSB_TSEL1_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,18))) +#define TSB_TSEL1_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,24))) +#define TSB_TSEL1_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,25))) +#define TSB_TSEL1_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR10,26))) +#define TSB_TSEL1_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,0))) +#define TSB_TSEL1_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,1))) +#define TSB_TSEL1_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,2))) +#define TSB_TSEL1_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,8))) +#define TSB_TSEL1_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,9))) +#define TSB_TSEL1_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,10))) +#define TSB_TSEL1_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,16))) +#define TSB_TSEL1_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,17))) +#define TSB_TSEL1_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,18))) +#define TSB_TSEL1_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,24))) +#define TSB_TSEL1_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,25))) +#define TSB_TSEL1_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR11,26))) +#define TSB_TSEL1_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,0))) +#define TSB_TSEL1_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,1))) +#define TSB_TSEL1_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,2))) +#define TSB_TSEL1_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,8))) +#define TSB_TSEL1_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,9))) +#define TSB_TSEL1_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,10))) +#define TSB_TSEL1_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,16))) +#define TSB_TSEL1_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,17))) +#define TSB_TSEL1_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,18))) +#define TSB_TSEL1_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,24))) +#define TSB_TSEL1_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,25))) +#define TSB_TSEL1_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR12,26))) +#define TSB_TSEL1_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,0))) +#define TSB_TSEL1_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,1))) +#define TSB_TSEL1_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,2))) +#define TSB_TSEL1_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,8))) +#define TSB_TSEL1_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,9))) +#define TSB_TSEL1_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,10))) +#define TSB_TSEL1_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,16))) +#define TSB_TSEL1_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,17))) +#define TSB_TSEL1_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,18))) +#define TSB_TSEL1_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,24))) +#define TSB_TSEL1_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,25))) +#define TSB_TSEL1_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR13,26))) +#define TSB_TSEL1_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,0))) +#define TSB_TSEL1_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,1))) +#define TSB_TSEL1_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,2))) +#define TSB_TSEL1_CR14_EN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,8))) +#define TSB_TSEL1_CR14_OUTSEL57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,9))) +#define TSB_TSEL1_CR14_UPDN57 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,10))) +#define TSB_TSEL1_CR14_EN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,16))) +#define TSB_TSEL1_CR14_OUTSEL58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,17))) +#define TSB_TSEL1_CR14_UPDN58 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,18))) +#define TSB_TSEL1_CR14_EN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,24))) +#define TSB_TSEL1_CR14_OUTSEL59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,25))) +#define TSB_TSEL1_CR14_UPDN59 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR14,26))) +#define TSB_TSEL1_CR15_EN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,0))) +#define TSB_TSEL1_CR15_OUTSEL60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,1))) +#define TSB_TSEL1_CR15_UPDN60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,2))) +#define TSB_TSEL1_CR15_EN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,8))) +#define TSB_TSEL1_CR15_OUTSEL61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,9))) +#define TSB_TSEL1_CR15_UPDN61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,10))) +#define TSB_TSEL1_CR15_EN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,16))) +#define TSB_TSEL1_CR15_OUTSEL62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,17))) +#define TSB_TSEL1_CR15_UPDN62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,18))) +#define TSB_TSEL1_CR15_EN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,24))) +#define TSB_TSEL1_CR15_OUTSEL63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,25))) +#define TSB_TSEL1_CR15_UPDN63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL1->CR15,26))) + + +/* RAM Parity */ +#define TSB_RPAR_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,0))) +#define TSB_RPAR_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR->CTL,1))) +#define TSB_RPAR_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,0))) +#define TSB_RPAR_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,1))) +#define TSB_RPAR_ST_RPARFG2 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,2))) +#define TSB_RPAR_ST_RPARFG3 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR->ST,3))) +#define TSB_RPAR_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,0))) +#define TSB_RPAR_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,1))) +#define TSB_RPAR_CLR_RPARCLR2 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,2))) +#define TSB_RPAR_CLR_RPARCLR3 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR->CLR,3))) + + + +/* CMP */ +#define TSB_CMP_CTRLA_CMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,0))) +#define TSB_CMP_CTRLA_CMPISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CMP->CTRLA,1))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) +#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) +#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) +#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) +#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) +#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) +#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) +#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) +#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) +#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) +#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) +#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) +#define TSB_PA_FR2_PA1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,1))) +#define TSB_PA_FR2_PA2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,2))) +#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) +#define TSB_PA_FR2_PA6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,6))) +#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) +#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) +#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) +#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) +#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) +#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) +#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) +#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) +#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) +#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) +#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) +#define TSB_PA_FR4_PA5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,5))) +#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) +#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) +#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) +#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) +#define TSB_PA_FR6_PA1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,1))) +#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) +#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) +#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) +#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) +#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) +#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) +#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) +#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) +#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) +#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) +#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) +#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) +#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) +#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) +#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) +#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) +#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) +#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) +#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) +#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) +#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) +#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) +#define TSB_PB_FR2_PB2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,2))) +#define TSB_PB_FR2_PB3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,3))) +#define TSB_PB_FR2_PB4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,4))) +#define TSB_PB_FR2_PB5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,5))) +#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) +#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) +#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) +#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) +#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) +#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) +#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) +#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) +#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) +#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) +#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) +#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) +#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) +#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) +#define TSB_PB_FR5_PB5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,5))) +#define TSB_PB_FR6_PB0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,0))) +#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) +#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) +#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) +#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) +#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) +#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) +#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) +#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) +#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) +#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) +#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) +#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) +#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) +#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) + + +/* Port C */ +#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) +#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) +#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) +#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) +#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) +#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) +#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) +#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) +#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) +#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) +#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) +#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) +#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) +#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) +#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) +#define TSB_PC_FR2_PC3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,3))) +#define TSB_PC_FR2_PC4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,4))) +#define TSB_PC_FR2_PC5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,5))) +#define TSB_PC_FR2_PC6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,6))) +#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) +#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) +#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) +#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) +#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) +#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) +#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) +#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) +#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) +#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) +#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) +#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) +#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) +#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) +#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) +#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) +#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) +#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) +#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) +#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) +#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) +#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) +#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) +#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) +#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) +#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) +#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) +#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) +#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) +#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) +#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) +#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) +#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) +#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) +#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) +#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) + + +/* Port F */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) +#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) +#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) +#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) +#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) +#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) +#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) +#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) +#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) +#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) +#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) +#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) +#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) +#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) + + +/* Port G */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) +#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) +#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) +#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) +#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) +#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) +#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) +#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) +#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) +#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) +#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) +#define TSB_PG_FR1_PG2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,2))) +#define TSB_PG_FR1_PG3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,3))) +#define TSB_PG_FR1_PG4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,4))) +#define TSB_PG_FR2_PG2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,2))) +#define TSB_PG_FR2_PG3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,3))) +#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) +#define TSB_PG_FR3_PG3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) +#define TSB_PG_FR3_PG4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,4))) +#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) +#define TSB_PG_FR3_PG6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,6))) +#define TSB_PG_FR3_PG7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,7))) +#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) +#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) +#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) +#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) +#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) +#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) +#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) +#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) +#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) +#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) +#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) +#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) +#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) +#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) +#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) +#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) +#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) +#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) +#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) +#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) +#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) +#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) +#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) +#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) + + +/* Port H */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) +#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) +#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) +#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) +#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) +#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) +#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) +#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) +#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) +#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) +#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) +#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) +#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) +#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) +#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) +#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) +#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) +#define TSB_PH_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) +#define TSB_PH_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) +#define TSB_PH_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) +#define TSB_PH_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) +#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) +#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) +#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) +#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) +#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) +#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) +#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) +#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) +#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) +#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) +#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) + + +/* Port J */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) +#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) +#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) +#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) +#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) +#define TSB_PJ_FR1_PJ2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,2))) +#define TSB_PJ_FR1_PJ3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,3))) +#define TSB_PJ_FR1_PJ4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,4))) +#define TSB_PJ_FR2_PJ1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,1))) +#define TSB_PJ_FR2_PJ2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,2))) +#define TSB_PJ_FR2_PJ3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,3))) +#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) +#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) +#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) +#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) +#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) +#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) +#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) +#define TSB_PJ_FR4_PJ0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,0))) +#define TSB_PJ_FR4_PJ1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,1))) +#define TSB_PJ_FR4_PJ2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR4,2))) +#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) +#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) +#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) +#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) +#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) +#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) +#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) +#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) +#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) +#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) +#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) + + +/* Port K */ +#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) +#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) +#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) +#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) +#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) +#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) +#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) +#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) +#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) +#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) +#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) +#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) +#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) +#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) +#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) +#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) +#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) +#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) +#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) +#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) +#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) +#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) +#define TSB_PK_FR2_PK2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,2))) +#define TSB_PK_FR2_PK3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,3))) +#define TSB_PK_FR2_PK4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,4))) +#define TSB_PK_FR3_PK2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,2))) +#define TSB_PK_FR3_PK3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,3))) +#define TSB_PK_FR3_PK4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,4))) +#define TSB_PK_FR3_PK5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,5))) +#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) +#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) +#define TSB_PK_FR4_PK2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,2))) +#define TSB_PK_FR4_PK3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,3))) +#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) +#define TSB_PK_FR5_PK0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,0))) +#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) +#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) +#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) +#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) +#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) +#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) +#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) +#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) +#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) +#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) +#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) +#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) +#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) +#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) +#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) +#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) +#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) +#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) +#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) +#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) +#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) +#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) +#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) +#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) +#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) +#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) +#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) +#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) +#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) +#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) +#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) +#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) +#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) + + +/* Port L */ +#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) +#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) +#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) +#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) +#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) +#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) +#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) +#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) +#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) +#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) +#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) +#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) +#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) +#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) +#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) +#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) +#define TSB_PL_FR1_PL0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,0))) +#define TSB_PL_FR1_PL1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,1))) +#define TSB_PL_FR1_PL2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,2))) +#define TSB_PL_FR1_PL3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,3))) +#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) +#define TSB_PL_FR2_PL1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,1))) +#define TSB_PL_FR2_PL2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,2))) +#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) +#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) +#define TSB_PL_FR3_PL1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,1))) +#define TSB_PL_FR3_PL2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,2))) +#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) +#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) +#define TSB_PL_FR3_PL5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,5))) +#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) +#define TSB_PL_FR3_PL7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,7))) +#define TSB_PL_FR4_PL5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,5))) +#define TSB_PL_FR4_PL6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,6))) +#define TSB_PL_FR4_PL7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,7))) +#define TSB_PL_FR5_PL0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,0))) +#define TSB_PL_FR5_PL1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1))) +#define TSB_PL_FR5_PL2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2))) +#define TSB_PL_FR5_PL3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3))) +#define TSB_PL_FR5_PL4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,4))) +#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) +#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) +#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) +#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) +#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) +#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) +#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) +#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) +#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) +#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) +#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) +#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) +#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) +#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) +#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) +#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) +#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) +#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) +#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) +#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) +#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) +#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) +#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) +#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) +#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) +#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) +#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) +#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) +#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) +#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) +#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) +#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) + + +/* Port M */ +#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) +#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) +#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) +#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) +#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) +#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) +#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) +#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) +#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) +#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) +#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) +#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) +#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) +#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) +#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) +#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) +#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) +#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) +#define TSB_PM_FR1_PM2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,2))) +#define TSB_PM_FR1_PM3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,3))) +#define TSB_PM_FR1_PM4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,4))) +#define TSB_PM_FR2_PM1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,1))) +#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) +#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) +#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) +#define TSB_PM_FR3_PM0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,0))) +#define TSB_PM_FR3_PM1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,1))) +#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) +#define TSB_PM_FR3_PM3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,3))) +#define TSB_PM_FR3_PM4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,4))) +#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) +#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) +#define TSB_PM_FR4_PM2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,2))) +#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) +#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) +#define TSB_PM_FR4_PM5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,5))) +#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) +#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) +#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) +#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) +#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) +#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) +#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) +#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) +#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) +#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) +#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) +#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) +#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) +#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) +#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) +#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) +#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) +#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) +#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) +#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) +#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) +#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) +#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) +#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) +#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) +#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) +#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) +#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) +#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) +#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) +#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) +#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) +#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) +#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) +#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) +#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) +#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) +#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) +#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) +#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) +#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) + + +/* Port N */ +#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) +#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) +#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) +#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) +#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) +#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) +#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) +#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) +#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) +#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) +#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) +#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) +#define TSB_PN_FR1_PN0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,0))) +#define TSB_PN_FR1_PN1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,1))) +#define TSB_PN_FR1_PN2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,2))) +#define TSB_PN_FR1_PN3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,3))) +#define TSB_PN_FR1_PN4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,4))) +#define TSB_PN_FR2_PN0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,0))) +#define TSB_PN_FR2_PN1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,1))) +#define TSB_PN_FR2_PN2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,2))) +#define TSB_PN_FR2_PN3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,3))) +#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) +#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) +#define TSB_PN_FR3_PN2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,2))) +#define TSB_PN_FR3_PN3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,3))) +#define TSB_PN_FR3_PN4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,4))) +#define TSB_PN_FR3_PN5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,5))) +#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) +#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) +#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) +#define TSB_PN_FR5_PN3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,3))) +#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) +#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) +#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) +#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) +#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) +#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) +#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) +#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) +#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) +#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) +#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) +#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) +#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) +#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) +#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) +#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) +#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) +#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) +#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) +#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) +#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) +#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) +#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) +#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) + + +/* Port P */ +#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) +#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) +#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) +#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) +#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) +#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) +#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) +#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) +#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) +#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) +#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) +#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) +#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) +#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) +#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) +#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) +#define TSB_PP_FR1_PP3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,3))) +#define TSB_PP_FR1_PP4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,4))) +#define TSB_PP_FR1_PP5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,5))) +#define TSB_PP_FR1_PP6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,6))) +#define TSB_PP_FR1_PP7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR1,7))) +#define TSB_PP_FR2_PP0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) +#define TSB_PP_FR2_PP1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) +#define TSB_PP_FR2_PP2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) +#define TSB_PP_FR2_PP6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) +#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) +#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) +#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) +#define TSB_PP_FR3_PP6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) +#define TSB_PP_FR4_PP0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,0))) +#define TSB_PP_FR4_PP1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,1))) +#define TSB_PP_FR4_PP2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR4,2))) +#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) +#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) +#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) +#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) +#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) +#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) +#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) +#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) +#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) +#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) +#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) +#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) +#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) +#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) +#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) +#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) +#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) +#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) +#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) +#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) +#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) +#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) +#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) +#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) +#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) +#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) +#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) +#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) +#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) +#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) +#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) +#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) + + +/* Port R */ +#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) +#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) +#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) +#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) +#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) +#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) +#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) +#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) +#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) +#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) +#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) +#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) +#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) +#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) +#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) +#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) +#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) +#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) +#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) +#define TSB_PR_FR4_PR0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,0))) +#define TSB_PR_FR4_PR1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,1))) +#define TSB_PR_FR4_PR2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR4,2))) +#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) +#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) +#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) +#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) +#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) +#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) +#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) +#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) +#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) +#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) +#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) +#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) +#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) +#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) +#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) +#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) +#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) +#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) +#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) +#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) +#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) +#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) +#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) +#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) +#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) +#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) +#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) +#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) +#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) +#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) +#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) +#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) + + +/* Port T */ +#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) +#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) +#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) +#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) +#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) +#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) +#define TSB_PT_DATA_PT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,6))) +#define TSB_PT_DATA_PT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,7))) +#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) +#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) +#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) +#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) +#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) +#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) +#define TSB_PT_CR_PT6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,6))) +#define TSB_PT_CR_PT7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,7))) +#define TSB_PT_FR1_PT0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,0))) +#define TSB_PT_FR1_PT1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,1))) +#define TSB_PT_FR1_PT2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,2))) +#define TSB_PT_FR1_PT3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) +#define TSB_PT_FR1_PT4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,4))) +#define TSB_PT_FR2_PT0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,0))) +#define TSB_PT_FR2_PT1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,1))) +#define TSB_PT_FR3_PT1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,1))) +#define TSB_PT_FR3_PT2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,2))) +#define TSB_PT_FR3_PT3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) +#define TSB_PT_FR3_PT4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,4))) +#define TSB_PT_FR3_PT5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,5))) +#define TSB_PT_FR3_PT6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,6))) +#define TSB_PT_FR3_PT7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,7))) +#define TSB_PT_FR4_PT5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,5))) +#define TSB_PT_FR4_PT6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,6))) +#define TSB_PT_FR4_PT7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR4,7))) +#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) +#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) +#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) +#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) +#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) +#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) +#define TSB_PT_OD_PT6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,6))) +#define TSB_PT_OD_PT7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,7))) +#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) +#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) +#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) +#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) +#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) +#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) +#define TSB_PT_PUP_PT6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,6))) +#define TSB_PT_PUP_PT7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,7))) +#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) +#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) +#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) +#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) +#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) +#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) +#define TSB_PT_PDN_PT6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,6))) +#define TSB_PT_PDN_PT7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,7))) +#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) +#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) +#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) +#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) +#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) +#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) +#define TSB_PT_IE_PT6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,6))) +#define TSB_PT_IE_PT7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,7))) + + +/* Port U */ +#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) +#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) +#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) +#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) +#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) +#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) +#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) +#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) +#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) +#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) +#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) +#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) +#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) +#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) +#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) +#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) +#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) +#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) +#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) +#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) +#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) +#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) +#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) +#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) +#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) +#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) +#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) +#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) +#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) +#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) +#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) +#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) +#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) +#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) +#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) +#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) + + +/* */ +#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) +#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) +#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) +#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) +#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) +#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) +#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) +#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) +#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) +#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) +#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) +#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) +#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) +#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) +#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) +#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) +#define TSB_PV_FR1_PV5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,5))) +#define TSB_PV_FR1_PV6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,6))) +#define TSB_PV_FR1_PV7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,7))) +#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) +#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) +#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) +#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) +#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) +#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) +#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) +#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) +#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) +#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) +#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) +#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) +#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) +#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) +#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) +#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) +#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) +#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) +#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) +#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) +#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) +#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) +#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) +#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) +#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) +#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) +#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) +#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) +#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) +#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) +#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) +#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) +#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) +#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) + + +/* */ +#define TSB_RTC_ADJCTL_AJEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJCTL,0))) +#define TSB_RTC_ADJSIGN_ADJSIGN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJSIGN,0))) + + +/* */ +#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) +#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) +#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) +#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) +#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) +#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) +#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) +#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) +#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) +#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) +#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) +#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) +#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) + + +/* */ +#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) +#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) +#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) +#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) + + +/* */ +#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_IHOSC2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,3))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) +#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) +#define TSB_CG_SCOCR_SCOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SCOCR,0))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) +#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) +#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) +#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) +#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) +#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) +#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) +#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) +#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) +#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) +#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) +#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) +#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) +#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) +#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) +#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) +#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) +#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) +#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) +#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) +#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) +#define TSB_CG_FSYSENA_IPENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,19))) +#define TSB_CG_FSYSENA_IPENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,20))) +#define TSB_CG_FSYSENA_IPENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,21))) +#define TSB_CG_FSYSENA_IPENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,22))) +#define TSB_CG_FSYSENA_IPENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,23))) +#define TSB_CG_FSYSENA_IPENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,24))) +#define TSB_CG_FSYSENA_IPENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,25))) +#define TSB_CG_FSYSENA_IPENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,26))) +#define TSB_CG_FSYSENA_IPENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,27))) +#define TSB_CG_FSYSENA_IPENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,28))) +#define TSB_CG_FSYSENA_IPENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,29))) +#define TSB_CG_FSYSENA_IPENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,30))) +#define TSB_CG_FSYSENA_IPENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,31))) +#define TSB_CG_FSYSENB_IPENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,0))) +#define TSB_CG_FSYSENB_IPENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,1))) +#define TSB_CG_FSYSENB_IPENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,2))) +#define TSB_CG_FSYSENB_IPENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,3))) +#define TSB_CG_FSYSENB_IPENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,4))) +#define TSB_CG_FSYSENB_IPENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,5))) +#define TSB_CG_FSYSENB_IPENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,6))) +#define TSB_CG_FSYSENB_IPENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,7))) +#define TSB_CG_FSYSENB_IPENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,8))) +#define TSB_CG_FSYSENB_IPENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,9))) +#define TSB_CG_FSYSENB_IPENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,10))) +#define TSB_CG_FSYSENB_IPENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,11))) +#define TSB_CG_FSYSENB_IPENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,12))) +#define TSB_CG_FSYSENB_IPENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,13))) +#define TSB_CG_FSYSENB_IPENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,14))) +#define TSB_CG_FSYSENB_IPENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,15))) +#define TSB_CG_FSYSENB_IPENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,16))) +#define TSB_CG_FSYSENB_IPENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,17))) +#define TSB_CG_FSYSENB_IPENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,18))) +#define TSB_CG_FSYSENB_IPENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,19))) +#define TSB_CG_FSYSENB_IPENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,20))) +#define TSB_CG_FSYSENB_IPENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,21))) +#define TSB_CG_FSYSENB_IPENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,22))) +#define TSB_CG_FSYSENB_IPENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,23))) +#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) +#define TSB_CG_FCEN_FCIPEN07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,7))) +#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) +#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) + + +/* */ +#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) + + + +/* */ +#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) +#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) +#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) +#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) +#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) +#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) +#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) +#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) +#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) +#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) +#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) +#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) +#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) +#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) +#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) +#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) +#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) +#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) +#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) +#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) +#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) +#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) +#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) +#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) +#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) +#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) +#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) +#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) +#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) +#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) +#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) +#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) +#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) +#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) +#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) +#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) +#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) +#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) +#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) +#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) +#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) +#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) +#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) +#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) +#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) +#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) +#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) +#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) +#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) +#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) +#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) +#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) +#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) +#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) +#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) +#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) +#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) +#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) +#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) +#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) +#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) +#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) +#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) +#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) +#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) +#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) +#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) +#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) +#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) +#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) +#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) +#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) +#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) +#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) +#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) +#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) +#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) +#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) +#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) +#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) +#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) +#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) +#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) +#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) +#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) +#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) +#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) +#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) +#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) +#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) +#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) +#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) +#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) +#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) +#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) +#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) +#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) +#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) +#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) +#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) +#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) +#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) +#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) + + +/* */ +#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) +#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) +#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) +#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) +#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) +#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) +#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) +#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) +#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) +#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) +#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) +#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) +#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) +#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) +#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) +#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) +#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) +#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) +#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) +#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) +#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) +#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) +#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) +#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) +#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) +#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) +#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) +#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) +#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) +#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) +#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) +#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) +#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) +#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) +#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) +#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) +#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) +#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) +#define TSB_PMD0_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,0))) +#define TSB_PMD0_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,3))) +#define TSB_PMD0_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,4))) +#define TSB_PMD0_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,8))) +#define TSB_PMD0_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,9))) +#define TSB_PMD0_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,10))) +#define TSB_PMD0_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,12))) +#define TSB_PMD0_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,16))) +#define TSB_PMD0_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,17))) +#define TSB_PMD0_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,18))) +#define TSB_PMD0_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,19))) +#define TSB_PMD0_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,20))) +#define TSB_PMD0_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,21))) +#define TSB_PMD0_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,31))) + + +/* Encoder Input (ENC) */ +#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) +#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) +#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) +#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) +#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) +#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) +#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) +#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) +#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) +#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) +#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) +#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) +#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) +#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) +#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) +#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) +#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) +#define TSB_EN0_INPCR_SYNCSPLND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) +#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) +#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) +#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) +#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) +#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) +#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) +#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) +#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) +#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) +#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) +#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) +#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) +#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) +#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) +#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) +#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) +#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) +#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) +#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) +#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) +#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) + +/** @} */ /* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM3HQ_H__ */ + +/** @} */ /* End of group TMPM3HQ */ +/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S new file mode 100644 index 0000000000..2e3b80ca0c --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S @@ -0,0 +1,614 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM3HQ.s +; * @brief CMSIS Cortex-M3 Core Device Startup File for the +; * TOSHIBA 'TMPM3HQ' Device Series +; * @version V1.0.0.0 +; * $Date:: 2017-12-08 #$ +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ +__initial_sp EQU 0x20010000 + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt Pin 00 + DCD INT01_IRQHandler ; 1: Interrupt Pin 01 + DCD INT02_IRQHandler ; 2: Interrupt Pin 02 + DCD INT03_IRQHandler ; 3: Interrupt Pin 03 + DCD INT04_IRQHandler ; 4: Interrupt Pin 04 + DCD INT05_IRQHandler ; 5: Interrupt Pin 05 + DCD INT06_IRQHandler ; 6: Interrupt Pin 06 + DCD INT07_IRQHandler ; 7: Interrupt Pin 07 + DCD INT08_IRQHandler ; 8: Interrupt Pin 08 + DCD INT09_IRQHandler ; 9: Interrupt Pin 09 + DCD INT10_IRQHandler ; 10: Interrupt Pin 10 + DCD INT11_IRQHandler ; 11: Interrupt Pin 11 + DCD INT12_IRQHandler ; 12: Interrupt Pin 12 + DCD INT13_IRQHandler ; 13: Interrupt Pin 13 + DCD INT14_IRQHandler ; 14: Interrupt Pin 14 + DCD INT15_IRQHandler ; 15: Interrupt Pin 15 + DCD INT16_IRQHandler ; 16: Interrupt Pin 16 + DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 + DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 + DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 + DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 + DCD INT29_IRQHandler ; 21: Interrupt Pin 29 + DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 + DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt + DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt + DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 + DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 + DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A + DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B + DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished + DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) + DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) + DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) + DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) + DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) + DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) + DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) + DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) + DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) + DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) + DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) + DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) + DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) + DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) + DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) + DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) + DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt + DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt + DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt + DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt + DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt + DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt + DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt + DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt + DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt + DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt + DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt + DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt + DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt + DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt + DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt + DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt + DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) + DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) + DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) + DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) + DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) + DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) + DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) + DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) + DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) + DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) + DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) + DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) + DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) + DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) + DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) + DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) + DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) + DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) + DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow + DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 + DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 + DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow + DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 + DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 + DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow + DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 + DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 + DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow + DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 + DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 + DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow + DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 + DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 + DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow + DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 + DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 + DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow + DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 + DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 + DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow + DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 + DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 + DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow + DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 + DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 + DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow + DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 + DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 + DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow + DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 + DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 + DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow + DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 + DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 + DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow + DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 + DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 + DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow + DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 + DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 + DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow + DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 + DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 + DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow + DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 + DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 + DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow + DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 + DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 + DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow + DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 + DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 + DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow + DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 + DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 + DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow + DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 + DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 + DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow + DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 + DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 + DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow + DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 + DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 + DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow + DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 + DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 + DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow + DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 + DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 + DCD INTPARI_IRQHandler ; 157: RAM parity interrupt + DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer + DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error + DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer + DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error + DCD INTRTC_IRQHandler ; 162: Real time clock interrupt + DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt + DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt + DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INT16_IRQHandler [WEAK] + EXPORT INT17_18_IRQHandler [WEAK] + EXPORT INT19_22_IRQHandler [WEAK] + EXPORT INT23_26_IRQHandler [WEAK] + EXPORT INT27_28_IRQHandler [WEAK] + EXPORT INT29_IRQHandler [WEAK] + EXPORT INT30_31_IRQHandler [WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTPMD0_IRQHandler [WEAK] + EXPORT INTENC00_IRQHandler [WEAK] + EXPORT INTENC01_IRQHandler [WEAK] + EXPORT INTADAPDA_IRQHandler [WEAK] + EXPORT INTADAPDB_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTT0RX_IRQHandler [WEAK] + EXPORT INTT0TX_IRQHandler [WEAK] + EXPORT INTT0ERR_IRQHandler [WEAK] + EXPORT INTT1RX_IRQHandler [WEAK] + EXPORT INTT1TX_IRQHandler [WEAK] + EXPORT INTT1ERR_IRQHandler [WEAK] + EXPORT INTT2RX_IRQHandler [WEAK] + EXPORT INTT2TX_IRQHandler [WEAK] + EXPORT INTT2ERR_IRQHandler [WEAK] + EXPORT INTT3RX_IRQHandler [WEAK] + EXPORT INTT3TX_IRQHandler [WEAK] + EXPORT INTT3ERR_IRQHandler [WEAK] + EXPORT INTT4RX_IRQHandler [WEAK] + EXPORT INTT4TX_IRQHandler [WEAK] + EXPORT INTT4ERR_IRQHandler [WEAK] + EXPORT INTI2CWUP_IRQHandler [WEAK] + EXPORT INTI2C0_IRQHandler [WEAK] + EXPORT INTI2C0AL_IRQHandler [WEAK] + EXPORT INTI2C0BF_IRQHandler [WEAK] + EXPORT INTI2C0NA_IRQHandler [WEAK] + EXPORT INTI2C1_IRQHandler [WEAK] + EXPORT INTI2C1AL_IRQHandler [WEAK] + EXPORT INTI2C1BF_IRQHandler [WEAK] + EXPORT INTI2C1NA_IRQHandler [WEAK] + EXPORT INTI2C2_IRQHandler [WEAK] + EXPORT INTI2C2AL_IRQHandler [WEAK] + EXPORT INTI2C2BF_IRQHandler [WEAK] + EXPORT INTI2C2NA_IRQHandler [WEAK] + EXPORT INTI2C3_IRQHandler [WEAK] + EXPORT INTI2C3AL_IRQHandler [WEAK] + EXPORT INTI2C3BF_IRQHandler [WEAK] + EXPORT INTI2C3NA_IRQHandler [WEAK] + EXPORT INTUART0RX_IRQHandler [WEAK] + EXPORT INTUART0TX_IRQHandler [WEAK] + EXPORT INTUART0ERR_IRQHandler [WEAK] + EXPORT INTUART1RX_IRQHandler [WEAK] + EXPORT INTUART1TX_IRQHandler [WEAK] + EXPORT INTUART1ERR_IRQHandler [WEAK] + EXPORT INTUART2RX_IRQHandler [WEAK] + EXPORT INTUART2TX_IRQHandler [WEAK] + EXPORT INTUART2ERR_IRQHandler [WEAK] + EXPORT INTUART3RX_IRQHandler [WEAK] + EXPORT INTUART3TX_IRQHandler [WEAK] + EXPORT INTUART3ERR_IRQHandler [WEAK] + EXPORT INTUART4RX_IRQHandler [WEAK] + EXPORT INTUART4TX_IRQHandler [WEAK] + EXPORT INTUART4ERR_IRQHandler [WEAK] + EXPORT INTUART5RX_IRQHandler [WEAK] + EXPORT INTUART5TX_IRQHandler [WEAK] + EXPORT INTUART5ERR_IRQHandler [WEAK] + EXPORT INTT32A00A_IRQHandler [WEAK] + EXPORT INTT32A00ACAP0_IRQHandler [WEAK] + EXPORT INTT32A00ACAP1_IRQHandler [WEAK] + EXPORT INTT32A00B_IRQHandler [WEAK] + EXPORT INTT32A00BCAP0_IRQHandler [WEAK] + EXPORT INTT32A00BCAP1_IRQHandler [WEAK] + EXPORT INTT32A00C_IRQHandler [WEAK] + EXPORT INTT32A00CCAP0_IRQHandler [WEAK] + EXPORT INTT32A00CCAP1_IRQHandler [WEAK] + EXPORT INTT32A01A_IRQHandler [WEAK] + EXPORT INTT32A01ACAP0_IRQHandler [WEAK] + EXPORT INTT32A01ACAP1_IRQHandler [WEAK] + EXPORT INTT32A01B_IRQHandler [WEAK] + EXPORT INTT32A01BCAP0_IRQHandler [WEAK] + EXPORT INTT32A01BCAP1_IRQHandler [WEAK] + EXPORT INTT32A01C_IRQHandler [WEAK] + EXPORT INTT32A01CCAP0_IRQHandler [WEAK] + EXPORT INTT32A01CCAP1_IRQHandler [WEAK] + EXPORT INTT32A02A_IRQHandler [WEAK] + EXPORT INTT32A02ACAP0_IRQHandler [WEAK] + EXPORT INTT32A02ACAP1_IRQHandler [WEAK] + EXPORT INTT32A02B_IRQHandler [WEAK] + EXPORT INTT32A02BCAP0_IRQHandler [WEAK] + EXPORT INTT32A02BCAP1_IRQHandler [WEAK] + EXPORT INTT32A02C_IRQHandler [WEAK] + EXPORT INTT32A02CCAP0_IRQHandler [WEAK] + EXPORT INTT32A02CCAP1_IRQHandler [WEAK] + EXPORT INTT32A03A_IRQHandler [WEAK] + EXPORT INTT32A03ACAP0_IRQHandler [WEAK] + EXPORT INTT32A03ACAP1_IRQHandler [WEAK] + EXPORT INTT32A03B_IRQHandler [WEAK] + EXPORT INTT32A03BCAP0_IRQHandler [WEAK] + EXPORT INTT32A03BCAP1_IRQHandler [WEAK] + EXPORT INTT32A03C_IRQHandler [WEAK] + EXPORT INTT32A03CCAP0_IRQHandler [WEAK] + EXPORT INTT32A03CCAP1_IRQHandler [WEAK] + EXPORT INTT32A04A_IRQHandler [WEAK] + EXPORT INTT32A04ACAP0_IRQHandler [WEAK] + EXPORT INTT32A04ACAP1_IRQHandler [WEAK] + EXPORT INTT32A04B_IRQHandler [WEAK] + EXPORT INTT32A04BCAP0_IRQHandler [WEAK] + EXPORT INTT32A04BCAP1_IRQHandler [WEAK] + EXPORT INTT32A04C_IRQHandler [WEAK] + EXPORT INTT32A04CCAP0_IRQHandler [WEAK] + EXPORT INTT32A04CCAP1_IRQHandler [WEAK] + EXPORT INTT32A05A_IRQHandler [WEAK] + EXPORT INTT32A05ACAP0_IRQHandler [WEAK] + EXPORT INTT32A05ACAP1_IRQHandler [WEAK] + EXPORT INTT32A05B_IRQHandler [WEAK] + EXPORT INTT32A05BCAP0_IRQHandler [WEAK] + EXPORT INTT32A05BCAP1_IRQHandler [WEAK] + EXPORT INTT32A05C_IRQHandler [WEAK] + EXPORT INTT32A05CCAP0_IRQHandler [WEAK] + EXPORT INTT32A05CCAP1_IRQHandler [WEAK] + EXPORT INTT32A06A_IRQHandler [WEAK] + EXPORT INTT32A06ACAP0_IRQHandler [WEAK] + EXPORT INTT32A06ACAP1_IRQHandler [WEAK] + EXPORT INTT32A06B_IRQHandler [WEAK] + EXPORT INTT32A06BCAP0_IRQHandler [WEAK] + EXPORT INTT32A06BCAP1_IRQHandler [WEAK] + EXPORT INTT32A06C_IRQHandler [WEAK] + EXPORT INTT32A06CCAP0_IRQHandler [WEAK] + EXPORT INTT32A06CCAP1_IRQHandler [WEAK] + EXPORT INTT32A07A_IRQHandler [WEAK] + EXPORT INTT32A07ACAP0_IRQHandler [WEAK] + EXPORT INTT32A07ACAP1_IRQHandler [WEAK] + EXPORT INTT32A07B_IRQHandler [WEAK] + EXPORT INTT32A07BCAP0_IRQHandler [WEAK] + EXPORT INTT32A07BCAP1_IRQHandler [WEAK] + EXPORT INTT32A07C_IRQHandler [WEAK] + EXPORT INTT32A07CCAP0_IRQHandler [WEAK] + EXPORT INTT32A07CCAP1_IRQHandler [WEAK] + EXPORT INTPARI_IRQHandler [WEAK] + EXPORT INTDMAATC_IRQHandler [WEAK] + EXPORT INTDMAAERR_IRQHandler [WEAK] + EXPORT INTDMABTC_IRQHandler [WEAK] + EXPORT INTDMABERR_IRQHandler [WEAK] + EXPORT INTRTC_IRQHandler [WEAK] + EXPORT INTRMC0_IRQHandler [WEAK] + EXPORT INTFLCRDY_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INT16_IRQHandler +INT17_18_IRQHandler +INT19_22_IRQHandler +INT23_26_IRQHandler +INT27_28_IRQHandler +INT29_IRQHandler +INT30_31_IRQHandler +INTEMG0_IRQHandler +INTOVV0_IRQHandler +INTPMD0_IRQHandler +INTENC00_IRQHandler +INTENC01_IRQHandler +INTADAPDA_IRQHandler +INTADAPDB_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTT0RX_IRQHandler +INTT0TX_IRQHandler +INTT0ERR_IRQHandler +INTT1RX_IRQHandler +INTT1TX_IRQHandler +INTT1ERR_IRQHandler +INTT2RX_IRQHandler +INTT2TX_IRQHandler +INTT2ERR_IRQHandler +INTT3RX_IRQHandler +INTT3TX_IRQHandler +INTT3ERR_IRQHandler +INTT4RX_IRQHandler +INTT4TX_IRQHandler +INTT4ERR_IRQHandler +INTI2CWUP_IRQHandler +INTI2C0_IRQHandler +INTI2C0AL_IRQHandler +INTI2C0BF_IRQHandler +INTI2C0NA_IRQHandler +INTI2C1_IRQHandler +INTI2C1AL_IRQHandler +INTI2C1BF_IRQHandler +INTI2C1NA_IRQHandler +INTI2C2_IRQHandler +INTI2C2AL_IRQHandler +INTI2C2BF_IRQHandler +INTI2C2NA_IRQHandler +INTI2C3_IRQHandler +INTI2C3AL_IRQHandler +INTI2C3BF_IRQHandler +INTI2C3NA_IRQHandler +INTUART0RX_IRQHandler +INTUART0TX_IRQHandler +INTUART0ERR_IRQHandler +INTUART1RX_IRQHandler +INTUART1TX_IRQHandler +INTUART1ERR_IRQHandler +INTUART2RX_IRQHandler +INTUART2TX_IRQHandler +INTUART2ERR_IRQHandler +INTUART3RX_IRQHandler +INTUART3TX_IRQHandler +INTUART3ERR_IRQHandler +INTUART4RX_IRQHandler +INTUART4TX_IRQHandler +INTUART4ERR_IRQHandler +INTUART5RX_IRQHandler +INTUART5TX_IRQHandler +INTUART5ERR_IRQHandler +INTT32A00A_IRQHandler +INTT32A00ACAP0_IRQHandler +INTT32A00ACAP1_IRQHandler +INTT32A00B_IRQHandler +INTT32A00BCAP0_IRQHandler +INTT32A00BCAP1_IRQHandler +INTT32A00C_IRQHandler +INTT32A00CCAP0_IRQHandler +INTT32A00CCAP1_IRQHandler +INTT32A01A_IRQHandler +INTT32A01ACAP0_IRQHandler +INTT32A01ACAP1_IRQHandler +INTT32A01B_IRQHandler +INTT32A01BCAP0_IRQHandler +INTT32A01BCAP1_IRQHandler +INTT32A01C_IRQHandler +INTT32A01CCAP0_IRQHandler +INTT32A01CCAP1_IRQHandler +INTT32A02A_IRQHandler +INTT32A02ACAP0_IRQHandler +INTT32A02ACAP1_IRQHandler +INTT32A02B_IRQHandler +INTT32A02BCAP0_IRQHandler +INTT32A02BCAP1_IRQHandler +INTT32A02C_IRQHandler +INTT32A02CCAP0_IRQHandler +INTT32A02CCAP1_IRQHandler +INTT32A03A_IRQHandler +INTT32A03ACAP0_IRQHandler +INTT32A03ACAP1_IRQHandler +INTT32A03B_IRQHandler +INTT32A03BCAP0_IRQHandler +INTT32A03BCAP1_IRQHandler +INTT32A03C_IRQHandler +INTT32A03CCAP0_IRQHandler +INTT32A03CCAP1_IRQHandler +INTT32A04A_IRQHandler +INTT32A04ACAP0_IRQHandler +INTT32A04ACAP1_IRQHandler +INTT32A04B_IRQHandler +INTT32A04BCAP0_IRQHandler +INTT32A04BCAP1_IRQHandler +INTT32A04C_IRQHandler +INTT32A04CCAP0_IRQHandler +INTT32A04CCAP1_IRQHandler +INTT32A05A_IRQHandler +INTT32A05ACAP0_IRQHandler +INTT32A05ACAP1_IRQHandler +INTT32A05B_IRQHandler +INTT32A05BCAP0_IRQHandler +INTT32A05BCAP1_IRQHandler +INTT32A05C_IRQHandler +INTT32A05CCAP0_IRQHandler +INTT32A05CCAP1_IRQHandler +INTT32A06A_IRQHandler +INTT32A06ACAP0_IRQHandler +INTT32A06ACAP1_IRQHandler +INTT32A06B_IRQHandler +INTT32A06BCAP0_IRQHandler +INTT32A06BCAP1_IRQHandler +INTT32A06C_IRQHandler +INTT32A06CCAP0_IRQHandler +INTT32A06CCAP1_IRQHandler +INTT32A07A_IRQHandler +INTT32A07ACAP0_IRQHandler +INTT32A07ACAP1_IRQHandler +INTT32A07B_IRQHandler +INTT32A07BCAP0_IRQHandler +INTT32A07BCAP1_IRQHandler +INTT32A07C_IRQHandler +INTT32A07CCAP0_IRQHandler +INTT32A07CCAP1_IRQHandler +INTPARI_IRQHandler +INTDMAATC_IRQHandler +INTDMAAERR_IRQHandler +INTDMABTC_IRQHandler +INTDMABERR_IRQHandler +INTRTC_IRQHandler +INTRMC0_IRQHandler +INTFLCRDY_IRQHandler +INTFLDRDY_IRQHandler + + B . + + ENDP + + ALIGN + END + diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct new file mode 100644 index 0000000000..007ecd61c1 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct @@ -0,0 +1,29 @@ +;; TMPM3HQFDFG scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) + +;; Compatible with ISSM model + +LR_IROM1 0x00000000 0x80000 +{ + ER_IROM1 0x00000000 0x80000 + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 0x200002D8 (0x10000 - 0x2D8) + { + .ANY (+RW, +ZI) + } +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S new file mode 100644 index 0000000000..113531b771 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S @@ -0,0 +1,582 @@ +/** + ******************************************************************************* + * @file startup_TMPM3HQ.s + * @brief CMSIS Cortex-M3 Core Device Startup File for the + * TOSHIBA 'TMPM3HQ' Device Series + * @version V5.00 + * @date 2016/03/02 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved + ******************************************************************************* + */ + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop // Top of Stack + .long Reset_Handler // Reset Handler + .long NMI_Handler // NMI Handler + .long HardFault_Handler // Hard Fault Handler + .long MemManage_Handler // MPU Fault Handler + .long BusFault_Handler // Bus Fault Handler + .long UsageFault_Handler // Usage Fault Handler + .long 0 // Reserved + .long 0 // Reserved + .long 0 // Reserved + .long 0 // Reserved + .long SVC_Handler // SVCall Handler + .long DebugMon_Handler // Debug Monitor Handler + .long 0 // Reserved + .long PendSV_Handler // PendSV Handler + .long SysTick_Handler // SysTick Handler + + // External interrupts + .long INT00_IRQHandler // 0: Interrupt Pin0 + .long INT01_IRQHandler // 1: Interrupt Pin1 + .long INT02_IRQHandler // 2: Interrupt Pin2 + .long INT03_IRQHandler // 3: Interrupt Pin3 + .long INT04_IRQHandler // 4: Interrupt Pin4 + .long INT05_IRQHandler // 5: Interrupt Pin5 + .long INT06_IRQHandler // 6: Interrupt Pin6 + .long INT07_IRQHandler // 7: Interrupt Pin7 + .long INT08_IRQHandler // 8: Interrupt Pin8 + .long INT09_IRQHandler // 9: Interrupt Pin9 + .long INT10_IRQHandler // 10: Interrupt Pin10 + .long INT11_IRQHandler // 11: Interrupt Pin11 + .long INT12_IRQHandler // 12: Interrupt Pin12 + .long INT13_IRQHandler // 13: Interrupt Pin13 + .long INT14_IRQHandler // 14: Interrupt Pin14 + .long INT15_IRQHandler // 15: Interrupt Pin15 + .long INT16_IRQHandler // 16: Interrupt Pin 16 + .long INT17_18_IRQHandler // 17: Interrupt Pin 17_18 + .long INT19_22_IRQHandler // 18: Interrupt Pin 19_22 + .long INT23_26_IRQHandler // 19: Interrupt Pin 23_26 + .long INT27_28_IRQHandler // 20: Interrupt Pin 27_28 + .long INT29_IRQHandler // 21: Interrupt Pin 29 + .long INT30_31_IRQHandler // 22: Interrupt Pin 30_31 + .long INTEMG0_IRQHandler // 23: PMD0 EMG interrupt + .long INTOVV0_IRQHandler // 24: PMD0 OVV interrupt + .long INTPMD0_IRQHandler // 25: PMD0 interrupt + .long INTENC00_IRQHandler // 26: Encoder 0 interrupt 0 + .long INTENC01_IRQHandler // 27: Encoder 0 interrupt 1 + .long INTADAPDA_IRQHandler // 28: ADC conversion triggered by PMD is finished A + .long INTADAPDB_IRQHandler // 29: ADC conversion triggered by PMD is finished B + .long INTADACP0_IRQHandler // 30: ADC conversion monitoring function interrupt 0 + .long INTADACP1_IRQHandler // 31: ADC conversion monitoring function interrupt 1 + .long INTADATRG_IRQHandler // 32: ADC conversion triggered by General purpose is finished + .long INTADASGL_IRQHandler // 33: ADC conversion triggered by Single program is finished + .long INTADACNT_IRQHandler // 34: ADC conversion triggered by Continuity program is finished + .long INTT0RX_IRQHandler // 35: TSPI/SIO reception (channel 0) + .long INTT0TX_IRQHandler // 36: TSPI/SIO transmit (channel 0) + .long INTT0ERR_IRQHandler // 37: TSPI/SIO error (channel 0) + .long INTT1RX_IRQHandler // 38: TSPI/SIO reception (channel 1) + .long INTT1TX_IRQHandler // 39: TSPI/SIO transmit (channel 1) + .long INTT1ERR_IRQHandler // 40: TSPI/SIO error (channel 1) + .long INTT2RX_IRQHandler // 41: TSPI/SIO reception (channel 2) + .long INTT2TX_IRQHandler // 42: TSPI/SIO transmit (channel 2) + .long INTT2ERR_IRQHandler // 43: TSPI/SIO error (channel 2) + .long INTT3RX_IRQHandler // 44: TSPI/SIO reception (channel 3) + .long INTT3TX_IRQHandler // 45: TSPI/SIO transmit (channel 3) + .long INTT3ERR_IRQHandler // 46: TSPI/SIO error (channel 3) + .long INTT4RX_IRQHandler // 47: TSPI/SIO reception (channel 4) + .long INTT4TX_IRQHandler // 48: TSPI/SIO transmit (channel 4) + .long INTT4ERR_IRQHandler // 49: TSPI/SIO error (channel 4) + .long INTI2CWUP_IRQHandler // 50: Serial bus interface (WakeUp) interrupt (channel 0) + .long INTI2C0_IRQHandler // 51: I2C0 transmission and reception interrupt + .long INTI2C0AL_IRQHandler // 52: I2C0 arbitration lost interrupt + .long INTI2C0BF_IRQHandler // 53: I2C0 bus free interrupt + .long INTI2C0NA_IRQHandler // 54: I2C0 no ack interrupt + .long INTI2C1_IRQHandler // 55: I2C1 transmission and reception interrupt + .long INTI2C1AL_IRQHandler // 56: I2C1 arbitration lost interrupt + .long INTI2C1BF_IRQHandler // 57: I2C1 bus free interrupt + .long INTI2C1NA_IRQHandler // 58: I2C1 no ack interrupt + .long INTI2C2_IRQHandler // 59: I2C2 transmission and reception interrupt + .long INTI2C2AL_IRQHandler // 60: I2C2 arbitration lost interrupt + .long INTI2C2BF_IRQHandler // 61: I2C2 bus free interrupt + .long INTI2C2NA_IRQHandler // 62: I2C2 no ack interrupt + .long INTI2C3_IRQHandler // 63: I2C3 transmission and reception interrupt + .long INTI2C3AL_IRQHandler // 64: I2C3 arbitration lost interrupt + .long INTI2C3BF_IRQHandler // 65: I2C3 bus free interrupt + .long INTI2C3NA_IRQHandler // 66: I2C3 no ack interrupt + .long INTUART0RX_IRQHandler // 67: UART reception (channel 0) + .long INTUART0TX_IRQHandler // 68: UART transmit (channel 0) + .long INTUART0ERR_IRQHandler // 69: UART error (channel 0) + .long INTUART1RX_IRQHandler // 70: UART reception (channel 1) + .long INTUART1TX_IRQHandler // 71: UART transmit (channel 1) + .long INTUART1ERR_IRQHandler // 72: UART error (channel 1) + .long INTUART2RX_IRQHandler // 73: UART reception (channel 2) + .long INTUART2TX_IRQHandler // 74: UART transmit (channel 2) + .long INTUART2ERR_IRQHandler // 75: UART error (channel 2) + .long INTUART3RX_IRQHandler // 76: UART reception (channel 3) + .long INTUART3TX_IRQHandler // 77: UART transmit (channel 3) + .long INTUART3ERR_IRQHandler // 78: UART error (channel 3) + .long INTUART4RX_IRQHandler // 79: UART reception (channel 4) + .long INTUART4TX_IRQHandler // 80: UART transmit (channel 4) + .long INTUART4ERR_IRQHandler // 81: UART error (channel 4) + .long INTUART5RX_IRQHandler // 82: UART reception (channel 5) + .long INTUART5TX_IRQHandler // 83: UART transmit (channel 5) + .long INTUART5ERR_IRQHandler // 84: UART error (channel 5) + .long INTT32A00A_IRQHandler // 85: 32bit T32A00A compare match detection 0 / Over flow / under flow + .long INTT32A00ACAP0_IRQHandler // 86: 32bit T32A00A input capture 0 + .long INTT32A00ACAP1_IRQHandler // 87: 32bit T32A00A input capture 1 + .long INTT32A00B_IRQHandler // 88: 32bit T32A00B compare match detection 0 / Over flow / under flow + .long INTT32A00BCAP0_IRQHandler // 89: 32bit T32A00B input capture 0 + .long INTT32A00BCAP1_IRQHandler // 90: 32bit T32A00B input capture 1 + .long INTT32A00C_IRQHandler // 91: 32bit T32A00C compare match detection 0 / Over flow / under flow + .long INTT32A00CCAP0_IRQHandler // 92: 32bit T32A00C input capture 0 + .long INTT32A00CCAP1_IRQHandler // 93: 32bit T32A00C input capture 1 + .long INTT32A01A_IRQHandler // 94: 32bit T32A01A compare match detection 0 / Over flow / under flow + .long INTT32A01ACAP0_IRQHandler // 95: 32bit T32A01A input capture 0 + .long INTT32A01ACAP1_IRQHandler // 96: 32bit T32A01A input capture 1 + .long INTT32A01B_IRQHandler // 97: 32bit T32A01B compare match detection 0 / Over flow / under flow + .long INTT32A01BCAP0_IRQHandler // 98: 32bit T32A01B input capture 0 + .long INTT32A01BCAP1_IRQHandler // 99: 32bit T32A01B input capture 1 + .long INTT32A01C_IRQHandler // 100: 32bit T32A01C compare match detection 0 / Over flow / under flow + .long INTT32A01CCAP0_IRQHandler // 101: 32bit T32A01C input capture 0 + .long INTT32A01CCAP1_IRQHandler // 102: 32bit T32A01C input capture 1 + .long INTT32A02A_IRQHandler // 103: 32bit T32A02A compare match detection 0 / Over flow / under flow + .long INTT32A02ACAP0_IRQHandler // 104: 32bit T32A02A input capture 0 + .long INTT32A02ACAP1_IRQHandler // 105: 32bit T32A02A input capture 1 + .long INTT32A02B_IRQHandler // 106: 32bit T32A02B compare match detection 0 / Over flow / under flow + .long INTT32A02BCAP0_IRQHandler // 107: 32bit T32A02B input capture 0 + .long INTT32A02BCAP1_IRQHandler // 108: 32bit T32A02B input capture 1 + .long INTT32A02C_IRQHandler // 109: 32bit T32A02C compare match detection 0 / Over flow / under flow + .long INTT32A02CCAP0_IRQHandler // 110: 32bit T32A02C input capture 0 + .long INTT32A02CCAP1_IRQHandler // 111: 32bit T32A02C input capture 1 + .long INTT32A03A_IRQHandler // 112: 32bit T32A03A compare match detection 0 / Over flow / under flow + .long INTT32A03ACAP0_IRQHandler // 113: 32bit T32A03A input capture 0 + .long INTT32A03ACAP1_IRQHandler // 114: 32bit T32A03A input capture 1 + .long INTT32A03B_IRQHandler // 115: 32bit T32A03B compare match detection 0 / Over flow / under flow + .long INTT32A03BCAP0_IRQHandler // 116: 32bit T32A03B input capture 0 + .long INTT32A03BCAP1_IRQHandler // 117: 32bit T32A03B input capture 1 + .long INTT32A03C_IRQHandler // 118: 32bit T32A03C compare match detection 0 / Over flow / under flow + .long INTT32A03CCAP0_IRQHandler // 119: 32bit T32A03C input capture 0 + .long INTT32A03CCAP1_IRQHandler // 120: 32bit T32A03C input capture 1 + .long INTT32A04A_IRQHandler // 121: 32bit T32A04A compare match detection 0 / Over flow / under flow + .long INTT32A04ACAP0_IRQHandler // 122: 32bit T32A04A input capture 0 + .long INTT32A04ACAP1_IRQHandler // 123: 32bit T32A04A input capture 1 + .long INTT32A04B_IRQHandler // 124: 32bit T32A04B compare match detection 0 / Over flow / under flow + .long INTT32A04BCAP0_IRQHandler // 125: 32bit T32A04B input capture 0 + .long INTT32A04BCAP1_IRQHandler // 126: 32bit T32A04B input capture 1 + .long INTT32A04C_IRQHandler // 127: 32bit T32A04C compare match detection 0 / Over flow / under flow + .long INTT32A04CCAP0_IRQHandler // 128: 32bit T32A04C input capture 0 + .long INTT32A04CCAP1_IRQHandler // 129: 32bit T32A04C input capture 1 + .long INTT32A05A_IRQHandler // 130: 32bit T32A05A compare match detection 0 / Over flow / under flow + .long INTT32A05ACAP0_IRQHandler // 131: 32bit T32A05A input capture 0 + .long INTT32A05ACAP1_IRQHandler // 132: 32bit T32A05A input capture 1 + .long INTT32A05B_IRQHandler // 133: 32bit T32A05B compare match detection 0 / Over flow / under flow + .long INTT32A05BCAP0_IRQHandler // 134: 32bit T32A05B input capture 0 + .long INTT32A05BCAP1_IRQHandler // 135: 32bit T32A05B input capture 1 + .long INTT32A05C_IRQHandler // 136: 32bit T32A05C compare match detection 0 / Over flow / under flow + .long INTT32A05CCAP0_IRQHandler // 137: 32bit T32A05C input capture 0 + .long INTT32A05CCAP1_IRQHandler // 138: 32bit T32A05C input capture 1 + .long INTT32A06A_IRQHandler // 139: 32bit T32A06A compare match detection 0 / Over flow / under flow + .long INTT32A06ACAP0_IRQHandler // 140: 32bit T32A06A input capture 0 + .long INTT32A06ACAP1_IRQHandler // 141: 32bit T32A06A input capture 1 + .long INTT32A06B_IRQHandler // 142: 32bit T32A06B compare match detection 0 / Over flow / under flow + .long INTT32A06BCAP0_IRQHandler // 143: 32bit T32A06B input capture 0 + .long INTT32A06BCAP1_IRQHandler // 144: 32bit T32A06B input capture 1 + .long INTT32A06C_IRQHandler // 145: 32bit T32A06C compare match detection 0 / Over flow / under flow + .long INTT32A06CCAP0_IRQHandler // 146: 32bit T32A06C input capture 0 + .long INTT32A06CCAP1_IRQHandler // 147: 32bit T32A06C input capture 1 + .long INTT32A07A_IRQHandler // 148: 32bit T32A07A compare match detection 0 / Over flow / under flow + .long INTT32A07ACAP0_IRQHandler // 149: 32bit T32A07A input capture 0 + .long INTT32A07ACAP1_IRQHandler // 150: 32bit T32A07A input capture 1 + .long INTT32A07B_IRQHandler // 151: 32bit T32A07B compare match detection 0 / Over flow / under flow + .long INTT32A07BCAP0_IRQHandler // 152: 32bit T32A07B input capture 0 + .long INTT32A07BCAP1_IRQHandler // 153: 32bit T32A07B input capture 1 + .long INTT32A07C_IRQHandler // 154: 32bit T32A07C compare match detection 0 / Over flow / under flow + .long INTT32A07CCAP0_IRQHandler // 155: 32bit T32A07C input capture 0 + .long INTT32A07CCAP1_IRQHandler // 156: 32bit T32A07C input capture 1 + .long INTPARI_IRQHandler // 157: RAM parity interrupt + .long INTDMAATC_IRQHandler // 158: DMAA end of transfer + .long INTDMAAERR_IRQHandler // 159: DMAA transfer error + .long INTDMABTC_IRQHandler // 160: DMAB end of transfer + .long INTDMABERR_IRQHandler // 161: DMAB transfer error + .long INTRTC_IRQHandler // 162: Real time clock interrupt + .long INTRMC0_IRQHandler // 163: Remote control reception interrupt + .long INTFLCRDY_IRQHandler // 164: Code FLASH Ready interrupt + .long INTFLDRDY_IRQHandler // 165: Data FLASH Ready interrupt + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INT16_IRQHandler + def_irq_handler INT17_18_IRQHandler + def_irq_handler INT19_22_IRQHandler + def_irq_handler INT23_26_IRQHandler + def_irq_handler INT27_28_IRQHandler + def_irq_handler INT29_IRQHandler + def_irq_handler INT30_31_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTPMD0_IRQHandler + def_irq_handler INTENC00_IRQHandler + def_irq_handler INTENC01_IRQHandler + def_irq_handler INTADAPDA_IRQHandler + def_irq_handler INTADAPDB_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTT0RX_IRQHandler + def_irq_handler INTT0TX_IRQHandler + def_irq_handler INTT0ERR_IRQHandler + def_irq_handler INTT1RX_IRQHandler + def_irq_handler INTT1TX_IRQHandler + def_irq_handler INTT1ERR_IRQHandler + def_irq_handler INTT2RX_IRQHandler + def_irq_handler INTT2TX_IRQHandler + def_irq_handler INTT2ERR_IRQHandler + def_irq_handler INTT3RX_IRQHandler + def_irq_handler INTT3TX_IRQHandler + def_irq_handler INTT3ERR_IRQHandler + def_irq_handler INTT4RX_IRQHandler + def_irq_handler INTT4TX_IRQHandler + def_irq_handler INTT4ERR_IRQHandler + def_irq_handler INTI2CWUP_IRQHandler + def_irq_handler INTI2C0_IRQHandler + def_irq_handler INTI2C0AL_IRQHandler + def_irq_handler INTI2C0BF_IRQHandler + def_irq_handler INTI2C0NA_IRQHandler + def_irq_handler INTI2C1_IRQHandler + def_irq_handler INTI2C1AL_IRQHandler + def_irq_handler INTI2C1BF_IRQHandler + def_irq_handler INTI2C1NA_IRQHandler + def_irq_handler INTI2C2_IRQHandler + def_irq_handler INTI2C2AL_IRQHandler + def_irq_handler INTI2C2BF_IRQHandler + def_irq_handler INTI2C2NA_IRQHandler + def_irq_handler INTI2C3_IRQHandler + def_irq_handler INTI2C3AL_IRQHandler + def_irq_handler INTI2C3BF_IRQHandler + def_irq_handler INTI2C3NA_IRQHandler + def_irq_handler INTUART0RX_IRQHandler + def_irq_handler INTUART0TX_IRQHandler + def_irq_handler INTUART0ERR_IRQHandler + def_irq_handler INTUART1RX_IRQHandler + def_irq_handler INTUART1TX_IRQHandler + def_irq_handler INTUART1ERR_IRQHandler + def_irq_handler INTUART2RX_IRQHandler + def_irq_handler INTUART2TX_IRQHandler + def_irq_handler INTUART2ERR_IRQHandler + def_irq_handler INTUART3RX_IRQHandler + def_irq_handler INTUART3TX_IRQHandler + def_irq_handler INTUART3ERR_IRQHandler + def_irq_handler INTUART4RX_IRQHandler + def_irq_handler INTUART4TX_IRQHandler + def_irq_handler INTUART4ERR_IRQHandler + def_irq_handler INTUART5RX_IRQHandler + def_irq_handler INTUART5TX_IRQHandler + def_irq_handler INTUART5ERR_IRQHandler + def_irq_handler INTT32A00A_IRQHandler + def_irq_handler INTT32A00ACAP0_IRQHandler + def_irq_handler INTT32A00ACAP1_IRQHandler + def_irq_handler INTT32A00B_IRQHandler + def_irq_handler INTT32A00BCAP0_IRQHandler + def_irq_handler INTT32A00BCAP1_IRQHandler + def_irq_handler INTT32A00C_IRQHandler + def_irq_handler INTT32A00CCAP0_IRQHandler + def_irq_handler INTT32A00CCAP1_IRQHandler + def_irq_handler INTT32A01A_IRQHandler + def_irq_handler INTT32A01ACAP0_IRQHandler + def_irq_handler INTT32A01ACAP1_IRQHandler + def_irq_handler INTT32A01B_IRQHandler + def_irq_handler INTT32A01BCAP0_IRQHandler + def_irq_handler INTT32A01BCAP1_IRQHandler + def_irq_handler INTT32A01C_IRQHandler + def_irq_handler INTT32A01CCAP0_IRQHandler + def_irq_handler INTT32A01CCAP1_IRQHandler + def_irq_handler INTT32A02A_IRQHandler + def_irq_handler INTT32A02ACAP0_IRQHandler + def_irq_handler INTT32A02ACAP1_IRQHandler + def_irq_handler INTT32A02B_IRQHandler + def_irq_handler INTT32A02BCAP0_IRQHandler + def_irq_handler INTT32A02BCAP1_IRQHandler + def_irq_handler INTT32A02C_IRQHandler + def_irq_handler INTT32A02CCAP0_IRQHandler + def_irq_handler INTT32A02CCAP1_IRQHandler + def_irq_handler INTT32A03A_IRQHandler + def_irq_handler INTT32A03ACAP0_IRQHandler + def_irq_handler INTT32A03ACAP1_IRQHandler + def_irq_handler INTT32A03B_IRQHandler + def_irq_handler INTT32A03BCAP0_IRQHandler + def_irq_handler INTT32A03BCAP1_IRQHandler + def_irq_handler INTT32A03C_IRQHandler + def_irq_handler INTT32A03CCAP0_IRQHandler + def_irq_handler INTT32A03CCAP1_IRQHandler + def_irq_handler INTT32A04A_IRQHandler + def_irq_handler INTT32A04ACAP0_IRQHandler + def_irq_handler INTT32A04ACAP1_IRQHandler + def_irq_handler INTT32A04B_IRQHandler + def_irq_handler INTT32A04BCAP0_IRQHandler + def_irq_handler INTT32A04BCAP1_IRQHandler + def_irq_handler INTT32A04C_IRQHandler + def_irq_handler INTT32A04CCAP0_IRQHandler + def_irq_handler INTT32A04CCAP1_IRQHandler + def_irq_handler INTT32A05A_IRQHandler + def_irq_handler INTT32A05ACAP0_IRQHandler + def_irq_handler INTT32A05ACAP1_IRQHandler + def_irq_handler INTT32A05B_IRQHandler + def_irq_handler INTT32A05BCAP0_IRQHandler + def_irq_handler INTT32A05BCAP1_IRQHandler + def_irq_handler INTT32A05C_IRQHandler + def_irq_handler INTT32A05CCAP0_IRQHandler + def_irq_handler INTT32A05CCAP1_IRQHandler + def_irq_handler INTT32A06A_IRQHandler + def_irq_handler INTT32A06ACAP0_IRQHandler + def_irq_handler INTT32A06ACAP1_IRQHandler + def_irq_handler INTT32A06B_IRQHandler + def_irq_handler INTT32A06BCAP0_IRQHandler + def_irq_handler INTT32A06BCAP1_IRQHandler + def_irq_handler INTT32A06C_IRQHandler + def_irq_handler INTT32A06CCAP0_IRQHandler + def_irq_handler INTT32A06CCAP1_IRQHandler + def_irq_handler INTT32A07A_IRQHandler + def_irq_handler INTT32A07ACAP0_IRQHandler + def_irq_handler INTT32A07ACAP1_IRQHandler + def_irq_handler INTT32A07B_IRQHandler + def_irq_handler INTT32A07BCAP0_IRQHandler + def_irq_handler INTT32A07BCAP1_IRQHandler + def_irq_handler INTT32A07C_IRQHandler + def_irq_handler INTT32A07CCAP0_IRQHandler + def_irq_handler INTT32A07CCAP1_IRQHandler + def_irq_handler INTPARI_IRQHandler + def_irq_handler INTDMAATC_IRQHandler + def_irq_handler INTDMAAERR_IRQHandler + def_irq_handler INTDMABTC_IRQHandler + def_irq_handler INTDMABERR_IRQHandler + def_irq_handler INTRTC_IRQHandler + def_irq_handler INTRMC0_IRQHandler + def_irq_handler INTFLCRDY_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + + .end diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld new file mode 100644 index 0000000000..4ae0b047e0 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld @@ -0,0 +1,161 @@ +/* Linker script for Toshiba TMPM3HQ */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K + RAM (rwx) : ORIGIN = (0x20000000 + 0x2D8), LENGTH = (64K - 0x2D8) +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S new file mode 100644 index 0000000000..cbed3bdbe3 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S @@ -0,0 +1,1107 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM3HQ.s +; * @brief CMSIS Cortex-M3 Core Device Startup File for the +; * TOSHIBA 'TMPM3HQ' Device Series +; * @version V1.0.0.0 +; * $Date:: 2017-12-08 #$ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt Pin 00 + DCD INT01_IRQHandler ; 1: Interrupt Pin 01 + DCD INT02_IRQHandler ; 2: Interrupt Pin 02 + DCD INT03_IRQHandler ; 3: Interrupt Pin 03 + DCD INT04_IRQHandler ; 4: Interrupt Pin 04 + DCD INT05_IRQHandler ; 5: Interrupt Pin 05 + DCD INT06_IRQHandler ; 6: Interrupt Pin 06 + DCD INT07_IRQHandler ; 7: Interrupt Pin 07 + DCD INT08_IRQHandler ; 8: Interrupt Pin 08 + DCD INT09_IRQHandler ; 9: Interrupt Pin 09 + DCD INT10_IRQHandler ; 10: Interrupt Pin 10 + DCD INT11_IRQHandler ; 11: Interrupt Pin 11 + DCD INT12_IRQHandler ; 12: Interrupt Pin 12 + DCD INT13_IRQHandler ; 13: Interrupt Pin 13 + DCD INT14_IRQHandler ; 14: Interrupt Pin 14 + DCD INT15_IRQHandler ; 15: Interrupt Pin 15 + DCD INT16_IRQHandler ; 16: Interrupt Pin 16 + DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18 + DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22 + DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26 + DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28 + DCD INT29_IRQHandler ; 21: Interrupt Pin 29 + DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31 + DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt + DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt + DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0 + DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1 + DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A + DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B + DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished + DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0) + DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0) + DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0) + DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1) + DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1) + DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1) + DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2) + DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2) + DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2) + DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3) + DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3) + DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3) + DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4) + DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4) + DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4) + DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0) + DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt + DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt + DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt + DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt + DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt + DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt + DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt + DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt + DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt + DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt + DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt + DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt + DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt + DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt + DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt + DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt + DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0) + DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0) + DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0) + DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1) + DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1) + DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1) + DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2) + DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2) + DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2) + DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3) + DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3) + DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3) + DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4) + DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4) + DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4) + DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5) + DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5) + DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5) + DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow + DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0 + DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1 + DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow + DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0 + DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1 + DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow + DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0 + DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1 + DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow + DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0 + DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1 + DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow + DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0 + DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1 + DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow + DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0 + DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1 + DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow + DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0 + DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1 + DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow + DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0 + DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1 + DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow + DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0 + DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1 + DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow + DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0 + DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1 + DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow + DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0 + DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1 + DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow + DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0 + DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1 + DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow + DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0 + DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1 + DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow + DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0 + DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1 + DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow + DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0 + DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1 + DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow + DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0 + DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1 + DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow + DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0 + DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1 + DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow + DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0 + DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1 + DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow + DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0 + DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1 + DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow + DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0 + DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1 + DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow + DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0 + DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1 + DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow + DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0 + DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1 + DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow + DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0 + DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1 + DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow + DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0 + DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1 + DCD INTPARI_IRQHandler ; 157: RAM parity interrupt + DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer + DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error + DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer + DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error + DCD INTRTC_IRQHandler ; 162: Real time clock interrupt + DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt + DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt + DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK INT00_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT00_IRQHandler + B INT00_IRQHandler + + PUBWEAK INT01_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT01_IRQHandler + B INT01_IRQHandler + + PUBWEAK INT02_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT02_IRQHandler + B INT02_IRQHandler + + PUBWEAK INT03_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT03_IRQHandler + B INT03_IRQHandler + + PUBWEAK INT04_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT04_IRQHandler + B INT04_IRQHandler + + PUBWEAK INT05_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT05_IRQHandler + B INT05_IRQHandler + + PUBWEAK INT06_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT06_IRQHandler + B INT06_IRQHandler + + PUBWEAK INT07_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT07_IRQHandler + B INT07_IRQHandler + + PUBWEAK INT08_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT08_IRQHandler + B INT08_IRQHandler + + PUBWEAK INT09_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT09_IRQHandler + B INT09_IRQHandler + + PUBWEAK INT10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT10_IRQHandler + B INT10_IRQHandler + + PUBWEAK INT11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT11_IRQHandler + B INT11_IRQHandler + + PUBWEAK INT12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT12_IRQHandler + B INT12_IRQHandler + + PUBWEAK INT13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT13_IRQHandler + B INT13_IRQHandler + + PUBWEAK INT14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT14_IRQHandler + B INT14_IRQHandler + + PUBWEAK INT15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT15_IRQHandler + B INT15_IRQHandler + + PUBWEAK INT16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT16_IRQHandler + B INT16_IRQHandler + + PUBWEAK INT17_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT17_18_IRQHandler + B INT17_18_IRQHandler + + PUBWEAK INT19_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT19_22_IRQHandler + B INT19_22_IRQHandler + + PUBWEAK INT23_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT23_26_IRQHandler + B INT23_26_IRQHandler + + PUBWEAK INT27_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT27_28_IRQHandler + B INT27_28_IRQHandler + + PUBWEAK INT29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT29_IRQHandler + B INT29_IRQHandler + + PUBWEAK INT30_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT30_31_IRQHandler + B INT30_31_IRQHandler + + PUBWEAK INTEMG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTEMG0_IRQHandler + B INTEMG0_IRQHandler + + PUBWEAK INTOVV0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTOVV0_IRQHandler + B INTOVV0_IRQHandler + + PUBWEAK INTPMD0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTPMD0_IRQHandler + B INTPMD0_IRQHandler + + PUBWEAK INTENC00_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTENC00_IRQHandler + B INTENC00_IRQHandler + + PUBWEAK INTENC01_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTENC01_IRQHandler + B INTENC01_IRQHandler + + PUBWEAK INTADAPDA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADAPDA_IRQHandler + B INTADAPDA_IRQHandler + + PUBWEAK INTADAPDB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADAPDB_IRQHandler + B INTADAPDB_IRQHandler + + PUBWEAK INTADACP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACP0_IRQHandler + B INTADACP0_IRQHandler + + PUBWEAK INTADACP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACP1_IRQHandler + B INTADACP1_IRQHandler + + PUBWEAK INTADATRG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADATRG_IRQHandler + B INTADATRG_IRQHandler + + PUBWEAK INTADASGL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADASGL_IRQHandler + B INTADASGL_IRQHandler + + PUBWEAK INTADACNT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADACNT_IRQHandler + B INTADACNT_IRQHandler + + PUBWEAK INTT0RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0RX_IRQHandler + B INTT0RX_IRQHandler + + PUBWEAK INTT0TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0TX_IRQHandler + B INTT0TX_IRQHandler + + PUBWEAK INTT0ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT0ERR_IRQHandler + B INTT0ERR_IRQHandler + + PUBWEAK INTT1RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1RX_IRQHandler + B INTT1RX_IRQHandler + + PUBWEAK INTT1TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1TX_IRQHandler + B INTT1TX_IRQHandler + + PUBWEAK INTT1ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT1ERR_IRQHandler + B INTT1ERR_IRQHandler + + PUBWEAK INTT2RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT2RX_IRQHandler + B INTT2RX_IRQHandler + + PUBWEAK INTT2TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT2TX_IRQHandler + B INTT2TX_IRQHandler + + PUBWEAK INTT2ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT2ERR_IRQHandler + B INTT2ERR_IRQHandler + + PUBWEAK INTT3RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT3RX_IRQHandler + B INTT3RX_IRQHandler + + PUBWEAK INTT3TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT3TX_IRQHandler + B INTT3TX_IRQHandler + + PUBWEAK INTT3ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT3ERR_IRQHandler + B INTT3ERR_IRQHandler + + PUBWEAK INTT4RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT4RX_IRQHandler + B INTT4RX_IRQHandler + + PUBWEAK INTT4TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT4TX_IRQHandler + B INTT4TX_IRQHandler + + PUBWEAK INTT4ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT4ERR_IRQHandler + B INTT4ERR_IRQHandler + + PUBWEAK INTI2CWUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2CWUP_IRQHandler + B INTI2CWUP_IRQHandler + + PUBWEAK INTI2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0_IRQHandler + B INTI2C0_IRQHandler + + PUBWEAK INTI2C0AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0AL_IRQHandler + B INTI2C0AL_IRQHandler + + PUBWEAK INTI2C0BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0BF_IRQHandler + B INTI2C0BF_IRQHandler + + PUBWEAK INTI2C0NA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0NA_IRQHandler + B INTI2C0NA_IRQHandler + + PUBWEAK INTI2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1_IRQHandler + B INTI2C1_IRQHandler + + PUBWEAK INTI2C1AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1AL_IRQHandler + B INTI2C1AL_IRQHandler + + PUBWEAK INTI2C1BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1BF_IRQHandler + B INTI2C1BF_IRQHandler + + PUBWEAK INTI2C1NA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1NA_IRQHandler + B INTI2C1NA_IRQHandler + + PUBWEAK INTI2C2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2_IRQHandler + B INTI2C2_IRQHandler + + PUBWEAK INTI2C2AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2AL_IRQHandler + B INTI2C2AL_IRQHandler + + PUBWEAK INTI2C2BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2BF_IRQHandler + B INTI2C2BF_IRQHandler + + PUBWEAK INTI2C2NA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C2NA_IRQHandler + B INTI2C2NA_IRQHandler + + PUBWEAK INTI2C3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3_IRQHandler + B INTI2C3_IRQHandler + + PUBWEAK INTI2C3AL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3AL_IRQHandler + B INTI2C3AL_IRQHandler + + PUBWEAK INTI2C3BF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3BF_IRQHandler + B INTI2C3BF_IRQHandler + + PUBWEAK INTI2C3NA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C3NA_IRQHandler + B INTI2C3NA_IRQHandler + + PUBWEAK INTUART0RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0RX_IRQHandler + B INTUART0RX_IRQHandler + + PUBWEAK INTUART0TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0TX_IRQHandler + B INTUART0TX_IRQHandler + + PUBWEAK INTUART0ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART0ERR_IRQHandler + B INTUART0ERR_IRQHandler + + PUBWEAK INTUART1RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1RX_IRQHandler + B INTUART1RX_IRQHandler + + PUBWEAK INTUART1TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1TX_IRQHandler + B INTUART1TX_IRQHandler + + PUBWEAK INTUART1ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART1ERR_IRQHandler + B INTUART1ERR_IRQHandler + + PUBWEAK INTUART2RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2RX_IRQHandler + B INTUART2RX_IRQHandler + + PUBWEAK INTUART2TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2TX_IRQHandler + B INTUART2TX_IRQHandler + + PUBWEAK INTUART2ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART2ERR_IRQHandler + B INTUART2ERR_IRQHandler + + PUBWEAK INTUART3RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART3RX_IRQHandler + B INTUART3RX_IRQHandler + + PUBWEAK INTUART3TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART3TX_IRQHandler + B INTUART3TX_IRQHandler + + PUBWEAK INTUART3ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART3ERR_IRQHandler + B INTUART3ERR_IRQHandler + + PUBWEAK INTUART4RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART4RX_IRQHandler + B INTUART4RX_IRQHandler + + PUBWEAK INTUART4TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART4TX_IRQHandler + B INTUART4TX_IRQHandler + + PUBWEAK INTUART4ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART4ERR_IRQHandler + B INTUART4ERR_IRQHandler + + PUBWEAK INTUART5RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART5RX_IRQHandler + B INTUART5RX_IRQHandler + + PUBWEAK INTUART5TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART5TX_IRQHandler + B INTUART5TX_IRQHandler + + PUBWEAK INTUART5ERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUART5ERR_IRQHandler + B INTUART5ERR_IRQHandler + + PUBWEAK INTT32A00A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00A_IRQHandler + B INTT32A00A_IRQHandler + + PUBWEAK INTT32A00ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00ACAP0_IRQHandler + B INTT32A00ACAP0_IRQHandler + + PUBWEAK INTT32A00ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00ACAP1_IRQHandler + B INTT32A00ACAP1_IRQHandler + + PUBWEAK INTT32A00B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00B_IRQHandler + B INTT32A00B_IRQHandler + + PUBWEAK INTT32A00BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00BCAP0_IRQHandler + B INTT32A00BCAP0_IRQHandler + + PUBWEAK INTT32A00BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00BCAP1_IRQHandler + B INTT32A00BCAP1_IRQHandler + + PUBWEAK INTT32A00C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00C_IRQHandler + B INTT32A00C_IRQHandler + + PUBWEAK INTT32A00CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00CCAP0_IRQHandler + B INTT32A00CCAP0_IRQHandler + + PUBWEAK INTT32A00CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A00CCAP1_IRQHandler + B INTT32A00CCAP1_IRQHandler + + PUBWEAK INTT32A01A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01A_IRQHandler + B INTT32A01A_IRQHandler + + PUBWEAK INTT32A01ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01ACAP0_IRQHandler + B INTT32A01ACAP0_IRQHandler + + PUBWEAK INTT32A01ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01ACAP1_IRQHandler + B INTT32A01ACAP1_IRQHandler + + PUBWEAK INTT32A01B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01B_IRQHandler + B INTT32A01B_IRQHandler + + PUBWEAK INTT32A01BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01BCAP0_IRQHandler + B INTT32A01BCAP0_IRQHandler + + PUBWEAK INTT32A01BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01BCAP1_IRQHandler + B INTT32A01BCAP1_IRQHandler + + PUBWEAK INTT32A01C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01C_IRQHandler + B INTT32A01C_IRQHandler + + PUBWEAK INTT32A01CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01CCAP0_IRQHandler + B INTT32A01CCAP0_IRQHandler + + PUBWEAK INTT32A01CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A01CCAP1_IRQHandler + B INTT32A01CCAP1_IRQHandler + + PUBWEAK INTT32A02A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02A_IRQHandler + B INTT32A02A_IRQHandler + + PUBWEAK INTT32A02ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02ACAP0_IRQHandler + B INTT32A02ACAP0_IRQHandler + + PUBWEAK INTT32A02ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02ACAP1_IRQHandler + B INTT32A02ACAP1_IRQHandler + + PUBWEAK INTT32A02B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02B_IRQHandler + B INTT32A02B_IRQHandler + + PUBWEAK INTT32A02BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02BCAP0_IRQHandler + B INTT32A02BCAP0_IRQHandler + + PUBWEAK INTT32A02BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02BCAP1_IRQHandler + B INTT32A02BCAP1_IRQHandler + + PUBWEAK INTT32A02C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02C_IRQHandler + B INTT32A02C_IRQHandler + + PUBWEAK INTT32A02CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02CCAP0_IRQHandler + B INTT32A02CCAP0_IRQHandler + + PUBWEAK INTT32A02CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A02CCAP1_IRQHandler + B INTT32A02CCAP1_IRQHandler + + PUBWEAK INTT32A03A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03A_IRQHandler + B INTT32A03A_IRQHandler + + PUBWEAK INTT32A03ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03ACAP0_IRQHandler + B INTT32A03ACAP0_IRQHandler + + PUBWEAK INTT32A03ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03ACAP1_IRQHandler + B INTT32A03ACAP1_IRQHandler + + PUBWEAK INTT32A03B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03B_IRQHandler + B INTT32A03B_IRQHandler + + PUBWEAK INTT32A03BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03BCAP0_IRQHandler + B INTT32A03BCAP0_IRQHandler + + PUBWEAK INTT32A03BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03BCAP1_IRQHandler + B INTT32A03BCAP1_IRQHandler + + PUBWEAK INTT32A03C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03C_IRQHandler + B INTT32A03C_IRQHandler + + PUBWEAK INTT32A03CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03CCAP0_IRQHandler + B INTT32A03CCAP0_IRQHandler + + PUBWEAK INTT32A03CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A03CCAP1_IRQHandler + B INTT32A03CCAP1_IRQHandler + + PUBWEAK INTT32A04A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04A_IRQHandler + B INTT32A04A_IRQHandler + + PUBWEAK INTT32A04ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04ACAP0_IRQHandler + B INTT32A04ACAP0_IRQHandler + + PUBWEAK INTT32A04ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04ACAP1_IRQHandler + B INTT32A04ACAP1_IRQHandler + + PUBWEAK INTT32A04B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04B_IRQHandler + B INTT32A04B_IRQHandler + + PUBWEAK INTT32A04BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04BCAP0_IRQHandler + B INTT32A04BCAP0_IRQHandler + + PUBWEAK INTT32A04BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04BCAP1_IRQHandler + B INTT32A04BCAP1_IRQHandler + + PUBWEAK INTT32A04C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04C_IRQHandler + B INTT32A04C_IRQHandler + + PUBWEAK INTT32A04CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04CCAP0_IRQHandler + B INTT32A04CCAP0_IRQHandler + + PUBWEAK INTT32A04CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A04CCAP1_IRQHandler + B INTT32A04CCAP1_IRQHandler + + PUBWEAK INTT32A05A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05A_IRQHandler + B INTT32A05A_IRQHandler + + PUBWEAK INTT32A05ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05ACAP0_IRQHandler + B INTT32A05ACAP0_IRQHandler + + PUBWEAK INTT32A05ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05ACAP1_IRQHandler + B INTT32A05ACAP1_IRQHandler + + PUBWEAK INTT32A05B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05B_IRQHandler + B INTT32A05B_IRQHandler + + PUBWEAK INTT32A05BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05BCAP0_IRQHandler + B INTT32A05BCAP0_IRQHandler + + PUBWEAK INTT32A05BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05BCAP1_IRQHandler + B INTT32A05BCAP1_IRQHandler + + PUBWEAK INTT32A05C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05C_IRQHandler + B INTT32A05C_IRQHandler + + PUBWEAK INTT32A05CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05CCAP0_IRQHandler + B INTT32A05CCAP0_IRQHandler + + PUBWEAK INTT32A05CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A05CCAP1_IRQHandler + B INTT32A05CCAP1_IRQHandler + + PUBWEAK INTT32A06A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06A_IRQHandler + B INTT32A06A_IRQHandler + + PUBWEAK INTT32A06ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06ACAP0_IRQHandler + B INTT32A06ACAP0_IRQHandler + + PUBWEAK INTT32A06ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06ACAP1_IRQHandler + B INTT32A06ACAP1_IRQHandler + + PUBWEAK INTT32A06B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06B_IRQHandler + B INTT32A06B_IRQHandler + + PUBWEAK INTT32A06BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06BCAP0_IRQHandler + B INTT32A06BCAP0_IRQHandler + + PUBWEAK INTT32A06BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06BCAP1_IRQHandler + B INTT32A06BCAP1_IRQHandler + + PUBWEAK INTT32A06C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06C_IRQHandler + B INTT32A06C_IRQHandler + + PUBWEAK INTT32A06CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06CCAP0_IRQHandler + B INTT32A06CCAP0_IRQHandler + + PUBWEAK INTT32A06CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A06CCAP1_IRQHandler + B INTT32A06CCAP1_IRQHandler + + PUBWEAK INTT32A07A_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07A_IRQHandler + B INTT32A07A_IRQHandler + + PUBWEAK INTT32A07ACAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07ACAP0_IRQHandler + B INTT32A07ACAP0_IRQHandler + + PUBWEAK INTT32A07ACAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07ACAP1_IRQHandler + B INTT32A07ACAP1_IRQHandler + + PUBWEAK INTT32A07B_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07B_IRQHandler + B INTT32A07B_IRQHandler + + PUBWEAK INTT32A07BCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07BCAP0_IRQHandler + B INTT32A07BCAP0_IRQHandler + + PUBWEAK INTT32A07BCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07BCAP1_IRQHandler + B INTT32A07BCAP1_IRQHandler + + PUBWEAK INTT32A07C_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07C_IRQHandler + B INTT32A07C_IRQHandler + + PUBWEAK INTT32A07CCAP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07CCAP0_IRQHandler + B INTT32A07CCAP0_IRQHandler + + PUBWEAK INTT32A07CCAP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTT32A07CCAP1_IRQHandler + B INTT32A07CCAP1_IRQHandler + + PUBWEAK INTPARI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTPARI_IRQHandler + B INTPARI_IRQHandler + + PUBWEAK INTDMAATC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTDMAATC_IRQHandler + B INTDMAATC_IRQHandler + + PUBWEAK INTDMAAERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTDMAAERR_IRQHandler + B INTDMAAERR_IRQHandler + + PUBWEAK INTDMABTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTDMABTC_IRQHandler + B INTDMABTC_IRQHandler + + PUBWEAK INTDMABERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTDMABERR_IRQHandler + B INTDMABERR_IRQHandler + + PUBWEAK INTRTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRTC_IRQHandler + B INTRTC_IRQHandler + + PUBWEAK INTRMC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRMC0_IRQHandler + B INTRMC0_IRQHandler + + PUBWEAK INTFLCRDY_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFLCRDY_IRQHandler + B INTFLCRDY_IRQHandler + + PUBWEAK INTFLDRDY_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTFLDRDY_IRQHandler + B INTFLDRDY_IRQHandler + + END diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf new file mode 100644 index 0000000000..6a61b3705a --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf @@ -0,0 +1,41 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200002D8; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __BRAM_start__ = 0x20010000; +define symbol __BRAM_end__ = 0x200107FF; +define symbol __DFLASH_start__ = 0x30000000; +define symbol __DFLASH_end__ = 0x30007FFF; +define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ]; +define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in BRAM_region { section .backup_ram }; +place in DFLASH_region { section .data_flash }; diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h new file mode 100644 index 0000000000..441eb0d0ef --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis.h @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library - CMSIS for TMPM3HQ + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in TMPM3HQ specifics + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM3HQ.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h new file mode 100644 index 0000000000..bb3ccde7a0 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/cmsis_nvic.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - cmsis_nvic for TMPM3HQ + * Copyright (c) 2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (182) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c new file mode 100644 index 0000000000..92a628a856 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.c @@ -0,0 +1,342 @@ +/** + ******************************************************************************* + * @file system_TMPM3Hy.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM3Hy' Device Series + * @version 0.0.5.0 + * $Date:: 2017-07-01 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +#include "TMPM3HQ.h" + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ +#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ +#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ +#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ +#define SYSCR_Val (0x00000000UL) + +#define STBYCR_Val (0x00000000UL) + +#define CG_6M_MUL_13_328_FPLL (0x001C6535UL<<8U) /* fPLL = 6MHz * 13.328 */ +#define CG_8M_MUL_10_FPLL (0x00246028UL<<8U) /* fPLL = 8MHz * 10 */ +#define CG_10M_MUL_8_FPLL (0x002E6020UL<<8U) /* fPLL = 10MHz * 8 */ +#define CG_12M_MUL_6_656_FPLL (0x0036EA1AUL<<8U) /* fPLL = 12MHz * 6.656 */ +#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */ +#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */ +#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */ +#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */ + +#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) +#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) +#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) + +#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) +#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) + +#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001) + +#if (CLOCK_SETUP) + #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) + #define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL +#else + #define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000) + #define PLL0SEL_Ready CG_10M_MUL_8_FPLL +#endif +#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) +#define PLL0SEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define EOSC_6M (6000000UL) +#define EOSC_8M (8000000UL) +#define EOSC_10M (10000000UL) +#define EOSC_12M (12000000UL) +#define IOSC_10M (10000000UL) +#define EXTALH EOSC_12M /* External high-speed oscillator freq */ +#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ +#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */ +#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */ +#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ +#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */ +#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ +#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ +#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ +#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ +#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ +#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ +#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ +#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = warm-up time(us) * EXTALH / 16 */ +#if (CLOCK_SETUP) + #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) + #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#else + #define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) + #define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#endif +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (CLOCK_SETUP) + #define CORE_TALH (EXTALH) +#else + #define CORE_TALH (IXTALH) +#endif + +#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ + #if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_13_328_FPLL)) + #define __CORE_CLK EOSC_6M_DIV4_PLLON /* output clock is 79.97MHz */ + #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL)) + #define __CORE_CLK EOSC_6M_DIV8_PLLON /* output clock is 39.98MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 6MHz */ + #elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_10_FPLL)) + #define __CORE_CLK EOSC_8M_DIV4_PLLON /* output clock is 80MHz */ + #elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL)) + #define __CORE_CLK EOSC_8M_DIV8_PLLON /* output clock is 40MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 8MHz */ + #elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) + #define __CORE_CLK EOSC_10M_DIV4_PLLON /* output clock is 80MHz */ + #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) + #define __CORE_CLK EOSC_10M_DIV8_PLLON /* output clock is 40MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 10MHz */ + #elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) + #define __CORE_CLK EOSC_12M_DIV4_PLLON /* output clock is 79.88MHz */ + #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) + #define __CORE_CLK EOSC_12M_DIV8_PLLON /* output clock is 39.94MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 12MHz */ + #elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ + #if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) + #define __CORE_CLK IOSC_10M_DIV4_PLLON /* output clock is 80MHz */ + #elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) + #define __CORE_CLK IOSC_10M_DIV8_PLLON /* output clock is 40MHz */ + #else /* fc -> reserved */ + #define __CORE_CLK (0U) + #endif /* End input is 10MHz */ + #else /* input clock not known */ + #define __CORE_CLK (0U) + #error "Core Oscillator Frequency invalid!" + #endif /* End switch input clock */ +#else + #define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ + #define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ + #define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ + #define __CORE_SYS (__CORE_CLK / 4U ) +#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ + #define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ + #define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ + #define __CORE_SYS (0U) +#endif + + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ /* Get Core Clock Frequency */ + uint32_t CoreClock = 0U; + uint32_t CoreClockInput = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pll0sel = 0U; + uint32_t pll0on = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = IXTALH; + } + regval = TSB_CG->PLL0SEL; + pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; + pll0on = regval & CG_PLL0SEL_PLL0ON_SET; + if (pll0sel && pll0on) { /* If PLL enabled */ + if (CoreClock == EOSC_6M) { /* If input is 6MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_13_328_FPLL) { + CoreClockInput = EOSC_6M_DIV4_PLLON; /* output clock is 79.97MHz */ + } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) { + CoreClockInput = EOSC_6M_DIV8_PLLON; /* output clock is 39.98MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_10_FPLL) { + CoreClockInput = EOSC_8M_DIV4_PLLON; /* output clock is 80MHz */ + } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) { + CoreClockInput = EOSC_8M_DIV8_PLLON; /* output clock is 40MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { + CoreClockInput = EOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ + } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { + CoreClockInput = EOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) { + CoreClockInput = EOSC_12M_DIV4_PLLON; /* output clock is 79.88MHz */ + } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) { + CoreClockInput = EOSC_12M_DIV8_PLLON; /* output clock is 39.94MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) { + CoreClockInput = IOSC_10M_DIV4_PLLON; /* output clock is 80MHz */ + } else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) { + CoreClockInput = IOSC_10M_DIV8_PLLON; /* output clock is 40MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { /* If PLL not used */ + CoreClockInput = CoreClock; + } + + switch (TSB_CG->SYSCR & 7U) { + case 0U: /* Gear -> fc */ + SystemCoreClock = CoreClockInput; + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + if (CoreClockInput >= EOSC_8M) { + SystemCoreClock = CoreClockInput / 8U; + } else { + SystemCoreClock = 0U; + } + break; + case 4U: /* Gear -> fc/16 */ + if (CoreClockInput > EOSC_12M) { + SystemCoreClock = CoreClockInput / 16U; + } else { + SystemCoreClock = 0U; + } + break; + case 5U: + case 6U: + case 7U: + SystemCoreClock = 0U; + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ +#if (SIWD_SETUP) /* Watchdog Setup */ + /* SIWD Disable */ + TSB_SIWD0->EN = SIWDEN_Val; + TSB_SIWD0->CR = SIWDCR_Val; +#else + /* SIWD Enable (Setting after a Reset) */ +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = SYSCR_Val; + + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + while (!TSB_CG_OSCCR_OSCF) { + ; + } /* Confirm CGOSCCR="1" */ + TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; +#else + /* Internal HOSC Enable (Setting after a Reset) */ +#endif + + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLL0SEL_Ready; + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + //Enable 32.768khz. + //TSB_RLM->LOSCCR = 0x01; + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Lockup */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + while (!TSB_CG_PLL0SEL_PLL0ST) { + ; + } /*Confirm CGPLL0SEL = "1" */ +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h new file mode 100644 index 0000000000..0dd2ddcdb5 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/device/system_TMPM3HQ.h @@ -0,0 +1,52 @@ +/** + ***************************************************************************** + * @file system_TMPM3Hy.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM3Hy' Device Series + * @version V1.0.1.0 + * $Date:: 2017-07-01 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. + * + * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM3HQ_H +#define __SYSTEM_TMPM3HQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c new file mode 100644 index 0000000000..ae96d4ae60 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_api.c @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_include.h" + +extern const PinMap PinMap_GPIO_IRQ[]; +#define GPIO_DATA PIN_DATA(0, 2) + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + // Checking pin name is not interrupt pins + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + // Return pin mask + return (1 << (pin & 0x07)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + obj->mask = gpio_set(pin); + obj->port = (PortName) (pin >> 3); + TSB_CG->FSYSENA |= (1<<(obj->port)); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->pin, mode); +} + +// Set gpio object pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + pin_function(obj->pin, PIN_INPUT); + break; + + case PIN_OUTPUT: + pin_function(obj->pin, PIN_OUTPUT); + break; + + case PIN_INOUT: + pin_function(obj->pin, PIN_INOUT); + break; + + default: + error("Invalid direction\n"); + break; + } +} + +// Write gpio object pin data +void gpio_write(gpio_t *obj, int value) +{ + int port = 0; + uint8_t bit = 0; + uint32_t base; + + // Calculate port and pin position + port = PIN_PORT(obj->pin); + bit = PIN_POS(obj->pin); + + base = BITBAND_PORT_BASE(port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + if(value == GPIO_PIN_SET) + BITBAND_PORT_SET(base, bit); + else if(value == GPIO_PIN_RESET) + BITBAND_PORT_CLR(base, bit); + else + error("Invalid value\n"); +} + +// Read gpio object pin data +int gpio_read (gpio_t *obj) +{ + int port = 0; + uint8_t bit = 0; + uint32_t base; + uint32_t val; + int BitValue; + + // Calculate port and pin position + port = PIN_PORT(obj->pin); + bit = PIN_POS(obj->pin); + + base = BITBAND_PORT_BASE(port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + BITBAND_PORT_READ(val, base, bit); + if(val == GPIO_PIN_RESET) + BitValue = GPIO_PIN_RESET; + else + BitValue = GPIO_PIN_SET; + return (BitValue); +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h new file mode 100644 index 0000000000..04b381798d --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_include.h @@ -0,0 +1,355 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __GPIO_INCLUDE_H +#define __GPIO_INCLUDE_H + +#include +#include "TMPM3HQ.h" +#include "objects.h" +#include "serial_api.h" + +enum BitMode { + GPIO_PIN_RESET = 0, /* 0: Clear */ + GPIO_PIN_SET, /* 1: Set */ +}; + +enum PortFunction { + GPIO_Mode_DATA = 0x0, /* 0x0: PxDATA */ + GPIO_Mode_CR = 0x04, /* 0x4: PxCR */ + GPIO_Mode_FR1 = 0x08, /* 0x8: PxFR1 */ + GPIO_Mode_FR2 = 0x0C, /* 0xC: PxFR2 */ + GPIO_Mode_FR3 = 0x10, /* 0x10: PxFR3 */ + GPIO_Mode_FR4 = 0x14, /* 0x14: PxFR4 */ + GPIO_Mode_FR5 = 0x18, /* 0x18: PxFR5 */ + GPIO_Mode_FR6 = 0x1C, /* 0x1C: PxFR6 */ + GPIO_Mode_FR7 = 0x20, /* 0x20: PxFR7 */ + GPIO_Mode_OD = 0x28, /* 0x28: PxOD */ + GPIO_Mode_PUP = 0x2C, /* 0x2C: PxPUP */ + GPIO_Mode_PDN = 0x30, /* 0x30: PxPDN */ + GPIO_Mode_IE = 0x38 /* 0x38: PxIE */ +}; + +#define PORT_BASE (0x400C0000UL) /* Port Register Base Adress */ +#define BITBAND_PORT_OFFSET (0x0000100UL) /* Port Register Offset Value */ +#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) /* Operational target Port Adress */ +#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /* Operational target Control Register Adress */ +#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) /* Target Pin Bit set */ +#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) /* Target Pin Bit clear */ +#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) /* Target Pin Bit read */ + +/* PWM Macros */ +#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) +#define T32A_COUNT_DONT_START ((uint32_t)0x00000000) +#define T32A_RUN_DISABLE ((uint32_t)0x00000000) +#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) +#define T32A_OCR_DISABLE ((uint32_t)0x00000000) +#define T32A_MODE_16 ((uint32_t)0x00000000) /* 16bit Mode */ +#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /* prescaler */ +#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /* Enable */ +#define T32A_COUNT_UP ((uint32_t)0x00000000) /* count up */ +#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /* match up Timer Register */ +#define T32A_STOP_NON ((uint32_t)0x00000000) /* No use trigger */ +#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /* external trigger rising edge */ +#define T32A_OCR_SET ((uint32_t)0x00000001) /* Hi */ +#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /* Hi */ +#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /* Hi */ +#define T32A_IMx0_MASK_ALL ((uint32_t)0x0000000F) /* request */ +#define T32A_COUNT_DOWN ((uint32_t)0x00010000) +#define MAX_COUNTER_16B 0xFFFF +#define DEFAULT_CLOCK_DIVISION 32 +#define DEFAULT_PERIOD 0.02f + +/* RTC Configuration Macro */ +#define RTC_24_HOUR_MODE ((uint8_t)0x01) +#define PAGER_PAGE_ONE ((uint8_t)0x01) +#define PAGER_PAGE_ZERO ((uint8_t)0xEE) +#define RTC_CLK_ENABLE ((uint8_t)0x08) +#define RTC_CLK_DISABLE ((uint8_t)0xE7) +#define RTC_INT_ENABLE ((uint8_t)0x80) +#define RTC_CLEAR_ALL ((uint8_t)0x00) +#define RTC_RESET ((uint8_t)0xF7) +#define RTC_INT_SET ((uint8_t)0xFB) +#define RTC_INT_CLR ((uint8_t)0x04) +#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) +#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) +#define ELOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ +#define ELOSC_CFG_CLOCK ((uint32_t)(32768)) /* Clock(hz) */ +#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) /* WUPTL :High Bit Mask */ +#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) /* WULEF :Mask */ +#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) /* WULEF :[R] :Done */ +#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) /* WULON :[W] :Enable */ +#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) /* XTEN :[R/W] :Enable */ +#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro +#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro + +/* Serial Macros */ +#define UART0 TSB_UART0 +#define UART1 TSB_UART1 +#define UART2 TSB_UART2 +#define UART3 TSB_UART3 +#define UART4 TSB_UART4 +#define UART5 TSB_UART5 +#define UART_ENABLE_RX ((uint32_t)0x00000001) +#define UART_ENABLE_TX ((uint32_t)0x00000002) +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /* SWRSTF :Mask */ +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /* SWRSTF :During "Software Reset */ +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /* SWRST :"10" */ +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /* SWRST :"01" */ +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /* TFCLR :Clear the transmit buff */ +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /* RFCLR :Clear the receive buff */ +#define UART_PLESCALER_1 ((uint32_t)0x00000000) /* Boudrate Generator prescale 1/1 */ +#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /* Enable */ +#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /* Available */ +#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /* Available */ +#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) /* 1 stage */ +#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /* Minimum Value :K=0 */ +#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /* Maximum Value :K=63 */ +#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /* Minimum Value :N=1 */ +#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /* Maximum Value :N=65535 */ +typedef struct { + uint32_t ken; /* Enable/Disable Division Definition */ + uint32_t brk; /* Division Value K */ + uint32_t brn; /* Division Value N */ +} uart_boudrate_t; +/* Sleep Macros */ +#define CG_STBY_MODE_IDLE 0x00 +#define CG_STBY_MODE_STOP1 0x01 +#define EXTERNEL_OSC_MASK 0xFFFFFFF9 +#define IHOSC_CFG_WARM_UP_TIME ((uint32_t)(5000)) /* Warm up time(us) */ +#define IHOSC_CFG_CLOCK ((uint32_t)(10000000)) /* Clock(hz) */ +#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000) /* WUPT :High Bit Mask */ +#define CGWUPHCR_WUCLK_MASK ((uint32_t)0x00000100) /* WUCLK :Mask */ +#define CGWUPHCR_WUCLK_RW_IHOSC ((uint32_t)0x00000000) /* WUCLK :[R/W] :IHOSC */ + +/* SPI macros */ +typedef enum { + SPI_MASTER, + SPI_SLAVE +} spi_mode; +#define IS_SPI_MODULE(param) (((param) == SPI_0) || ((param) == SPI_1)) +#define TSPI_INT_ALL (uint32_t)0xF4 /* All above interrupt control */ +#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /* DR :Mask for 8bit */ +/* TSPI_SW_Reset SW Reset */ +#define TSPI_RESET10 ((uint32_t)0x00000010) /* RESET Pattarn 10 */ +#define TSPI_RESET01 ((uint32_t)0x00000001) /* RESET Pattarn 01 */ +/* TSPI_Enable TSPI Enable/Disable Control */ +#define TSPI_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_ENABLE ((uint32_t)0x00000001) /* Enable */ +/* TSPI_Triger_Control Triger Control */ +#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /* Enable */ +#define TSPI_SPI_MODE ((uint32_t)0x00000000) /* TSPI MODE */ +#define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) /* MASTER MODE */ +#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /* TWO WAY */ +#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) /* Single Transfer Frame :0 */ +#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /* Low */ +#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /* Hi */ +#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 0 */ +#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /* 8 */ +#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /* Disable */ +/* TSPI_Baudrate_Clock */ +#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /* T16 */ +#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /* 1/3 */ +#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /* MSB first */ +#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /* 8 bit */ +#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /* 0 */ +#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ +#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ +#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ +#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /* negative logic */ +#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /* 1st Edge Sampling */ +#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /* IDLE Term TSPII??SCK LOW */ +#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /* 1 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ +#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /* 1 x TSPIIxSCK */ +/* Format control1 Register */ +#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /* Odd Parity */ +#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /* Clear */ +#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /* Enable */ +#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /* TX_REACH_FILL_LEVEL_MASK */ +#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /* Send Data Complete Flag */ +#define TSPI_TX_DONE ((uint32_t)0x00400000) /* Send Data Complete */ +#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /* Disable MASK */ +#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /* Transfer Mode bit MASK */ +#define TSPI_RX_ONLY ((uint32_t)0x00000800) /* RECEIVE ONLY */ +#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /* Receive Data Complete Flag */ +#define TSPI_RX_DONE ((uint32_t)0x00000040) /* Send Data Complete */ +#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /* TX_REACH_FILL_LEVEL_MASK */ +#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /* Receive Data Complete Flag Clear */ +#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /* Clear */ + +/* Ticker Macros */ +#define T32A_MODE_32 ((uint32_t)0x00000001) +#define T32A_PRSCLx_32 ((uint32_t)0x30000000) +#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) +#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) +#define T32A_COUNT_STOP ((uint32_t)0x00000004) +#define T32A_COUNT_START ((uint32_t)0x00000002) +#define T32A_RUN_ENABLE ((uint32_t)0x00000001) + +/* I2C Macros */ + +#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080) +#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) +#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) +#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) +#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) +#define I2CxCR2_INIT ((uint32_t)0x00000008) +#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) +#define I2CxCR2_TRX ((uint32_t)0x00000040) +#define I2CxST_I2C ((uint32_t)0x00000001) +#define I2CxST_CLEAR ((uint32_t)0x0000000F) +#define I2CxCR1_ACK ((uint32_t)0x00000010) +#define I2CxSR_BB ((uint32_t)0x00000020) +#define I2CxSR_LRB ((uint32_t)0x00000001) +#define I2CxOP_RSTA ((uint32_t)0x00000008) +#define I2CxOP_SREN ((uint32_t)0x00000002) +#define I2CxOP_MFACK ((uint32_t)0x00000001) +#define I2CxOP_INIT ((uint32_t)0x00000084) +#define I2CxIE_CLEAR ((uint32_t)0x00000000) +#define I2CxPRS_PRCK ((uint32_t)0x0000000F) +#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) +// Slave Initial Settings. +#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) +#define I2CAR_SA_MASK ((uint32_t)0x000000FE) +#define I2CxSR_TRX ((uint32_t)0x00000040) +#define I2CxOP_SAST ((uint32_t)0x00000020) +#define I2CxIE_INTI2C ((uint32_t)0x00000001) +#define I2C_NO_DATA (0) +#define I2C_READ_ADDRESSED (1) +#define I2C_WRITE_GENERAL (2) +#define I2C_WRITE_ADDRESSED (3) +#define I2C_ACK (1) +#define I2C_TIMEOUT (100000) + +/* ADC macros */ +#define ADC_12BIT_RANGE 0xFFF +#define ADC_SCLK_1 ((uint32_t)0x00000000) /* SCLK : ADCLK/1 */ +#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /* RCUT : Normal */ +#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /* DACON : DAC on */ +#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /* ENINT :Disable */ +#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040) /* TRGS :Single */ +#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /* CNTDMEN :Disable */ +#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /* SGLDMEN :Disable */ +#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /* TRGDMEN :Disable */ +#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /* TRGEN :Disable */ +#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /* ADEN :Disable */ +#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /* ADEN :Enable */ +#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /* SGL :Enable */ +#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /* CNT :Disable */ +#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /* SNGF :Idle */ +#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /* SNGF :Running */ +#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /* ADRFn :Mask */ +#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /* ADRFn :Flag on */ +#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /* ADRn :Mask */ +#define ADC_SAMPLING_PERIOD_3V ((uint32_t)0x00000008) +#define ADC_MOD2_TMPM3Hx ((uint32_t)0x00000300) +#define ADC_MOD1_AVDD5_3V ((uint32_t)0x0000B001) + +/* RMC Include */ +#define RMC_LI_ENABLE ((uint32_t)0x80000000) /* Enable */ +#define RMC_EDI_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define RMC_LD_DISABLE ((uint32_t)0x00000000) /* Disable */ +#define RMC_PHM_DISABLE ((uint32_t)0x00000000) /* A remote control signal of the phase system isn't received */ +#define RMC_LL_MAX ((uint32_t)0x00000FF) /* Maximum Value(Disable Receiving End Interrupt) */ +#define RMC_THRESH_HIGH_MIN ((uint32_t)0x0000000) /* Minimum Value */ +#define RMC_POLARITY_POSITIVE ((uint32_t)0x0000000) /* Positive side */ +#define RMC_NOISE_REDUCTION_MIN ((uint32_t)0x0000000) /* Minimum Value */ +#define RMC_RX_DATA_BITS_MIN ((uint32_t)0x0000000) /* Minimum Value */ +#define RMC_CLK_LOW_SPEED ((uint32_t)0x00000000) /* Low speed clock(32.768kHz) */ +#define RMC_CYCLE_MAX_INT_OCCUR ((uint32_t)0x00002000) /* It occurs */ +#define RMC_LEADER_DETECT ((uint32_t)0x00000080) /* It detests */ +#define RMC_RX_BIT_NUM_MASK ((uint32_t)0x0000007F) /* Mask */ +#define RMCxEN_RMCEN_ENABLE ((uint32_t)0x00000001) /* RMCEN : Enable */ + +typedef struct { + uint32_t lcMax; /* Upper limit in a cycle period of leader detection */ + uint32_t lcMin; /* Lower limit in a cycle period of leader detection */ + uint32_t llMax; /* Upper limit in a low period of leader detection */ + uint32_t llMin; /* Lower limit in a low period of leader detection */ +} rmc_control1_t; + +typedef struct { + uint32_t lien; /* Enable a leader detection interrupt */ + uint32_t edien; /* Enable a remote control input falling edge interrupt */ + uint32_t cld; /* Enable a receive mode, that receives both remote control signals without leaders and with leaders */ + uint32_t phim; /* Setting of a remote control reception mode of the phase system */ + uint32_t ll; /* Setting at the timing of a "Receiving End Interrupt" by detection Low */ + uint32_t dmax; /* Setting at the timing of a "Receiving End Interrupt" by the cycle of the data bit */ +} rmc_control2_t; + +/* Receive Control Setting "3" */ +typedef struct { + uint32_t dath; /* Threshold value high setting of 3 price judgement of a Data bit */ + uint32_t datl; /* Threshold value low setting of 3 price judgement of a Data bit */ +} rmc_control3_t; + +/* Receive Control Setting "4" */ +typedef struct { + uint32_t po; /* Polarity choice of a remote control input signal */ + uint32_t nc; /* Setting of noise reduction time */ +} rmc_control4_t; + +/* Num of received end bit "1" */ +typedef struct { + uint32_t end1; /* Num of received data bits */ +} rmc_end1_t; + +/* Num of received end bit "2" */ +typedef struct { + uint32_t end2; /* Num of received data bits */ +} rmc_end2_t; + +/* Num of received end bit "3" */ +typedef struct { + uint32_t end3; /* Num of received data bits */ +} rmc_end3_t; + +/* Select source clock */ +typedef struct { + uint32_t clk; /* Select RMC sampling clock */ +} rmc_fssel_t; + +/* Initial setting structure definition */ +typedef struct { + rmc_control1_t cnt1; /* Receive Control Setting "1" */ + rmc_control2_t cnt2; /* Receive Control Setting "2" */ + rmc_control3_t cnt3; /* Receive Control Setting "3" */ + rmc_control4_t cnt4; /* Control4 setting */ + rmc_end1_t end1; /* Receive End Bit1 setting */ + rmc_end2_t end2; /* Receive End Bit2 setting */ + rmc_end3_t end3; /* Receive End Bit3 setting */ + rmc_fssel_t fssel; /* Select source clock */ +} rmc_initial_setting_t; + +/* RMC handle structure definition */ +typedef struct uart_handle { + TSB_RMC_TypeDef *p_instance; /* Registers base address */ + rmc_initial_setting_t init; /* Initial setting */ +} rmc_t; + +void rmc_init(rmc_t *p_obj); +void rmc_get_data(rmc_t *p_obj, uint32_t data[]); + + +#endif /* __GPIO_INCLUDE_H */ diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c new file mode 100644 index 0000000000..81fd7c1964 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_irq_api.c @@ -0,0 +1,437 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "gpio_include.h" +#include "mbed_critical.h" + +#define CHANNEL_NUM 32 + +const PinMap PinMap_GPIO_IRQ[] = { + {PC0, GPIO_IRQ_00, PIN_DATA(0, 0)}, + {PC1, GPIO_IRQ_01, PIN_DATA(0, 0)}, + {PC2, GPIO_IRQ_02, PIN_DATA(0, 0)}, + {PB1, GPIO_IRQ_03, PIN_DATA(0, 0)}, + {PJ4, GPIO_IRQ_04, PIN_DATA(0, 0)}, + {PK1, GPIO_IRQ_05, PIN_DATA(0, 0)}, + {PH3, GPIO_IRQ_06, PIN_DATA(0, 0)}, + {PA6, GPIO_IRQ_07, PIN_DATA(0, 0)}, + {PL3, GPIO_IRQ_08, PIN_DATA(0, 0)}, + {PM2, GPIO_IRQ_09, PIN_DATA(0, 0)}, + {PN3, GPIO_IRQ_10, PIN_DATA(0, 0)}, + {PA7, GPIO_IRQ_11, PIN_DATA(0, 0)}, + {PL4, GPIO_IRQ_12, PIN_DATA(0, 0)}, + {PK7, GPIO_IRQ_13, PIN_DATA(0, 0)}, + {PP3, GPIO_IRQ_14, PIN_DATA(0, 0)}, + {PM6, GPIO_IRQ_15, PIN_DATA(0, 0)}, + {PB7, GPIO_IRQ_16, PIN_DATA(0, 0)}, + {PV2, GPIO_IRQ_17_18, PIN_DATA(0, 0)}, + {PH4, GPIO_IRQ_19_22, PIN_DATA(0, 0)}, + {PT0, GPIO_IRQ_23_26, PIN_DATA(0, 0)}, + {PG2, GPIO_IRQ_27_28, PIN_DATA(0, 0)}, + {PT7, GPIO_IRQ_29, PIN_DATA(0, 0)}, + {PU0, GPIO_IRQ_30_31, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; +static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState ); +cg_intactivestate CurrentState; +static void INT_IRQHandler(PinName pin, uint32_t index); + +// Initialize gpio IRQ pin +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint8_t bit = 0; + uint32_t port_base = 0; + + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + + // Disable interrupt by CPU + core_util_critical_section_enter(); + + // Calculate port and pin position + obj->port = (PortName)PIN_PORT(pin); + obj->pin = pin; + bit = PIN_POS(pin); + + port_base = BITBAND_PORT_BASE(obj->port); + port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); + BITBAND_PORT_CLR(port_base, bit); + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + + // Get GPIO irq source + switch (obj->irq_id) { + case GPIO_IRQ_00: + obj->irq_src = CG_INT_SRC_01; + break; + case GPIO_IRQ_01: + obj->irq_src = CG_INT_SRC_02; + break; + case GPIO_IRQ_02: + obj->irq_src = CG_INT_SRC_03; + break; + case GPIO_IRQ_03: + obj->irq_src = CG_INT_SRC_04; + break; + case GPIO_IRQ_04: + obj->irq_src = CG_INT_SRC_05; + break; + case GPIO_IRQ_05: + obj->irq_src = CG_INT_SRC_06; + break; + case GPIO_IRQ_06: + obj->irq_src = CG_INT_SRC_07; + break; + case GPIO_IRQ_07: + obj->irq_src = CG_INT_SRC_08; + break; + case GPIO_IRQ_08: + obj->irq_src = CG_INT_SRC_09; + break; + case GPIO_IRQ_09: + obj->irq_src = CG_INT_SRC_0A; + break; + case GPIO_IRQ_10: + obj->irq_src = CG_INT_SRC_0B; + break; + case GPIO_IRQ_11: + obj->irq_src = CG_INT_SRC_0C; + break; + case GPIO_IRQ_12: + obj->irq_src = CG_INT_SRC_0D; + break; + case GPIO_IRQ_13: + obj->irq_src = CG_INT_SRC_0E; + break; + case GPIO_IRQ_14: + obj->irq_src = CG_INT_SRC_0F; + break; + case GPIO_IRQ_15: + obj->irq_src = CG_INT_SRC_10; + break; + case GPIO_IRQ_16: + obj->irq_src = CG_INT_SRC_11; + break; + case GPIO_IRQ_17_18: + obj->irq_src = CG_INT_SRC_12; + break; + case GPIO_IRQ_19_22: + obj->irq_src = CG_INT_SRC_14; + break; + case GPIO_IRQ_23_26: + obj->irq_src = CG_INT_SRC_18; + break; + case GPIO_IRQ_27_28: + obj->irq_src = CG_INT_SRC_1C; + break; + case GPIO_IRQ_29: + obj->irq_src = CG_INT_SRC_1E; + break; + case GPIO_IRQ_30_31: + obj->irq_src = CG_INT_SRC_1F; + break; + default: + break; + } + + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + + // Save irq id + channel_ids[obj->irq_src] = id; + + // Initialize interrupt event as both edges detection + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + CurrentState = CG_INT_ACTIVE_STATE_BOTH_EDGES; + // Set interrupt event and enable INTx clear + SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE); + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id); + + core_util_critical_section_exit(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_ids[obj->irq_src] = 0; +} + +// Set interrupt event of gpio_irq object +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint8_t bit = 0; + uint32_t port_base = 0; + + //Disable GPIO interrupt on obj + gpio_irq_disable(obj); + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_INVALID; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_INVALID; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else { + error("Not supported event\n"); + } + } + CurrentState = obj->event; + // Calculate port and pin position + bit = PIN_POS(obj->pin); + + port_base = BITBAND_PORT_BASE(obj->port); + port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); + + if(obj->event != CG_INT_ACTIVE_STATE_INVALID ) { + // Set interrupt event and enable INTx clear + SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE); + BITBAND_PORT_CLR(port_base, bit); + } else { + BITBAND_PORT_SET(port_base, bit); + } + //Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +// Enable gpio_irq object +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +// Disable gpio_irq object +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} + +static void INT_IRQHandler(PinName pin, uint32_t index) +{ + int port = 0; + uint8_t bit = 0; + uint32_t data = 0; + uint32_t port_base = 0; + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Clear interrupt request + SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, DISABLE); + + port_base = BITBAND_PORT_BASE(port); + port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA); + BITBAND_PORT_READ(data, port_base, bit); + + switch (data) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_ids[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_ids[index], IRQ_RISE); + break; + default: + break; + } + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_01 + index)); + + // Enable interrupt request + SetSTBYReleaseINTSrc((cg_intsrc)(CG_INT_SRC_01 + index), CurrentState, ENABLE); +} + +void INT00_IRQHandler(void) +{ + INT_IRQHandler(PC0, 0); +} + +void INT01_IRQHandler(void) +{ + INT_IRQHandler(PC1, 1); +} + +void INT02_IRQHandler(void) +{ + INT_IRQHandler(PC2, 2); +} + +void INT03_IRQHandler(void) +{ + INT_IRQHandler(PB1, 3); +} + +void INT04_IRQHandler(void) +{ + INT_IRQHandler(PJ4, 4); +} + +void INT05_IRQHandler(void) +{ + INT_IRQHandler(PK1, 5); +} + +void INT06_IRQHandler(void) +{ + INT_IRQHandler(PH3, 6); +} + +void INT07_IRQHandler(void) +{ + INT_IRQHandler(PA6, 7); +} + +void INT08_IRQHandler(void) +{ + INT_IRQHandler(PL3, 8); +} + +void INT09_IRQHandler(void) +{ + INT_IRQHandler(PM2, 9); +} + +void INT10_IRQHandler(void) +{ + INT_IRQHandler(PN3, 10); +} + +void INT11_IRQHandler(void) +{ + INT_IRQHandler(PA7, 11); +} + +void INT12_IRQHandler(void) +{ + INT_IRQHandler(PL4, 12); +} + +void INT13_IRQHandler(void) +{ + INT_IRQHandler(PK7, 13); +} + +void INT14_IRQHandler(void) +{ + INT_IRQHandler(PP3, 14); +} + +void INT15_IRQHandler(void) +{ + INT_IRQHandler(PM6, 15); +} + +void INT16_IRQHandler(void) +{ + INT_IRQHandler(PB7, 16); +} + +void INT17_18_IRQHandler(void) +{ + INT_IRQHandler(PV2, 17); +} + +void INT19_22_IRQHandler(void) +{ + INT_IRQHandler(PH4, 19); +} + +void INT23_26_IRQHandler(void) +{ + INT_IRQHandler(PT0, 23); +} + +void INT27_28_IRQHandler(void) +{ + INT_IRQHandler(PG2, 27); +} + +void INT29_IRQHandler(void) +{ + INT_IRQHandler(PT7, 29); +} + +void INT30_31_IRQHandler(void) +{ + INT_IRQHandler(PU0, 30); +} + +static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState) +{ + __IO uint8_t *p_imc; + + if(intsource < 3U || intsource == 13U) { + if(intsource == 13U) { + intsource = (cg_intsrc)3U; + } + p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource)); + *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); + } else { + if(intsource > 13U) { + intsource -= 4; + } else { + intsource -= 3; + } + p_imc = (__IO uint8_t *)(&TSB_IB->IMC066 + (intsource)); + *p_imc = (uint8_t)(0xC0 | ActiveState | NewState); + } + // Dummy read is need + { + __IO uint8_t imc = *p_imc; + } +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h new file mode 100644 index 0000000000..3569f43804 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/gpio_object.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) +#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) +#define GPIO_BIT_ALL ((uint8_t)0xFF) + +typedef enum { + CG_INT_SRC_01 = 0U, + CG_INT_SRC_02, + CG_INT_SRC_03, + CG_INT_SRC_04, + CG_INT_SRC_05, + CG_INT_SRC_06, + CG_INT_SRC_07, + CG_INT_SRC_08, + CG_INT_SRC_09, + CG_INT_SRC_0A, + CG_INT_SRC_0B, + CG_INT_SRC_0C, + CG_INT_SRC_0D, + CG_INT_SRC_0E, + CG_INT_SRC_0F, + CG_INT_SRC_10, + CG_INT_SRC_11, + CG_INT_SRC_12, + CG_INT_SRC_13, + CG_INT_SRC_14, + CG_INT_SRC_15, + CG_INT_SRC_16, + CG_INT_SRC_17, + CG_INT_SRC_18, + CG_INT_SRC_19, + CG_INT_SRC_1A, + CG_INT_SRC_1B, + CG_INT_SRC_1C, + CG_INT_SRC_1D, + CG_INT_SRC_1E, + CG_INT_SRC_1F, + CG_INT_SRC_20 +} cg_intsrc; + +typedef enum { + CG_INT_ACTIVE_STATE_L = 0x00U, + CG_INT_ACTIVE_STATE_H = 0x02U, + CG_INT_ACTIVE_STATE_FALLING = 0x04U, + CG_INT_ACTIVE_STATE_RISING = 0x06U, + CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, + CG_INT_ACTIVE_STATE_INVALID = 0x0AU +} cg_intactivestate; + +typedef struct { + PinName pin; + uint32_t mask; + PortName port; +} gpio_t; + +struct gpio_irq_s { + uint32_t mask; + PortName port; + PinName pin; + uint32_t irq_id; + cg_intactivestate event; + cg_intsrc irq_src; +}; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c new file mode 100644 index 0000000000..59e478c033 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/i2c_api.c @@ -0,0 +1,356 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "gpio_include.h" + +static const PinMap PinMap_I2C_SDA[] = { + {PC1, I2C_0, PIN_DATA(1, 2)}, + {PA5, I2C_1, PIN_DATA(1, 2)}, + {PL1, I2C_2, PIN_DATA(3, 2)}, + {PT0, I2C_3, PIN_DATA(1, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PC0, I2C_0, PIN_DATA(1, 2)}, + {PA4, I2C_1, PIN_DATA(1, 2)}, + {PL0, I2C_2, PIN_DATA(3, 2)}, + {PT1, I2C_3, PIN_DATA(1, 2)}, + {NC, NC, 0} +}; + +// Clock setting structure definition +typedef struct { + uint32_t sck; + uint32_t prsck; +} I2C_clock_setting_t; + +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { + 20, 24, 32, 48, 80, 144, 272, 528 +}; // SCK Divider value table + +I2C_clock_setting_t clk; +static uint32_t start_flag = 0; + +static int32_t wait_status(i2c_t *p_obj); +static void i2c_start_bit(i2c_t *obj); + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj != NULL); + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)i2c_name != NC); + + switch (i2c_name) { + case I2C_0: + TSB_CG_FSYSENB_IPENB11 = ENABLE; + TSB_CG_FSYSENA_IPENA02 = ENABLE; + obj->i2c = TSB_I2C0; + break; + case I2C_1: + TSB_CG_FSYSENB_IPENB12 = ENABLE; + TSB_CG_FSYSENA_IPENA00 = ENABLE; + obj->i2c = TSB_I2C1; + break; + case I2C_2: + TSB_CG_FSYSENB_IPENB13 = ENABLE; + TSB_CG_FSYSENA_IPENA10 = ENABLE; + obj->i2c = TSB_I2C2; + case I2C_3: + TSB_CG_FSYSENB_IPENB14 = ENABLE; + TSB_CG_FSYSENA_IPENA15 = ENABLE; + obj->i2c = TSB_I2C3; + break; + default: + error("I2C is not available"); + break; + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + i2c_reset(obj); + i2c_frequency(obj, 100000); + obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | + I2CxCR2_INIT); + obj->i2c->OP = I2CxOP_INIT; + obj->i2c->IE = I2CxIE_CLEAR; +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + uint64_t sck, tmp_sck; + uint64_t prsck, tmp_prsck; + uint64_t fscl, tmp_fscl; + uint64_t fx; + + SystemCoreClockUpdate(); + + if (hz <= 1000000) { + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)SystemCoreClock / prsck); + if ((fx < 20000000U) && (fx > 6666666U)) { + for (sck = 0; sck <= 7; sck++) { + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32) ? prsck : 0; + } + } + } + } + clk.sck = (uint32_t)tmp_sck; + clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0; + } + + obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); + obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); +} + +int i2c_start(i2c_t *obj) +{ + start_flag = 1; // Start Condition + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + uint32_t timeout = I2C_TIMEOUT; + + obj->i2c->CR2 = I2CxCR2_STOP_CONDITION; + while ((obj->i2c->SR & I2CxSR_BB) == I2CxSR_BB) { + if (timeout == 0) + break; + timeout--; + } + return 0; +} + +void i2c_reset(i2c_t *obj) +{ + obj->i2c->CR2 = I2CxCR2_SWRES_10; + obj->i2c->CR2 = I2CxCR2_SWRES_01; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t result = 0; + int32_t count = 0; + int32_t pdata = 0; + + if (length > 0) { + start_flag = 1; // Start Condition + if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { + while (count < length) { + pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); + if (pdata < 0) { + break; + } + data[count++] = (uint8_t)pdata; + } + result = count; + } else { + stop = 1; + result = I2C_ERROR_NO_SLAVE; + } + + if (stop) { // Stop Condition + i2c_stop(obj); + } + } + return (result); +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int32_t result = 0; + int32_t count = 0; + + start_flag = 1; // Start Condition + if (i2c_byte_write(obj, address) == I2C_ACK) { + while (count < length) { + if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { + break; + } + } + result = count; + } else { + stop = 1; + result = I2C_ERROR_NO_SLAVE; + } + + if (stop) { // Stop Condition + i2c_stop(obj); + } + return (result); +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t result; + + obj->i2c->ST = I2CxST_CLEAR; + if (last) { + obj->i2c->OP |= I2CxOP_MFACK; + } else { + obj->i2c->OP &= ~I2CxOP_MFACK; + } + obj->i2c->DBR = (0 & I2CxDBR_DB_MASK); + if (wait_status(obj) < 0) { + result = -1; + } else { + result = (int32_t)(obj->i2c->DBR & I2CxDBR_DB_MASK); + } + return (result); +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result; + + obj->i2c->ST = I2CxST_CLEAR; + if (start_flag == 1) { + obj->i2c->DBR = (data & I2CxDBR_DB_MASK); + i2c_start_bit(obj); + start_flag = 0; + } else { + obj->i2c->DBR = (data & I2CxDBR_DB_MASK); + } + + if (wait_status(obj) < 0) { + return (-1); + } + + if (!((obj->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +static void i2c_start_bit(i2c_t *obj) // Send START command +{ + uint32_t opreg; + opreg = obj->i2c->OP; + opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); + if ((obj->i2c->SR & I2CxSR_BB)) { + opreg |= I2CxOP_SREN; + } + obj->i2c->OP = opreg; + obj->i2c->CR2 |= I2CxCR2_START_CONDITION; +} + +static int32_t wait_status(i2c_t *p_obj) +{ + volatile int32_t timeout; + timeout = I2C_TIMEOUT; + while (!((p_obj->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) { + if ((timeout--) == 0) { + return (-1); + } + } + return (0); +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + if (enable_slave) { + obj->i2c->OP = I2CxOP_SLAVE_INIT; + obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); + obj->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); + obj->i2c->AR = (obj->address & I2CAR_SA_MASK); + obj->i2c->IE = I2CxIE_INTI2C; + } else { + i2c_reset(obj); + obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR | + I2CxCR2_INIT); + obj->i2c->OP = I2CxOP_INIT; + obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck); + obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck); + NVIC_DisableIRQ(obj->IRQn); + NVIC_ClearPendingIRQ(obj->IRQn); + obj->i2c->ST = I2CxST_CLEAR; + } +} + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = I2C_NO_DATA; + + if ((obj->i2c->ST & I2CxST_I2C) && (obj->i2c->OP & I2CxOP_SAST)) { + if ((obj->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) { + result = I2C_READ_ADDRESSED; + } else { + result = I2C_WRITE_ADDRESSED; + } + } + return (result); +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + + while (count < length) { + int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); + if ((obj->i2c->SR & I2CxSR_TRX)) { + return (count); + } else { + if (pdata < 0) { + break; + } + data[count++] = (uint8_t)pdata; + } + } + i2c_slave_mode(obj,1); + return (count); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + + while (count < length) { + if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { + break; + } + } + i2c_slave_mode(obj,1); + return (count); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + obj->address = address & I2CAR_SA_MASK; + i2c_slave_mode(obj,1); +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h b/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h new file mode 100644 index 0000000000..7a27af03e9 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/objects.h @@ -0,0 +1,113 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "TMPM3HQ.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t BaudRate; + uint32_t DataBits; + uint32_t StopBits; + uint32_t Parity; + uint32_t Mode; + uint32_t FlowCtrl; +} uart_inittypedef_t; + +struct port_s { + PortName port; + uint32_t mask; +}; + +typedef struct { + uint8_t PinDATA; + uint8_t PinCR; + uint8_t PinFR[FRMAX]; + uint8_t PinOD; + uint8_t PinPUP; + uint8_t PinPDN; + uint8_t PinIE; +} gpio_regtypedef_t; + +typedef struct { + __IO uint32_t DATA; + __IO uint32_t CR; + __IO uint32_t FR[FRMAX]; + uint32_t RESERVED0[1]; + __IO uint32_t OD; + __IO uint32_t PUP; + __IO uint32_t PDN; + uint32_t RESERVED1; + __IO uint32_t IE; +} TSB_Port_TypeDef; + +struct serial_s { + PinName pin; + uint32_t index; + TSB_UART_TypeDef * UARTx; + uart_inittypedef_t uart_config; +}; + +struct analogin_s { + PinName pin; + ADCName adc; + TSB_AD_TypeDef* obj; +}; + +struct dac_s { + DACName dac; + TSB_DA_TypeDef* handler; +}; + +struct pwmout_s { + PinName pin; + TSB_T32A_TypeDef * channel; + uint16_t trailing_timing; + uint16_t leading_timing; + uint16_t divisor; + float period; +}; + +struct i2c_s { + uint32_t address; + IRQn_Type IRQn; + TSB_I2C_TypeDef *i2c; +}; + +struct spi_s { + TSB_TSPI_TypeDef *spi; + SPIName module; + uint8_t bits; +}; + +extern const gpio_regtypedef_t GPIO_SFRs[]; +extern const uint32_t GPIO_Base[]; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c b/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c new file mode 100644 index 0000000000..9e05a6fe8c --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/pinmap.c @@ -0,0 +1,215 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "gpio_include.h" + +void pin_function(PinName pin, int function) +{ + int port = 0; + uint8_t bit = 0; + uint8_t func = 0; + uint8_t dir = 0; + uint32_t port_base = 0; + uint32_t mode_base = 0; + + /* Assert that pin is valid*/ + MBED_ASSERT(pin != NC); + + /* Calculate pin function and pin direction*/ + func = PIN_FUNC(function); + dir = PIN_DIR(function); + + /* Calculate port and pin position*/ + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + port_base = BITBAND_PORT_BASE(port); + /* Initialization PxFR OFF */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_CLR(mode_base, bit); + + /* Initialize Input */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, bit); + switch (func) { + case 0: + break; + case 1: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + break; + case 2: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + break; + case 3: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + break; + case 4: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + break; + case 5: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + break; + case 6: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + break; + case 7: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + break; + default: + break; + } + if (func != 0) + BITBAND_PORT_SET(mode_base, bit); + if(dir == PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, bit); + } else if(dir == PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, bit); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, bit); + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + int port = 0; + uint8_t bit = 0; + uint8_t val = 0; + + /* Assert that pin is valid*/ + MBED_ASSERT(pin != NC); + + /* Check if function is in range*/ + if (mode > OpenDrain) { + return; + } + + /* Calculate port and pin position*/ + port = PIN_PORT(pin); + bit = PIN_POS(pin); + val = (1 << bit); + + switch (port) { + case PortA: + if(mode == OpenDrain) TSB_PA->OD = val; + else if(mode == PullUp) TSB_PA->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PA->PDN = val; + break; + case PortB: + if(mode == OpenDrain) TSB_PB->OD = val; + else if(mode == PullUp) TSB_PB->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PB->PDN = val; + break; + case PortC: + if(mode == OpenDrain) TSB_PC->OD = val; + else if(mode == PullUp) TSB_PC->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PC->PDN = val; + break; + case PortD: + if(mode == OpenDrain) TSB_PD->OD = val; + else if(mode == PullUp) TSB_PD->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PD->PDN = val; + break; + case PortE: + if(mode == OpenDrain) TSB_PE->OD = val; + else if(mode == PullUp) TSB_PE->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PE->PDN = val; + break; + case PortF: + if(mode == OpenDrain) TSB_PF->OD = val; + else if(mode == PullUp) TSB_PF->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PF->PDN = val; + break; + case PortG: + if(mode == OpenDrain) TSB_PG->OD = val; + else if(mode == PullUp) TSB_PG->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PG->PDN = val; + break; + case PortH: + if(mode == PullDown) TSB_PH->PDN = val; + break; + case PortJ: + if(mode == OpenDrain) TSB_PJ->OD = val; + else if(mode == PullUp) TSB_PJ->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PJ->PDN = val; + break; + case PortK: + if(mode == OpenDrain) TSB_PK->OD = val; + else if(mode == PullUp) TSB_PK->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PK->PDN = val; + break; + case PortL: + if(mode == OpenDrain) TSB_PL->OD = val; + else if(mode == PullUp) TSB_PL->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PL->PDN = val; + break; + case PortM: + if(mode == OpenDrain) TSB_PM->OD = val; + else if(mode == PullUp) TSB_PM->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PM->PDN = val; + break; + case PortN: + if(mode == OpenDrain) TSB_PN->OD = val; + else if(mode == PullUp) TSB_PN->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PN->PDN = val; + break; + case PortP: + if(mode == OpenDrain) TSB_PP->OD = val; + else if(mode == PullUp) TSB_PP->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PP->PDN = val; + break; + case PortR: + if(mode == OpenDrain) TSB_PR->OD = val; + else if(mode == PullUp) TSB_PR->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PR->PDN = val; + break; + case PortT: + if(mode == OpenDrain) TSB_PT->OD = val; + else if(mode == PullUp) TSB_PT->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PT->PDN = val; + break; + case PortU: + if(mode == OpenDrain) TSB_PU->OD = val; + else if(mode == PullUp) TSB_PU->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PU->PDN = val; + break; + case PortV: + if(mode == OpenDrain) TSB_PV->OD = val; + else if(mode == PullUp) TSB_PV->PUP = val; + else if(mode == PullDown || mode == PullDefault) TSB_PV->PDN = val; + break; + default: + break; + } +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c new file mode 100644 index 0000000000..3ff6359bee --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/port_api.c @@ -0,0 +1,150 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_include.h" + +#define PORT_PIN_NUM 8 + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName) ((port << 3 ) | pin_n); + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortV); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + // Enabling Port Clock Supply + TSB_CG->FSYSENA |= (1<<(obj->port)); + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + if (obj->mask & (1 << i)) { // If the pin is used + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + if (obj->mask & (1 << i)) { // If the pin is used + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint8_t bit = 0; + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + // Set direction for masked pins + switch (dir) { + case PIN_INPUT: + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + pin_function((PinName)bit, PIN_INPUT); + } + } + break; + case PIN_OUTPUT: + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + pin_function((PinName)bit, PIN_OUTPUT); + } + } + break; + case PIN_INOUT: + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + pin_function((PinName)bit, PIN_INOUT); + } + } + break; + default: + break; + } +} + +void port_write(port_t *obj, int value) +{ + uint8_t port_data = 0; + uint8_t data = 0; + int bit = 0; + uint8_t val = 0; + uint32_t base; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + base = BITBAND_PORT_BASE(obj->port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + // Get current data of port + for (bit = 7; bit >= 0; bit--) { + BITBAND_PORT_READ(val, base, bit); + port_data <<= 1; + port_data |= val; + } + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + for (bit = 0; bit < PORT_PIN_NUM; bit++) { + if (((obj->mask >> bit) & 0x01) == 0x01) { + if(((data >> bit) & 0x01) == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, bit); + } else { + BITBAND_PORT_CLR(base, bit); + } + } + } +} + +int port_read(port_t *obj) +{ + uint8_t port_data = 0; + uint8_t data = 0; + int bit = 0; + uint8_t val = 0; + uint32_t base; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + base = BITBAND_PORT_BASE(obj->port); + base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA); + + // Get current data of port + for (bit = 7; bit >= 0; bit--) { + BITBAND_PORT_READ(val, base, bit); + port_data <<= 1; + port_data |= val; + } + // Calculate data of masked pins + data = port_data & obj->mask; + return data; +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c new file mode 100644 index 0000000000..88519dd98a --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/pwmout_api.c @@ -0,0 +1,195 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "pinmap.h" +#include "gpio_include.h" + +static const PinMap PinMap_PWM[] = { + {PB0, PWM_0, PIN_DATA(5, 1)}, + {PC0, PWM_1, PIN_DATA(4, 1)}, + {PJ0, PWM_2, PIN_DATA(4, 1)}, + {PK2, PWM_3, PIN_DATA(4, 1)}, + {PN0, PWM_4, PIN_DATA(4, 1)}, + {PL5, PWM_5, PIN_DATA(4, 1)}, + {PG2, PWM_6, PIN_DATA(4, 1)}, + {NC, NC, 0} +}; + +static const uint32_t prescale_tbl[] = { + 2, 8, 32, 128, 256, 512, 1024 +}; + +void pwmout_init(pwmout_t* obj, PinName pin) +{ + uint16_t counter = 0; + + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel + MBED_ASSERT(pwm != (PWMName)NC); + + switch (pwm) { + case PWM_0: + obj->channel = TSB_T32A1; + TSB_CG_FSYSENA_IPENA25 = ENABLE; + TSB_CG_FSYSENA_IPENA01 = ENABLE; + break; + case PWM_1: + obj->channel = TSB_T32A2; + TSB_CG_FSYSENA_IPENA26 = ENABLE; + TSB_CG_FSYSENA_IPENA02 = ENABLE; + break; + case PWM_2: + obj->channel = TSB_T32A3; + TSB_CG_FSYSENA_IPENA27 = ENABLE; + TSB_CG_FSYSENA_IPENA08 = ENABLE; + break; + case PWM_3: + obj->channel = TSB_T32A4; + TSB_CG_FSYSENA_IPENA28 = ENABLE; + TSB_CG_FSYSENA_IPENA09 = ENABLE; + break; + case PWM_4: + obj->channel = TSB_T32A5; + TSB_CG_FSYSENA_IPENA29 = ENABLE; + TSB_CG_FSYSENA_IPENA12 = ENABLE; + break; + case PWM_5: + obj->channel = TSB_T32A6; + TSB_CG_FSYSENA_IPENA30 = ENABLE; + TSB_CG_FSYSENA_IPENA10 = ENABLE; + break; + case PWM_6: + obj->channel = TSB_T32A7; + TSB_CG_FSYSENA_IPENA31 = ENABLE; + TSB_CG_FSYSENA_IPENA06 = ENABLE; + break; + default: + obj->channel = NULL; + break; + } + + pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM + obj->pin = pin; + obj->period = DEFAULT_PERIOD; + obj->divisor = DEFAULT_CLOCK_DIVISION; + obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP); + obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE); + obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); + obj->channel->OUTCRC0 = T32A_OCR_DISABLE; + obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); + counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor); + obj->channel->RGC0 = counter; + obj->channel->RGC1 = counter; + obj->trailing_timing = counter; + obj->leading_timing = counter; +} + +void pwmout_free(pwmout_t* obj) +{ + // Stops and clear count operation + obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + pwmout_write(obj, 0); + obj->pin = NC; + obj->channel = NULL; + obj->trailing_timing = 0; + obj->leading_timing = 0; + obj->divisor = 0; +} + +void pwmout_write(pwmout_t* obj, float value) +{ + obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again + obj->leading_timing = (obj->trailing_timing - + (obj->trailing_timing * value)); // leading_timing value + obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register + obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation +} + +float pwmout_read(pwmout_t* obj) +{ + float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) + / obj->trailing_timing); + return duty_cycle; +} + +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +void pwmout_period_us(pwmout_t* obj, int us) +{ + float seconds = 0; + int cycles = 0; + uint32_t clkdiv = 0; + int i = 0; + float duty_cycle = 0; + + seconds = (float)(us / 1000000.0f); + // Select highest timer resolution + for (i = 0; i < 7; ++i) { + cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds); + if (cycles <= MAX_COUNTER_16B) { + clkdiv = i + 1; // range 1:7 + clkdiv <<= 28; + break; + } else { + cycles = MAX_COUNTER_16B; + clkdiv = 7; + clkdiv <<= 28; + } + } + // Stop timer for setting clock again + obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + // Restore the duty-cycle + duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) + / obj->trailing_timing); + obj->trailing_timing = cycles; + obj->leading_timing = (cycles - (cycles * duty_cycle)); + // Change the source clock division and period + obj->channel->MOD = T32A_MODE_32; + obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx); + obj->channel->OUTCRC0 = T32A_OCR_DISABLE; + obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR); + obj->channel->RGC0 = obj->leading_timing; + obj->channel->RGC1 = obj->trailing_timing; + obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + float seconds = 0; + float value = 0; + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + + pwmout_write(obj, value); +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c new file mode 100644 index 0000000000..0adda061b9 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/serial_api.c @@ -0,0 +1,439 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "serial_api.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_include.h" +#include "objects.h" + +static const PinMap PinMap_UART_TX[] = { + {PA1, SERIAL_0, PIN_DATA(1, 1)}, + {PJ1, SERIAL_1, PIN_DATA(1, 1)}, + {PB2, SERIAL_2, PIN_DATA(5, 1)}, + {PA6, SERIAL_3, PIN_DATA(2, 1)}, + {PV6, SERIAL_4, PIN_DATA(1, 1)}, + {PN2, SERIAL_5, PIN_DATA(2, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PA2, SERIAL_0, PIN_DATA(1, 0)}, + {PJ2, SERIAL_1, PIN_DATA(1, 0)}, + {PB3, SERIAL_2, PIN_DATA(5, 0)}, + {PA7, SERIAL_3, PIN_DATA(2, 0)}, + {PV7, SERIAL_4, PIN_DATA(1, 0)}, + {PN3, SERIAL_5, PIN_DATA(2, 0)}, + {NC, NC, 0} +}; + +#define UART_NUM 6 + +static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; +int stdio_uart_inited = 0; +serial_t stdio_uart; + +static void uart_init(TSB_UART_TypeDef * UARTx, uart_inittypedef_t * InitStruct); +static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate); +static void uart_swreset(TSB_UART_TypeDef * UARTx); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart_name != NC); + + obj->index = uart_name; + switch (uart_name) { /* Initialize UART instance */ + case SERIAL_0: + obj->UARTx = UART0; + TSB_CG_FSYSENB_IPENB05 = ENABLE; + TSB_CG_FSYSENA_IPENA00 = ENABLE; + break; + case SERIAL_1: + obj->UARTx = UART1; + TSB_CG_FSYSENB_IPENB06 = ENABLE; + TSB_CG_FSYSENA_IPENA08 = ENABLE; + break; + case SERIAL_2: + obj->UARTx = UART2; + TSB_CG_FSYSENB_IPENB07 = ENABLE; + TSB_CG_FSYSENA_IPENA01 = ENABLE; + break; + case SERIAL_3: + obj->UARTx = UART3; + TSB_CG_FSYSENB_IPENB08 = ENABLE; + TSB_CG_FSYSENA_IPENA00 = ENABLE; + break; + case SERIAL_4: + obj->UARTx = UART4; + TSB_CG_FSYSENB_IPENB09 = ENABLE; + TSB_CG_FSYSENA_IPENA17 = ENABLE; + break; + case SERIAL_5: + obj->UARTx = UART5; + TSB_CG_FSYSENB_IPENB10 = ENABLE; + TSB_CG_FSYSENA_IPENA12 = ENABLE; + break; + default: + error("UART is not available"); + break; + } + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC && rx != NC) { + obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->uart_config.Mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->uart_config.Mode = UART_ENABLE_RX; + } + } + } + obj->uart_config.BaudRate = 9600; + obj->uart_config.DataBits = 8; + obj->uart_config.StopBits = 0; + obj->uart_config.Parity = ParityNone; + obj->uart_config.FlowCtrl = FlowControlNone; + + uart_init(obj->UARTx, &obj->uart_config); + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + obj->UARTx->TRANS = 0; + obj->UARTx->CR0 = 0; + obj->UARTx->CR1 = 0; + + uart_swreset(obj->UARTx); + + obj->uart_config.BaudRate = 0; + obj->uart_config.DataBits = 0; + obj->uart_config.StopBits = 0; + obj->uart_config.Parity = 0; + obj->uart_config.Mode = 0; + obj->uart_config.FlowCtrl = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->uart_config.BaudRate = baudrate; + uart_init(obj->UARTx, &obj->uart_config); +} +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits + + obj->uart_config.DataBits = data_bits; + obj->uart_config.StopBits = stop_bits; + obj->uart_config.Parity = parity; + uart_init(obj->UARTx, &obj->uart_config); +} + +void INTUART0TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], TxIrq); +} + +void INTUART0RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], RxIrq); +} + +void INTUART1TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], TxIrq); +} + +void INTUART1RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], RxIrq); +} +void INTUART2TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], TxIrq); +} + +void INTUART2RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], RxIrq); +} + +void INTUART3TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], TxIrq); +} + +void INTUART3RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], RxIrq); +} + +void INTUART4TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_4], TxIrq); +} + +void INTUART4RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_4], RxIrq); +} + +void INTUART5TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_5], TxIrq); +} + +void INTUART5RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_5], RxIrq); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTUART0RX_IRQn; + } else { + irq_n = INTUART0TX_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTUART1RX_IRQn; + } else { + irq_n = INTUART1TX_IRQn; + } + break; + case SERIAL_2: + if (irq == RxIrq) { + irq_n = INTUART2RX_IRQn; + } else { + irq_n = INTUART2TX_IRQn; + } + break; + case SERIAL_3: + if (irq == RxIrq) { + irq_n = INTUART3RX_IRQn; + } else { + irq_n = INTUART3TX_IRQn; + } + break; + case SERIAL_4: + if (irq == RxIrq) { + irq_n = INTUART4RX_IRQn; + } else { + irq_n = INTUART4TX_IRQn; + } + break; + case SERIAL_5: + if (irq == RxIrq) { + irq_n = INTUART5RX_IRQn; + } else { + irq_n = INTUART5TX_IRQn; + } + break; + default: + break; + } + NVIC_ClearPendingIRQ(irq_n); + if (enable) { + NVIC_EnableIRQ(irq_n); + } else { + NVIC_DisableIRQ(irq_n); + } +} + +int serial_getc(serial_t *obj) +{ + int data = 0; + + while (!serial_readable(obj)) { // Wait until Rx buffer is full + // Do nothing + } + + if (obj->uart_config.Mode & UART_ENABLE_TX) { + obj->UARTx->TRANS &= 0x0D; + } + + data = data | (obj->UARTx->DR & 0xFFU); + + if (obj->uart_config.Mode & UART_ENABLE_TX) { + obj->UARTx->TRANS |= UART_ENABLE_TX; + } + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + + while (!serial_writable(obj)) { + // Do nothing + } + + if (obj->uart_config.Mode & UART_ENABLE_RX) { + obj->UARTx->TRANS &= 0x0E; + } + + obj->UARTx->DR = c & 0xFFU; + + if (obj->uart_config.Mode & UART_ENABLE_RX) { + obj->UARTx->TRANS |= UART_ENABLE_RX; + } +} + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR & 0x0000000F) != 0) { + ret = 1; + } + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR &0x8000) == 0) { + ret = 1; + } + + return ret; +} + +void serial_clear(serial_t *obj) +{ + obj->UARTx->FIFOCLR = 0x03; +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + obj->UARTx->TRANS |= 0x08; +} + +void serial_break_clear(serial_t *obj) +{ + obj->UARTx->TRANS &= ~(0x08); +} + +static void uart_swreset(TSB_UART_TypeDef * UARTx) +{ + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + + UARTx->SWRST = UARTxSWRST_SWRST_10; + UARTx->SWRST = UARTxSWRST_SWRST_01; + + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } +} + +static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate) +{ + uint32_t clock = 0U; + uint32_t k = 0U; + uint64_t tx = 0U; + uint64_t work = 1U; + uint64_t p_range64 = 0U; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 1; + + SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency + clock = SystemCoreClock; + tx = (uint64_t)((uint64_t)clock << 6); + tx /= work; + tx64 = (uint64_t)((uint64_t)clock << 8); + tx64 /= work64; + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + + boud64 = (64U * boudrate); + p_range64 = ((boud64 / 100) * 3); + + for (k=UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) { + work = tx + k; + if (work >= (uint64_t)((uint64_t)1 << 6)) { + work -= (uint64_t)((uint64_t)1 << 6); + work >>= 6; + if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { + work64 = work <<6; + work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); + work64 = (tx64 / work64); + if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) { + brddiviser->brn = work; + brddiviser->brk = k; + break; + } + } + } + } +} + +static void uart_init(TSB_UART_TypeDef * UARTx, uart_inittypedef_t * InitStruct) +{ + uart_boudrate_t UTx_brd = {0}; + uint32_t brk; + uint32_t tmp; + uint32_t parity_check; + uint32_t data_length; + + UARTx->CLK = UART_PLESCALER_1; // Register Setting + uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate); + UTx_brd.ken = UART_DIVISION_ENABLE; + brk = (UTx_brd.brk << 16); + UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn); + parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0); + data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2); + tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length); + UARTx->CR0 = tmp; + UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); + UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); + UARTx->TRANS = InitStruct->Mode; +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c b/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c new file mode 100644 index 0000000000..9e1d93c2b1 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/sleep.c @@ -0,0 +1,75 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" +#include "gpio_include.h" + +static void warming_up_time(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + TSB_CG->STBYCR = CG_STBY_MODE_IDLE; + __DSB(); // Enter idle mode + __WFI(); +} + +void hal_deepsleep(void) +{ + uint32_t tmp; + // WDT sysclock enable + TSB_CG_FSYSENB_IPENB31 = ENABLE; + while ((TSB_FC->SR0 & 0x01) != 0x01); // Flash Wait + // Wait for end of Warming-up for IHOSC1 + while(TSB_CG_WUPHCR_WUEF); + // Set Warm-up clock to IHOSC1 + TSB_CG_WUPHCR_WUCLK = DISABLE; + // Set Warming-up time (xxxx) for IHOSC1 return from STOP1 mode + warming_up_time(); + // Set low power consumption mode STOP1 + TSB_CG->STBYCR = CG_STBY_MODE_STOP1; + // Set PLL of fsys to fosc(= PLL no USE) + TSB_CG_PLL0SEL_PLL0SEL = DISABLE; + // Wait for PLL status of fsys until off state(fosc = 0) + while(TSB_CG_PLL0SEL_PLL0ST); + TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys + TSB_CG_OSCCR_IHOSC1EN = ENABLE; // Enable IHOSC1 + TSB_CG_OSCCR_OSCSEL = DISABLE; // Set fosc to IHOSC1 + while(TSB_CG_OSCCR_OSCF); // Wait for fosc status until IHOSC1 + tmp = TSB_CG->OSCCR; // Set EHOSC off + tmp &= EXTERNEL_OSC_MASK; + TSB_CG->OSCCR = tmp; + TSB_CG_OSCCR_IHOSC2EN = DISABLE; //Stop IHOSC2 of OFD + // Wait for status of OFD until off ”0” + while(TSB_CG_OSCCR_IHOSC2F); + __DSB(); // Enter STOP1 mode + __WFI(); +} + +static void warming_up_time(void) +{ + uint32_t work; + uint64_t x; + x = (uint64_t)((uint64_t)(IHOSC_CFG_WARM_UP_TIME) * (uint64_t)(IHOSC_CFG_CLOCK)); + x = (uint64_t)(x / (uint64_t)(1000000)); + if (x > (uint64_t)(0xFFFF)) { + // invalid value + } + work = (uint32_t)x; + work &= (uint32_t)(0xFFFFFFF0); + work <<= 16; + work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK); + TSB_CG->WUPHCR = work; +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c b/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c new file mode 100644 index 0000000000..3fff8b5e28 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/spi_api.c @@ -0,0 +1,276 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "spi_api.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "gpio_include.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {PM0, SPI_0, PIN_DATA(3, 1)}, + {PB2, SPI_1, PIN_DATA(3, 1)}, + {PT2, SPI_2, PIN_DATA(1, 1)}, + {PP5, SPI_3, PIN_DATA(1, 1)}, + {PH4, SPI_4, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {PM1, SPI_0, PIN_DATA(3, 1)}, + {PB3, SPI_1, PIN_DATA(3, 1)}, + {PT3, SPI_2, PIN_DATA(1, 1)}, + {PP4, SPI_3, PIN_DATA(1, 1)}, + {PH5, SPI_4, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PM2, SPI_0, PIN_DATA(3, 0)}, + {PB4, SPI_1, PIN_DATA(3, 0)}, + {PT4, SPI_2, PIN_DATA(1, 0)}, + {PP3, SPI_3, PIN_DATA(1, 0)}, + {PH6, SPI_4, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PM3, SPI_0, PIN_DATA(3, 1)}, + {PB5, SPI_1, PIN_DATA(3, 1)}, + {PT1, SPI_2, PIN_DATA(2, 1)}, + {PP6, SPI_3, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + TSB_TSPI_TypeDef* spi; + // Check pin parameters + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl); + spi = obj->spi; + switch ((int)obj->module) { + case SPI_0: + TSB_CG_FSYSENA_IPENA11 = ENABLE; + TSB_CG_FSYSENB_IPENB00 = ENABLE; + spi = TSB_TSPI0; + break; + case SPI_1: + TSB_CG_FSYSENA_IPENA01 = ENABLE; + TSB_CG_FSYSENB_IPENB01 = ENABLE; + spi = TSB_TSPI1; + break; + case SPI_2: + TSB_CG_FSYSENA_IPENA15 = ENABLE; + TSB_CG_FSYSENB_IPENB02 = ENABLE; + spi = TSB_TSPI2; + break; + case SPI_3: + TSB_CG_FSYSENA_IPENA13 = ENABLE; + TSB_CG_FSYSENB_IPENB03 = ENABLE; + spi = TSB_TSPI3; + break; + case SPI_4: + TSB_CG_FSYSENA_IPENA07 = ENABLE; + TSB_CG_FSYSENB_IPENB04 = ENABLE; + spi = TSB_TSPI4; + break; + default: + error("Cannot found SPI module corresponding with input pins."); + break; + } + obj->spi = spi; + // pin out the SPI pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + // TTSPI Software Reset + spi->CR0 = TSPI_RESET10; + spi->CR0 = TSPI_RESET01; + + // Wait for 2 clocks of reset completion + __NOP(); + __NOP(); + + // Enable the selected TSPI peripheral (TTSPIE) + spi->CR0 = TSPI_ENABLE; + spi->CR1 = 0; + spi->CR1 = TSPI_MASTER_OPEARTION; + spi->CR2 = 0; + spi->CR2 = (TSPI_TIDLE_LOW | TSPI_TXDEMP_HI); + // Format control0 Register Set + spi->FMTR0 = (TSPI_DATA_DIRECTION_MSB | TSPI_DATA_LENGTH_8 | + TSPI_MIN_IDLE_TIME_1); + // Format control1 Register Set + spi->FMTR1 = 0; + // Enable the selected TSPI peripheral + spi->CR0 |= TSPI_ENABLE; + spi_frequency(obj, 1000000); +} + +void spi_free(spi_t *obj) +{ + TSB_TSPI_TypeDef* spi; + + spi = obj->spi; + spi->CR0 |= TSPI_DISABLE; + spi->CR2 = TSPI_INT_ALL; // Disable all interrupt +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + TSB_TSPI_TypeDef* spi; + + obj->bits = bits; + spi = obj->spi; + obj->bits = bits; + spi->CR0 |= TSPI_DISABLE; + + if (bits >= 8 || bits <= 32) { + spi->FMTR0 |= (bits << 24); + } else { + // Do nothing + } + spi->FMTR0 |= (((mode >> 1) & 0x1) << 14); + spi->FMTR0 |= ((mode & 0x01) << 15); + spi->CR0 |= TSPI_ENABLE; +} + +void spi_frequency(spi_t *obj, int hz) +{ + TSB_TSPI_TypeDef* spi; + int clk_div = 1; + uint32_t clocks = ((SystemCoreClock / 2) / hz); + obj->spi->CR0 |= TSPI_DISABLE; + + while (clk_div < 10) { + if (clocks < 16) { + break; + } + clk_div++; + clocks >>= 1; + } + clk_div--; + if (clk_div == 0) { + clocks++; + } + spi = obj->spi; + spi->CR0 |= TSPI_DISABLE; + spi->BR = ((clk_div << 4) | clocks); + spi->CR0 |= TSPI_ENABLE; +} + +int spi_master_write(spi_t *obj, int value) +{ + TSB_TSPI_TypeDef* spi; + MBED_ASSERT(obj != NULL); + spi = obj->spi; + spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; // FIFO Cear + // Check if the TSPI is already enabled + if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + spi->CR0 |= TSPI_ENABLE; + } + // Enable TSPI Transmission Control + spi->CR1 |= TSPI_TRXE_ENABLE; + // Check the current fill level + if(((spi->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { + do { + spi->DR = (value & TSPI_DR_8BIT_MASK); + // check complete transmit + } while ((spi->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE); + spi->CR3 |= TSPI_TX_BUFF_CLR_DONE; + spi->CR1 &= TSPI_TRXE_DISABLE_MASK; + } + if((spi->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + // Enable TSPI Transmission Control + spi->CR1 |= TSPI_TRXE_ENABLE; + } + // Check if the TSPI is already enabled + if((spi->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + // Enable TSPI Transmission Control + spi->CR0 |= TSPI_ENABLE; + } + value = 0; + // Wait until Receive Complete Flag is set to receive data + if((spi->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { + // Check the remain data exist + if((spi->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { + value = (spi->DR & TSPI_DR_8BIT_MASK); + } + spi->SR |= TSPI_RX_DONE_CLR; // Receive Complete Flag is clear + spi->CR2 |= TSPI_RX_BUFF_CLR_DONE; // FIFO Clear + spi->CR1 &= TSPI_TRXE_DISABLE_MASK; + } + return value; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_busy(spi_t *obj) +{ + TSB_TSPI_TypeDef* spi; + uint8_t result = 0; + + spi = obj->spi; + if( (spi->SR & (1<<7)) || (spi->SR & (1<<23))) { + result = 1; + } else { + result = 0; + } + return result; +} + +uint8_t spi_get_module(spi_t *obj) +{ + return (uint8_t)(obj->module); +} diff --git a/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c b/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c new file mode 100644 index 0000000000..6a0ef9f851 --- /dev/null +++ b/targets/TARGET_TT/TARGET_TT_M3HQ/us_ticker.c @@ -0,0 +1,101 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "gpio_include.h" + + +#define T32A_INT_MASK ((uint32_t)0x0000000F) +#define TXZ_ENABLE 1 +static bool us_ticker_inited = false; // Is ticker initialized yet? + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + 1248125, // (39.94 MHz / 32 ) + 32 // 32 bit counter + }; + return &info; +} + +void us_ticker_init(void) +{ + if (us_ticker_inited) { + us_ticker_disable_interrupt(); + return; + } + us_ticker_inited = true; + + TSB_CG_FSYSENA_IPENA24 = TXZ_ENABLE; + TSB_T32A0->MOD = T32A_MODE_32; + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->CRC = T32A_PRSCLx_32; + TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); + + NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INTT32A00C_IRQn); +} + +uint32_t us_ticker_read(void) +{ + if (!us_ticker_inited) { + us_ticker_init(); + } + + return (TSB_T32A0->TMRC); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + NVIC_DisableIRQ(INTT32A00C_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->RGC1 = timestamp; + NVIC_EnableIRQ(INTT32A00C_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INTT32A00C_IRQn); + NVIC_EnableIRQ(INTT32A00C_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + // Disable interrupts by NVIC + NVIC_DisableIRQ(INTT32A00C_IRQn); + NVIC_ClearPendingIRQ(INTT32A00C_IRQn); + TSB_T32A0->STC = T32A_INT_MASK; +} + +void us_ticker_clear_interrupt(void) +{ + TSB_T32A0->STC = T32A_INT_MASK; + NVIC_ClearPendingIRQ(INTT32A00C_IRQn); +} + +void us_ticker_free(void) +{ + TSB_T32A0->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + us_ticker_inited = false; + TSB_T32A0->STC = 0x0F; + // Clear Pending interrupt in NVIC + NVIC_ClearPendingIRQ(INTT32A00C_IRQn); + // Disable interrupt in NVIC + NVIC_DisableIRQ(INTT32A00C_IRQn); + // Disable Clock. + TSB_CG_FSYSENA_IPENA24 = 0; +} diff --git a/targets/TARGET_TT/mbed_rtx.h b/targets/TARGET_TT/mbed_rtx.h new file mode 100644 index 0000000000..10ae73dba7 --- /dev/null +++ b/targets/TARGET_TT/mbed_rtx.h @@ -0,0 +1,29 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + + +#if defined(TARGET_TT_M3HQ) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20010000UL) +#endif + +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar index a35d3bea92..58181b8f34 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar and b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.ar differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar index b66788e1fa..f57b893173 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar and b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.ar differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar index e76307dcdc..31224614d7 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar and b/targets/TARGET_WICED/TOOLCHAIN_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.ar differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a index af353cea56..856c968bb3 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a and b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a index 06bfc1cd5d..9002c7adee 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a and b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a index 6fd927a5d7..2da717b52f 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a and b/targets/TARGET_WICED/TOOLCHAIN_GCC_ARM/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a index f908ee0d92..ca7d56ba3c 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a and b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_ADV_WISE_1530/libwiced_drivers.a differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a index cd858cb0e8..4aed83e010 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a and b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_MXCHIP_EMW3166/libwiced_drivers.a differ diff --git a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a index 575ffd6f62..2188395a4c 100644 Binary files a/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a and b/targets/TARGET_WICED/TOOLCHAIN_IAR/TARGET_MTB_USI_WM_BN_BM_22/libwiced_drivers.a differ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c index 14fd15d73b..e7912d6d59 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c +++ b/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c @@ -82,6 +82,12 @@ static inline uint16_t adc_read(analogin_t *obj) case PC_10: adc_ch = ADC_CH5; break; + case PC_09: + adc_ch = ADC_CH6; + break; + case PC_08: + adc_ch = ADC_CH7; + break; default: return 0; } diff --git a/targets/targets.json b/targets/targets.json index beb5618d79..417d3c3ba1 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -33,8 +33,7 @@ }, "mpu-rom-end": { "help": "Last address of ROM protected by the MPU", - "value": "0x0fffffff", - "macro_name": "MPU_ROM_END" + "value": "0x0fffffff" } } }, @@ -1646,6 +1645,7 @@ "macros": ["FSL_RTOS_MBED", "USE_EXTERNAL_RTC"], "default_toolchain": "ARM", "default_lib": "std", + "forced_reset_timeout": 7, "release_versions": ["2", "5"] }, "RAPIDIOT_K64F": { @@ -1685,10 +1685,46 @@ "TRNG", "FLASH" ], - "forced_reset_timeout": 7, "device_name": "MK64FN1M0xxx12", "bootloader_supported": true }, + "RAPIDIOT_KW41Z": { + "inherits": ["RAPIDIOT"], + "core": "Cortex-M0+", + "extra_labels": [ + "Freescale", + "MCUXpresso_MCUS", + "KSDK2_MCUS", + "KW41Z" + ], + "macros_add": ["CPU_MKW41Z512VHT4"], + "is_disk_virtual": true, + "mbed_rom_start": "0x00004000", + "mbed_rom_size": "0x7C000", + "detect_code": ["0234"], + "device_has": [ + "USTICKER", + "LPTICKER", + "ANALOGIN", + "ANALOGOUT", + "I2C", + "I2CSLAVE", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SLEEP", + "SPI", + "SPISLAVE", + "TRNG", + "STDIO_MESSAGES", + "FLASH" + ], + "device_name": "MKW41Z512xxx4", + "bootloader_supported": true + }, "K66F": { "supported_form_factors": ["ARDUINO"], "components_add": ["SD", "FLASHIAP"], @@ -1808,6 +1844,9 @@ "value": 1 } }, + "overrides": { + "deep-sleep-latency": 3 + }, "device_has": [ "USTICKER", "LPTICKER", @@ -1916,9 +1955,9 @@ "core": "Cortex-M4F", "supported_toolchains": ["ARM", "IAR", "GCC_ARM"], "extra_labels": [ - "NXP", - "MCUXpresso_MCUS", - "LPC", + "NXP", + "MCUXpresso_MCUS", + "LPC", "NXP_EMAC" ], "is_disk_virtual": true, @@ -2339,6 +2378,10 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0744"], "device_has_add": [ "ANALOGOUT", @@ -2510,8 +2553,13 @@ "value": 1 } }, + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0743"], - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "macros_add": [ + "MBED_TICKLESS", + "USB_STM_HAL", + "USBHOST_OTHER" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -2547,8 +2595,13 @@ "value": 1 } }, + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0743"], - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "macros_add": [ + "MBED_TICKLESS", + "USB_STM_HAL", + "USBHOST_OTHER" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -2604,7 +2657,10 @@ "STM32F429xI", "STM_EMAC" ], - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "macros_add": [ + "USB_STM_HAL", + "USBHOST_OTHER" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -2661,6 +2717,7 @@ "ANALOGOUT", "CAN", "EMAC", + "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH", @@ -2768,7 +2825,10 @@ "value": 1 } }, - "macros_add": ["USBHOST_OTHER"], + "macros_add": [ + "MBED_TICKLESS", + "USBHOST_OTHER" + ], "supported_form_factors": ["ARDUINO"], "detect_code": ["0816"], "device_has_add": [ @@ -2785,6 +2845,7 @@ "device_name": "STM32F746ZG", "bootloader_supported": true, "overrides": { + "lpticker_delay_ticks": 4, "network-default-interface-type": "ETHERNET" } }, @@ -2815,7 +2876,7 @@ } }, "macros_add": [ - "TRANSACTION_QUEUE_SIZE_SPI=2", + "MBED_TICKLESS", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT" ], @@ -2834,6 +2895,7 @@ "release_versions": ["2", "5"], "device_name": "STM32F756ZG", "overrides": { + "lpticker_delay_ticks": 4, "network-default-interface-type": "ETHERNET" } }, @@ -2868,7 +2930,10 @@ } }, "supported_form_factors": ["ARDUINO"], - "macros_add": ["USBHOST_OTHER"], + "macros_add": [ + "MBED_TICKLESS", + "USBHOST_OTHER" + ], "detect_code": ["0818"], "device_has_add": [ "ANALOGOUT", @@ -2884,6 +2949,7 @@ "device_name": "STM32F767ZI", "bootloader_supported": true, "overrides": { + "lpticker_delay_ticks": 4, "network-default-interface-type": "ETHERNET" } }, @@ -2982,6 +3048,9 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0760"], "device_has_add": [ @@ -3035,6 +3104,10 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0770"], "device_has_add": [ "ANALOGOUT", @@ -3066,6 +3139,10 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0779"], "device_has_add": [ "ANALOGOUT", @@ -3126,8 +3203,13 @@ "value": 1 } }, + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0765"], - "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], + "macros_add": [ + "MBED_TICKLESS", + "USBHOST_OTHER", + "TWO_RAM_REGIONS" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -3185,8 +3267,10 @@ "value": 1 } }, + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0827"], "macros_add": [ + "MBED_TICKLESS", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT", "TWO_RAM_REGIONS" @@ -3247,17 +3331,31 @@ "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", - "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], + "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "program_cycle_s": 2, "extra_labels_add": [ "STM32F4", "STM32F407", "STM32F407xG", - "STM32F407VG" + "STM32F407VG", + "STM_EMAC" ], - "device_has_add": ["ANALOGOUT", "TRNG", "FLASH", "MPU"], - "release_versions": ["2"], - "device_name": "STM32F407VG" + "device_has_add": ["ANALOGOUT", "TRNG", "FLASH", "EMAC", "MPU"], + "device_has_remove": ["LPTICKER"], + "macros_add": ["USB_STM_HAL"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_HSE_XTAL", + "macro_name": "CLOCK_SOURCE" + } + }, + "release_versions": ["2", "5"], + "overrides": {"lse_available": 0}, + "device_name": "STM32F407VG", + "overrides": { + "network-default-interface-type": "ETHERNET" + } }, "WIO_3G": { "inherits": ["FAMILY_STM32"], @@ -3557,6 +3655,9 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0833"], "device_has_add": [ @@ -3602,6 +3703,7 @@ "STM32F746NG", "STM_EMAC" ], + "components_add": ["QSPIF"], "supported_form_factors": ["ARDUINO"], "config": { "clock_source": { @@ -3619,7 +3721,11 @@ } }, "detect_code": ["0815"], - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "macros_add": [ + "MBED_TICKLESS", + "USB_STM_HAL", + "USBHOST_OTHER" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -3634,6 +3740,7 @@ "device_name": "STM32F746NG", "bootloader_supported": true, "overrides": { + "lpticker_delay_ticks": 4, "network-default-interface-type": "ETHERNET" } }, @@ -3647,6 +3754,7 @@ "STM32F769NI", "STM_EMAC" ], + "components_add": ["QSPIF"], "supported_form_factors": ["ARDUINO"], "config": { "flash_dual_bank": { @@ -3664,7 +3772,11 @@ } }, "detect_code": ["0817"], - "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], + "macros_add": [ + "MBED_TICKLESS", + "USB_STM_HAL", + "USBHOST_OTHER" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -3672,12 +3784,14 @@ "SERIAL_ASYNCH", "TRNG", "FLASH", - "MPU" + "MPU", + "QSPI" ], "bootloader_supported": true, "release_versions": ["2", "5"], "device_name": "STM32F769NI", "overrides": { + "lpticker_delay_ticks": 4, "network-default-interface-type": "ETHERNET" } }, @@ -3697,9 +3811,14 @@ "value": 1 } }, + "overrides": { "lpticker_delay_ticks": 4 }, "supported_form_factors": ["ARDUINO"], "detect_code": ["0764"], - "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], + "macros_add": [ + "MBED_TICKLESS", + "USBHOST_OTHER", + "TWO_RAM_REGIONS" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -3729,8 +3848,13 @@ "value": 1 } }, + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0820"], - "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"], + "macros_add": [ + "MBED_TICKLESS", + "USBHOST_OTHER", + "TWO_RAM_REGIONS" + ], "device_has_add": [ "ANALOGOUT", "CAN", @@ -3775,7 +3899,6 @@ "inherits": ["FAMILY_STM32"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F4", "STM32F411RE"], - "device_has_add": ["MPU"], "config": { "modem_is_on_board": { "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.", @@ -4041,6 +4164,7 @@ "MTB_UBLOX_ODIN_W2": { "inherits": ["MODULE_UBLOX_ODIN_W2"], "device_has_add": [], + "overrides": {"lse_available": 0}, "release_versions": ["5"] }, "UBLOX_C030": { @@ -4073,7 +4197,6 @@ "HSE_VALUE=12000000", "GNSSBAUD=9600" ], - "overrides": { "lse_available": 0 }, "device_has_add": [ "ANALOGOUT", "EMAC", @@ -4086,6 +4209,7 @@ "device_name": "STM32F437VG", "bootloader_supported": true, "overrides": { + "lse_available": 0, "network-default-interface-type": "ETHERNET" } }, @@ -4936,6 +5060,7 @@ "inherits": ["RZ_A1XX"], "supported_form_factors": ["ARDUINO"], "extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"], + "components_add": ["SD"], "device_has_add": ["EMAC", "FLASH", "LPTICKER"], "release_versions": ["2", "5"], "device_name": "R7S72100", @@ -4951,6 +5076,7 @@ "inherits": ["RZ_A1XX"], "supported_form_factors": ["ARDUINO"], "extra_labels_add": ["RZA1UL", "MBRZA1LU"], + "components_add": ["SD"], "device_has_add": ["TRNG", "FLASH", "LPTICKER"], "device_has_remove": ["ETHERNET"], "release_versions": ["2", "5"], @@ -6589,6 +6715,11 @@ "device_name": "nRF52832_xxAA", "detect_code": ["0466"] }, + "MTB_ACONNO_ACN52832": { + "inherits": ["MCU_NRF52832"], + "release_versions": ["5"], + "device_name": "nRF52832_xxAA" + }, "DELTA_DFBM_NQ620": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52832"], @@ -6658,6 +6789,9 @@ "value": 0 } }, + "overrides": { + "mpu-rom-end": "0x1fffffff" + }, "OUTPUT_EXT": "hex", "is_disk_virtual": true, "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], @@ -6856,6 +6990,7 @@ "LPTICKER", "RTC", "ANALOGIN", + "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", @@ -6921,6 +7056,7 @@ "LPTICKER", "RTC", "ANALOGIN", + "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", @@ -7081,6 +7217,7 @@ "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"], + "components_add": ["QSPIF"], "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", @@ -7092,6 +7229,10 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0822"], "device_has_add": [ "ANALOGOUT", @@ -7101,7 +7242,8 @@ "SERIAL_FC", "TRNG", "FLASH", - "MPU" + "MPU", + "QSPI" ], "release_versions": ["2", "5"], "device_name": "STM32L496AG", @@ -7123,6 +7265,10 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0823"], "device_has_add": [ "ANALOGOUT", @@ -7158,6 +7304,10 @@ "value": 1 } }, + "macros_add": [ + "MBED_TICKLESS" + ], + "overrides": { "lpticker_delay_ticks": 4 }, "detect_code": ["0776"], "device_has_add": [ "ANALOGOUT", @@ -7173,6 +7323,10 @@ "device_name": "STM32L4R5ZI", "bootloader_supported": true }, + "NUCLEO_L4R5ZI_P": { + "inherits": ["NUCLEO_L4R5ZI"], + "detect_code": ["0781"] + }, "VBLUNO52": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52832"], @@ -7219,6 +7373,7 @@ "LPTICKER", "RTC", "ANALOGIN", + "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", @@ -7446,6 +7601,9 @@ "value": "GPIO_DBCTL_DBCLKSEL_16" } }, + "overrides": { + "mpu-rom-end": "0x1fffffff" + }, "inherits": ["Target"], "device_has": [ "USTICKER", @@ -7613,7 +7771,7 @@ "extra_labels_add": ["CY8C63XX", "CORDIO"], "macros_add": ["CY8C6347BZI_BLD53"], "detect_code": ["6000"], - "m0_core_img": "psoc63_m0_default_1.01.hex", + "m0_core_img": "psoc63_m0_default_1.02.hex", "post_binary_hook": { "function": "PSOC6Code.complete" }, @@ -7723,5 +7881,76 @@ "UNO_91H": { "inherits": ["RDA5981X"], "detect_code": ["8001"] + }, + "GD32_Target": { + "inherits": ["Target"], + "public": false, + "extra_labels": ["GigaDevice"], + "supported_toolchains": ["ARM", "IAR", "GCC_ARM"], + "device_has": [ + "USTICKER", + "ANALOGIN", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL" + ] + }, + "GD32_F307VG": { + "inherits": ["GD32_Target"], + "supported_form_factors": ["ARDUINO"], + "core": "Cortex-M4", + "extra_labels_add": ["GD32F30X", "GD32F307VG", "GD_EMAC"], + "device_has_add": [ + "RTC", + "I2C", + "CAN", + "I2CSLAVE", + "ANALOGOUT", + "SPI", + "SPISLAVE", + "SERIAL_ASYNCH", + "SERIAL_FC", + "EMAC", + "FLASH", + "SLEEP", + "MPU" + ], + "detect_code": ["1701"], + "macros_add": ["GD32F30X_CL"], + "release_versions": ["5"], + "overrides": { + "network-default-interface-type": "ETHERNET" + } + }, + "TT_M3HQ": { + "inherits": ["Target"], + "core": "Cortex-M3", + "is_disk_virtual": true, + "extra_labels": ["TT"], + "macros": ["__TT_M3HQ__"], + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "device_has": [ + "ANALOGIN", + "USTICKER", + "ANALOGOUT", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SLEEP", + "SPI", + "I2C", + "I2CSLAVE", + "STDIO_MESSAGES", + "MPU" + ], + "device_name": "TMPM3HQFDFG", + "detect_code": ["8012"], + "release_versions": ["5"] } } diff --git a/tools/build_api.py b/tools/build_api.py index a6bb06add0..0faf8eadb8 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -401,6 +401,7 @@ def _fill_header(region_list, current_region): start += Config.header_member_size(member) return header + def merge_region_list(region_list, destination, notify, padding=b'\xFF'): """Merge the region_list into a single image @@ -411,7 +412,6 @@ def merge_region_list(region_list, destination, notify, padding=b'\xFF'): """ merged = IntelHex() _, format = splitext(destination) - notify.info("Merging Regions") for region in region_list: @@ -426,20 +426,17 @@ def merge_region_list(region_list, destination, notify, padding=b'\xFF'): notify.info(" Filling region %s with %s" % (region.name, region.filename)) part = intelhex_offset(region.filename, offset=region.start) part.start_addr = None - part_size = (part.maxaddr() - part.minaddr()) + 1 - if part_size > region.size: - raise ToolException("Contents of region %s does not fit" - % region.name) merged.merge(part) - pad_size = region.size - part_size - if pad_size > 0 and region != region_list[-1]: - notify.info(" Padding region %s with 0x%x bytes" % - (region.name, pad_size)) - if format is ".hex": - """The offset will be in the hex file generated when we're done, - so we can skip padding here""" - else: - merged.puts(merged.maxaddr() + 1, padding * pad_size) + + # Hex file can have gaps, so no padding needed. While other formats may + # need padding. Iterate through segments and pad the gaps. + if format != ".hex": + # begin patching from the end of the first segment + _, begin = merged.segments()[0] + for start, stop in merged.segments()[1:]: + pad_size = start - begin + merged.puts(begin, padding * pad_size) + begin = stop + 1 if not exists(dirname(destination)): makedirs(dirname(destination)) diff --git a/tools/config/__init__.py b/tools/config/__init__.py index 3bb8f8b996..36606ead92 100644 --- a/tools/config/__init__.py +++ b/tools/config/__init__.py @@ -778,7 +778,7 @@ class Config(object): newstart = rom_start + integer(new_offset, 0) if newstart < start: raise ConfigException( - "Can not place % region inside previous region" % region_name) + "Can not place %r region inside previous region" % region_name) return newstart def _generate_bootloader_build(self, rom_memories): @@ -797,8 +797,19 @@ class Config(object): if part.minaddr() != rom_start: raise ConfigException("bootloader executable does not " "start at 0x%x" % rom_start) - part_size = (part.maxaddr() - part.minaddr()) + 1 - part_size = Config._align_ceiling(rom_start + part_size, self.sectors) - rom_start + + # find the last valid address that's within rom_end and use that + # to compute the bootloader size + end_address = None + for start, stop in part.segments(): + if (stop < rom_end): + end_address = stop + else: + break + if end_address == None: + raise ConfigException("bootloader segments don't fit within rom region") + part_size = Config._align_ceiling(end_address, self.sectors) - rom_start + yield Region("bootloader", rom_start, part_size, False, filename) start = rom_start + part_size @@ -809,9 +820,14 @@ class Config(object): start, region = self._make_header_region( start, self.target.header_format) yield region._replace(filename=self.target.header_format) + if self.target.restrict_size is not None: new_size = int(self.target.restrict_size, 0) new_size = Config._align_floor(start + new_size, self.sectors) - start + + if self.target.app_offset: + start = self._assign_new_offset(rom_start, start, self.target.app_offset, "application") + yield Region("application", start, new_size, True, None) start += new_size if self.target.header_format and not self.target.bootloader_img: @@ -821,9 +837,7 @@ class Config(object): start, region = self._make_header_region( start, self.target.header_format) yield region - if self.target.app_offset: - start = self._assign_new_offset( - rom_start, start, self.target.app_offset, "application") + yield Region("post_application", start, rom_end - start, False, None) else: @@ -832,7 +846,7 @@ class Config(object): rom_start, start, self.target.app_offset, "application") yield Region("application", start, rom_end - start, True, None) - if start > rom_start + rom_size: + if start > rom_end: raise ConfigException("Not enough memory on device to fit all " "application regions") diff --git a/tools/export/__init__.py b/tools/export/__init__.py index 70f0a33b8e..1b2f2207e7 100644 --- a/tools/export/__init__.py +++ b/tools/export/__init__.py @@ -69,7 +69,7 @@ To export this project please RESET_PROC -> SLEEP(RESET_TOUT) # When the build and test system were separate, this was relative to a - # base network folder base path: join(NETWORK_BASE_PATH, ) - image_path = image + # base network folder base path: join(NETWORK_BASE_PATH, ). + # "image" is now a list representing a development image and an update image + # (for device management). When testing, we only use the development image. + image_path = image[0] # Host test execution start_host_exec_time = time() single_test_result = self.TEST_RESULT_UNDEF # single test run result _copy_method = selected_copy_method - if not exists(image_path): single_test_result = self.TEST_RESULT_NO_IMAGE elapsed_time = 0 @@ -2381,4 +2382,4 @@ def build_tests(tests, base_source_paths, build_path, target, toolchain_name, def test_spec_from_test_builds(test_builds): return { "builds": test_builds - } \ No newline at end of file + } diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index 31c2a8e77d..106fba98f7 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -19,7 +19,7 @@ from __future__ import print_function, division, absolute_import import re import sys import json -from os import stat, walk, getcwd, sep, remove, getenv +from os import stat, walk, getcwd, sep, remove, getenv, rename, remove from copy import copy from time import time, sleep from shutil import copyfile @@ -41,6 +41,7 @@ from ..notifier.term import TerminalNotifier from ..resources import FileType from ..memap import MemapParser from ..config import (ConfigException, RAM_ALL_MEMORIES, ROM_ALL_MEMORIES) +from ..settings import COMPARE_FIXED #Disables multiprocessing if set to higher number than the host machine CPUs @@ -77,6 +78,8 @@ class mbedToolchain: "Cortex-M33": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M33F-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1", "__FPU_PRESENT=1U", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M33F": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT=1U", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33FD-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1", "__FPU_PRESENT=1U", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33FD": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT=1U", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], } MBED_CONFIG_FILE_NAME="mbed_config.h" @@ -617,7 +620,7 @@ class mbedToolchain: full_path = join(tmp_path, filename) elf = join(tmp_path, name + '.elf') bin = None if ext == 'elf' else full_path - map = join(tmp_path, name + '.map') + mapfile = join(tmp_path, name + '.map') objects = sorted(set(r.get_file_paths(FileType.OBJECT))) config_file = ([self.config.app_config_location] @@ -634,6 +637,11 @@ class mbedToolchain: dependencies = objects + libraries + [linker_script] + config_file + hex_files dependencies.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-ld")) if self.need_update(elf, dependencies): + if not COMPARE_FIXED and exists(mapfile): + old_mapfile = "%s.old" % mapfile + if exists(old_mapfile): + remove(old_mapfile) + rename(mapfile, old_mapfile) needed_update = True self.progress("link", name) self.link(elf, objects, libraries, lib_dirs, linker_script) @@ -644,7 +652,7 @@ class mbedToolchain: self.binary(r, elf, bin) # Initialize memap and process map file. This doesn't generate output. - self.mem_stats(map) + self.mem_stats(mapfile) self.notify.var("compile_succeded", True) self.notify.var("binary", filename) @@ -711,7 +719,7 @@ class mbedToolchain: ld_string = self.make_ld_define(*ld_string) self.ld.append(ld_string) self.flags["ld"].append(ld_string) - + def _add_all_regions(self, region_list, active_region_name): for region in region_list: self._add_defines_from_region(region) @@ -738,8 +746,8 @@ class mbedToolchain: )) self._add_all_regions(regions, "MBED_APP") except ConfigException: - pass - + pass + if self.config.has_ram_regions: try: regions = list(self.config.ram_regions) @@ -749,7 +757,7 @@ class mbedToolchain: )) self._add_all_regions(regions, "MBED_RAM") except ConfigException: - pass + pass Region = namedtuple("Region", "name start size") diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 2d16e7c349..d02c184226 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -166,7 +166,7 @@ class ARM(mbedToolchain): msg = None else: msg['text'] += line+"\n" - + if msg is not None: self.notify.cc_info(msg) @@ -304,7 +304,7 @@ class ARM(mbedToolchain): @hook_tool def binary(self, resources, elf, bin): _, fmt = splitext(bin) - # On .hex format, combine multiple .hex files (for multiple load regions) into one + # On .hex format, combine multiple .hex files (for multiple load regions) into one bin_arg = {".bin": "--bin", ".hex": "--i32combined"}[fmt] cmd = [self.elf2bin, bin_arg, '-o', bin, elf] cmd = self.hook.get_cmdline_binary(cmd) @@ -364,7 +364,8 @@ class ARMC6(ARM_STD): SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD", "Cortex-M23", "Cortex-M23-NS", "Cortex-M33", "Cortex-M33F", - "Cortex-M33-NS", "Cortex-M33F-NS", "Cortex-A9"] + "Cortex-M33-NS", "Cortex-M33F-NS", "Cortex-M33FD-NS", "Cortex-M33FD", + "Cortex-A9"] ARMCC_RANGE = (LooseVersion("6.10"), LooseVersion("7.0")) @staticmethod @@ -392,6 +393,10 @@ class ARMC6(ARM_STD): self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-2]) self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-2]) self.SHEBANG += " -mcpu=%s" % target.core.lower()[:-2] + elif target.core.lower().endswith("fd-ns"): + self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-5]) + self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-5]) + self.SHEBANG += " -mcpu=%s" % target.core.lower()[:-5] elif target.core.lower().endswith("f"): self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-1]) self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-1]) @@ -420,18 +425,25 @@ class ARMC6(ARM_STD): self.flags['common'].append("-mfpu=fpv5-sp-d16") self.flags['common'].append("-mfloat-abi=softfp") - if target.core == "Cortex-M23" or target.core == "Cortex-M33": + if ((target.core.startswith("Cortex-M23") or + target.core.startswith("Cortex-M33")) and + not target.core.endswith("-NS")): self.flags['cxx'].append("-mcmse") self.flags['c'].append("-mcmse") # Create Secure library - if ((target.core == "Cortex-M23" or self.target.core == "Cortex-M33") and + if ((target.core.startswith("Cortex-M23") or + target.core.startswith("Cortex-M33")) and + not target.core.endswith("-NS") and kwargs.get('build_dir', False)): build_dir = kwargs['build_dir'] secure_file = join(build_dir, "cmse_lib.o") self.flags["ld"] += ["--import_cmse_lib_out=%s" % secure_file] + # Add linking time preprocessor macro DOMAIN_NS - if target.core == "Cortex-M23-NS" or self.target.core == "Cortex-M33-NS": + if ((target.core.startswith("Cortex-M23") or + target.core.startswith("Cortex-M33")) and + target.core.endswith("-NS")): define_string = self.make_ld_define("DOMAIN_NS", "0x1") self.flags["ld"].append(define_string) diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index 1a48bb0408..af3c5ca6aa 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -60,6 +60,8 @@ class GCC(mbedToolchain): self.cpu = ["-mcpu=cortex-m7"] elif target.core.startswith("Cortex-M23"): self.cpu = ["-mcpu=cortex-m23"] + elif target.core.startswith("Cortex-M33FD"): + self.cpu = ["-mcpu=cortex-m33"] elif target.core.startswith("Cortex-M33F"): self.cpu = ["-mcpu=cortex-m33+nodsp"] elif target.core.startswith("Cortex-M33"): @@ -80,6 +82,9 @@ class GCC(mbedToolchain): elif target.core == "Cortex-M7FD": self.cpu.append("-mfpu=fpv5-d16") self.cpu.append("-mfloat-abi=softfp") + elif target.core.startswith("Cortex-M33F"): + self.cpu.append("-mfpu=fpv5-sp-d16") + self.cpu.append("-mfloat-abi=softfp") if target.core == "Cortex-A9": self.cpu.append("-mthumb-interwork") @@ -97,8 +102,12 @@ class GCC(mbedToolchain): "-Wl,--cmse-implib", "-Wl,--out-implib=%s" % join(build_dir, "cmse_lib.o") ]) - elif target.core == "Cortex-M23-NS" or target.core == "Cortex-M33-NS" or target.core == "Cortex-M33F-NS": - self.flags["ld"].append("-DDOMAIN_NS=1") + + # Add linking time preprocessor macro DOMAIN_NS + if ((target.core.startswith("Cortex-M23") or + target.core.startswith("Cortex-M33")) and + target.core.endswith("-NS")): + self.flags["ld"].append("-DDOMAIN_NS=1") self.flags["common"] += self.cpu