PSOC6: use prebuilt CM0+ C arrays instead of HEX images

Replace the prebuilt CM0+ HEX images with C files that provide the
variable cy_m0p_image placed to the combined ELF image with linker
script. This simplifies build flow of PSoC 6 application and improves
compatibility with IDE export targets. It is still possible to use
the custom prebuilt HEX images for PSA targets that remove CM0P_SLEEP
label and specify the `hex_filename` in targets.json.
Linker scripts are compatible with both scenarios.
pull/10692/head
Volodymyr Medvid 2019-05-27 16:05:24 +03:00 committed by Volodymyr Medvid
parent 9d983478d7
commit c9105eb068
31 changed files with 279 additions and 888 deletions

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@ -43,7 +43,7 @@
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
@ -55,7 +55,7 @@
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001FE000 #define MBED_ROM_SIZE 0x00200000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
@ -133,8 +133,26 @@
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x2000
#define FLASH_CM0P_START FLASH_START
LR_IROM1 FLASH_START FLASH_SIZE ; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE)
#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE)
; Cortex-M0+ application image
LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {

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@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001FE000 #define MBED_ROM_SIZE 0x00200000
#endif #endif
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -118,6 +118,13 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
} }
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x2000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* Library configurations */ /* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a) GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -157,7 +164,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS SECTIONS
{ {
.text : /* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Cortex-M4 application image */
.text FLASH_CM4_START :
{ {
. = ALIGN(4); . = ALIGN(4);
__Vectors = . ; __Vectors = . ;

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@ -42,7 +42,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) { if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10002000; define symbol MBED_ROM_START = 0x10000000;
} }
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
} }
if (!isdefinedsymbol(MBED_ROM_SIZE)) { if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x001FE000; define symbol MBED_ROM_SIZE = 0x00200000;
} }
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -161,6 +161,9 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@ -182,6 +185,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
/*-Initializations-*/ /*-Initializations-*/
@ -190,8 +194,11 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
@ -228,7 +235,8 @@ place at end of IRAM1_region { block CSTACK };
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature, keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,

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@ -1,51 +0,0 @@
Copyright (c) 2018-2019 Cypress Semiconductor Corporation
Permissive Binary License
Version 1.0, September 2015
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named "DEPENDENCIES" and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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@ -1,18 +0,0 @@
README for pre-compiled PSoC 6 Cortex M0+ core images
=====================================================
This folder contains precompiled program images for the CM0+ core of the
PSoC 6 MCU suitable for use with Mbed OS applications running on CM4 core.
* `psoc6_02_cm0p_sleep.hex`
This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10080000
and puts CM0+ core into a deep sleep.
The images are 'bare metal' code prepared with Cypress ModusToolbox IDE
and are toolchain agnostic, i.e. can be used with CM4 Mbed applications
build with any supported toolchain.
**These images were prepared by Cypress Semiconductor Corporation
and are made available under the conditions of Permissive Binary Licence,
see file LICENSE.txt**

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@ -1,82 +0,0 @@
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:00000001FF

View File

@ -43,7 +43,7 @@
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
@ -55,7 +55,7 @@
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000FE000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
@ -133,8 +133,26 @@
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x2000
#define FLASH_CM0P_START FLASH_START
LR_IROM1 FLASH_START FLASH_SIZE ; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE)
#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE)
; Cortex-M0+ application image
LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {

View File

@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000FE000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -118,6 +118,13 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
} }
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x2000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* Library configurations */ /* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a) GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -157,7 +164,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS SECTIONS
{ {
.text : /* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Cortex-M4 application image */
.text FLASH_CM4_START :
{ {
. = ALIGN(4); . = ALIGN(4);
__Vectors = . ; __Vectors = . ;

View File

@ -42,7 +42,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) { if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10002000; define symbol MBED_ROM_START = 0x10000000;
} }
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
} }
if (!isdefinedsymbol(MBED_ROM_SIZE)) { if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x000FE000; define symbol MBED_ROM_SIZE = 0x00100000;
} }
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -161,6 +161,9 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@ -182,6 +185,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
/*-Initializations-*/ /*-Initializations-*/
@ -190,8 +194,11 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
@ -228,7 +235,8 @@ place at end of IRAM1_region { block CSTACK };
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature, keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,

View File

@ -1,51 +0,0 @@
Copyright (c) 2018-2019 Cypress Semiconductor Corporation
Permissive Binary License
Version 1.0, September 2015
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named "DEPENDENCIES" and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

View File

@ -1,18 +0,0 @@
README for pre-compiled PSoC 6 Cortex M0+ core images
=====================================================
This folder contains precompiled program images for the CM0+ core of the
PSoC 6 MCU suitable for use with Mbed OS applications running on CM4 core.
* `psoc6_01_cm0p_sleep.hex`
This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10080000
and puts CM0+ core into a deep sleep.
The images are 'bare metal' code prepared with Cypress ModusToolbox IDE
and are toolchain agnostic, i.e. can be used with CM4 Mbed applications
build with any supported toolchain.
**These images were prepared by Cypress Semiconductor Corporation
and are made available under the conditions of Permissive Binary Licence,
see file LICENSE.txt**

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@ -1,106 +0,0 @@
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:00000001FF

View File

@ -43,7 +43,7 @@
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
@ -55,7 +55,7 @@
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000FE000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
@ -133,8 +133,26 @@
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x2000
#define FLASH_CM0P_START FLASH_START
LR_IROM1 FLASH_START FLASH_SIZE ; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE)
#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE)
; Cortex-M0+ application image
LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {

View File

@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000FE000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -118,6 +118,13 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
} }
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x2000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* Library configurations */ /* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a) GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -157,7 +164,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS SECTIONS
{ {
.text : /* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Cortex-M4 application image */
.text FLASH_CM4_START :
{ {
. = ALIGN(4); . = ALIGN(4);
__Vectors = . ; __Vectors = . ;

View File

@ -42,7 +42,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) { if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10002000; define symbol MBED_ROM_START = 0x10000000;
} }
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
} }
if (!isdefinedsymbol(MBED_ROM_SIZE)) { if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x000FE000; define symbol MBED_ROM_SIZE = 0x00100000;
} }
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -161,6 +161,9 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@ -182,6 +185,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
/*-Initializations-*/ /*-Initializations-*/
@ -190,8 +194,11 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
@ -228,7 +235,8 @@ place at end of IRAM1_region { block CSTACK };
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature, keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,

View File

@ -1,51 +0,0 @@
Copyright (c) 2018-2019 Cypress Semiconductor Corporation
Permissive Binary License
Version 1.0, September 2015
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named "DEPENDENCIES" and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

View File

@ -1,18 +0,0 @@
README for pre-compiled PSoC 6 Cortex M0+ core images
=====================================================
This folder contains precompiled program images for the CM0+ core of the
PSoC 6 MCU suitable for use with Mbed OS applications running on CM4 core.
* `psoc6_01_cm0p_sleep.hex`
This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10080000
and puts CM0+ core into a deep sleep.
The images are 'bare metal' code prepared with Cypress ModusToolbox IDE
and are toolchain agnostic, i.e. can be used with CM4 Mbed applications
build with any supported toolchain.
**These images were prepared by Cypress Semiconductor Corporation
and are made available under the conditions of Permissive Binary Licence,
see file LICENSE.txt**

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@ -1,106 +0,0 @@
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:00000001FF

View File

@ -43,7 +43,7 @@
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
@ -55,7 +55,7 @@
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001FE000 #define MBED_ROM_SIZE 0x00200000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
@ -133,8 +133,26 @@
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x2000
#define FLASH_CM0P_START FLASH_START
LR_IROM1 FLASH_START FLASH_SIZE ; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE)
#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE)
; Cortex-M0+ application image
LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {

View File

@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001FE000 #define MBED_ROM_SIZE 0x00200000
#endif #endif
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -118,6 +118,13 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
} }
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x2000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* Library configurations */ /* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a) GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -157,7 +164,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS SECTIONS
{ {
.text : /* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Cortex-M4 application image */
.text FLASH_CM4_START :
{ {
. = ALIGN(4); . = ALIGN(4);
__Vectors = . ; __Vectors = . ;

View File

@ -42,7 +42,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) { if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10002000; define symbol MBED_ROM_START = 0x10000000;
} }
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
} }
if (!isdefinedsymbol(MBED_ROM_SIZE)) { if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x001FE000; define symbol MBED_ROM_SIZE = 0x00200000;
} }
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -161,6 +161,9 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@ -182,6 +185,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
/*-Initializations-*/ /*-Initializations-*/
@ -190,8 +194,11 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
@ -228,7 +235,8 @@ place at end of IRAM1_region { block CSTACK };
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature, keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,

View File

@ -1,51 +0,0 @@
Copyright (c) 2018-2019 Cypress Semiconductor Corporation
Permissive Binary License
Version 1.0, September 2015
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named "DEPENDENCIES" and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

View File

@ -1,18 +0,0 @@
README for pre-compiled PSoC 6 Cortex M0+ core images
=====================================================
This folder contains precompiled program images for the CM0+ core of the
PSoC 6 MCU suitable for use with Mbed OS applications running on CM4 core.
* `psoc6_02_cm0p_sleep.hex`
This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10080000
and puts CM0+ core into a deep sleep.
The images are 'bare metal' code prepared with Cypress ModusToolbox IDE
and are toolchain agnostic, i.e. can be used with CM4 Mbed applications
build with any supported toolchain.
**These images were prepared by Cypress Semiconductor Corporation
and are made available under the conditions of Permissive Binary Licence,
see file LICENSE.txt**

View File

@ -1,82 +0,0 @@
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:00000001FF

View File

@ -43,7 +43,7 @@
;******************************************************************************/ ;******************************************************************************/
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
;* MBED_APP_START is being used by the bootloader build script and ;* MBED_APP_START is being used by the bootloader build script and
@ -55,7 +55,7 @@
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000FE000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
;* MBED_APP_SIZE is being used by the bootloader build script and ;* MBED_APP_SIZE is being used by the bootloader build script and
@ -133,8 +133,26 @@
#define EFUSE_START 0x90700000 #define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000 #define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x2000
#define FLASH_CM0P_START FLASH_START
LR_IROM1 FLASH_START FLASH_SIZE ; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE)
#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE)
; Cortex-M0+ application image
LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
* (.cy_m0p_image)
}
}
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
{ {
ER_FLASH_VECTORS +0 ER_FLASH_VECTORS +0
{ {

View File

@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START) #if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10002000 #define MBED_ROM_START 0x10000000
#endif #endif
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
#endif #endif
#if !defined(MBED_ROM_SIZE) #if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x000FE000 #define MBED_ROM_SIZE 0x00100000
#endif #endif
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -118,6 +118,13 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
} }
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x2000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* Library configurations */ /* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a) GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -157,7 +164,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS SECTIONS
{ {
.text : /* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Cortex-M4 application image */
.text FLASH_CM4_START :
{ {
. = ALIGN(4); . = ALIGN(4);
__Vectors = . ; __Vectors = . ;

View File

@ -42,7 +42,7 @@
define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) { if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10002000; define symbol MBED_ROM_START = 0x10000000;
} }
/* MBED_APP_START is being used by the bootloader build script and /* MBED_APP_START is being used by the bootloader build script and
@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
} }
if (!isdefinedsymbol(MBED_ROM_SIZE)) { if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x000FE000; define symbol MBED_ROM_SIZE = 0x00100000;
} }
/* MBED_APP_SIZE is being used by the bootloader build script and /* MBED_APP_SIZE is being used by the bootloader build script and
@ -161,6 +161,9 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
} }
/**** End of ICF editor section. ###ICF###*/ /**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G; define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@ -182,6 +185,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image };
define block RO {first section .intvec, readonly}; define block RO {first section .intvec, readonly};
/*-Initializations-*/ /*-Initializations-*/
@ -190,8 +194,11 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/ /*-Placement-*/
/* Flash */ /* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block RO }; place at start of IROM1_region { block CM0P_RO };
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */ /* Emulated EEPROM Flash area */
@ -228,7 +235,8 @@ place at end of IRAM1_region { block CSTACK };
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature, keep { section .cy_m0p_image,
section .cy_app_signature,
section .cy_em_eeprom, section .cy_em_eeprom,
section .cy_sflash_user_data, section .cy_sflash_user_data,
section .cy_sflash_nar, section .cy_sflash_nar,

View File

@ -1,51 +0,0 @@
Copyright (c) 2018-2019 Cypress Semiconductor Corporation
Permissive Binary License
Version 1.0, September 2015
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named "DEPENDENCIES" and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

View File

@ -1,18 +0,0 @@
README for pre-compiled PSoC 6 Cortex M0+ core images
=====================================================
This folder contains precompiled program images for the CM0+ core of the
PSoC 6 MCU suitable for use with Mbed OS applications running on CM4 core.
* `psoc6_01_cm0p_sleep.hex`
This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10080000
and puts CM0+ core into a deep sleep.
The images are 'bare metal' code prepared with Cypress ModusToolbox IDE
and are toolchain agnostic, i.e. can be used with CM4 Mbed applications
build with any supported toolchain.
**These images were prepared by Cypress Semiconductor Corporation
and are made available under the conditions of Permissive Binary Licence,
see file LICENSE.txt**

View File

@ -1,106 +0,0 @@
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View File

@ -8382,6 +8382,7 @@
"supported_form_factors": ["ARDUINO"], "supported_form_factors": ["ARDUINO"],
"extra_labels_add": [ "extra_labels_add": [
"PSOC6_01", "PSOC6_01",
"CM0P_SLEEP",
"WICED", "WICED",
"CYW43XXX", "CYW43XXX",
"CYW4343X", "CYW4343X",
@ -8389,7 +8390,6 @@
], ],
"macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"], "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
"detect_code": ["1900"], "detect_code": ["1900"],
"hex_filename": "psoc6_01_cm0p_sleep.hex",
"post_binary_hook": { "post_binary_hook": {
"function": "PSOC6Code.complete" "function": "PSOC6Code.complete"
}, },
@ -8427,6 +8427,7 @@
"CY8CKIT_062_WIFI_BT_PSA": { "CY8CKIT_062_WIFI_BT_PSA": {
"inherits": ["NSPE_Target", "CY8CKIT_062_WIFI_BT"], "inherits": ["NSPE_Target", "CY8CKIT_062_WIFI_BT"],
"extra_labels_add": ["PSA", "MBED_SPM"], "extra_labels_add": ["PSA", "MBED_SPM"],
"extra_labels_remove": ["CM0P_SLEEP"],
"components_add": ["SPM_MAILBOX", "FLASHIAP"], "components_add": ["SPM_MAILBOX", "FLASHIAP"],
"device_has_remove": ["CRC"], "device_has_remove": ["CRC"],
"hex_filename": "psa_release_1.0.hex", "hex_filename": "psa_release_1.0.hex",
@ -8453,6 +8454,7 @@
"device_has_remove": ["ANALOGOUT"], "device_has_remove": ["ANALOGOUT"],
"extra_labels_add": [ "extra_labels_add": [
"PSOC6_02", "PSOC6_02",
"CM0P_SLEEP",
"WICED", "WICED",
"CYW43XXX", "CYW43XXX",
"CYW4343X", "CYW4343X",
@ -8468,7 +8470,6 @@
"inherits": ["CY8CMOD_062_4343W"], "inherits": ["CY8CMOD_062_4343W"],
"components_add": ["QSPIF"], "components_add": ["QSPIF"],
"detect_code": ["1901"], "detect_code": ["1901"],
"hex_filename": "psoc6_02_cm0p_sleep.hex",
"post_binary_hook": { "post_binary_hook": {
"function": "PSOC6Code.complete" "function": "PSOC6Code.complete"
} }
@ -8477,10 +8478,12 @@
"inherits": ["MCU_PSOC6_M4"], "inherits": ["MCU_PSOC6_M4"],
"components_add": ["QSPIF"], "components_add": ["QSPIF"],
"supported_form_factors": ["ARDUINO"], "supported_form_factors": ["ARDUINO"],
"extra_labels_add": ["PSOC6_01"], "extra_labels_add": [
"PSOC6_01",
"CM0P_SLEEP"
],
"macros_add": ["CY8C6347BZI_BLD53", "PSOC6_DYNSRM_DISABLE=1"], "macros_add": ["CY8C6347BZI_BLD53", "PSOC6_DYNSRM_DISABLE=1"],
"detect_code": ["1902"], "detect_code": ["1902"],
"hex_filename": "psoc6_01_cm0p_sleep.hex",
"post_binary_hook": { "post_binary_hook": {
"function": "PSOC6Code.complete" "function": "PSOC6Code.complete"
}, },
@ -8494,6 +8497,7 @@
"device_has_remove": ["ANALOGOUT"], "device_has_remove": ["ANALOGOUT"],
"extra_labels_add": [ "extra_labels_add": [
"PSOC6_02", "PSOC6_02",
"CM0P_SLEEP",
"WICED", "WICED",
"CYW43XXX", "CYW43XXX",
"CYW4343X", "CYW4343X",
@ -8501,7 +8505,6 @@
], ],
"macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"], "macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"],
"detect_code": ["1905"], "detect_code": ["1905"],
"hex_filename": "psoc6_02_cm0p_sleep.hex",
"post_binary_hook": { "post_binary_hook": {
"function": "PSOC6Code.complete" "function": "PSOC6Code.complete"
}, },
@ -8522,6 +8525,7 @@
"features": ["BLE"], "features": ["BLE"],
"extra_labels_add": [ "extra_labels_add": [
"PSOC6_01", "PSOC6_01",
"CM0P_SLEEP",
"WICED", "WICED",
"CYW43XXX", "CYW43XXX",
"CYW43012", "CYW43012",
@ -8529,7 +8533,6 @@
], ],
"macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"], "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
"detect_code": ["1906"], "detect_code": ["1906"],
"hex_filename": "psoc6_01_cm0p_sleep.hex",
"post_binary_hook": { "post_binary_hook": {
"function": "PSOC6Code.complete" "function": "PSOC6Code.complete"
}, },