From c8e8912d0eca97f8e79b34938f7d64f301a94bfd Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Thu, 13 Dec 2018 16:05:04 +0200 Subject: [PATCH] CM3: Make ACTLR bit definitions conditional The ACTLR register itself is conditional on chip revision, but its bit definitions were always defined. Make the the bit definitions also conditional, so it is possible to produce portable code that sets DISDEFWBUF if available: #ifdef SCnSCB_ACTLR_DISDEFWBUF_Msk SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk; #endif (cherry-picked from CMSIS b2b04dbeece0a046556bfc320bef6b20bef3f16f) --- cmsis/TARGET_CORTEX_M/core_cm3.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cmsis/TARGET_CORTEX_M/core_cm3.h b/cmsis/TARGET_CORTEX_M/core_cm3.h index 74bff64be4..e84a9f5b7d 100644 --- a/cmsis/TARGET_CORTEX_M/core_cm3.h +++ b/cmsis/TARGET_CORTEX_M/core_cm3.h @@ -668,7 +668,7 @@ typedef struct #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ - +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ @@ -677,6 +677,7 @@ typedef struct #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif /*@} end of group CMSIS_SCnotSCB */