mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #15075 from jeromecoutant/PR_G0_CUBE
STM32G0 update drivers version to CUBE V1.5.0pull/15074/head
Martin Kojtal
GitHub
commit
c8b489ea9b
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@ -109,7 +109,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
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| F3 | 1.11.2 | https://github.com/STMicroelectronics/STM32CubeF3 |
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| F4 | 1.26.1 | https://github.com/STMicroelectronics/STM32CubeF4 |
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| F7 | 1.16.1 | https://github.com/STMicroelectronics/STM32CubeF7 |
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| G0 | 1.4.1 | https://github.com/STMicroelectronics/STM32CubeG0 |
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| G0 | 1.5.0 | https://github.com/STMicroelectronics/STM32CubeG0 |
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| G4 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeG4 |
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| H7 | 1.9.0 | https://github.com/STMicroelectronics/STM32CubeH7 |
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| L0 | 1.12.0 | https://github.com/STMicroelectronics/STM32CubeL0 |
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@ -181,8 +181,8 @@ But also each STM32 Part Number with different FLASH size : STM32F401xC / STM32F
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Mbed OS porting layer specific for this family are placed here.
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Example in TARGET_STM32G0:
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- TARGET_STM32G031xx
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- TARGET_STM32G071xx
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- TARGET_STM32G031x8
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- TARGET_STM32G071xB
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- ...
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Each STM32 sub-family contains:
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@ -578,6 +578,7 @@ the CAN interface.
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While using RxInterrupt with the CAN object the receive ISR callback registered should defer read to thread context.
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A simple example is as shown below:
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```
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#include "mbed.h"
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Ticker ticker;
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@ -621,6 +622,7 @@ int main() {
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while(1) {
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}
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}
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```
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## Mbed OS Wiki pages
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@ -1,16 +1,29 @@
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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(TARGET_STM32G030xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G031xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G041xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G070xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G071xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G081xx EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G030x8 EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G031x8 EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G041x8 EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G050x8 EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G051x8 EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G061x8 EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G070xB EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G071xB EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G081xB EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G0B0xE EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G0B1xE EXCLUDE_FROM_ALL)
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add_subdirectory(TARGET_STM32G0C1xE EXCLUDE_FROM_ALL)
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add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL)
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add_library(mbed-stm32g0 INTERFACE)
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target_include_directories(mbed-stm32g0
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INTERFACE
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.
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)
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target_sources(mbed-stm32g0
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INTERFACE
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analogin_device.c
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@ -23,9 +36,4 @@ target_sources(mbed-stm32g0
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spi_api.c
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)
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target_include_directories(mbed-stm32g0
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INTERFACE
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.
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)
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target_link_libraries(mbed-stm32g0 INTERFACE mbed-stm mbed-stm32g0cube-fw)
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@ -22,42 +22,87 @@ extern "C" {
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#endif
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typedef enum {
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ADC_1 = (int)ADC1_BASE
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ADC_1 = (int)ADC1_BASE,
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} ADCName;
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#if defined DAC_BASE
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typedef enum {
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DAC_1 = (int)DAC_BASE
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DAC_1 = (int)DAC_BASE,
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} DACName;
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#endif
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typedef enum {
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UART_1 = (int)USART1_BASE,
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UART_2 = (int)USART2_BASE,
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#if defined USART3_BASE
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UART_3 = (int)USART3_BASE,
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#endif
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#if defined USART4_BASE
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UART_4 = (int)USART4_BASE,
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LPUART_1 = (int)LPUART1_BASE
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#endif
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#if defined USART5_BASE
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UART_5 = (int)USART5_BASE,
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#endif
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#if defined USART6_BASE
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UART_6 = (int)USART6_BASE,
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#endif
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#if defined LPUART1_BASE
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LPUART_1 = (int)LPUART1_BASE,
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#endif
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#if defined LPUART2_BASE
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LPUART_2 = (int)LPUART2_BASE,
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#endif
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} UARTName;
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#define DEVICE_SPI_COUNT 2
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typedef enum {
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SPI_1 = (int)SPI1_BASE,
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SPI_2 = (int)SPI2_BASE
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SPI_2 = (int)SPI2_BASE,
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#if defined SPI3_BASE
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SPI_3 = (int)SPI3_BASE,
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#endif
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} SPIName;
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typedef enum {
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I2C_1 = (int)I2C1_BASE,
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I2C_2 = (int)I2C2_BASE
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I2C_2 = (int)I2C2_BASE,
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#if defined I2C3_BASE
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I2C_3 = (int)I2C3_BASE,
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#endif
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} I2CName;
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typedef enum {
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PWM_1 = (int)TIM1_BASE,
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#if defined TIM2_BASE
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PWM_2 = (int)TIM2_BASE,
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#endif
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PWM_3 = (int)TIM3_BASE,
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#if defined TIM4_BASE
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PWM_4 = (int)TIM4_BASE,
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#endif
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PWM_14 = (int)TIM14_BASE,
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#if defined TIM15_BASE
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PWM_15 = (int)TIM15_BASE,
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#endif
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PWM_16 = (int)TIM16_BASE,
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PWM_17 = (int)TIM17_BASE
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PWM_17 = (int)TIM17_BASE,
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} PWMName;
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#if defined FDCAN1_BASE
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typedef enum {
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CAN_1 = (int)FDCAN1_BASE,
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#if defined FDCAN2_BASE
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CAN_2 = (int)FDCAN2_BASE,
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#endif
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} CANName;
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#endif
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#if defined USB_BASE
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typedef enum {
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USB_FS = (int)USB_BASE
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} USBName;
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#endif
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,6 @@
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This software component is provided to you as part of a software package and
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applicable license terms are in the Package_license file. If you received this
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software component outside of a package or without applicable license terms,
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the terms of the Apache-2.0 license shall apply.
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You may obtain a copy of the Apache-2.0 at:
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https://opensource.org/licenses/Apache-2.0
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@ -14,17 +14,15 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2018-2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under Apache License, Version 2.0,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/Apache-2.0
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS_Device
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* @{
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*/
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@ -521,6 +519,7 @@ typedef struct
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#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
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#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U)
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/*!< Peripheral memory map */
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#define APBPERIPH_BASE (PERIPH_BASE)
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#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
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@ -661,6 +660,15 @@ typedef struct
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* @{
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*/
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/** @addtogroup Hardware_Constant_Definition
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* @{
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*/
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#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
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/**
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* @}
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*/
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/** @addtogroup Peripheral_Registers_Bits_Definition
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* @{
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*/
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@ -784,7 +792,7 @@ typedef struct
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#define ADC_CFGR1_ALIGN_Pos (5U)
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#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
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#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
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#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
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#define ADC_CFGR1_EXTSEL_Pos (6U)
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#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
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@ -1591,7 +1599,6 @@ typedef struct
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#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
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#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
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#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
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#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
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#define DMAMUX_CxCR_SOIE_Pos (8U)
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#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
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#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
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@ -2287,92 +2294,92 @@ typedef struct
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/******************* Bits definition for FLASH_CR register ******************/
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#define FLASH_CR_PG_Pos (0U)
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#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
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#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
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#define FLASH_CR_PG FLASH_CR_PG_Msk
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#define FLASH_CR_PER_Pos (1U)
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#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
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#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
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#define FLASH_CR_PER FLASH_CR_PER_Msk
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#define FLASH_CR_MER1_Pos (2U)
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#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
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#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
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#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
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#define FLASH_CR_PNB_Pos (3U)
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#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
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#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
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#define FLASH_CR_PNB FLASH_CR_PNB_Msk
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#define FLASH_CR_STRT_Pos (16U)
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#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
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#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
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#define FLASH_CR_STRT FLASH_CR_STRT_Msk
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#define FLASH_CR_OPTSTRT_Pos (17U)
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#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
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#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
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#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
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#define FLASH_CR_FSTPG_Pos (18U)
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#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
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#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
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#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
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#define FLASH_CR_EOPIE_Pos (24U)
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#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
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#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
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#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
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#define FLASH_CR_ERRIE_Pos (25U)
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#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
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#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
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#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
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#define FLASH_CR_OBL_LAUNCH_Pos (27U)
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#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
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#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
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#define FLASH_CR_OPTLOCK_Pos (30U)
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#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
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#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
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#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
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#define FLASH_CR_LOCK_Pos (31U)
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#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
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#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
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#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
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/******************* Bits definition for FLASH_ECCR register ****************/
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#define FLASH_ECCR_ADDR_ECC_Pos (0U)
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#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
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#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
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#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
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#define FLASH_ECCR_SYSF_ECC_Pos (20U)
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#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
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#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
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#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
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#define FLASH_ECCR_ECCCIE_Pos (24U)
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#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
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#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
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#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
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#define FLASH_ECCR_ECCC_Pos (30U)
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#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
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#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
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#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
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#define FLASH_ECCR_ECCD_Pos (31U)
|
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#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
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#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
|
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#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
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|
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/******************* Bits definition for FLASH_OPTR register ****************/
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#define FLASH_OPTR_RDP_Pos (0U)
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#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
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#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
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#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
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#define FLASH_OPTR_nRST_STOP_Pos (13U)
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#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
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#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
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#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
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#define FLASH_OPTR_nRST_STDBY_Pos (14U)
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#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
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#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
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#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
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#define FLASH_OPTR_IWDG_SW_Pos (16U)
|
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#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
|
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#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
|
||||
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
|
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#define FLASH_OPTR_IWDG_STOP_Pos (17U)
|
||||
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
|
||||
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
|
||||
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
|
||||
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
|
||||
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
|
||||
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
|
||||
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
|
||||
#define FLASH_OPTR_WWDG_SW_Pos (19U)
|
||||
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
|
||||
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
|
||||
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
|
||||
#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
|
||||
#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
|
||||
#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
|
||||
#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
|
||||
#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
|
||||
#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
|
||||
#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
|
||||
#define FLASH_OPTR_nBOOT1_Pos (25U)
|
||||
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
|
||||
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
|
||||
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
|
||||
#define FLASH_OPTR_nBOOT0_Pos (26U)
|
||||
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
|
||||
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
|
||||
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
|
||||
|
||||
/****************** Bits definition for FLASH_WRP1AR register ***************/
|
||||
|
|
@ -3942,7 +3949,6 @@ typedef struct
|
|||
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
|
||||
#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
|
||||
|
||||
|
||||
/*!< HPRE configuration */
|
||||
#define RCC_CFGR_HPRE_Pos (8U)
|
||||
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
|
||||
|
|
@ -5566,9 +5572,9 @@ typedef struct
|
|||
#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
|
||||
#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
|
||||
#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)
|
||||
#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */
|
||||
|
|
@ -6429,7 +6435,7 @@ typedef struct
|
|||
/******************* Bit definition for TIM_TISEL register *********************/
|
||||
#define TIM_TISEL_TI1SEL_Pos (0U)
|
||||
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
|
||||
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL) */
|
||||
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
|
||||
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
|
||||
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
|
||||
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
|
||||
|
|
@ -6437,7 +6443,7 @@ typedef struct
|
|||
|
||||
#define TIM_TISEL_TI2SEL_Pos (8U)
|
||||
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
|
||||
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL) */
|
||||
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
|
||||
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
|
||||
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
|
||||
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
|
||||
|
|
@ -6445,7 +6451,7 @@ typedef struct
|
|||
|
||||
#define TIM_TISEL_TI3SEL_Pos (16U)
|
||||
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
|
||||
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL) */
|
||||
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
|
||||
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
|
||||
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
|
||||
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
|
||||
|
|
@ -6453,7 +6459,7 @@ typedef struct
|
|||
|
||||
#define TIM_TISEL_TI4SEL_Pos (24U)
|
||||
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
|
||||
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL) */
|
||||
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
|
||||
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
|
||||
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
|
||||
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -150,6 +148,8 @@ typedef struct
|
|||
} ADC_Common_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRC calculation unit
|
||||
*/
|
||||
|
|
@ -552,6 +552,7 @@ typedef struct
|
|||
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
|
||||
|
||||
#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U)
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
#define APBPERIPH_BASE (PERIPH_BASE)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
|
||||
|
|
@ -702,6 +703,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -825,7 +835,7 @@ typedef struct
|
|||
|
||||
#define ADC_CFGR1_ALIGN_Pos (5U)
|
||||
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
|
||||
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
|
||||
#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
|
||||
|
||||
#define ADC_CFGR1_EXTSEL_Pos (6U)
|
||||
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
|
||||
|
|
@ -1632,7 +1642,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
@ -2422,88 +2431,88 @@ typedef struct
|
|||
#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
|
||||
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
|
||||
#define FLASH_ECCR_SYSF_ECC_Pos (20U)
|
||||
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
|
||||
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
|
||||
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
|
||||
#define FLASH_ECCR_ECCCIE_Pos (24U)
|
||||
#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
|
||||
#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
|
||||
#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
|
||||
#define FLASH_ECCR_ECCC_Pos (30U)
|
||||
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
|
||||
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
|
||||
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
|
||||
#define FLASH_ECCR_ECCD_Pos (31U)
|
||||
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
|
||||
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
|
||||
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
|
||||
|
||||
/******************* Bits definition for FLASH_OPTR register ****************/
|
||||
#define FLASH_OPTR_RDP_Pos (0U)
|
||||
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
|
||||
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
|
||||
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
|
||||
#define FLASH_OPTR_BOR_EN_Pos (8U)
|
||||
#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */
|
||||
#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */
|
||||
#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk
|
||||
#define FLASH_OPTR_BORR_LEV_Pos (9U)
|
||||
#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */
|
||||
#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */
|
||||
#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk
|
||||
#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */
|
||||
#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */
|
||||
#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */
|
||||
#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */
|
||||
#define FLASH_OPTR_BORF_LEV_Pos (11U)
|
||||
#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */
|
||||
#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */
|
||||
#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk
|
||||
#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */
|
||||
#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */
|
||||
#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */
|
||||
#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */
|
||||
#define FLASH_OPTR_nRST_STOP_Pos (13U)
|
||||
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
|
||||
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
|
||||
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
|
||||
#define FLASH_OPTR_nRST_STDBY_Pos (14U)
|
||||
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
|
||||
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
|
||||
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
|
||||
#define FLASH_OPTR_nRST_SHDW_Pos (15U)
|
||||
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */
|
||||
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */
|
||||
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
|
||||
#define FLASH_OPTR_IWDG_SW_Pos (16U)
|
||||
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
|
||||
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
|
||||
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
|
||||
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
|
||||
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
|
||||
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
|
||||
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
|
||||
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
|
||||
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
|
||||
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
|
||||
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
|
||||
#define FLASH_OPTR_WWDG_SW_Pos (19U)
|
||||
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
|
||||
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
|
||||
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
|
||||
#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
|
||||
#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
|
||||
#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
|
||||
#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
|
||||
#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
|
||||
#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
|
||||
#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
|
||||
#define FLASH_OPTR_nBOOT1_Pos (25U)
|
||||
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
|
||||
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
|
||||
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
|
||||
#define FLASH_OPTR_nBOOT0_Pos (26U)
|
||||
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
|
||||
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
|
||||
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
|
||||
#define FLASH_OPTR_NRST_MODE_Pos (27U)
|
||||
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */
|
||||
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */
|
||||
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
|
||||
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */
|
||||
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
|
||||
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */
|
||||
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
|
||||
#define FLASH_OPTR_IRHEN_Pos (29U)
|
||||
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */
|
||||
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */
|
||||
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
|
||||
|
||||
/****************** Bits definition for FLASH_PCROP1ASR register ************/
|
||||
#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U)
|
||||
#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk
|
||||
|
||||
/****************** Bits definition for FLASH_PCROP1AER register ************/
|
||||
#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U)
|
||||
#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk
|
||||
#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U)
|
||||
#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
|
||||
#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
|
||||
#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk
|
||||
|
||||
/****************** Bits definition for FLASH_WRP1AR register ***************/
|
||||
|
|
@ -2524,12 +2533,12 @@ typedef struct
|
|||
|
||||
/****************** Bits definition for FLASH_PCROP1BSR register ************/
|
||||
#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U)
|
||||
#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk
|
||||
|
||||
/****************** Bits definition for FLASH_PCROP1BER register ************/
|
||||
#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U)
|
||||
#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */
|
||||
#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk
|
||||
|
||||
|
||||
|
|
@ -5815,8 +5824,8 @@ typedef struct
|
|||
#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
|
||||
#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
|
||||
#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
|
||||
#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
|
||||
#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)
|
||||
#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
|
||||
|
|
@ -6703,7 +6712,7 @@ typedef struct
|
|||
/******************* Bit definition for TIM_TISEL register *********************/
|
||||
#define TIM_TISEL_TI1SEL_Pos (0U)
|
||||
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
|
||||
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL) */
|
||||
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
|
||||
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
|
||||
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
|
||||
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
|
||||
|
|
@ -6711,7 +6720,7 @@ typedef struct
|
|||
|
||||
#define TIM_TISEL_TI2SEL_Pos (8U)
|
||||
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
|
||||
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL) */
|
||||
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
|
||||
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
|
||||
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
|
||||
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
|
||||
|
|
@ -6719,7 +6728,7 @@ typedef struct
|
|||
|
||||
#define TIM_TISEL_TI3SEL_Pos (16U)
|
||||
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
|
||||
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL) */
|
||||
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
|
||||
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
|
||||
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
|
||||
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
|
||||
|
|
@ -6727,7 +6736,7 @@ typedef struct
|
|||
|
||||
#define TIM_TISEL_TI4SEL_Pos (24U)
|
||||
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
|
||||
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL) */
|
||||
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
|
||||
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
|
||||
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
|
||||
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -596,6 +594,7 @@ typedef struct
|
|||
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
|
||||
|
||||
#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U)
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
#define APBPERIPH_BASE (PERIPH_BASE)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
|
||||
|
|
@ -751,6 +750,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1870,7 +1878,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -681,6 +679,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1611,7 +1618,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -768,6 +766,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1929,7 +1936,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -815,6 +813,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2165,7 +2172,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -684,6 +682,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1614,7 +1621,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -821,6 +819,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2119,7 +2126,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -868,6 +866,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2355,7 +2362,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -770,6 +768,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1700,12 +1707,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_8 (0x100UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_9 (0x200UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000200 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_10 (0x400UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000400 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_11 (0x800UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000800 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_12 (0x1000UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00001000 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -992,6 +990,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2388,12 +2395,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_8 (0x100UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_9 (0x200UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000200 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_10 (0x400UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000400 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_11 (0x800UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000800 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_12 (0x1000UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00001000 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -14,17 +14,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS_Device
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1039,6 +1037,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2624,12 +2631,6 @@ typedef struct
|
|||
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_8 (0x100UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_9 (0x200UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000200 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_10 (0x400UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000400 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_11 (0x800UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000800 */
|
||||
#define DMAMUX_CxCR_DMAREQ_ID_12 (0x1000UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00001000 */
|
||||
#define DMAMUX_CxCR_SOIE_Pos (8U)
|
||||
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
|
||||
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
|
||||
|
|
|
|||
|
|
@ -16,17 +16,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -92,7 +90,7 @@
|
|||
*/
|
||||
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
|
||||
#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G0_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
@ -183,6 +181,46 @@ typedef enum
|
|||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/* Use of interrupt control for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
SET_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
CLEAR_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
|
||||
/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -6,17 +6,15 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/Apache-2.0
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ target_sources(mbed-stm32g0cube-fw
|
|||
STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.c
|
||||
STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.c
|
||||
STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.c
|
||||
STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.c
|
||||
STM32G0xx_HAL_Driver/stm32g0xx_hal_spi.c
|
||||
STM32G0xx_HAL_Driver/stm32g0xx_hal_spi_ex.c
|
||||
STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.c
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
# Copyright (c) 2018 STMicroelectronics
|
||||
|
||||
This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
#define STM32_HAL_LEGACY
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -38,6 +38,14 @@
|
|||
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
|
||||
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
|
||||
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
|
||||
#if defined(STM32U5)
|
||||
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
|
||||
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
|
||||
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
|
||||
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
|
||||
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
|
||||
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -210,6 +218,18 @@
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
|
||||
#else
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -235,7 +255,7 @@
|
|||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||
|
||||
#if defined(STM32G4) || defined(STM32H7)
|
||||
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
|
||||
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
|
||||
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
|
||||
#endif
|
||||
|
|
@ -382,7 +402,6 @@
|
|||
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -470,15 +489,24 @@
|
|||
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
|
||||
#endif
|
||||
#if defined(STM32H7)
|
||||
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#endif /* STM32H7 */
|
||||
#if defined(STM32U5)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -521,6 +549,7 @@
|
|||
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||
#endif /* STM32G4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -595,24 +624,24 @@
|
|||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
|
||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
|
||||
|
||||
#if defined(STM32L1)
|
||||
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#endif /* STM32L1 */
|
||||
|
||||
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
|
||||
#endif /* STM32F0 || STM32F3 || STM32F1 */
|
||||
|
||||
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
|
||||
|
|
@ -773,49 +802,6 @@
|
|||
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
|
||||
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
|
||||
|
||||
/** @brief Constants defining the events that can be selected to configure the
|
||||
* set/reset crossbar of a timer output
|
||||
*/
|
||||
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
|
||||
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
|
||||
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
|
||||
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
|
||||
|
||||
/** @brief Constants defining the event filtering applied to external events
|
||||
* by a timer
|
||||
*/
|
||||
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||
|
||||
/** @brief Constants defining the DLL calibration periods (in micro seconds)
|
||||
*/
|
||||
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
|
||||
|
|
@ -895,7 +881,11 @@
|
|||
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
|
||||
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
|
||||
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -968,6 +958,11 @@
|
|||
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32L5)
|
||||
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
|
||||
#elif defined(STM32G4)
|
||||
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -979,15 +974,15 @@
|
|||
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define I2S_IT_TXE I2S_IT_TXP
|
||||
#define I2S_IT_RXNE I2S_IT_RXP
|
||||
#define I2S_IT_TXE I2S_IT_TXP
|
||||
#define I2S_IT_RXNE I2S_IT_RXP
|
||||
|
||||
#define I2S_FLAG_TXE I2S_FLAG_TXP
|
||||
#define I2S_FLAG_RXNE I2S_FLAG_RXP
|
||||
#define I2S_FLAG_TXE I2S_FLAG_TXP
|
||||
#define I2S_FLAG_RXNE I2S_FLAG_RXP
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
||||
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1022,7 +1017,7 @@
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1122,16 +1117,16 @@
|
|||
|
||||
#if defined(STM32H7)
|
||||
|
||||
#define SPI_FLAG_TXE SPI_FLAG_TXP
|
||||
#define SPI_FLAG_RXNE SPI_FLAG_RXP
|
||||
#define SPI_FLAG_TXE SPI_FLAG_TXP
|
||||
#define SPI_FLAG_RXNE SPI_FLAG_RXP
|
||||
|
||||
#define SPI_IT_TXE SPI_IT_TXP
|
||||
#define SPI_IT_RXNE SPI_IT_RXP
|
||||
#define SPI_IT_TXE SPI_IT_TXP
|
||||
#define SPI_IT_RXNE SPI_IT_RXP
|
||||
|
||||
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
|
||||
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
|
||||
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
|
||||
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
|
||||
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
|
||||
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
|
||||
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
|
||||
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
|
|
@ -1417,6 +1412,20 @@
|
|||
*/
|
||||
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
|
||||
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|
||||
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|
||||
|| defined(STM32H7) || defined(STM32U5)
|
||||
/** @defgroup DMA2D_Aliases DMA2D API Aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
|
||||
for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1435,6 +1444,16 @@
|
|||
* @}
|
||||
*/
|
||||
|
||||
#if !defined(STM32F2)
|
||||
/** @defgroup HASH_alias HASH API alias
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
|
||||
/**
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F2 */
|
||||
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1494,7 +1513,8 @@
|
|||
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
|
||||
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
|
||||
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
|
||||
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
|
||||
#if defined(STM32L0)
|
||||
|
|
@ -1502,7 +1522,8 @@
|
|||
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
|
|
@ -1525,9 +1546,9 @@
|
|||
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
|
||||
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
|
|
@ -1537,7 +1558,8 @@
|
|||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
|
|
@ -1562,9 +1584,9 @@
|
|||
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32F4 */
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||
* @{
|
||||
|
|
@ -1619,9 +1641,9 @@
|
|||
|
||||
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
|
|
@ -1870,15 +1892,15 @@
|
|||
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
||||
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#else
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#endif /* STM32H7 */
|
||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
||||
|
|
@ -2089,8 +2111,8 @@
|
|||
*/
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -2146,7 +2168,7 @@
|
|||
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -2283,7 +2305,8 @@
|
|||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
|
|
@ -3251,7 +3274,7 @@
|
|||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
|
|
@ -3363,7 +3386,20 @@
|
|||
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
|
||||
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
|
||||
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
|
||||
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
|
||||
#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
|
||||
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
|
||||
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
|
||||
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -3380,7 +3416,7 @@
|
|||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
|
|
@ -3400,19 +3436,19 @@
|
|||
#else
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
|
|
@ -3437,13 +3473,17 @@
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
|
||||
/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
|
||||
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
|
||||
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
|
||||
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
|
||||
|
||||
#if defined(STM32F4) || defined(STM32F2)
|
||||
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
|
||||
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
|
||||
|
|
@ -3596,6 +3636,13 @@
|
|||
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
|
||||
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
|
||||
#define USART_OVERSAMPLING_16 0x00000000U
|
||||
#define USART_OVERSAMPLING_8 USART_CR1_OVER8
|
||||
|
||||
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
|
||||
((__SAMPLING__) == USART_OVERSAMPLING_8))
|
||||
#endif /* STM32F0 || STM32F3 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@
|
|||
*/
|
||||
#define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
|
||||
#define __STM32G0xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\
|
||||
|(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\
|
||||
|
|
|
|||
|
|
@ -19,6 +19,18 @@
|
|||
* Other functions (extended functions) are available in file
|
||||
* "stm32g0xx_hal_adc_ex.c".
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### ADC peripheral features #####
|
||||
|
|
@ -275,17 +287,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -415,7 +416,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|||
assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
|
||||
assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
|
||||
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
|
||||
|
||||
if (hadc->Init.OversamplingMode == ENABLE)
|
||||
{
|
||||
assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
|
||||
assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
|
||||
assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
|
||||
}
|
||||
assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
|
||||
|
||||
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
||||
|
|
@ -475,7 +481,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
|
||||
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while (wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
|
|
@ -530,7 +536,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|||
/* function on the fly (update of a parameter of ADC_InitTypeDef */
|
||||
/* without needing to reconfigure all other ADC groups/channels */
|
||||
/* parameters): */
|
||||
/* - internal measurement paths: Vbat, temperature sensor, Vref */
|
||||
/* - internal measurement paths (VrefInt, ...) */
|
||||
/* (set into HAL_ADC_ConfigChannel() ) */
|
||||
|
||||
/* Configuration of ADC resolution */
|
||||
|
|
@ -539,15 +545,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|||
hadc->Init.Resolution);
|
||||
|
||||
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
|
||||
hadc->Init.Oversampling.Ratio |
|
||||
hadc->Init.Oversampling.RightBitShift |
|
||||
hadc->Init.Oversampling.TriggeredMode |
|
||||
hadc->Init.TriggerFrequencyMode
|
||||
);
|
||||
|
||||
if (hadc->Init.OversamplingMode == ENABLE)
|
||||
{
|
||||
SET_BIT(tmpCFGR2, ADC_CFGR2_OVSE);
|
||||
tmpCFGR2 |= (ADC_CFGR2_OVSE |
|
||||
(hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
|
||||
hadc->Init.Oversampling.Ratio |
|
||||
hadc->Init.Oversampling.RightBitShift |
|
||||
hadc->Init.Oversampling.TriggeredMode
|
||||
);
|
||||
}
|
||||
|
||||
MODIFY_REG(hadc->Instance->CFGR2,
|
||||
|
|
@ -747,7 +755,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|||
tmp_hal_status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -763,9 +770,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|||
* bypassed without error reporting: it can be the intended behavior in
|
||||
* case of reset of a single ADC while the other ADCs sharing the same
|
||||
* common group is still running.
|
||||
* @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
|
||||
* this saves more power by reducing leakage currents
|
||||
* and is particularly interesting before entering MCU low-power modes.
|
||||
* @param hadc ADC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
@ -857,12 +861,10 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
|
|||
/* ========== Hard reset ADC peripheral ========== */
|
||||
/* Performs a global reset of the entire ADC peripheral: ADC state is */
|
||||
/* forced to a similar state after device power-on. */
|
||||
/* If needed, copy-paste and uncomment the following reset code into */
|
||||
/* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
|
||||
/* */
|
||||
/* __HAL_RCC_ADC1_FORCE_RESET() */
|
||||
/* __HAL_RCC_ADC1_RELEASE_RESET() */
|
||||
|
||||
/* Note: A possible implementation is to add RCC bus reset of ADC */
|
||||
/* (for example, using macro */
|
||||
/* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
|
||||
/* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
if (hadc->MspDeInitCallback == NULL)
|
||||
{
|
||||
|
|
@ -885,10 +887,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
|
|||
/* Set ADC state */
|
||||
hadc->State = HAL_ADC_STATE_RESET;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -1191,7 +1191,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
|||
/* Perform ADC enable and conversion start if no conversion is on going */
|
||||
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Enable the ADC peripheral */
|
||||
|
|
@ -1229,7 +1228,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
|||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
}
|
||||
}
|
||||
|
|
@ -1238,7 +1236,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
|||
tmp_hal_status = HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -1258,7 +1255,6 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* 1. Stop potential conversion on going, on ADC group regular */
|
||||
|
|
@ -1280,10 +1276,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
|
|||
}
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -1308,7 +1302,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
|
|||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t tmp_Flag_End;
|
||||
uint32_t tmp_flag_end;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
|
@ -1316,7 +1310,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
|
|||
/* If end of conversion selected to end of sequence conversions */
|
||||
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
|
||||
{
|
||||
tmp_Flag_End = ADC_FLAG_EOS;
|
||||
tmp_flag_end = ADC_FLAG_EOS;
|
||||
}
|
||||
/* If end of conversion selected to end of unitary conversion */
|
||||
else /* ADC_EOC_SINGLE_CONV */
|
||||
|
|
@ -1336,7 +1330,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
|
|||
}
|
||||
else
|
||||
{
|
||||
tmp_Flag_End = (ADC_FLAG_EOC);
|
||||
tmp_flag_end = (ADC_FLAG_EOC);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1344,20 +1338,23 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
|
|||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until End of unitary conversion or sequence conversions flag is raised */
|
||||
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
||||
while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
|
||||
{
|
||||
/* Check if timeout is disabled (set to infinite wait) */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1451,13 +1448,16 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy
|
|||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
|
||||
{
|
||||
/* Update ADC state machine to timeout */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1569,7 +1569,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
|
|||
/* Perform ADC enable and conversion start if no conversion is on going */
|
||||
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Enable the ADC peripheral */
|
||||
|
|
@ -1632,7 +1631,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
|
|||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
}
|
||||
|
||||
|
|
@ -1642,7 +1640,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
|
|||
tmp_hal_status = HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -1660,7 +1657,6 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* 1. Stop potential conversion on going, on ADC group regular */
|
||||
|
|
@ -1686,10 +1682,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
|
|||
}
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -1713,7 +1707,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
|
|||
/* Perform ADC enable and conversion start if no conversion is on going */
|
||||
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Specific case for first call occurrence of this function (DMA transfer */
|
||||
|
|
@ -1790,7 +1783,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
|
|||
tmp_hal_status = HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -1808,7 +1800,6 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* 1. Stop potential ADC group regular conversion on going */
|
||||
|
|
@ -1859,10 +1850,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
|
|||
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -2099,7 +2088,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
|
|||
/* ========== Check channel configuration ready flag ========== */
|
||||
if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
|
||||
{
|
||||
/* Level out of window 1 callback */
|
||||
/* Channel configuration ready callback */
|
||||
HAL_ADCEx_ChannelConfigReadyCallback(hadc);
|
||||
|
||||
/* Clear ADC analog watchdog flag */
|
||||
|
|
@ -2207,10 +2196,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
|
|||
* The setting of these parameters is conditioned to ADC state:
|
||||
* Refer to comments of structure "ADC_ChannelConfTypeDef".
|
||||
* @param hadc ADC handle
|
||||
* @param sConfig Structure of ADC channel assigned to ADC group regular.
|
||||
* @param pConfig Structure of ADC channel assigned to ADC group regular.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tmp_config_internal_channel;
|
||||
|
|
@ -2218,22 +2207,21 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
|
||||
assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime));
|
||||
assert_param(IS_ADC_CHANNEL(pConfig->Channel));
|
||||
assert_param(IS_ADC_SAMPLING_TIME_COMMON(pConfig->SamplingTime));
|
||||
|
||||
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
|
||||
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
|
||||
{
|
||||
assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank));
|
||||
assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(pConfig->Rank));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
|
||||
|
||||
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
|
||||
assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Parameters update conditioned to ADC state: */
|
||||
|
|
@ -2251,7 +2239,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
/* Otherwise (sequencer set to fully configurable or to to not fully */
|
||||
/* configurable with channel rank to be set), configure the selected */
|
||||
/* channel. */
|
||||
if (sConfig->Rank != ADC_RANK_NONE)
|
||||
if (pConfig->Rank != ADC_RANK_NONE)
|
||||
{
|
||||
/* Regular sequence configuration */
|
||||
/* Note: ADC channel configuration requires few ADC clock cycles */
|
||||
|
|
@ -2264,7 +2252,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
{
|
||||
/* Sequencer set to not fully configurable: */
|
||||
/* Set the channel by enabling the corresponding bitfield. */
|
||||
LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
|
||||
LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -2273,21 +2261,21 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
|
||||
/* Memorize the channel set into variable in HAL ADC handle */
|
||||
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
|
||||
ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL),
|
||||
__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL));
|
||||
ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL),
|
||||
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) << (pConfig->Rank & 0x1FUL));
|
||||
|
||||
/* If the selected rank is below ADC group regular sequencer length, */
|
||||
/* apply the configuration in ADC register. */
|
||||
/* Note: Otherwise, configuration is not applied. */
|
||||
/* To apply it, parameter'NbrOfConversion' must be increased. */
|
||||
if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
|
||||
if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
|
||||
{
|
||||
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
|
||||
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set sampling time of the selected ADC channel */
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
|
||||
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
|
||||
|
||||
/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
|
||||
/* internal measurement paths enable: If internal channel selected, */
|
||||
|
|
@ -2295,13 +2283,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
/* Note: these internal measurement paths can be disabled using */
|
||||
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
|
||||
/* channel configuration parameter "Rank". */
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
|
||||
{
|
||||
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
|
||||
/* If the requested internal measurement path has already been enabled, */
|
||||
/* bypass the configuration processing. */
|
||||
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
|
||||
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
|
||||
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
|
||||
{
|
||||
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
||||
|
|
@ -2312,18 +2300,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
|
||||
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while (wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
}
|
||||
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
||||
else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
||||
{
|
||||
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
||||
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
|
||||
}
|
||||
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
|
||||
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
|
||||
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
|
||||
{
|
||||
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
||||
|
|
@ -2347,27 +2335,27 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
{
|
||||
/* Sequencer set to not fully configurable: */
|
||||
/* Reset the channel by disabling the corresponding bitfield. */
|
||||
LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel);
|
||||
LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel);
|
||||
}
|
||||
|
||||
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
|
||||
/* If internal channel selected, enable dedicated internal buffers and */
|
||||
/* paths. */
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
||||
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
|
||||
{
|
||||
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
||||
|
||||
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
||||
if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
||||
{
|
||||
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
||||
~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
|
||||
}
|
||||
else if (sConfig->Channel == ADC_CHANNEL_VBAT)
|
||||
else if (pConfig->Channel == ADC_CHANNEL_VBAT)
|
||||
{
|
||||
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
||||
~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
|
||||
}
|
||||
else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
|
||||
else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
|
||||
{
|
||||
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
||||
~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
|
||||
|
|
@ -2391,10 +2379,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
tmp_hal_status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -2417,24 +2403,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
* bus activity, this might cause an uncertainty on the
|
||||
* effective timing of the new programmed threshold values.
|
||||
* @param hadc ADC handle
|
||||
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
|
||||
* @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
|
||||
{
|
||||
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
||||
uint32_t tmpAWDHighThresholdShifted;
|
||||
uint32_t tmpAWDLowThresholdShifted;
|
||||
uint32_t tmp_awd_high_threshold_shifted;
|
||||
uint32_t tmp_awd_low_threshold_shifted;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
|
||||
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
|
||||
|
||||
if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
|
||||
if (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
|
||||
{
|
||||
assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
|
||||
assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel));
|
||||
}
|
||||
|
||||
/* Verify thresholds range */
|
||||
|
|
@ -2443,17 +2429,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
/* Case of oversampling enabled: depending on ratio and shift configuration,
|
||||
analog watchdog thresholds can be higher than ADC resolution.
|
||||
Verify if thresholds are within maximum thresholds range. */
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Verify if thresholds are within the selected ADC resolution */
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
|
||||
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Parameters update conditioned to ADC state: */
|
||||
|
|
@ -2463,16 +2448,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
/* Analog watchdog configuration */
|
||||
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
|
||||
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
|
||||
{
|
||||
/* Configuration of analog watchdog: */
|
||||
/* - Set the analog watchdog enable mode: one or overall group of */
|
||||
/* channels. */
|
||||
switch (AnalogWDGConfig->WatchdogMode)
|
||||
switch (pAnalogWDGConfig->WatchdogMode)
|
||||
{
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_REG:
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
|
||||
__LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
|
||||
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
|
||||
break;
|
||||
|
||||
case ADC_ANALOGWATCHDOG_ALL_REG:
|
||||
|
|
@ -2494,7 +2479,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
LL_ADC_ClearFlag_AWD1(hadc->Instance);
|
||||
|
||||
/* Configure ADC analog watchdog interrupt */
|
||||
if (AnalogWDGConfig->ITMode == ENABLE)
|
||||
if (pAnalogWDGConfig->ITMode == ENABLE)
|
||||
{
|
||||
LL_ADC_EnableIT_AWD1(hadc->Instance);
|
||||
}
|
||||
|
|
@ -2506,31 +2491,31 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
|
||||
else
|
||||
{
|
||||
switch (AnalogWDGConfig->WatchdogMode)
|
||||
switch (pAnalogWDGConfig->WatchdogMode)
|
||||
{
|
||||
case ADC_ANALOGWATCHDOG_SINGLE_REG:
|
||||
/* Update AWD by bitfield to keep the possibility to monitor */
|
||||
/* several channels by successive calls of this function. */
|
||||
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
{
|
||||
SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
|
||||
SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
|
||||
SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
|
||||
}
|
||||
break;
|
||||
|
||||
case ADC_ANALOGWATCHDOG_ALL_REG:
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
|
||||
break;
|
||||
|
||||
default: /* ADC_ANALOGWATCHDOG_NONE */
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
|
||||
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
|
||||
break;
|
||||
}
|
||||
|
||||
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
|
||||
{
|
||||
/* Update state, clear previous result related to AWD2 */
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
|
||||
|
|
@ -2542,7 +2527,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
LL_ADC_ClearFlag_AWD2(hadc->Instance);
|
||||
|
||||
/* Configure ADC analog watchdog interrupt */
|
||||
if (AnalogWDGConfig->ITMode == ENABLE)
|
||||
if (pAnalogWDGConfig->ITMode == ENABLE)
|
||||
{
|
||||
LL_ADC_EnableIT_AWD2(hadc->Instance);
|
||||
}
|
||||
|
|
@ -2551,7 +2536,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
LL_ADC_DisableIT_AWD2(hadc->Instance);
|
||||
}
|
||||
}
|
||||
/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
|
||||
/* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
|
||||
else
|
||||
{
|
||||
/* Update state, clear previous result related to AWD3 */
|
||||
|
|
@ -2564,7 +2549,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
LL_ADC_ClearFlag_AWD3(hadc->Instance);
|
||||
|
||||
/* Configure ADC analog watchdog interrupt */
|
||||
if (AnalogWDGConfig->ITMode == ENABLE)
|
||||
if (pAnalogWDGConfig->ITMode == ENABLE)
|
||||
{
|
||||
LL_ADC_EnableIT_AWD3(hadc->Instance);
|
||||
}
|
||||
|
|
@ -2578,13 +2563,13 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
}
|
||||
|
||||
/* Analog watchdog thresholds configuration */
|
||||
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
|
||||
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
|
||||
{
|
||||
/* Shift the offset with respect to the selected ADC resolution: */
|
||||
/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
|
||||
/* are set to 0. */
|
||||
tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
|
||||
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
|
||||
tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
|
||||
tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
|
||||
}
|
||||
/* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
|
||||
else
|
||||
|
|
@ -2592,18 +2577,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
|
|||
/* No need to shift the offset with respect to the selected ADC resolution: */
|
||||
/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
|
||||
/* are set to 0. */
|
||||
tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold;
|
||||
tmpAWDLowThresholdShifted = AnalogWDGConfig->LowThreshold;
|
||||
tmp_awd_high_threshold_shifted = pAnalogWDGConfig->HighThreshold;
|
||||
tmp_awd_low_threshold_shifted = pAnalogWDGConfig->LowThreshold;
|
||||
}
|
||||
|
||||
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
|
||||
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
|
||||
tmpAWDLowThresholdShifted);
|
||||
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
|
||||
tmp_awd_low_threshold_shifted);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -2707,13 +2690,17 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc)
|
|||
{
|
||||
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
|
||||
return HAL_ERROR;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2763,7 +2750,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
|
|||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
|
||||
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while (wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
|
|
@ -2794,13 +2781,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
|
|||
|
||||
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
|
||||
return HAL_ERROR;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2855,13 +2846,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
|
|||
{
|
||||
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
|
||||
return HAL_ERROR;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -132,8 +132,7 @@ typedef struct
|
|||
|
||||
FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
|
||||
This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
|
||||
after the first ADC conversion start trigger occurred (software start or external trigger).
|
||||
|
|
@ -473,7 +472,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
|||
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
|
||||
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
|
||||
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -516,17 +515,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
|||
#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#if defined(TIM2)
|
||||
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#endif
|
||||
#endif /* TIM2 */
|
||||
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#if defined(TIM4)
|
||||
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#endif
|
||||
#endif /* TIM4 */
|
||||
#if defined(TIM6)
|
||||
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#endif
|
||||
#endif /* TIM6 */
|
||||
#if defined(TIM15)
|
||||
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#endif
|
||||
#endif /* TIM15 */
|
||||
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -941,7 +940,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
|||
((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START) )
|
||||
#endif
|
||||
#endif /* TIM15 && TIM6 && TIM2 */
|
||||
|
||||
#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
|
||||
((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
|
||||
|
|
@ -1707,8 +1706,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -12,12 +12,6 @@
|
|||
* Other functions (generic functions) are available in file
|
||||
* "stm32g0xx_hal_adc.c".
|
||||
*
|
||||
@verbatim
|
||||
[..]
|
||||
(@) Sections "ADC peripheral features" and "How to use this driver" are
|
||||
available in file of generic functions "stm32g0xx_hal_adc.c".
|
||||
[..]
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
|
|
@ -30,6 +24,12 @@
|
|||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
[..]
|
||||
(@) Sections "ADC peripheral features" and "How to use this driver" are
|
||||
available in file of generic functions "stm32g0xx_hal_adc.c".
|
||||
[..]
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -110,7 +110,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Calibration prerequisite: ADC must be disabled. */
|
||||
|
|
@ -149,7 +148,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
|
|||
HAL_ADC_STATE_BUSY_INTERNAL,
|
||||
HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_ERROR;
|
||||
|
|
@ -172,10 +170,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
|
|||
/* to state "HAL_ERROR" by function disabling the ADC. */
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
@ -209,7 +205,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
|
|||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_CALFACT(CalibrationFactor));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
/* Verification of hardware constraints before modifying the calibration */
|
||||
|
|
@ -234,10 +229,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
|
|||
tmp_hal_status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
/* Return function status */
|
||||
return tmp_hal_status;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -822,19 +822,15 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
/* CEC TX byte request interrupt ------------------------------------------------*/
|
||||
if ((reg & CEC_FLAG_TXBR) != 0U)
|
||||
{
|
||||
--hcec->TxXferCount;
|
||||
if (hcec->TxXferCount == 0U)
|
||||
{
|
||||
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
|
||||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
}
|
||||
else
|
||||
{
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
hcec->TxXferCount--;
|
||||
}
|
||||
/* In all cases transmit the byte */
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
/* clear Tx-Byte request flag */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -240,7 +240,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
|||
#if defined(COMP3)
|
||||
__IO uint32_t * comp_common_odd;
|
||||
__IO uint32_t * comp_common_even;
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if(hcomp == NULL)
|
||||
|
|
@ -425,7 +425,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
|||
CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
|
||||
/* Delay for COMP scaler bridge voltage stabilization */
|
||||
/* Apply the delay if voltage scaler bridge is required and not already enabled */
|
||||
|
|
@ -436,7 +436,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
|||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
|
||||
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while(wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
|
|
@ -811,7 +811,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
|
|||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
|
||||
wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while(wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
|
|
@ -907,7 +907,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
|
|||
comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
|
||||
comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
|
||||
comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2);
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
|
||||
/* Check COMP EXTI flag */
|
||||
if(LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL)
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ typedef enum
|
|||
typedef struct __COMP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
|
|
@ -173,7 +173,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
|
|||
#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
|
||||
#if defined(COMP3)
|
||||
#define COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -307,7 +307,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
|
|||
} while(0)
|
||||
#else
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
#endif
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
|
||||
|
|
@ -674,7 +674,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
|
|||
#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */
|
||||
#if defined(COMP3)
|
||||
#define COMP_EXTI_LINE_COMP3 (EXTI_IMR1_IM20) /*!< EXTI line 20 connected to COMP3 output */
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -714,7 +714,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
|
|||
#else
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
|
||||
: COMP_EXTI_LINE_COMP2)
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -738,7 +738,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
|
|||
(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
|
||||
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \
|
||||
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) )
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
|
||||
#define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \
|
||||
((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \
|
||||
|
|
|
|||
|
|
@ -62,8 +62,8 @@
|
|||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions CRC Private Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
|
|
@ -77,8 +77,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
|
|||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
|
@ -250,8 +250,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
|||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
|
@ -385,8 +385,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
|||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
|
@ -418,8 +418,8 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
|||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enter 8-bit input data to the CRC calculator.
|
||||
|
|
|
|||
|
|
@ -60,19 +60,22 @@ typedef struct
|
|||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
|
||||
X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
|
||||
CRCLength fields must be set. */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
|
||||
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal,
|
||||
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
|
||||
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
|
||||
DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
|
|
@ -87,14 +90,18 @@ typedef struct
|
|||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
|
||||
becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
|
||||
0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
|
||||
becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
|
||||
into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -112,12 +119,16 @@ typedef struct
|
|||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
|
||||
(8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
|
||||
half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
|
||||
(32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
||||
must occur if InputBufferFormat is not one of the three values listed above */
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
|
||||
error must occur if InputBufferFormat is not one of the three values listed
|
||||
above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -199,15 +210,6 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -267,7 +269,6 @@ typedef struct
|
|||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
|
|
|
|||
|
|
@ -587,15 +587,17 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
|
|||
__HAL_LOCK(hcryp);
|
||||
|
||||
/* Set CRYP parameters */
|
||||
hcryp->Init.DataType = pConf->DataType;
|
||||
hcryp->Init.pKey = pConf->pKey;
|
||||
hcryp->Init.Algorithm = pConf->Algorithm;
|
||||
hcryp->Init.KeySize = pConf->KeySize;
|
||||
hcryp->Init.pInitVect = pConf->pInitVect;
|
||||
hcryp->Init.Header = pConf->Header;
|
||||
hcryp->Init.HeaderSize = pConf->HeaderSize;
|
||||
hcryp->Init.B0 = pConf->B0;
|
||||
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
|
||||
hcryp->Init.DataType = pConf->DataType;
|
||||
hcryp->Init.pKey = pConf->pKey;
|
||||
hcryp->Init.Algorithm = pConf->Algorithm;
|
||||
hcryp->Init.KeySize = pConf->KeySize;
|
||||
hcryp->Init.pInitVect = pConf->pInitVect;
|
||||
hcryp->Init.Header = pConf->Header;
|
||||
hcryp->Init.HeaderSize = pConf->HeaderSize;
|
||||
hcryp->Init.B0 = pConf->B0;
|
||||
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
|
||||
hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
|
||||
hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
|
||||
|
||||
/* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/
|
||||
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
|
||||
|
|
@ -661,7 +663,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
|
|||
pConf->Header = hcryp->Init.Header ;
|
||||
pConf->HeaderSize = hcryp->Init.HeaderSize;
|
||||
pConf->B0 = hcryp->Init.B0;
|
||||
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
|
||||
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
|
||||
pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
|
||||
pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
|
|
@ -693,8 +697,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspInit could be implemented in the user file
|
||||
/* NOTE : This function should not be modified; when the callback is needed,
|
||||
the HAL_CRYP_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
|
@ -709,8 +713,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_MspDeInit could be implemented in the user file
|
||||
/* NOTE : This function should not be modified; when the callback is needed,
|
||||
the HAL_CRYP_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
|
@ -1205,7 +1209,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
|
|||
|
||||
/* Check input buffer size */
|
||||
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
|
|
@ -1305,7 +1309,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
|
|||
|
||||
/* Check input buffer size */
|
||||
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
|
|
@ -1404,7 +1408,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
|
|||
|
||||
/* Check input buffer size */
|
||||
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
|
|
@ -1514,7 +1518,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
|
|||
|
||||
/* Check input buffer size */
|
||||
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
|
|
@ -1624,7 +1628,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
|
|||
|
||||
/* Check input buffer size */
|
||||
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
|
|
@ -1750,7 +1754,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
|
|||
|
||||
/* Check input buffer size */
|
||||
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
|
|
@ -1929,8 +1933,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_InCpltCallback could be implemented in the user file
|
||||
/* NOTE : This function should not be modified; when the callback is needed,
|
||||
the HAL_CRYP_InCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
|
@ -1945,8 +1949,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_OutCpltCallback could be implemented in the user file
|
||||
/* NOTE : This function should not be modified; when the callback is needed,
|
||||
the HAL_CRYP_OutCpltCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
|
@ -1961,8 +1965,8 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcryp);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_CRYP_ErrorCallback could be implemented in the user file
|
||||
/* NOTE : This function should not be modified; when the callback is needed,
|
||||
the HAL_CRYP_ErrorCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
/**
|
||||
|
|
@ -2570,15 +2574,31 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
|
|||
/* Initiate payload DMA IN and processed data DMA OUT transfers */
|
||||
(void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint32_t algo;
|
||||
/* ECB, CBC or CTR end of input data feeding
|
||||
or
|
||||
end of GCM/CCM payload data feeding through DMA */
|
||||
algo = hcryp->Instance->CR & AES_CR_CHMOD;
|
||||
|
||||
/* Call input data transfer complete callback */
|
||||
/* Don't call input data transfer complete callback only if
|
||||
it remains some input data to write to the peripheral.
|
||||
This case can only occur for GCM and CCM with a payload length
|
||||
not a multiple of 16 bytes */
|
||||
if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \
|
||||
(((hcryp->Size) % 16U) != 0U)))
|
||||
{
|
||||
/* Call input data transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
} /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2642,6 +2662,14 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
|
|||
hcryp->Instance->DINR = 0x0U;
|
||||
count++;
|
||||
}
|
||||
/* Call input data transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/*Wait on CCF flag*/
|
||||
CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
|
||||
|
|
@ -3380,7 +3408,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypInCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
|
||||
hcryp->CrypInCount++;
|
||||
if (hcryp->CrypInCount == (hcryp->Size / 4U))
|
||||
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
|
||||
{
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
|
|
@ -3431,6 +3459,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
/* Enter header data */
|
||||
|
|
@ -3470,15 +3506,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -3528,7 +3555,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypInCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
|
||||
hcryp->CrypInCount++;
|
||||
if (hcryp->CrypInCount == (hcryp->Size / 4U))
|
||||
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
|
||||
{
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
|
|
@ -3579,6 +3606,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3904,6 +3939,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
uint32_t npblb;
|
||||
uint32_t mode;
|
||||
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
|
||||
uint32_t headersize_in_bytes;
|
||||
uint32_t tmp;
|
||||
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
|
||||
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
|
||||
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
|
||||
|
|
@ -3993,7 +4033,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
/* Enable the CRYP peripheral */
|
||||
__HAL_CRYP_ENABLE(hcryp);
|
||||
|
||||
if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
|
||||
}
|
||||
else
|
||||
{
|
||||
headersize_in_bytes = hcryp->Init.HeaderSize;
|
||||
}
|
||||
|
||||
if (headersize_in_bytes == 0U) /* Header phase is skipped */
|
||||
{
|
||||
/* Set the phase */
|
||||
hcryp->Phase = CRYP_PHASE_PROCESS;
|
||||
|
|
@ -4077,26 +4126,63 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */
|
||||
/* Enter header data */
|
||||
/* Check first whether header length is small enough to enter the full header in one shot */
|
||||
else if (headersize_in_bytes <= 16U)
|
||||
{
|
||||
/* Last block optionally pad the data with zeros*/
|
||||
for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
|
||||
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
|
||||
{
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++ ;
|
||||
}
|
||||
/* If the header size is a multiple of words */
|
||||
if ((headersize_in_bytes % 4U) == 0U)
|
||||
{
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter last bytes, padded with zeros */
|
||||
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
|
||||
hcryp->Instance->DINR = tmp;
|
||||
hcryp->CrypHeaderCount++;
|
||||
loopcounter++;
|
||||
/* Pad the data with zeros to have a complete block */
|
||||
while (loopcounter < 4U)
|
||||
{
|
||||
/* pad the data with zeros to have a complete block */
|
||||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
}
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Write the input block in the IN FIFO */
|
||||
/* Write the first input header block in the Input FIFO,
|
||||
the following header data will be fed after interrupt occurrence */
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
|
|
@ -4105,9 +4191,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypHeaderCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
|
||||
hcryp->CrypHeaderCount++;
|
||||
}
|
||||
|
||||
} /* end of if (DoKeyIVConfig == 1U) */
|
||||
}/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
|
||||
} /* end of if (dokeyivconfig == 1U) */
|
||||
else /* Key and IV have already been configured,
|
||||
header has already been processed;
|
||||
only process here message payload */
|
||||
|
|
@ -4182,6 +4267,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
/* Call Input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4387,9 +4480,9 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypInCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
|
||||
hcryp->CrypInCount++;
|
||||
if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
|
||||
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
|
||||
{
|
||||
/* Call output transfer complete callback */
|
||||
/* Call input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
|
|
@ -4435,6 +4528,14 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
/* Call input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4509,6 +4610,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr
|
|||
hcryp->Instance->DINR = 0U;
|
||||
index++;
|
||||
}
|
||||
/* Call the input data transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
/* Wait for CCF flag to be raised */
|
||||
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
|
||||
do
|
||||
|
|
@ -4550,6 +4659,15 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr
|
|||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
|
||||
/* Call Output transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Output complete callback*/
|
||||
hcryp->OutCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Output complete callback*/
|
||||
HAL_CRYP_OutCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -4947,6 +5065,14 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->Instance->DINR = 0x0U;
|
||||
loopcounter++;
|
||||
}
|
||||
/* Call the input data transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
#else
|
||||
/*Call legacy weak Input complete callback*/
|
||||
HAL_CRYP_InCpltCallback(hcryp);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
|
||||
|
|
@ -5398,9 +5524,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
|
|||
hcryp->CrypInCount++;
|
||||
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
|
||||
hcryp->CrypInCount++;
|
||||
if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
|
||||
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
|
||||
{
|
||||
/* Call output transfer complete callback */
|
||||
/* Call input transfer complete callback */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Input complete callback*/
|
||||
hcryp->InCpltCallback(hcryp);
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ typedef enum
|
|||
typedef struct __CRYP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
{
|
||||
AES_TypeDef *Instance; /*!< AES Register base address */
|
||||
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ typedef enum
|
|||
typedef struct __DAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
|
|
|||
|
|
@ -110,10 +110,10 @@ typedef enum
|
|||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#endif /* __packed */
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
|
|
@ -129,10 +129,10 @@ typedef enum
|
|||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#endif /* __ALIGN_END */
|
||||
#elif defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4U)))
|
||||
|
|
@ -185,7 +185,7 @@ typedef enum
|
|||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
#endif /* __CC_ARM || __ARMCC_VERSION */
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
|
|
@ -202,7 +202,7 @@ typedef enum
|
|||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
#endif /* __CC_ARM || __ARMCC_VERSION */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
|
||||
thanks to:
|
||||
(##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE();
|
||||
(##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
|
@ -185,7 +184,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|||
}
|
||||
#else
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
|
@ -286,7 +285,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
|||
}
|
||||
#else
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Reset DMA Channel control register */
|
||||
hdma->Instance->CCR = 0U;
|
||||
|
|
@ -296,7 +295,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
|||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Initialize parameters for DMAMUX channel :
|
||||
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
|
||||
|
|
@ -537,7 +536,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
|
@ -595,7 +594,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
||||
|
|
@ -710,7 +709,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
|||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
|
|
@ -764,7 +763,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
|||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
|
@ -780,7 +779,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
|||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -798,7 +797,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
||||
#else
|
||||
uint32_t flag_it = DMA1->ISR;
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
uint32_t source_it = hdma->Instance->CCR;
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
|
|
@ -815,7 +814,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* but in Transfer Complete case */
|
||||
|
|
@ -864,7 +863,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
|
@ -1082,7 +1081,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
|
|||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
#else
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
|
@ -1143,7 +1142,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
|
||||
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
|
||||
/* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */
|
||||
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
#if defined(DMA2)
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||
|
||||
#endif
|
||||
#endif /* DMA2 */
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
|
||||
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
|
||||
|
|
@ -190,11 +190,11 @@ typedef struct __DMA_HandleTypeDef
|
|||
#if defined(AES)
|
||||
#define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */
|
||||
#define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */
|
||||
#endif
|
||||
#endif /* AES */
|
||||
#if defined(DAC1)
|
||||
#define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1 /*!< DMAMUX DAC_CH1 request */
|
||||
#define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2 /*!< DMAMUX DAC_CH2 request */
|
||||
#endif
|
||||
#endif /* DAC1 */
|
||||
#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */
|
||||
#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */
|
||||
#define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */
|
||||
|
|
@ -202,7 +202,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
#if defined(LPUART1)
|
||||
#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */
|
||||
#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */
|
||||
#endif
|
||||
#endif /* LPUART1 */
|
||||
#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */
|
||||
#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */
|
||||
#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */
|
||||
|
|
@ -220,7 +220,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */
|
||||
#define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */
|
||||
#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */
|
||||
#endif
|
||||
#endif /* TIM2 */
|
||||
#define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */
|
||||
#define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */
|
||||
#define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */
|
||||
|
|
@ -229,16 +229,16 @@ typedef struct __DMA_HandleTypeDef
|
|||
#define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */
|
||||
#if defined(TIM6)
|
||||
#define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */
|
||||
#endif
|
||||
#endif /* TIM6 */
|
||||
#if defined(TIM7)
|
||||
#define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */
|
||||
#endif
|
||||
#endif /* TIM7 */
|
||||
#if defined(TIM15)
|
||||
#define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */
|
||||
#define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */
|
||||
#define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */
|
||||
#define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */
|
||||
#endif
|
||||
#endif /* TIM15 */
|
||||
#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */
|
||||
#define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */
|
||||
#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */
|
||||
|
|
@ -252,34 +252,34 @@ typedef struct __DMA_HandleTypeDef
|
|||
#if defined(USART3)
|
||||
#define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */
|
||||
#define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */
|
||||
#endif
|
||||
#endif /* USART3 */
|
||||
#if defined(USART4)
|
||||
#define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */
|
||||
#define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */
|
||||
#endif
|
||||
#endif /* USART4 */
|
||||
#if defined(UCPD1)
|
||||
#define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX /*!< DMAMUX UCPD1 RX request */
|
||||
#define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX /*!< DMAMUX UCPD1 TX request */
|
||||
#endif
|
||||
#endif/* UCPD1 */
|
||||
#if defined(UCPD2)
|
||||
#define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX /*!< DMAMUX UCPD2 RX request */
|
||||
#define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX /*!< DMAMUX UCPD2 TX request */
|
||||
#endif
|
||||
#endif /* UCPD2 */
|
||||
|
||||
#if defined(I2C3)
|
||||
#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */
|
||||
#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */
|
||||
#endif
|
||||
#endif /* I2C3 */
|
||||
|
||||
#if defined(LPUART2)
|
||||
#define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */
|
||||
#define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */
|
||||
#endif
|
||||
#endif /* LPUART2 */
|
||||
|
||||
#if defined(SPI3)
|
||||
#define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */
|
||||
#define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */
|
||||
#endif
|
||||
#endif /* SPI3 */
|
||||
|
||||
#if defined(TIM4)
|
||||
#define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1 /*!< DMAMUX TIM4 CH1 request */
|
||||
|
|
@ -288,17 +288,17 @@ typedef struct __DMA_HandleTypeDef
|
|||
#define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4 /*!< DMAMUX TIM4 CH4 request */
|
||||
#define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG /*!< DMAMUX TIM4 TRIG request */
|
||||
#define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP /*!< DMAMUX TIM4 UP request */
|
||||
#endif
|
||||
#endif /* TIM4 */
|
||||
|
||||
#if defined(USART5)
|
||||
#define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX /*!< DMAMUX USART5 RX request */
|
||||
#define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX /*!< DMAMUX USART5 TX request */
|
||||
#endif
|
||||
#endif /* USART5 */
|
||||
|
||||
#if defined(USART6)
|
||||
#define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX /*!< DMAMUX USART6 RX request */
|
||||
#define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX /*!< DMAMUX USART6 TX request */
|
||||
#endif
|
||||
#endif /* USART6 */
|
||||
|
||||
|
||||
#define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ
|
||||
|
|
@ -391,36 +391,36 @@ typedef struct __DMA_HandleTypeDef
|
|||
|
||||
#define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */
|
||||
#define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */
|
||||
#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */
|
||||
#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */
|
||||
#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */
|
||||
#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */
|
||||
#define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */
|
||||
#define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */
|
||||
#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */
|
||||
#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */
|
||||
#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */
|
||||
#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */
|
||||
#define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */
|
||||
#define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */
|
||||
#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */
|
||||
#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */
|
||||
#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */
|
||||
#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */
|
||||
#define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */
|
||||
#define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */
|
||||
#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */
|
||||
#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */
|
||||
#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */
|
||||
#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */
|
||||
#define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */
|
||||
#define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */
|
||||
#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */
|
||||
#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */
|
||||
#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */
|
||||
#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */
|
||||
#if defined(DMA1_Channel6)
|
||||
#define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */
|
||||
#define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */
|
||||
#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */
|
||||
#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */
|
||||
#endif
|
||||
#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */
|
||||
#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */
|
||||
#endif /* DMA1_Channel6 */
|
||||
#if defined(DMA1_Channel7)
|
||||
#define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */
|
||||
#define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */
|
||||
#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */
|
||||
#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */
|
||||
#endif
|
||||
#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */
|
||||
#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */
|
||||
#endif /* DMA1_Channel7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -490,7 +490,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
#endif
|
||||
#endif /* DMA1_Channel8 */
|
||||
#endif /* DMA2 */
|
||||
|
||||
/**
|
||||
|
|
@ -529,7 +529,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
#endif
|
||||
#endif /* DMA1_Channel8 */
|
||||
#endif /* DMA2 */
|
||||
|
||||
/**
|
||||
|
|
@ -568,7 +568,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
#endif
|
||||
#endif /* DMA1_Channel8 */
|
||||
#endif /* DMA2 */
|
||||
|
||||
/**
|
||||
|
|
@ -607,7 +607,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
|
||||
DMA_FLAG_GI5)
|
||||
#endif
|
||||
#endif /* DMA1_Channel8 */
|
||||
#endif /* DMA2 */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -116,10 +116,10 @@ typedef struct
|
|||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3 /*!< Synchronization signal from DMAMUX channel3 Event */
|
||||
#if defined(LPTIM1)
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */
|
||||
#endif
|
||||
#endif /* LPTIM1 */
|
||||
#if defined(LPTIM2)
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */
|
||||
#endif
|
||||
#endif /* LPTIM2 */
|
||||
#define HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC /*!< Synchronization signal from TIM14 OC */
|
||||
|
||||
#define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC
|
||||
|
|
@ -164,10 +164,10 @@ typedef struct
|
|||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3 /*!< Request signal generation from DMAMUX channel3 Event */
|
||||
#if defined(LPTIM1)
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */
|
||||
#endif
|
||||
#endif /* LPTIM1 */
|
||||
#if defined(LPTIM2)
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */
|
||||
#endif
|
||||
#endif /* LPTIM2 */
|
||||
#define HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC /*!< Request signal generation from TIM14 OC */
|
||||
|
||||
#define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC
|
||||
|
|
|
|||
|
|
@ -312,6 +312,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
|||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* Get default Trigger and GPIOSel configuration */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
|
|
@ -323,10 +327,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
|||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
|
|
@ -346,15 +346,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
|||
regval = EXTI->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
|
|||
|
|
@ -109,80 +109,80 @@ typedef struct
|
|||
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
|
||||
#else
|
||||
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
|
||||
#endif
|
||||
#endif /* COMP1 */
|
||||
#if defined(COMP2)
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u)
|
||||
#else
|
||||
#define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u)
|
||||
#endif
|
||||
#endif /* COMP2 */
|
||||
#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u)
|
||||
#if defined(COMP3)
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
|
||||
#else
|
||||
#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u)
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u)
|
||||
#if defined(RCC_CCIPR_I2C2SEL)
|
||||
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
|
||||
#else
|
||||
#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u)
|
||||
#endif
|
||||
#endif /* RCC_CCIPR_I2C2SEL */
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
|
||||
#if defined(RCC_CCIPR_USART3SEL)
|
||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
|
||||
#else
|
||||
#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u)
|
||||
#endif
|
||||
#endif /* RCC_CCIPR_USART3SEL */
|
||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
|
||||
#if defined(RCC_CCIPR_USART2SEL)
|
||||
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
|
||||
#else
|
||||
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
|
||||
#endif
|
||||
#endif /* RCC_CCIPR_USART2SEL */
|
||||
#if defined(CEC)
|
||||
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
|
||||
#else
|
||||
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
|
||||
#endif
|
||||
#endif /* CEC */
|
||||
#if defined(LPUART1)
|
||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
|
||||
#else
|
||||
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
|
||||
#endif
|
||||
#endif /* LPUART1 */
|
||||
#if defined(LPTIM1)
|
||||
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
|
||||
#else
|
||||
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
|
||||
#endif
|
||||
#endif /* LPTIM1 */
|
||||
#if defined(LPTIM2)
|
||||
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
|
||||
#else
|
||||
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
|
||||
#endif
|
||||
#endif /* LPTIM2 */
|
||||
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu)
|
||||
#if defined(UCPD1)
|
||||
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u)
|
||||
#else
|
||||
#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
|
||||
#endif
|
||||
#endif /* UCPD1 */
|
||||
#if defined(UCPD2)
|
||||
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u)
|
||||
#else
|
||||
#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u)
|
||||
#endif
|
||||
#endif /* UCPD2 */
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
||||
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u)
|
||||
#else
|
||||
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
|
||||
#endif
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx */
|
||||
#if defined(LPUART2)
|
||||
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
|
||||
#else
|
||||
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
|
||||
#endif
|
||||
#endif /* LPUART2 */
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
|
||||
#endif
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -218,7 +218,7 @@ typedef struct
|
|||
#define EXTI_GPIOD 0x00000003u
|
||||
#if defined(GPIOE)
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#endif
|
||||
#endif /* GPIOE */
|
||||
#define EXTI_GPIOF 0x00000005u
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -285,7 +285,7 @@ typedef struct
|
|||
#define EXTI_LINE_NB 32uL
|
||||
#else
|
||||
#define EXTI_LINE_NB 32uL
|
||||
#endif
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -325,7 +325,7 @@ typedef struct
|
|||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#endif
|
||||
#endif /* GPIOE */
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
|
||||
|
|
|
|||
|
|
@ -103,8 +103,8 @@
|
|||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Variable used for Program/Erase sectors under interruption
|
||||
*/
|
||||
|
|
@ -122,8 +122,8 @@ FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
|
|||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
|
||||
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
|
||||
/**
|
||||
|
|
@ -136,8 +136,8 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
|
|||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Programming operation functions #####
|
||||
|
|
@ -157,7 +157,9 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
|
|||
* @param Address Specifies the address to be programmed.
|
||||
* @param Data Specifies the data to be programmed
|
||||
* This parameter is the data for the double word program and the address where
|
||||
* are stored the data for the row fast program.
|
||||
* are stored the data for the row fast program depending on the TypeProgram:
|
||||
* TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit)
|
||||
* TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit).
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
|
|
@ -217,7 +219,9 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
|
|||
* @param Address Specifies the address to be programmed.
|
||||
* @param Data Specifies the data to be programmed
|
||||
* This parameter is the data for the double word program and the address where
|
||||
* are stored the data for the row fast program.
|
||||
* are stored the data for the row fast program depending on the TypeProgram:
|
||||
* TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit)
|
||||
* TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit).
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
|
|
@ -410,8 +414,8 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
|||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Management functions
|
||||
*
|
||||
* @brief Management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
|
@ -531,8 +535,8 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
|||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
|
|
@ -598,7 +602,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
|||
error = (FLASH_SR_BSY1 | FLASH_SR_BSY2);
|
||||
#else
|
||||
error = FLASH_SR_BSY1;
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
while ((FLASH->SR & error) != 0x00U)
|
||||
{
|
||||
|
|
@ -694,7 +698,7 @@ static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress
|
|||
while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U)
|
||||
#else
|
||||
while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U)
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -117,8 +117,8 @@ typedef struct
|
|||
to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
|
||||
uint32_t PCROP2BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
uint32_t BootEntryPoint; /*!< Allow to force a unique boot entry point to Flash or system Flash */
|
||||
uint32_t SecSize; /*!< This parameter defines securable memory area width in number of pages starting from Flash base address.
|
||||
|
|
@ -128,13 +128,13 @@ typedef struct
|
|||
uint32_t SecSize2; /*!< This parameter defines securable memory area width in number of pages starting from 2nd Bank start address.
|
||||
This parameter must be a value between [0] and [FLASH_PAGE_NB],
|
||||
[0] meaning no secure area defined, [1] meaning first page only protected, etc... */
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
|
|
@ -196,18 +196,18 @@ typedef struct
|
|||
#define FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos) /*!< FLASH Operation Busy flag for Bank 1 */
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos) /*!< FLASH Operation Busy flag for Bank 2 */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#define FLASH_FLAG_BSY FLASH_FLAG_BSY1 /*!< FLASH Operation Busy flag - legacy name for single bank */
|
||||
#define FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos) /*!< FLASH Configuration Busy flag */
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos) /*!< FLASH Programming/erase operation suspended */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#define FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos) /*!< FLASH ECC correction on bank 1 */
|
||||
#define FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos) /*!< FLASH ECC detection on bank 1 */
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos) /*!< FLASH ECC correction on bank 2 */
|
||||
#define FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos) /*!< FLASH ECC detection on bank 2 */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#define FLASH_FLAG_ECCC FLASH_FLAG_ECCC1 /*!< FLASH ECC correction - legacy name for single bank */
|
||||
#define FLASH_FLAG_ECCD FLASH_FLAG_ECCD1 /*!< FLASH ECC detection - legacy name for single bank */
|
||||
/**
|
||||
|
|
@ -222,11 +222,11 @@ typedef struct
|
|||
#define FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos) /*!< Error Interrupt source */
|
||||
#if defined(FLASH_PCROP_SUPPORT)
|
||||
#define FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos) /*!< PCROP Read Error Interrupt source*/
|
||||
#endif
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
#define FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction on Bank 1 Interrupt source */
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos) /*!< ECC Correction on Bank 2 Interrupt source */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#define FLASH_IT_ECCC FLASH_IT_ECCC1 /*!< ECC Correction - legacy name for single bank */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -246,7 +246,7 @@ typedef struct
|
|||
#define HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR
|
||||
#if defined(FLASH_PCROP_SUPPORT)
|
||||
#define HAL_FLASH_ERROR_RD FLASH_SR_RDERR
|
||||
#endif
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
#define HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR
|
||||
#define HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD
|
||||
/**
|
||||
|
|
@ -268,7 +268,7 @@ typedef struct
|
|||
#define FLASH_BANK_1 FLASH_CR_MER1 /*!< Bank 1 */
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define FLASH_BANK_2 FLASH_CR_MER2 /*!< Bank 2 */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -291,17 +291,17 @@ typedef struct
|
|||
#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */
|
||||
#if defined(FLASH_PCROP_SUPPORT)
|
||||
#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */
|
||||
#endif
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
#define OPTIONBYTE_SEC 0x00000010U /*!< SEC option byte configuration */
|
||||
#endif
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
|
||||
#if defined(FLASH_PCROP_SUPPORT) && defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
|
||||
OPTIONBYTE_PCROP | OPTIONBYTE_SEC) /*!< All option byte configuration */
|
||||
#else
|
||||
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER) /*!< All option byte configuration */
|
||||
#endif
|
||||
#endif /* FLASH_PCROP_SUPPORT && FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -314,7 +314,7 @@ typedef struct
|
|||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define OB_WRPAREA_ZONE2_A 0x00000004U /*!< Flash Bank 2 Zone A */
|
||||
#define OB_WRPAREA_ZONE2_B 0x00000008U /*!< Flash Bank 2 Zone B */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -336,12 +336,12 @@ typedef struct
|
|||
#if defined(PWR_BOR_SUPPORT)
|
||||
#define OB_USER_BOR_EN FLASH_OPTR_BOR_EN /*!< BOR reset enable */
|
||||
#define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV) /*!< BOR reset Level */
|
||||
#endif
|
||||
#endif /* PWR_BOR_SUPPORT */
|
||||
#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */
|
||||
#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */
|
||||
#if defined(PWR_SHDW_SUPPORT)
|
||||
#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */
|
||||
#endif
|
||||
#endif /* PWR_SHDW_SUPPORT */
|
||||
#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */
|
||||
#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */
|
||||
#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */
|
||||
|
|
@ -349,17 +349,17 @@ typedef struct
|
|||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK /*!< Swap bank memory addresses */
|
||||
#define OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK /*!< Select single or dual bank (depending of device memory size) */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#define OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity check control */
|
||||
#define OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL /*!< Boot Selection */
|
||||
#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< nBoot1 configuration */
|
||||
#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBoot0 configuration */
|
||||
#if defined(GPIO_NRST_CONFIG_SUPPORT)
|
||||
#define OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE /*!< Reset pin configuration */
|
||||
#endif
|
||||
#endif /* GPIO_NRST_CONFIG_SUPPORT */
|
||||
#if defined(FLASH_OPTR_IRHEN)
|
||||
#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */
|
||||
#endif
|
||||
#endif /* FLASH_OPTR_IRHEN */
|
||||
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT)
|
||||
|
|
@ -371,12 +371,12 @@ typedef struct
|
|||
OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */
|
||||
#else
|
||||
#define OB_USER_ALL ( OB_USER_nRST_STOP | \
|
||||
OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \
|
||||
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \
|
||||
OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \
|
||||
OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \
|
||||
OB_USER_nBOOT0) /*!< all option bits */
|
||||
#endif
|
||||
OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \
|
||||
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \
|
||||
OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \
|
||||
OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \
|
||||
OB_USER_nBOOT0) /*!< all option bits */
|
||||
#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */
|
||||
#else
|
||||
#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT)
|
||||
#define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_nRST_STOP | \
|
||||
|
|
@ -386,12 +386,12 @@ typedef struct
|
|||
OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */
|
||||
#else
|
||||
#define OB_USER_ALL ( OB_USER_nRST_STOP | \
|
||||
OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \
|
||||
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \
|
||||
OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \
|
||||
OB_USER_nBOOT0) /*!< all option bits */
|
||||
#endif
|
||||
#endif
|
||||
OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \
|
||||
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \
|
||||
OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \
|
||||
OB_USER_nBOOT0) /*!< all option bits */
|
||||
#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -420,7 +420,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* PWR_BOR_SUPPORT */
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
|
||||
* @{
|
||||
|
|
@ -449,7 +449,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* PWR_SHDW_SUPPORT */
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
|
||||
* @{
|
||||
|
|
@ -505,7 +505,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity
|
||||
* @{
|
||||
|
|
@ -553,7 +553,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* GPIO_NRST_CONFIG_SUPPORT */
|
||||
|
||||
#if defined(FLASH_OPTR_IRHEN)
|
||||
/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit
|
||||
|
|
@ -564,7 +564,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* FLASH_OPTR_IRHEN */
|
||||
|
||||
#if defined(FLASH_PCROP_SUPPORT)
|
||||
/** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE
|
||||
|
|
@ -575,7 +575,7 @@ typedef struct
|
|||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define OB_PCROP_ZONE2_A 0x00000004U /*!< PCROP Bank 2 Zone A */
|
||||
#define OB_PCROP_ZONE2_B 0x00000008U /*!< PCROP Bank 2 Zone B */
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -591,7 +591,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
/** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock
|
||||
|
|
@ -602,7 +602,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -672,9 +672,9 @@ typedef struct
|
|||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
|
|
@ -698,7 +698,7 @@ typedef struct
|
|||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
|
||||
else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
|
||||
} while(0U)
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
|
|
@ -722,7 +722,7 @@ typedef struct
|
|||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
|
||||
else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
|
||||
} while(0U)
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FLASH flag is set or not.
|
||||
|
|
@ -754,15 +754,15 @@ typedef struct
|
|||
*/
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
|
||||
(READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
|
||||
((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
|
||||
(READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)))
|
||||
(READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
|
||||
((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
|
||||
(READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)))
|
||||
#else
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
|
||||
(READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
|
||||
(READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))
|
||||
#endif
|
||||
(READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
|
||||
(READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Clear the FLASH pending flags.
|
||||
|
|
@ -797,7 +797,7 @@ typedef struct
|
|||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \
|
||||
else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \
|
||||
} while(0U)
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -883,7 +883,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
|||
#define FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos) /*!< 0x02000000 */
|
||||
#define FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE))
|
||||
#define OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK))
|
||||
#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U) || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U)
|
||||
#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U)\
|
||||
|| ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U)
|
||||
#define FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U)) /*!< FLASH Bank Size. Divided by 2 if 2 Banks */
|
||||
#else /* FLASH_DBANK_SUPPORT */
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */
|
||||
|
|
@ -896,21 +897,21 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
|||
|
||||
#if defined(FLASH_PCROP_SUPPORT)
|
||||
#define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \
|
||||
FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \
|
||||
FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR | \
|
||||
FLASH_SR_OPTVERR) /*!< All SR error flags */
|
||||
FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \
|
||||
FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR | \
|
||||
FLASH_SR_OPTVERR) /*!< All SR error flags */
|
||||
#else
|
||||
#define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \
|
||||
FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \
|
||||
FLASH_SR_MISERR | FLASH_SR_FASTERR | \
|
||||
FLASH_SR_OPTVERR) /*!< All SR error flags */
|
||||
#endif
|
||||
FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \
|
||||
FLASH_SR_MISERR | FLASH_SR_FASTERR | \
|
||||
FLASH_SR_OPTVERR) /*!< All SR error flags */
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD)
|
||||
#else
|
||||
#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP)
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
/* Internal defines for HAL macro usage */
|
||||
#define FLASH_FLAG_REG_POS 16u
|
||||
|
|
@ -925,35 +926,42 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
|||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
|
||||
&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
|
||||
|
||||
#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL)))
|
||||
#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
|
||||
&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL)))
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
|
||||
#endif
|
||||
#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE))\
|
||||
&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL)))
|
||||
#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
|
||||
&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL)))
|
||||
|
||||
#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U) && ((__ADDRESS__) <= (0x1FFF7400U - 8UL)))
|
||||
#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U)\
|
||||
&& ((__ADDRESS__) <= (0x1FFF7400U - 8UL)))
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__)) || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__))\
|
||||
|| (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)))
|
||||
|
||||
#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL)))
|
||||
#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
|
||||
&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL)))
|
||||
|
||||
#define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB)
|
||||
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define IS_FLASH_BANK(__BANK__) \
|
||||
((FLASH_BANK_NB == 2U) ? \
|
||||
(((__BANK__) == FLASH_BANK_1) || \
|
||||
((__BANK__) == FLASH_BANK_2) || \
|
||||
((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \
|
||||
((__BANK__) == FLASH_BANK_1))
|
||||
((FLASH_BANK_NB == 2U) ? \
|
||||
(((__BANK__) == FLASH_BANK_1) || \
|
||||
((__BANK__) == FLASH_BANK_2) || \
|
||||
((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \
|
||||
((__BANK__) == FLASH_BANK_1))
|
||||
#else
|
||||
#define IS_FLASH_BANK(__BANK__) ((__BANK__) == FLASH_BANK_1)
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
|
||||
((__VALUE__) == FLASH_TYPEERASE_MASS))
|
||||
|
|
@ -962,17 +970,18 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
|||
((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
|
||||
|
||||
#define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \
|
||||
(((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U))
|
||||
(((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U))
|
||||
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define IS_OB_WRPAREA(__VALUE__) \
|
||||
((FLASH_BANK_NB == 2U) ? \
|
||||
(((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \
|
||||
((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \
|
||||
(((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)))
|
||||
((FLASH_BANK_NB == 2U) ? \
|
||||
(((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \
|
||||
((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \
|
||||
(((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)))
|
||||
#else
|
||||
#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B))
|
||||
#endif
|
||||
#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A)\
|
||||
|| ((__VALUE__) == OB_WRPAREA_ZONE_B))
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
#define IS_OB_RDP_LEVEL(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
|
||||
((__LEVEL__) == OB_RDP_LEVEL_1) ||\
|
||||
|
|
@ -986,20 +995,22 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
|||
#if defined(FLASH_PCROP_SUPPORT)
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
#define IS_OB_PCROP_CONFIG(__CONFIG__) \
|
||||
((FLASH_BANK_NB == 2U) ? \
|
||||
(((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \
|
||||
OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U): \
|
||||
(((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U))
|
||||
((FLASH_BANK_NB == 2U) ? \
|
||||
(((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \
|
||||
OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U): \
|
||||
(((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U))
|
||||
#else
|
||||
#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)
|
||||
#endif
|
||||
#endif
|
||||
#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__)\
|
||||
& ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE) || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH))
|
||||
#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE)\
|
||||
|| ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH))
|
||||
|
||||
#define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U))
|
||||
#endif
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
|
||||
((__LATENCY__) == FLASH_LATENCY_1) || \
|
||||
|
|
|
|||
|
|
@ -89,8 +89,8 @@
|
|||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_MassErase(uint32_t Banks);
|
||||
void FLASH_FlushCaches(void);
|
||||
static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
|
||||
|
|
@ -99,17 +99,19 @@ static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserCo
|
|||
static uint32_t FLASH_OB_GetRDP(void);
|
||||
static uint32_t FLASH_OB_GetUser(void);
|
||||
#if defined(FLASH_PCROP_SUPPORT)
|
||||
static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr);
|
||||
static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr,
|
||||
uint32_t PCROP1AEndAddr);
|
||||
static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr);
|
||||
static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr);
|
||||
static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr,
|
||||
uint32_t *PCROP1AEndAddr);
|
||||
static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr);
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr);
|
||||
static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr);
|
||||
static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr);
|
||||
static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr);
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2);
|
||||
|
|
@ -117,8 +119,8 @@ static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecS
|
|||
#else
|
||||
static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize);
|
||||
static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize);
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -129,8 +131,8 @@ static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecS
|
|||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
|
||||
* @brief Extended IO operation functions
|
||||
*
|
||||
* @brief Extended IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended programming operation functions #####
|
||||
|
|
@ -173,7 +175,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
|
|||
#if !defined(FLASH_DBANK_SUPPORT)
|
||||
/* For single bank product force Banks to Bank 1 */
|
||||
pEraseInit->Banks = FLASH_BANK_1;
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS)
|
||||
{
|
||||
|
|
@ -252,7 +254,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
|||
#if !defined(FLASH_DBANK_SUPPORT)
|
||||
/* For single bank product force Banks to Bank 1 */
|
||||
pEraseInit->Banks = FLASH_BANK_1;
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
/* Store Bank number */
|
||||
pFlash.Banks = pEraseInit->Banks;
|
||||
|
||||
|
|
@ -368,9 +370,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
|||
/* Configure the 2B Proprietary code readout protection */
|
||||
FLASH_OB_PCROP2BConfig(pOBInit->PCROP2BStartAddr, pOBInit->PCROP2BEndAddr);
|
||||
}
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
}
|
||||
#endif
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
/* Securable Memory Area Configuration */
|
||||
|
|
@ -382,9 +384,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
|||
#else
|
||||
/* Configure the securable memory area protection */
|
||||
FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize);
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
}
|
||||
#endif
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
|
@ -441,8 +443,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
|||
FLASH_OB_GetPCROP2A(&(pOBInit->PCROP2AStartAddr), &(pOBInit->PCROP2AEndAddr));
|
||||
FLASH_OB_GetPCROP2B(&(pOBInit->PCROP2BStartAddr), &(pOBInit->PCROP2BEndAddr));
|
||||
pOBInit->PCROPConfig |= (OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B);
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
|
|
@ -451,8 +453,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
|||
#else
|
||||
/* Get the Securable Memory Area protection */
|
||||
FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize));
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
}
|
||||
|
||||
#if defined(FLASH_ACR_DBG_SWEN)
|
||||
|
|
@ -537,12 +539,12 @@ void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks)
|
|||
else
|
||||
#else
|
||||
UNUSED(Banks);
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
{
|
||||
FLASH->CR |= FLASH_CR_SEC_PROT;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -598,7 +600,7 @@ void FLASH_PageErase(uint32_t Banks, uint32_t Page)
|
|||
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
/* Check if page has to be erased in bank 1 or 2 */
|
||||
if(Banks != FLASH_BANK_1)
|
||||
if (Banks != FLASH_BANK_1)
|
||||
{
|
||||
tmp |= FLASH_CR_BKER;
|
||||
}
|
||||
|
|
@ -606,7 +608,7 @@ void FLASH_PageErase(uint32_t Banks, uint32_t Page)
|
|||
{
|
||||
tmp &= ~FLASH_CR_BKER;
|
||||
}
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
|
||||
/* Set page number, Page Erase bit & Start bit */
|
||||
FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER));
|
||||
|
|
@ -674,7 +676,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32
|
|||
{
|
||||
FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset);
|
||||
}
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
else
|
||||
{
|
||||
FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset);
|
||||
|
|
@ -718,8 +720,8 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t
|
|||
*WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
|
||||
*WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos);
|
||||
}
|
||||
#endif
|
||||
else
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
else
|
||||
{
|
||||
*WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
|
||||
*WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos);
|
||||
|
|
@ -862,7 +864,7 @@ static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAd
|
|||
ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AStartAddr));
|
||||
|
|
@ -931,7 +933,7 @@ static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEn
|
|||
ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BStartAddr));
|
||||
|
|
@ -973,7 +975,7 @@ static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAdd
|
|||
ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
{
|
||||
/* No Bank swap, bank 1 read only protection is on first half of Flash */
|
||||
ropbase = FLASH_BASE;
|
||||
|
|
@ -1012,7 +1014,7 @@ static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEnd
|
|||
ropbase = (FLASH_BASE + FLASH_BANK_SIZE);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
{
|
||||
/* No Bank swap, bank 1 read only protection is on first half of Flash */
|
||||
ropbase = FLASH_BASE;
|
||||
|
|
@ -1193,8 +1195,8 @@ static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEnd
|
|||
*PCROP2BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET);
|
||||
*PCROP2BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_PCROP_SUPPORT */
|
||||
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
#if defined(FLASH_DBANK_SUPPORT)
|
||||
|
|
@ -1284,8 +1286,8 @@ static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize)
|
|||
*BootEntry = (secmem & FLASH_SECR_BOOT_LOCK);
|
||||
*SecSize = (secmem & FLASH_SECR_SEC_SIZE);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
#endif /* FLASH_DBANK_SUPPORT */
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ uint32_t HAL_FLASHEx_FlashEmptyCheck(void);
|
|||
void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
|
||||
#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
|
||||
void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks);
|
||||
#endif
|
||||
#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -123,17 +123,9 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
/** @addtogroup GPIO_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE (0x00000003u)
|
||||
#define EXTI_MODE (0x10000000u)
|
||||
#define GPIO_MODE_IT (0x00010000u)
|
||||
#define GPIO_MODE_EVT (0x00020000u)
|
||||
#define RISING_EDGE (0x00100000u)
|
||||
#define FALLING_EDGE (0x00200000u)
|
||||
#define GPIO_OUTPUT_TYPE (0x00000010u)
|
||||
|
||||
#define GPIO_NUMBER (16u)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -177,7 +169,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||||
|
|
@ -189,11 +180,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
||||
|
|
@ -203,18 +194,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
|
||||
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
||||
GPIOx->PUPDR = temp;
|
||||
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Check the Pull parameter */
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
|
|
@ -235,7 +232,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
||||
{
|
||||
temp = EXTI->EXTICR[position >> 2u];
|
||||
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
|
||||
|
|
@ -245,7 +242,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
|
|
@ -253,7 +250,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
|
||||
temp = EXTI->EMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
|
|
@ -262,7 +259,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
|
|
@ -270,7 +267,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
|
||||
temp = EXTI->FTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -107,26 +107,25 @@ typedef enum
|
|||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */
|
||||
#define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -135,10 +134,10 @@ typedef enum
|
|||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< High speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< Very high speed */
|
||||
#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -147,9 +146,9 @@ typedef enum
|
|||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */
|
||||
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -246,6 +245,31 @@ typedef enum
|
|||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_Pos 0u
|
||||
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4u
|
||||
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16u
|
||||
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20u
|
||||
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ extern "C" {
|
|||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0A)
|
||||
|
||||
#endif
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx */
|
||||
|
||||
#if defined (STM32G0B0xx)
|
||||
/*------------------------- STM32G0B0xx ------------------------*/
|
||||
|
|
@ -297,7 +297,7 @@ extern "C" {
|
|||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x09)
|
||||
|
||||
#endif
|
||||
#endif /* STM32G0B0xx */
|
||||
|
||||
|
||||
#if defined (STM32G081xx) || defined (STM32G071xx)
|
||||
|
|
@ -810,7 +810,7 @@ extern "C" {
|
|||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOD))? 3uL : 5uL)
|
||||
#endif
|
||||
#endif /* GPIOE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
|
@ -57,10 +57,9 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
//#ifdef HAL_HCD_MODULE_ENABLED //-> ERREUR DE COMPILATION
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#if defined (USB_DRD_FS)
|
||||
|
||||
|
||||
/** @defgroup HCD HCD
|
||||
* @brief HCD HAL module driver
|
||||
* @{
|
||||
|
|
@ -191,9 +190,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
|
|||
* This parameter can be a value from 0 to 255
|
||||
* @param speed Current device speed.
|
||||
* This parameter can be one of these values:
|
||||
* HCD_SPEED_HIGH High speed mode,
|
||||
* HCD_SPEED_FULL Full speed mode,
|
||||
* HCD_SPEED_LOW Low speed mode
|
||||
* HCD_DEVICE_SPEED_HIGH High speed mode,
|
||||
* HCD_DEVICE_SPEED_FULL Full speed mode,
|
||||
* HCD_DEVICE_SPEED_LOW Low speed mode
|
||||
* @param ep_type Endpoint Type.
|
||||
* This parameter can be one of these values:
|
||||
* USBH_EP_CONTROL Control type,
|
||||
|
|
@ -602,6 +601,12 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
uint8_t chnum;
|
||||
uint32_t epch_reg;
|
||||
|
||||
/* check if this is an USB pending IT */
|
||||
if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Port Change Detected (Connection/Disconnection) */
|
||||
if (__HAL_HCD_GET_FLAG(hhcd, USB_ISTR_DCON))
|
||||
{
|
||||
|
|
@ -1354,7 +1359,10 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
|
|||
/**
|
||||
* @brief Return the Host enumeration speed.
|
||||
* @param hhcd HCD handle
|
||||
* @retval Enumeration speed
|
||||
* @retval speed : Device speed after Host enumeration
|
||||
* This parameter can be one of these values:
|
||||
* @arg HCD_DEVICE_SPEED_FULL: Full speed mode
|
||||
* @arg HCD_DEVICE_SPEED_LOW: Low speed mode
|
||||
*/
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
|
||||
{
|
||||
|
|
@ -2492,8 +2500,8 @@ static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USB_DRD_FS */
|
||||
//#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
#endif /* defined (USB_DRD_FS) */
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
|
@ -29,7 +29,6 @@ extern "C" {
|
|||
#include "stm32g0xx_ll_usb.h"
|
||||
|
||||
#if defined (USB_DRD_FS)
|
||||
|
||||
/** @addtogroup STM32G0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -55,8 +54,7 @@ typedef enum
|
|||
HAL_HCD_STATE_TIMEOUT = 0x04
|
||||
} HCD_StateTypeDef;
|
||||
|
||||
|
||||
typedef USB_DRD_TypeDef HCD_TypeDef;
|
||||
typedef USB_DRD_TypeDef HCD_TypeDef;
|
||||
typedef USB_DRD_CfgTypeDef HCD_InitTypeDef;
|
||||
typedef USB_DRD_HCTypeDef HCD_HCTypeDef;
|
||||
typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef;
|
||||
|
|
@ -131,7 +129,16 @@ typedef struct
|
|||
*/
|
||||
#define HCD_SPEED_FULL USBH_FSLS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_FSLS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Device_Speed HCD Device Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_DEVICE_SPEED_HIGH 0U
|
||||
#define HCD_DEVICE_SPEED_FULL 1U
|
||||
#define HCD_DEVICE_SPEED_LOW 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -169,7 +176,8 @@ typedef struct
|
|||
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
|
||||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
|
|
@ -449,14 +457,35 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
|
|||
*/
|
||||
#define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
|
||||
#define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
|
||||
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
|
||||
#define HCD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT
|
||||
|
||||
/**
|
||||
* @brief gets counter of the rx buffer.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
|
|
@ -470,27 +499,59 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
|
|||
#define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
|
||||
#define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT
|
||||
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval None
|
||||
* @brief gets counter of the rx buffer0.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define HCD_GET_CH_DBUF0_CNT USB_DRD_GET_CHEP_DBUF0_CNT
|
||||
#define HCD_GET_CH_DBUF1_CNT USB_DRD_GET_CHEP_DBUF1_CNT
|
||||
__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief gets counter of the rx buffer1.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
#endif /* defined (USB_DRD_FS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -48,29 +48,30 @@ extern "C" {
|
|||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual */
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
|
|
@ -200,7 +201,8 @@ typedef struct __I2C_HandleTypeDef
|
|||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
|
|
@ -217,20 +219,32 @@ typedef struct __I2C_HandleTypeDef
|
|||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
|
@ -259,8 +273,11 @@ typedef enum
|
|||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
|
@ -440,14 +457,14 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
|
|||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
|
|
@ -495,7 +512,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
|
|||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
|
|
@ -521,7 +539,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
|
|||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
|
|
@ -540,26 +559,27 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
|
|||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -583,7 +603,8 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
|
|
@ -598,49 +619,72 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
|||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
|
|
@ -732,10 +776,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
|||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
|
@ -743,13 +792,20 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
|||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -71,17 +71,15 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @brief Filter Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
##### Filter Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
(+) Configure Wake Up Feature
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
|
|
@ -182,6 +180,23 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
|
|||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @brief WakeUp Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### WakeUp Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Wake Up Feature
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable I2C wakeup from Stop mode(s).
|
||||
|
|
@ -260,6 +275,23 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
|
|||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @brief Fast Mode Plus Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Fast Mode Plus Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability.
|
||||
|
|
@ -314,7 +346,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
|||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@ extern "C" {
|
|||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -68,7 +67,7 @@ extern "C" {
|
|||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
|
||||
#endif
|
||||
#endif /* SYSCFG_CFGR1_I2C3_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -78,24 +77,50 @@ extern "C" {
|
|||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
|
|
@ -111,7 +136,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
|
|
@ -125,9 +150,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -149,14 +171,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -356,7 +356,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
|||
#else
|
||||
/* Get the source clock value: based on System Clock value */
|
||||
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S1);
|
||||
#endif
|
||||
#endif /* RCC_PERIPHCLK_I2S2 */
|
||||
/* Compute the Real divider depending on the MCLK output state, with a floating point */
|
||||
if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
|
||||
{
|
||||
|
|
@ -755,7 +755,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @param Timeout Timeout duration
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
|
|
@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @param Timeout Timeout duration
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
|
|
@ -973,7 +973,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
|
@ -1037,7 +1037,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
|
||||
|
|
@ -1103,7 +1103,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
|
@ -1194,7 +1194,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
|
|||
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
||||
* configuration phase, the Size parameter means the number of 16-bit data length
|
||||
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
||||
* the Size parameter means the number of 16-bit data length.
|
||||
* the Size parameter means the number of 24-bit or 32-bit data length.
|
||||
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
||||
* between Master and Slave(example: audio streaming).
|
||||
* @retval HAL status
|
||||
|
|
|
|||
|
|
@ -40,7 +40,8 @@
|
|||
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
|
||||
(+++) Configure the DMA Tx/Rx channel.
|
||||
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer
|
||||
complete interrupt on the DMA Tx/Rx channel.
|
||||
|
||||
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
|
||||
the normal or low power mode and the clock prescaler in the hirda handle Init structure.
|
||||
|
|
@ -612,43 +613,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
|
||||
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
|
||||
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_TX_COMPLETE_CB_ID :
|
||||
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
|
||||
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
|
||||
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_RX_COMPLETE_CB_ID :
|
||||
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ERROR_CB_ID :
|
||||
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
|
||||
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
|
||||
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
|
||||
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
|
||||
AbortTransmitCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
|
||||
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
|
||||
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
|
||||
AbortReceiveCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_MSPINIT_CB_ID :
|
||||
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
|
||||
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
|
||||
break;
|
||||
|
||||
case HAL_IRDA_MSPDEINIT_CB_ID :
|
||||
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -771,13 +774,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
|
|||
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
|
||||
Errors are handled as follows :
|
||||
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
|
||||
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
|
||||
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
|
||||
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
|
||||
in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
|
||||
to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
|
||||
Transfer is kept ongoing on IRDA side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
|
||||
Error code is set to allow user to identify error type, and
|
||||
HAL_IRDA_ErrorCallback() user callback is executed.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
|
|
@ -1482,7 +1488,8 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
|
|||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
|
||||
{
|
||||
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
||||
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
|
||||
USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
||||
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Disable the IRDA DMA Tx request if enabled */
|
||||
|
|
@ -1680,7 +1687,8 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
|
|||
uint32_t abortcplt = 1U;
|
||||
|
||||
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
||||
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
|
||||
USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
||||
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
|
||||
|
|
@ -2338,7 +2346,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
|
|||
uint32_t tmpreg;
|
||||
IRDA_ClockSourceTypeDef clocksource;
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
|
||||
static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
|
||||
uint32_t pclk;
|
||||
|
||||
/* Check the communication parameters */
|
||||
|
|
@ -2475,7 +2483,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
|
|||
{
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||||
interrupts for the interrupt process */
|
||||
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
|
|
|
|||
|
|
@ -78,7 +78,8 @@ typedef struct
|
|||
|
||||
/**
|
||||
* @brief HAL IRDA State definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
|
||||
* @note HAL IRDA State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref IRDA_State_Definition).
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
|
|
@ -89,7 +90,7 @@ typedef struct
|
|||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
|
||||
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
|
@ -106,7 +107,7 @@ typedef struct
|
|||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
|
@ -247,7 +248,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
Value is allowed for RxState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
Value is result of combination (Or) between
|
||||
gState and RxState values */
|
||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
||||
|
|
@ -259,15 +261,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
|
||||
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -570,9 +572,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
|
@ -586,10 +593,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
|
@ -605,8 +616,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
||||
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
|
@ -620,9 +631,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
|||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
|
||||
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
|
||||
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
|
|
|
|||
|
|
@ -220,7 +220,7 @@ extern "C" {
|
|||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
||||
|
||||
/** @brief Compute the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
|
|
|
|||
|
|
@ -65,13 +65,13 @@
|
|||
(++) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(++) Wait for status flags to be reset.
|
||||
(++) Depending on window parameter:
|
||||
(+++) If Window Init parameter is same as Window register value,
|
||||
nothing more is done but reload counter value in order to exit
|
||||
function with exact time base.
|
||||
(+++) Else modify Window register. This will automatically reload
|
||||
watchdog counter.
|
||||
(++) Wait for status flags to be reset.
|
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
|
|
@ -121,11 +121,14 @@
|
|||
/* Status register needs up to 5 LSI clock periods divided by the clock
|
||||
prescaler to be updated. The number of LSI clock periods is upper-rounded to
|
||||
6 for the timeout value calculation.
|
||||
The timeout value is also calculated using the highest prescaler (256) and
|
||||
The timeout value is calculated using the highest prescaler (256) and
|
||||
the LSI_VALUE constant. The value of this constant can be changed by the user
|
||||
to take into account possible LSI clock period variations.
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
|
||||
The timeout value is multiplied by 1000 to be converted in milliseconds.
|
||||
LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT
|
||||
converted in milliseconds. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
|
||||
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -196,11 +199,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while (hiwdg->Instance->SR != 0x00u)
|
||||
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -223,6 +229,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -242,7 +249,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
|
|
@ -258,6 +264,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -87,7 +87,6 @@ typedef struct
|
|||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -100,7 +99,6 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -138,7 +136,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
|||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -188,10 +188,10 @@
|
|||
*/
|
||||
#if defined(LPTIM2)
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
|
||||
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
|
||||
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())
|
||||
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())
|
||||
#else
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()
|
||||
|
||||
|
|
@ -215,8 +215,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
|
@ -253,19 +253,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
|
||||
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
|
||||
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
|
||||
}
|
||||
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
|
||||
}
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
|
||||
{
|
||||
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
|
||||
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
|
||||
}
|
||||
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
|
||||
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
|
||||
|
|
@ -299,21 +297,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
/* Get the LPTIMx CFGR value */
|
||||
tmpcfgr = hlptim->Instance->CFGR;
|
||||
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
|
||||
}
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
|
||||
}
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
|
||||
{
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
|
||||
}
|
||||
|
||||
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
|
||||
/* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
|
||||
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
|
||||
LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
|
||||
|
||||
/* Set initialization parameters */
|
||||
|
|
@ -332,19 +327,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
|
|||
hlptim->Init.UltraLowPowerClock.SampleTime);
|
||||
}
|
||||
|
||||
/* Configure the active edge or edges used by the counter only if LPTIM is
|
||||
* clocked by an external clock source
|
||||
*/
|
||||
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
/* Configure LPTIM external clock polarity and digital filter */
|
||||
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
|
||||
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
|
||||
hlptim->Init.UltraLowPowerClock.SampleTime);
|
||||
}
|
||||
|
||||
/* Configure LPTIM external trigger */
|
||||
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
|
||||
{
|
||||
/* Enable External trigger and set the trigger source */
|
||||
tmpcfgr |= (hlptim->Init.Trigger.Source |
|
||||
hlptim->Init.Trigger.ActiveEdge);
|
||||
tmpcfgr |= (hlptim->Init.Trigger.Source |
|
||||
hlptim->Init.Trigger.ActiveEdge |
|
||||
hlptim->Init.Trigger.SampleTime);
|
||||
}
|
||||
|
||||
/* Write to LPTIMx CFGR */
|
||||
|
|
@ -458,8 +455,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
|
||||
* @brief Start-Stop operation functions.
|
||||
*
|
||||
* @brief Start-Stop operation functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM Start Stop operation functions #####
|
||||
|
|
@ -563,7 +560,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
|
|||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Change the TIM state*/
|
||||
/* Change the LPTIM state*/
|
||||
hlptim->State = HAL_LPTIM_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
|
|
@ -699,7 +696,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
|
|||
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
|
||||
}
|
||||
|
||||
/* Change the TIM state*/
|
||||
/* Change the LPTIM state*/
|
||||
hlptim->State = HAL_LPTIM_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
|
|
@ -786,7 +783,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
|
|||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Change the TIM state*/
|
||||
/* Change the LPTIM state*/
|
||||
hlptim->State = HAL_LPTIM_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
|
|
@ -922,7 +919,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
|
|||
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
|
||||
}
|
||||
|
||||
/* Change the TIM state*/
|
||||
/* Change the LPTIM state*/
|
||||
hlptim->State = HAL_LPTIM_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
|
|
@ -1009,7 +1006,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
|
|||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Change the TIM state*/
|
||||
/* Change the LPTIM state*/
|
||||
hlptim->State = HAL_LPTIM_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
|
|
@ -1145,7 +1142,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
|
|||
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
|
||||
}
|
||||
|
||||
/* Change the TIM state*/
|
||||
/* Change the LPTIM state*/
|
||||
hlptim->State = HAL_LPTIM_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
|
|
@ -1584,7 +1581,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
hlptim->State = HAL_LPTIM_STATE_BUSY;
|
||||
|
||||
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
/* Check if clock is prescaled */
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
|
||||
|
|
@ -1665,7 +1663,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
|
|||
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
|
||||
|
||||
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
|
||||
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
{
|
||||
/* Check if clock is prescaled */
|
||||
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
|
||||
|
|
@ -1756,8 +1755,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
|
||||
* @brief Read operation functions.
|
||||
*
|
||||
* @brief Read operation functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM Read operation functions #####
|
||||
|
|
@ -1814,8 +1813,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
|
||||
* @brief LPTIM IRQ handler.
|
||||
*
|
||||
* @brief LPTIM IRQ handler.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### LPTIM IRQ handler and callbacks #####
|
||||
|
|
@ -2205,39 +2204,48 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_LPTIM_MSPINIT_CB_ID :
|
||||
hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
|
||||
/* Legacy weak MspInit Callback */
|
||||
hlptim->MspInitCallback = HAL_LPTIM_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_MSPDEINIT_CB_ID :
|
||||
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
|
||||
/* Legacy weak Msp DeInit Callback */
|
||||
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_COMPARE_MATCH_CB_ID :
|
||||
hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */
|
||||
/* Legacy weak Compare match Callback */
|
||||
hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
|
||||
hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */
|
||||
/* Legacy weak Auto-reload match Callback */
|
||||
hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_TRIGGER_CB_ID :
|
||||
hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */
|
||||
/* Legacy weak External trigger event detection Callback */
|
||||
hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_COMPARE_WRITE_CB_ID :
|
||||
hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */
|
||||
/* Legacy weak Compare register write complete Callback */
|
||||
hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
|
||||
hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */
|
||||
/* Legacy weak Auto-reload register write complete Callback */
|
||||
hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_DIRECTION_UP_CB_ID :
|
||||
hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */
|
||||
/* Legacy weak Up-counting direction change Callback */
|
||||
hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
|
||||
hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */
|
||||
/* Legacy weak Down-counting direction change Callback */
|
||||
hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -2251,11 +2259,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_LPTIM_MSPINIT_CB_ID :
|
||||
hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
|
||||
/* Legacy weak MspInit Callback */
|
||||
hlptim->MspInitCallback = HAL_LPTIM_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_LPTIM_MSPDEINIT_CB_ID :
|
||||
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
|
||||
/* Legacy weak Msp DeInit Callback */
|
||||
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -2282,8 +2292,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
|
|||
*/
|
||||
|
||||
/** @defgroup LPTIM_Group5 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
|
@ -2330,13 +2340,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
|
|||
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
|
||||
{
|
||||
/* Reset the LPTIM callback to the legacy weak callbacks */
|
||||
lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */
|
||||
lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */
|
||||
lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */
|
||||
lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */
|
||||
lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
|
||||
lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */
|
||||
lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */
|
||||
lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
|
||||
lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
|
||||
lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
|
||||
lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
|
||||
lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
|
||||
lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
|
||||
lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
|
||||
}
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
||||
|
|
@ -2358,8 +2368,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
|
|||
{
|
||||
result = HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
|
||||
} while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -98,30 +98,30 @@ typedef struct
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
|
||||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
|
||||
|
||||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
|
||||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
|
||||
|
||||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
|
||||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
|
||||
|
||||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
||||
This parameter can be a value of @ref LPTIM_Output_Polarity */
|
||||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
||||
This parameter can be a value of @ref LPTIM_Output_Polarity */
|
||||
|
||||
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
|
||||
values is done immediately or after the end of current period.
|
||||
This parameter can be a value of @ref LPTIM_Updating_Mode */
|
||||
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
|
||||
values is done immediately or after the end of current period.
|
||||
This parameter can be a value of @ref LPTIM_Updating_Mode */
|
||||
|
||||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
||||
or each external event.
|
||||
This parameter can be a value of @ref LPTIM_Counter_Source */
|
||||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
||||
or each external event.
|
||||
This parameter can be a value of @ref LPTIM_Counter_Source */
|
||||
|
||||
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
|
||||
This parameter can be a value of @ref LPTIM_Input1_Source */
|
||||
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
|
||||
This parameter can be a value of @ref LPTIM_Input1_Source */
|
||||
|
||||
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
|
||||
Note: This parameter is used only for encoder feature so is used only
|
||||
for LPTIM1 instance.
|
||||
This parameter can be a value of @ref LPTIM_Input2_Source */
|
||||
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
|
||||
Note: This parameter is used only for encoder feature so is used only
|
||||
for LPTIM1 instance.
|
||||
This parameter can be a value of @ref LPTIM_Input2_Source */
|
||||
} LPTIM_InitTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -378,10 +378,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
|
@ -531,7 +531,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @retval Interrupt status.
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the LPTIM1 EXTI line in interrupt mode.
|
||||
|
|
@ -543,7 +544,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @brief Disable the LPTIM1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
|
||||
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1\
|
||||
&= ~(LPTIM_EXTI_LINE_LPTIM1))
|
||||
|
||||
|
||||
/**
|
||||
|
|
@ -556,7 +558,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @brief Disable the LPTIM1 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
|
||||
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1\
|
||||
&= ~(LPTIM_EXTI_LINE_LPTIM1))
|
||||
|
||||
/**
|
||||
* @brief Enable the LPTIM2 EXTI line in interrupt mode.
|
||||
|
|
@ -568,7 +571,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @brief Disable the LPTIM2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
|
||||
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1\
|
||||
&= ~(LPTIM_EXTI_LINE_LPTIM2))
|
||||
|
||||
|
||||
/**
|
||||
|
|
@ -581,7 +585,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
* @brief Disable the LPTIM2 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
|
||||
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1\
|
||||
&= ~(LPTIM_EXTI_LINE_LPTIM2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -593,9 +598,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
|
@ -608,9 +613,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
|
|
@ -664,9 +669,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
|
|
@ -676,9 +681,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
|
|
@ -693,7 +698,8 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
|
||||
pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
|
@ -701,9 +707,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
|
|||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Group5
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
|
|
@ -807,20 +813,20 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
|||
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == LPTIM2) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == LPTIM2) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
|
||||
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
|
||||
(((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
|
@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|||
|
||||
hpcd->USB_Address = 0U;
|
||||
hpcd->State = HAL_PCD_STATE_READY;
|
||||
|
||||
|
||||
/* Activate LPM */
|
||||
if (hpcd->Init.lpm_enable == 1U)
|
||||
{
|
||||
|
|
@ -695,7 +695,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
|||
|
||||
/**
|
||||
* @brief Unregister the USB PCD Iso OUT incomplete Callback
|
||||
* USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
|
||||
* USB PCD Iso OUT incomplete Callback is redirected
|
||||
* to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
@ -769,7 +770,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
|||
|
||||
/**
|
||||
* @brief Unregister the USB PCD Iso IN incomplete Callback
|
||||
* USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
|
||||
* USB PCD Iso IN incomplete Callback is redirected
|
||||
* to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
@ -1003,6 +1005,12 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
/* check if this is an USB pending IT */
|
||||
if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
|
||||
{
|
||||
/* servicing of the endpoint correct transfer interrupt */
|
||||
|
|
@ -1759,8 +1767,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
|
||||
if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
|
||||
{
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1847,9 +1858,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
/* clear int flag */
|
||||
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
|
||||
|
||||
/* Manage all non bulk transaction or Bulk Single Buffer Transaction */
|
||||
if ((ep->type != EP_TYPE_BULK) ||
|
||||
((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
|
||||
/* Manage all non bulk/isoc transaction Bulk Single Buffer Transaction */
|
||||
if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_CTRL) ||
|
||||
((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
|
||||
{
|
||||
/* multi-packet on the NON control IN endpoint */
|
||||
TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
||||
|
|
@ -1881,7 +1892,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
(void)USB_EPStartXfer(hpcd->Instance, ep);
|
||||
}
|
||||
}
|
||||
/* bulk in double buffer enable in case of transferLen> Ep_Mps */
|
||||
/* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */
|
||||
else
|
||||
{
|
||||
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
|
||||
|
|
@ -1927,7 +1938,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
|
|||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
|
||||
}
|
||||
|
||||
/* Check if Buffer1 is in blocked state which requires to toggle */
|
||||
/* Check if Buffer1 is in blocked sate which requires to toggle */
|
||||
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
|
||||
|
|
@ -2005,6 +2016,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
|
|||
/* Transfer is completed */
|
||||
if (ep->xfer_len == 0U)
|
||||
{
|
||||
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
||||
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
||||
|
||||
/* TX COMPLETE */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->DataInStageCallback(hpcd, ep->num);
|
||||
|
|
@ -2075,6 +2089,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
|
|||
/* Transfer is completed */
|
||||
if (ep->xfer_len == 0U)
|
||||
{
|
||||
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
||||
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
|
||||
|
||||
/* TX COMPLETE */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->DataInStageCallback(hpcd, ep->num);
|
||||
|
|
@ -2082,7 +2099,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
|
|||
HAL_PCD_DataInStageCallback(hpcd, ep->num);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
/*need to Free USB Buff*/
|
||||
/* need to Free USB Buff */
|
||||
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
|
||||
{
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
|
@ -190,8 +190,11 @@ typedef struct
|
|||
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
|
||||
&= (uint16_t)(~(__INTERRUPT__)))
|
||||
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE)
|
||||
|
|
@ -528,7 +531,26 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT
|
||||
#define PCD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT
|
||||
|
||||
/**
|
||||
* @brief gets counter of the rx buffer.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bEpNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(PCD_TypeDef *Instance, uint16_t bEpNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets addresses in a double buffer endpoint.
|
||||
|
|
@ -554,13 +576,44 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
|||
#define PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
* @brief gets counter of the rx buffer0.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bEpNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_CNT USB_DRD_GET_CHEP_DBUF0_CNT
|
||||
#define PCD_GET_EP_DBUF1_CNT USB_DRD_GET_CHEP_DBUF1_CNT
|
||||
__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(PCD_TypeDef *Instance, uint16_t bEpNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief gets counter of the rx buffer1.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bEpNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(PCD_TypeDef *Instance, uint16_t bEpNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
|
|
|
|||
|
|
@ -11,11 +11,11 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
|
|
@ -246,7 +246,7 @@ void HAL_PWR_DisableBkUpAccess(void)
|
|||
* @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
|
||||
* This parameter can be one of the following legacy values which set
|
||||
* the default polarity i.e. detection on high level (rising edge):
|
||||
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*),
|
||||
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*),
|
||||
* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
|
||||
* or one of the following value where the user can explicitly specify
|
||||
* the enabled pin and the chosen polarity:
|
||||
|
|
@ -323,11 +323,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
|||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Set Regulator parameter */
|
||||
if(Regulator != PWR_MAINREGULATOR_ON)
|
||||
if (Regulator != PWR_MAINREGULATOR_ON)
|
||||
{
|
||||
/* If in run mode, first move to low-power run mode.
|
||||
The system clock frequency must be below 2 MHz at this point. */
|
||||
if((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u)
|
||||
if ((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u)
|
||||
{
|
||||
HAL_PWREx_EnableLowPowerRunMode();
|
||||
}
|
||||
|
|
@ -335,7 +335,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
|||
else
|
||||
{
|
||||
/* If in low-power run mode at this point, exit it */
|
||||
if((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u)
|
||||
if ((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u)
|
||||
{
|
||||
if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
|
||||
{
|
||||
|
|
@ -348,7 +348,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
|||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
|
|
@ -417,7 +417,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
|||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select Stop mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
if (STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
|
|
@ -459,10 +459,10 @@ void HAL_PWR_EnterSTANDBYMode(void)
|
|||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
#endif /* __CC_ARM */
|
||||
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
|
|
|
|||
|
|
@ -6,11 +6,11 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32G0xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -58,31 +58,31 @@
|
|||
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP3 */
|
||||
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP5 */
|
||||
#define PWR_WAKEUP_PIN6 PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */
|
||||
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */
|
||||
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP3 */
|
||||
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP5*/
|
||||
#define PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */
|
||||
#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level detection) */
|
||||
#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level detection) */
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level detection) */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP3 */
|
||||
#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level detection) */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level detection) */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP5 */
|
||||
#define PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6) /*!< Wakeup pin 6 (with low level detection) */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -96,7 +96,7 @@
|
|||
#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */
|
||||
#if defined(PWR_SHDW_SUPPORT)
|
||||
#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */
|
||||
#endif
|
||||
#endif /* PWR_SHDW_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -142,11 +142,11 @@
|
|||
#define PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2) /*!< Wakeup event on wakeup pin 2 */
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3) /*!< Wakeup event on wakeup pin 3 */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP3 */
|
||||
#define PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4) /*!< Wakeup event on wakeup pin 4 */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5) /*!< Wakeup event on wakeup pin 5 */
|
||||
#endif
|
||||
#endif /* PWR_CR3_EWUP5 */
|
||||
#define PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6) /*!< Wakeup event on wakeup pin 6 */
|
||||
#define PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF) /*!< Wakeup event on all wakeup pin */
|
||||
#define PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF) /*!< Standby flag */
|
||||
|
|
@ -156,15 +156,15 @@
|
|||
#define PWR_FLAG_REGLPF (0x00020000u | PWR_SR2_REGLPF) /*!< Regulator Low Power flag */
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
#define PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO) /*!< Power Voltage Detector output */
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
#define PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB) /*!< Power Voltage Monitoring output */
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -206,8 +206,8 @@
|
|||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) (((__FLAG__) & 0x00010000u) ?\
|
||||
((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\
|
||||
((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)))
|
||||
((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\
|
||||
((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)))
|
||||
|
||||
/** @brief Clear a specific PWR flag.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
|
|
|
|||
|
|
@ -11,11 +11,11 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
|
|
@ -56,7 +56,7 @@
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
/** @defgroup PWREx_TimeOut_Value PWREx Flag Setting Time Out Value
|
||||
* @{
|
||||
|
|
@ -171,7 +171,7 @@ void HAL_PWREx_DisablePORMonitorSampling(void)
|
|||
{
|
||||
PWR->CR3 &= ~PWR_CR3_ENB_ULP;
|
||||
}
|
||||
#endif
|
||||
#endif /* PWR_CR3_ENB_ULP */
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
|
|
@ -201,24 +201,24 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
|||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
|
|
@ -245,7 +245,7 @@ void HAL_PWREx_DisablePVD(void)
|
|||
{
|
||||
CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
|
||||
}
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
/**
|
||||
|
|
@ -266,7 +266,7 @@ void HAL_PWREx_DisableVddUSB(void)
|
|||
{
|
||||
CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
|
||||
}
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
|
||||
#if defined(PWR_CR2_IOSV)
|
||||
/**
|
||||
|
|
@ -308,7 +308,7 @@ void HAL_PWREx_DisablePVMUSB(void)
|
|||
{
|
||||
CLEAR_BIT(PWR->CR2, PWR_PVM_USB);
|
||||
}
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
/**
|
||||
|
|
@ -344,24 +344,24 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
|
|||
__HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
|
||||
if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVM_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
|
||||
if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVM_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
|
||||
if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
|
||||
if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
|
|
@ -374,7 +374,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
|
|||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
/**
|
||||
* @brief Enable Internal Wake-up Line.
|
||||
* @retval None
|
||||
|
|
@ -422,35 +422,35 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
|
|||
switch (GPIO)
|
||||
{
|
||||
case PWR_GPIO_A:
|
||||
SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14));
|
||||
CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13));
|
||||
break;
|
||||
SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14));
|
||||
CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13));
|
||||
break;
|
||||
|
||||
case PWR_GPIO_B:
|
||||
SET_BIT(PWR->PUCRB, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRB, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PUCRB, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRB, GPIONumber);
|
||||
break;
|
||||
|
||||
case PWR_GPIO_C:
|
||||
SET_BIT(PWR->PUCRC, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRC, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PUCRC, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRC, GPIONumber);
|
||||
break;
|
||||
|
||||
case PWR_GPIO_D:
|
||||
SET_BIT(PWR->PUCRD, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRD, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PUCRD, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRD, GPIONumber);
|
||||
break;
|
||||
|
||||
#if defined(GPI0E)
|
||||
case PWR_GPIO_E:
|
||||
SET_BIT(PWR->PUCRE, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRE, GPIONumber);
|
||||
break;
|
||||
#endif
|
||||
SET_BIT(PWR->PUCRE, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRE, GPIONumber);
|
||||
break;
|
||||
#endif /* GPI0E */
|
||||
case PWR_GPIO_F:
|
||||
SET_BIT(PWR->PUCRF, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRF, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PUCRF, GPIONumber);
|
||||
CLEAR_BIT(PWR->PDCRF, GPIONumber);
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
|
|
@ -503,14 +503,14 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber
|
|||
case PWR_GPIO_E:
|
||||
CLEAR_BIT(PWR->PUCRE, GPIONumber);
|
||||
break;
|
||||
#endif
|
||||
#endif /* GPI0E */
|
||||
case PWR_GPIO_F:
|
||||
CLEAR_BIT(PWR->PUCRF, GPIONumber);
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
|
|
@ -546,35 +546,35 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe
|
|||
switch (GPIO)
|
||||
{
|
||||
case PWR_GPIO_A:
|
||||
SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13));
|
||||
CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14));
|
||||
break;
|
||||
SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13));
|
||||
CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14));
|
||||
break;
|
||||
|
||||
case PWR_GPIO_B:
|
||||
SET_BIT(PWR->PDCRB, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRB, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PDCRB, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRB, GPIONumber);
|
||||
break;
|
||||
|
||||
case PWR_GPIO_C:
|
||||
SET_BIT(PWR->PDCRC, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRC, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PDCRC, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRC, GPIONumber);
|
||||
break;
|
||||
|
||||
case PWR_GPIO_D:
|
||||
SET_BIT(PWR->PDCRD, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRD, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PDCRD, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRD, GPIONumber);
|
||||
break;
|
||||
|
||||
#if defined(GPIOE)
|
||||
case PWR_GPIO_E:
|
||||
SET_BIT(PWR->PDCRE, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRE, GPIONumber);
|
||||
break;
|
||||
#endif
|
||||
SET_BIT(PWR->PDCRE, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRE, GPIONumber);
|
||||
break;
|
||||
#endif /* GPI0E */
|
||||
case PWR_GPIO_F:
|
||||
SET_BIT(PWR->PDCRF, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRF, GPIONumber);
|
||||
break;
|
||||
SET_BIT(PWR->PDCRF, GPIONumber);
|
||||
CLEAR_BIT(PWR->PUCRF, GPIONumber);
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
|
|
@ -627,7 +627,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb
|
|||
case PWR_GPIO_E:
|
||||
CLEAR_BIT(PWR->PDCRE, GPIONumber);
|
||||
break;
|
||||
#endif
|
||||
#endif /* GPI0E */
|
||||
case PWR_GPIO_F:
|
||||
CLEAR_BIT(PWR->PDCRF, GPIONumber);
|
||||
break;
|
||||
|
|
@ -690,7 +690,7 @@ void HAL_PWREx_DisableSRAMRetention(void)
|
|||
{
|
||||
CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
|
||||
}
|
||||
#endif
|
||||
#endif /* PWR_CR3_RRS */
|
||||
|
||||
/**
|
||||
* @brief Enable Flash Power Down.
|
||||
|
|
@ -770,15 +770,15 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|||
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
|
||||
|
||||
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
|
||||
if(VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
||||
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
||||
{
|
||||
/* Set timeout value */
|
||||
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock ) / 1000000U) + 1U;
|
||||
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
|
||||
|
||||
/* Wait until VOSF is reset */
|
||||
while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
||||
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
||||
{
|
||||
if(wait_loop_index != 0U)
|
||||
if (wait_loop_index != 0U)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
|
|
@ -818,15 +818,15 @@ void HAL_PWREx_EnableLowPowerRunMode(void)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
|
||||
{
|
||||
uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock ) / 1000000U) + 1U;
|
||||
uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
|
||||
|
||||
/* Clear LPR bit */
|
||||
CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
|
||||
|
||||
/* Wait until REGLPF is reset */
|
||||
while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
|
||||
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
|
||||
{
|
||||
if(wait_loop_index != 0U)
|
||||
if (wait_loop_index != 0U)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
|
|
@ -869,12 +869,12 @@ void HAL_PWREx_EnterSHUTDOWNMode(void)
|
|||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
#endif /* __CC_ARM */
|
||||
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
#endif
|
||||
#endif /* PWR_SHDW_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT)
|
||||
/**
|
||||
|
|
@ -885,7 +885,7 @@ void HAL_PWREx_EnterSHUTDOWNMode(void)
|
|||
void HAL_PWREx_PVD_PVM_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR PVD exti Rising flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U)
|
||||
if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U)
|
||||
{
|
||||
/* Clear PVD exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG();
|
||||
|
|
@ -895,7 +895,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
|
|||
}
|
||||
|
||||
/* Check PWR exti fallling flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U)
|
||||
if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U)
|
||||
{
|
||||
/* Clear PVD exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG();
|
||||
|
|
@ -903,9 +903,9 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
|
|||
/* PWR PVD interrupt falling user callback */
|
||||
HAL_PWREx_PVD_PVM_Falling_Callback();
|
||||
}
|
||||
|
||||
|
||||
/* Check PWR PVM exti Rising flag */
|
||||
if(__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U)
|
||||
if (__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U)
|
||||
{
|
||||
/* Clear PVM exti pending bit */
|
||||
__HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG();
|
||||
|
|
@ -915,7 +915,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
|
|||
}
|
||||
|
||||
/* Check PWR PVM exti fallling flag */
|
||||
if(__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U)
|
||||
if (__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U)
|
||||
{
|
||||
/* Clear PVM exti pending bit */
|
||||
__HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG();
|
||||
|
|
@ -955,7 +955,7 @@ __weak void HAL_PWREx_PVD_PVM_Falling_Callback(void)
|
|||
void HAL_PWREx_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti Rising flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U)
|
||||
if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U)
|
||||
{
|
||||
/* Clear PVD exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG();
|
||||
|
|
@ -965,7 +965,7 @@ void HAL_PWREx_PVD_IRQHandler(void)
|
|||
}
|
||||
|
||||
/* Check PWR exti fallling flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U)
|
||||
if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U)
|
||||
{
|
||||
/* Clear PVD exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG();
|
||||
|
|
@ -997,7 +997,7 @@ __weak void HAL_PWREx_PVD_Falling_Callback(void)
|
|||
*/
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -6,11 +6,11 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32G0xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -54,8 +54,8 @@ typedef struct
|
|||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_PVM_Mode. */
|
||||
}PWR_PVMTypeDef;
|
||||
#endif
|
||||
} PWR_PVMTypeDef;
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT)
|
||||
/**
|
||||
|
|
@ -69,8 +69,8 @@ typedef struct
|
|||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode. */
|
||||
}PWR_PVDTypeDef;
|
||||
#endif
|
||||
} PWR_PVDTypeDef;
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -139,7 +139,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
|
||||
|
|
@ -177,7 +177,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
|
||||
* @{
|
||||
|
|
@ -221,7 +221,7 @@ typedef struct
|
|||
#define PWR_GPIO_D (0x00000003u) /*!< GPIO port D */
|
||||
#if defined (GPIOE)
|
||||
#define PWR_GPIO_E (0x00000004u) /*!< GPIO port E */
|
||||
#endif
|
||||
#endif /* GPIOE */
|
||||
#define PWR_GPIO_F (0x00000005u) /*!< GPIO port F */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -258,7 +258,7 @@ typedef struct
|
|||
*/
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
#define PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB) /*!< USB Peripheral Voltage Monitoring output */
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -369,7 +369,7 @@ typedef struct
|
|||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD)
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
/**
|
||||
|
|
@ -469,7 +469,7 @@ typedef struct
|
|||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM)
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -516,7 +516,7 @@ typedef struct
|
|||
((__GPIO__) == PWR_GPIO_C) || \
|
||||
((__GPIO__) == PWR_GPIO_D) || \
|
||||
((__GPIO__) == PWR_GPIO_F))
|
||||
#endif
|
||||
#endif /* GPIOE */
|
||||
|
||||
#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \
|
||||
(((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u))
|
||||
|
|
@ -534,7 +534,7 @@ typedef struct
|
|||
((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB)
|
||||
|
|
@ -546,7 +546,7 @@ typedef struct
|
|||
((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -566,7 +566,7 @@ void HAL_PWREx_DisableBatteryCharging(void);
|
|||
#if defined(PWR_CR3_ENB_ULP)
|
||||
void HAL_PWREx_EnablePORMonitorSampling(void);
|
||||
void HAL_PWREx_DisablePORMonitorSampling(void);
|
||||
#endif
|
||||
#endif /* PWR_CR3_ENB_ULP */
|
||||
void HAL_PWREx_EnableInternalWakeUpLine(void);
|
||||
void HAL_PWREx_DisableInternalWakeUpLine(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
||||
|
|
@ -578,7 +578,7 @@ void HAL_PWREx_DisablePullUpPullDownConfig(void);
|
|||
#if defined(PWR_CR3_RRS)
|
||||
void HAL_PWREx_EnableSRAMRetention(void);
|
||||
void HAL_PWREx_DisableSRAMRetention(void);
|
||||
#endif
|
||||
#endif /* PWR_CR3_RRS */
|
||||
void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
|
||||
void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||
|
|
@ -588,7 +588,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
|||
HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWREx_EnablePVD(void);
|
||||
void HAL_PWREx_DisablePVD(void);
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT */
|
||||
#if defined(PWR_PVM_SUPPORT)
|
||||
/* Power voltage monitoring configuration functions ***************************/
|
||||
void HAL_PWREx_EnableVddIO2(void);
|
||||
|
|
@ -598,14 +598,14 @@ void HAL_PWREx_DisableVddUSB(void);
|
|||
void HAL_PWREx_EnablePVMUSB(void);
|
||||
void HAL_PWREx_DisablePVMUSB(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
|
||||
#endif
|
||||
#endif /* PWR_PVM_SUPPORT */
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWREx_EnableLowPowerRunMode(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
|
||||
#if defined(PWR_SHDW_SUPPORT)
|
||||
void HAL_PWREx_EnterSHUTDOWNMode(void);
|
||||
#endif
|
||||
#endif /* PWR_SHDW_SUPPORT */
|
||||
|
||||
#if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT)
|
||||
void HAL_PWREx_PVD_PVM_IRQHandler(void);
|
||||
|
|
@ -615,7 +615,7 @@ void HAL_PWREx_PVD_PVM_Falling_Callback(void);
|
|||
void HAL_PWREx_PVD_IRQHandler(void);
|
||||
void HAL_PWREx_PVD_Rising_Callback(void);
|
||||
void HAL_PWREx_PVD_Falling_Callback(void);
|
||||
#endif
|
||||
#endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@
|
|||
#endif /* RCC_MCO2_SUPPORT */
|
||||
|
||||
#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
|
||||
(MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
|
||||
(MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -334,7 +334,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
||||
|
||||
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
||||
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
|
||||
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
|
||||
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
|
||||
{
|
||||
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
||||
{
|
||||
|
|
@ -388,7 +389,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
|
||||
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
||||
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
||||
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
|
||||
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
|
||||
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
|
||||
{
|
||||
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
|
||||
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
||||
|
|
@ -991,7 +993,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
|
|||
* @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP clock selected as MCO1 source(*)
|
||||
* @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ clock selected as MCO1 source(*)
|
||||
* @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO1 source(*)
|
||||
* @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*)
|
||||
* @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*)
|
||||
* @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2(*)
|
||||
* @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source(*)
|
||||
* @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48(*)
|
||||
|
|
@ -1236,9 +1238,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|||
{
|
||||
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
|
||||
}
|
||||
|
||||
RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
|
||||
RCC_OscInitStruct->HSIDiv = ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos);
|
||||
RCC_OscInitStruct->HSIDiv = (RCC->CR & RCC_CR_HSIDIV);
|
||||
|
||||
/* Get the LSE configuration -----------------------------------------------*/
|
||||
if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
|
||||
|
|
@ -1417,6 +1418,25 @@ __weak void HAL_RCC_LSECSSCallback(void)
|
|||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get and clear reset flags
|
||||
* @note Once reset flags are retrieved, this API is clearing them in order
|
||||
* to isolate next reset reason.
|
||||
* @retval can be a combination of @ref RCC_Reset_Flag
|
||||
*/
|
||||
uint32_t HAL_RCC_GetResetSource(void)
|
||||
{
|
||||
uint32_t reset;
|
||||
|
||||
/* Get all reset flags */
|
||||
reset = RCC->CSR & RCC_RESET_FLAG_ALL;
|
||||
|
||||
/* Clear Reset flags */
|
||||
RCC->CSR |= RCC_CSR_RMVF;
|
||||
|
||||
return reset;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -107,7 +107,10 @@ extern "C" {
|
|||
((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_PLLSOURCE_HSE))
|
||||
|
||||
#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= RCC_PLLM_DIV8)
|
||||
#define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \
|
||||
((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \
|
||||
((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \
|
||||
((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8))
|
||||
|
||||
#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
|
||||
|
||||
|
|
@ -119,13 +122,14 @@ extern "C" {
|
|||
|
||||
#define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
|
||||
|
||||
#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
|
||||
#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\
|
||||
& RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
|
||||
|
||||
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
|
||||
|
||||
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
|
||||
|
|
@ -148,7 +152,7 @@ extern "C" {
|
|||
#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
|
||||
#endif /* RCC_MCO2_SUPPORT */
|
||||
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
||||
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
|
||||
|
|
@ -696,7 +700,7 @@ typedef struct
|
|||
#define RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLLPCLK selection as MCO2 source */
|
||||
#define RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0) /*!< PLLQCLK selection as MCO2 source */
|
||||
#define RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1) /*!< RTCCLK selection as MCO2 source */
|
||||
#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */
|
||||
#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -751,6 +755,11 @@ typedef struct
|
|||
#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
|
||||
#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
|
||||
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
/* Flags in the CR register */
|
||||
#define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
|
||||
/* Flags in the BDCR register */
|
||||
#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
|
||||
#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
|
||||
|
|
@ -765,11 +774,6 @@ typedef struct
|
|||
#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
|
||||
#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
|
||||
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
/* Flags in the CRRCR register */
|
||||
#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_RC48RDY_Pos) /*!< HSI48 Ready flag */
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -785,6 +789,23 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Reset_Flag Reset Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */
|
||||
#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */
|
||||
#define RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */
|
||||
#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */
|
||||
#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
|
||||
#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
|
||||
#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */
|
||||
#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
|
||||
RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
|
||||
RCC_RESET_FLAG_LPWR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -804,59 +825,59 @@ typedef struct
|
|||
*/
|
||||
|
||||
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(DMA2)
|
||||
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#endif /* DMA2 */
|
||||
|
||||
|
||||
#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(RNG)
|
||||
#define __HAL_RCC_RNG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* RNG */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
|
||||
|
|
@ -884,54 +905,54 @@ typedef struct
|
|||
*/
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(GPIOE)
|
||||
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* GPIOE */
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
|
||||
#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
|
||||
|
|
@ -955,275 +976,275 @@ typedef struct
|
|||
*/
|
||||
#if defined(TIM2)
|
||||
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* TIM2 */
|
||||
|
||||
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(TIM4)
|
||||
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* TIM4 */
|
||||
|
||||
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(CRS)
|
||||
#define __HAL_RCC_CRS_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* CRS */
|
||||
|
||||
#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#if defined(SPI3)
|
||||
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* SPI3 */
|
||||
|
||||
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_USART4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(USART5)
|
||||
#define __HAL_RCC_USART5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* USART5 */
|
||||
|
||||
#if defined(USART6)
|
||||
#define __HAL_RCC_USART6_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* USART6 */
|
||||
|
||||
#if defined(LPUART1)
|
||||
#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* LPUART1 */
|
||||
|
||||
#if defined(LPUART2)
|
||||
#define __HAL_RCC_LPUART2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* LPUART2 */
|
||||
|
||||
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(I2C3)
|
||||
#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* I2C3 */
|
||||
|
||||
#if defined(CEC)
|
||||
#define __HAL_RCC_CEC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* CEC */
|
||||
|
||||
#if defined(UCPD1)
|
||||
#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* UCPD1 */
|
||||
|
||||
#if defined(UCPD2)
|
||||
#define __HAL_RCC_UCPD2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* UCPD2 */
|
||||
|
||||
#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
|
||||
#define __HAL_RCC_USB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
|
||||
|
||||
#if defined(FDCAN1) || defined(FDCAN2)
|
||||
#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* FDCAN1 || FDCAN2 */
|
||||
|
||||
#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(DAC1)
|
||||
#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* DAC1 */
|
||||
|
||||
#if defined(LPTIM2)
|
||||
#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* LPTIM2 */
|
||||
|
||||
#if defined(LPTIM1)
|
||||
#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* LPTIM1 */
|
||||
|
||||
/**
|
||||
|
|
@ -1239,78 +1260,78 @@ typedef struct
|
|||
*/
|
||||
|
||||
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(TIM15)
|
||||
#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
#endif /* TIM15 */
|
||||
|
||||
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_ADC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
#if defined(TIM2)
|
||||
#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
|
||||
|
|
@ -2585,7 +2606,7 @@ typedef struct
|
|||
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
|
||||
* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
|
||||
|
|
@ -2734,18 +2755,18 @@ typedef struct
|
|||
MODIFY_REG(RCC->PLLCFGR, \
|
||||
(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
|
||||
RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \
|
||||
((uint32_t) (__PLLSOURCE__) | \
|
||||
(uint32_t) (__PLLM__) | \
|
||||
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
|
||||
(uint32_t) (__PLLP__) | \
|
||||
(uint32_t) (__PLLQ__) | \
|
||||
(uint32_t) (__PLLR__)))
|
||||
((uint32_t) (__PLLSOURCE__) | \
|
||||
(uint32_t) (__PLLM__) | \
|
||||
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
|
||||
(uint32_t) (__PLLP__) | \
|
||||
(uint32_t) (__PLLQ__) | \
|
||||
(uint32_t) (__PLLR__)))
|
||||
#else
|
||||
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \
|
||||
MODIFY_REG(RCC->PLLCFGR, \
|
||||
(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
|
||||
RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLR), \
|
||||
((uint32_t) (__PLLSOURCE__) | \
|
||||
((uint32_t) (__PLLSOURCE__) | \
|
||||
(uint32_t) (__PLLM__) | \
|
||||
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
|
||||
(uint32_t) (__PLLP__) | \
|
||||
|
|
@ -2866,7 +2887,7 @@ typedef struct
|
|||
* @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source
|
||||
@if STM32G0C1xx
|
||||
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
|
||||
@endif
|
||||
|
|
@ -2878,8 +2899,13 @@ typedef struct
|
|||
* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
|
||||
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
|
||||
* @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
|
||||
* @arg @ref RCC_MCODIV_64 MCO clock source is divided by 128
|
||||
* @arg @ref RCC_MCODIV_128 MCO clock source is divided by 256
|
||||
* @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
|
||||
* @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
|
||||
@if STM32G0C1xx
|
||||
* @arg @ref RCC_MCODIV_256 MCO clock source is divided by 256
|
||||
* @arg @ref RCC_MCODIV_512 MCO clock source is divided by 512
|
||||
* @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024
|
||||
@endif
|
||||
*/
|
||||
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
||||
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
|
||||
|
|
@ -3024,15 +3050,15 @@ typedef struct
|
|||
#if defined(RCC_HSI48_SUPPORT)
|
||||
#define __HAL_RCC_GET_FLAG(__FLAG__) \
|
||||
(((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
|
||||
((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \
|
||||
((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
|
||||
((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \
|
||||
((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \
|
||||
((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
|
||||
((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \
|
||||
(1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
|
||||
#else
|
||||
#define __HAL_RCC_GET_FLAG(__FLAG__) \
|
||||
(((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
|
||||
((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
|
||||
((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \
|
||||
((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
|
||||
((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \
|
||||
(1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
|
||||
|
|
@ -3080,6 +3106,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void);
|
|||
uint32_t HAL_RCC_GetPCLK1Freq(void);
|
||||
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
|
||||
uint32_t HAL_RCC_GetResetSource(void);
|
||||
/* LSE & HSE CSS NMI IRQ handler */
|
||||
void HAL_RCC_NMI_IRQHandler(void);
|
||||
/* User Callbacks in non blocking mode (IT mode) */
|
||||
|
|
|
|||
|
|
@ -419,7 +419,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
|
|||
}
|
||||
#endif /* RCC_CCIPR2_I2S2SEL */
|
||||
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
/*-------------------------- USB clock source configuration ---------------------*/
|
||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
||||
{
|
||||
|
|
@ -1528,8 +1528,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
|
|||
/* frequency error counter reached a zero value */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
|
||||
}
|
||||
}
|
||||
while (RCC_CRS_NONE == crsstatus);
|
||||
} while (RCC_CRS_NONE == crsstatus);
|
||||
|
||||
return crsstatus;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -611,8 +611,8 @@ typedef struct
|
|||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @brief Macro to configure the I2C1 clock (I2C1CLK).
|
||||
|
|
@ -623,7 +623,7 @@ typedef struct
|
|||
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
|
||||
*/
|
||||
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2C1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -641,7 +641,7 @@ typedef struct
|
|||
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
|
||||
*/
|
||||
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2C2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -662,10 +662,10 @@ typedef struct
|
|||
*/
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
#define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
|
||||
#else
|
||||
#define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__))
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
||||
/** @brief Macro to get the I2S1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -691,7 +691,7 @@ typedef struct
|
|||
* @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock
|
||||
*/
|
||||
#define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2S2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -713,7 +713,7 @@ typedef struct
|
|||
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
|
||||
*/
|
||||
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USART1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -735,7 +735,7 @@ typedef struct
|
|||
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
|
||||
*/
|
||||
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USART2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -758,7 +758,7 @@ typedef struct
|
|||
* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
|
||||
*/
|
||||
#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USART3 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -781,7 +781,7 @@ typedef struct
|
|||
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
||||
*/
|
||||
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the LPUART1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -804,7 +804,7 @@ typedef struct
|
|||
* @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock
|
||||
*/
|
||||
#define __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the LPUART2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -827,7 +827,7 @@ typedef struct
|
|||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
|
||||
*/
|
||||
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the LPTIM1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -850,7 +850,7 @@ typedef struct
|
|||
* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
|
||||
*/
|
||||
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the LPTIM2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -871,7 +871,7 @@ typedef struct
|
|||
* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
|
||||
*/
|
||||
#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the CEC clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -893,7 +893,7 @@ typedef struct
|
|||
* @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock
|
||||
*/
|
||||
#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the RNG clock.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -915,7 +915,7 @@ typedef struct
|
|||
* @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8
|
||||
*/
|
||||
#define __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__))
|
||||
|
||||
/** @brief Macro to get the RNG clock division factor.
|
||||
* @retval The division factor can be one of the following values:
|
||||
|
|
@ -935,7 +935,7 @@ typedef struct
|
|||
* @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock
|
||||
*/
|
||||
#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the ADC clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -953,7 +953,7 @@ typedef struct
|
|||
* @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock
|
||||
*/
|
||||
#define __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the TIM1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -971,7 +971,7 @@ typedef struct
|
|||
* @arg RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock
|
||||
*/
|
||||
#define __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the TIM15 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -991,7 +991,7 @@ typedef struct
|
|||
* (*) Feature not available on all devices
|
||||
*/
|
||||
#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USB clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -1011,7 +1011,7 @@ typedef struct
|
|||
* @arg RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock
|
||||
*/
|
||||
#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the FDCAN clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -1074,15 +1074,15 @@ typedef struct
|
|||
#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
|
||||
|
||||
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
|
||||
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
|
||||
} \
|
||||
} while(0)
|
||||
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified CRS flag is set or not.
|
||||
|
|
@ -1118,15 +1118,15 @@ typedef struct
|
|||
#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
|
||||
|
||||
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
|
||||
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, (__FLAG__)); \
|
||||
} \
|
||||
} while(0)
|
||||
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, (__FLAG__)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#endif /* CRS */
|
||||
|
||||
|
|
@ -1248,303 +1248,303 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
|||
#if defined(STM32G0C1xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
|
||||
#elif defined(STM32G0B1xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
|
||||
#elif defined(STM32G0B0xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
|
||||
|
||||
#elif defined(STM32G081xx)
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
#elif defined(STM32G071xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
|
||||
#elif defined(STM32G070xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
|
||||
#elif defined(STM32G061xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
|
||||
#elif defined(STM32G051xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15))
|
||||
|
||||
#elif defined(STM32G041xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
|
||||
|
||||
#elif defined(STM32G031xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
|
||||
|
||||
#elif defined(STM32G030xx) || defined(STM32G050xx)
|
||||
#elif defined(STM32G030xx) || defined(STM32G050xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
#endif /* STM32G0C1xx */
|
||||
|
||||
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
|
||||
|
||||
#if defined(RCC_CCIPR_USART2SEL)
|
||||
#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
|
||||
#endif /* RCC_CCIPR_USART2SEL */
|
||||
|
||||
#if defined(RCC_CCIPR_USART3SEL)
|
||||
#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
|
||||
#endif /* RCC_CCIPR_USART3SEL */
|
||||
|
||||
#if defined(LPUART1)
|
||||
#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
|
||||
#endif /* LPUART1 */
|
||||
|
||||
#if defined(LPUART2)
|
||||
#define IS_RCC_LPUART2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI))
|
||||
#endif /* LPUART2 */
|
||||
|
||||
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
|
||||
|
||||
#if defined(RCC_CCIPR_I2C2SEL)
|
||||
#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
|
||||
|
||||
#endif /* RCC_CCIPR_I2C2SEL */
|
||||
|
||||
#define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT))
|
||||
(((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT))
|
||||
|
||||
#if defined(RCC_CCIPR2_I2S2SEL)
|
||||
#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT))
|
||||
(((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT))
|
||||
#endif /* RCC_CCIPR2_I2S2SEL */
|
||||
|
||||
#if defined(RCC_CCIPR_LPTIM1SEL)
|
||||
#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
#endif /* RCC_CCIPR_LPTIM1SEL */
|
||||
|
||||
#if defined(RCC_CCIPR_LPTIM2SEL)
|
||||
#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \
|
||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
|
||||
(((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \
|
||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
|
||||
#endif /* RCC_CCIPR_LPTIM2SEL */
|
||||
|
||||
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC) || \
|
||||
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_ADCCLKSOURCE_HSI))
|
||||
(((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC) || \
|
||||
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_ADCCLKSOURCE_HSI))
|
||||
|
||||
#if defined(RNG)
|
||||
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
|
||||
((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8) || \
|
||||
((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
|
||||
(((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
|
||||
((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8) || \
|
||||
((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
|
||||
#define IS_RCC_RNGDIV(__DIV__) \
|
||||
(((__DIV__) == RCC_RNGCLK_DIV1) || \
|
||||
((__DIV__) == RCC_RNGCLK_DIV2) || \
|
||||
((__DIV__) == RCC_RNGCLK_DIV4) || \
|
||||
((__DIV__) == RCC_RNGCLK_DIV8))
|
||||
(((__DIV__) == RCC_RNGCLK_DIV1) || \
|
||||
((__DIV__) == RCC_RNGCLK_DIV2) || \
|
||||
((__DIV__) == RCC_RNGCLK_DIV4) || \
|
||||
((__DIV__) == RCC_RNGCLK_DIV8))
|
||||
#endif /* RNG */
|
||||
|
||||
#if defined(CEC)
|
||||
#define IS_RCC_CECCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \
|
||||
((__SOURCE__) == RCC_CECCLKSOURCE_LSE))
|
||||
(((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \
|
||||
((__SOURCE__) == RCC_CECCLKSOURCE_LSE))
|
||||
#endif /* CEC */
|
||||
|
||||
#if defined(FDCAN1) || defined(FDCAN2)
|
||||
#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \
|
||||
((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \
|
||||
((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
|
||||
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \
|
||||
((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \
|
||||
((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
|
||||
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
|
||||
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
|
||||
#else
|
||||
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
|
||||
(((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
|
||||
#if defined(RCC_CCIPR_TIM1SEL)
|
||||
#define IS_RCC_TIM1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1))
|
||||
(((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1))
|
||||
#endif /* RCC_CCIPR_TIM1SEL */
|
||||
|
||||
#if defined(RCC_CCIPR_TIM15SEL)
|
||||
#define IS_RCC_TIM15CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1))
|
||||
(((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1))
|
||||
#endif /* RCC_CCIPR_TIM15SEL */
|
||||
|
||||
#if defined(CRS)
|
||||
|
|
|
|||
|
|
@ -129,8 +129,8 @@
|
|||
*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group1
|
||||
* @brief Initialization and configuration functions
|
||||
*
|
||||
* @brief Initialization and configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and configuration functions #####
|
||||
|
|
@ -301,7 +301,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
|
||||
pRNG_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -318,44 +319,44 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
|
|||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_ERROR_CB_ID :
|
||||
hrng->ErrorCallback = pCallback;
|
||||
break;
|
||||
case HAL_RNG_ERROR_CB_ID :
|
||||
hrng->ErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_RNG_STATE_RESET == hrng->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -393,44 +394,44 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
|
|||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_ERROR_CB_ID :
|
||||
hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
case HAL_RNG_ERROR_CB_ID :
|
||||
hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_RNG_STATE_RESET == hrng->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -520,8 +521,8 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
|
|||
*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group2
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
|
@ -538,11 +539,11 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
|
|||
/**
|
||||
* @brief Generates a 32-bit random number.
|
||||
* @note This function checks value of RNG_FLAG_DRDY flag to know if valid
|
||||
* random number is available in the DR register (RNG_FLAG_DRDY flag set
|
||||
* random number is available in the DR register (RNG_FLAG_DRDY flag set
|
||||
* whenever a random number is available through the RNG_DR register).
|
||||
* After transitioning from 0 to 1 (random number available),
|
||||
* RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
|
||||
* four words from the RNG_DR register, i.e. further function calls
|
||||
* After transitioning from 0 to 1 (random number available),
|
||||
* RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
|
||||
* four words from the RNG_DR register, i.e. further function calls
|
||||
* will immediately return a new u32 random number (additional words are
|
||||
* available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
|
||||
* @note When no more random number data is available in DR register, RNG_FLAG_DRDY
|
||||
|
|
@ -575,11 +576,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
|
|||
{
|
||||
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
|
||||
{
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
return HAL_ERROR;
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
|
||||
{
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -693,6 +698,8 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
|
|||
|
||||
/* Clear the clock error flag */
|
||||
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check RNG data ready interrupt occurred */
|
||||
|
|
@ -738,7 +745,7 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
|
|||
* @note When RNG_FLAG_DRDY flag value is set, first random number has been read
|
||||
* from DR register in IRQ Handler and is provided as callback parameter.
|
||||
* Depending on valid data available in the conditioning output buffer,
|
||||
* additional words can be read by the application from DR register till
|
||||
* additional words can be read by the application from DR register till
|
||||
* DRDY bit remains high.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
|
|
@ -775,8 +782,8 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
|
|||
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group3
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
|
@ -804,7 +811,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
|
|||
* @brief Return the RNG handle error code.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure.
|
||||
* @retval RNG Error Code
|
||||
*/
|
||||
*/
|
||||
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Return RNG Error Code */
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
#define STM32G0xx_HAL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -81,7 +81,7 @@ typedef enum
|
|||
typedef struct __RNG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
{
|
||||
RNG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
|
@ -91,7 +91,7 @@ typedef struct
|
|||
|
||||
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< RNG Error code */
|
||||
__IO uint32_t ErrorCode; /*!< RNG Error code */
|
||||
|
||||
uint32_t RandomNumber; /*!< Last Generated RNG Data */
|
||||
|
||||
|
|
@ -171,14 +171,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
|
|||
/** @defgroup RNG_Error_Definition RNG Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
|
||||
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
|
||||
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
|
||||
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
|
||||
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
|
||||
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -204,7 +204,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
|
|||
} while(0U)
|
||||
#else
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
|
||||
#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG peripheral.
|
||||
|
|
@ -299,7 +299,8 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
|
||||
pRNG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
|
||||
|
|
@ -346,8 +347,8 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
|
|||
((IT) == RNG_IT_SEI))
|
||||
|
||||
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
|
||||
((FLAG) == RNG_FLAG_CECS) || \
|
||||
((FLAG) == RNG_FLAG_SECS))
|
||||
((FLAG) == RNG_FLAG_CECS) || \
|
||||
((FLAG) == RNG_FLAG_SECS))
|
||||
|
||||
/**
|
||||
* @brief Verify the RNG Clock Error Detection mode.
|
||||
|
|
|
|||
|
|
@ -274,7 +274,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
|||
hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
|
||||
#if defined(TAMP_CR1_TAMP3E)
|
||||
hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /*!< Legacy weak InternalTamper3EventCallback */
|
||||
hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; /*!< Legacy weak InternalTamper4EventCallback */
|
||||
hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /*!< Legacy weak InternalTamper5EventCallback */
|
||||
|
|
@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
|
|||
case HAL_RTC_TAMPER3_EVENT_CB_ID :
|
||||
hrtc->Tamper3EventCallback = pCallback;
|
||||
break;
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
|
||||
case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
|
||||
hrtc->InternalTamper3EventCallback = pCallback;
|
||||
|
|
@ -616,7 +616,7 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca
|
|||
case HAL_RTC_TAMPER3_EVENT_CB_ID :
|
||||
hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
|
||||
break;
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
|
||||
case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
|
||||
hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /* Legacy weak InternalTamper3EventCallback */
|
||||
|
|
@ -803,10 +803,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
|||
/* Set the RTC_TR register */
|
||||
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
|
||||
|
||||
/* Clear the bits to be configured */
|
||||
/* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
|
||||
|
||||
/* Configure the RTC_CR register */
|
||||
/* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
|
||||
|
||||
/* Exit Initialization mode */
|
||||
|
|
@ -1833,6 +1833,67 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value)
|
|||
return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Add one hour to the calendar in one single operation
|
||||
* without going through the initialization procedure.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Subtract one hour from the calendar in one
|
||||
* single operation without going through the initialization procedure.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Set the store operation bit.
|
||||
* @note It can be used by the software in order to memorize the DST status.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
SET_BIT(hrtc->Instance->CR, RTC_CR_BKP);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Clear the store operation bit.
|
||||
* @param hrtc RTC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Daylight Saving Time, Read the store operation bit.
|
||||
* @param hrtc RTC handle
|
||||
* @retval operation see RTC_StoreOperation_Definitions
|
||||
*/
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -112,12 +112,11 @@ typedef struct
|
|||
with [1 Sec / SecondFraction +1] granularity.
|
||||
This field will be used only by HAL_RTC_GetTime function */
|
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
|
||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit
|
||||
in CR register to store the operation.
|
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
|
||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -170,7 +169,7 @@ typedef struct
|
|||
typedef struct __RTC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
|
|
@ -197,7 +196,7 @@ typedef struct
|
|||
|
||||
#if defined(TAMP_CR1_TAMP3E)
|
||||
void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
|
||||
void (* InternalTamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Internal Tamper 3 Event callback */
|
||||
|
||||
|
|
@ -230,7 +229,7 @@ typedef enum
|
|||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
|
||||
#if defined(TAMP_CR1_TAMP3E)
|
||||
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U, /*!< RTC Internal Tamper 3 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, /*!< RTC Internal Tamper 4 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU, /*!< RTC Internal Tamper 5 Callback ID */
|
||||
|
|
@ -566,6 +565,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
|||
|
||||
/**
|
||||
* @brief Add 1 hour (summer time change).
|
||||
* @note This interface is deprecated.
|
||||
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __BKP__ Backup
|
||||
* This parameter can be:
|
||||
|
|
@ -583,6 +584,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
|||
|
||||
/**
|
||||
* @brief Subtract 1 hour (winter time change).
|
||||
* @note This interface is deprecated.
|
||||
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __BKP__ Backup
|
||||
* This parameter can be:
|
||||
|
|
@ -759,6 +762,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
|||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -251,12 +251,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
|
|||
/* Enable IT timestamp */
|
||||
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
|
||||
|
||||
/* RTC timestamp Interrupt Configuration: EXTI configuration */
|
||||
__HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* RTC timestamp Interrupt Configuration: EXTI configuration */
|
||||
__HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
|
||||
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
|
|
@ -1712,7 +1712,7 @@ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
|
|||
HAL_RTCEx_Tamper3EventCallback(hrtc);
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
}
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
|
||||
/* Check Internal Tamper3 status */
|
||||
if((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
|
||||
|
|
@ -1811,7 +1811,7 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
|
|||
the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
|
||||
/**
|
||||
* @brief Internal Tamper 3 callback.
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ typedef struct
|
|||
#define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E)
|
||||
#else
|
||||
#define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E)
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -316,7 +316,7 @@ typedef struct
|
|||
#define RTC_IT_TAMPALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE)
|
||||
#else
|
||||
#define RTC_IT_TAMPALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE)
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
|
||||
#define RTC_IT_INT_TAMP3 TAMP_IER_ITAMP3IE
|
||||
#define RTC_IT_INT_TAMP4 TAMP_IER_ITAMP4IE
|
||||
|
|
@ -338,7 +338,7 @@ typedef struct
|
|||
#define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3)
|
||||
#else
|
||||
#define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2)
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
#define RTC_FLAG_INT_TAMP3 TAMP_SR_ITAMP3F
|
||||
#define RTC_FLAG_INT_TAMP4 TAMP_SR_ITAMP4F
|
||||
#define RTC_FLAG_INT_TAMP5 TAMP_SR_ITAMP5F
|
||||
|
|
@ -985,7 +985,7 @@ void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
|||
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#if defined(TAMP_CR1_TAMP3E)
|
||||
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#endif
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
|
|
|
|||
|
|
@ -35,7 +35,8 @@
|
|||
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
|
||||
(+++) Configure the DMA Tx/Rx channel.
|
||||
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer complete
|
||||
interrupt on the DMA Tx/Rx channel.
|
||||
|
||||
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
|
||||
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
|
||||
|
|
@ -107,8 +108,8 @@
|
|||
allows the user to configure dynamically the driver callbacks.
|
||||
|
||||
[..]
|
||||
Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
|
||||
Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
|
||||
Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
|
||||
Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
|
||||
(+) TxCpltCallback : Tx Complete Callback.
|
||||
(+) RxCpltCallback : Rx Complete Callback.
|
||||
(+) ErrorCallback : Error Callback.
|
||||
|
|
@ -123,9 +124,9 @@
|
|||
and a pointer to the user callback function.
|
||||
|
||||
[..]
|
||||
Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
|
||||
Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
@ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TxCpltCallback : Tx Complete Callback.
|
||||
|
|
@ -140,13 +141,13 @@
|
|||
(+) MspDeInitCallback : SMARTCARD MspDeInit.
|
||||
|
||||
[..]
|
||||
By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
|
||||
By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
|
||||
all callbacks are set to the corresponding weak (surcharged) functions:
|
||||
examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
|
||||
examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
|
||||
and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
|
||||
reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
|
||||
and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
||||
[..]
|
||||
|
|
@ -155,8 +156,8 @@
|
|||
in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
|
||||
MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
|
||||
or @ref HAL_SMARTCARD_Init() function.
|
||||
using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
|
||||
or HAL_SMARTCARD_Init() function.
|
||||
|
||||
[..]
|
||||
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
|
||||
|
|
@ -198,23 +199,24 @@
|
|||
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
|
||||
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
|
||||
|
||||
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
|
||||
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
|
||||
USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
|
||||
USART_CR1_RE | USART_CR1_OVER8| \
|
||||
USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
|
||||
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
|
||||
USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
|
||||
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
|
||||
USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
|
||||
|
||||
#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
|
||||
USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
|
||||
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
|
||||
USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
|
||||
USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
|
||||
|
||||
#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
|
||||
#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
|
||||
|
||||
#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
|
||||
#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -483,7 +485,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
|
||||
pSMARTCARD_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -618,43 +621,45 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ERROR_CB_ID :
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
|
||||
AbortTransmitCpltCallback*/
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
|
||||
AbortReceiveCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
|
||||
hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
|
||||
hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
|
||||
hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
|
||||
hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_MSPINIT_CB_ID :
|
||||
hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
|
||||
hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
|
||||
break;
|
||||
|
||||
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
|
||||
hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -725,62 +730,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
|
|||
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
|
||||
|
||||
[..]
|
||||
(+) There are two modes of transfer:
|
||||
(++) Blocking mode: The communication is performed in polling mode.
|
||||
(#) There are two modes of transfer:
|
||||
(##) Blocking mode: The communication is performed in polling mode.
|
||||
The HAL status of all data processing is returned by the same function
|
||||
after finishing transfer.
|
||||
(++) Non-Blocking mode: The communication is performed using Interrupts
|
||||
(##) Non-Blocking mode: The communication is performed using Interrupts
|
||||
or DMA, the relevant API's return the HAL status.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
|
||||
using DMA mode.
|
||||
(++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
|
||||
(##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
|
||||
will be executed respectively at the end of the Transmit or Receive process
|
||||
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
|
||||
error is detected.
|
||||
|
||||
(+) Blocking mode APIs are :
|
||||
(++) HAL_SMARTCARD_Transmit()
|
||||
(++) HAL_SMARTCARD_Receive()
|
||||
(#) Blocking mode APIs are :
|
||||
(##) HAL_SMARTCARD_Transmit()
|
||||
(##) HAL_SMARTCARD_Receive()
|
||||
|
||||
(+) Non Blocking mode APIs with Interrupt are :
|
||||
(++) HAL_SMARTCARD_Transmit_IT()
|
||||
(++) HAL_SMARTCARD_Receive_IT()
|
||||
(++) HAL_SMARTCARD_IRQHandler()
|
||||
(#) Non Blocking mode APIs with Interrupt are :
|
||||
(##) HAL_SMARTCARD_Transmit_IT()
|
||||
(##) HAL_SMARTCARD_Receive_IT()
|
||||
(##) HAL_SMARTCARD_IRQHandler()
|
||||
|
||||
(+) Non Blocking mode functions with DMA are :
|
||||
(++) HAL_SMARTCARD_Transmit_DMA()
|
||||
(++) HAL_SMARTCARD_Receive_DMA()
|
||||
(#) Non Blocking mode functions with DMA are :
|
||||
(##) HAL_SMARTCARD_Transmit_DMA()
|
||||
(##) HAL_SMARTCARD_Receive_DMA()
|
||||
|
||||
(+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
|
||||
(++) HAL_SMARTCARD_TxCpltCallback()
|
||||
(++) HAL_SMARTCARD_RxCpltCallback()
|
||||
(++) HAL_SMARTCARD_ErrorCallback()
|
||||
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
|
||||
(##) HAL_SMARTCARD_TxCpltCallback()
|
||||
(##) HAL_SMARTCARD_RxCpltCallback()
|
||||
(##) HAL_SMARTCARD_ErrorCallback()
|
||||
|
||||
[..]
|
||||
(#) Non-Blocking mode transfers could be aborted using Abort API's :
|
||||
(++) HAL_SMARTCARD_Abort()
|
||||
(++) HAL_SMARTCARD_AbortTransmit()
|
||||
(++) HAL_SMARTCARD_AbortReceive()
|
||||
(++) HAL_SMARTCARD_Abort_IT()
|
||||
(++) HAL_SMARTCARD_AbortTransmit_IT()
|
||||
(++) HAL_SMARTCARD_AbortReceive_IT()
|
||||
(##) HAL_SMARTCARD_Abort()
|
||||
(##) HAL_SMARTCARD_AbortTransmit()
|
||||
(##) HAL_SMARTCARD_AbortReceive()
|
||||
(##) HAL_SMARTCARD_Abort_IT()
|
||||
(##) HAL_SMARTCARD_AbortTransmit_IT()
|
||||
(##) HAL_SMARTCARD_AbortReceive_IT()
|
||||
|
||||
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
|
||||
(++) HAL_SMARTCARD_AbortCpltCallback()
|
||||
(++) HAL_SMARTCARD_AbortTransmitCpltCallback()
|
||||
(++) HAL_SMARTCARD_AbortReceiveCpltCallback()
|
||||
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
|
||||
a set of Abort Complete Callbacks are provided:
|
||||
(##) HAL_SMARTCARD_AbortCpltCallback()
|
||||
(##) HAL_SMARTCARD_AbortTransmitCpltCallback()
|
||||
(##) HAL_SMARTCARD_AbortReceiveCpltCallback()
|
||||
|
||||
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
|
||||
Errors are handled as follows :
|
||||
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
|
||||
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
|
||||
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
|
||||
(##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
|
||||
to be evaluated by user : this concerns Frame Error,
|
||||
Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer,
|
||||
Error code is set to allow user to identify error type,
|
||||
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
|
||||
mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type,
|
||||
and HAL_SMARTCARD_ErrorCallback() user callback is executed.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
|
|
@ -828,7 +838,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
|
|||
the bidirectional line to detect a NACK signal in case of parity error.
|
||||
Therefore, the receiver block must be enabled as well (RE bit must be set). */
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
|
|
@ -855,8 +865,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
|
|||
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
|
||||
ptmpdata++;
|
||||
}
|
||||
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
|
||||
Timeout) != HAL_OK)
|
||||
if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
|
||||
tickstart, Timeout) != HAL_OK)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
|
@ -864,14 +874,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui
|
|||
/* Disable the Peripheral first to update mode */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
|
||||
for Transmit phase. Disable this receiver block. */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|
||||
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
|
||||
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
|
||||
|
|
@ -1001,7 +1011,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard,
|
|||
the bidirectional line to detect a NACK signal in case of parity error.
|
||||
Therefore, the receiver block must be enabled as well (RE bit must be set). */
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
|
|
@ -1158,7 +1168,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
the bidirectional line to detect a NACK signal in case of parity error.
|
||||
Therefore, the receiver block must be enabled as well (RE bit must be set). */
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
|
|
@ -1311,7 +1321,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard,
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
|
||||
ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1,
|
||||
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
|
||||
USART_CR1_EOBIE));
|
||||
|
|
@ -1373,8 +1384,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -1465,7 +1476,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar
|
|||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
|
||||
USART_CR1_EOBIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
|
||||
|
|
@ -1505,8 +1517,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -1533,14 +1545,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
{
|
||||
uint32_t abortcplt = 1U;
|
||||
|
||||
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
|
||||
ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1,
|
||||
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
|
||||
USART_CR1_EOBIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
|
||||
|
||||
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
|
||||
before any call to DMA Abort functions */
|
||||
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
|
||||
DMA Abort complete callbacks should be initialised before any call
|
||||
to DMA Abort functions */
|
||||
/* DMA Tx Handle is valid */
|
||||
if (hsmartcard->hdmatx != NULL)
|
||||
{
|
||||
|
|
@ -1634,8 +1648,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
|
||||
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -1767,7 +1781,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart
|
|||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
|
||||
USART_CR1_EOBIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
|
||||
|
|
@ -1806,8 +1821,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
|
||||
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -1832,8 +1847,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
|
||||
SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -2304,14 +2319,18 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
{
|
||||
/* Init the SMARTCARD Callback settings */
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
|
||||
hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
|
||||
hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
|
||||
hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
|
||||
AbortTransmitCpltCallback */
|
||||
hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
|
||||
AbortReceiveCpltCallback */
|
||||
hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
|
||||
RxFifoFullCallback */
|
||||
hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
|
||||
TxFifoEmptyCallback */
|
||||
|
||||
}
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
|
|
@ -2327,7 +2346,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
uint32_t tmpreg;
|
||||
SMARTCARD_ClockSourceTypeDef clocksource;
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
|
||||
static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
|
||||
uint32_t pclk;
|
||||
|
||||
/* Check the parameters */
|
||||
|
|
@ -2352,8 +2371,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
* Configure the Parity and Mode:
|
||||
* set PS bit according to hsmartcard->Init.Parity value
|
||||
* set TE and RE bits according to hsmartcard->Init.Mode value */
|
||||
tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
|
||||
tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode;
|
||||
tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
|
||||
((uint32_t)hsmartcard->Init.WordLength));
|
||||
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
||||
|
||||
/*-------------------------- USART CR2 Configuration -----------------------*/
|
||||
|
|
@ -2401,17 +2420,21 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
{
|
||||
case SMARTCARD_CLOCKSOURCE_PCLK1:
|
||||
pclk = HAL_RCC_GetPCLK1Freq();
|
||||
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
|
||||
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
break;
|
||||
case SMARTCARD_CLOCKSOURCE_HSI:
|
||||
tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
|
||||
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
break;
|
||||
case SMARTCARD_CLOCKSOURCE_SYSCLK:
|
||||
pclk = HAL_RCC_GetSysClockFreq();
|
||||
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
|
||||
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
break;
|
||||
case SMARTCARD_CLOCKSOURCE_LSE:
|
||||
tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
|
||||
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
|
||||
break;
|
||||
default:
|
||||
ret = HAL_ERROR;
|
||||
|
|
@ -2572,7 +2595,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
|
|||
{
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||||
interrupts for the interrupt process */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
|
|
@ -2766,8 +2790,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -2815,8 +2839,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
|
||||
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -2877,8 +2901,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Clear the Error flags in the ICR register */
|
||||
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
|
||||
SMARTCARD_CLEAR_EOBF);
|
||||
SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
|
||||
SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
|
||||
|
||||
/* Restore hsmartcard->RxState to Ready */
|
||||
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
|
||||
|
|
@ -2984,14 +3008,14 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
/* Disable the Peripheral first to update mode */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
&& (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
|
||||
for Transmit phase. Disable this receiver block. */
|
||||
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
|
||||
}
|
||||
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
|
||||
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
|| (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
|
||||
{
|
||||
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
|
||||
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
|
||||
|
|
|
|||
|
|
@ -52,7 +52,8 @@ typedef struct
|
|||
where usart_ker_ckpres is the USART input clock divided by a prescaler */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
|
||||
This parameter @ref SMARTCARD_Word_Length can only be
|
||||
set to 9 (8 data + 1 parity bits). */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits.
|
||||
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
|
||||
|
|
@ -76,13 +77,14 @@ typedef struct
|
|||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Last_Bit */
|
||||
|
||||
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
|
||||
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
|
||||
is selected. Selecting the single sample method increases
|
||||
the receiver tolerance to clock deviations. This parameter can be a value
|
||||
of @ref SMARTCARD_OneBit_Sampling. */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
|
||||
This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
|
||||
by 2 to give the division factor of the source clock frequency */
|
||||
This parameter can be any value from 0x01 to 0x1F. Prescaler value is
|
||||
multiplied by 2 to give the division factor of the source clock frequency */
|
||||
|
||||
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
|
||||
|
||||
|
|
@ -141,14 +143,16 @@ typedef struct
|
|||
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
|
||||
This parameter can be a value of @ref SMARTCARD_MSB_First */
|
||||
|
||||
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
|
||||
relevant flag is available) or once guard time period has elapsed.
|
||||
This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
|
||||
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
|
||||
relevant flag is available) or once guard time period has elapsed.
|
||||
This parameter can be a value
|
||||
of @ref SMARTCARDEx_Transmission_Completion_Indication. */
|
||||
} SMARTCARD_AdvFeatureInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMARTCARD State definition
|
||||
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
|
||||
* @note HAL SMARTCARD State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref SMARTCARD_State_Definition).
|
||||
* - gState contains SMARTCARD state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
|
|
@ -159,7 +163,7 @@ typedef struct
|
|||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
|
||||
* 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
|
@ -176,7 +180,7 @@ typedef struct
|
|||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
|
@ -215,7 +219,8 @@ typedef struct __SMARTCARD_HandleTypeDef
|
|||
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
|
||||
|
||||
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
|
||||
This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
|
||||
This parameter can be a value of
|
||||
@ref SMARTCARDEx_FIFO_mode. */
|
||||
|
||||
void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
|
||||
|
||||
|
|
@ -227,12 +232,14 @@ typedef struct __SMARTCARD_HandleTypeDef
|
|||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
|
||||
Handle management and also related to Tx operations.
|
||||
This parameter can be a value
|
||||
of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
This parameter can be a value
|
||||
of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
|
||||
|
||||
|
|
@ -311,23 +318,26 @@ typedef enum
|
|||
/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
|
||||
is allowed for gState and RxState */
|
||||
#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
|
||||
use. Value is allowed for gState
|
||||
and RxState */
|
||||
#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
|
||||
process is ongoing Not to be used for
|
||||
neither gState nor RxState.
|
||||
Value is result of combination (Or)
|
||||
between gState and RxState values */
|
||||
#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -335,15 +345,15 @@ typedef enum
|
|||
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
||||
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
|
||||
#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
|
||||
#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
|
||||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -663,7 +673,8 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
|
||||
* guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
|
|
@ -676,9 +687,16 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 |= (1UL <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 |= (1UL <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1UL <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified SmartCard interrupt.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
|
@ -688,7 +706,8 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
|
||||
* time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
|
|
@ -701,9 +720,16 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
|
||||
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
|
@ -713,7 +739,8 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
|
||||
* interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
|
|
@ -726,8 +753,10 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
||||
& ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
|
||||
(((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
|
||||
& SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
|
||||
? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
|
@ -737,7 +766,8 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
|
||||
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
|
||||
* interrupt (when interruption available)
|
||||
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
|
||||
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
|
||||
|
|
@ -750,9 +780,16 @@ typedef enum
|
|||
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 0x01U)?\
|
||||
(__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
|
||||
SMARTCARD_CR_POS) == 0x02U)?\
|
||||
(__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) &\
|
||||
(0x01UL << (((uint16_t)(__INTERRUPT__))\
|
||||
& SMARTCARD_IT_MASK))) != 0U)\
|
||||
? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
|
|
@ -817,162 +854,6 @@ typedef enum
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the SMARTCARD clock source.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif
|
||||
|
||||
/** @brief Check the Baud rate range.
|
||||
* @note The maximum Baud Rate is derived from the maximum clock on G0 (64 MHz)
|
||||
|
|
@ -1181,7 +1062,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
|||
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
|
||||
pSMARTCARD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
|
||||
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
|
||||
|
|
|
|||
|
|
@ -458,8 +458,8 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
uint8_t rx_fifo_threshold;
|
||||
uint8_t tx_fifo_threshold;
|
||||
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
|
||||
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
|
||||
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
|
||||
{
|
||||
|
|
@ -472,8 +472,10 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
|
|||
tx_fifo_depth = TX_FIFO_DEPTH;
|
||||
rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
||||
tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
|
||||
hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
|
||||
hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
|
||||
hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
|
||||
(uint16_t)denominator[tx_fifo_threshold];
|
||||
hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
|
||||
(uint16_t)denominator[rx_fifo_threshold];
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -196,6 +196,162 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the SMARTCARD clock source.
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
||||
/** @brief Set the Transmission Completion flag
|
||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
||||
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
|
||||
|
|
|
|||
|
|
@ -44,35 +44,41 @@
|
|||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
|
||||
(++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
|
||||
add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
|
||||
(+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
|
||||
(++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
|
||||
add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
|
||||
(+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
|
||||
using @ref HAL_SMBUS_Master_Transmit_IT()
|
||||
(++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
|
||||
(+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
|
||||
using @ref HAL_SMBUS_Master_Receive_IT()
|
||||
(++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
|
||||
(+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
|
||||
(++) The associated previous transfer callback is called at the end of abort process
|
||||
(++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
|
||||
(++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
|
||||
(+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
|
||||
using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
|
||||
(++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
|
||||
add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
|
||||
(++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
|
||||
add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
|
||||
(+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
|
||||
(++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
|
||||
add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
|
||||
(+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
|
||||
(++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
|
||||
add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
|
||||
(+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
|
||||
(++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
|
||||
add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
|
||||
(++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and users can
|
||||
add their own code to check the Address Match Code and the transmission direction
|
||||
request by master/host (Write/Read).
|
||||
(++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
|
||||
(+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
|
||||
using @ref HAL_SMBUS_Slave_Transmit_IT()
|
||||
(++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
|
||||
(+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
|
||||
using @ref HAL_SMBUS_Slave_Receive_IT()
|
||||
(++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
|
||||
(+) Enable/Disable the SMBUS alert mode using
|
||||
@ref HAL_SMBUS_EnableAlert_IT() or @ref HAL_SMBUS_DisableAlert_IT()
|
||||
(++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and users can
|
||||
add their own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
|
||||
to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
|
||||
(+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
|
||||
(+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
|
||||
add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
|
||||
(+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and users can
|
||||
add their own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
|
||||
to check the Error Code using function @ref HAL_SMBUS_GetError()
|
||||
|
||||
*** SMBUS HAL driver macros list ***
|
||||
|
|
@ -203,7 +209,8 @@
|
|||
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
|
||||
* @{
|
||||
*/
|
||||
static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
|
||||
static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
|
||||
FlagStatus Status, uint32_t Timeout);
|
||||
|
||||
static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
|
||||
static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
|
||||
|
|
@ -214,7 +221,8 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
|
|||
|
||||
static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
|
||||
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
|
||||
uint32_t Mode, uint32_t Request);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -226,8 +234,8 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
|
|||
*/
|
||||
|
||||
/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
|
@ -362,15 +370,20 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
|
|||
|
||||
/*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
|
||||
/* Configure SMBUSx: Dual mode and Own Address2 */
|
||||
hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
|
||||
hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
|
||||
(hsmbus->Init.OwnAddress2Masks << 8U));
|
||||
|
||||
/*---------------------------- SMBUSx CR1 Configuration ------------------------*/
|
||||
/* Configure SMBUSx: Generalcall and NoStretch mode */
|
||||
hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
|
||||
hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
|
||||
hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
|
||||
hsmbus->Init.AnalogFilter);
|
||||
|
||||
/* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
|
||||
if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
|
||||
&& ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
|
||||
/* Enable Slave Byte Control only in case of Packet Error Check is enabled
|
||||
and SMBUS Peripheral is set in Slave mode */
|
||||
if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
|
||||
((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
(hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
|
||||
{
|
||||
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
|
||||
}
|
||||
|
|
@ -579,7 +592,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
|
|||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
HAL_SMBUS_CallbackIDTypeDef CallbackID,
|
||||
pSMBUS_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -692,7 +707,8 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM
|
|||
* @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
HAL_SMBUS_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -787,7 +803,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_
|
|||
* @param pCallback pointer to the Address Match Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
pSMBUS_AddrCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -858,8 +875,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
|
|||
*/
|
||||
|
||||
/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
|
|
@ -911,7 +928,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
|
|||
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
||||
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
|
|
@ -950,7 +968,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
|
|||
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
|
||||
SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
|
||||
SMBUS_GENERATE_START_WRITE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -960,9 +980,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
|
|||
/* Store current volatile XferOptions, misra rule */
|
||||
tmp = hsmbus->XferOptions;
|
||||
|
||||
if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
|
||||
if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
|
||||
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
|
||||
SMBUS_NO_STARTSTOP);
|
||||
}
|
||||
/* Else transfer direction change, so generate Restart with new transfer direction */
|
||||
else
|
||||
|
|
@ -971,7 +993,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
|
|||
SMBUS_ConvertOtherXferOptions(hsmbus);
|
||||
|
||||
/* Handle Transfer */
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
|
||||
hsmbus->XferOptions,
|
||||
SMBUS_GENERATE_START_WRITE);
|
||||
}
|
||||
|
||||
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
|
||||
|
|
@ -1010,7 +1034,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
|
|||
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
|
|
@ -1050,7 +1075,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
|
|||
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
|
||||
SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
|
||||
SMBUS_GENERATE_START_READ);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1060,9 +1087,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
|
|||
/* Store current volatile XferOptions, Misra rule */
|
||||
tmp = hsmbus->XferOptions;
|
||||
|
||||
if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
|
||||
if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
|
||||
(IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
|
||||
SMBUS_NO_STARTSTOP);
|
||||
}
|
||||
/* Else transfer direction change, so generate Restart with new transfer direction */
|
||||
else
|
||||
|
|
@ -1071,7 +1100,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
|
|||
SMBUS_ConvertOtherXferOptions(hsmbus);
|
||||
|
||||
/* Handle Transfer */
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
|
||||
hsmbus->XferOptions,
|
||||
SMBUS_GENERATE_START_READ);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1165,7 +1196,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_
|
|||
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
|
@ -1213,12 +1245,15 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
|
|||
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
|
||||
SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
|
||||
SMBUS_NO_STARTSTOP);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set NBYTE to transmit */
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
|
||||
SMBUS_NO_STARTSTOP);
|
||||
|
||||
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
|
||||
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
|
||||
|
|
@ -1259,7 +1294,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
|
|||
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
|
|
@ -1303,7 +1339,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
|
|||
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
|
||||
if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
|
||||
SMBUS_NO_STARTSTOP);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1417,7 +1454,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
|
|
@ -1526,8 +1564,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
|
|||
|
||||
/* Increment Trials */
|
||||
SMBUS_Trials++;
|
||||
}
|
||||
while (SMBUS_Trials < Trials);
|
||||
} while (SMBUS_Trials < Trials);
|
||||
|
||||
hsmbus->State = HAL_SMBUS_STATE_READY;
|
||||
|
||||
|
|
@ -1549,8 +1586,8 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
|
|||
*/
|
||||
|
||||
/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle SMBUS event interrupt request.
|
||||
|
|
@ -1566,7 +1603,13 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
|
||||
|
||||
/* SMBUS in mode Transmitter ---------------------------------------------------*/
|
||||
if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
|
||||
if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
|
||||
SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
|
||||
((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
|
||||
{
|
||||
/* Slave mode selected */
|
||||
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
|
||||
|
|
@ -1585,7 +1628,13 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* SMBUS in mode Receiver ----------------------------------------------------*/
|
||||
if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
|
||||
if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
|
||||
SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
|
||||
((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
|
||||
{
|
||||
/* Slave mode selected */
|
||||
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
|
||||
|
|
@ -1604,7 +1653,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* SMBUS in mode Listener Only --------------------------------------------------*/
|
||||
if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
|
||||
if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
|
||||
(SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
|
||||
(SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
|
||||
((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
|
||||
{
|
||||
if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
|
||||
{
|
||||
|
|
@ -1695,7 +1749,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
|
|||
* @param AddrMatchCode Address Match Code
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
|
||||
__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hsmbus);
|
||||
|
|
@ -1744,8 +1799,8 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
|
|||
*/
|
||||
|
||||
/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
|
|
@ -1771,11 +1826,11 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Return the SMBUS error code.
|
||||
* @brief Return the SMBUS error code.
|
||||
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified SMBUS.
|
||||
* @retval SMBUS Error Code
|
||||
*/
|
||||
* @retval SMBUS Error Code
|
||||
*/
|
||||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
|
||||
{
|
||||
return hsmbus->ErrorCode;
|
||||
|
|
@ -1790,7 +1845,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
|
||||
* @brief Data transfers Private functions
|
||||
* @brief Data transfers Private functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -1941,13 +1996,16 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t
|
|||
|
||||
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
|
||||
(SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
|
||||
SMBUS_NO_STARTSTOP);
|
||||
hsmbus->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
hsmbus->XferSize = hsmbus->XferCount;
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
|
||||
SMBUS_NO_STARTSTOP);
|
||||
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
|
||||
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
|
||||
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
|
||||
|
|
@ -2155,7 +2213,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
|
|||
HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
}
|
||||
else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
|
||||
else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
|
||||
(SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
|
||||
{
|
||||
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
|
||||
{
|
||||
|
|
@ -2198,7 +2257,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
|
|||
else
|
||||
{
|
||||
/* Set Reload for next Bytes */
|
||||
SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, 0, 1,
|
||||
SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
|
||||
SMBUS_NO_STARTSTOP);
|
||||
|
||||
/* Ack last Byte Read */
|
||||
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
|
||||
|
|
@ -2210,13 +2271,16 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
|
|||
{
|
||||
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
|
||||
(SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
|
||||
SMBUS_NO_STARTSTOP);
|
||||
hsmbus->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
hsmbus->XferSize = hsmbus->XferCount;
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
|
||||
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
|
||||
SMBUS_NO_STARTSTOP);
|
||||
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
|
||||
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
|
||||
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
|
||||
|
|
@ -2461,7 +2525,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
uint32_t tmperror;
|
||||
|
||||
/* SMBUS Bus error interrupt occurred ------------------------------------*/
|
||||
if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
|
||||
((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
{
|
||||
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
|
||||
|
||||
|
|
@ -2470,7 +2535,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
|
||||
if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
|
||||
((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
{
|
||||
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
|
||||
|
||||
|
|
@ -2479,7 +2545,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
|
||||
if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
|
||||
((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
{
|
||||
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
|
||||
|
||||
|
|
@ -2488,7 +2555,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
|
||||
if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
|
||||
((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
{
|
||||
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
|
||||
|
||||
|
|
@ -2497,7 +2565,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* SMBUS Alert error interrupt occurred -----------------------------------------------*/
|
||||
if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
|
||||
((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
{
|
||||
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
|
||||
|
||||
|
|
@ -2506,7 +2575,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
}
|
||||
|
||||
/* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
|
||||
if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
|
||||
((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
|
||||
{
|
||||
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
|
||||
|
||||
|
|
@ -2554,7 +2624,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
|
||||
static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
|
||||
FlagStatus Status, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
|
|
@ -2603,7 +2674,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu
|
|||
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
|
||||
* @retval None
|
||||
*/
|
||||
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
|
||||
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
|
||||
uint32_t Mode, uint32_t Request)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
|
||||
|
|
@ -2611,8 +2683,13 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
|
|||
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
||||
MODIFY_REG(hsmbus->Instance->CR2,
|
||||
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
||||
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
|
||||
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
|
||||
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
||||
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
||||
(uint32_t)Mode | (uint32_t)Request));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -48,42 +48,43 @@ extern "C" {
|
|||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
This parameter calculated by referring to SMBUS initialization section
|
||||
in Reference manual */
|
||||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
||||
This parameter can be a value of @ref SMBUS_Analog_Filter */
|
||||
This parameter can be a value of @ref SMBUS_Analog_Filter */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
|
||||
This parameter can be a value of @ref SMBUS_addressing_mode */
|
||||
This parameter can be a value of @ref SMBUS_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
|
||||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
|
||||
if dual addressing mode is selected
|
||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
|
||||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_nostretch_mode */
|
||||
This parameter can be a value of @ref SMBUS_nostretch_mode */
|
||||
|
||||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
|
||||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
|
||||
|
||||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
||||
This parameter can be a value of @ref SMBUS_peripheral_mode */
|
||||
This parameter can be a value of @ref SMBUS_peripheral_mode */
|
||||
|
||||
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
|
||||
(Enable bits and different timeout values)
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
(Enable bits and different timeout values)
|
||||
This parameter calculated by referring to SMBUS initialization section
|
||||
in Reference manual */
|
||||
} SMBUS_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -102,7 +103,7 @@ typedef struct
|
|||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
|
||||
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -121,7 +122,7 @@ typedef struct
|
|||
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
|
||||
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
|
|
@ -159,17 +160,26 @@ typedef struct
|
|||
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
|
||||
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
|
||||
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
|
||||
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Listen Complete callback */
|
||||
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Error callback */
|
||||
|
||||
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
|
||||
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< SMBUS Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
|
||||
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< SMBUS Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
} SMBUS_HandleTypeDef;
|
||||
|
|
@ -195,8 +205,11 @@ typedef enum
|
|||
/**
|
||||
* @brief HAL SMBUS Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
|
||||
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
|
||||
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
|
||||
/*!< pointer to an SMBUS callback function */
|
||||
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an SMBUS Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
|
@ -358,8 +371,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define SMBUS_IT_RXI I2C_CR1_RXIE
|
||||
#define SMBUS_IT_TXI I2C_CR1_TXIE
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
|
||||
SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
|
||||
SMBUS_IT_RXI)
|
||||
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
|
||||
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
|
||||
/**
|
||||
|
|
@ -407,14 +422,14 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
|
||||
#endif
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
|
|
@ -462,7 +477,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
*
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SMBUS flag is set or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
|
|
@ -488,7 +504,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define SMBUS_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
||||
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
|
|
@ -539,15 +557,15 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
*/
|
||||
|
||||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
||||
((MASK) == SMBUS_OA2_MASK01) || \
|
||||
|
|
@ -565,47 +583,58 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
|
||||
((PEC) == SMBUS_PEC_ENABLE))
|
||||
((PEC) == SMBUS_PEC_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
|
||||
SMBUS_RELOAD_MODE )))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
||||
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
|
||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
|
||||
I2C_CR1_PECEN)))
|
||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & \
|
||||
(I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
|
||||
(I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
|
||||
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
||||
|
|
@ -613,7 +642,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
||||
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
||||
|
||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
||||
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
||||
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
|
|
@ -623,14 +653,17 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Include SMBUS HAL Extended module */
|
||||
#include "stm32g0xx_hal_smbus_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
|
@ -642,10 +675,14 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
|
|||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
HAL_SMBUS_CallbackIDTypeDef CallbackID,
|
||||
pSMBUS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
HAL_SMBUS_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
|
||||
pSMBUS_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
|
@ -653,28 +690,33 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
||||
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
||||
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
|
@ -685,8 +727,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
||||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
|
@ -703,8 +745,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
|||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,152 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g0xx_hal_smbus_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief SMBUS Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of SMBUS Extended peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SMBUS peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the SMBUS interface for STM32G0xx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_SMBUSEx_EnableFastModePlus()
|
||||
(++) HAL_SMBUSEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32G0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUSEx SMBUSEx
|
||||
* @brief SMBUS Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the SMBUS fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref SMBUSEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled
|
||||
* only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be enabled
|
||||
* only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the SMBUS fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref SMBUSEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be disabled
|
||||
* only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be disabled
|
||||
* only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g0xx_hal_smbus_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SMBUS HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G0xx_HAL_SMBUS_EX_H
|
||||
#define STM32G0xx_HAL_SMBUS_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUSEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#define SMBUS_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */
|
||||
#define SMBUS_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */
|
||||
#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#if defined(SYSCFG_CFGR1_I2C3_FMP)
|
||||
#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#else
|
||||
#define SMBUS_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C3_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
|
||||
((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA9)) == SMBUS_FASTMODEPLUS_PA9) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA10)) == SMBUS_FASTMODEPLUS_PA10) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32g0xx_hal_smbus_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G0xx_HAL_SMBUS_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -987,6 +987,11 @@ error:
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
__IO uint8_t * ptmpreg8;
|
||||
__IO uint8_t tmpreg8 = 0;
|
||||
#endif /* USE_SPI_CRC */
|
||||
uint32_t tickstart;
|
||||
HAL_StatusTypeDef errorcode = HAL_OK;
|
||||
|
||||
|
|
@ -1153,12 +1158,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
|
|||
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
|
||||
{
|
||||
/* Read 16bit CRC */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the 8bit temporary pointer */
|
||||
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
||||
/* Read 8bit CRC */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
|
||||
if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
|
||||
{
|
||||
|
|
@ -1170,7 +1181,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
|
|||
goto error;
|
||||
}
|
||||
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1220,8 +1233,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
|
|||
HAL_SPI_StateTypeDef tmp_state;
|
||||
uint32_t tickstart;
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
uint32_t spi_cr1;
|
||||
uint32_t spi_cr2;
|
||||
__IO uint8_t * ptmpreg8;
|
||||
__IO uint8_t tmpreg8 = 0;
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
/* Variable used to alternate Rx and Tx during transfer */
|
||||
|
|
@ -1422,12 +1438,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
|
|||
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
|
||||
{
|
||||
/* Read 16bit CRC */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the 8bit temporary pointer */
|
||||
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
||||
/* Read 8bit CRC */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
|
||||
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
|
||||
{
|
||||
|
|
@ -1439,7 +1461,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
|
|||
goto error;
|
||||
}
|
||||
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2994,6 +3018,11 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
|
||||
uint32_t tickstart;
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
__IO uint8_t * ptmpreg8;
|
||||
__IO uint8_t tmpreg8 = 0;
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
/* Init tickstart for timeout management*/
|
||||
tickstart = HAL_GetTick();
|
||||
|
|
@ -3018,12 +3047,18 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
||||
{
|
||||
/* Read 16bit CRC */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the 8bit temporary pointer */
|
||||
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
||||
/* Read 8bit CRC */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
|
||||
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
|
||||
{
|
||||
|
|
@ -3033,7 +3068,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
||||
}
|
||||
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -3098,6 +3135,11 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
|
||||
uint32_t tickstart;
|
||||
#if (USE_SPI_CRC != 0U)
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
__IO uint8_t * ptmpreg8;
|
||||
__IO uint8_t tmpreg8 = 0;
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
||||
/* Init tickstart for timeout management*/
|
||||
tickstart = HAL_GetTick();
|
||||
|
|
@ -3120,8 +3162,12 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
/* Error on the CRC reception */
|
||||
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
||||
}
|
||||
/* Read CRC to Flush DR and RXNE flag */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
/* Initialize the 8bit temporary pointer */
|
||||
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
||||
/* Read 8bit CRC */
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -3131,7 +3177,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
|
||||
}
|
||||
/* Read CRC to Flush DR and RXNE flag */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
}
|
||||
}
|
||||
#endif /* USE_SPI_CRC */
|
||||
|
|
@ -3466,8 +3514,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint8_t * ptmpreg8;
|
||||
__IO uint8_t tmpreg8 = 0;
|
||||
|
||||
/* Initialize the 8bit temporary pointer */
|
||||
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
||||
/* Read 8bit CRC to flush Data Register */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
|
||||
hspi->CRCSize--;
|
||||
|
||||
|
|
@ -3574,8 +3629,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
|
||||
/* Read 16bit CRC to flush Data Register */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
|
||||
/* Disable RXNE interrupt */
|
||||
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
|
||||
|
|
@ -3630,8 +3689,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint8_t * ptmpreg8;
|
||||
__IO uint8_t tmpreg8 = 0;
|
||||
|
||||
/* Initialize the 8bit temporary pointer */
|
||||
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
||||
/* Read 8bit CRC to flush Data Register */
|
||||
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
|
||||
hspi->CRCSize--;
|
||||
|
||||
|
|
@ -3684,8 +3750,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
|
|||
*/
|
||||
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0U;
|
||||
|
||||
/* Read 16bit CRC to flush Data Register */
|
||||
READ_REG(hspi->Instance->DR);
|
||||
tmpreg = READ_REG(hspi->Instance->DR);
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg);
|
||||
|
||||
/* Disable RXNE and ERR interrupt */
|
||||
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
|
||||
|
|
@ -3863,11 +3933,16 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
|
|||
__IO uint32_t count;
|
||||
uint32_t tmp_timeout;
|
||||
uint32_t tmp_tickstart;
|
||||
__IO uint8_t * ptmpreg8;
|
||||
__IO uint8_t tmpreg8 = 0;
|
||||
|
||||
/* Adjust Timeout value in case of end of transfer */
|
||||
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
||||
tmp_tickstart = HAL_GetTick();
|
||||
|
||||
/* Initialize the 8bit temporary pointer */
|
||||
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
||||
|
||||
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
||||
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
|
||||
|
||||
|
|
@ -3875,8 +3950,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
|
|||
{
|
||||
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
|
||||
{
|
||||
/* Read 8bit CRC to flush Data Register */
|
||||
READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
|
||||
/* Flush Data Register by a blank read */
|
||||
tmpreg8 = *ptmpreg8;
|
||||
/* To avoid GCC warning */
|
||||
UNUSED(tmpreg8);
|
||||
}
|
||||
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
|
|
|
|||
|
|
@ -569,7 +569,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
|
|||
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1086,7 +1087,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1107,7 +1109,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1128,7 +1131,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1148,7 +1152,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1726,7 +1731,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
|
|||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1747,7 +1753,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
|
|||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1767,7 +1774,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
|
|||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1787,7 +1795,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
|
|||
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -2341,6 +2350,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Enable the Input Capture channel */
|
||||
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
case TIM_CHANNEL_1:
|
||||
|
|
@ -2353,7 +2379,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -2373,7 +2400,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -2393,7 +2421,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -2413,7 +2442,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -2427,23 +2457,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
|||
break;
|
||||
}
|
||||
|
||||
/* Enable the Input Capture channel */
|
||||
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
||||
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_TIM_ENABLE(htim);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -2698,11 +2711,12 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
|
|||
|
||||
/**
|
||||
* @brief Starts the TIM One Pulse signal generation.
|
||||
* @note Though OutputChannel parameter is deprecated and ignored by the function
|
||||
* it has been kept to avoid HAL_TIM API compatibility break.
|
||||
* @note The pulse output channel is determined when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channels to be enabled
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @param OutputChannel See note above
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
|
|
@ -2734,7 +2748,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
|
|||
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
||||
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
||||
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
||||
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
||||
whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
||||
|
||||
No need to enable the counter, it's enabled automatically by hardware
|
||||
(the counter starts in response to a stimulus and generate a pulse */
|
||||
|
|
@ -2754,11 +2768,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
|
|||
|
||||
/**
|
||||
* @brief Stops the TIM One Pulse signal generation.
|
||||
* @note Though OutputChannel parameter is deprecated and ignored by the function
|
||||
* it has been kept to avoid HAL_TIM API compatibility break.
|
||||
* @note The pulse output channel is determined when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channels to be disable
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @param OutputChannel See note above
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
|
|
@ -2770,7 +2785,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
|
|||
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
||||
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
||||
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
||||
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
||||
whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
||||
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
||||
|
|
@ -2796,11 +2811,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
|
|||
|
||||
/**
|
||||
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
|
||||
* @note Though OutputChannel parameter is deprecated and ignored by the function
|
||||
* it has been kept to avoid HAL_TIM API compatibility break.
|
||||
* @note The pulse output channel is determined when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channels to be enabled
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @param OutputChannel See note above
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
|
|
@ -2832,7 +2848,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
|
|||
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
||||
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
||||
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
||||
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
||||
whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
||||
|
||||
No need to enable the counter, it's enabled automatically by hardware
|
||||
(the counter starts in response to a stimulus and generate a pulse */
|
||||
|
|
@ -2858,11 +2874,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
|
|||
|
||||
/**
|
||||
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
|
||||
* @note Though OutputChannel parameter is deprecated and ignored by the function
|
||||
* it has been kept to avoid HAL_TIM API compatibility break.
|
||||
* @note The pulse output channel is determined when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channels to be enabled
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @param OutputChannel See note above
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
|
|
@ -2880,7 +2897,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
|
|||
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
||||
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
||||
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
||||
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
||||
whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
||||
|
||||
|
|
@ -3563,7 +3580,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
|
|||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -3588,7 +3606,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
|
|||
/* Set the DMA error callback */
|
||||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -3614,7 +3633,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
|
|||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -3628,7 +3648,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
|
|||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -6105,115 +6126,143 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_TIM_BASE_MSPINIT_CB_ID :
|
||||
htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
|
||||
/* Legacy weak Base MspInit Callback */
|
||||
htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
|
||||
htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
|
||||
/* Legacy weak Base Msp DeInit Callback */
|
||||
htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_IC_MSPINIT_CB_ID :
|
||||
htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
|
||||
/* Legacy weak IC Msp Init Callback */
|
||||
htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_IC_MSPDEINIT_CB_ID :
|
||||
htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
|
||||
/* Legacy weak IC Msp DeInit Callback */
|
||||
htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_OC_MSPINIT_CB_ID :
|
||||
htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
|
||||
/* Legacy weak OC Msp Init Callback */
|
||||
htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_OC_MSPDEINIT_CB_ID :
|
||||
htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
|
||||
/* Legacy weak OC Msp DeInit Callback */
|
||||
htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PWM_MSPINIT_CB_ID :
|
||||
htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
|
||||
/* Legacy weak PWM Msp Init Callback */
|
||||
htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
|
||||
htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
|
||||
/* Legacy weak PWM Msp DeInit Callback */
|
||||
htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
|
||||
htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
|
||||
/* Legacy weak One Pulse Msp Init Callback */
|
||||
htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
|
||||
htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
|
||||
/* Legacy weak One Pulse Msp DeInit Callback */
|
||||
htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
|
||||
htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
|
||||
/* Legacy weak Encoder Msp Init Callback */
|
||||
htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
|
||||
htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
|
||||
/* Legacy weak Encoder Msp DeInit Callback */
|
||||
htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
|
||||
htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
|
||||
/* Legacy weak Hall Sensor Msp Init Callback */
|
||||
htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
|
||||
htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
|
||||
/* Legacy weak Hall Sensor Msp DeInit Callback */
|
||||
htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PERIOD_ELAPSED_CB_ID :
|
||||
htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
|
||||
/* Legacy weak Period Elapsed Callback */
|
||||
htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
|
||||
htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
|
||||
/* Legacy weak Period Elapsed half complete Callback */
|
||||
htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_TRIGGER_CB_ID :
|
||||
htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
|
||||
/* Legacy weak Trigger Callback */
|
||||
htim->TriggerCallback = HAL_TIM_TriggerCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_TRIGGER_HALF_CB_ID :
|
||||
htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
|
||||
/* Legacy weak Trigger half complete Callback */
|
||||
htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_IC_CAPTURE_CB_ID :
|
||||
htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
|
||||
/* Legacy weak IC Capture Callback */
|
||||
htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
|
||||
htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
|
||||
/* Legacy weak IC Capture half complete Callback */
|
||||
htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
|
||||
htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
|
||||
/* Legacy weak OC Delay Elapsed Callback */
|
||||
htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
|
||||
htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
|
||||
/* Legacy weak PWM Pulse Finished Callback */
|
||||
htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
|
||||
htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
|
||||
/* Legacy weak PWM Pulse Finished half complete Callback */
|
||||
htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ERROR_CB_ID :
|
||||
htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
|
||||
/* Legacy weak Error Callback */
|
||||
htim->ErrorCallback = HAL_TIM_ErrorCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_COMMUTATION_CB_ID :
|
||||
htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
|
||||
/* Legacy weak Commutation Callback */
|
||||
htim->CommutationCallback = HAL_TIMEx_CommutCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_COMMUTATION_HALF_CB_ID :
|
||||
htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
|
||||
/* Legacy weak Commutation half complete Callback */
|
||||
htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_BREAK_CB_ID :
|
||||
htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
|
||||
/* Legacy weak Break Callback */
|
||||
htim->BreakCallback = HAL_TIMEx_BreakCallback;
|
||||
break;
|
||||
|
||||
case HAL_TIM_BREAK2_CB_ID :
|
||||
htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
|
||||
/* Legacy weak Break2 Callback */
|
||||
htim->Break2Callback = HAL_TIMEx_Break2Callback;
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -6227,59 +6276,73 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_TIM_BASE_MSPINIT_CB_ID :
|
||||
htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
|
||||
/* Legacy weak Base MspInit Callback */
|
||||
htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
|
||||
htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
|
||||
/* Legacy weak Base Msp DeInit Callback */
|
||||
htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_IC_MSPINIT_CB_ID :
|
||||
htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
|
||||
/* Legacy weak IC Msp Init Callback */
|
||||
htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_IC_MSPDEINIT_CB_ID :
|
||||
htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
|
||||
/* Legacy weak IC Msp DeInit Callback */
|
||||
htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_OC_MSPINIT_CB_ID :
|
||||
htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
|
||||
/* Legacy weak OC Msp Init Callback */
|
||||
htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_OC_MSPDEINIT_CB_ID :
|
||||
htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
|
||||
/* Legacy weak OC Msp DeInit Callback */
|
||||
htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PWM_MSPINIT_CB_ID :
|
||||
htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
|
||||
/* Legacy weak PWM Msp Init Callback */
|
||||
htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
|
||||
htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
|
||||
/* Legacy weak PWM Msp DeInit Callback */
|
||||
htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
|
||||
htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
|
||||
/* Legacy weak One Pulse Msp Init Callback */
|
||||
htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
|
||||
htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
|
||||
/* Legacy weak One Pulse Msp DeInit Callback */
|
||||
htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
|
||||
htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
|
||||
/* Legacy weak Encoder Msp Init Callback */
|
||||
htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
|
||||
htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
|
||||
/* Legacy weak Encoder Msp DeInit Callback */
|
||||
htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
|
||||
htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
|
||||
/* Legacy weak Hall Sensor Msp Init Callback */
|
||||
htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
|
||||
break;
|
||||
|
||||
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
|
||||
htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
|
||||
/* Legacy weak Hall Sensor Msp DeInit Callback */
|
||||
htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -7687,20 +7750,20 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat
|
|||
void TIM_ResetCallback(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
/* Reset the TIM callback to the legacy weak callbacks */
|
||||
htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
|
||||
htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
|
||||
htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
|
||||
htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
|
||||
htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
|
||||
htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
|
||||
htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
|
||||
htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
|
||||
htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
|
||||
htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
|
||||
htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
|
||||
htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
|
||||
htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
|
||||
htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
|
||||
htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
|
||||
htim->TriggerCallback = HAL_TIM_TriggerCallback;
|
||||
htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
|
||||
htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
|
||||
htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
|
||||
htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
|
||||
htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
|
||||
htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
|
||||
htim->ErrorCallback = HAL_TIM_ErrorCallback;
|
||||
htim->CommutationCallback = HAL_TIMEx_CommutCallback;
|
||||
htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
|
||||
htim->BreakCallback = HAL_TIMEx_BreakCallback;
|
||||
htim->Break2Callback = HAL_TIMEx_Break2Callback;
|
||||
}
|
||||
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
||||
|
||||
|
|
|
|||
|
|
@ -65,8 +65,10 @@ typedef struct
|
|||
This means in PWM mode that (N+1) corresponds to:
|
||||
- the number of PWM periods in edge-aligned mode
|
||||
- the number of half PWM period in center-aligned mode
|
||||
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
|
||||
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
GP timers: this parameter must be a number between Min_Data = 0x00 and
|
||||
Max_Data = 0xFF.
|
||||
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
|
||||
Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
|
||||
This parameter can be a value of @ref TIM_AutoReloadPreload */
|
||||
|
|
@ -218,7 +220,8 @@ typedef struct
|
|||
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
|
||||
This parameter can be a value of @ref TIM_ClearInput_Polarity */
|
||||
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
|
||||
This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
|
||||
This parameter must be 0: When OCRef clear feature is used with ETR source,
|
||||
ETR prescaler must be off */
|
||||
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
} TIM_ClearInputConfigTypeDef;
|
||||
|
|
@ -268,32 +271,32 @@ typedef struct
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode
|
||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
|
||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
uint32_t LockLevel; /*!< TIM Lock level
|
||||
This parameter can be a value of @ref TIM_Lock_level */
|
||||
uint32_t DeadTime; /*!< TIM dead Time
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint32_t BreakState; /*!< TIM Break State
|
||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
||||
uint32_t BreakPolarity; /*!< TIM Break input polarity
|
||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
||||
uint32_t BreakFilter; /*!< Specifies the break input filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
|
||||
This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
|
||||
uint32_t Break2State; /*!< TIM Break2 State
|
||||
This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
|
||||
uint32_t Break2Polarity; /*!< TIM Break2 input polarity
|
||||
This parameter can be a value of @ref TIM_Break2_Polarity */
|
||||
uint32_t Break2Filter; /*!< TIM break2 input filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
|
||||
This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
|
||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
|
||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
|
||||
uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
|
||||
|
||||
uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
|
||||
uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
||||
|
||||
uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
|
||||
|
||||
uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
|
||||
|
||||
uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
|
||||
|
||||
uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
|
||||
|
||||
uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
|
||||
|
||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
|
||||
} TIM_BreakDeadTimeConfigTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -671,10 +674,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC2, IC1, IC4 or IC3, respectively */
|
||||
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
|
||||
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
|
||||
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -934,19 +935,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
* @{
|
||||
*/
|
||||
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
|
||||
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
|
||||
(if none of the break inputs BRK and BRK2 is active) */
|
||||
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
|
||||
/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
|
||||
* @{
|
||||
*/
|
||||
#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
|
||||
#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
|
||||
#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1086,24 +1086,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
|
||||
* @{
|
||||
*/
|
||||
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1238,7 +1238,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
* @brief Disable the TIM main Output.
|
||||
* @param __HANDLE__ TIM handle
|
||||
* @retval None
|
||||
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
|
||||
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
|
||||
* disabled
|
||||
*/
|
||||
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
|
||||
do { \
|
||||
|
|
@ -1405,7 +1406,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
|
||||
/**
|
||||
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
|
||||
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
|
||||
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
|
||||
* in an atomic way.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval None
|
||||
mode.
|
||||
|
|
@ -1432,8 +1434,8 @@ mode.
|
|||
* @brief Indicates whether or not the TIM Counter is used as downcounter.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
|
||||
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
|
||||
mode.
|
||||
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
|
||||
* or Encoder mode.
|
||||
*/
|
||||
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
|
||||
|
||||
|
|
@ -1447,7 +1449,8 @@ mode.
|
|||
|
||||
/**
|
||||
* @brief Set the TIM Counter Register value on runtime.
|
||||
* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
|
||||
* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
|
||||
* case of 32 bits counter TIM instance.
|
||||
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __COUNTER__ specifies the Counter register new value.
|
||||
|
|
@ -1509,7 +1512,8 @@ mode.
|
|||
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
|
||||
|
||||
/**
|
||||
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
|
||||
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
|
||||
* function.
|
||||
* @param __HANDLE__ TIM handle.
|
||||
* @param __CHANNEL__ TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -2117,12 +2121,18 @@ mode.
|
|||
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[0] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[2] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[3] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[4] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[5] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
|
||||
|
|
@ -2138,10 +2148,14 @@ mode.
|
|||
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[0] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[2] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[3] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
|
|
@ -2316,14 +2330,14 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_Sla
|
|||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
|
||||
uint32_t DataLength);
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
|
||||
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
|
|
|||
|
|
@ -56,10 +56,13 @@
|
|||
the commutation event).
|
||||
|
||||
(#) Activate the TIM peripheral using one of the start functions:
|
||||
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
|
||||
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
|
||||
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
|
||||
HAL_TIMEx_OCN_Start_IT()
|
||||
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
|
||||
HAL_TIMEx_PWMN_Start_IT()
|
||||
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
|
||||
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
|
||||
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
|
||||
HAL_TIMEx_HallSensor_Start_IT().
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
|
|
@ -348,7 +351,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
|
|||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the Input Capture channel 1
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
|
||||
TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
|
|
@ -380,7 +384,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
|
|||
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
|
||||
|
||||
/* Disable the Input Capture channels 1, 2 and 3
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
|
||||
TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
||||
|
||||
/* Disable the Peripheral */
|
||||
|
|
@ -431,7 +436,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
|
|||
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
||||
|
||||
/* Enable the Input Capture channel 1
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
|
||||
TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
||||
|
||||
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
||||
|
|
@ -463,7 +469,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
|
|||
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
|
||||
|
||||
/* Disable the Input Capture channel 1
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
|
||||
TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
||||
|
||||
/* Disable the capture compare Interrupts event */
|
||||
|
|
@ -523,7 +530,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
|
|||
}
|
||||
|
||||
/* Enable the Input Capture channel 1
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
|
||||
TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
||||
|
||||
/* Set the DMA Input Capture 1 Callbacks */
|
||||
|
|
@ -570,7 +578,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
|
|||
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
|
||||
|
||||
/* Disable the Input Capture channel 1
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
|
||||
TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
||||
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
||||
|
||||
|
||||
|
|
@ -899,7 +908,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -919,7 +929,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -939,7 +950,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1356,7 +1368,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
|||
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1376,7 +1389,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
|||
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1396,7 +1410,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
|||
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
|
||||
Length) != HAL_OK)
|
||||
{
|
||||
/* Return error status */
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1521,8 +1536,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
/**
|
||||
* @brief Starts the TIM One Pulse signal generation on the complementary
|
||||
* output.
|
||||
* @note OutputChannel must match the pulse output channel chosen when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channel to be enabled
|
||||
* @param OutputChannel pulse output channel to enable
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
|
|
@ -1531,22 +1548,28 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
|
|||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
{
|
||||
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
|
||||
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
|
||||
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
|
||||
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
||||
|
||||
/* Check the TIM channels state */
|
||||
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the complementary One Pulse output channel and the Input Capture channel */
|
||||
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
|
||||
|
|
@ -1562,8 +1585,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
|
|||
/**
|
||||
* @brief Stops the TIM One Pulse signal generation on the complementary
|
||||
* output.
|
||||
* @note OutputChannel must match the pulse output channel chosen when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channel to be disabled
|
||||
* @param OutputChannel pulse output channel to disable
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
|
|
@ -1587,8 +1612,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
|
|||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
|
@ -1597,8 +1624,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
|
|||
/**
|
||||
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
|
||||
* complementary channel.
|
||||
* @note OutputChannel must match the pulse output channel chosen when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channel to be enabled
|
||||
* @param OutputChannel pulse output channel to enable
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
|
|
@ -1607,22 +1636,28 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
|
|||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
||||
{
|
||||
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
|
||||
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
|
||||
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
|
||||
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
||||
|
||||
/* Check the TIM channels state */
|
||||
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
||||
|
||||
/* Enable the TIM Capture/Compare 1 interrupt */
|
||||
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
||||
|
|
@ -1644,8 +1679,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
|
|||
/**
|
||||
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
|
||||
* complementary channel.
|
||||
* @note OutputChannel must match the pulse output channel chosen when calling
|
||||
* @ref HAL_TIM_OnePulse_ConfigChannel().
|
||||
* @param htim TIM One Pulse handle
|
||||
* @param OutputChannel TIM Channel to be disabled
|
||||
* @param OutputChannel pulse output channel to disable
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
|
|
@ -1675,8 +1712,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
|
|||
__HAL_TIM_DISABLE(htim);
|
||||
|
||||
/* Set the TIM channels state */
|
||||
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
|
@ -2443,15 +2482,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br
|
|||
/* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
do
|
||||
while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
|
||||
{
|
||||
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM)
|
||||
if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
|
||||
{
|
||||
return HAL_OK;
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
} while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -2464,15 +2505,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br
|
|||
/* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
do
|
||||
while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
|
||||
{
|
||||
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM)
|
||||
if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
|
||||
{
|
||||
return HAL_OK;
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
} while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -71,8 +71,7 @@ typedef struct
|
|||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
|
||||
uint32_t Polarity; /*!< Specifies the break input source polarity.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
|
||||
}
|
||||
TIMEx_BreakInputConfigTypeDef;
|
||||
} TIMEx_BreakInputConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -97,7 +96,7 @@ TIMEx_BreakInputConfigTypeDef;
|
|||
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
#if defined(COMP3)
|
||||
#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
#if defined(TIM2)
|
||||
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
|
||||
#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
|
||||
|
|
@ -107,7 +106,7 @@ TIMEx_BreakInputConfigTypeDef;
|
|||
#define TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */
|
||||
#define TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */
|
||||
#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */
|
||||
#endif
|
||||
#endif /* COMP3 */
|
||||
#endif /* TIM2 */
|
||||
#if defined(TIM3)
|
||||
#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
|
||||
|
|
@ -136,8 +135,8 @@ TIMEx_BreakInputConfigTypeDef;
|
|||
/** @defgroup TIMEx_Break_Input TIM Extended Break input
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
|
||||
#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
|
||||
#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
|
||||
#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -160,8 +159,8 @@ TIMEx_BreakInputConfigTypeDef;
|
|||
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
|
||||
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
|
||||
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
|
||||
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -169,8 +168,8 @@ TIMEx_BreakInputConfigTypeDef;
|
|||
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -262,17 +261,17 @@ TIMEx_BreakInputConfigTypeDef;
|
|||
#define TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */
|
||||
#if defined(RCC_MCO2_SUPPORT)
|
||||
#define TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */
|
||||
#endif
|
||||
#endif /* RCC_MCO2_SUPPORT */
|
||||
|
||||
#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */
|
||||
#if defined(RCC_HSI48_SUPPORT)
|
||||
#define TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */
|
||||
#endif
|
||||
#endif /* RCC_HSI48_SUPPORT */
|
||||
#define TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */
|
||||
#define TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */
|
||||
#if defined(RCC_MCO2_SUPPORT)
|
||||
#define TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */
|
||||
#endif
|
||||
#endif /* RCC_MCO2_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -177,27 +177,22 @@
|
|||
/** @defgroup UART_Private_Constants UART Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
|
||||
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
|
||||
USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
|
||||
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
|
||||
USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
|
||||
|
||||
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
|
||||
USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
|
||||
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
|
||||
USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
|
||||
|
||||
#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
|
||||
#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
|
||||
|
||||
#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
|
||||
#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @addtogroup UART_Private_Functions
|
||||
* @{
|
||||
|
|
@ -227,6 +222,16 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup UART_Private_variables
|
||||
* @{
|
||||
*/
|
||||
const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported Constants --------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup UART_Exported_Functions UART Exported Functions
|
||||
|
|
@ -1073,7 +1078,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
|
|||
(+) HAL_UART_AbortTransmitCpltCallback()
|
||||
(+) HAL_UART_AbortReceiveCpltCallback()
|
||||
|
||||
(#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
|
||||
(#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
|
||||
reception services:
|
||||
(+) HAL_UARTEx_RxEventCallback()
|
||||
|
||||
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
|
||||
|
|
@ -1212,8 +1218,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
|
|||
* RXFNE flag is set. From hardware perspective, RXFNE flag and
|
||||
* RXNE are mapped on the same bit-field.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
|
||||
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
|
|
@ -1371,7 +1377,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
|
|||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Enable the TX FIFO threshold interrupt */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1388,7 +1394,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
|
|||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Enable the Transmit Data Register Empty interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -1405,8 +1411,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
|
|||
* the received data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
|
||||
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
|
|
@ -1440,7 +1446,17 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
|
|||
/* Set Reception type to Standard reception */
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
|
||||
return(UART_Start_Receive_IT(huart, pData, Size));
|
||||
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
||||
{
|
||||
/* Check that USART RTOEN bit is set */
|
||||
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
||||
{
|
||||
/* Enable the UART Receiver Timeout Interrupt */
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
||||
}
|
||||
}
|
||||
|
||||
return (UART_Start_Receive_IT(huart, pData, Size));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1528,7 +1544,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
|
|||
|
||||
/* Enable the DMA transfer for transmit request by setting the DMAT bit
|
||||
in the UART CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -1581,7 +1597,17 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
|
|||
/* Set Reception type to Standard reception */
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
|
||||
return(UART_Start_Receive_DMA(huart, pData, Size));
|
||||
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
||||
{
|
||||
/* Check that USART RTOEN bit is set */
|
||||
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
||||
{
|
||||
/* Enable the UART Receiver Timeout Interrupt */
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
||||
}
|
||||
}
|
||||
|
||||
return (UART_Start_Receive_DMA(huart, pData, Size));
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1605,17 +1631,17 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
|
|||
(gstate == HAL_UART_STATE_BUSY_TX))
|
||||
{
|
||||
/* Disable the UART DMA Tx request */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
}
|
||||
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
|
||||
(rxstate == HAL_UART_STATE_BUSY_RX))
|
||||
{
|
||||
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Disable the UART DMA Rx request */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
}
|
||||
|
||||
__HAL_UNLOCK(huart);
|
||||
|
|
@ -1635,7 +1661,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
|
|||
if (huart->gState == HAL_UART_STATE_BUSY_TX)
|
||||
{
|
||||
/* Enable the UART DMA Tx request */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
}
|
||||
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
||||
{
|
||||
|
|
@ -1643,11 +1669,11 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
|
|||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
||||
|
||||
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Enable the UART DMA Rx request */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
}
|
||||
|
||||
__HAL_UNLOCK(huart);
|
||||
|
|
@ -1676,7 +1702,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
|
|||
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
|
||||
(gstate == HAL_UART_STATE_BUSY_TX))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
/* Abort the UART DMA Tx channel */
|
||||
if (huart->hdmatx != NULL)
|
||||
|
|
@ -1700,7 +1726,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
|
|||
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
|
||||
(rxstate == HAL_UART_STATE_BUSY_RX))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* Abort the UART DMA Rx channel */
|
||||
if (huart->hdmarx != NULL)
|
||||
|
|
@ -1738,20 +1764,20 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
|
|||
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
|
||||
USART_CR1_TCIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
|
||||
USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
|
||||
|
||||
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
}
|
||||
|
||||
/* Disable the UART DMA Tx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
|
||||
if (huart->hdmatx != NULL)
|
||||
|
|
@ -1776,7 +1802,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
|
|||
/* Disable the UART DMA Rx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
|
||||
if (huart->hdmarx != NULL)
|
||||
|
|
@ -1839,13 +1865,13 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
|
|||
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable TCIE, TXEIE and TXFTIE interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
|
||||
/* Disable the UART DMA Tx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
|
||||
if (huart->hdmatx != NULL)
|
||||
|
|
@ -1897,19 +1923,19 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
|
|||
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
|
||||
|
||||
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
}
|
||||
|
||||
/* Disable the UART DMA Rx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
|
||||
if (huart->hdmarx != NULL)
|
||||
|
|
@ -1966,14 +1992,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
|
|||
uint32_t abortcplt = 1U;
|
||||
|
||||
/* Disable interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
|
||||
USART_CR1_TXEIE_TXFNFIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
|
||||
USART_CR1_TXEIE_TXFNFIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
|
||||
|
||||
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
}
|
||||
|
||||
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
|
||||
|
|
@ -2011,7 +2037,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
|
|||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
|
||||
{
|
||||
/* Disable DMA Tx at UART level */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
|
||||
if (huart->hdmatx != NULL)
|
||||
|
|
@ -2034,7 +2060,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
|
|||
/* Disable the UART DMA Rx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
|
||||
if (huart->hdmarx != NULL)
|
||||
|
|
@ -2116,13 +2142,13 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
|
|||
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
|
||||
/* Disable the UART DMA Tx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
|
||||
if (huart->hdmatx != NULL)
|
||||
|
|
@ -2206,19 +2232,19 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
|
|||
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
||||
}
|
||||
|
||||
/* Disable the UART DMA Rx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
|
||||
if (huart->hdmarx != NULL)
|
||||
|
|
@ -2399,7 +2425,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
/* Disable the UART DMA Rx request if enabled */
|
||||
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* Abort the UART DMA Rx channel */
|
||||
if (huart->hdmarx != NULL)
|
||||
|
|
@ -2460,9 +2486,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
|
||||
/* Check current reception Mode :
|
||||
If Reception till IDLE event has been selected : */
|
||||
if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
&&((isrflags & USART_ISR_IDLE) != 0U)
|
||||
&&((cr1its & USART_ISR_IDLE) != 0U))
|
||||
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
||||
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
|
||||
|
|
@ -2474,8 +2500,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
(DMA cplt callback will be called).
|
||||
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
||||
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
||||
if ( (nb_remaining_rx_data > 0U)
|
||||
&&(nb_remaining_rx_data < huart->RxXferSize))
|
||||
if ((nb_remaining_rx_data > 0U)
|
||||
&& (nb_remaining_rx_data < huart->RxXferSize))
|
||||
{
|
||||
/* Reception is not complete */
|
||||
huart->RxXferCount = nb_remaining_rx_data;
|
||||
|
|
@ -2484,18 +2510,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
||||
{
|
||||
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
||||
in the UART CR3 register */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* At end of Rx process, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
|
||||
/* Last bytes received, so no need as the abort is immediate */
|
||||
(void)HAL_DMA_Abort(huart->hdmarx);
|
||||
|
|
@ -2506,7 +2532,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
#else
|
||||
/*Call legacy weak Rx Event callback*/
|
||||
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
||||
#endif
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
|
@ -2516,14 +2542,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
/* Check received length : If all expected data are received, do nothing.
|
||||
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
||||
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
||||
if ( (huart->RxXferCount > 0U)
|
||||
&&(nb_rx_data > 0U) )
|
||||
if ((huart->RxXferCount > 0U)
|
||||
&& (nb_rx_data > 0U))
|
||||
{
|
||||
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
|
||||
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* Rx process is completed, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -2532,14 +2558,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|||
/* Clear RxISR function pointer */
|
||||
huart->RxISR = NULL;
|
||||
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Rx complete callback*/
|
||||
huart->RxEventCallback(huart, nb_rx_data);
|
||||
#else
|
||||
/*Call legacy weak Rx Event callback*/
|
||||
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
||||
#endif
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
|
@ -2882,7 +2908,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
|
|||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Enable USART mute mode by setting the MME bit in the CR1 register */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_MME);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
|
|
@ -2902,7 +2928,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
|
|||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable USART mute mode by clearing the MME bit in the CR1 register */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
|
|
@ -2931,10 +2957,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
|
|||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Clear TE and RE bits */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
|
||||
|
||||
/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_TE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
|
|
@ -2954,10 +2980,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
|
|||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Clear TE and RE bits */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
|
||||
|
||||
/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_RE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
||||
|
|
@ -3116,7 +3142,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|||
* set TE and RE bits according to huart->Init.Mode value
|
||||
* set OVER8 bit according to huart->Init.OverSampling value */
|
||||
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
||||
tmpreg |= (uint32_t)huart->FifoMode;
|
||||
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
||||
|
||||
/*-------------------------- USART CR2 Configuration -----------------------*/
|
||||
|
|
@ -3429,8 +3454,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
|
|||
{
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||||
interrupts for the interrupt process */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
|
||||
USART_CR1_TXEIE_TXFNFIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -3449,8 +3475,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
|
|||
|
||||
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
||||
interrupts for the interrupt process */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
|
||||
USART_CR1_TXEIE_TXFNFIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -3492,7 +3519,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
|
|||
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
||||
|
||||
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Configure Rx interrupt processing */
|
||||
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
|
||||
|
|
@ -3510,8 +3537,8 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
|
|||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -3528,7 +3555,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
|
|||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -3574,8 +3601,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa
|
|||
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Restore huart->gState to ready */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
/* Restore huart->RxState to ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
|
@ -3583,14 +3610,14 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa
|
|||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Enable the UART Parity Error Interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
|
||||
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
|
||||
in the UART CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -3604,8 +3631,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa
|
|||
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable TXEIE, TCIE, TXFT interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
|
||||
|
||||
/* At end of Tx process, restore huart->gState to Ready */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
|
@ -3620,13 +3647,13 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
|||
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
|
||||
/* At end of Rx process, restore huart->RxState to Ready */
|
||||
|
|
@ -3654,10 +3681,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
|
|||
|
||||
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
|
||||
in the UART CR3 register */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
|
||||
|
||||
/* Enable the UART Transmit Complete Interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
}
|
||||
/* DMA Circular mode */
|
||||
else
|
||||
|
|
@ -3705,12 +3732,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
huart->RxXferCount = 0U;
|
||||
|
||||
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
||||
in the UART CR3 register */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
||||
|
||||
/* At end of Rx process, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -3718,7 +3745,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
|
|||
/* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3762,10 +3789,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Rx Event callback*/
|
||||
huart->RxEventCallback(huart, huart->RxXferSize/2U);
|
||||
huart->RxEventCallback(huart, huart->RxXferSize / 2U);
|
||||
#else
|
||||
/*Call legacy weak Rx Event callback*/
|
||||
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U);
|
||||
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
|
|
@ -4030,10 +4057,10 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
|
|||
if (huart->TxXferCount == 0U)
|
||||
{
|
||||
/* Disable the UART Transmit Data Register Empty Interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
||||
|
||||
/* Enable the UART Transmit Complete Interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -4061,10 +4088,10 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
|
|||
if (huart->TxXferCount == 0U)
|
||||
{
|
||||
/* Disable the UART Transmit Data Register Empty Interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
|
||||
|
||||
/* Enable the UART Transmit Complete Interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -4095,10 +4122,10 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
if (huart->TxXferCount == 0U)
|
||||
{
|
||||
/* Disable the TX FIFO threshold interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
|
||||
/* Enable the UART Transmit Complete Interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
|
||||
break; /* force exit loop */
|
||||
}
|
||||
|
|
@ -4136,10 +4163,10 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
if (huart->TxXferCount == 0U)
|
||||
{
|
||||
/* Disable the TX FIFO threshold interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
|
||||
|
||||
/* Enable the UART Transmit Complete Interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
|
||||
break; /* force exit loop */
|
||||
}
|
||||
|
|
@ -4167,7 +4194,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Disable the UART Transmit Complete Interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
||||
|
||||
/* Tx process is ended, restore huart->gState to Ready */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
|
@ -4205,10 +4232,10 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|||
if (huart->RxXferCount == 0U)
|
||||
{
|
||||
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
|
||||
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Rx process is completed, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -4220,16 +4247,24 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|||
If Reception till IDLE event has been selected : */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
/* Disable IDLE interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
/* Set reception type to Standard */
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
|
||||
/* Disable IDLE interrupt */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
||||
{
|
||||
/* Clear IDLE Flag */
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
}
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Rx Event callback*/
|
||||
huart->RxEventCallback(huart, huart->RxXferSize);
|
||||
#else
|
||||
/*Call legacy weak Rx Event callback*/
|
||||
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
||||
#endif
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -4242,7 +4277,6 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|||
HAL_UART_RxCpltCallback(huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
}
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -4277,10 +4311,10 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|||
if (huart->RxXferCount == 0U)
|
||||
{
|
||||
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
|
||||
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
||||
|
||||
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
||||
|
||||
/* Rx process is completed, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -4292,16 +4326,24 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|||
If Reception till IDLE event has been selected : */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
/* Disable IDLE interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
/* Set reception type to Standard */
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
|
||||
/* Disable IDLE interrupt */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
||||
{
|
||||
/* Clear IDLE Flag */
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
}
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Rx Event callback*/
|
||||
huart->RxEventCallback(huart, huart->RxXferSize);
|
||||
#else
|
||||
/*Call legacy weak Rx Event callback*/
|
||||
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
||||
#endif
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -4314,7 +4356,6 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|||
HAL_UART_RxCpltCallback(huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
}
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -4399,11 +4440,11 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
if (huart->RxXferCount == 0U)
|
||||
{
|
||||
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
|
||||
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
||||
and RX FIFO Threshold interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* Rx process is completed, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -4415,16 +4456,24 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
If Reception till IDLE event has been selected : */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
/* Disable IDLE interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
/* Set reception type to Standard */
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
|
||||
/* Disable IDLE interrupt */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
||||
{
|
||||
/* Clear IDLE Flag */
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
}
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Rx Event callback*/
|
||||
huart->RxEventCallback(huart, huart->RxXferSize);
|
||||
#else
|
||||
/*Call legacy weak Rx Event callback*/
|
||||
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
||||
#endif
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -4437,7 +4486,6 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
HAL_UART_RxCpltCallback(huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
}
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4449,13 +4497,13 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
||||
{
|
||||
/* Disable the UART RXFT interrupt*/
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
||||
|
||||
/* Update the RxISR function pointer */
|
||||
huart->RxISR = UART_RxISR_8BIT;
|
||||
|
||||
/* Enable the UART Data Register Not Empty interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -4542,11 +4590,11 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
if (huart->RxXferCount == 0U)
|
||||
{
|
||||
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
||||
|
||||
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
||||
and RX FIFO Threshold interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* Rx process is completed, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -4558,16 +4606,24 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
If Reception till IDLE event has been selected : */
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
/* Disable IDLE interrupt */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
/* Set reception type to Standard */
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
|
||||
/* Disable IDLE interrupt */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
||||
{
|
||||
/* Clear IDLE Flag */
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
}
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Rx Event callback*/
|
||||
huart->RxEventCallback(huart, huart->RxXferSize);
|
||||
#else
|
||||
/*Call legacy weak Rx Event callback*/
|
||||
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
||||
#endif
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -4580,7 +4636,6 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
HAL_UART_RxCpltCallback(huart);
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
}
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -4592,13 +4647,13 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|||
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
||||
{
|
||||
/* Disable the UART RXFT interrupt*/
|
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
||||
|
||||
/* Update the RxISR function pointer */
|
||||
huart->RxISR = UART_RxISR_16BIT;
|
||||
|
||||
/* Enable the UART Data Register Not Empty interrupt */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -46,54 +46,54 @@ extern "C" {
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
LPUART:
|
||||
=======
|
||||
Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
|
||||
where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
|
||||
UART:
|
||||
=====
|
||||
- If oversampling is 16 or in LIN mode,
|
||||
Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
|
||||
- If oversampling is 8,
|
||||
Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
|
||||
((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[3] = 0
|
||||
Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
|
||||
((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where uart_ker_ck_pres is the UART input clock divided by a prescaler */
|
||||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
LPUART:
|
||||
=======
|
||||
Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
|
||||
where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
|
||||
UART:
|
||||
=====
|
||||
- If oversampling is 16 or in LIN mode,
|
||||
Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
|
||||
- If oversampling is 8,
|
||||
Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
|
||||
((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[3] = 0
|
||||
Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
|
||||
((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where uart_ker_ck_pres is the UART input clock divided by a prescaler */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref UARTEx_Word_Length. */
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref UARTEx_Word_Length. */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref UART_Stop_Bits. */
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref UART_Stop_Bits. */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref UART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref UART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Mode. */
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Mode. */
|
||||
|
||||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref UART_Hardware_Flow_Control. */
|
||||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref UART_Hardware_Flow_Control. */
|
||||
|
||||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
|
||||
to achieve higher speed (up to f_PCLK/8).
|
||||
This parameter can be a value of @ref UART_Over_Sampling. */
|
||||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
|
||||
to achieve higher speed (up to f_PCLK/8).
|
||||
This parameter can be a value of @ref UART_Over_Sampling. */
|
||||
|
||||
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
|
||||
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
|
||||
|
||||
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
|
||||
This parameter can be a value of @ref UART_ClockPrescaler. */
|
||||
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
|
||||
This parameter can be a value of @ref UART_ClockPrescaler. */
|
||||
|
||||
} UART_InitTypeDef;
|
||||
|
||||
|
|
@ -151,7 +151,7 @@ typedef struct
|
|||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
|
||||
* 1 : Init done (Peripheral initialized. HAL UART Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
|
|
@ -168,7 +168,7 @@ typedef struct
|
|||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
|
@ -301,8 +301,9 @@ typedef enum
|
|||
/**
|
||||
* @brief HAL UART Callback pointer definition
|
||||
*/
|
||||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
|
||||
typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
|
||||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
|
||||
typedef void (*pUART_RxEventCallbackTypeDef)
|
||||
(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
|
||||
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
|
|
@ -342,16 +343,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart
|
|||
/** @defgroup UART_Error_Definition UART Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
|
||||
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
|
||||
#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
|
||||
#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1136,10 +1137,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart
|
|||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
|
||||
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Disable CTS flow control.
|
||||
|
|
@ -1155,10 +1156,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart
|
|||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
|
||||
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Enable RTS flow control.
|
||||
|
|
@ -1174,10 +1175,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart
|
|||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
|
||||
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Disable RTS flow control.
|
||||
|
|
@ -1193,10 +1194,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart
|
|||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
|
||||
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
|
||||
} while(0U)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1570,12 +1571,6 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart
|
|||
/* Include UART HAL Extended module */
|
||||
#include "stm32g0xx_hal_uart_ex.h"
|
||||
|
||||
|
||||
/* Prescaler Table used in BRR computation macros.
|
||||
Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
|
||||
extern const uint16_t UARTPrescTable[12];
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UART_Exported_Functions UART Exported Functions
|
||||
* @{
|
||||
|
|
@ -1697,6 +1692,17 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
|
|||
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables -----------------------------------------------------------*/
|
||||
/** @defgroup UART_Private_variables UART Private variables
|
||||
* @{
|
||||
*/
|
||||
/* Prescaler Table used in BRR computation macros.
|
||||
Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
|
||||
extern const uint16_t UARTPrescTable[12];
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -483,7 +483,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
|
|||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set UESM bit */
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
|
@ -502,7 +502,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
|
|||
__HAL_LOCK(huart);
|
||||
|
||||
/* Clear UESM bit */
|
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
|
@ -688,29 +688,33 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
|
||||
* @note HAL_OK is returned if reception is completed (expected number of data has been received)
|
||||
* or if reception is stopped after IDLE event (less than the expected number of data has been received)
|
||||
* In this case, RxLen output parameter indicates number of data available in reception buffer.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @brief Receive an amount of data in blocking mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note HAL_OK is returned if reception is completed (expected number of data has been received)
|
||||
* or if reception is stopped after IDLE event (less than the expected number of data has been received)
|
||||
* In this case, RxLen output parameter indicates number of data available in reception buffer.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
|
||||
* is not empty. Read operations from the RDR register are performed when
|
||||
* RXFNE flag is set. From hardware perspective, RXFNE flag and
|
||||
* RXNE are mapped on the same bit-field.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
|
||||
* (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper
|
||||
* alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
|
||||
* @param RxLen Number of data elements finally received
|
||||
* (could be lower than Size, in case reception ends on IDLE event)
|
||||
* @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint8_t *pdata8bits;
|
||||
uint16_t *pdata16bits;
|
||||
|
|
@ -832,17 +836,19 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
|
||||
* number of received data elements.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
|
||||
* (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
|
||||
* @brief Receive an amount of data in interrupt mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
|
||||
* number of received data elements.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
|
|
@ -884,7 +890,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
|
|||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -905,20 +911,22 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to DMA services, transferring automatically received data elements in user reception buffer and
|
||||
* calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
|
||||
* reception phase as ended. In all cases, callback execution will indicate number of received data elements.
|
||||
* @note When the UART parity is enabled (PCE = 1), the received data contain
|
||||
* the parity bit (MSB position).
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
|
||||
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
|
||||
* @brief Receive an amount of data in DMA mode till either the expected number
|
||||
* of data is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to DMA services, transferring automatically received data elements in user reception buffer and
|
||||
* calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
|
||||
* reception phase as ended. In all cases, callback execution will indicate number of received data elements.
|
||||
* @note When the UART parity is enabled (PCE = 1), the received data contain
|
||||
* the parity bit (MSB position).
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
|
|
@ -960,7 +968,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
|
|||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1022,8 +1030,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
|
|||
uint8_t tx_fifo_depth;
|
||||
uint8_t rx_fifo_threshold;
|
||||
uint8_t tx_fifo_threshold;
|
||||
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
|
||||
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -99,12 +99,12 @@ typedef struct
|
|||
* @brief UART TXFIFO threshold level
|
||||
* @{
|
||||
*/
|
||||
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
|
||||
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
|
||||
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -113,12 +113,12 @@ typedef struct
|
|||
* @brief UART RXFIFO threshold level
|
||||
* @{
|
||||
*/
|
||||
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
|
||||
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
|
||||
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -174,7 +174,8 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
|
|||
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
|
||||
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
|
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
|
|
@ -654,7 +655,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
|
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx */
|
||||
|
||||
/** @brief Report the UART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
|
|
|
|||
|
|
@ -39,7 +39,8 @@
|
|||
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
|
||||
(+++) Configure the DMA Tx/Rx channel.
|
||||
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
|
||||
(+++) Configure the priority and enable the NVIC for the transfer
|
||||
complete interrupt on the DMA Tx/Rx channel.
|
||||
|
||||
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
|
||||
(Receiver/Transmitter) in the husart handle Init structure.
|
||||
|
|
@ -317,7 +318,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
|
|||
|
||||
/* In Synchronous mode, the following bits must be kept cleared:
|
||||
- LINEN bit in the USART_CR2 register
|
||||
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
|
||||
- HDSEL, SCEN and IREN bits in the USART_CR3 register.
|
||||
*/
|
||||
husart->Instance->CR2 &= ~USART_CR2_LINEN;
|
||||
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
|
||||
|
||||
|
|
@ -532,7 +534,7 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US
|
|||
|
||||
/**
|
||||
* @brief Unregister an USART Callback
|
||||
* USART callback is redirected to the weak predefined callback
|
||||
* USART callaback is redirected to the weak predefined callback
|
||||
* @param husart usart handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -561,47 +563,47 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_USART_TX_HALFCOMPLETE_CB_ID :
|
||||
husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
|
||||
husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_TX_COMPLETE_CB_ID :
|
||||
husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_RX_HALFCOMPLETE_CB_ID :
|
||||
husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
|
||||
husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_RX_COMPLETE_CB_ID :
|
||||
husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_TX_RX_COMPLETE_CB_ID :
|
||||
husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
|
||||
husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_ERROR_CB_ID :
|
||||
husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_ABORT_COMPLETE_CB_ID :
|
||||
husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_RX_FIFO_FULL_CB_ID :
|
||||
husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
|
||||
husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_TX_FIFO_EMPTY_CB_ID :
|
||||
husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
|
||||
husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_MSPINIT_CB_ID :
|
||||
husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
|
||||
husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
|
||||
break;
|
||||
|
||||
case HAL_USART_MSPDEINIT_CB_ID :
|
||||
husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -720,13 +722,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
|
|||
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
|
||||
Errors are handled as follows :
|
||||
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
|
||||
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
|
||||
and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
|
||||
to be evaluated by user : this concerns Frame Error,
|
||||
Parity Error or Noise Error in Interrupt mode reception .
|
||||
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
|
||||
error type, and HAL_USART_ErrorCallback() user callback is executed.
|
||||
Transfer is kept ongoing on USART side.
|
||||
If user wants to abort it, Abort services should be called by user.
|
||||
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
|
||||
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
|
||||
Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
|
||||
Error code is set to allow user to identify error type,
|
||||
and HAL_USART_ErrorCallback() user callback is executed.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
|
|
@ -740,7 +745,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
|
|||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
|
||||
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pTxData.
|
||||
* @param husart USART handle.
|
||||
* @param pTxData Pointer to data buffer (u8 or u16 data elements).
|
||||
* @param Size Amount of data elements (u8 or u16) to be sent.
|
||||
|
|
@ -1472,7 +1478,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
|
|||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
|
||||
* (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pTxData.
|
||||
* @param husart USART handle.
|
||||
* @param pTxData pointer to data buffer (u8 or u16 data elements).
|
||||
* @param Size amount of data elements (u8 or u16) to be sent.
|
||||
|
|
@ -1570,9 +1577,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
|
|||
* the received data is handled as a set of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pRxData.
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
|
||||
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
|
||||
* address of user data buffer for storing data to be received, should be aligned on
|
||||
* a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier).
|
||||
* Depending on compilation chain, use of specific alignment compilation directives or pragmas
|
||||
* might be required to ensure proper alignment for pRxData.
|
||||
* @param husart USART handle.
|
||||
* @param pRxData pointer to data buffer (u8 or u16 data elements).
|
||||
* @param Size amount of data elements (u8 or u16) to be received.
|
||||
|
|
@ -1701,9 +1709,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
|
|||
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
|
||||
* of u16 available through pTxData and through pRxData.
|
||||
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
|
||||
* (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
|
||||
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier
|
||||
* (16 bits) (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation
|
||||
* chain, use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pTxData and pRxData.
|
||||
* @param husart USART handle.
|
||||
* @param pTxData pointer to TX data buffer (u8 or u16 data elements).
|
||||
* @param pRxData pointer to RX data buffer (u8 or u16 data elements).
|
||||
|
|
@ -2226,7 +2235,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
|
|||
uint32_t errorcode;
|
||||
|
||||
/* If no error occurs */
|
||||
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
|
||||
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
|
||||
USART_ISR_UDR));
|
||||
if (errorflags == 0U)
|
||||
{
|
||||
/* USART in mode Receiver ---------------------------------------------------*/
|
||||
|
|
@ -2281,6 +2291,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
|
|||
husart->ErrorCode |= HAL_USART_ERROR_ORE;
|
||||
}
|
||||
|
||||
/* USART Receiver Timeout interrupt occurred ---------------------------------*/
|
||||
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
||||
{
|
||||
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
|
||||
|
||||
husart->ErrorCode |= HAL_USART_ERROR_RTO;
|
||||
}
|
||||
|
||||
/* USART SPI slave underrun error interrupt occurred -------------------------*/
|
||||
if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
||||
{
|
||||
|
|
@ -3032,7 +3050,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
|
|||
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
|
||||
break;
|
||||
case USART_CLOCKSOURCE_LSE:
|
||||
usartdiv = (uint32_t)(USART_DIV_SAMPLING8((uint32_t)LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
|
||||
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
|
||||
break;
|
||||
default:
|
||||
ret = HAL_ERROR;
|
||||
|
|
@ -3543,7 +3561,8 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
|
|||
/* Disable the USART Parity Error Interrupt */
|
||||
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
|
||||
|
||||
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
||||
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
|
||||
and RX FIFO Threshold interrupt */
|
||||
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* Clear RxISR function pointer */
|
||||
|
|
@ -3677,7 +3696,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
|
|||
/* Disable the USART Parity Error Interrupt */
|
||||
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
|
||||
|
||||
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
||||
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
|
||||
and RX FIFO Threshold interrupt */
|
||||
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
||||
|
||||
/* Clear RxISR function pointer */
|
||||
|
|
|
|||
|
|
@ -48,11 +48,15 @@ typedef struct
|
|||
{
|
||||
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[15:4] = ((2 * fclk_pres) /
|
||||
((huart->Init.BaudRate)))[15:4]
|
||||
Baud Rate Register[3] = 0
|
||||
Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.
|
||||
@note Oversampling by 8 is systematically applied to achieve high baud rates. */
|
||||
Baud Rate Register[2:0] = (((2 * fclk_pres) /
|
||||
((huart->Init.BaudRate)))[3:0]) >> 1
|
||||
where fclk_pres is the USART input clock frequency (fclk)
|
||||
divided by a prescaler.
|
||||
@note Oversampling by 8 is systematically applied to
|
||||
achieve high baud rates. */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USARTEx_Word_Length. */
|
||||
|
|
@ -138,7 +142,7 @@ typedef struct __USART_HandleTypeDef
|
|||
|
||||
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
|
||||
|
||||
uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
|
||||
uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
|
||||
of @ref USARTEx_Slave_Mode */
|
||||
|
||||
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
|
||||
|
|
@ -215,16 +219,17 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
/** @defgroup USART_Error_Definition USART Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
|
||||
#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */
|
||||
#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
|
||||
#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
|
||||
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
|
||||
#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -260,15 +265,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Over_Sampling USART Over Sampling
|
||||
* @{
|
||||
*/
|
||||
#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
|
||||
#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock USART Clock
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -349,6 +345,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
|
||||
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
|
||||
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
|
||||
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
|
||||
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
|
||||
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
|
||||
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
|
||||
|
|
@ -403,6 +400,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
|
||||
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
|
||||
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -459,6 +457,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
|
||||
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
|
||||
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
|
||||
* @arg @ref USART_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref USART_FLAG_NE Noise Error flag
|
||||
|
|
@ -479,6 +478,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
|
||||
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
|
||||
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -544,9 +544,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
|
||||
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified USART interrupt.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
|
@ -566,10 +569,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
|
||||
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified USART interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
|
@ -592,7 +597,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
||||
& ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
|
||||
& (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
|
||||
USART_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified USART interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
|
@ -614,10 +620,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
|
||||
(__HANDLE__)->Instance->CR1 : \
|
||||
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
|
||||
(__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & (0x01U <<\
|
||||
(((uint16_t)(__INTERRUPT__)) &\
|
||||
USART_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
|
|
@ -629,6 +638,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
|
||||
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
|
||||
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
|
||||
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
|
||||
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
|
|
@ -703,189 +713,9 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
* @param __CLOCKPRESCALER__ USART prescaler value.
|
||||
* @retval Division result
|
||||
*/
|
||||
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
|
||||
+ ((__BAUD__)/2U)) / (__BAUD__))
|
||||
|
||||
/** @brief Report the USART clock source.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval the USART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif
|
||||
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
|
||||
(((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
|
||||
+ ((__BAUD__)/2U)) / (__BAUD__))
|
||||
|
||||
/** @brief Check USART Baud rate.
|
||||
* @param __BAUDRATE__ Baudrate specified by the user.
|
||||
|
|
@ -920,14 +750,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
|||
*/
|
||||
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART oversampling is valid.
|
||||
* @param __SAMPLING__ USART oversampling.
|
||||
* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
|
||||
*/
|
||||
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
|
||||
((__SAMPLING__) == USART_OVERSAMPLING_8))
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART clock state is valid.
|
||||
* @param __CLOCK__ USART clock state.
|
||||
|
|
|
|||
|
|
@ -57,10 +57,10 @@
|
|||
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* UART RX FIFO depth */
|
||||
/* USART RX FIFO depth */
|
||||
#define RX_FIFO_DEPTH 8U
|
||||
|
||||
/* UART TX FIFO depth */
|
||||
/* USART TX FIFO depth */
|
||||
#define TX_FIFO_DEPTH 8U
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -503,8 +503,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
|
|||
uint8_t rx_fifo_threshold;
|
||||
uint8_t tx_fifo_threshold;
|
||||
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
|
||||
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
||||
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
||||
|
||||
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
|
||||
{
|
||||
|
|
@ -515,10 +515,14 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
|
|||
{
|
||||
rx_fifo_depth = RX_FIFO_DEPTH;
|
||||
tx_fifo_depth = TX_FIFO_DEPTH;
|
||||
rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
|
||||
tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
|
||||
husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
|
||||
husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
|
||||
rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
|
||||
USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
|
||||
tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
|
||||
USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
|
||||
husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
||||
(uint16_t)denominator[tx_fifo_threshold];
|
||||
husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
||||
(uint16_t)denominator[rx_fifo_threshold];
|
||||
}
|
||||
}
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -45,9 +45,9 @@ extern "C" {
|
|||
/** @defgroup USARTEx_Word_Length USARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
|
||||
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
|
||||
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -119,6 +119,186 @@ extern "C" {
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the USART clock source.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval the USART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
||||
/** @brief Compute the USART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
|
|
@ -169,7 +349,6 @@ extern "C" {
|
|||
} \
|
||||
} while(0U)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Ensure that USART frame length is valid.
|
||||
* @param __LENGTH__ USART frame length.
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32G0xx_LL_Driver
|
||||
* @{
|
||||
|
|
@ -172,7 +172,7 @@
|
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|
||||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
|
||||
)
|
||||
#endif
|
||||
#endif /* TIM15 && TIM6 && TIM2 */
|
||||
|
||||
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
|
||||
(((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|
||||
|
|
@ -262,18 +262,18 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
|
|||
* must be disabled.
|
||||
* @param ADCxy_COMMON ADC common instance
|
||||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
|
||||
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
|
||||
* @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ADC common registers are initialized
|
||||
* - ERROR: ADC common registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
|
||||
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
|
||||
assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
|
||||
assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
|
||||
|
||||
/* Note: Hardware constraint (refer to description of functions */
|
||||
/* "LL_ADC_SetCommonXXX()": */
|
||||
|
|
@ -286,7 +286,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni
|
|||
/* - common to several ADC */
|
||||
/* (all ADC instances belonging to the same ADC common instance) */
|
||||
/* - Set ADC clock (conversion clock) */
|
||||
LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
|
||||
LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -300,16 +300,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni
|
|||
|
||||
/**
|
||||
* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
|
||||
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
|
||||
* @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
|
||||
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
|
||||
{
|
||||
/* Set ADC_CommonInitStruct fields to default values */
|
||||
/* Set pADC_CommonInitStruct fields to default values */
|
||||
/* Set fields of ADC common */
|
||||
/* (all ADC instances belonging to the same ADC common instance) */
|
||||
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
|
||||
pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -533,22 +533,22 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
|
|||
* Refer to function LL_ADC_SetSamplingTimeCommonChannels();
|
||||
* Refer to function LL_ADC_SetChannelSamplingTime();
|
||||
* @param ADCx ADC instance
|
||||
* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ADC registers are initialized
|
||||
* - ERROR: ADC registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
|
||||
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||
|
||||
assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
|
||||
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
|
||||
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
|
||||
assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
|
||||
assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock));
|
||||
assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
|
||||
assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
|
||||
assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
|
||||
|
||||
/* Note: Hardware constraint (refer to description of this function): */
|
||||
/* ADC instance must be disabled. */
|
||||
|
|
@ -565,15 +565,15 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
|
|||
| ADC_CFGR1_WAIT
|
||||
| ADC_CFGR1_AUTOFF
|
||||
,
|
||||
ADC_InitStruct->Resolution
|
||||
| ADC_InitStruct->DataAlignment
|
||||
| ADC_InitStruct->LowPowerMode
|
||||
pADC_InitStruct->Resolution
|
||||
| pADC_InitStruct->DataAlignment
|
||||
| pADC_InitStruct->LowPowerMode
|
||||
);
|
||||
|
||||
MODIFY_REG(ADCx->CFGR2,
|
||||
ADC_CFGR2_CKMODE
|
||||
,
|
||||
ADC_InitStruct->Clock
|
||||
pADC_InitStruct->Clock
|
||||
);
|
||||
}
|
||||
else
|
||||
|
|
@ -587,18 +587,18 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
|
|||
|
||||
/**
|
||||
* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
|
||||
* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
|
||||
* @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
|
||||
void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
|
||||
{
|
||||
/* Set ADC_InitStruct fields to default values */
|
||||
/* Set pADC_InitStruct fields to default values */
|
||||
/* Set fields of ADC instance */
|
||||
ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
|
||||
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
|
||||
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
|
||||
ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
|
||||
pADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
|
||||
pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
|
||||
pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
|
||||
pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -637,37 +637,37 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
|
|||
* Refer to function LL_ADC_SetSamplingTimeCommonChannels();
|
||||
* Refer to function LL_ADC_SetChannelSamplingTime();
|
||||
* @param ADCx ADC instance
|
||||
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: ADC registers are initialized
|
||||
* - ERROR: ADC registers are not initialized
|
||||
*/
|
||||
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
||||
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
|
||||
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
|
||||
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
|
||||
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
|
||||
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
|
||||
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
|
||||
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
|
||||
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
|
||||
|
||||
if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
|
||||
{
|
||||
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
|
||||
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
|
||||
}
|
||||
|
||||
if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
|
||||
|| (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
|
||||
|| (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
|
||||
)
|
||||
{
|
||||
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
|
||||
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
|
||||
|
||||
/* ADC group regular continuous mode and discontinuous mode */
|
||||
/* can not be enabled simultenaeously */
|
||||
assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
|
||||
|| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
|
||||
assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
|
||||
|| (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
|
||||
}
|
||||
|
||||
/* Note: Hardware constraint (refer to description of this function): */
|
||||
|
|
@ -686,7 +686,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
|
|||
/* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
|
||||
/* setting of trigger source to SW start. */
|
||||
if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
|
||||
|| (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
|
||||
|| (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
|
||||
)
|
||||
{
|
||||
/* Case of sequencer mode fixed
|
||||
|
|
@ -701,11 +701,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
|
|||
| ADC_CFGR1_DMACFG
|
||||
| ADC_CFGR1_OVRMOD
|
||||
,
|
||||
ADC_REG_InitStruct->TriggerSource
|
||||
| ADC_REG_InitStruct->SequencerDiscont
|
||||
| ADC_REG_InitStruct->ContinuousMode
|
||||
| ADC_REG_InitStruct->DMATransfer
|
||||
| ADC_REG_InitStruct->Overrun
|
||||
pADC_RegInitStruct->TriggerSource
|
||||
| pADC_RegInitStruct->SequencerDiscont
|
||||
| pADC_RegInitStruct->ContinuousMode
|
||||
| pADC_RegInitStruct->DMATransfer
|
||||
| pADC_RegInitStruct->Overrun
|
||||
);
|
||||
}
|
||||
else
|
||||
|
|
@ -722,18 +722,18 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
|
|||
| ADC_CFGR1_DMACFG
|
||||
| ADC_CFGR1_OVRMOD
|
||||
,
|
||||
ADC_REG_InitStruct->TriggerSource
|
||||
pADC_RegInitStruct->TriggerSource
|
||||
| LL_ADC_REG_SEQ_DISCONT_DISABLE
|
||||
| ADC_REG_InitStruct->ContinuousMode
|
||||
| ADC_REG_InitStruct->DMATransfer
|
||||
| ADC_REG_InitStruct->Overrun
|
||||
| pADC_RegInitStruct->ContinuousMode
|
||||
| pADC_RegInitStruct->DMATransfer
|
||||
| pADC_RegInitStruct->Overrun
|
||||
);
|
||||
}
|
||||
|
||||
/* Set ADC group regular sequencer length */
|
||||
if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
|
||||
{
|
||||
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
|
||||
LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -746,22 +746,22 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
|
|||
|
||||
/**
|
||||
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
|
||||
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
||||
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
|
||||
{
|
||||
/* Set ADC_REG_InitStruct fields to default values */
|
||||
/* Set pADC_RegInitStruct fields to default values */
|
||||
/* Set fields of ADC group regular */
|
||||
/* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
|
||||
/* setting of trigger source to SW start. */
|
||||
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
|
||||
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
|
||||
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
|
||||
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
|
||||
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
|
||||
ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
|
||||
pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
|
||||
pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
|
||||
pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
|
||||
pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
|
||||
pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
|
||||
pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue