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Merge remote-tracking branch 'ARMmbed/master' into ARMmaster

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4
README.md
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@ -11,9 +11,9 @@ The current release, along with a selection of previous versions are detailed he
## Getting Started for Developers
We have a getting started guide for developers using mbed OS in applications:
Please note that you will require [mbed CLI](https://github.com/ARMmbed/mbed-cli) to build mbed OS. For more details, please read the getting started guide for developers using mbed OS in applications:
- [Getting Started](https://docs.mbed.com/docs/mbed-os-handbook/en/5.2/)
- [Getting Started](https://docs.mbed.com/docs/mbed-os-handbook/en/latest/)
## Getting Started for Contributors

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docs/mbed_targets.md
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# Adding and configuring mbed targets
mbed uses JSON as a description language for its build targets. The JSON description of mbed targets can be found in `tools/targets.json`. To better understand how a target is defined, we'll use this example (taken from `targets.json`):
```
"TEENSY3_1": {
"inherits": ["Target"],
"core": "Cortex-M4",
"extra_labels": ["Freescale", "K20XX", "K20DX256"],
"OUTPUT_EXT": "hex",
"is_disk_virtual": true,
"supported_toolchains": ["GCC_ARM", "ARM"],
"post_binary_hook": {
"function": "TEENSY3_1Code.binary_hook",
"toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
},
"device_name": "MK20DX256xxx7",
"detect_code": ["0230"]
```
The definition of the target called **TEENSY3_1** is a JSON object. The properties in the object are either "standard" (understood by the mbed build system) or specific to the target.
# Standard properties
This section lists all the properties that are known to the mbed build system. Unless specified otherwise, all properties are optional.
## inherits
The description of a mbed target can "inherit" from one of more descriptions of other targets. When a target **A** inherits from another target **B** (**A** is the _child_ of **B** and **B** is the _parent_ of **A**), it automatically "borrows" all the definitions of properties from **B** and can modify them as needed (if you're familiar with Python, this is very similar with how class inheritance works in Python). In our example above, `TEENSY3_1` inherits from `Target` (most mbed targets inherit from `Target`). This is how `Target` is defined:
```
"Target": {
"core": null,
"default_toolchain": "ARM",
"supported_toolchains": null,
"extra_labels": [],
"is_disk_virtual": false,
"macros": [],
"detect_code": [],
"public": false
}
```
Since `TEENSY3_1` inherits from `Target`:
- `core` is a property defined both in `TEENSY3_1` and `Target`. Since `TEENSY3_1` redefines it, the value of `core` for `TEENSY3_1` will be `Cortex-M4`.
- `default_toolchain` is not defined in `TEENSY3_1`, but since it is defined in `Target`, `TEENSY3_1` borrows it, so the value of `default_toolchain` for `TEENSY3_1` will be `ARM`.
A target can add properties that don't exist in its parent(s). For example, `OUTPUT_EXT` is defined in `TEENSY3_1`, but doesn't exist in `Target`.
It's possible to inherit from more than one target. For example:
```
"ImaginaryTarget": {
"inherits": ["Target", "TEENSY3_1"]
}
```
In this case, `ImaginaryTarget` inherits the properties of both `Target` and `TEENSY3_1`, so:
- the value of `ImaginaryTarget.default_toolchain` will be `ARM` (from `Target`)
- the value of `ImaginaryTarget.OUTPUT_EXT` will be `hex` (from `TEENSY3_1`).
- the value of `ImaginaryTarget.core` will be `null` (from `Target`, since that's the first parent of `ImaginaryTarget` that defines `core`).
Avoid using multiple inheritance for your targets if possible, since it can get pretty tricky to figure out how a property is inherited if multiple inheritance is used. If you have to use multiple inheritance, keep in mind that the mbed target description mechanism uses the old (pre 2.3) Python mechanism for finding the method resolution order:
- look for the property in the current target.
- if not found, look for the property in the first target's parent, then in the parent of the parent and so on.
- if not found, look for the property in the rest of the target's parents, relative to the current inheritance level.
For more details about the Python method resolution order, check for example [this link](http://makina-corpus.com/blog/metier/2014/python-tutorial-understanding-python-mro-class-search-path).
## core
The name of the ARM core used by the target.
Possible values: `"Cortex-M0"`, `"Cortex-M0+"`, `"Cortex-M1"`, `"Cortex-M3"`, `"Cortex-M4"`, `"Cortex-M4F"`, `"Cortex-M7"`, `"Cortex-M7F"`, `"Cortex-A9"`
## public
Some mbed targets might be defined solely for the purpose of serving as an inheritance base for other targets (as opposed to being used to build mbed code). When such a target is defined, its description must have the `public` property set to `false` to prevent the mbed build system from considering it as a build target. An example is the `Target` target shown in a previous paragraph.
If `public` is not defined for a target, it defaults to `true`.
Note that unlike other target properties, **the value of `public` is not inherited from a parent to its children**.
## macros, macros_add, macros_remove
The macros in this list will be defined when compiling mbed code. The macros can be defined with or without a value. For example, the declaration `"macros": ["NO_VALUE", "VALUE=10"]` will add these definitions to the compiler's command line: `-DNO_VALUE -DVALUE=10`.
When target inheritance is used, it's possible to alter the values of `macros` in inherited targets without re-defining `macros` completely:
- an inherited target can use `macros_add` to add its own macros.
- an inherited target can use `macros_remove` to remove macros defined by its parents.
For example, in this configuration:
```
"TargetA": {
"macros": ["PARENT_MACRO1", "PARENT_MACRO2"]
},
"TargetB": {
"inherits": ["TargetA"],
"macros_add": ["CHILD_MACRO1"],
"macros_remove": ["PARENT_MACRO2"]
}
```
the value of `TargetB.macros` will be `["PARENT_MACRO1", "CHILD_MACRO1"]`.
## extra_labels, extra_labels_add, extra_labels_remove
The list of **labels** defines how the build system looks for sources, libraries, include directories and any other additional files that are needed at compile time. `extra_labels` can be used to make the build system aware of additional directories that must be scanned for such files.
If target inheritance is used, it's possible to alter the values of `extra_labels` using `extra_labels_add` and `extra_labels_remove`. This is similar to the `macros_add` and `macros_remove` mechanism described in the previous paragraph.
## features, features_add, features_remove
The list of **features** defines what hardware a device has.
This allows allowing mbed, libraries, or application source code to select between different implementations of drivers based on hardware availability, to selectively compile drivers for only the hardware that exists, or to test only the tests that apply to a particular platform.
If target inheritance is used, it's possible to alter the values of `features` using `features_add` and `features_remove`. This is similar to the `macros_add` and `macros_remove` mechanism described in the previous two paragraphs.
## supported_toolchains
This is the list of toolchains that can be used to compile code for the target. The known toolchains are `ARM`, `uARM`, `GCC_ARM`, `GCC_CR`, `IAR`.
## default_toolchain
The name of the toolchain that will be used by default to compile this target (if another toolchain is not specified). Possible values are `ARM` or `uARM`.
## post_binary_hook
Some mbed targets require specific actions for generating a binary image that can be flashed to the target. If that's the case, these specific actions can be specified using the `post_binary_hook` property and custom Python code. For the `TEENSY3_1` target above, the definition of `post_binary_hook` looks like this:
```
"post_binary_hook": {
"function": "TEENSY3_1Code.binary_hook",
"toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
}
```
Following this definition, the build system will call the function `binary_hook` in the `TEENSY3_1Code` class after the initial binary image for the target is generated. The definition of the `TEENSY3_1Code` class **must** exist in the *targets.py* file. Since `toolchains` is also specified, `binary_hook` will only be called if the toolchain used for compiling the code is either `ARM_STD`, `ARM_MICRO` or `GCC_ARM`. Note that specifying `toolchains` is optional: if it's not specified, the hook will be called no matter what toolchain is used.
As for the `binary_hook` code, this is how it looks in *targets.py*:
```
class TEENSY3_1Code:
@staticmethod
def binary_hook(t_self, resources, elf, binf):
from intelhex import IntelHex
binh = IntelHex()
binh.loadbin(binf, offset = 0)
with open(binf.replace(".bin", ".hex"), "w") as f:
binh.tofile(f, format='hex')
```
In this case, it converts the output file (`binf`) from binary format to Intel HEX format.
The hook code can look quite different between different targets. Take a look at the other classes in *targets.py* for more examples of hook code.
## device_name
This property is used to pass necessary data for exporting the mbed code to various 3rd party tools and IDEs.
Please see [exporters.md](exporters.md) for information about this field.

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# Testing in mbed OS 5
The way tests are run and compiled in mbed OS 5 is substantially different from previous versions of mbed. Previously, tests were located in one known location and a python file (`tools/tests.py`) kept track of their dependencies, capabilities, and configurations. mbed OS 5 has adopted a more distributed approach to testing. Test code lives alongside the application code, and which is dynamically discovered by the test tools.
## Table of Contents
- [Using tests](#using-tests)
- [Test code structure](#test-code-structure)
- [Test discovery](#test-discovery)
- [Test names](#test-names)
- [Building tests](#building-tests)
- [Building process](#building-process)
- [App config](#app-config)
- [Running tests](#running-tests)
- [Writing tests](#writing-tests)
- [Debugging tests](#debugging-tests)
- [Exporting tests](#exporting-tests)
- [Running a test while debugging](#running-a-test-while-debugging)
- [Known issues](#known-issues)
## Using tests
### Test code structure
Tests can exist throughout mbed OS and your project's code. They are located under a special directory called `TESTS` (case is important!).
Placing code under this directory means it will be ignored when building applications and libraries. This code is only ever used when building tests. This is important since all tests require a `main()` function, and building it with your application would cause multiple `main()` functions to be defined.
In addition to being placed under a `TESTS` directory, test sources must exist under two other directories: a test group directory and a test case directory. The following are an examples of this structure:
```
myproject/TESTS/test_group/test_case_1
```
In this example, `myproject` is the project root and all the source files under the `test_case_1` directory will be included in the test. Any other source files from the OS, libraries, and your project that apply to your target's configuration will also be included in the build of your test.
**Note:** Both the test group and test case directory can be named anything you like. However, the `TESTS` directory **must** be named `TESTS` for the tools to detect the test cases correctly.
#### Test discovery
Since test cases can exist throughout a project, the tools must find them in your project's file structure before building them. This is done by searching for paths that match the pattern detailed above in the [Test code structure](#test-code-structure) section.
Test discovery also obeys the same rules that are used when building your project. This means that tests that are placed under a directory with a prefix like `TARGET_`, `TOOLCHAIN_`, or `FEATURE_` will only be discovered, built, and run if your current configuration matches this prefix.
For example, if you place a test under the directory `FEATURE_BLE` with the following path:
```
myproject/mbed-os/features/FEATURE_BLE/TESTS/ble_tests/unit_test
```
This test case will only be discovered if the target being testing supports the BLE feature. Otherwise, the test will be ignored.
Generally, a test should not be placed under a `TARGET_` or `TOOLCHAIN_` directory, since most tests should be designed to work for all target and toolchain configurations.
Tests can also be completely ignored by using the `.mbedignore` file described [here](../ignoring_files_from_build.md)
#### Test names
A test case is named from its position in your project's file structure. For instance, in the above example, a test case with the path `myproject/TESTS/test_group/test_case_1` would be named `tests-test_group-test_case_1`. You will notice that the name is created by joining the directories that make up the path to the test case with a "dash" (`-`) character. This will be a unique name to identify the test case. You will see this name used throughout the build and testing process.
### Building tests
Tests can be built easily through mbed CLI. For information on using mbed CLI, please see its [documentation](https://github.com/ARMmbed/mbed-cli).
When tests are built for a target and a given toolchain, the available tests are first discovered, then built in series. You can also create a "test specification" file, which can be used by our testing tools to run automated hardware tests. For more information on the test specification file, please see the documentation [here](https://github.com/ARMmbed/greentea#test-specification-json-formatted-input).
#### Building process
The process for building tests is handled by the `test.py` script (not to be confused with `tests.py`) located under the `tools` directory. This handles the discovery and building of all test cases for a given target and toolchain.
The full build process is:
1. Build the non-test code (all code not under a `TESTS` folder), but do not link it. The resulting object files are placed in the build directory.
1. Find all tests that match the given target and toolchain.
1. For each discovered test, build all of its source files and link it with the non-test code that was built in step 1.
1. If specified, create a test specification file and place it in the given directory for use by testing tools. This is placed in the build directory by default when using mbed CLI.
#### App config
When building an mbed application, the presence of a `mbed_app.json` file allows you to set or override different config settings from libraries and targets. However, because the tests share a common build, this can cause issues when tests have different configurations that affect the OS.
The build system will look for an `mbed_app.json` file in your shared project files (any directory not inside of a `TESTS` folder). If this is found, this configuration file will be used for both the non-test code as well as each test case inside your project's source tree. If there is more than one `mbed_app.json` files in the source tree, the config system will error.
If you need to test with multiple configurations, then you can use the `--app-config` option. This will override the search for an `mbed_app.json` file and use the config file you specify for the build.
### Running tests
Automated tests can be run easily through mbed CLI. For information on using mbed CLI, please see its documentation.
The testing process requires that the tests are built and that a test specification JSON file exists that describes these available tests. The test specification format is detailed [here](https://github.com/ARMmbed/greentea#test-specification-json-formatted-input).
The actual testing process is handled by the Greentea tool. To read more about this tool, please visit its [GitHub repository](https://github.com/ARMmbed/greentea).
### Writing tests
You can write tests for your own project, or add more tests to mbed OS. Tests are written using the [Greentea client](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/greentea-client), [UNITY](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/unity), and [utest](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/utest) frameworks, located in `/features/frameworks`. Below is an example test that uses all of these frameworks:
```c++
#include "mbed.h"
#include "greentea-client/test_env.h"
#include "unity.h"
#include "utest.h"
#include "rtos.h"
using namespace utest::v1;
// A test that returns successfully is considered successful
void test_success() {
TEST_ASSERT(true);
}
// Tests that assert are considered failing
void test_failure() {
TEST_ASSERT(false);
}
utest::v1::status_t test_setup(const size_t number_of_cases) {
// Setup Greentea using a reasonable timeout in seconds
GREENTEA_SETUP(40, "default_auto");
return verbose_test_setup_handler(number_of_cases);
}
// Test cases
Case cases[] = {
Case("Testing success test", test_success),
Case("Testing failure test", test_failure),
};
Specification specification(test_setup, cases);
// Entry point into the tests
int main() {
return !Harness::run(specification);
}
```
This test will first run a case that succeeds, then a case that fails. This is a good template to use when creating tests. For more complex testing examples, please see the documentation for [utest](https://github.com/ARMmbed/mbed-os/tree/master/features/frameworks/utest).
## Debugging tests
Debugging tests is a crucial part of the development and porting process. This section will cover exporting the test, then driving the test with the test tools while the target is attached to a debugger.
### Exporting tests
Currently, the easiest way to export a test is to copy the test's source code from its test directory to your project's root. This way it will be treated like a normal application by the tools.
You can find the path to the test you wish to export by running the following command:
```
mbed test --compile-list -n <test name>
```
Once you've copied all of the test's source files to your project root, go ahead and export your project:
```
mbed export -i <IDE name>
```
Your exported project should now be in `projectfiles/<IDE>_<target>`. Go ahead and open this project in your IDE.
### Running a test while debugging
Assuming your test was exported correctly to your IDE, go ahead and build the project and load it onto your target via your debugger.
Bring the target out of reset and run the program. Your target will now be waiting for a synchronizing character string to be sent from the test tools over the serial port. Do not run the `mbed test` commands, because that will attempt to flash the device, which you've already done with your IDE.
Instead, the underlying test tools can be used to drive the test. [htrun](https://github.com/ARMmbed/htrun) is the tool that needs to be used in this case. This is installed when you install the requirements for mbed OS. However, if you do not have it installed you can do this by running `pip install mbed-host-tests`.
First, find your target's serial port by running the following command:
```
$ mbed detect
[mbed] Detected KL46Z, port COM270, mounted D:
...
```
From the output, take note of your target's serial port (in this case, it's `COM270`).
Run the following command when your device is running the test in your debugger:
```
mbedhtrun --skip-flashing --skip-reset -p <serial port>:9600
```
Replace `<serial port>` with the serial port you found by running `mbed detect` above.
So for the example above, the command would be:
```
mbedhtrun --skip-flashing --skip-reset -p COM270:9600
```
This detects your attached target and drives the test. At this point the test will proceed and allow you to debug it. If you need to rerun the test, simply reset the device with your debugger, run the program, and run the same command.
For an explanation of the arguments used in this command, please run `mbedhtrun --help`.
## Known issues
- There cannot be a `main()` function outside of a `TESTS` directory when building and running tests. This is because this function will be included in the non-test code build as described in the [Building process](#building-process) section. When the test code is compiled and linked with the non-test code build, a linker error will occur due to their being multiple `main()` functions defined. For this reason, please either rename your main application file if you need to build and run tests or use a different project.
- **NOTE:** This does not affect building projects or applications, just building and running tests.

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features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c
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@ -23,7 +23,7 @@
// In this case, bits which are equal to 0 are the bits reserved in this register
#define SCB_ICSR_RESERVED_BITS_MASK 0x9E43F03F
void sleep(void)
void hal_sleep(void)
{
// ensure debug is disconnected if semihost is enabled....
@ -64,7 +64,7 @@ void sleep(void)
}
}
void deepsleep(void)
void hal_deepsleep(void)
{
sleep();
// NRF_POWER->SYSTEMOFF=1;

5
features/FEATURE_LWIP/TESTS/mbedmicro-net/host_tests/udp_shotgun.py
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@ -65,7 +65,10 @@ class UDPEchoClientTest(BaseHostTest):
:return:
"""
s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
s.connect((target_ip, 0)) # Target IP, Any port
try:
s.connect((target_ip, 0)) # Target IP, any port
except socket.error:
s.connect((target_ip, 8000)) # Target IP, 'random' port
ip = s.getsockname()[0]
s.close()
return ip

4
features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_echo_parallel/main.cpp
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@ -42,6 +42,10 @@ private:
Thread thread;
public:
// Limiting stack size to 1k
Echo(): thread(osPriorityNormal, 1024) {
}
void start() {
osStatus status = thread.start(callback(this, &Echo::echo));
TEST_ASSERT_EQUAL(osOK, status);

4
features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_echo_parallel/main.cpp
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@ -46,6 +46,10 @@ private:
Thread thread;
public:
// Limiting stack size to 1k
Echo(): thread(osPriorityNormal, 1024) {
}
void start() {
osStatus status = thread.start(callback(this, &Echo::echo));
TEST_ASSERT_EQUAL(osOK, status);

0
features/frameworks/greentea-client/source/test_env.cpp → features/frameworks/greentea-client/source/greentea_test_env.cpp
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hal/sleep_api.h
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@ -41,7 +41,7 @@ extern "C" {
* Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
* able to access the LocalFileSystem
*/
void sleep(void);
void hal_sleep(void);
/** Send the microcontroller to deep sleep
*
@ -56,7 +56,7 @@ void sleep(void);
* Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
* able to access the LocalFileSystem
*/
void deepsleep(void);
void hal_deepsleep(void);
#ifdef __cplusplus
}

1
mbed.h
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@ -92,6 +92,7 @@
#include "drivers/InterruptIn.h"
#include "platform/wait_api.h"
#include "hal/sleep_api.h"
#include "platform/sleep.h"
#include "platform/rtc_time.h"
// mbed Non-hardware components

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platform/sleep.h Normal file
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@ -0,0 +1,85 @@
/** \addtogroup platform */
/** @{*/
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_SLEEP_H
#define MBED_SLEEP_H
#include "sleep_api.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Send the microcontroller to sleep
*
* @note This function can be a noop if not implemented by the platform.
* @note This function will only put device to sleep in release mode (small profile or when NDEBUG is defined).
*
* The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
* system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
* dynamic power used by the processor, memory systems and buses. The processor, peripheral and
* memory state are maintained, and the peripherals continue to work and can generate interrupts.
*
* The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
*
* @note
* The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
* Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
* able to access the LocalFileSystem
*/
__INLINE static void sleep(void)
{
#ifdef NDEBUG
#if DEVICE_SLEEP
hal_sleep();
#endif /* DEVICE_SLEEP */
#endif /* NDEBUG */
}
/** Send the microcontroller to deep sleep
*
* @note This function can be a noop if not implemented by the platform.
* @note This function will only put device to sleep in release mode (small profile or when NDEBUG is defined).
*
* This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
* has the same sleep features as sleep plus it powers down peripherals and clocks. All state
* is still maintained.
*
* The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
*
* @note
* The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
* Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
* able to access the LocalFileSystem
*/
__INLINE static void deepsleep(void)
{
#ifdef NDEBUG
#if DEVICE_SLEEP
hal_deepsleep();
#endif /* DEVICE_SLEEP */
#endif /* NDEBUG */
}
#ifdef __cplusplus
}
#endif
#endif
/** @}*/

4
targets/TARGET_ARM_SSG/TARGET_BEETLE/sleep.c
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@ -16,13 +16,13 @@
#include "sleep_api.h"
#include "cmsis.h"
void sleep(void)
void hal_sleep(void)
{
SystemPowerSuspend(POWER_MODE_SLEEP);
SystemPowerResume(POWER_MODE_SLEEP);
}
void deepsleep(void)
void hal_deepsleep(void)
{
SystemPowerSuspend(POWER_MODE_DEEP_SLEEP);
SystemPowerResume(POWER_MODE_DEEP_SLEEP);

4
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/sleep_api.c
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@ -25,7 +25,7 @@
* @param[void] void
* @return void
*/
void sleep(void)
void hal_sleep(void)
{
#if (SAMD21) || (SAMR21)
system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE_2);
@ -43,7 +43,7 @@ void sleep(void)
* @param[void] void
* @return void
*/
void deepsleep(void)
void hal_deepsleep(void)
{
system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
system_sleep();

4
targets/TARGET_Atmel/TARGET_SAM_CortexM4/sleep_api.c
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@ -24,7 +24,7 @@
* @param[void] void
* @return void
*/
void sleep(void)
void hal_sleep(void)
{
enum sleepmgr_mode sleep_mode;
@ -40,7 +40,7 @@ void sleep(void)
* @param[void] void
* @return void
*/
void deepsleep(void)
void hal_deepsleep(void)
{
enum sleepmgr_mode sleep_mode;

4
targets/TARGET_Freescale/TARGET_K20XX/sleep.c
View File

@ -17,7 +17,7 @@
#include "cmsis.h"
//Normal wait mode
void sleep(void)
void hal_sleep(void)
{
SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
@ -27,7 +27,7 @@ void sleep(void)
}
//Very low-power stop mode
void deepsleep(void)
void hal_deepsleep(void)
{
//Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
uint8_t ADC_HSC = 0;

4
targets/TARGET_Freescale/TARGET_KLXX/sleep.c
View File

@ -18,7 +18,7 @@
#include "PeripheralPins.h"
//Normal wait mode
void sleep(void)
void hal_sleep(void)
{
SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
@ -28,7 +28,7 @@ void sleep(void)
}
//Very low-power stop mode
void deepsleep(void)
void hal_deepsleep(void)
{
//Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
uint8_t ADC_HSC = 0;

82
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/trng_api.c Normal file
View File

@ -0,0 +1,82 @@
/*
* Hardware entropy collector for the K22F, using Freescale's RNGA
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#if defined(DEVICE_TRNG)
#include <stdlib.h>
#include "cmsis.h"
#include "fsl_common.h"
#include "fsl_clock.h"
#include "trng_api.h"
void trng_init(trng_t *obj)
{
(void)obj;
CLOCK_EnableClock(kCLOCK_Rnga0);
CLOCK_DisableClock(kCLOCK_Rnga0);
CLOCK_EnableClock(kCLOCK_Rnga0);
}
void trng_free(trng_t *obj)
{
(void)obj;
CLOCK_DisableClock(kCLOCK_Rnga0);
}
/*
* Get one byte of entropy from the RNG, assuming it is up and running.
* As recommended, get only one bit of each output.
*/
static void trng_get_byte(unsigned char *byte)
{
size_t bit;
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
for( bit = 0; bit < 8; bit++ )
{
while((RNG->SR & RNG_SR_OREG_LVL_MASK) == 0 );
*byte |= (RNG->OR & 1) << bit;
}
}
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
(void)obj;
size_t i;
/* Set "Interrupt Mask", "High Assurance" and "Go",
* unset "Clear interrupt" and "Sleep" */
RNG->CR = RNG_CR_INTM_MASK | RNG_CR_HA_MASK | RNG_CR_GO_MASK;
for (i = 0; i < length; i++) {
trng_get_byte(output + i);
}
/* Just be extra sure that we didn't do it wrong */
if ((RNG->SR & RNG_SR_SECV_MASK) != 0) {
return -1;
}
*output_length = length;
return 0;
}
#endif

4
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/sleep.c
View File

@ -18,14 +18,14 @@
#include "fsl_smc.h"
#include "fsl_clock_config.h"
void sleep(void)
void hal_sleep(void)
{
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeWait(SMC);
}
void deepsleep(void)
void hal_deepsleep(void)
{
#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT)
mcg_mode_t mode = CLOCK_GetMode();

4
targets/TARGET_Maxim/TARGET_MAX32600/sleep.c
View File

@ -41,7 +41,7 @@
static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
// Normal wait mode
void sleep(void)
void hal_sleep(void)
{
// Normal sleep mode for ARM core
SCB->SCR = 0;
@ -70,7 +70,7 @@ static void clearAllGPIOWUD(void)
}
// Low-power stop mode
void deepsleep(void)
void hal_deepsleep(void)
{
__disable_irq();

4
targets/TARGET_Maxim/TARGET_MAX32610/sleep.c
View File

@ -41,7 +41,7 @@
static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
// Normal wait mode
void sleep(void)
void hal_sleep(void)
{
// Normal sleep mode for ARM core
SCB->SCR = 0;
@ -70,7 +70,7 @@ static void clearAllGPIOWUD(void)
}
// Low-power stop mode
void deepsleep(void)
void hal_deepsleep(void)
{
__disable_irq();

4
targets/TARGET_Maxim/TARGET_MAX32620/sleep.c
View File

@ -54,7 +54,7 @@ static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
static int restore_usb;
static usb_state_t usb_state;
void sleep(void)
void hal_sleep(void)
{
// Normal sleep mode for ARM core
SCB->SCR = 0;
@ -109,7 +109,7 @@ static void usb_wakeup(void)
}
// Low-power stop mode
void deepsleep(void)
void hal_deepsleep(void)
{
unsigned int part_rev = MXC_PWRMAN->mask_id0 & MXC_F_PWRMAN_MASK_ID0_REVISION_ID;

6
targets/TARGET_Maxim/TARGET_MAX32625/sleep.c
View File

@ -34,13 +34,13 @@
#include "sleep_api.h"
#include "lp.h"
void sleep(void)
void hal_sleep(void)
{
LP_EnterLP2();
}
// Low-power stop mode
void deepsleep(void)
void hal_deepsleep(void)
{
sleep();
hal_sleep();
}

6
targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c
View File

@ -18,7 +18,7 @@
#include "mbed_interface.h"
#include "toolchain.h"
MBED_WEAK void sleep(void)
void hal_sleep(void)
{
// ensure debug is disconnected if semihost is enabled....
NRF_POWER->TASKS_LOWPWR = 1;
@ -26,8 +26,8 @@ MBED_WEAK void sleep(void)
__WFE();
}
MBED_WEAK void deepsleep(void)
void hal_deepsleep(void)
{
sleep();
hal_sleep();
// NRF_POWER->SYSTEMOFF=1;
}

181
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_DELTA_DFCM_NNN50/PinNames.h Normal file
View File

@ -0,0 +1,181 @@
/* mbed Microcontroller Library
* Copyright (c) 2017 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
//NORMAL PINS...
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
P0_31 = p31,
LED1 = p13,
LED2 = p23,
LED3 = p24,
LED4 = p25,
BUTTON1 = p20,
BUTTON2 = p21,
BUTTON3 = p22,
BUTTON4 = p0,
RX_PIN_NUMBER = p16,
TX_PIN_NUMBER = p17,
CTS_PIN_NUMBER = p20,
RTS_PIN_NUMBER = p21,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPI_PSELMOSI0 = p15,
SPI_PSELMISO0 = p9,
SPI_PSELSS0 = p29,
SPI_PSELSCK0 = p11,
SPI_PSELMOSI1 = p17,
SPI_PSELMISO1 = p20,
SPI_PSELSS1 = p16,
SPI_PSELSCK1 = p21,
SPIS_PSELMOSI = p17,
SPIS_PSELMISO = p20,
SPIS_PSELSS = p16,
SPIS_PSELSCK = p21,
I2C_SDA0 = p31,
I2C_SCL0 = p30,
D0 = p16,
D1 = p17,
D2 = p20,
D3 = p21,
D4 = p22,
D5 = p0,
D6 = p13,
D7 = p23,
D8 = p24,
D9 = p25,
D10 = p29,
D11 = p15,
D12 = p9,
D13 = p11,
D14 = p30,
D15 = p31,
A0 = p3,
A1 = p4,
A2 = p5,
A3 = p6,
A4 = p26,
A5 = p27,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

26
targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F412ZG/PortNames.h → targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_DELTA_DFCM_NNN50/device.h
View File

@ -1,5 +1,7 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@ -13,25 +15,9 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#ifdef __cplusplus
extern "C" {
#endif
#include "objects.h"
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7
} PortName;
#ifdef __cplusplus
}
#endif
#endif

48
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_DELTA_DFCM_NNN50/mbed_overrides.c Normal file
View File

@ -0,0 +1,48 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "PinNames.h"
void mbed_sdk_init()
{
char* debug_date = __DATE__;
char* debug_time = __TIME__;
// Default RF switch setting, pull p19 to low and p28 to high for turning antenna switch to BLE radiated path
NRF_GPIO->PIN_CNF[p19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->PIN_CNF[p28] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
NRF_GPIO->OUTSET = (GPIO_OUTCLR_PIN28_High << GPIO_OUTCLR_PIN28_Pos);
// Config External Crystal to 32MHz
NRF_CLOCK->XTALFREQ = 0x00;
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
NRF_CLOCK->TASKS_HFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) {
// Do nothing.
}
}

6
targets/TARGET_NORDIC/TARGET_NRF5/sleep.c
View File

@ -25,7 +25,7 @@
#define FPU_EXCEPTION_MASK 0x0000009F
void sleep(void)
void hal_sleep(void)
{
// ensure debug is disconnected if semihost is enabled....
@ -73,8 +73,8 @@ void sleep(void)
}
}
void deepsleep(void)
void hal_deepsleep(void)
{
sleep();
hal_sleep();
// NRF_POWER->SYSTEMOFF=1;
}

4
targets/TARGET_NUVOTON/TARGET_M451/sleep.c
View File

@ -38,7 +38,7 @@ int pwmout_allow_powerdown(void);
/**
* Enter Idle mode.
*/
void sleep(void)
void hal_sleep(void)
{
struct sleep_s sleep_obj;
sleep_obj.powerdown = 0;
@ -49,7 +49,7 @@ void sleep(void)
/**
* Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
*/
void deepsleep(void)
void hal_deepsleep(void)
{
struct sleep_s sleep_obj;
sleep_obj.powerdown = 1;

4
targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c
View File

@ -38,7 +38,7 @@ int pwmout_allow_powerdown(void);
/**
* Enter Idle mode.
*/
void sleep(void)
void hal_sleep(void)
{
struct sleep_s sleep_obj;
sleep_obj.powerdown = 0;
@ -49,7 +49,7 @@ void sleep(void)
/**
* Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
*/
void deepsleep(void)
void hal_deepsleep(void)
{
struct sleep_s sleep_obj;
sleep_obj.powerdown = 1;

4
targets/TARGET_NXP/TARGET_LPC11U6X/sleep.c
View File

@ -19,7 +19,7 @@
#if DEVICE_SLEEP
void sleep(void) {
void hal_sleep(void) {
#if (DEVICE_SEMIHOST == 1)
// ensure debug is disconnected
@ -37,7 +37,7 @@ void sleep(void) {
}
void deepsleep(void) {
void hal_deepsleep(void) {
#if (DEVICE_SEMIHOST == 1)
// ensure debug is disconnected

4
targets/TARGET_NXP/TARGET_LPC11UXX/sleep.c
View File

@ -17,7 +17,7 @@
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void) {
void hal_sleep(void) {
// ensure debug is disconnected
#if DEVICE_SEMIHOST
mbed_interface_disconnect();
@ -59,7 +59,7 @@ void sleep(void) {
* We treat a deepsleep() as a normal sleep().
*/
void deepsleep(void) {
void hal_deepsleep(void) {
// ensure debug is disconnected
#if DEVICE_SEMIHOST
mbed_interface_disconnect();

4
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/sleep.c
View File

@ -17,7 +17,7 @@
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void) {
void hal_sleep(void) {
// PCON[DPDEN] set to sleep
LPC_PMU->PCON = 0x0;
@ -29,7 +29,7 @@ void sleep(void) {
__WFI();
}
void deepsleep(void) {
void hal_deepsleep(void) {
// PCON[DPDEN] set to deepsleep
LPC_PMU->PCON = 0;

4
targets/TARGET_NXP/TARGET_LPC13XX/sleep.c
View File

@ -17,7 +17,7 @@
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void) {
void hal_sleep(void) {
// PCON[PD] set to sleep
LPC_PMU->PCON = 0x0;
@ -28,7 +28,7 @@ void sleep(void) {
__WFI();
}
void deepsleep(void) {
void hal_deepsleep(void) {
// PCON[PD] set to deepsleep
LPC_PMU->PCON = 0x1;

6
targets/TARGET_NXP/TARGET_LPC176X/sleep.c
View File

@ -17,7 +17,7 @@
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void) {
void hal_sleep(void) {
#if (DEVICE_SEMIHOST == 1)
// ensure debug is disconnected
@ -60,7 +60,7 @@ void sleep(void) {
* We treat a deepsleep() as a normal sleep().
*/
void deepsleep(void) {
void hal_deepsleep(void) {
#if (DEVICE_SEMIHOST == 1)
// ensure debug is disconnected
@ -68,5 +68,5 @@ void deepsleep(void) {
#endif
// PCON[PD] set to deepsleep
sleep();
hal_sleep();
}

6
targets/TARGET_NXP/TARGET_LPC408X/sleep.c
View File

@ -17,7 +17,7 @@
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void) {
void hal_sleep(void) {
LPC_SC->PCON = 0x0;
// SRC[SLEEPDEEP] set to 0 = sleep
@ -52,6 +52,6 @@ void sleep(void) {
*
* We treat a deepsleep() as a normal sleep().
*/
void deepsleep(void) {
sleep();
void hal_deepsleep(void) {
hal_sleep();
}

6
targets/TARGET_NXP/TARGET_LPC43XX/sleep.c
View File

@ -19,7 +19,7 @@
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void) {
void hal_sleep(void) {
// SRC[SLEEPDEEP] set to 0 = sleep
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
@ -31,6 +31,6 @@ void sleep(void) {
/*
* ToDo: Implement deepsleep()
*/
void deepsleep(void) {
sleep();
void hal_deepsleep(void) {
hal_sleep();
}

6
targets/TARGET_NXP/TARGET_LPC81X/sleep.c
View File

@ -20,7 +20,7 @@
//#define DEEPSLEEP
#define POWERDOWN
void sleep(void) {
void hal_sleep(void) {
//Normal sleep mode for PCON:
LPC_PMU->PCON &= ~0x03;
@ -36,7 +36,7 @@ void sleep(void) {
//Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly
#ifdef DEEPSLEEP
void deepsleep(void) {
void hal_deepsleep(void) {
//Deep sleep in PCON
LPC_PMU->PCON &= ~0x03;
LPC_PMU->PCON |= 0x01;
@ -59,7 +59,7 @@ void deepsleep(void) {
#endif
#ifdef POWERDOWN
void deepsleep(void) {
void hal_deepsleep(void) {
//Powerdown in PCON
LPC_PMU->PCON &= ~0x03;
LPC_PMU->PCON |= 0x02;

4
targets/TARGET_NXP/TARGET_LPC82X/sleep.c
View File

@ -20,7 +20,7 @@
//#define DEEPSLEEP
#define POWERDOWN
void sleep(void)
void hal_sleep(void)
{
//Normal sleep mode for PCON:
LPC_PMU->PCON &= ~0x03;
@ -34,7 +34,7 @@ void sleep(void)
// Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly
void deepsleep(void)
void hal_deepsleep(void)
{
//Deep sleep in PCON
LPC_PMU->PCON &= ~0x03;

93
targets/TARGET_STM/PinNamesTypes.h Normal file
View File

@ -0,0 +1,93 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PINNAMESTYPES_H
#define MBED_PINNAMESTYPES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// The last mode is only valid for specific families, so we put it in the end
#define STM_MODE_ANALOG_ADC_CONTROL (13)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

2
targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h → targets/TARGET_STM/PortNames.h
View File

@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

49
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -241,14 +202,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -188,14 +149,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -157,14 +118,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

47
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PortNames.h
View File

@ -1,47 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2, /* used for compilation needs */
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -156,14 +117,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

47
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PortNames.h
View File

@ -1,47 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2, /* used for compilation needs */
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -184,14 +145,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -184,14 +145,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -185,14 +146,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -192,14 +153,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -203,14 +164,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -180,14 +141,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4
} PortName;
#ifdef __cplusplus
}
#endif
#endif

52
targets/TARGET_STM/TARGET_STM32F2/PortNames.h
View File

@ -1,52 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2016, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7,
PortI = 8
} PortName;
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -254,14 +215,6 @@ typedef enum {
#define STDIO_UART_RX SERIAL_RX
#define STDIO_UART UART_3
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -244,14 +205,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PortNames.h
View File

@ -1,49 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

138
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/stm32f303xc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303xc.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File.
*
* This file contains:
@ -2397,9 +2397,6 @@ typedef struct
#define COMP1_CSR_COMP1INSEL_0 (0x1U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
#define COMP1_CSR_COMP1INSEL_1 (0x2U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
#define COMP1_CSR_COMP1INSEL_2 (0x4U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
#define COMP1_CSR_COMP1NONINSEL_Pos (7U)
#define COMP1_CSR_COMP1NONINSEL_Msk (0x1U << COMP1_CSR_COMP1NONINSEL_Pos) /*!< 0x00000080 */
#define COMP1_CSR_COMP1NONINSEL COMP1_CSR_COMP1NONINSEL_Msk /*!< COMP1 non inverting input select */
#define COMP1_CSR_COMP1OUTSEL_Pos (10U)
#define COMP1_CSR_COMP1OUTSEL_Msk (0xFU << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */
@ -2438,12 +2435,11 @@ typedef struct
#define COMP2_CSR_COMP2MODE_0 (0x1U << COMP2_CSR_COMP2MODE_Pos) /*!< 0x00000004 */
#define COMP2_CSR_COMP2MODE_1 (0x2U << COMP2_CSR_COMP2MODE_Pos) /*!< 0x00000008 */
#define COMP2_CSR_COMP2INSEL_Pos (4U)
#define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
#define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */
#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
#define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
#define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
#define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
#define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
#define COMP2_CSR_COMP2NONINSEL_Pos (7U)
#define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
#define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */
@ -2534,12 +2530,11 @@ typedef struct
#define COMP4_CSR_COMP4MODE_0 (0x1U << COMP4_CSR_COMP4MODE_Pos) /*!< 0x00000004 */
#define COMP4_CSR_COMP4MODE_1 (0x2U << COMP4_CSR_COMP4MODE_Pos) /*!< 0x00000008 */
#define COMP4_CSR_COMP4INSEL_Pos (4U)
#define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
#define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */
#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
#define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
#define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
#define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
#define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
#define COMP4_CSR_COMP4NONINSEL_Pos (7U)
#define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
#define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */
@ -2630,12 +2625,11 @@ typedef struct
#define COMP6_CSR_COMP6MODE_0 (0x1U << COMP6_CSR_COMP6MODE_Pos) /*!< 0x00000004 */
#define COMP6_CSR_COMP6MODE_1 (0x2U << COMP6_CSR_COMP6MODE_Pos) /*!< 0x00000008 */
#define COMP6_CSR_COMP6INSEL_Pos (4U)
#define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
#define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */
#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
#define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
#define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
#define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
#define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
#define COMP6_CSR_COMP6NONINSEL_Pos (7U)
#define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
#define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */
@ -2729,12 +2723,11 @@ typedef struct
#define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */
#define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */
#define COMP_CSR_COMPxINSEL_Pos (4U)
#define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxNONINSEL_Pos (7U)
#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
@ -7183,9 +7176,6 @@ typedef struct
#define EXTI_IMR_MR26_Pos (26U)
#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27_Pos (27U)
#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28_Pos (28U)
#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
@ -7227,7 +7217,9 @@ typedef struct
#define EXTI_IMR_IM24 EXTI_IMR_MR24
#define EXTI_IMR_IM25 EXTI_IMR_MR25
#define EXTI_IMR_IM26 EXTI_IMR_MR26
#if defined(EXTI_IMR_MR27)
#define EXTI_IMR_IM27 EXTI_IMR_MR27
#endif
#define EXTI_IMR_IM28 EXTI_IMR_MR28
#define EXTI_IMR_IM29 EXTI_IMR_MR29
#define EXTI_IMR_IM30 EXTI_IMR_MR30
@ -7319,9 +7311,6 @@ typedef struct
#define EXTI_EMR_MR26_Pos (26U)
#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27_Pos (27U)
#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28_Pos (28U)
#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
@ -7363,7 +7352,9 @@ typedef struct
#define EXTI_EMR_EM24 EXTI_EMR_MR24
#define EXTI_EMR_EM25 EXTI_EMR_MR25
#define EXTI_EMR_EM26 EXTI_EMR_MR26
#if defined(EXTI_EMR_MR27)
#define EXTI_EMR_EM27 EXTI_EMR_MR27
#endif
#define EXTI_EMR_EM28 EXTI_EMR_MR28
#define EXTI_EMR_EM29 EXTI_EMR_MR29
#define EXTI_EMR_EM30 EXTI_EMR_MR30
@ -7473,6 +7464,24 @@ typedef struct
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
#if defined(EXTI_RTSR_TR23)
#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
#endif
#if defined(EXTI_RTSR_TR24)
#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
#endif
#if defined(EXTI_RTSR_TR25)
#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
#endif
#if defined(EXTI_RTSR_TR26)
#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
#endif
#if defined(EXTI_RTSR_TR27)
#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
#endif
#if defined(EXTI_RTSR_TR28)
#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
#endif
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
@ -7581,6 +7590,24 @@ typedef struct
#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
#if defined(EXTI_FTSR_TR23)
#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
#endif
#if defined(EXTI_FTSR_TR24)
#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
#endif
#if defined(EXTI_FTSR_TR25)
#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
#endif
#if defined(EXTI_FTSR_TR26)
#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
#endif
#if defined(EXTI_FTSR_TR27)
#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
#endif
#if defined(EXTI_FTSR_TR28)
#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
#endif
#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
@ -7689,6 +7716,24 @@ typedef struct
#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
#if defined(EXTI_SWIER_SWIER23)
#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
#endif
#if defined(EXTI_SWIER_SWIER24)
#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
#endif
#if defined(EXTI_SWIER_SWIER25)
#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
#endif
#if defined(EXTI_SWIER_SWIER26)
#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
#endif
#if defined(EXTI_SWIER_SWIER27)
#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
#endif
#if defined(EXTI_SWIER_SWIER28)
#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
#endif
#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
@ -7781,6 +7826,7 @@ typedef struct
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@ -7797,6 +7843,24 @@ typedef struct
#define EXTI_PR_PIF20 EXTI_PR_PR20
#define EXTI_PR_PIF21 EXTI_PR_PR21
#define EXTI_PR_PIF22 EXTI_PR_PR22
#if defined(EXTI_PR_PR23)
#define EXTI_PR_PIF23 EXTI_PR_PR23
#endif
#if defined(EXTI_PR_PR24)
#define EXTI_PR_PIF24 EXTI_PR_PR24
#endif
#if defined(EXTI_PR_PR25)
#define EXTI_PR_PIF25 EXTI_PR_PR25
#endif
#if defined(EXTI_PR_PR26)
#define EXTI_PR_PIF26 EXTI_PR_PR26
#endif
#if defined(EXTI_PR_PR27)
#define EXTI_PR_PIF27 EXTI_PR_PR27
#endif
#if defined(EXTI_PR_PR28)
#define EXTI_PR_PIF28 EXTI_PR_PR28
#endif
#define EXTI_PR_PIF29 EXTI_PR_PR29
#define EXTI_PR_PIF30 EXTI_PR_PR30
#define EXTI_PR_PIF31 EXTI_PR_PR31
@ -7818,6 +7882,7 @@ typedef struct
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
@ -7858,6 +7923,12 @@ typedef struct
/* References Defines */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
#if defined(EXTI_RTSR2_TR34)
#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
#endif
#if defined(EXTI_RTSR2_TR35)
#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
@ -7870,6 +7941,12 @@ typedef struct
/* References Defines */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
#if defined(EXTI_FTSR2_TR34)
#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
#endif
#if defined(EXTI_FTSR2_TR35)
#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
@ -7882,6 +7959,12 @@ typedef struct
/* References Defines */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
#if defined(EXTI_SWIER2_SWIER34)
#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
#endif
#if defined(EXTI_SWIER2_SWIER35)
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
@ -7894,6 +7977,13 @@ typedef struct
/* References Defines */
#define EXTI_PR2_PIF32 EXTI_PR2_PR32
#define EXTI_PR2_PIF33 EXTI_PR2_PR33
#if defined(EXTI_PR2_PR34)
#define EXTI_PR2_PIF34 EXTI_PR2_PR34
#endif
#if defined(EXTI_PR2_PR35)
#define EXTI_PR2_PIF35 EXTI_PR2_PR35
#endif
/******************************************************************************/
/* */
@ -10976,6 +11066,7 @@ typedef struct
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@ -12582,9 +12673,9 @@ typedef struct
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@ -12859,6 +12950,11 @@ typedef struct
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \

8
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/system_stm32f3xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/system_stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -174,14 +135,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

318
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/stm32f334x8.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f334x8.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
@ -6634,48 +6634,24 @@ typedef struct
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19_Pos (19U)
#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21_Pos (21U)
#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23_Pos (23U)
#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR_MR24_Pos (24U)
#define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR_MR25_Pos (25U)
#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR_MR26_Pos (26U)
#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27_Pos (27U)
#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28_Pos (28U)
#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR_MR29_Pos (29U)
#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR_MR30_Pos (30U)
#define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR_MR31_Pos (31U)
#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@ -6696,20 +6672,36 @@ typedef struct
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#if defined(EXTI_IMR_MR18)
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#endif
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
#if defined(EXTI_IMR_MR21)
#define EXTI_IMR_IM21 EXTI_IMR_MR21
#endif
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
#if defined(EXTI_IMR_MR24)
#define EXTI_IMR_IM24 EXTI_IMR_MR24
#endif
#define EXTI_IMR_IM25 EXTI_IMR_MR25
#if defined(EXTI_IMR_MR26)
#define EXTI_IMR_IM26 EXTI_IMR_MR26
#endif
#if defined(EXTI_IMR_MR27)
#define EXTI_IMR_IM27 EXTI_IMR_MR27
#endif
#if defined(EXTI_IMR_MR28)
#define EXTI_IMR_IM28 EXTI_IMR_MR28
#endif
#if defined(EXTI_IMR_MR29)
#define EXTI_IMR_IM29 EXTI_IMR_MR29
#endif
#define EXTI_IMR_IM30 EXTI_IMR_MR30
#if defined(EXTI_IMR_MR31)
#define EXTI_IMR_IM31 EXTI_IMR_MR31
#endif
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
@ -6770,48 +6762,24 @@ typedef struct
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19_Pos (19U)
#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21_Pos (21U)
#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23_Pos (23U)
#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR_MR24_Pos (24U)
#define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR_MR25_Pos (25U)
#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR_MR26_Pos (26U)
#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27_Pos (27U)
#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28_Pos (28U)
#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR_MR29_Pos (29U)
#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR_MR30_Pos (30U)
#define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR_MR31_Pos (31U)
#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@ -6832,20 +6800,36 @@ typedef struct
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#if defined(EXTI_EMR_MR18)
#define EXTI_EMR_EM18 EXTI_EMR_MR18
#endif
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
#if defined(EXTI_EMR_MR21)
#define EXTI_EMR_EM21 EXTI_EMR_MR21
#endif
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
#if defined(EXTI_EMR_MR24)
#define EXTI_EMR_EM24 EXTI_EMR_MR24
#endif
#define EXTI_EMR_EM25 EXTI_EMR_MR25
#if defined(EXTI_EMR_MR26)
#define EXTI_EMR_EM26 EXTI_EMR_MR26
#endif
#if defined(EXTI_EMR_MR27)
#define EXTI_EMR_EM27 EXTI_EMR_MR27
#endif
#if defined(EXTI_EMR_MR28)
#define EXTI_EMR_EM28 EXTI_EMR_MR28
#endif
#if defined(EXTI_EMR_MR29)
#define EXTI_EMR_EM29 EXTI_EMR_MR29
#endif
#define EXTI_EMR_EM30 EXTI_EMR_MR30
#if defined(EXTI_EMR_MR31)
#define EXTI_EMR_EM31 EXTI_EMR_MR31
#endif
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@ -6902,30 +6886,18 @@ typedef struct
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19_Pos (19U)
#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21_Pos (21U)
#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR_TR29_Pos (29U)
#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR_TR30_Pos (30U)
#define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
#define EXTI_RTSR_TR31_Pos (31U)
#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@ -6946,14 +6918,40 @@ typedef struct
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#if defined(EXTI_RTSR_TR18)
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
#endif
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#if defined(EXTI_RTSR_TR21)
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#endif
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
#if defined(EXTI_RTSR_TR23)
#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
#endif
#if defined(EXTI_RTSR_TR24)
#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
#endif
#if defined(EXTI_RTSR_TR25)
#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
#endif
#if defined(EXTI_RTSR_TR26)
#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
#endif
#if defined(EXTI_RTSR_TR27)
#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
#endif
#if defined(EXTI_RTSR_TR28)
#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
#endif
#if defined(EXTI_RTSR_TR29)
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#endif
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#if defined(EXTI_RTSR_TR31)
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
#endif
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@ -7010,30 +7008,18 @@ typedef struct
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19_Pos (19U)
#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21_Pos (21U)
#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR_TR29_Pos (29U)
#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR_TR30_Pos (30U)
#define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
#define EXTI_FTSR_TR31_Pos (31U)
#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@ -7054,14 +7040,40 @@ typedef struct
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#if defined(EXTI_FTSR_TR18)
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
#endif
#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
#if defined(EXTI_FTSR_TR21)
#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
#endif
#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
#if defined(EXTI_FTSR_TR23)
#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
#endif
#if defined(EXTI_FTSR_TR24)
#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
#endif
#if defined(EXTI_FTSR_TR25)
#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
#endif
#if defined(EXTI_FTSR_TR26)
#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
#endif
#if defined(EXTI_FTSR_TR27)
#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
#endif
#if defined(EXTI_FTSR_TR28)
#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
#endif
#if defined(EXTI_FTSR_TR29)
#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
#endif
#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
#if defined(EXTI_FTSR_TR31)
#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
#endif
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@ -7118,30 +7130,18 @@ typedef struct
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19_Pos (19U)
#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21_Pos (21U)
#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER_SWIER29_Pos (29U)
#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER_SWIER30_Pos (30U)
#define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
#define EXTI_SWIER_SWIER31_Pos (31U)
#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@ -7162,14 +7162,40 @@ typedef struct
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#if defined(EXTI_SWIER_SWIER18)
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
#endif
#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
#if defined(EXTI_SWIER_SWIER21)
#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
#endif
#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
#if defined(EXTI_SWIER_SWIER23)
#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
#endif
#if defined(EXTI_SWIER_SWIER24)
#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
#endif
#if defined(EXTI_SWIER_SWIER25)
#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
#endif
#if defined(EXTI_SWIER_SWIER26)
#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
#endif
#if defined(EXTI_SWIER_SWIER27)
#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
#endif
#if defined(EXTI_SWIER_SWIER28)
#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
#endif
#if defined(EXTI_SWIER_SWIER29)
#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
#endif
#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
#if defined(EXTI_SWIER_SWIER31)
#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
#endif
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@ -7226,30 +7252,18 @@ typedef struct
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR_PR19_Pos (19U)
#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR_PR21_Pos (21U)
#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR_PR29_Pos (29U)
#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR_PR30_Pos (30U)
#define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
#define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
#define EXTI_PR_PR31_Pos (31U)
#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@ -7259,6 +7273,7 @@ typedef struct
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@ -7270,14 +7285,40 @@ typedef struct
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#if defined(EXTI_PR_PR18)
#define EXTI_PR_PIF18 EXTI_PR_PR18
#endif
#define EXTI_PR_PIF19 EXTI_PR_PR19
#define EXTI_PR_PIF20 EXTI_PR_PR20
#if defined(EXTI_PR_PR21)
#define EXTI_PR_PIF21 EXTI_PR_PR21
#endif
#define EXTI_PR_PIF22 EXTI_PR_PR22
#if defined(EXTI_PR_PR23)
#define EXTI_PR_PIF23 EXTI_PR_PR23
#endif
#if defined(EXTI_PR_PR24)
#define EXTI_PR_PIF24 EXTI_PR_PR24
#endif
#if defined(EXTI_PR_PR25)
#define EXTI_PR_PIF25 EXTI_PR_PR25
#endif
#if defined(EXTI_PR_PR26)
#define EXTI_PR_PIF26 EXTI_PR_PR26
#endif
#if defined(EXTI_PR_PR27)
#define EXTI_PR_PIF27 EXTI_PR_PR27
#endif
#if defined(EXTI_PR_PR28)
#define EXTI_PR_PIF28 EXTI_PR_PR28
#endif
#if defined(EXTI_PR_PR29)
#define EXTI_PR_PIF29 EXTI_PR_PR29
#endif
#define EXTI_PR_PIF30 EXTI_PR_PR30
#if defined(EXTI_PR_PR31)
#define EXTI_PR_PIF31 EXTI_PR_PR31
#endif
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@ -7285,21 +7326,19 @@ typedef struct
#define EXTI_IMR2_MR32_Pos (0U)
#define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_MR33_Pos (1U)
#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_MR34_Pos (2U)
#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_MR35_Pos (3U)
#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
#if defined(EXTI_IMR2_MR33)
#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
#endif
#if defined(EXTI_IMR2_MR34)
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
#endif
#if defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
@ -7309,69 +7348,87 @@ typedef struct
#define EXTI_EMR2_MR32_Pos (0U)
#define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_MR33_Pos (1U)
#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_MR34_Pos (2U)
#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_MR35_Pos (3U)
#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
#if defined(EXTI_EMR2_MR33)
#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
#endif
#if defined(EXTI_EMR2_MR34)
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#endif
#if defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
#define EXTI_RTSR2_TR33_Pos (1U)
#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
#if defined(EXTI_RTSR2_TR33)
#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
#endif
#if defined(EXTI_RTSR2_TR34)
#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
#endif
#if defined(EXTI_RTSR2_TR35)
#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
#define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
#define EXTI_FTSR2_TR33_Pos (1U)
#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
#if defined(EXTI_FTSR2_TR33)
#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
#endif
#if defined(EXTI_FTSR2_TR34)
#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
#endif
#if defined(EXTI_FTSR2_TR35)
#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
#define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
#define EXTI_SWIER2_SWIER33_Pos (1U)
#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
#if defined(EXTI_SWIER2_SWIER33)
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
#endif
#if defined(EXTI_SWIER2_SWIER34)
#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
#endif
#if defined(EXTI_SWIER2_SWIER35)
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
#define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
#define EXTI_PR2_PR33_Pos (1U)
#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
#define EXTI_PR2_PIF32 EXTI_PR2_PR32
#if defined(EXTI_PR2_PR33)
#define EXTI_PR2_PIF33 EXTI_PR2_PR33
#endif
#if defined(EXTI_PR2_PR34)
#define EXTI_PR2_PIF34 EXTI_PR2_PR34
#endif
#if defined(EXTI_PR2_PR35)
#define EXTI_PR2_PIF35 EXTI_PR2_PR35
#endif
/******************************************************************************/
/* */
@ -12980,6 +13037,7 @@ typedef struct
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@ -14713,6 +14771,10 @@ typedef struct
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \

8
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/system_stm32f3xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/system_stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -184,14 +145,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

48
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PortNames.h
View File

@ -1,48 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

275
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/stm32f302x8.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f302x8.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
@ -2280,9 +2280,6 @@ typedef struct
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxNONINSEL_Pos (7U)
#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
#define COMP_CSR_COMPxOUTSEL_Pos (10U)
#define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
@ -6434,9 +6431,6 @@ typedef struct
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21_Pos (21U)
#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
@ -6449,24 +6443,12 @@ typedef struct
#define EXTI_IMR_MR25_Pos (25U)
#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR_MR26_Pos (26U)
#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27_Pos (27U)
#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28_Pos (28U)
#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR_MR29_Pos (29U)
#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR_MR30_Pos (30U)
#define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR_MR31_Pos (31U)
#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@ -6490,17 +6472,27 @@ typedef struct
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
#if defined(EXTI_IMR_MR21)
#define EXTI_IMR_IM21 EXTI_IMR_MR21
#endif
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
#define EXTI_IMR_IM24 EXTI_IMR_MR24
#define EXTI_IMR_IM25 EXTI_IMR_MR25
#if defined(EXTI_IMR_MR26)
#define EXTI_IMR_IM26 EXTI_IMR_MR26
#endif
#define EXTI_IMR_IM27 EXTI_IMR_MR27
#if defined(EXTI_IMR_MR28)
#define EXTI_IMR_IM28 EXTI_IMR_MR28
#endif
#if defined(EXTI_IMR_MR29)
#define EXTI_IMR_IM29 EXTI_IMR_MR29
#endif
#define EXTI_IMR_IM30 EXTI_IMR_MR30
#if defined(EXTI_IMR_MR31)
#define EXTI_IMR_IM31 EXTI_IMR_MR31
#endif
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
@ -6570,9 +6562,6 @@ typedef struct
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21_Pos (21U)
#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
@ -6585,24 +6574,12 @@ typedef struct
#define EXTI_EMR_MR25_Pos (25U)
#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR_MR26_Pos (26U)
#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27_Pos (27U)
#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28_Pos (28U)
#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR_MR29_Pos (29U)
#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR_MR30_Pos (30U)
#define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR_MR31_Pos (31U)
#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@ -6626,17 +6603,27 @@ typedef struct
#define EXTI_EMR_EM18 EXTI_EMR_MR18
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
#if defined(EXTI_EMR_MR21)
#define EXTI_EMR_EM21 EXTI_EMR_MR21
#endif
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
#define EXTI_EMR_EM24 EXTI_EMR_MR24
#define EXTI_EMR_EM25 EXTI_EMR_MR25
#if defined(EXTI_EMR_MR26)
#define EXTI_EMR_EM26 EXTI_EMR_MR26
#endif
#define EXTI_EMR_EM27 EXTI_EMR_MR27
#if defined(EXTI_EMR_MR28)
#define EXTI_EMR_EM28 EXTI_EMR_MR28
#endif
#if defined(EXTI_EMR_MR29)
#define EXTI_EMR_EM29 EXTI_EMR_MR29
#endif
#define EXTI_EMR_EM30 EXTI_EMR_MR30
#if defined(EXTI_EMR_MR31)
#define EXTI_EMR_EM31 EXTI_EMR_MR31
#endif
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@ -6702,21 +6689,12 @@ typedef struct
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21_Pos (21U)
#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR_TR29_Pos (29U)
#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR_TR30_Pos (30U)
#define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
#define EXTI_RTSR_TR31_Pos (31U)
#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@ -6740,11 +6718,35 @@ typedef struct
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#if defined(EXTI_RTSR_TR21)
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#endif
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
#if defined(EXTI_RTSR_TR23)
#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
#endif
#if defined(EXTI_RTSR_TR24)
#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
#endif
#if defined(EXTI_RTSR_TR25)
#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
#endif
#if defined(EXTI_RTSR_TR26)
#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
#endif
#if defined(EXTI_RTSR_TR27)
#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
#endif
#if defined(EXTI_RTSR_TR28)
#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
#endif
#if defined(EXTI_RTSR_TR29)
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#endif
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#if defined(EXTI_RTSR_TR31)
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
#endif
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@ -6810,21 +6812,12 @@ typedef struct
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21_Pos (21U)
#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR_TR29_Pos (29U)
#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR_TR30_Pos (30U)
#define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
#define EXTI_FTSR_TR31_Pos (31U)
#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@ -6848,11 +6841,35 @@ typedef struct
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
#if defined(EXTI_FTSR_TR21)
#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
#endif
#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
#if defined(EXTI_FTSR_TR23)
#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
#endif
#if defined(EXTI_FTSR_TR24)
#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
#endif
#if defined(EXTI_FTSR_TR25)
#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
#endif
#if defined(EXTI_FTSR_TR26)
#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
#endif
#if defined(EXTI_FTSR_TR27)
#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
#endif
#if defined(EXTI_FTSR_TR28)
#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
#endif
#if defined(EXTI_FTSR_TR29)
#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
#endif
#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
#if defined(EXTI_FTSR_TR31)
#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
#endif
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@ -6918,21 +6935,12 @@ typedef struct
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21_Pos (21U)
#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER_SWIER29_Pos (29U)
#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER_SWIER30_Pos (30U)
#define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
#define EXTI_SWIER_SWIER31_Pos (31U)
#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@ -6956,11 +6964,35 @@ typedef struct
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
#if defined(EXTI_SWIER_SWIER21)
#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
#endif
#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
#if defined(EXTI_SWIER_SWIER23)
#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
#endif
#if defined(EXTI_SWIER_SWIER24)
#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
#endif
#if defined(EXTI_SWIER_SWIER25)
#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
#endif
#if defined(EXTI_SWIER_SWIER26)
#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
#endif
#if defined(EXTI_SWIER_SWIER27)
#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
#endif
#if defined(EXTI_SWIER_SWIER28)
#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
#endif
#if defined(EXTI_SWIER_SWIER29)
#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
#endif
#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
#if defined(EXTI_SWIER_SWIER31)
#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
#endif
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@ -7026,21 +7058,12 @@ typedef struct
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR_PR21_Pos (21U)
#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR_PR29_Pos (29U)
#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR_PR30_Pos (30U)
#define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
#define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
#define EXTI_PR_PR31_Pos (31U)
#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@ -7050,6 +7073,7 @@ typedef struct
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@ -7064,11 +7088,35 @@ typedef struct
#define EXTI_PR_PIF18 EXTI_PR_PR18
#define EXTI_PR_PIF19 EXTI_PR_PR19
#define EXTI_PR_PIF20 EXTI_PR_PR20
#if defined(EXTI_PR_PR21)
#define EXTI_PR_PIF21 EXTI_PR_PR21
#endif
#define EXTI_PR_PIF22 EXTI_PR_PR22
#if defined(EXTI_PR_PR23)
#define EXTI_PR_PIF23 EXTI_PR_PR23
#endif
#if defined(EXTI_PR_PR24)
#define EXTI_PR_PIF24 EXTI_PR_PR24
#endif
#if defined(EXTI_PR_PR25)
#define EXTI_PR_PIF25 EXTI_PR_PR25
#endif
#if defined(EXTI_PR_PR26)
#define EXTI_PR_PIF26 EXTI_PR_PR26
#endif
#if defined(EXTI_PR_PR27)
#define EXTI_PR_PIF27 EXTI_PR_PR27
#endif
#if defined(EXTI_PR_PR28)
#define EXTI_PR_PIF28 EXTI_PR_PR28
#endif
#if defined(EXTI_PR_PR29)
#define EXTI_PR_PIF29 EXTI_PR_PR29
#endif
#define EXTI_PR_PIF30 EXTI_PR_PR30
#if defined(EXTI_PR_PR31)
#define EXTI_PR_PIF31 EXTI_PR_PR31
#endif
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@ -7076,21 +7124,19 @@ typedef struct
#define EXTI_IMR2_MR32_Pos (0U)
#define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_MR33_Pos (1U)
#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_MR34_Pos (2U)
#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_MR35_Pos (3U)
#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
#if defined(EXTI_IMR2_MR33)
#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
#endif
#if defined(EXTI_IMR2_MR34)
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
#endif
#if defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
@ -7100,69 +7146,87 @@ typedef struct
#define EXTI_EMR2_MR32_Pos (0U)
#define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_MR33_Pos (1U)
#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_MR34_Pos (2U)
#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_MR35_Pos (3U)
#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
#if defined(EXTI_EMR2_MR33)
#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
#endif
#if defined(EXTI_EMR2_MR34)
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#endif
#if defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
#define EXTI_RTSR2_TR33_Pos (1U)
#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
#if defined(EXTI_RTSR2_TR33)
#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
#endif
#if defined(EXTI_RTSR2_TR34)
#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
#endif
#if defined(EXTI_RTSR2_TR35)
#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
#define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
#define EXTI_FTSR2_TR33_Pos (1U)
#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
#if defined(EXTI_FTSR2_TR33)
#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
#endif
#if defined(EXTI_FTSR2_TR34)
#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
#endif
#if defined(EXTI_FTSR2_TR35)
#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
#define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
#define EXTI_SWIER2_SWIER33_Pos (1U)
#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
#if defined(EXTI_SWIER2_SWIER33)
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
#endif
#if defined(EXTI_SWIER2_SWIER34)
#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
#endif
#if defined(EXTI_SWIER2_SWIER35)
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
#define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
#define EXTI_PR2_PR33_Pos (1U)
#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
#define EXTI_PR2_PIF32 EXTI_PR2_PR32
#if defined(EXTI_PR2_PR33)
#define EXTI_PR2_PIF33 EXTI_PR2_PR33
#endif
#if defined(EXTI_PR2_PR34)
#define EXTI_PR2_PIF34 EXTI_PR2_PR34
#endif
#if defined(EXTI_PR2_PR35)
#define EXTI_PR2_PIF35 EXTI_PR2_PR35
#endif
/******************************************************************************/
/* */
@ -10130,6 +10194,7 @@ typedef struct
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@ -11749,9 +11814,9 @@ typedef struct
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@ -11985,6 +12050,10 @@ typedef struct
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \

8
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/system_stm32f3xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/system_stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -159,14 +120,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PortNames.h
View File

@ -1,49 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

318
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/stm32f303x8.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303x8.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
@ -6446,48 +6446,24 @@ typedef struct
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19_Pos (19U)
#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21_Pos (21U)
#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23_Pos (23U)
#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR_MR24_Pos (24U)
#define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR_MR25_Pos (25U)
#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR_MR26_Pos (26U)
#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27_Pos (27U)
#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28_Pos (28U)
#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR_MR29_Pos (29U)
#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR_MR30_Pos (30U)
#define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR_MR31_Pos (31U)
#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@ -6508,20 +6484,36 @@ typedef struct
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#if defined(EXTI_IMR_MR18)
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#endif
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
#if defined(EXTI_IMR_MR21)
#define EXTI_IMR_IM21 EXTI_IMR_MR21
#endif
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
#if defined(EXTI_IMR_MR24)
#define EXTI_IMR_IM24 EXTI_IMR_MR24
#endif
#define EXTI_IMR_IM25 EXTI_IMR_MR25
#if defined(EXTI_IMR_MR26)
#define EXTI_IMR_IM26 EXTI_IMR_MR26
#endif
#if defined(EXTI_IMR_MR27)
#define EXTI_IMR_IM27 EXTI_IMR_MR27
#endif
#if defined(EXTI_IMR_MR28)
#define EXTI_IMR_IM28 EXTI_IMR_MR28
#endif
#if defined(EXTI_IMR_MR29)
#define EXTI_IMR_IM29 EXTI_IMR_MR29
#endif
#define EXTI_IMR_IM30 EXTI_IMR_MR30
#if defined(EXTI_IMR_MR31)
#define EXTI_IMR_IM31 EXTI_IMR_MR31
#endif
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
@ -6582,48 +6574,24 @@ typedef struct
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19_Pos (19U)
#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21_Pos (21U)
#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23_Pos (23U)
#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR_MR24_Pos (24U)
#define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR_MR25_Pos (25U)
#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR_MR26_Pos (26U)
#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27_Pos (27U)
#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28_Pos (28U)
#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR_MR29_Pos (29U)
#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR_MR30_Pos (30U)
#define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR_MR31_Pos (31U)
#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@ -6644,20 +6612,36 @@ typedef struct
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#if defined(EXTI_EMR_MR18)
#define EXTI_EMR_EM18 EXTI_EMR_MR18
#endif
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
#if defined(EXTI_EMR_MR21)
#define EXTI_EMR_EM21 EXTI_EMR_MR21
#endif
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
#if defined(EXTI_EMR_MR24)
#define EXTI_EMR_EM24 EXTI_EMR_MR24
#endif
#define EXTI_EMR_EM25 EXTI_EMR_MR25
#if defined(EXTI_EMR_MR26)
#define EXTI_EMR_EM26 EXTI_EMR_MR26
#endif
#if defined(EXTI_EMR_MR27)
#define EXTI_EMR_EM27 EXTI_EMR_MR27
#endif
#if defined(EXTI_EMR_MR28)
#define EXTI_EMR_EM28 EXTI_EMR_MR28
#endif
#if defined(EXTI_EMR_MR29)
#define EXTI_EMR_EM29 EXTI_EMR_MR29
#endif
#define EXTI_EMR_EM30 EXTI_EMR_MR30
#if defined(EXTI_EMR_MR31)
#define EXTI_EMR_EM31 EXTI_EMR_MR31
#endif
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@ -6714,30 +6698,18 @@ typedef struct
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19_Pos (19U)
#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21_Pos (21U)
#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR_TR29_Pos (29U)
#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR_TR30_Pos (30U)
#define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
#define EXTI_RTSR_TR31_Pos (31U)
#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@ -6758,14 +6730,40 @@ typedef struct
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#if defined(EXTI_RTSR_TR18)
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
#endif
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#if defined(EXTI_RTSR_TR21)
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#endif
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
#if defined(EXTI_RTSR_TR23)
#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
#endif
#if defined(EXTI_RTSR_TR24)
#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
#endif
#if defined(EXTI_RTSR_TR25)
#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
#endif
#if defined(EXTI_RTSR_TR26)
#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
#endif
#if defined(EXTI_RTSR_TR27)
#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
#endif
#if defined(EXTI_RTSR_TR28)
#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
#endif
#if defined(EXTI_RTSR_TR29)
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#endif
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#if defined(EXTI_RTSR_TR31)
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
#endif
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@ -6822,30 +6820,18 @@ typedef struct
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19_Pos (19U)
#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21_Pos (21U)
#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR_TR29_Pos (29U)
#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR_TR30_Pos (30U)
#define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
#define EXTI_FTSR_TR31_Pos (31U)
#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@ -6866,14 +6852,40 @@ typedef struct
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#if defined(EXTI_FTSR_TR18)
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
#endif
#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
#if defined(EXTI_FTSR_TR21)
#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
#endif
#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
#if defined(EXTI_FTSR_TR23)
#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
#endif
#if defined(EXTI_FTSR_TR24)
#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
#endif
#if defined(EXTI_FTSR_TR25)
#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
#endif
#if defined(EXTI_FTSR_TR26)
#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
#endif
#if defined(EXTI_FTSR_TR27)
#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
#endif
#if defined(EXTI_FTSR_TR28)
#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
#endif
#if defined(EXTI_FTSR_TR29)
#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
#endif
#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
#if defined(EXTI_FTSR_TR31)
#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
#endif
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@ -6930,30 +6942,18 @@ typedef struct
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19_Pos (19U)
#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21_Pos (21U)
#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER_SWIER29_Pos (29U)
#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER_SWIER30_Pos (30U)
#define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
#define EXTI_SWIER_SWIER31_Pos (31U)
#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@ -6974,14 +6974,40 @@ typedef struct
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#if defined(EXTI_SWIER_SWIER18)
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
#endif
#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
#if defined(EXTI_SWIER_SWIER21)
#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
#endif
#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
#if defined(EXTI_SWIER_SWIER23)
#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
#endif
#if defined(EXTI_SWIER_SWIER24)
#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
#endif
#if defined(EXTI_SWIER_SWIER25)
#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
#endif
#if defined(EXTI_SWIER_SWIER26)
#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
#endif
#if defined(EXTI_SWIER_SWIER27)
#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
#endif
#if defined(EXTI_SWIER_SWIER28)
#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
#endif
#if defined(EXTI_SWIER_SWIER29)
#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
#endif
#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
#if defined(EXTI_SWIER_SWIER31)
#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
#endif
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@ -7038,30 +7064,18 @@ typedef struct
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR_PR19_Pos (19U)
#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR_PR21_Pos (21U)
#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR_PR29_Pos (29U)
#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR_PR30_Pos (30U)
#define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
#define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
#define EXTI_PR_PR31_Pos (31U)
#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@ -7071,6 +7085,7 @@ typedef struct
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@ -7082,14 +7097,40 @@ typedef struct
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#if defined(EXTI_PR_PR18)
#define EXTI_PR_PIF18 EXTI_PR_PR18
#endif
#define EXTI_PR_PIF19 EXTI_PR_PR19
#define EXTI_PR_PIF20 EXTI_PR_PR20
#if defined(EXTI_PR_PR21)
#define EXTI_PR_PIF21 EXTI_PR_PR21
#endif
#define EXTI_PR_PIF22 EXTI_PR_PR22
#if defined(EXTI_PR_PR23)
#define EXTI_PR_PIF23 EXTI_PR_PR23
#endif
#if defined(EXTI_PR_PR24)
#define EXTI_PR_PIF24 EXTI_PR_PR24
#endif
#if defined(EXTI_PR_PR25)
#define EXTI_PR_PIF25 EXTI_PR_PR25
#endif
#if defined(EXTI_PR_PR26)
#define EXTI_PR_PIF26 EXTI_PR_PR26
#endif
#if defined(EXTI_PR_PR27)
#define EXTI_PR_PIF27 EXTI_PR_PR27
#endif
#if defined(EXTI_PR_PR28)
#define EXTI_PR_PIF28 EXTI_PR_PR28
#endif
#if defined(EXTI_PR_PR29)
#define EXTI_PR_PIF29 EXTI_PR_PR29
#endif
#define EXTI_PR_PIF30 EXTI_PR_PR30
#if defined(EXTI_PR_PR31)
#define EXTI_PR_PIF31 EXTI_PR_PR31
#endif
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@ -7097,21 +7138,19 @@ typedef struct
#define EXTI_IMR2_MR32_Pos (0U)
#define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_MR33_Pos (1U)
#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_MR34_Pos (2U)
#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_MR35_Pos (3U)
#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
#if defined(EXTI_IMR2_MR33)
#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
#endif
#if defined(EXTI_IMR2_MR34)
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
#endif
#if defined(EXTI_IMR2_MR35)
#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#endif
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
@ -7121,69 +7160,87 @@ typedef struct
#define EXTI_EMR2_MR32_Pos (0U)
#define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_MR33_Pos (1U)
#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_MR34_Pos (2U)
#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_MR35_Pos (3U)
#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
#if defined(EXTI_EMR2_MR33)
#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
#endif
#if defined(EXTI_EMR2_MR34)
#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
#endif
#if defined(EXTI_EMR2_MR35)
#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
#define EXTI_RTSR2_TR33_Pos (1U)
#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
#if defined(EXTI_RTSR2_TR33)
#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
#endif
#if defined(EXTI_RTSR2_TR34)
#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
#endif
#if defined(EXTI_RTSR2_TR35)
#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
#define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
#define EXTI_FTSR2_TR33_Pos (1U)
#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
#if defined(EXTI_FTSR2_TR33)
#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
#endif
#if defined(EXTI_FTSR2_TR34)
#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
#endif
#if defined(EXTI_FTSR2_TR35)
#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
#define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
#define EXTI_SWIER2_SWIER33_Pos (1U)
#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
#if defined(EXTI_SWIER2_SWIER33)
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
#endif
#if defined(EXTI_SWIER2_SWIER34)
#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
#endif
#if defined(EXTI_SWIER2_SWIER35)
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
#define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
#define EXTI_PR2_PR33_Pos (1U)
#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
#define EXTI_PR2_PIF32 EXTI_PR2_PR32
#if defined(EXTI_PR2_PR33)
#define EXTI_PR2_PIF33 EXTI_PR2_PR33
#endif
#if defined(EXTI_PR2_PR34)
#define EXTI_PR2_PIF34 EXTI_PR2_PR34
#endif
#if defined(EXTI_PR2_PR35)
#define EXTI_PR2_PIF35 EXTI_PR2_PR35
#endif
/******************************************************************************/
/* */
@ -10025,6 +10082,7 @@ typedef struct
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@ -11755,6 +11813,10 @@ typedef struct
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \

8
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/system_stm32f3xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/system_stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -192,14 +153,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

51
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h
View File

@ -1,51 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7
} PortName;
#ifdef __cplusplus
}
#endif
#endif

152
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f303xe.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303xe.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
*
* This file contains:
@ -2531,18 +2531,11 @@ typedef struct
#define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
#define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
#define COMP2_CSR_COMP2INSEL_Pos (4U)
#define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
#define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */
#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
#define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
#define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
#define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
#define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
#define COMP2_CSR_COMP2NONINSEL_Pos (7U)
#define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
#define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */
#define COMP2_CSR_COMP2WNDWEN_Pos (9U)
#define COMP2_CSR_COMP2WNDWEN_Msk (0x1U << COMP2_CSR_COMP2WNDWEN_Pos) /*!< 0x00000200 */
#define COMP2_CSR_COMP2WNDWEN COMP2_CSR_COMP2WNDWEN_Msk /*!< COMP2 window mode enable */
#define COMP2_CSR_COMP2OUTSEL_Pos (10U)
#define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
@ -2604,18 +2597,11 @@ typedef struct
#define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
#define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
#define COMP4_CSR_COMP4INSEL_Pos (4U)
#define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
#define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */
#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
#define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
#define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
#define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
#define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
#define COMP4_CSR_COMP4NONINSEL_Pos (7U)
#define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
#define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */
#define COMP4_CSR_COMP4WNDWEN_Pos (9U)
#define COMP4_CSR_COMP4WNDWEN_Msk (0x1U << COMP4_CSR_COMP4WNDWEN_Pos) /*!< 0x00000200 */
#define COMP4_CSR_COMP4WNDWEN COMP4_CSR_COMP4WNDWEN_Msk /*!< COMP4 window mode enable */
#define COMP4_CSR_COMP4OUTSEL_Pos (10U)
#define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
@ -2677,20 +2663,11 @@ typedef struct
#define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
#define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
#define COMP6_CSR_COMP6INSEL_Pos (4U)
#define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
#define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */
#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
#define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
#define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
#define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
#define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
#if defined(STM32F303xE)
#define COMP6_CSR_COMP6NONINSEL_Pos (7U)
#define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
#define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */
#endif
#define COMP6_CSR_COMP6WNDWEN_Pos (9U)
#define COMP6_CSR_COMP6WNDWEN_Msk (0x1U << COMP6_CSR_COMP6WNDWEN_Pos) /*!< 0x00000200 */
#define COMP6_CSR_COMP6WNDWEN COMP6_CSR_COMP6WNDWEN_Msk /*!< COMP6 window mode enable */
#define COMP6_CSR_COMP6OUTSEL_Pos (10U)
#define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
@ -2755,18 +2732,11 @@ typedef struct
#define COMP_CSR_COMPxSW1_Msk (0x1U << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */
#define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */
#define COMP_CSR_COMPxINSEL_Pos (4U)
#define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxNONINSEL_Pos (7U)
#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
#define COMP_CSR_COMPxWNDWEN_Pos (9U)
#define COMP_CSR_COMPxWNDWEN_Msk (0x1U << COMP_CSR_COMPxWNDWEN_Pos) /*!< 0x00000200 */
#define COMP_CSR_COMPxWNDWEN COMP_CSR_COMPxWNDWEN_Msk /*!< COMPx window mode enable */
#define COMP_CSR_COMPxOUTSEL_Pos (10U)
#define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
@ -7500,6 +7470,24 @@ typedef struct
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
#if defined(EXTI_RTSR_TR23)
#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
#endif
#if defined(EXTI_RTSR_TR24)
#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
#endif
#if defined(EXTI_RTSR_TR25)
#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
#endif
#if defined(EXTI_RTSR_TR26)
#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
#endif
#if defined(EXTI_RTSR_TR27)
#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
#endif
#if defined(EXTI_RTSR_TR28)
#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
#endif
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
@ -7608,6 +7596,24 @@ typedef struct
#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
#if defined(EXTI_FTSR_TR23)
#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
#endif
#if defined(EXTI_FTSR_TR24)
#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
#endif
#if defined(EXTI_FTSR_TR25)
#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
#endif
#if defined(EXTI_FTSR_TR26)
#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
#endif
#if defined(EXTI_FTSR_TR27)
#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
#endif
#if defined(EXTI_FTSR_TR28)
#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
#endif
#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
@ -7716,6 +7722,24 @@ typedef struct
#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
#if defined(EXTI_SWIER_SWIER23)
#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
#endif
#if defined(EXTI_SWIER_SWIER24)
#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
#endif
#if defined(EXTI_SWIER_SWIER25)
#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
#endif
#if defined(EXTI_SWIER_SWIER26)
#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
#endif
#if defined(EXTI_SWIER_SWIER27)
#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
#endif
#if defined(EXTI_SWIER_SWIER28)
#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
#endif
#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
@ -7808,6 +7832,7 @@ typedef struct
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@ -7824,6 +7849,24 @@ typedef struct
#define EXTI_PR_PIF20 EXTI_PR_PR20
#define EXTI_PR_PIF21 EXTI_PR_PR21
#define EXTI_PR_PIF22 EXTI_PR_PR22
#if defined(EXTI_PR_PR23)
#define EXTI_PR_PIF23 EXTI_PR_PR23
#endif
#if defined(EXTI_PR_PR24)
#define EXTI_PR_PIF24 EXTI_PR_PR24
#endif
#if defined(EXTI_PR_PR25)
#define EXTI_PR_PIF25 EXTI_PR_PR25
#endif
#if defined(EXTI_PR_PR26)
#define EXTI_PR_PIF26 EXTI_PR_PR26
#endif
#if defined(EXTI_PR_PR27)
#define EXTI_PR_PIF27 EXTI_PR_PR27
#endif
#if defined(EXTI_PR_PR28)
#define EXTI_PR_PIF28 EXTI_PR_PR28
#endif
#define EXTI_PR_PIF29 EXTI_PR_PR29
#define EXTI_PR_PIF30 EXTI_PR_PR30
#define EXTI_PR_PIF31 EXTI_PR_PR31
@ -7845,6 +7888,7 @@ typedef struct
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
@ -7885,6 +7929,12 @@ typedef struct
/* References Defines */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
#if defined(EXTI_RTSR2_TR34)
#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
#endif
#if defined(EXTI_RTSR2_TR35)
#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
@ -7897,6 +7947,12 @@ typedef struct
/* References Defines */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
#if defined(EXTI_FTSR2_TR34)
#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
#endif
#if defined(EXTI_FTSR2_TR35)
#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
@ -7909,6 +7965,12 @@ typedef struct
/* References Defines */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
#if defined(EXTI_SWIER2_SWIER34)
#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
#endif
#if defined(EXTI_SWIER2_SWIER35)
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
@ -7921,6 +7983,13 @@ typedef struct
/* References Defines */
#define EXTI_PR2_PIF32 EXTI_PR2_PR32
#define EXTI_PR2_PIF33 EXTI_PR2_PR33
#if defined(EXTI_PR2_PR34)
#define EXTI_PR2_PIF34 EXTI_PR2_PR34
#endif
#if defined(EXTI_PR2_PR35)
#define EXTI_PR2_PIF35 EXTI_PR2_PR35
#endif
/******************************************************************************/
/* */
@ -12757,6 +12826,7 @@ typedef struct
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@ -14394,9 +14464,9 @@ typedef struct
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@ -14688,6 +14758,12 @@ typedef struct
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \

8
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -259,14 +220,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

51
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PortNames.h
View File

@ -1,51 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5,
PortG = 6,
PortH = 7
} PortName;
#ifdef __cplusplus
}
#endif
#endif

152
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f303xe.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303xe.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
*
* This file contains:
@ -2531,18 +2531,11 @@ typedef struct
#define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
#define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
#define COMP2_CSR_COMP2INSEL_Pos (4U)
#define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
#define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */
#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
#define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
#define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
#define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
#define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
#define COMP2_CSR_COMP2NONINSEL_Pos (7U)
#define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
#define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */
#define COMP2_CSR_COMP2WNDWEN_Pos (9U)
#define COMP2_CSR_COMP2WNDWEN_Msk (0x1U << COMP2_CSR_COMP2WNDWEN_Pos) /*!< 0x00000200 */
#define COMP2_CSR_COMP2WNDWEN COMP2_CSR_COMP2WNDWEN_Msk /*!< COMP2 window mode enable */
#define COMP2_CSR_COMP2OUTSEL_Pos (10U)
#define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
@ -2604,18 +2597,11 @@ typedef struct
#define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
#define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
#define COMP4_CSR_COMP4INSEL_Pos (4U)
#define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
#define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */
#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
#define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
#define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
#define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
#define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
#define COMP4_CSR_COMP4NONINSEL_Pos (7U)
#define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
#define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */
#define COMP4_CSR_COMP4WNDWEN_Pos (9U)
#define COMP4_CSR_COMP4WNDWEN_Msk (0x1U << COMP4_CSR_COMP4WNDWEN_Pos) /*!< 0x00000200 */
#define COMP4_CSR_COMP4WNDWEN COMP4_CSR_COMP4WNDWEN_Msk /*!< COMP4 window mode enable */
#define COMP4_CSR_COMP4OUTSEL_Pos (10U)
#define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
@ -2677,20 +2663,11 @@ typedef struct
#define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
#define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
#define COMP6_CSR_COMP6INSEL_Pos (4U)
#define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
#define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */
#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
#define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
#define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
#define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
#define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
#if defined(STM32F303xE)
#define COMP6_CSR_COMP6NONINSEL_Pos (7U)
#define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
#define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */
#endif
#define COMP6_CSR_COMP6WNDWEN_Pos (9U)
#define COMP6_CSR_COMP6WNDWEN_Msk (0x1U << COMP6_CSR_COMP6WNDWEN_Pos) /*!< 0x00000200 */
#define COMP6_CSR_COMP6WNDWEN COMP6_CSR_COMP6WNDWEN_Msk /*!< COMP6 window mode enable */
#define COMP6_CSR_COMP6OUTSEL_Pos (10U)
#define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
@ -2755,18 +2732,11 @@ typedef struct
#define COMP_CSR_COMPxSW1_Msk (0x1U << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */
#define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */
#define COMP_CSR_COMPxINSEL_Pos (4U)
#define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxNONINSEL_Pos (7U)
#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
#define COMP_CSR_COMPxWNDWEN_Pos (9U)
#define COMP_CSR_COMPxWNDWEN_Msk (0x1U << COMP_CSR_COMPxWNDWEN_Pos) /*!< 0x00000200 */
#define COMP_CSR_COMPxWNDWEN COMP_CSR_COMPxWNDWEN_Msk /*!< COMPx window mode enable */
#define COMP_CSR_COMPxOUTSEL_Pos (10U)
#define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
@ -7500,6 +7470,24 @@ typedef struct
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
#if defined(EXTI_RTSR_TR23)
#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
#endif
#if defined(EXTI_RTSR_TR24)
#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
#endif
#if defined(EXTI_RTSR_TR25)
#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
#endif
#if defined(EXTI_RTSR_TR26)
#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
#endif
#if defined(EXTI_RTSR_TR27)
#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
#endif
#if defined(EXTI_RTSR_TR28)
#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
#endif
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
@ -7608,6 +7596,24 @@ typedef struct
#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
#if defined(EXTI_FTSR_TR23)
#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
#endif
#if defined(EXTI_FTSR_TR24)
#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
#endif
#if defined(EXTI_FTSR_TR25)
#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
#endif
#if defined(EXTI_FTSR_TR26)
#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
#endif
#if defined(EXTI_FTSR_TR27)
#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
#endif
#if defined(EXTI_FTSR_TR28)
#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
#endif
#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
@ -7716,6 +7722,24 @@ typedef struct
#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
#if defined(EXTI_SWIER_SWIER23)
#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
#endif
#if defined(EXTI_SWIER_SWIER24)
#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
#endif
#if defined(EXTI_SWIER_SWIER25)
#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
#endif
#if defined(EXTI_SWIER_SWIER26)
#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
#endif
#if defined(EXTI_SWIER_SWIER27)
#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
#endif
#if defined(EXTI_SWIER_SWIER28)
#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
#endif
#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
@ -7808,6 +7832,7 @@ typedef struct
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@ -7824,6 +7849,24 @@ typedef struct
#define EXTI_PR_PIF20 EXTI_PR_PR20
#define EXTI_PR_PIF21 EXTI_PR_PR21
#define EXTI_PR_PIF22 EXTI_PR_PR22
#if defined(EXTI_PR_PR23)
#define EXTI_PR_PIF23 EXTI_PR_PR23
#endif
#if defined(EXTI_PR_PR24)
#define EXTI_PR_PIF24 EXTI_PR_PR24
#endif
#if defined(EXTI_PR_PR25)
#define EXTI_PR_PIF25 EXTI_PR_PR25
#endif
#if defined(EXTI_PR_PR26)
#define EXTI_PR_PIF26 EXTI_PR_PR26
#endif
#if defined(EXTI_PR_PR27)
#define EXTI_PR_PIF27 EXTI_PR_PR27
#endif
#if defined(EXTI_PR_PR28)
#define EXTI_PR_PIF28 EXTI_PR_PR28
#endif
#define EXTI_PR_PIF29 EXTI_PR_PR29
#define EXTI_PR_PIF30 EXTI_PR_PR30
#define EXTI_PR_PIF31 EXTI_PR_PR31
@ -7845,6 +7888,7 @@ typedef struct
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
@ -7885,6 +7929,12 @@ typedef struct
/* References Defines */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
#if defined(EXTI_RTSR2_TR34)
#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
#endif
#if defined(EXTI_RTSR2_TR35)
#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
@ -7897,6 +7947,12 @@ typedef struct
/* References Defines */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
#if defined(EXTI_FTSR2_TR34)
#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
#endif
#if defined(EXTI_FTSR2_TR35)
#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
@ -7909,6 +7965,12 @@ typedef struct
/* References Defines */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
#if defined(EXTI_SWIER2_SWIER34)
#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
#endif
#if defined(EXTI_SWIER2_SWIER35)
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
@ -7921,6 +7983,13 @@ typedef struct
/* References Defines */
#define EXTI_PR2_PIF32 EXTI_PR2_PR32
#define EXTI_PR2_PIF33 EXTI_PR2_PR33
#if defined(EXTI_PR2_PR34)
#define EXTI_PR2_PIF34 EXTI_PR2_PR34
#endif
#if defined(EXTI_PR2_PR35)
#define EXTI_PR2_PIF35 EXTI_PR2_PR35
#endif
/******************************************************************************/
/* */
@ -12757,6 +12826,7 @@ typedef struct
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@ -14394,9 +14464,9 @@ typedef struct
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@ -14688,6 +14758,12 @@ typedef struct
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \

8
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.0
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.c
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
* @version V2.3.0
* @date 29-April-2015
* @version V2.3.1
* @date 16-December-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PinNames.h
View File

@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7)))
#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
((PUPD & 0x07) << 4) |\
((AFNUM & 0x0F) << 7) |\
((CHANNEL & 0x1F) << 11) |\
((INVERTED & 0x01) << 16)))
#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
#define STM_MODE_INPUT (0)
#define STM_MODE_OUTPUT_PP (1)
#define STM_MODE_OUTPUT_OD (2)
#define STM_MODE_AF_PP (3)
#define STM_MODE_AF_OD (4)
#define STM_MODE_ANALOG (5)
#define STM_MODE_IT_RISING (6)
#define STM_MODE_IT_FALLING (7)
#define STM_MODE_IT_RISING_FALLING (8)
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
#define STM_PIN(X) ((uint32_t)(X) & 0xF)
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@ -187,14 +148,6 @@ typedef enum {
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif

49
targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h
View File

@ -1,49 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4,
PortF = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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