ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

PSOC6: update BSP GeneratedSource, add design.modus

pull/10692/head
Volodymyr Medvid 2019-07-08 13:02:54 +03:00
parent 4bd47e9bca
commit c647531767
68 changed files with 9769 additions and 3402 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c
View File

@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
init_cycfg_platform();
init_cycfg_routing();
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h
View File

@ -30,11 +30,11 @@ extern "C" {
#endif
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
#include "cycfg_platform.h"
#include "cycfg_routing.h"
void init_cycfg_all(void);

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c
View File

@ -32,14 +32,10 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
}

17
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h
View File

@ -32,14 +32,15 @@
extern "C" {
#endif
#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_0_NUM 0U
#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_1_NUM 1U
#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_2_NUM 2U
#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_3_NUM 3U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 0U
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
void init_cycfg_clocks(void);

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c
View File

@ -28,7 +28,7 @@ cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@ -36,16 +36,16 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t KITPROG_UART_config =
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 12,
.oversample = 8,
.enableMsbFirst = false,
.dataWidth = 9UL,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
@ -64,14 +64,14 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_smif_config_t QSPI_config =
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = QSPI_DESELECT_DELAY,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
const cy_stc_mcwdt_config_t MCWDT0_config =
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@ -84,7 +84,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
const cy_stc_rtc_config_t RTC_config =
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,

83
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h
View File

@ -38,6 +38,7 @@
extern "C" {
#endif
#define CYBSP_BLE_ENABLED 1U
#define CY_BLE_CORE_CORTEX_M4 4U
#define CY_BLE_CORE_CORTEX_M0P 0U
#define CY_BLE_CORE_DUAL 255U
@ -45,9 +46,10 @@ extern "C" {
#define CY_BLE_CORE 4U
#endif
#define CY_BLE_IRQ bless_interrupt_IRQn
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 50000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 0u
@ -78,45 +80,50 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
#define CapSense_HW CSD0
#define CapSense_IRQ csd_interrupt_IRQn
#define CSD_COMM_HW SCB3
#define CSD_COMM_IRQ scb_3_interrupt_IRQn
#define KITPROG_UART_HW SCB5
#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
#define QSPI_HW SMIF0
#define QSPI_IRQ smif_interrupt_IRQn
#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_DATALINES0_1 (1UL)
#define QSPI_DATALINES2_3 (1UL)
#define QSPI_DATALINES4_5 (0UL)
#define QSPI_DATALINES6_7 (0UL)
#define QSPI_SS0 (1UL)
#define QSPI_SS1 (0UL)
#define QSPI_SS2 (0UL)
#define QSPI_SS3 (0UL)
#define QSPI_DESELECT_DELAY 7
#define MCWDT0_HW MCWDT_STRUCT0
#define RTC_10_MONTH_OFFSET (28U)
#define RTC_MONTH_OFFSET (24U)
#define RTC_10_DAY_OFFSET (20U)
#define RTC_DAY_OFFSET (16U)
#define RTC_1000_YEAR_OFFSET (12U)
#define RTC_100_YEAR_OFFSET (8U)
#define RTC_10_YEAR_OFFSET (4U)
#define RTC_YEAR_OFFSET (0U)
#define CYBSP_CSD_HW CSD0
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_DATALINES0_1 (1UL)
#define CYBSP_QSPI_DATALINES2_3 (1UL)
#define CYBSP_QSPI_DATALINES4_5 (0UL)
#define CYBSP_QSPI_DATALINES6_7 (0UL)
#define CYBSP_QSPI_SS0 (1UL)
#define CYBSP_QSPI_SS1 (0UL)
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
#define CYBSP_MCWDT0_ENABLED 1U
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
#define CYBSP_RTC_ENABLED 1U
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
#define CYBSP_RTC_MONTH_OFFSET (24U)
#define CYBSP_RTC_10_DAY_OFFSET (20U)
#define CYBSP_RTC_DAY_OFFSET (16U)
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
extern const cy_stc_smif_config_t QSPI_config;
extern const cy_stc_mcwdt_config_t MCWDT0_config;
extern const cy_stc_rtc_config_t RTC_config;
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
void init_cycfg_peripherals(void);

260
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c
View File

@ -24,512 +24,512 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t WCO_IN_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = WCO_IN_HSIOM,
.hsiom = CYBSP_WCO_IN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t WCO_OUT_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = WCO_OUT_HSIOM,
.hsiom = CYBSP_WCO_OUT_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED_RED_config =
const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED_RED_HSIOM,
.hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SW2_config =
const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = SW2_HSIOM,
.hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED_BLUE_config =
const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED_BLUE_HSIOM,
.hsiom = CYBSP_LED_BLUE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_SS0_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = QSPI_SS0_HSIOM,
.hsiom = CYBSP_QSPI_SS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA3_HSIOM,
.hsiom = CYBSP_QSPI_D3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA2_HSIOM,
.hsiom = CYBSP_QSPI_D2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA1_HSIOM,
.hsiom = CYBSP_QSPI_D1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA0_HSIOM,
.hsiom = CYBSP_QSPI_D0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = QSPI_SPI_CLOCK_HSIOM,
.hsiom = CYBSP_QSPI_SCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED9_config =
const cy_stc_gpio_pin_config_t CYBSP_LED9_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED9_HSIOM,
.hsiom = CYBSP_LED9_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_TX_HSIOM,
.hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED_GREEN_config =
const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED_GREEN_HSIOM,
.hsiom = CYBSP_LED_GREEN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t ioss_0_port_1_pin_4_config =
const cy_stc_gpio_pin_config_t CYBSP_LED8_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = ioss_0_port_1_pin_4_HSIOM,
.hsiom = CYBSP_LED8_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED8_config =
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED8_HSIOM,
.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t EZI2C_SCL_config =
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
.hsiom = EZI2C_SCL_HSIOM,
.hsiom = CYBSP_EZI2C_SCL_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t EZI2C_SDA_config =
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
.hsiom = EZI2C_SDA_HSIOM,
.hsiom = CYBSP_EZI2C_SDA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SWO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = SWO_HSIOM,
.hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SWDIO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = SWDIO_HSIOM,
.hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SWDCK_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
.hsiom = SWDCK_HSIOM,
.hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CINA_config =
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CINA_HSIOM,
.hsiom = CYBSP_CINA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CINB_config =
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CINB_HSIOM,
.hsiom = CYBSP_CINB_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CMOD_config =
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CMOD_HSIOM,
.hsiom = CYBSP_CMOD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_BTN0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_BTN0_HSIOM,
.hsiom = CYBSP_CSD_BTN0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_BTN1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_BTN1_HSIOM,
.hsiom = CYBSP_CSD_BTN1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD0_HSIOM,
.hsiom = CYBSP_CSD_SLD0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD1_HSIOM,
.hsiom = CYBSP_CSD_SLD1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD2_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD2_HSIOM,
.hsiom = CYBSP_CSD_SLD2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD3_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD3_HSIOM,
.hsiom = CYBSP_CSD_SLD3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD4_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD4_HSIOM,
.hsiom = CYBSP_CSD_SLD4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@ -540,48 +540,48 @@ const cy_stc_gpio_pin_config_t CSD_SLD4_config =
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config);
Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config);
Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config);
Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config);
Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config);
Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
Cy_GPIO_Pin_Init(ioss_0_port_1_pin_4_PORT, ioss_0_port_1_pin_4_PIN, &ioss_0_port_1_pin_4_config);
Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config);
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config);
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config);
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config);
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);

549
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h
View File

@ -33,358 +33,391 @@
extern "C" {
#endif
#define WCO_IN_PORT GPIO_PRT0
#define WCO_IN_PIN 0U
#define WCO_IN_NUM 0U
#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define WCO_IN_INIT_DRIVESTATE 1
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT0
#define CYBSP_WCO_IN_PIN 0U
#define CYBSP_WCO_IN_NUM 0U
#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#define WCO_OUT_PORT GPIO_PRT0
#define WCO_OUT_PIN 1U
#define WCO_OUT_NUM 1U
#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define WCO_OUT_INIT_DRIVESTATE 1
#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT0
#define CYBSP_WCO_OUT_PIN 1U
#define CYBSP_WCO_OUT_NUM 1U
#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define LED_RED_PORT GPIO_PRT0
#define LED_RED_PIN 3U
#define LED_RED_NUM 3U
#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_RED_INIT_DRIVESTATE 1
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_LED_RED_ENABLED 1U
#define CYBSP_LED_RED_PORT GPIO_PRT0
#define CYBSP_LED_RED_PIN 3U
#define CYBSP_LED_RED_NUM 3U
#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_3_HSIOM
#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
#define SW2_PORT GPIO_PRT0
#define SW2_PIN 4U
#define SW2_NUM 4U
#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
#define SW2_INIT_DRIVESTATE 1
#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_BTN2_ENABLED 1U
#define CYBSP_BTN2_PORT GPIO_PRT0
#define CYBSP_BTN2_PIN 4U
#define CYBSP_BTN2_NUM 4U
#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define SW2_IRQ ioss_interrupts_gpio_0_IRQn
#define LED_BLUE_PORT GPIO_PRT11
#define LED_BLUE_PIN 1U
#define LED_BLUE_NUM 1U
#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_BLUE_INIT_DRIVESTATE 1
#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_LED_BLUE_ENABLED 1U
#define CYBSP_LED_BLUE_PORT GPIO_PRT11
#define CYBSP_LED_BLUE_PIN 1U
#define CYBSP_LED_BLUE_NUM 1U
#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_SS0_PORT GPIO_PRT11
#define QSPI_SS0_PIN 2U
#define QSPI_SS0_NUM 2U
#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define QSPI_SS0_INIT_DRIVESTATE 1
#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_SS_ENABLED 1U
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
#define CYBSP_QSPI_SS_PIN 2U
#define CYBSP_QSPI_SS_NUM 2U
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA3_PORT GPIO_PRT11
#define QSPI_DATA3_PIN 3U
#define QSPI_DATA3_NUM 3U
#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA3_INIT_DRIVESTATE 1
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D3_ENABLED 1U
#define CYBSP_QSPI_D3_PORT GPIO_PRT11
#define CYBSP_QSPI_D3_PIN 3U
#define CYBSP_QSPI_D3_NUM 3U
#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA2_PORT GPIO_PRT11
#define QSPI_DATA2_PIN 4U
#define QSPI_DATA2_NUM 4U
#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA2_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D2_ENABLED 1U
#define CYBSP_QSPI_D2_PORT GPIO_PRT11
#define CYBSP_QSPI_D2_PIN 4U
#define CYBSP_QSPI_D2_NUM 4U
#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA1_PORT GPIO_PRT11
#define QSPI_DATA1_PIN 5U
#define QSPI_DATA1_NUM 5U
#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA1_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D1_ENABLED 1U
#define CYBSP_QSPI_D1_PORT GPIO_PRT11
#define CYBSP_QSPI_D1_PIN 5U
#define CYBSP_QSPI_D1_NUM 5U
#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA0_PORT GPIO_PRT11
#define QSPI_DATA0_PIN 6U
#define QSPI_DATA0_NUM 6U
#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA0_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D0_ENABLED 1U
#define CYBSP_QSPI_D0_PORT GPIO_PRT11
#define CYBSP_QSPI_D0_PIN 6U
#define CYBSP_QSPI_D0_NUM 6U
#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
#define QSPI_SPI_CLOCK_PIN 7U
#define QSPI_SPI_CLOCK_NUM 7U
#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_SCK_ENABLED 1U
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SCK_PIN 7U
#define CYBSP_QSPI_SCK_NUM 7U
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
#define LED9_PORT GPIO_PRT13
#define LED9_PIN 7U
#define LED9_NUM 7U
#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED9_INIT_DRIVESTATE 1
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_LED9_ENABLED 1U
#define CYBSP_LED9_PORT GPIO_PRT13
#define CYBSP_LED9_PIN 7U
#define CYBSP_LED9_NUM 7U
#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED9_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
#define CSD_TX_PORT GPIO_PRT1
#define CSD_TX_PIN 0U
#define CSD_TX_NUM 0U
#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_TX_INIT_DRIVESTATE 1
#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CSD_TX_PIN 0U
#define CYBSP_CSD_TX_NUM 0U
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define LED_GREEN_PORT GPIO_PRT1
#define LED_GREEN_PIN 1U
#define LED_GREEN_NUM 1U
#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_GREEN_INIT_DRIVESTATE 1
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_LED_GREEN_ENABLED 1U
#define CYBSP_LED_GREEN_PORT GPIO_PRT1
#define CYBSP_LED_GREEN_PIN 1U
#define CYBSP_LED_GREEN_NUM 1U
#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
#define ioss_0_port_1_pin_4_PORT GPIO_PRT1
#define ioss_0_port_1_pin_4_PIN 4U
#define ioss_0_port_1_pin_4_NUM 4U
#define ioss_0_port_1_pin_4_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define ioss_0_port_1_pin_4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_4_HSIOM
#define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_1_pin_4_IRQ ioss_interrupts_gpio_1_IRQn
#define LED8_PORT GPIO_PRT1
#define LED8_PIN 5U
#define LED8_NUM 5U
#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED8_INIT_DRIVESTATE 1
#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_LED8_ENABLED 1U
#define CYBSP_LED8_PORT GPIO_PRT1
#define CYBSP_LED8_PIN 5U
#define CYBSP_LED8_NUM 5U
#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED8_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
#define UART_TX_PORT GPIO_PRT5
#define UART_TX_PIN 1U
#define UART_TX_NUM 1U
#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define UART_TX_INIT_DRIVESTATE 1
#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_DEBUG_UART_RX_ENABLED 1U
#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_RX_PIN 0U
#define CYBSP_DEBUG_UART_RX_NUM 0U
#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_DEBUG_UART_TX_ENABLED 1U
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_TX_PIN 1U
#define CYBSP_DEBUG_UART_TX_NUM 1U
#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#define EZI2C_SCL_PORT GPIO_PRT6
#define EZI2C_SCL_PIN 0U
#define EZI2C_SCL_NUM 0U
#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define EZI2C_SCL_INIT_DRIVESTATE 1
#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PIN 0U
#define CYBSP_EZI2C_SCL_NUM 0U
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_0_HSIOM
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#define EZI2C_SDA_PORT GPIO_PRT6
#define EZI2C_SDA_PIN 1U
#define EZI2C_SDA_NUM 1U
#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define EZI2C_SDA_INIT_DRIVESTATE 1
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_EZI2C_SDA_ENABLED 1U
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
#define CYBSP_EZI2C_SDA_PIN 1U
#define CYBSP_EZI2C_SDA_NUM 1U
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_1_HSIOM
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#define SWO_PORT GPIO_PRT6
#define SWO_PIN 4U
#define SWO_NUM 4U
#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define SWO_INIT_DRIVESTATE 1
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define SWDIO_PORT GPIO_PRT6
#define SWDIO_PIN 6U
#define SWDIO_NUM 6U
#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define SWDIO_INIT_DRIVESTATE 1
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#define SWDCK_PORT GPIO_PRT6
#define SWDCK_PIN 7U
#define SWDCK_NUM 7U
#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define SWDCK_INIT_DRIVESTATE 1
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
#define CYBSP_SWDCK_PIN 7U
#define CYBSP_SWDCK_NUM 7U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#define CINA_PORT GPIO_PRT7
#define CINA_PIN 1U
#define CINA_NUM 1U
#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
#define CINA_INIT_DRIVESTATE 1
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_CINA_ENABLED 1U
#define CYBSP_CINA_PORT GPIO_PRT7
#define CYBSP_CINA_PIN 1U
#define CYBSP_CINA_NUM 1U
#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
#define CINB_PORT GPIO_PRT7
#define CINB_PIN 2U
#define CINB_NUM 2U
#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
#define CINB_INIT_DRIVESTATE 1
#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CINB_ENABLED 1U
#define CYBSP_CINB_PORT GPIO_PRT7
#define CYBSP_CINB_PIN 2U
#define CYBSP_CINB_NUM 2U
#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
#define CMOD_PORT GPIO_PRT7
#define CMOD_PIN 7U
#define CMOD_NUM 7U
#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
#define CMOD_INIT_DRIVESTATE 1
#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CMOD_ENABLED 1U
#define CYBSP_CMOD_PORT GPIO_PRT7
#define CYBSP_CMOD_PIN 7U
#define CYBSP_CMOD_NUM 7U
#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#define CSD_BTN0_PORT GPIO_PRT8
#define CSD_BTN0_PIN 1U
#define CSD_BTN0_NUM 1U
#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_BTN0_INIT_DRIVESTATE 1
#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CSD_BTN0_ENABLED 1U
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
#define CYBSP_CSD_BTN0_PIN 1U
#define CYBSP_CSD_BTN0_NUM 1U
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_BTN1_PORT GPIO_PRT8
#define CSD_BTN1_PIN 2U
#define CSD_BTN1_NUM 2U
#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_BTN1_INIT_DRIVESTATE 1
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_BTN1_ENABLED 1U
#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
#define CYBSP_CSD_BTN1_PIN 2U
#define CYBSP_CSD_BTN1_NUM 2U
#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD0_PORT GPIO_PRT8
#define CSD_SLD0_PIN 3U
#define CSD_SLD0_NUM 3U
#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD0_INIT_DRIVESTATE 1
#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD0_ENABLED 1U
#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
#define CYBSP_CSD_SLD0_PIN 3U
#define CYBSP_CSD_SLD0_NUM 3U
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD1_PORT GPIO_PRT8
#define CSD_SLD1_PIN 4U
#define CSD_SLD1_NUM 4U
#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD1_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD1_ENABLED 1U
#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
#define CYBSP_CSD_SLD1_PIN 4U
#define CYBSP_CSD_SLD1_NUM 4U
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD2_PORT GPIO_PRT8
#define CSD_SLD2_PIN 5U
#define CSD_SLD2_NUM 5U
#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD2_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD2_ENABLED 1U
#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
#define CYBSP_CSD_SLD2_PIN 5U
#define CYBSP_CSD_SLD2_NUM 5U
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD3_PORT GPIO_PRT8
#define CSD_SLD3_PIN 6U
#define CSD_SLD3_NUM 6U
#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD3_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD3_ENABLED 1U
#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
#define CYBSP_CSD_SLD3_PIN 6U
#define CYBSP_CSD_SLD3_NUM 6U
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD4_PORT GPIO_PRT8
#define CSD_SLD4_PIN 7U
#define CSD_SLD4_NUM 7U
#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD4_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD4_ENABLED 1U
#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
#define CYBSP_CSD_SLD4_PIN 7U
#define CYBSP_CSD_SLD4_NUM 7U
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
extern const cy_stc_gpio_pin_config_t WCO_IN_config;
extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t LED_RED_config;
extern const cy_stc_gpio_pin_config_t SW2_config;
extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
extern const cy_stc_gpio_pin_config_t LED9_config;
extern const cy_stc_gpio_pin_config_t CSD_TX_config;
extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
extern const cy_stc_gpio_pin_config_t ioss_0_port_1_pin_4_config;
extern const cy_stc_gpio_pin_config_t LED8_config;
extern const cy_stc_gpio_pin_config_t UART_TX_config;
extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
extern const cy_stc_gpio_pin_config_t SWO_config;
extern const cy_stc_gpio_pin_config_t SWDIO_config;
extern const cy_stc_gpio_pin_config_t SWDCK_config;
extern const cy_stc_gpio_pin_config_t CINA_config;
extern const cy_stc_gpio_pin_config_t CINB_config;
extern const cy_stc_gpio_pin_config_t CMOD_config;
extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
void init_cycfg_pins(void);

53
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h
View File

@ -1,53 +0,0 @@
/*******************************************************************************
* File Name: cycfg_platform.h
*
* Description:
* Platform configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PLATFORM_H)
#define CYCFG_PLATFORM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_ble_clk.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_platform(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PLATFORM_H */

264
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.c Normal file
View File

@ -0,0 +1,264 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.c
*
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_QUAD,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0x01U,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 4U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25FL512S_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25FL512S_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 520U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 134000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 340U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

49
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.h Normal file
View File

@ -0,0 +1,49 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.h
*
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#ifndef CYCFG_QSPI_MEMSLOT_H
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h
View File

@ -32,6 +32,8 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
@ -39,6 +41,7 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
@ -50,8 +53,8 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA

200
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.c
View File

@ -1,8 +1,8 @@
/*******************************************************************************
* File Name: cycfg_platform.c
* File Name: cycfg_system.c
*
* Description:
* Platform configuration
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@ -22,26 +22,29 @@
* limitations under the License.
********************************************************************************/
#include "cycfg_platform.h"
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
#define CY_CFG_SYSCLK_PLL1_AVAILABLE 1
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_FLL_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL
#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
@ -56,13 +59,15 @@
#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@ -78,12 +83,24 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
.outputDiv = 5,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while(1);
}
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
{
Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
}
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
@ -108,17 +125,23 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(2U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(4U, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(4U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(4U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@ -153,12 +176,30 @@ __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkPeriSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_Pll0Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
{
Cy_SysClk_ClkTimerDisable();
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
Cy_SysClk_ClkTimerSetDivider(0U);
Cy_SysClk_ClkTimerEnable();
}
__STATIC_INLINE void Cy_SysClk_WcoInit()
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
@ -168,37 +209,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
__STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
#else
Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
#endif /* CY_CFG_PWR_USING_LDO */
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif /* CY_CFG_PWR_USING_PMIC */
}
void init_cycfg_platform(void)
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */){ Cy_SysLib_ResetBackupDomain(); }
#endif
#ifdef CY_CFG_PWR_ENABLED
/* Configure power mode */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
#else
Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
#endif
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif
#endif
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
{
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@ -210,62 +272,10 @@ void init_cycfg_platform(void)
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
#ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
#endif
#ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
#endif
#ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
#endif
#ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
#endif
#ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
#endif
#ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
#endif
#ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
#endif
#ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
#endif
#ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
#endif
#ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
#endif
#ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
#endif
#ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
#endif
#ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@ -498,6 +508,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);

91
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.h Normal file
View File

@ -0,0 +1,91 @@
/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_ble_clk.h"
#include "cy_systick.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_1_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF1 1UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
#define CY_CFG_PWR_MODE_LP 0x01UL
#define CY_CFG_PWR_MODE_ULP 0x02UL
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_system(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_SYSTEM_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg Normal file
View File

@ -0,0 +1,2 @@
set SMIF_BANKS {
}

710
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/design.modus Normal file
View File

@ -0,0 +1,710 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C6347BZI-BLD53">
<BlockConfig>
<Block location="bless[0]" alias="CYBSP_BLE" template="mxs40ble" version="1.1">
<Param id="BleConfigurator" value="0"/>
<Param id="BleSharing" value="0"/>
<Param id="ExtPaLnaEnable" value="false"/>
</Block>
<Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Block>
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
<Param id="SensorCount" value="12"/>
<Param id="CapacitorCount" value="3"/>
<Param id="SensorName0" value="Cmod"/>
<Param id="SensorName1" value="CintA"/>
<Param id="SensorName2" value="CintB"/>
<Param id="SensorName3" value="Button0_Rx0"/>
<Param id="SensorName4" value="Button0_Tx"/>
<Param id="SensorName5" value="Button1_Rx0"/>
<Param id="SensorName6" value="Button1_Tx"/>
<Param id="SensorName7" value="LinearSlider0_Sns0"/>
<Param id="SensorName8" value="LinearSlider0_Sns1"/>
<Param id="SensorName9" value="LinearSlider0_Sns2"/>
<Param id="SensorName10" value="LinearSlider0_Sns3"/>
<Param id="SensorName11" value="LinearSlider0_Sns4"/>
<Param id="CapSenseConfigurator" value="0"/>
<Param id="CapSenseTuner" value="0"/>
<Param id="CsdAdcEnable" value="false"/>
<Param id="numChannels" value="1"/>
<Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
<Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
<Param id="acqTime" value="10"/>
<Param id="autoCalibrInterval" value="30"/>
<Param id="vref" value="-1"/>
<Param id="operClkDivider" value="1"/>
<Param id="azTime" value="5"/>
<Param id="csdInitTime" value="25"/>
<Param id="inFlash" value="true"/>
<Param id="CsdIdacEnable" value="false"/>
<Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
<Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
<Param id="csdIdacInitTime" value="25"/>
<Param id="idacInFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[0]" alias="CYBSP_WCO_IN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[1]" alias="CYBSP_WCO_OUT" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[3]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED_BLUE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED_GREEN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[1]" alias="CYBSP_EZI2C_SDA" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWDCK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[1]" alias="CYBSP_CINA" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[2]" alias="CYBSP_CINB" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[1]" alias="CYBSP_CSD_BTN0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[2]" alias="CYBSP_CSD_BTN1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[3]" alias="CYBSP_CSD_SLD0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[4]" alias="CYBSP_CSD_SLD1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[5]" alias="CYBSP_CSD_SLD2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[6]" alias="CYBSP_CSD_SLD3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[7]" alias="CYBSP_CSD_SLD4" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="8"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
<Param id="DataRate" value="100"/>
<Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
<Param id="SlaveAddress1" value="8"/>
<Param id="SlaveAddress2" value="9"/>
<Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="8"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="8"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="false"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
<Param id="isrUnderflow" value="false"/>
<Param id="isrCmdOverflow" value="false"/>
<Param id="isrDataOverflow" value="false"/>
<Param id="rxTriggerLevel" value="0"/>
<Param id="txTriggerLevel" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
<Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
<Param id="sourceClock" value="lfclk"/>
</Block>
<Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="wco"/>
</Block>
<Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
</Block>
<Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Block>
<Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
</Block>
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
</Block>
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="wco"/>
</Block>
<Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
<Param id="optimization" value="MinPower"/>
</Block>
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
<Param id="sourceClock" value="imo"/>
<Param id="timerDivider" value="1"/>
</Block>
<Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
<Param id="clockLostDetection" value="false"/>
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
<Param id="accuracyPpm" value="150"/>
</Block>
<Block location="srss[0].mcwdt[0]" alias="CYBSP_MCWDT0" template="mxs40mcwdt" version="1.0">
<Param id="C0ClearOnMatch" value="FREE_RUNNING"/>
<Param id="C0Match" value="32768"/>
<Param id="C0Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C1ClearOnMatch" value="FREE_RUNNING"/>
<Param id="C1Match" value="32768"/>
<Param id="C1Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C2Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C2Period" value="16"/>
<Param id="CascadeC0C1" value="true"/>
<Param id="CascadeC1C2" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
<Param id="deepsleepLatency" value="0"/>
<Param id="vddaMv" value="3300"/>
<Param id="vdddMv" value="3300"/>
<Param id="vBackupMv" value="3300"/>
<Param id="vddNsMv" value="3300"/>
<Param id="vddio0Mv" value="3300"/>
<Param id="vddio1Mv" value="3300"/>
</Block>
<Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
<Param id="format" value="0"/>
<Param id="dst" value="false"/>
<Param id="dstFormat" value="CY_RTC_DST_RELATIVE"/>
<Param id="sec" value="0"/>
<Param id="min" value="0"/>
<Param id="hrFormat" value="CY_RTC_24_HOURS"/>
<Param id="hr" value="12"/>
<Param id="amPmPeriodOfDay" value="CY_RTC_AM"/>
<Param id="dayOfTheWeek" value="CY_RTC_SUNDAY"/>
<Param id="dayOfTheMonth" value="1"/>
<Param id="month" value="CY_RTC_JANUARY"/>
<Param id="year" value="0"/>
<Param id="dstStartMonth" value="CY_RTC_MARCH"/>
<Param id="dstStartDay" value="22"/>
<Param id="dstStartWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
<Param id="dstStartDayOfWeek" value="CY_RTC_SUNDAY"/>
<Param id="dstStartHour" value="0"/>
<Param id="dstStopMonth" value="CY_RTC_OCTOBER"/>
<Param id="dstStopDay" value="22"/>
<Param id="dstStopWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
<Param id="dstStopDayOfWeek" value="CY_RTC_SUNDAY"/>
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
</BlockConfig>
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
<Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
<Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
</Net>
<Net>
<Port name="csd[0].csd[0].clock[0]"/>
<Port name="peri[0].div_8[0].clk[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[0].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
<Port name="scb[5].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
<Port name="scb[5].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[1].digital_inout[0]"/>
<Port name="scb[3].i2c_sda[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
<Port name="smif[0].spi_select0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
<Port name="smif[0].spi_data3[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
<Port name="smif[0].spi_data2[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
<Port name="smif[0].spi_data1[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
<Port name="smif[0].spi_data0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[2].clk[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
<Mux name="sense" location="csd[0].csd[0]">
<Arm>
<Port name="ioss[0].port[7].pin[7].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[3].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[4].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[5].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[6].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[7].analog[0]"/>
</Arm>
</Mux>
</Netlist>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<ConfiguratorData/>
</Design>

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c
View File

@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
init_cycfg_platform();
init_cycfg_routing();
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h
View File

@ -30,12 +30,12 @@ extern "C" {
#endif
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_dmas.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
#include "cycfg_platform.h"
#include "cycfg_routing.h"
void init_cycfg_all(void);

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c
View File

@ -44,10 +44,6 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
}

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h
View File

@ -32,18 +32,21 @@
extern "C" {
#endif
#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
#define peri_0_div_16_0_NUM 0U
#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_0_NUM 0U
#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_1_NUM 1U
#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_2_NUM 2U
#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_3_NUM 3U
#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_4_NUM 4U
#define CYBSP_USB_CLK_DIV_ENABLED 1U
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_CLK_DIV_NUM 0U
#define CYBSP_SDIO_DIV_ENABLED 1U
#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_SDIO_DIV_NUM 0U
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 3U
void init_cycfg_clocks(void);

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h
View File

@ -32,15 +32,19 @@
extern "C" {
#endif
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn

57
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c
View File

@ -24,14 +24,13 @@
#include "cycfg_peripherals.h"
#define PWM_INPUT_DISABLED 0x7U
#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
@ -43,7 +42,7 @@ cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
const cy_stc_scb_uart_config_t BT_UART_config =
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@ -71,7 +70,7 @@ const cy_stc_scb_uart_config_t BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@ -79,7 +78,7 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t KITPROG_UART_config =
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@ -107,14 +106,14 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_smif_config_t QSPI_config =
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = QSPI_DESELECT_DELAY,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
const cy_stc_mcwdt_config_t MCWDT0_config =
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@ -127,7 +126,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
const cy_stc_rtc_config_t RTC_config =
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
@ -139,35 +138,7 @@ const cy_stc_rtc_config_t RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
const cy_stc_tcpwm_pwm_config_t PWM_config =
{
.pwmMode = CY_TCPWM_PWM_MODE_PWM,
.clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
.pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
.deadTimeClocks = 0,
.runMode = CY_TCPWM_PWM_CONTINUOUS,
.period0 = 32000,
.period1 = 32768,
.enablePeriodSwap = false,
.compare0 = 16384,
.compare1 = 16384,
.enableCompareSwap = false,
.interruptSources = CY_TCPWM_INT_NONE,
.invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
.invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
.killMode = CY_TCPWM_PWM_STOP_ON_KILL,
.swapInputMode = PWM_INPUT_DISABLED & 0x3U,
.swapInput = CY_TCPWM_INPUT_0,
.reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
.reloadInput = CY_TCPWM_INPUT_0,
.startInputMode = PWM_INPUT_DISABLED & 0x3U,
.startInput = CY_TCPWM_INPUT_0,
.killInputMode = PWM_INPUT_DISABLED & 0x3U,
.killInput = CY_TCPWM_INPUT_0,
.countInputMode = PWM_INPUT_DISABLED & 0x3U,
.countInput = CY_TCPWM_INPUT_1,
};
const cy_stc_usbfs_dev_drv_config_t USBUART_config =
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
@ -182,13 +153,13 @@ const cy_stc_usbfs_dev_drv_config_t USBUART_config =
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
.intrLevelSel = USBUART_INTR_LVL_SEL,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
@ -196,8 +167,6 @@ void init_cycfg_peripherals(void)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);

115
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h
View File

@ -33,20 +33,19 @@
#include "cy_smif.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_tcpwm_pwm.h"
#include "cycfg_routing.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 4u
#define CY_CAPSENSE_PERI_DIV_INDEX 3u
#define Cmod_PORT GPIO_PRT7
#define CintA_PORT GPIO_PRT7
#define CintB_PORT GPIO_PRT7
@ -74,61 +73,65 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
#define CapSense_HW CSD0
#define CapSense_IRQ csd_interrupt_IRQn
#define BT_UART_HW SCB2
#define BT_UART_IRQ scb_2_interrupt_IRQn
#define CSD_COMM_HW SCB3
#define CSD_COMM_IRQ scb_3_interrupt_IRQn
#define KITPROG_UART_HW SCB5
#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
#define QSPI_HW SMIF0
#define QSPI_IRQ smif_interrupt_IRQn
#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_DATALINES0_1 (1UL)
#define QSPI_DATALINES2_3 (1UL)
#define QSPI_DATALINES4_5 (0UL)
#define QSPI_DATALINES6_7 (0UL)
#define QSPI_SS0 (1UL)
#define QSPI_SS1 (0UL)
#define QSPI_SS2 (0UL)
#define QSPI_SS3 (0UL)
#define QSPI_DESELECT_DELAY 7
#define MCWDT0_HW MCWDT_STRUCT0
#define RTC_10_MONTH_OFFSET (28U)
#define RTC_MONTH_OFFSET (24U)
#define RTC_10_DAY_OFFSET (20U)
#define RTC_DAY_OFFSET (16U)
#define RTC_1000_YEAR_OFFSET (12U)
#define RTC_100_YEAR_OFFSET (8U)
#define RTC_10_YEAR_OFFSET (4U)
#define RTC_YEAR_OFFSET (0U)
#define PWM_HW TCPWM1
#define PWM_NUM 1UL
#define PWM_MASK (1UL << 1)
#define USBUART_ACTIVE_ENDPOINTS_MASK 7U
#define USBUART_ENDPOINTS_BUFFER_SIZE 140U
#define USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define USBUART_USB_CORE 4U
#define USBUART_HW USBFS0
#define USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define USBUART_MED_IRQ usb_interrupt_med_IRQn
#define USBUART_LO_IRQ usb_interrupt_lo_IRQn
#define CYBSP_CSD_HW CSD0
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
#define CYBSP_BT_UART_ENABLED 1U
#define CYBSP_BT_UART_HW SCB2
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_DATALINES0_1 (1UL)
#define CYBSP_QSPI_DATALINES2_3 (1UL)
#define CYBSP_QSPI_DATALINES4_5 (0UL)
#define CYBSP_QSPI_DATALINES6_7 (0UL)
#define CYBSP_QSPI_SS0 (1UL)
#define CYBSP_QSPI_SS1 (0UL)
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
#define CYBSP_MCWDT0_ENABLED 1U
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
#define CYBSP_RTC_ENABLED 1U
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
#define CYBSP_RTC_MONTH_OFFSET (24U)
#define CYBSP_RTC_10_DAY_OFFSET (20U)
#define CYBSP_RTC_DAY_OFFSET (16U)
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_SDIO_ENABLED 1U
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_USB_CORE 4U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t BT_UART_config;
extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
extern const cy_stc_smif_config_t QSPI_config;
extern const cy_stc_mcwdt_config_t MCWDT0_config;
extern const cy_stc_rtc_config_t RTC_config;
extern const cy_stc_tcpwm_pwm_config_t PWM_config;
extern const cy_stc_usbfs_dev_drv_config_t USBUART_config;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
void init_cycfg_peripherals(void);

368
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c
View File

File diff suppressed because it is too large Load Diff

796
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h
View File

@ -33,126 +33,139 @@
extern "C" {
#endif
#define WCO_IN_PORT GPIO_PRT0
#define WCO_IN_PIN 0U
#define WCO_IN_NUM 0U
#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define WCO_IN_INIT_DRIVESTATE 1
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT0
#define CYBSP_WCO_IN_PIN 0U
#define CYBSP_WCO_IN_NUM 0U
#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#define WCO_OUT_PORT GPIO_PRT0
#define WCO_OUT_PIN 1U
#define WCO_OUT_NUM 1U
#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define WCO_OUT_INIT_DRIVESTATE 1
#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT0
#define CYBSP_WCO_OUT_PIN 1U
#define CYBSP_WCO_OUT_NUM 1U
#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define LED_RED_PORT GPIO_PRT0
#define LED_RED_PIN 3U
#define LED_RED_NUM 3U
#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_RED_INIT_DRIVESTATE 1
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_LED_RED_ENABLED 1U
#define CYBSP_LED_RED_PORT GPIO_PRT0
#define CYBSP_LED_RED_PIN 3U
#define CYBSP_LED_RED_NUM 3U
#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_3_HSIOM
#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
#define SW2_PORT GPIO_PRT0
#define SW2_PIN 4U
#define SW2_NUM 4U
#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
#define SW2_INIT_DRIVESTATE 1
#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_BTN2_ENABLED 1U
#define CYBSP_BTN2_PORT GPIO_PRT0
#define CYBSP_BTN2_PIN 4U
#define CYBSP_BTN2_NUM 4U
#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define SW2_IRQ ioss_interrupts_gpio_0_IRQn
#define LED_BLUE_PORT GPIO_PRT11
#define LED_BLUE_PIN 1U
#define LED_BLUE_NUM 1U
#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_BLUE_INIT_DRIVESTATE 1
#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_LED_BLUE_ENABLED 1U
#define CYBSP_LED_BLUE_PORT GPIO_PRT11
#define CYBSP_LED_BLUE_PIN 1U
#define CYBSP_LED_BLUE_NUM 1U
#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_SS0_PORT GPIO_PRT11
#define QSPI_SS0_PIN 2U
#define QSPI_SS0_NUM 2U
#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define QSPI_SS0_INIT_DRIVESTATE 1
#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_SS_ENABLED 1U
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
#define CYBSP_QSPI_SS_PIN 2U
#define CYBSP_QSPI_SS_NUM 2U
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA3_PORT GPIO_PRT11
#define QSPI_DATA3_PIN 3U
#define QSPI_DATA3_NUM 3U
#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA3_INIT_DRIVESTATE 1
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D3_ENABLED 1U
#define CYBSP_QSPI_D3_PORT GPIO_PRT11
#define CYBSP_QSPI_D3_PIN 3U
#define CYBSP_QSPI_D3_NUM 3U
#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA2_PORT GPIO_PRT11
#define QSPI_DATA2_PIN 4U
#define QSPI_DATA2_NUM 4U
#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA2_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D2_ENABLED 1U
#define CYBSP_QSPI_D2_PORT GPIO_PRT11
#define CYBSP_QSPI_D2_PIN 4U
#define CYBSP_QSPI_D2_NUM 4U
#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA1_PORT GPIO_PRT11
#define QSPI_DATA1_PIN 5U
#define QSPI_DATA1_NUM 5U
#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA1_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D1_ENABLED 1U
#define CYBSP_QSPI_D1_PORT GPIO_PRT11
#define CYBSP_QSPI_D1_PIN 5U
#define CYBSP_QSPI_D1_NUM 5U
#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA0_PORT GPIO_PRT11
#define QSPI_DATA0_PIN 6U
#define QSPI_DATA0_NUM 6U
#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA0_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_D0_ENABLED 1U
#define CYBSP_QSPI_D0_PORT GPIO_PRT11
#define CYBSP_QSPI_D0_PIN 6U
#define CYBSP_QSPI_D0_NUM 6U
#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
#define QSPI_SPI_CLOCK_PIN 7U
#define QSPI_SPI_CLOCK_NUM 7U
#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_SCK_ENABLED 1U
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SCK_PIN 7U
#define CYBSP_QSPI_SCK_NUM 7U
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
#define LED9_PORT GPIO_PRT13
#define LED9_PIN 7U
#define LED9_NUM 7U
#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED9_INIT_DRIVESTATE 1
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_LED9_ENABLED 1U
#define CYBSP_LED9_PORT GPIO_PRT13
#define CYBSP_LED9_PIN 7U
#define CYBSP_LED9_NUM 7U
#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED9_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
#define ioss_0_port_14_pin_0_ENABLED 1U
#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
#define ioss_0_port_14_pin_0_PIN 0U
#define ioss_0_port_14_pin_0_NUM 0U
@ -162,6 +175,7 @@ extern "C" {
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
#define ioss_0_port_14_pin_1_ENABLED 1U
#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
#define ioss_0_port_14_pin_1_PIN 1U
#define ioss_0_port_14_pin_1_NUM 1U
@ -171,395 +185,441 @@ extern "C" {
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
#define CSD_TX_PORT GPIO_PRT1
#define CSD_TX_PIN 0U
#define CSD_TX_NUM 0U
#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_TX_INIT_DRIVESTATE 1
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CSD_TX_PIN 0U
#define CYBSP_CSD_TX_NUM 0U
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define LED_GREEN_PORT GPIO_PRT1
#define LED_GREEN_PIN 1U
#define LED_GREEN_NUM 1U
#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_GREEN_INIT_DRIVESTATE 1
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_LED_GREEN_ENABLED 1U
#define CYBSP_LED_GREEN_PORT GPIO_PRT1
#define CYBSP_LED_GREEN_PIN 1U
#define CYBSP_LED_GREEN_NUM 1U
#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
#define LED8_PORT GPIO_PRT1
#define LED8_PIN 5U
#define LED8_NUM 5U
#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED8_INIT_DRIVESTATE 1
#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_LED8_ENABLED 1U
#define CYBSP_LED8_PORT GPIO_PRT1
#define CYBSP_LED8_PIN 5U
#define CYBSP_LED8_NUM 5U
#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED8_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
#define SDHC0_DAT0_PORT GPIO_PRT2
#define SDHC0_DAT0_PIN 0U
#define SDHC0_DAT0_NUM 0U
#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT0_INIT_DRIVESTATE 1
#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_WIFI_SDIO_D0_ENABLED 1U
#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_D0_PIN 0U
#define CYBSP_WIFI_SDIO_D0_NUM 0U
#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_0_HSIOM
#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_DAT1_PORT GPIO_PRT2
#define SDHC0_DAT1_PIN 1U
#define SDHC0_DAT1_NUM 1U
#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT1_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_2_pin_0_HSIOM
#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_D1_ENABLED 1U
#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_D1_PIN 1U
#define CYBSP_WIFI_SDIO_D1_NUM 1U
#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_1_HSIOM
#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_DAT2_PORT GPIO_PRT2
#define SDHC0_DAT2_PIN 2U
#define SDHC0_DAT2_NUM 2U
#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT2_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_2_pin_1_HSIOM
#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_D2_ENABLED 1U
#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_D2_PIN 2U
#define CYBSP_WIFI_SDIO_D2_NUM 2U
#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_2_HSIOM
#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_DAT3_PORT GPIO_PRT2
#define SDHC0_DAT3_PIN 3U
#define SDHC0_DAT3_NUM 3U
#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT3_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_2_pin_2_HSIOM
#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_D3_ENABLED 1U
#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_D3_PIN 3U
#define CYBSP_WIFI_SDIO_D3_NUM 3U
#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_3_HSIOM
#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_CMD_PORT GPIO_PRT2
#define SDHC0_CMD_PIN 4U
#define SDHC0_CMD_NUM 4U
#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_CMD_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_2_pin_3_HSIOM
#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_CMD_PIN 4U
#define CYBSP_WIFI_SDIO_CMD_NUM 4U
#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_4_HSIOM
#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_CLK_PORT GPIO_PRT2
#define SDHC0_CLK_PIN 5U
#define SDHC0_CLK_NUM 5U
#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define SDHC0_CLK_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_CLK_PIN 5U
#define CYBSP_WIFI_SDIO_CLK_NUM 5U
#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_5_HSIOM
#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
#define ENABLE_WIFI_PORT GPIO_PRT2
#define ENABLE_WIFI_PIN 6U
#define ENABLE_WIFI_NUM 6U
#define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define ENABLE_WIFI_INIT_DRIVESTATE 0
#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U
#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT2
#define CYBSP_WIFI_WL_REG_ON_PIN 6U
#define CYBSP_WIFI_WL_REG_ON_NUM 6U
#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 0
#ifndef ioss_0_port_2_pin_6_HSIOM
#define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM
#define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn
#define BT_UART_RX_PORT GPIO_PRT3
#define BT_UART_RX_PIN 0U
#define BT_UART_RX_NUM 0U
#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define BT_UART_RX_INIT_DRIVESTATE 1
#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_2_pin_6_HSIOM
#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
#define CYBSP_WIFI_HOST_WAKE_PIN 7U
#define CYBSP_WIFI_HOST_WAKE_NUM 7U
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_2_pin_7_HSIOM
#define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_BT_UART_RX_ENABLED 1U
#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
#define CYBSP_BT_UART_RX_PIN 0U
#define CYBSP_BT_UART_RX_NUM 0U
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_0_HSIOM
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_UART_TX_PORT GPIO_PRT3
#define BT_UART_TX_PIN 1U
#define BT_UART_TX_NUM 1U
#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define BT_UART_TX_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_UART_TX_ENABLED 1U
#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
#define CYBSP_BT_UART_TX_PIN 1U
#define CYBSP_BT_UART_TX_NUM 1U
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_1_HSIOM
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_UART_RTS_PORT GPIO_PRT3
#define BT_UART_RTS_PIN 2U
#define BT_UART_RTS_NUM 2U
#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define BT_UART_RTS_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_UART_RTS_ENABLED 1U
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
#define CYBSP_BT_UART_RTS_PIN 2U
#define CYBSP_BT_UART_RTS_NUM 2U
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_2_HSIOM
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_UART_CTS_PORT GPIO_PRT3
#define BT_UART_CTS_PIN 3U
#define BT_UART_CTS_NUM 3U
#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
#define BT_UART_CTS_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_UART_CTS_ENABLED 1U
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
#define CYBSP_BT_UART_CTS_PIN 3U
#define CYBSP_BT_UART_CTS_NUM 3U
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_3_HSIOM
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_POWER_PORT GPIO_PRT3
#define BT_POWER_PIN 4U
#define BT_POWER_NUM 4U
#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
#define BT_POWER_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_POWER_ENABLED 1U
#define CYBSP_BT_POWER_PORT GPIO_PRT3
#define CYBSP_BT_POWER_PIN 4U
#define CYBSP_BT_POWER_NUM 4U
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_4_HSIOM
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_HOST_WAKE_PORT GPIO_PRT3
#define BT_HOST_WAKE_PIN 5U
#define BT_HOST_WAKE_NUM 5U
#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define BT_HOST_WAKE_INIT_DRIVESTATE 0
#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
#define CYBSP_BT_HOST_WAKE_PIN 5U
#define CYBSP_BT_HOST_WAKE_NUM 5U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_3_pin_5_HSIOM
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_DEVICE_WAKE_PORT GPIO_PRT4
#define BT_DEVICE_WAKE_PIN 0U
#define BT_DEVICE_WAKE_NUM 0U
#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
#define CYBSP_BT_DEVICE_WAKE_PIN 0U
#define CYBSP_BT_DEVICE_WAKE_NUM 0U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#define UART_RX_PORT GPIO_PRT5
#define UART_RX_PIN 0U
#define UART_RX_NUM 0U
#define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define UART_RX_INIT_DRIVESTATE 1
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_DEBUG_UART_RX_ENABLED 1U
#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_RX_PIN 0U
#define CYBSP_DEBUG_UART_RX_NUM 0U
#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
#define UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
#define UART_TX_PORT GPIO_PRT5
#define UART_TX_PIN 1U
#define UART_TX_NUM 1U
#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define UART_TX_INIT_DRIVESTATE 1
#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_DEBUG_UART_TX_ENABLED 1U
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_TX_PIN 1U
#define CYBSP_DEBUG_UART_TX_NUM 1U
#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#define EZI2C_SCL_PORT GPIO_PRT6
#define EZI2C_SCL_PIN 0U
#define EZI2C_SCL_NUM 0U
#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define EZI2C_SCL_INIT_DRIVESTATE 1
#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PIN 0U
#define CYBSP_EZI2C_SCL_NUM 0U
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_0_HSIOM
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#define EZI2C_SDA_PORT GPIO_PRT6
#define EZI2C_SDA_PIN 1U
#define EZI2C_SDA_NUM 1U
#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define EZI2C_SDA_INIT_DRIVESTATE 1
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_EZI2C_SDA_ENABLED 1U
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
#define CYBSP_EZI2C_SDA_PIN 1U
#define CYBSP_EZI2C_SDA_NUM 1U
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_1_HSIOM
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#define SWO_PORT GPIO_PRT6
#define SWO_PIN 4U
#define SWO_NUM 4U
#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define SWO_INIT_DRIVESTATE 1
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define SWDIO_PORT GPIO_PRT6
#define SWDIO_PIN 6U
#define SWDIO_NUM 6U
#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define SWDIO_INIT_DRIVESTATE 1
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#define SWDCK_PORT GPIO_PRT6
#define SWDCK_PIN 7U
#define SWDCK_NUM 7U
#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define SWDCK_INIT_DRIVESTATE 1
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
#define CYBSP_SWDCK_PIN 7U
#define CYBSP_SWDCK_NUM 7U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#define CINA_PORT GPIO_PRT7
#define CINA_PIN 1U
#define CINA_NUM 1U
#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
#define CINA_INIT_DRIVESTATE 1
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_CINA_ENABLED 1U
#define CYBSP_CINA_PORT GPIO_PRT7
#define CYBSP_CINA_PIN 1U
#define CYBSP_CINA_NUM 1U
#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
#define CINB_PORT GPIO_PRT7
#define CINB_PIN 2U
#define CINB_NUM 2U
#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
#define CINB_INIT_DRIVESTATE 1
#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CINB_ENABLED 1U
#define CYBSP_CINB_PORT GPIO_PRT7
#define CYBSP_CINB_PIN 2U
#define CYBSP_CINB_NUM 2U
#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
#define CMOD_PORT GPIO_PRT7
#define CMOD_PIN 7U
#define CMOD_NUM 7U
#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
#define CMOD_INIT_DRIVESTATE 1
#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CMOD_ENABLED 1U
#define CYBSP_CMOD_PORT GPIO_PRT7
#define CYBSP_CMOD_PIN 7U
#define CYBSP_CMOD_NUM 7U
#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#define CSD_BTN0_PORT GPIO_PRT8
#define CSD_BTN0_PIN 1U
#define CSD_BTN0_NUM 1U
#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_BTN0_INIT_DRIVESTATE 1
#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CSD_BTN0_ENABLED 1U
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
#define CYBSP_CSD_BTN0_PIN 1U
#define CYBSP_CSD_BTN0_NUM 1U
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_BTN1_PORT GPIO_PRT8
#define CSD_BTN1_PIN 2U
#define CSD_BTN1_NUM 2U
#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_BTN1_INIT_DRIVESTATE 1
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_BTN1_ENABLED 1U
#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
#define CYBSP_CSD_BTN1_PIN 2U
#define CYBSP_CSD_BTN1_NUM 2U
#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD0_PORT GPIO_PRT8
#define CSD_SLD0_PIN 3U
#define CSD_SLD0_NUM 3U
#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD0_INIT_DRIVESTATE 1
#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD0_ENABLED 1U
#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
#define CYBSP_CSD_SLD0_PIN 3U
#define CYBSP_CSD_SLD0_NUM 3U
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD1_PORT GPIO_PRT8
#define CSD_SLD1_PIN 4U
#define CSD_SLD1_NUM 4U
#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD1_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD1_ENABLED 1U
#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
#define CYBSP_CSD_SLD1_PIN 4U
#define CYBSP_CSD_SLD1_NUM 4U
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD2_PORT GPIO_PRT8
#define CSD_SLD2_PIN 5U
#define CSD_SLD2_NUM 5U
#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD2_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD2_ENABLED 1U
#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
#define CYBSP_CSD_SLD2_PIN 5U
#define CYBSP_CSD_SLD2_NUM 5U
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD3_PORT GPIO_PRT8
#define CSD_SLD3_PIN 6U
#define CSD_SLD3_NUM 6U
#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD3_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD3_ENABLED 1U
#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
#define CYBSP_CSD_SLD3_PIN 6U
#define CYBSP_CSD_SLD3_NUM 6U
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD4_PORT GPIO_PRT8
#define CSD_SLD4_PIN 7U
#define CSD_SLD4_NUM 7U
#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD4_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD4_ENABLED 1U
#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
#define CYBSP_CSD_SLD4_PIN 7U
#define CYBSP_CSD_SLD4_NUM 7U
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
extern const cy_stc_gpio_pin_config_t WCO_IN_config;
extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t LED_RED_config;
extern const cy_stc_gpio_pin_config_t SW2_config;
extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
extern const cy_stc_gpio_pin_config_t LED9_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
extern const cy_stc_gpio_pin_config_t CSD_TX_config;
extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
extern const cy_stc_gpio_pin_config_t LED8_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config;
extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config;
extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config;
extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config;
extern const cy_stc_gpio_pin_config_t BT_UART_RX_config;
extern const cy_stc_gpio_pin_config_t BT_UART_TX_config;
extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config;
extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config;
extern const cy_stc_gpio_pin_config_t BT_POWER_config;
extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config;
extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config;
extern const cy_stc_gpio_pin_config_t UART_RX_config;
extern const cy_stc_gpio_pin_config_t UART_TX_config;
extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
extern const cy_stc_gpio_pin_config_t SWO_config;
extern const cy_stc_gpio_pin_config_t SWDIO_config;
extern const cy_stc_gpio_pin_config_t SWDCK_config;
extern const cy_stc_gpio_pin_config_t CINA_config;
extern const cy_stc_gpio_pin_config_t CINB_config;
extern const cy_stc_gpio_pin_config_t CMOD_config;
extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
void init_cycfg_pins(void);

53
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h
View File

@ -1,53 +0,0 @@
/*******************************************************************************
* File Name: cycfg_platform.h
*
* Description:
* Platform configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PLATFORM_H)
#define CYCFG_PLATFORM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_platform(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PLATFORM_H */

264
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.c Normal file
View File

@ -0,0 +1,264 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.c
*
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_QUAD,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0x01U,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 4U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25FL512S_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25FL512S_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 520U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 134000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 340U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

49
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.h Normal file
View File

@ -0,0 +1,49 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.h
*
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#ifndef CYCFG_QSPI_MEMSLOT_H
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c
View File

@ -34,12 +34,12 @@ void init_cycfg_routing(void)
{
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |

29
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h
View File

@ -32,14 +32,17 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
@ -60,26 +63,26 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
#if defined(__cplusplus)
}

157
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.c
View File

@ -1,8 +1,8 @@
/*******************************************************************************
* File Name: cycfg_platform.c
* File Name: cycfg_system.c
*
* Description:
* Platform configuration
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@ -22,7 +22,7 @@
* limitations under the License.
********************************************************************************/
#include "cycfg_platform.h"
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
@ -64,10 +64,10 @@
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@ -127,21 +127,21 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
}
__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
{
Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(1U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(2U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(3U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@ -209,42 +209,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
__STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
#else
Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
#endif /* CY_CFG_PWR_USING_LDO */
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif /* CY_CFG_PWR_USING_PMIC */
}
void init_cycfg_platform(void)
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#endif
#ifdef CY_CFG_PWR_ENABLED
/* Configure power mode */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
#else
Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
#endif
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif
#endif
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
{
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@ -260,61 +276,6 @@ void init_cycfg_platform(void)
(void)Cy_BLE_EcoReset();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
#endif
#ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
#endif
#ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
#endif
#ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
#endif
#ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
#endif
#ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
#endif
#ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
#endif
#ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
#endif
#ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
#endif
#ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
#endif
#ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
#endif
#ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
#endif
#ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
#endif
#ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@ -547,6 +508,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);

90
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.h Normal file
View File

@ -0,0 +1,90 @@
/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_1_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF1 1UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
#define CY_CFG_PWR_MODE_LP 0x01UL
#define CY_CFG_PWR_MODE_ULP 0x02UL
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_system(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_SYSTEM_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/qspi_config.cfg Normal file
View File

@ -0,0 +1,2 @@
set SMIF_BANKS {
}

1183
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/design.modus Normal file
View File

File diff suppressed because it is too large Load Diff

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c
View File

@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
init_cycfg_platform();
init_cycfg_routing();
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h
View File

@ -30,11 +30,11 @@ extern "C" {
#endif
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
#include "cycfg_platform.h"
#include "cycfg_routing.h"
void init_cycfg_all(void);

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c
View File

@ -38,8 +38,4 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
}

17
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h
View File

@ -32,14 +32,15 @@
extern "C" {
#endif
#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_0_NUM 0U
#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_1_NUM 1U
#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_2_NUM 2U
#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_3_NUM 3U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 0U
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
void init_cycfg_clocks(void);

62
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c
View File

@ -24,13 +24,11 @@
#include "cycfg_peripherals.h"
#define PWM_INPUT_DISABLED 0x7U
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
const cy_stc_scb_uart_config_t BT_UART_config =
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@ -58,7 +56,7 @@ const cy_stc_scb_uart_config_t BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@ -66,7 +64,7 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t KITPROG_UART_config =
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@ -94,31 +92,31 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
cy_en_sd_host_card_capacity_t RADIO_cardCapacity = CY_SD_HOST_SDSC;
cy_en_sd_host_card_type_t RADIO_cardType = CY_SD_HOST_NOT_EMMC;
uint32_t RADIO_rca = 0u;
const cy_stc_sd_host_init_config_t RADIO_config =
cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
uint32_t CYBSP_RADIO_rca = 0u;
const cy_stc_sd_host_init_config_t CYBSP_RADIO_config =
{
.emmc = false,
.dmaType = CY_SD_HOST_DMA_SDMA,
.enableLedControl = false,
};
cy_stc_sd_host_sd_card_config_t RADIO_card_cfg =
cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg =
{
.lowVoltageSignaling = false,
.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
.cardType = &RADIO_cardType,
.rca = &RADIO_rca,
.cardCapacity = &RADIO_cardCapacity,
.cardType = &CYBSP_RADIO_cardType,
.rca = &CYBSP_RADIO_rca,
.cardCapacity = &CYBSP_RADIO_cardCapacity,
};
const cy_stc_smif_config_t QSPI_config =
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = QSPI_DESELECT_DELAY,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
const cy_stc_mcwdt_config_t MCWDT0_config =
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@ -131,7 +129,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
const cy_stc_rtc_config_t RTC_config =
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
@ -143,34 +141,6 @@ const cy_stc_rtc_config_t RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
const cy_stc_tcpwm_pwm_config_t PWM_config =
{
.pwmMode = CY_TCPWM_PWM_MODE_PWM,
.clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
.pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
.deadTimeClocks = 0,
.runMode = CY_TCPWM_PWM_CONTINUOUS,
.period0 = 32000,
.period1 = 32768,
.enablePeriodSwap = false,
.compare0 = 16384,
.compare1 = 16384,
.enableCompareSwap = false,
.interruptSources = CY_TCPWM_INT_NONE,
.invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
.invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
.killMode = CY_TCPWM_PWM_STOP_ON_KILL,
.swapInputMode = PWM_INPUT_DISABLED & 0x3U,
.swapInput = CY_TCPWM_INPUT_0,
.reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
.reloadInput = CY_TCPWM_INPUT_0,
.startInputMode = PWM_INPUT_DISABLED & 0x3U,
.startInput = CY_TCPWM_INPUT_0,
.killInputMode = PWM_INPUT_DISABLED & 0x3U,
.killInput = CY_TCPWM_INPUT_0,
.countInputMode = PWM_INPUT_DISABLED & 0x3U,
.countInput = CY_TCPWM_INPUT_1,
};
void init_cycfg_peripherals(void)
@ -182,6 +152,4 @@ void init_cycfg_peripherals(void)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
}

108
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h
View File

@ -34,13 +34,12 @@
#include "cy_smif.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_tcpwm_pwm.h"
#include "cycfg_routing.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 50000000u
@ -74,59 +73,62 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
#define CapSense_HW CSD0
#define CapSense_IRQ csd_interrupt_IRQn
#define BT_UART_HW SCB2
#define BT_UART_IRQ scb_2_interrupt_IRQn
#define CSD_COMM_HW SCB3
#define CSD_COMM_IRQ scb_3_interrupt_IRQn
#define KITPROG_UART_HW SCB5
#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
#define RADIO_HW SDHC0
#define RADIO_IRQ sdhc_0_interrupt_general_IRQn
#define QSPI_HW SMIF0
#define QSPI_IRQ smif_interrupt_IRQn
#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_DATALINES0_1 (1UL)
#define QSPI_DATALINES2_3 (1UL)
#define QSPI_DATALINES4_5 (0UL)
#define QSPI_DATALINES6_7 (0UL)
#define QSPI_SS0 (1UL)
#define QSPI_SS1 (0UL)
#define QSPI_SS2 (0UL)
#define QSPI_SS3 (0UL)
#define QSPI_DESELECT_DELAY 7
#define MCWDT0_HW MCWDT_STRUCT0
#define RTC_10_MONTH_OFFSET (28U)
#define RTC_MONTH_OFFSET (24U)
#define RTC_10_DAY_OFFSET (20U)
#define RTC_DAY_OFFSET (16U)
#define RTC_1000_YEAR_OFFSET (12U)
#define RTC_100_YEAR_OFFSET (8U)
#define RTC_10_YEAR_OFFSET (4U)
#define RTC_YEAR_OFFSET (0U)
#define PWM_HW TCPWM0
#define PWM_NUM 1UL
#define PWM_MASK (1UL << 1)
#define CYBSP_CSD_HW CSD0
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
#define CYBSP_BT_UART_ENABLED 1U
#define CYBSP_BT_UART_HW SCB2
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_RADIO_ENABLED 1U
#define CYBSP_RADIO_HW SDHC0
#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_DATALINES0_1 (1UL)
#define CYBSP_QSPI_DATALINES2_3 (1UL)
#define CYBSP_QSPI_DATALINES4_5 (0UL)
#define CYBSP_QSPI_DATALINES6_7 (0UL)
#define CYBSP_QSPI_SS0 (1UL)
#define CYBSP_QSPI_SS1 (0UL)
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
#define CYBSP_MCWDT0_ENABLED 1U
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
#define CYBSP_RTC_ENABLED 1U
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
#define CYBSP_RTC_MONTH_OFFSET (24U)
#define CYBSP_RTC_10_DAY_OFFSET (20U)
#define CYBSP_RTC_DAY_OFFSET (16U)
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t BT_UART_config;
extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
extern cy_en_sd_host_card_capacity_t RADIO_cardCapacity;
extern cy_en_sd_host_card_type_t RADIO_cardType;
extern uint32_t RADIO_rca;
extern const cy_stc_sd_host_init_config_t RADIO_config;
extern cy_stc_sd_host_sd_card_config_t RADIO_card_cfg;
extern const cy_stc_smif_config_t QSPI_config;
extern const cy_stc_mcwdt_config_t MCWDT0_config;
extern const cy_stc_rtc_config_t RTC_config;
extern const cy_stc_tcpwm_pwm_config_t PWM_config;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
extern uint32_t CYBSP_RADIO_rca;
extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
void init_cycfg_peripherals(void);

490
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c
View File

@ -24,704 +24,656 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t WCO_IN_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = WCO_IN_HSIOM,
.hsiom = CYBSP_WCO_IN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t WCO_OUT_config =
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = WCO_OUT_HSIOM,
.hsiom = CYBSP_WCO_OUT_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SW2_config =
const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = SW2_HSIOM,
.hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED_BLUE_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED_BLUE_HSIOM,
.hsiom = CYBSP_QSPI_SS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_SS0_config =
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = QSPI_SS0_HSIOM,
.hsiom = CYBSP_QSPI_SCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = QSPI_DATA0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config =
const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = QSPI_SPI_CLOCK_HSIOM,
.hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED9_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED9_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_TX_HSIOM,
.hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED_GREEN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED_GREEN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t LED8_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = LED8_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SDHC0_DAT0_config =
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = SDHC0_DAT0_HSIOM,
.hsiom = CYBSP_WIFI_SDIO_DAT0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SDHC0_DAT1_config =
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = SDHC0_DAT1_HSIOM,
.hsiom = CYBSP_WIFI_SDIO_DAT1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SDHC0_DAT2_config =
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = SDHC0_DAT2_HSIOM,
.hsiom = CYBSP_WIFI_SDIO_DAT2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SDHC0_DAT3_config =
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = SDHC0_DAT3_HSIOM,
.hsiom = CYBSP_WIFI_SDIO_DAT3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SDHC0_CMD_config =
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = SDHC0_CMD_HSIOM,
.hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SDHC0_CLK_config =
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = SDHC0_CLK_HSIOM,
.hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t BT_UART_RX_config =
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = BT_UART_RX_HSIOM,
.hsiom = CYBSP_BT_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t BT_UART_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = BT_UART_TX_HSIOM,
.hsiom = CYBSP_BT_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t BT_UART_RTS_config =
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = BT_UART_RTS_HSIOM,
.hsiom = CYBSP_BT_UART_RTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t BT_UART_CTS_config =
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = BT_UART_CTS_HSIOM,
.hsiom = CYBSP_BT_UART_CTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t BT_POWER_config =
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
.hsiom = BT_POWER_HSIOM,
.hsiom = CYBSP_BT_POWER_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config =
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = BT_HOST_WAKE_HSIOM,
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config =
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = BT_DEVICE_WAKE_HSIOM,
.hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t UART_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = UART_TX_HSIOM,
.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t EZI2C_SCL_config =
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
.hsiom = EZI2C_SCL_HSIOM,
.hsiom = CYBSP_EZI2C_SCL_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t EZI2C_SDA_config =
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
.hsiom = EZI2C_SDA_HSIOM,
.hsiom = CYBSP_EZI2C_SDA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SWO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = SWO_HSIOM,
.hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SWDIO_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = SWDIO_HSIOM,
.hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t SWDCK_config =
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
.hsiom = SWDCK_HSIOM,
.hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CINA_config =
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CINA_HSIOM,
.hsiom = CYBSP_CINA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CINB_config =
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CINB_HSIOM,
.hsiom = CYBSP_CINB_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CMOD_config =
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CMOD_HSIOM,
.hsiom = CYBSP_CMOD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_BTN0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_BTN0_HSIOM,
.hsiom = CYBSP_CSD_BTN0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_BTN1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_BTN1_HSIOM,
.hsiom = CYBSP_CSD_BTN1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD0_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD0_HSIOM,
.hsiom = CYBSP_CSD_SLD0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD1_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD1_HSIOM,
.hsiom = CYBSP_CSD_SLD1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD2_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD2_HSIOM,
.hsiom = CYBSP_CSD_SLD2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD3_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD3_HSIOM,
.hsiom = CYBSP_CSD_SLD3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CSD_SLD4_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CSD_SLD4_HSIOM,
.hsiom = CYBSP_CSD_SLD4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@ -732,72 +684,66 @@ const cy_stc_gpio_pin_config_t CSD_SLD4_config =
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config);
Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config);
Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config);
Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config);
Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT0_PORT, CYBSP_WIFI_SDIO_DAT0_PIN, &CYBSP_WIFI_SDIO_DAT0_config);
Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT1_PORT, CYBSP_WIFI_SDIO_DAT1_PIN, &CYBSP_WIFI_SDIO_DAT1_config);
Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT2_PORT, CYBSP_WIFI_SDIO_DAT2_PIN, &CYBSP_WIFI_SDIO_DAT2_config);
Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT3_PORT, CYBSP_WIFI_SDIO_DAT3_PIN, &CYBSP_WIFI_SDIO_DAT3_config);
Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config);
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config);
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config);
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config);
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config);
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config);
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config);
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config);
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config);
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config);
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config);
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config);
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);

736
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h
View File

@ -33,491 +33,499 @@
extern "C" {
#endif
#define WCO_IN_PORT GPIO_PRT0
#define WCO_IN_PIN 0U
#define WCO_IN_NUM 0U
#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define WCO_IN_INIT_DRIVESTATE 1
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT0
#define CYBSP_WCO_IN_PIN 0U
#define CYBSP_WCO_IN_NUM 0U
#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#define WCO_OUT_PORT GPIO_PRT0
#define WCO_OUT_PIN 1U
#define WCO_OUT_NUM 1U
#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define WCO_OUT_INIT_DRIVESTATE 1
#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT0
#define CYBSP_WCO_OUT_PIN 1U
#define CYBSP_WCO_OUT_NUM 1U
#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define LED_RED_PORT GPIO_PRT0
#define LED_RED_PIN 3U
#define LED_RED_NUM 3U
#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_3_HSIOM
#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
#define SW2_PORT GPIO_PRT0
#define SW2_PIN 4U
#define SW2_NUM 4U
#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
#define SW2_INIT_DRIVESTATE 1
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_BTN2_ENABLED 1U
#define CYBSP_BTN2_PORT GPIO_PRT0
#define CYBSP_BTN2_PIN 4U
#define CYBSP_BTN2_NUM 4U
#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define SW2_IRQ ioss_interrupts_gpio_0_IRQn
#define LED_BLUE_PORT GPIO_PRT11
#define LED_BLUE_PIN 1U
#define LED_BLUE_NUM 1U
#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_BLUE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_SS0_PORT GPIO_PRT11
#define QSPI_SS0_PIN 2U
#define QSPI_SS0_NUM 2U
#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define QSPI_SS0_INIT_DRIVESTATE 1
#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_QSPI_SS_ENABLED 1U
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
#define CYBSP_QSPI_SS_PIN 2U
#define CYBSP_QSPI_SS_NUM 2U
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA3_PORT GPIO_PRT11
#define QSPI_DATA3_PIN 3U
#define QSPI_DATA3_NUM 3U
#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA3_INIT_DRIVESTATE 1
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_DATA3_ENABLED 1U
#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA3_PIN 3U
#define CYBSP_QSPI_DATA3_NUM 3U
#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA2_PORT GPIO_PRT11
#define QSPI_DATA2_PIN 4U
#define QSPI_DATA2_NUM 4U
#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA2_INIT_DRIVESTATE 1
#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_DATA2_ENABLED 1U
#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA2_PIN 4U
#define CYBSP_QSPI_DATA2_NUM 4U
#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA1_PORT GPIO_PRT11
#define QSPI_DATA1_PIN 5U
#define QSPI_DATA1_NUM 5U
#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA1_INIT_DRIVESTATE 1
#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_DATA1_ENABLED 1U
#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA1_PIN 5U
#define CYBSP_QSPI_DATA1_NUM 5U
#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_DATA0_PORT GPIO_PRT11
#define QSPI_DATA0_PIN 6U
#define QSPI_DATA0_NUM 6U
#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
#define QSPI_DATA0_INIT_DRIVESTATE 1
#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_DATA0_ENABLED 1U
#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA0_PIN 6U
#define CYBSP_QSPI_DATA0_NUM 6U
#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
#define QSPI_SPI_CLOCK_PIN 7U
#define QSPI_SPI_CLOCK_NUM 7U
#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_QSPI_SCK_ENABLED 1U
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SCK_PIN 7U
#define CYBSP_QSPI_SCK_NUM 7U
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
#define LED9_PORT GPIO_PRT13
#define LED9_PIN 7U
#define LED9_NUM 7U
#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED9_INIT_DRIVESTATE 1
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_LED_RED_ENABLED 1U
#define CYBSP_LED_RED_PORT GPIO_PRT13
#define CYBSP_LED_RED_PIN 7U
#define CYBSP_LED_RED_NUM 7U
#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
#define CSD_TX_PORT GPIO_PRT1
#define CSD_TX_PIN 0U
#define CSD_TX_NUM 0U
#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_TX_INIT_DRIVESTATE 1
#define CYBSP_LED_RED_HSIOM ioss_0_port_13_pin_7_HSIOM
#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_13_IRQn
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CSD_TX_PIN 0U
#define CYBSP_CSD_TX_NUM 0U
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define LED_GREEN_PORT GPIO_PRT1
#define LED_GREEN_PIN 1U
#define LED_GREEN_NUM 1U
#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_GREEN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
#define LED8_PORT GPIO_PRT1
#define LED8_PIN 5U
#define LED8_NUM 5U
#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED8_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
#define SDHC0_DAT0_PORT GPIO_PRT2
#define SDHC0_DAT0_PIN 0U
#define SDHC0_DAT0_NUM 0U
#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT0_INIT_DRIVESTATE 1
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_WIFI_SDIO_DAT0_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT0_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT0_PIN 0U
#define CYBSP_WIFI_SDIO_DAT0_NUM 0U
#define CYBSP_WIFI_SDIO_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_0_HSIOM
#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_DAT1_PORT GPIO_PRT2
#define SDHC0_DAT1_PIN 1U
#define SDHC0_DAT1_NUM 1U
#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT1_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
#define CYBSP_WIFI_SDIO_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_DAT1_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT1_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT1_PIN 1U
#define CYBSP_WIFI_SDIO_DAT1_NUM 1U
#define CYBSP_WIFI_SDIO_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_1_HSIOM
#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_DAT2_PORT GPIO_PRT2
#define SDHC0_DAT2_PIN 2U
#define SDHC0_DAT2_NUM 2U
#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT2_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
#define CYBSP_WIFI_SDIO_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_DAT2_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT2_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT2_PIN 2U
#define CYBSP_WIFI_SDIO_DAT2_NUM 2U
#define CYBSP_WIFI_SDIO_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_2_HSIOM
#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_DAT3_PORT GPIO_PRT2
#define SDHC0_DAT3_PIN 3U
#define SDHC0_DAT3_NUM 3U
#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_DAT3_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
#define CYBSP_WIFI_SDIO_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_DAT3_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT3_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT3_PIN 3U
#define CYBSP_WIFI_SDIO_DAT3_NUM 3U
#define CYBSP_WIFI_SDIO_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_3_HSIOM
#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_CMD_PORT GPIO_PRT2
#define SDHC0_CMD_PIN 4U
#define SDHC0_CMD_NUM 4U
#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_CMD_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
#define CYBSP_WIFI_SDIO_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_CMD_PIN 4U
#define CYBSP_WIFI_SDIO_CMD_NUM 4U
#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_4_HSIOM
#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
#define SDHC0_CLK_PORT GPIO_PRT2
#define SDHC0_CLK_PIN 5U
#define SDHC0_CLK_NUM 5U
#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG
#define SDHC0_CLK_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_CLK_PIN 5U
#define CYBSP_WIFI_SDIO_CLK_NUM 5U
#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_5_HSIOM
#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
#define BT_UART_RX_PORT GPIO_PRT3
#define BT_UART_RX_PIN 0U
#define BT_UART_RX_NUM 0U
#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define BT_UART_RX_INIT_DRIVESTATE 1
#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_BT_UART_RX_ENABLED 1U
#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
#define CYBSP_BT_UART_RX_PIN 0U
#define CYBSP_BT_UART_RX_NUM 0U
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_0_HSIOM
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_UART_TX_PORT GPIO_PRT3
#define BT_UART_TX_PIN 1U
#define BT_UART_TX_NUM 1U
#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define BT_UART_TX_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_UART_TX_ENABLED 1U
#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
#define CYBSP_BT_UART_TX_PIN 1U
#define CYBSP_BT_UART_TX_NUM 1U
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_1_HSIOM
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_UART_RTS_PORT GPIO_PRT3
#define BT_UART_RTS_PIN 2U
#define BT_UART_RTS_NUM 2U
#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define BT_UART_RTS_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_UART_RTS_ENABLED 1U
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
#define CYBSP_BT_UART_RTS_PIN 2U
#define CYBSP_BT_UART_RTS_NUM 2U
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_2_HSIOM
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_UART_CTS_PORT GPIO_PRT3
#define BT_UART_CTS_PIN 3U
#define BT_UART_CTS_NUM 3U
#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
#define BT_UART_CTS_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_UART_CTS_ENABLED 1U
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
#define CYBSP_BT_UART_CTS_PIN 3U
#define CYBSP_BT_UART_CTS_NUM 3U
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_3_HSIOM
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_POWER_PORT GPIO_PRT3
#define BT_POWER_PIN 4U
#define BT_POWER_NUM 4U
#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
#define BT_POWER_INIT_DRIVESTATE 1
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_POWER_ENABLED 1U
#define CYBSP_BT_POWER_PORT GPIO_PRT3
#define CYBSP_BT_POWER_PIN 4U
#define CYBSP_BT_POWER_NUM 4U
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_4_HSIOM
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_HOST_WAKE_PORT GPIO_PRT3
#define BT_HOST_WAKE_PIN 5U
#define BT_HOST_WAKE_NUM 5U
#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define BT_HOST_WAKE_INIT_DRIVESTATE 0
#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
#define CYBSP_BT_HOST_WAKE_PIN 5U
#define CYBSP_BT_HOST_WAKE_NUM 5U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_3_pin_5_HSIOM
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#define BT_DEVICE_WAKE_PORT GPIO_PRT4
#define BT_DEVICE_WAKE_PIN 0U
#define BT_DEVICE_WAKE_NUM 0U
#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
#define CYBSP_BT_DEVICE_WAKE_PIN 0U
#define CYBSP_BT_DEVICE_WAKE_NUM 0U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#define UART_TX_PORT GPIO_PRT5
#define UART_TX_PIN 1U
#define UART_TX_NUM 1U
#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define UART_TX_INIT_DRIVESTATE 1
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_DEBUG_UART_RX_ENABLED 1U
#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_RX_PIN 0U
#define CYBSP_DEBUG_UART_RX_NUM 0U
#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_DEBUG_UART_TX_ENABLED 1U
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_TX_PIN 1U
#define CYBSP_DEBUG_UART_TX_NUM 1U
#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#define EZI2C_SCL_PORT GPIO_PRT6
#define EZI2C_SCL_PIN 0U
#define EZI2C_SCL_NUM 0U
#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define EZI2C_SCL_INIT_DRIVESTATE 1
#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PIN 0U
#define CYBSP_EZI2C_SCL_NUM 0U
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_0_HSIOM
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#define EZI2C_SDA_PORT GPIO_PRT6
#define EZI2C_SDA_PIN 1U
#define EZI2C_SDA_NUM 1U
#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define EZI2C_SDA_INIT_DRIVESTATE 1
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_EZI2C_SDA_ENABLED 1U
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
#define CYBSP_EZI2C_SDA_PIN 1U
#define CYBSP_EZI2C_SDA_NUM 1U
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_1_HSIOM
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#define SWO_PORT GPIO_PRT6
#define SWO_PIN 4U
#define SWO_NUM 4U
#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define SWO_INIT_DRIVESTATE 1
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define SWDIO_PORT GPIO_PRT6
#define SWDIO_PIN 6U
#define SWDIO_NUM 6U
#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define SWDIO_INIT_DRIVESTATE 1
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#define SWDCK_PORT GPIO_PRT6
#define SWDCK_PIN 7U
#define SWDCK_NUM 7U
#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define SWDCK_INIT_DRIVESTATE 1
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
#define CYBSP_SWDCK_PIN 7U
#define CYBSP_SWDCK_NUM 7U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#define CINA_PORT GPIO_PRT7
#define CINA_PIN 1U
#define CINA_NUM 1U
#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
#define CINA_INIT_DRIVESTATE 1
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_CINA_ENABLED 1U
#define CYBSP_CINA_PORT GPIO_PRT7
#define CYBSP_CINA_PIN 1U
#define CYBSP_CINA_NUM 1U
#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
#define CINB_PORT GPIO_PRT7
#define CINB_PIN 2U
#define CINB_NUM 2U
#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
#define CINB_INIT_DRIVESTATE 1
#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CINB_ENABLED 1U
#define CYBSP_CINB_PORT GPIO_PRT7
#define CYBSP_CINB_PIN 2U
#define CYBSP_CINB_NUM 2U
#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CINB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
#define CMOD_PORT GPIO_PRT7
#define CMOD_PIN 7U
#define CMOD_NUM 7U
#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
#define CMOD_INIT_DRIVESTATE 1
#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CMOD_ENABLED 1U
#define CYBSP_CMOD_PORT GPIO_PRT7
#define CYBSP_CMOD_PIN 7U
#define CYBSP_CMOD_NUM 7U
#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#define CSD_BTN0_PORT GPIO_PRT8
#define CSD_BTN0_PIN 1U
#define CSD_BTN0_NUM 1U
#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_BTN0_INIT_DRIVESTATE 1
#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_CSD_BTN0_ENABLED 1U
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
#define CYBSP_CSD_BTN0_PIN 1U
#define CYBSP_CSD_BTN0_NUM 1U
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_BTN1_PORT GPIO_PRT8
#define CSD_BTN1_PIN 2U
#define CSD_BTN1_NUM 2U
#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_BTN1_INIT_DRIVESTATE 1
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_BTN1_ENABLED 1U
#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
#define CYBSP_CSD_BTN1_PIN 2U
#define CYBSP_CSD_BTN1_NUM 2U
#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD0_PORT GPIO_PRT8
#define CSD_SLD0_PIN 3U
#define CSD_SLD0_NUM 3U
#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD0_INIT_DRIVESTATE 1
#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD0_ENABLED 1U
#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
#define CYBSP_CSD_SLD0_PIN 3U
#define CYBSP_CSD_SLD0_NUM 3U
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD1_PORT GPIO_PRT8
#define CSD_SLD1_PIN 4U
#define CSD_SLD1_NUM 4U
#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD1_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD1_ENABLED 1U
#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
#define CYBSP_CSD_SLD1_PIN 4U
#define CYBSP_CSD_SLD1_NUM 4U
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD2_PORT GPIO_PRT8
#define CSD_SLD2_PIN 5U
#define CSD_SLD2_NUM 5U
#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD2_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD2_ENABLED 1U
#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
#define CYBSP_CSD_SLD2_PIN 5U
#define CYBSP_CSD_SLD2_NUM 5U
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD3_PORT GPIO_PRT8
#define CSD_SLD3_PIN 6U
#define CSD_SLD3_NUM 6U
#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD3_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD3_ENABLED 1U
#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
#define CYBSP_CSD_SLD3_PIN 6U
#define CYBSP_CSD_SLD3_NUM 6U
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CSD_SLD4_PORT GPIO_PRT8
#define CSD_SLD4_PIN 7U
#define CSD_SLD4_NUM 7U
#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CSD_SLD4_INIT_DRIVESTATE 1
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD4_ENABLED 1U
#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
#define CYBSP_CSD_SLD4_PIN 7U
#define CYBSP_CSD_SLD4_NUM 7U
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
extern const cy_stc_gpio_pin_config_t WCO_IN_config;
extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t LED_RED_config;
extern const cy_stc_gpio_pin_config_t SW2_config;
extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
extern const cy_stc_gpio_pin_config_t LED9_config;
extern const cy_stc_gpio_pin_config_t CSD_TX_config;
extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
extern const cy_stc_gpio_pin_config_t LED8_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config;
extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config;
extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config;
extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config;
extern const cy_stc_gpio_pin_config_t BT_UART_RX_config;
extern const cy_stc_gpio_pin_config_t BT_UART_TX_config;
extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config;
extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config;
extern const cy_stc_gpio_pin_config_t BT_POWER_config;
extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config;
extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config;
extern const cy_stc_gpio_pin_config_t UART_TX_config;
extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
extern const cy_stc_gpio_pin_config_t SWO_config;
extern const cy_stc_gpio_pin_config_t SWDIO_config;
extern const cy_stc_gpio_pin_config_t SWDCK_config;
extern const cy_stc_gpio_pin_config_t CINA_config;
extern const cy_stc_gpio_pin_config_t CINB_config;
extern const cy_stc_gpio_pin_config_t CMOD_config;
extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
void init_cycfg_pins(void);

52
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h
View File

@ -1,52 +0,0 @@
/*******************************************************************************
* File Name: cycfg_platform.h
*
* Description:
* Platform configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PLATFORM_H)
#define CYCFG_PLATFORM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_platform(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PLATFORM_H */

264
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.c Normal file
View File

@ -0,0 +1,264 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.c
*
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_QUAD,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0x01U,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 8U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x21U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x12U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25HL512T_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25HL512T_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25HL512T_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25HL512T_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x0001000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25HL512T_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25HL512T_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x0000100U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25HL512T_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25HL512T_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25HL512T_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 42U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 201000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 418U
};
const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25HL512T_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25HL512T_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

49
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.h Normal file
View File

@ -0,0 +1,49 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.h
*
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#ifndef CYCFG_QSPI_MEMSLOT_H
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h
View File

@ -32,14 +32,15 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM0_LINE_COMPL1
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00
#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01
#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02
@ -50,22 +51,23 @@ void init_cycfg_routing(void);
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#if defined(__cplusplus)
}

160
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.c
View File

@ -1,8 +1,8 @@
/*******************************************************************************
* File Name: cycfg_platform.c
* File Name: cycfg_system.c
*
* Description:
* Platform configuration
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@ -22,7 +22,7 @@
* limitations under the License.
********************************************************************************/
#include "cycfg_platform.h"
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
@ -38,6 +38,9 @@
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
@ -51,14 +54,16 @@
#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@ -106,9 +111,15 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(2U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@ -141,6 +152,10 @@ __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
{
Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath5Init()
{
Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
@ -158,42 +173,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
__STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
#else
Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
#endif /* CY_CFG_PWR_USING_LDO */
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif /* CY_CFG_PWR_USING_PMIC */
}
void init_cycfg_platform(void)
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#endif
#ifdef CY_CFG_PWR_ENABLED
/* Configure power mode */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
#else
Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
#endif
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif
#endif
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
{
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@ -209,61 +240,6 @@ void init_cycfg_platform(void)
(void)Cy_BLE_EcoReset();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
#endif
#ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
#endif
#ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
#endif
#ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
#endif
#ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
#endif
#ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
#endif
#ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
#endif
#ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
#endif
#ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
#endif
#ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
#endif
#ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
#endif
#ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
#endif
#ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
#endif
#ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@ -496,6 +472,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);

85
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.h Normal file
View File

@ -0,0 +1,85 @@
/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_pathmux_5_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
#define CY_CFG_PWR_MODE_LP 0x01UL
#define CY_CFG_PWR_MODE_ULP 0x02UL
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_system(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_SYSTEM_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/qspi_config.cfg Normal file
View File

@ -0,0 +1,2 @@
set SMIF_BANKS {
}

885
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/design.modus Normal file
View File

@ -0,0 +1,885 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C624ABZI-D44">
<BlockConfig>
<Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Block>
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="1.1">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
<Param id="SensorCount" value="12"/>
<Param id="CapacitorCount" value="3"/>
<Param id="SensorName0" value="Cmod"/>
<Param id="SensorName1" value="CintA"/>
<Param id="SensorName2" value="CintB"/>
<Param id="SensorName3" value="Button0_Rx0"/>
<Param id="SensorName4" value="Button0_Tx"/>
<Param id="SensorName5" value="Button1_Rx0"/>
<Param id="SensorName6" value="Button1_Tx"/>
<Param id="SensorName7" value="LinearSlider0_Sns0"/>
<Param id="SensorName8" value="LinearSlider0_Sns1"/>
<Param id="SensorName9" value="LinearSlider0_Sns2"/>
<Param id="SensorName10" value="LinearSlider0_Sns3"/>
<Param id="SensorName11" value="LinearSlider0_Sns4"/>
<Param id="CapSenseConfigurator" value="0"/>
<Param id="CapSenseTuner" value="0"/>
<Param id="CsdAdcEnable" value="false"/>
<Param id="numChannels" value="1"/>
<Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
<Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
<Param id="acqTime" value="10"/>
<Param id="autoCalibrInterval" value="30"/>
<Param id="vref" value="-1"/>
<Param id="operClkDivider" value="1"/>
<Param id="azTime" value="5"/>
<Param id="csdInitTime" value="25"/>
<Param id="inFlash" value="true"/>
<Param id="CsdIdacEnable" value="false"/>
<Param id="CsdIdacAEnable" value="false"/>
<Param id="IdacAbusOnly" value="false"/>
<Param id="CsdIdacBEnable" value="false"/>
<Param id="IdacBbusOnly" value="false"/>
<Param id="csdIdacInitTime" value="25"/>
<Param id="idacInFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[0]" alias="CYBSP_WCO_IN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[1]" alias="CYBSP_WCO_OUT" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_DATA3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_DATA2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_DATA1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_DATA0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_DAT0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_DAT1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_DAT2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_DAT3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[1]" alias="CYBSP_BT_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[2]" alias="CYBSP_BT_UART_RTS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[3]" alias="CYBSP_BT_UART_CTS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[4]" alias="CYBSP_BT_POWER" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[1]" alias="CYBSP_EZI2C_SDA" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWDCK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[1]" alias="CYBSP_CINA" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[2]" alias="CYBSP_CINB" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[1]" alias="CYBSP_CSD_BTN0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[2]" alias="CYBSP_CSD_BTN1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[3]" alias="CYBSP_CSD_SLD0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[4]" alias="CYBSP_CSD_SLD1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[5]" alias="CYBSP_CSD_SLD2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[6]" alias="CYBSP_CSD_SLD3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[7]" alias="CYBSP_CSD_SLD4" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="4"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="36"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="scb[2]" alias="CYBSP_BT_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="12"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="8"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="true"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="1"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
<Param id="DataRate" value="100"/>
<Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
<Param id="SlaveAddress1" value="8"/>
<Param id="SlaveAddress2" value="9"/>
<Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="12"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="9"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="false"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_HIGH"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="sdhc[0]" alias="CYBSP_RADIO" template="mxs40sdhost" version="1.0">
<Param id="cardType" value="nonEmmc"/>
<Param id="dmaType" value="CY_SD_HOST_DMA_SDMA"/>
<Param id="enableLedControl" value="false"/>
<Param id="busWidth" value="CY_SD_HOST_BUS_WIDTH_4_BIT"/>
<Param id="lowVoltageSignaling" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value=""/>
<Param id="isrAlignment" value="false"/>
<Param id="isrUnderflow" value="false"/>
<Param id="isrCmdOverflow" value="false"/>
<Param id="isrDataOverflow" value="false"/>
<Param id="rxTriggerLevel" value="0"/>
<Param id="txTriggerLevel" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
<Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="wco"/>
</Block>
<Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
</Block>
<Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Block>
<Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
</Block>
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
</Block>
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="wco"/>
</Block>
<Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[5]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
<Param id="divider" value="2"/>
</Block>
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
<Param id="clockLostDetection" value="false"/>
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
<Param id="accuracyPpm" value="150"/>
</Block>
<Block location="srss[0].mcwdt[0]" alias="CYBSP_MCWDT0" template="mxs40mcwdt" version="1.0">
<Param id="C0ClearOnMatch" value="FREE_RUNNING"/>
<Param id="C0Match" value="32768"/>
<Param id="C0Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C1ClearOnMatch" value="FREE_RUNNING"/>
<Param id="C1Match" value="32768"/>
<Param id="C1Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C2Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C2Period" value="16"/>
<Param id="CascadeC0C1" value="true"/>
<Param id="CascadeC1C2" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
<Param id="deepsleepLatency" value="0"/>
<Param id="vddaMv" value="3300"/>
<Param id="vdddMv" value="3300"/>
<Param id="vBackupMv" value="3300"/>
<Param id="vddNsMv" value="3300"/>
<Param id="vddio0Mv" value="3300"/>
<Param id="vddio1Mv" value="3300"/>
</Block>
<Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
<Param id="format" value="0"/>
<Param id="dst" value="false"/>
<Param id="dstFormat" value="CY_RTC_DST_RELATIVE"/>
<Param id="sec" value="0"/>
<Param id="min" value="0"/>
<Param id="hrFormat" value="CY_RTC_24_HOURS"/>
<Param id="hr" value="12"/>
<Param id="amPmPeriodOfDay" value="CY_RTC_AM"/>
<Param id="dayOfTheWeek" value="CY_RTC_SUNDAY"/>
<Param id="dayOfTheMonth" value="1"/>
<Param id="month" value="CY_RTC_JANUARY"/>
<Param id="year" value="0"/>
<Param id="dstStartMonth" value="CY_RTC_MARCH"/>
<Param id="dstStartDay" value="22"/>
<Param id="dstStartWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
<Param id="dstStartDayOfWeek" value="CY_RTC_SUNDAY"/>
<Param id="dstStartHour" value="0"/>
<Param id="dstStopMonth" value="CY_RTC_OCTOBER"/>
<Param id="dstStopDay" value="22"/>
<Param id="dstStopWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
<Param id="dstStopDayOfWeek" value="CY_RTC_SUNDAY"/>
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
</BlockConfig>
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
<Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
<Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
</Net>
<Net>
<Port name="csd[0].csd[0].clock[0]"/>
<Port name="peri[0].div_8[0].clk[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[0].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[1]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[2]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[3]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].digital_inout[0]"/>
<Port name="sdhc[0].card_cmd[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
<Port name="sdhc[0].clk_card[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
<Port name="scb[2].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[1].digital_inout[0]"/>
<Port name="scb[2].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[2].digital_out[0]"/>
<Port name="scb[2].uart_rts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
<Port name="scb[2].uart_cts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
<Port name="scb[5].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
<Port name="scb[5].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[1].digital_inout[0]"/>
<Port name="scb[3].i2c_sda[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
<Port name="smif[0].spi_select0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
<Port name="smif[0].spi_data3[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
<Port name="smif[0].spi_data2[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
<Port name="smif[0].spi_data1[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
<Port name="smif[0].spi_data0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[2].clk[0]"/>
<Port name="scb[2].clock[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="sdhc[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[4].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
<Mux name="sense" location="csd[0].csd[0]">
<Arm>
<Port name="ioss[0].port[7].pin[7].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[3].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[4].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[5].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[6].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[7].analog[0]"/>
</Arm>
</Mux>
</Netlist>
</Device>
<Device mpn="CYW4343WKUBG">
<BlockConfig/>
<Netlist/>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<ConfiguratorData/>
</Design>

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c
View File

@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
init_cycfg_platform();
init_cycfg_routing();
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h
View File

@ -30,12 +30,12 @@ extern "C" {
#endif
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_dmas.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
#include "cycfg_platform.h"
#include "cycfg_routing.h"
void init_cycfg_all(void);

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c
View File

@ -43,11 +43,15 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 5U, 6U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 6U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
}

33
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h
View File

@ -32,18 +32,27 @@
extern "C" {
#endif
#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
#define peri_0_div_16_0_NUM 0U
#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_0_NUM 0U
#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_1_NUM 1U
#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_2_NUM 2U
#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_3_NUM 3U
#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_4_NUM 4U
#define CYBSP_USB_UART_CLK_DIV_ENABLED 1U
#define CYBSP_USB_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_UART_CLK_DIV_NUM 0U
#define CYBSP_SDIO_CLK_DIV_ENABLED 1U
#define CYBSP_SDIO_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_SDIO_CLK_DIV_NUM 0U
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 4U
#define CYBSP_SPI_CLK_DIV_ENABLED 1U
#define CYBSP_SPI_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_SPI_CLK_DIV_NUM 5U
#define CYBSP_WL_UART_CLK_DIV_ENABLED 1U
#define CYBSP_WL_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_WL_UART_CLK_DIV_NUM 6U
void init_cycfg_clocks(void);

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h
View File

@ -32,15 +32,19 @@
extern "C" {
#endif
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn

107
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c
View File

@ -24,8 +24,7 @@
#include "cycfg_peripherals.h"
#define PWM_INPUT_DISABLED 0x7U
#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
@ -43,7 +42,31 @@ cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
const cy_stc_scb_uart_config_t BT_UART_config =
const cy_stc_scb_spi_config_t CYBSP_SPI_config =
{
.spiMode = CY_SCB_SPI_MASTER,
.subMode = CY_SCB_SPI_MOTOROLA,
.sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
.oversample = 16,
.rxDataWidth = 8UL,
.txDataWidth = 8UL,
.enableMsbFirst = true,
.enableInputFilter = false,
.enableFreeRunSclk = false,
.enableMisoLateSample = true,
.enableTransferSeperation = false,
.ssPolarity = ((CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT0) | \
(CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT1) | \
(CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT2) | \
(CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT3)),
.enableWakeFromSleep = false,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
.masterSlaveIntEnableMask = 0UL,
};
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@ -71,7 +94,7 @@ const cy_stc_scb_uart_config_t BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@ -79,7 +102,7 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t KITPROG_UART_config =
const cy_stc_scb_uart_config_t CYBSP_WL_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@ -107,14 +130,42 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_smif_config_t QSPI_config =
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 8,
.enableMsbFirst = false,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = false,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 0UL,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = QSPI_DESELECT_DELAY,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
const cy_stc_mcwdt_config_t MCWDT0_config =
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@ -127,7 +178,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
const cy_stc_rtc_config_t RTC_config =
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
@ -139,35 +190,7 @@ const cy_stc_rtc_config_t RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
const cy_stc_tcpwm_pwm_config_t PWM_config =
{
.pwmMode = CY_TCPWM_PWM_MODE_PWM,
.clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
.pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
.deadTimeClocks = 0,
.runMode = CY_TCPWM_PWM_CONTINUOUS,
.period0 = 32000,
.period1 = 32768,
.enablePeriodSwap = false,
.compare0 = 16384,
.compare1 = 16384,
.enableCompareSwap = false,
.interruptSources = CY_TCPWM_INT_NONE,
.invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
.invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
.killMode = CY_TCPWM_PWM_STOP_ON_KILL,
.swapInputMode = PWM_INPUT_DISABLED & 0x3U,
.swapInput = CY_TCPWM_INPUT_0,
.reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
.reloadInput = CY_TCPWM_INPUT_0,
.startInputMode = PWM_INPUT_DISABLED & 0x3U,
.startInput = CY_TCPWM_INPUT_0,
.killInputMode = PWM_INPUT_DISABLED & 0x3U,
.killInput = CY_TCPWM_INPUT_0,
.countInputMode = PWM_INPUT_DISABLED & 0x3U,
.countInput = CY_TCPWM_INPUT_1,
};
const cy_stc_usbfs_dev_drv_config_t USBUART_config =
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
@ -182,7 +205,7 @@ const cy_stc_usbfs_dev_drv_config_t USBUART_config =
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
.intrLevelSel = USBUART_INTR_LVL_SEL,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
@ -190,13 +213,15 @@ void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 5U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 6U);
Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);

122
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h
View File

@ -28,19 +28,19 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_csd.h"
#include "cy_scb_spi.h"
#include "cy_scb_uart.h"
#include "cy_scb_ezi2c.h"
#include "cy_smif.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_tcpwm_pwm.h"
#include "cycfg_routing.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_CapSense_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
@ -74,61 +74,73 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
#define CapSense_HW CSD0
#define CapSense_IRQ csd_interrupt_IRQn
#define BT_UART_HW SCB2
#define BT_UART_IRQ scb_2_interrupt_IRQn
#define CSD_COMM_HW SCB3
#define CSD_COMM_IRQ scb_3_interrupt_IRQn
#define KITPROG_UART_HW SCB6
#define KITPROG_UART_IRQ scb_6_interrupt_IRQn
#define QSPI_HW SMIF0
#define QSPI_IRQ smif_interrupt_IRQn
#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define QSPI_DATALINES0_1 (1UL)
#define QSPI_DATALINES2_3 (1UL)
#define QSPI_DATALINES4_5 (0UL)
#define QSPI_DATALINES6_7 (0UL)
#define QSPI_SS0 (1UL)
#define QSPI_SS1 (0UL)
#define QSPI_SS2 (0UL)
#define QSPI_SS3 (0UL)
#define QSPI_DESELECT_DELAY 7
#define MCWDT0_HW MCWDT_STRUCT0
#define RTC_10_MONTH_OFFSET (28U)
#define RTC_MONTH_OFFSET (24U)
#define RTC_10_DAY_OFFSET (20U)
#define RTC_DAY_OFFSET (16U)
#define RTC_1000_YEAR_OFFSET (12U)
#define RTC_100_YEAR_OFFSET (8U)
#define RTC_10_YEAR_OFFSET (4U)
#define RTC_YEAR_OFFSET (0U)
#define PWM_HW TCPWM1
#define PWM_NUM 1UL
#define PWM_MASK (1UL << 1)
#define USBUART_ACTIVE_ENDPOINTS_MASK 7U
#define USBUART_ENDPOINTS_BUFFER_SIZE 140U
#define USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define USBUART_USB_CORE 4U
#define USBUART_HW USBFS0
#define USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define USBUART_MED_IRQ usb_interrupt_med_IRQn
#define USBUART_LO_IRQ usb_interrupt_lo_IRQn
#define CYBSP_CapSense_HW CSD0
#define CYBSP_CapSense_IRQ csd_interrupt_IRQn
#define CYBSP_SPI_ENABLED 1U
#define CYBSP_SPI_HW SCB1
#define CYBSP_SPI_IRQ scb_1_interrupt_IRQn
#define CYBSP_BT_UART_ENABLED 1U
#define CYBSP_BT_UART_HW SCB2
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_WL_UART_ENABLED 1U
#define CYBSP_WL_UART_HW SCB5
#define CYBSP_WL_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB6
#define CYBSP_DEBUG_UART_IRQ scb_6_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_DATALINES0_1 (1UL)
#define CYBSP_QSPI_DATALINES2_3 (1UL)
#define CYBSP_QSPI_DATALINES4_5 (0UL)
#define CYBSP_QSPI_DATALINES6_7 (0UL)
#define CYBSP_QSPI_SS0 (1UL)
#define CYBSP_QSPI_SS1 (0UL)
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
#define CYBSP_MCWDT0_ENABLED 1U
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
#define CYBSP_RTC_ENABLED 1U
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
#define CYBSP_RTC_MONTH_OFFSET (24U)
#define CYBSP_RTC_10_DAY_OFFSET (20U)
#define CYBSP_RTC_DAY_OFFSET (16U)
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_SDIO_ENABLED 1U
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 140U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_USB_CORE 4U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t BT_UART_config;
extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
extern const cy_stc_smif_config_t QSPI_config;
extern const cy_stc_mcwdt_config_t MCWDT0_config;
extern const cy_stc_rtc_config_t RTC_config;
extern const cy_stc_tcpwm_pwm_config_t PWM_config;
extern const cy_stc_usbfs_dev_drv_config_t USBUART_config;
extern const cy_stc_scb_spi_config_t CYBSP_SPI_config;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_WL_UART_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
void init_cycfg_peripherals(void);

988
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c
View File

File diff suppressed because it is too large Load Diff

1170
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h
View File

File diff suppressed because it is too large Load Diff

53
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h
View File

@ -1,53 +0,0 @@
/*******************************************************************************
* File Name: cycfg_platform.h
*
* Description:
* Platform configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PLATFORM_H)
#define CYCFG_PLATFORM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_platform(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PLATFORM_H */

264
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.c Normal file
View File

@ -0,0 +1,264 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.c
*
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_QUAD,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0x01U,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 4U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25FL512S_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25FL512S_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 520U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 134000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 340U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

49
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.h Normal file
View File

@ -0,0 +1,49 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.h
*
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#ifndef CYCFG_QSPI_MEMSLOT_H
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c
View File

@ -32,14 +32,14 @@
void init_cycfg_routing(void)
{
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT5, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT49, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT48, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT45, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT2, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT6, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h
View File

@ -32,14 +32,25 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_10_pin_0_HSIOM P10_0_SCB1_SPI_MOSI
#define ioss_0_port_10_pin_2_HSIOM P10_2_SCB1_SPI_CLK
#define ioss_0_port_10_pin_3_HSIOM P10_3_SCB1_SPI_SELECT0
#define ioss_0_port_11_pin_0_HSIOM P11_0_SCB5_UART_RX
#define ioss_0_port_11_pin_1_HSIOM P11_1_SCB5_UART_TX
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_12_pin_6_ANALOG P12_6_SRSS_ECO_IN
#define ioss_0_port_12_pin_7_ANALOG P12_7_SRSS_ECO_OUT
#define ioss_0_port_13_pin_0_HSIOM P13_0_SCB6_UART_RX
#define ioss_0_port_13_pin_1_HSIOM P13_1_SCB6_UART_TX
#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
@ -57,33 +68,33 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_0_HSIOM P7_0_CPUSS_TRACE_CLOCK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_9_pin_0_HSIOM P9_0_CPUSS_TRACE_DATA3
#define ioss_0_port_9_pin_1_HSIOM P9_1_CPUSS_TRACE_DATA2
#define ioss_0_port_9_pin_2_HSIOM P9_2_CPUSS_TRACE_DATA1
#define ioss_0_port_9_pin_3_HSIOM P9_3_CPUSS_TRACE_DATA0
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT1
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT2
#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT6
#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT5
#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT0
#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT2
#if defined(__cplusplus)
}

157
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.c
View File

@ -1,8 +1,8 @@
/*******************************************************************************
* File Name: cycfg_platform.c
* File Name: cycfg_system.c
*
* Description:
* Platform configuration
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@ -22,7 +22,7 @@
* limitations under the License.
********************************************************************************/
#include "cycfg_platform.h"
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
@ -65,10 +65,10 @@
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@ -141,21 +141,21 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
}
__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
{
Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(1U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(2U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(3U);
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@ -223,42 +223,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
__STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
#else
Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
#endif /* CY_CFG_PWR_USING_LDO */
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif /* CY_CFG_PWR_USING_PMIC */
}
void init_cycfg_platform(void)
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#endif
#ifdef CY_CFG_PWR_ENABLED
/* Configure power mode */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
#else
Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
#endif
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif
#endif
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
{
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@ -274,61 +290,6 @@ void init_cycfg_platform(void)
(void)Cy_BLE_EcoReset();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
#endif
#ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
#endif
#ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
#endif
#ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
#endif
#ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
#endif
#ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
#endif
#ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
#endif
#ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
#endif
#ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
#endif
#ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
#endif
#ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
#endif
#ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
#endif
#ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
#endif
#ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@ -561,6 +522,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);

91
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.h Normal file
View File

@ -0,0 +1,91 @@
/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_eco_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_1_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF1 1UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
#define CY_CFG_PWR_MODE_LP 0x01UL
#define CY_CFG_PWR_MODE_ULP 0x02UL
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_SLEEP
#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
void init_cycfg_system(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_SYSTEM_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/qspi_config.cfg Normal file
View File

@ -0,0 +1,2 @@
set SMIF_BANKS {
}

1583
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/design.modus Normal file
View File

File diff suppressed because it is too large Load Diff