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Merge pull request #12355 from panmasuo/hani_iot_new_target 

HANI_IOT: add new target board support
pull/12363/head
Martin Kojtal 2020-02-04 08:37:12 +00:00 committed by GitHub
parent 586341541c 66d729af9a
commit c63daa5fb8
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 985 additions and 0 deletions
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6
components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json
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@ -13,6 +13,12 @@
} }
}, },
"target_overrides": { "target_overrides": {
"HANI_IOT": {
"SPI_MOSI": "P0_26",
"SPI_MISO": "P1_3",
"SPI_CLK": "P1_2",
"SPI_CS": "P0_20"
},
"LPC54114": { "LPC54114": {
"SPI_MOSI": "P0_20", "SPI_MOSI": "P0_20",
"SPI_MISO": "P0_18", "SPI_MISO": "P0_18",

3
features/storage/kvstore/conf/global/mbed_lib.json
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@ -11,6 +11,9 @@
} }
}, },
"target_overrides": { "target_overrides": {
"HANI_IOT": {
"storage_type": "TDB_INTERNAL"
},
"K66F": { "K66F": {
"storage_type": "TDB_INTERNAL" "storage_type": "TDB_INTERNAL"
}, },

140
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PortNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
} RTCName;
typedef enum {
UART_0 = Flexcomm0,
UART_1 = Flexcomm2,
UART_2 = Flexcomm6
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
typedef enum {
I2C_0 = Flexcomm1,
I2C_1 = Flexcomm4
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
} PWMName;
#define ADC_INSTANCE_SHIFT 8
#define ADC_B_CHANNEL_SHIFT 5
typedef enum {
ADC0_SE0 = 0,
ADC0_SE1 = 1,
ADC0_SE2 = 2,
ADC0_SE3 = 3,
ADC0_SE4 = 4,
ADC0_SE5 = 5,
ADC0_SE6 = 6,
ADC0_SE7 = 7,
ADC0_SE8 = 8,
ADC0_SE9 = 9,
ADC0_SE10 = 10,
ADC0_SE11 = 11,
ADC0_SE12 = 12,
ADC0_SE13 = 13,
ADC0_SE14 = 14,
ADC0_SE15 = 15,
ADC0_SE0_B = (1 << ADC_B_CHANNEL_SHIFT) | 0,
ADC0_SE1_B = (1 << ADC_B_CHANNEL_SHIFT) | 1,
ADC0_SE2_B = (1 << ADC_B_CHANNEL_SHIFT) | 2,
ADC0_SE3_B = (1 << ADC_B_CHANNEL_SHIFT) | 3,
ADC0_SE4_B = (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC0_SE5_B = (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC0_SE6_B = (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC0_SE7_B = (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC0_SE8_B = (1 << ADC_B_CHANNEL_SHIFT) | 8,
ADC0_SE9_B = (1 << ADC_B_CHANNEL_SHIFT) | 9,
ADC0_SE10_B = (1 << ADC_B_CHANNEL_SHIFT) | 10,
ADC0_SE11_B = (1 << ADC_B_CHANNEL_SHIFT) | 11,
ADC0_SE12_B = (1 << ADC_B_CHANNEL_SHIFT) | 12,
ADC0_SE13_B = (1 << ADC_B_CHANNEL_SHIFT) | 13,
ADC0_SE14_B = (1 << ADC_B_CHANNEL_SHIFT) | 14,
ADC0_SE15_B = (1 << ADC_B_CHANNEL_SHIFT) | 15
} ADCName;
typedef enum {
CAN_0 = 0,
CAN_1 = 1
} CANName;
#define SSELNUM_SHIFT 16
typedef enum {
SPI_0 = Flexcomm3,
SPI_1 = Flexcomm5,
SPI_2 = Flexcomm8
} SPIName;
/* Flexcomm 8 on LPC55S69 is dedicated for HS-SPI and hence uses different naming convention */
#define kFRO12M_to_FLEXCOMM8 (kFRO12M_to_HSLSPI)
#define kFC8_RST_SHIFT_RSTn (kHSLSPI_RST_SHIFT_RSTn)
#ifdef __cplusplus
}
#endif
#endif

146
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPinMaps.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINMAPS_H
#define MBED_PERIPHERALPINMAPS_H
#include <mstd_cstddef>
/************RTC***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_RTC[] = {
{NC, OSC32KCLK, 0},
};
/************ADC***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_ADC[] = {
{P0_23, ADC0_SE0, 0},
{P0_10, ADC0_SE1, 0},
{P0_31, ADC0_SE3, 0},
{P1_8, ADC0_SE4, 0},
{P2_0, ADC0_SE5, 0},
{P2_13, ADC0_SE6, 0},
{P2_11, ADC0_SE7, 0},
{NC , NC , 0}
};
/************CAN***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_TD[] = {
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_CAN_RD[] = {
{NC , NC , 0}
};
/************DAC***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_DAC[] = {
{NC , NC , 0}
};
/************I2C***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SDA[] = {
{P0_13, I2C_0, 1},
{P1_21, I2C_1, 5},
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_I2C_SCL[] = {
{P0_14, I2C_0, 1},
{P1_20, I2C_1, 5},
{NC , NC , 0}
};
/************UART***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_TX[] = {
{P0_30, UART_0, 1},
{P1_6, UART_0, 1},
{P0_27, UART_1, 1},
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RX[] = {
{P0_29, UART_0, 1},
{P1_5, UART_0, 1},
{P1_24, UART_1, 1},
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_CTS[] = {
{P1_8, UART_0, 1},
{P1_26, UART_1, 1},
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_UART_RTS[] = {
{P1_7, UART_0, 1},
{P1_27, UART_1, 1},
{NC , NC , 0}
};
/************SPI***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SCLK[] = {
{P0_6, SPI_0, 1},
{P0_21, SPI_1, 7},
{P1_2, SPI_2, 6},
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MOSI[] = {
{P0_3, SPI_0, 1},
{P0_20, SPI_1, 7},
{P0_26, SPI_2, 9},
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_MISO[] = {
{P0_2, SPI_0, 1},
{P0_19, SPI_1, 7},
{P1_3, SPI_2, 6},
{NC , NC , 0}
};
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_SPI_SSEL[] = {
{P0_4, SPI_0, 8},
{P1_20, SPI_1, ((1 << SSELNUM_SHIFT) | 1)},
{P1_1, SPI_2, ((1 << SSELNUM_SHIFT) | 5)},
{NC , NC , 0}
};
/************PWM***************/
MSTD_CONSTEXPR_OBJ_11 PinMap PinMap_PWM[] = {
{NC , NC , 0}
};
#define PINMAP_ANALOGIN PinMap_ADC
#define PINMAP_ANALOGOUT PinMap_DAC
#define PINMAP_I2C_SDA PinMap_I2C_SDA
#define PINMAP_I2C_SCL PinMap_I2C_SCL
#define PINMAP_UART_TX PinMap_UART_TX
#define PINMAP_UART_RX PinMap_UART_RX
#define PINMAP_UART_CTS PinMap_UART_CTS
#define PINMAP_UART_RTS PinMap_UART_RTS
#define PINMAP_SPI_SCLK PinMap_SPI_SCLK
#define PINMAP_SPI_MOSI PinMap_SPI_MOSI
#define PINMAP_SPI_MISO PinMap_SPI_MISO
#define PINMAP_SPI_SSEL PinMap_SPI_SSEL
#define PINMAP_PWM PinMap_PWM
#define PINMAP_CAN_TD PinMap_CAN_TD
#define PINMAP_CAN_RD PinMap_CAN_RD
#endif

19
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PeripheralPins.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
#include "PeripheralPinMaps.h"

211
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
/* If this macro is defined, then constexpr utility functions for pin-map seach can be used. */
#define STATIC_PINMAP_READY 0
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
P0_0 = (0 << PORT_SHIFT | 0),
P0_1 = (0 << PORT_SHIFT | 1),
P0_2 = (0 << PORT_SHIFT | 2),
P0_3 = (0 << PORT_SHIFT | 3),
P0_4 = (0 << PORT_SHIFT | 4),
P0_5 = (0 << PORT_SHIFT | 5),
P0_6 = (0 << PORT_SHIFT | 6),
P0_7 = (0 << PORT_SHIFT | 7),
P0_8 = (0 << PORT_SHIFT | 8),
P0_9 = (0 << PORT_SHIFT | 9),
P0_10 = (0 << PORT_SHIFT | 10),
P0_11 = (0 << PORT_SHIFT | 11),
P0_12 = (0 << PORT_SHIFT | 12),
P0_13 = (0 << PORT_SHIFT | 13),
P0_14 = (0 << PORT_SHIFT | 14),
P0_15 = (0 << PORT_SHIFT | 15),
P0_16 = (0 << PORT_SHIFT | 16),
P0_17 = (0 << PORT_SHIFT | 17),
P0_18 = (0 << PORT_SHIFT | 18),
P0_19 = (0 << PORT_SHIFT | 19),
P0_20 = (0 << PORT_SHIFT | 20),
P0_21 = (0 << PORT_SHIFT | 21),
P0_22 = (0 << PORT_SHIFT | 22),
P0_23 = (0 << PORT_SHIFT | 23),
P0_24 = (0 << PORT_SHIFT | 24),
P0_25 = (0 << PORT_SHIFT | 25),
P0_26 = (0 << PORT_SHIFT | 26),
P0_27 = (0 << PORT_SHIFT | 27),
P0_28 = (0 << PORT_SHIFT | 28),
P0_29 = (0 << PORT_SHIFT | 29),
P0_30 = (0 << PORT_SHIFT | 30),
P0_31 = (0 << PORT_SHIFT | 31),
P1_0 = (1 << PORT_SHIFT | 0),
P1_1 = (1 << PORT_SHIFT | 1),
P1_2 = (1 << PORT_SHIFT | 2),
P1_3 = (1 << PORT_SHIFT | 3),
P1_4 = (1 << PORT_SHIFT | 4),
P1_5 = (1 << PORT_SHIFT | 5),
P1_6 = (1 << PORT_SHIFT | 6),
P1_7 = (1 << PORT_SHIFT | 7),
P1_8 = (1 << PORT_SHIFT | 8),
P1_9 = (1 << PORT_SHIFT | 9),
P1_10 = (1 << PORT_SHIFT | 10),
P1_11 = (1 << PORT_SHIFT | 11),
P1_12 = (1 << PORT_SHIFT | 12),
P1_13 = (1 << PORT_SHIFT | 13),
P1_14 = (1 << PORT_SHIFT | 14),
P1_15 = (1 << PORT_SHIFT | 15),
P1_16 = (1 << PORT_SHIFT | 16),
P1_17 = (1 << PORT_SHIFT | 17),
P1_18 = (1 << PORT_SHIFT | 18),
P1_19 = (1 << PORT_SHIFT | 19),
P1_20 = (1 << PORT_SHIFT | 20),
P1_21 = (1 << PORT_SHIFT | 21),
P1_22 = (1 << PORT_SHIFT | 22),
P1_23 = (1 << PORT_SHIFT | 23),
P1_24 = (1 << PORT_SHIFT | 24),
P1_25 = (1 << PORT_SHIFT | 25),
P1_26 = (1 << PORT_SHIFT | 26),
P1_27 = (1 << PORT_SHIFT | 27),
P1_28 = (1 << PORT_SHIFT | 28),
P1_29 = (1 << PORT_SHIFT | 29),
P1_30 = (1 << PORT_SHIFT | 30),
P1_31 = (1 << PORT_SHIFT | 31),
P2_0 = (2 << PORT_SHIFT | 0),
P2_1 = (2 << PORT_SHIFT | 1),
P2_2 = (2 << PORT_SHIFT | 2),
P2_3 = (2 << PORT_SHIFT | 3),
P2_4 = (2 << PORT_SHIFT | 4),
P2_5 = (2 << PORT_SHIFT | 5),
P2_6 = (2 << PORT_SHIFT | 6),
P2_7 = (2 << PORT_SHIFT | 7),
P2_8 = (2 << PORT_SHIFT | 8),
P2_9 = (2 << PORT_SHIFT | 9),
P2_10 = (2 << PORT_SHIFT | 10),
P2_11 = (2 << PORT_SHIFT | 11),
P2_12 = (2 << PORT_SHIFT | 12),
P2_13 = (2 << PORT_SHIFT | 13),
P2_14 = (2 << PORT_SHIFT | 14),
P2_15 = (2 << PORT_SHIFT | 15),
P2_16 = (2 << PORT_SHIFT | 16),
P2_17 = (2 << PORT_SHIFT | 17),
P2_18 = (2 << PORT_SHIFT | 18),
P2_19 = (2 << PORT_SHIFT | 19),
P2_20 = (2 << PORT_SHIFT | 20),
P2_21 = (2 << PORT_SHIFT | 21),
P2_22 = (2 << PORT_SHIFT | 22),
P2_23 = (2 << PORT_SHIFT | 23),
P2_24 = (2 << PORT_SHIFT | 24),
P2_25 = (2 << PORT_SHIFT | 25),
P2_26 = (2 << PORT_SHIFT | 26),
P2_27 = (2 << PORT_SHIFT | 27),
P2_28 = (2 << PORT_SHIFT | 28),
P2_29 = (2 << PORT_SHIFT | 29),
P2_30 = (2 << PORT_SHIFT | 30),
P2_31 = (2 << PORT_SHIFT | 31),
P3_0 = (3 << PORT_SHIFT | 0),
P3_1 = (3 << PORT_SHIFT | 1),
P3_2 = (3 << PORT_SHIFT | 2),
P3_3 = (3 << PORT_SHIFT | 3),
P3_4 = (3 << PORT_SHIFT | 4),
P3_5 = (3 << PORT_SHIFT | 5),
LED_RED = P1_4,
LED_GREEN = P1_17,
LED_BLUE = P1_18,
BUZZER = P1_19,
// LED naming
LED1 = LED_RED,
LED2 = LED_BLUE,
// Push buttons
SW1 = P1_1,
// USB Pins
USBTX = P0_30,
USBRX = P0_29,
// Arduino Headers
D0 = P1_24,
D1 = P0_27,
D2 = P1_31,
D3 = P1_28,
D4 = P1_27,
D5 = P1_26,
D6 = P1_25,
D7 = P1_22,
D8 = P1_23,
D9 = P0_21,
D10 = P0_4,
D11 = P0_3,
D12 = P0_2,
D13 = P0_6,
D14 = P1_21,
D15 = P1_20,
I2C_SDA = D14,
I2C_SCL = D15,
A0 = P0_23,
A1 = P0_15,
A2 = P0_31,
A3 = P1_8,
A4 = P0_16,
A5 = P1_0,
// SPI Pins configuration
SPI_MOSI = D11,
SPI_MISO = D12,
SPI_SCK = D13,
SPI_CS = D10,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

228
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.c Normal file
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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* How to set up clock using clock driver functions:
*
* 1. Setup clock sources.
*
* 2. Set up wait states of the flash.
*
* 3. Set up all dividers.
*
* 4. Set up all selectors to provide selected clocks.
*/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v5.0
processor: LPC55S69
package_id: LPC55S69JBD100
mcu_data: ksdk2_0
processor_version: 0.0.6
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
#include "fsl_power.h"
#include "fsl_clock.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockFROHF96M();
}
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: System_clock.outFreq, value: 12 MHz}
settings:
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFRO12M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFRO12M configuration
******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
#ifndef SDK_SECONDARY_CORE
/*!< Set up the clock sources */
/*!< Configure FRO192M */
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
/*< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
#endif
}
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF96M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF96M
called_from_default_init: true
outputs:
- {id: System_clock.outFreq, value: 96 MHz}
settings:
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockFROHF96M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockFROHF96M configuration
******************************************************************************/
void BOARD_BootClockFROHF96M(void)
{
#ifndef SDK_SECONDARY_CORE
/*!< Set up the clock sources */
/*!< Configure FRO192M */
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
/*< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
#endif
}
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL100M
outputs:
- {id: System_clock.outFreq, value: 100 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
- {id: ENABLE_CLKIN_ENA, value: Enabled}
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockPLL100M configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockPLL100M configuration
******************************************************************************/
void BOARD_BootClockPLL100M(void)
{
#ifndef SDK_SECONDARY_CORE
/*!< Set up the clock sources */
/*!< Configure FRO192M */
POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
/*!< Set up PLL */
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
const pll_setup_t pll0Setup = {
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),
.pllndec = SYSCON_PLL0NDEC_NDIV(4U),
.pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
.pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
.pllRate = 100000000U,
.flags = PLL_SETUPFLAG_WAITLOCK
};
CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
/*< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
#endif
}

121
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/clock_config.h Normal file
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@ -0,0 +1,121 @@
/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockFRO12M **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFRO12M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFRO12M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFRO12M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************* Configuration BOARD_BootClockFROHF96M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockFROHF96M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
/*******************************************************************************
* API for BOARD_BootClockFROHF96M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockFROHF96M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
******************** Configuration BOARD_BootClockPLL100M *********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockPLL100M configuration
******************************************************************************/
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL100M configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockPLL100M(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

37
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/device.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define NUMBER_OF_GPIO_INTS 8
#define LPADC_VREF_SOURCE kLPADC_ReferenceVoltageAlt2
#define LPADC_DO_OFFSET_CALIBRATION false
#define LPADC_OFFSET_VALUE_A 10U
#define LPADC_OFFSET_VALUE_B 10U
#define APP_EXCLUDE_FROM_DEEPSLEEP (kPDRUNCFG_PD_DCDC | kPDRUNCFG_PD_FRO192M | kPDRUNCFG_PD_FRO32K)
/* Defines used by the sleep code */
#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M()
#define LPC_CLOCK_RUN BOARD_BootClockFROHF96M()
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

68
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_HANI_IOT/mbed_overrides.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "clock_config.h"
#include "fsl_power.h"
/*******************************************************************************
* Definitions
******************************************************************************/
// called before main
void mbed_sdk_init()
{
BOARD_BootClockFROHF96M();
}
// Enable the RTC oscillator if available on the board
void rtc_setup_oscillator(void)
{
}
uint32_t us_ticker_get_clock()
{
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Use 96 MHz clock us ticker timer */
CLOCK_AttachClk(kFRO_HF_to_CTIMER0);
return CLOCK_GetFreq(kCLOCK_CTmier0);;
#else
/* Use 96 MHz clock us ticker timer */
CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
return CLOCK_GetFreq(kCLOCK_CTmier1);;
#endif
}
void ADC_ClockPower_Configuration(void)
{
/* Set clock source for ADC0 */
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true);
CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK);
/* Disable LDOGPADC power down */
POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn);
}
void sdio_clock_setup(void)
{
/* Attach main clock to SDIF */
CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK);
CLOCK_SetClkDiv(kCLOCK_DivSdioClk, 1U, true);
}

6
targets/targets.json
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@ -3153,6 +3153,12 @@
"secure-ram-size": "0x22000" "secure-ram-size": "0x22000"
} }
}, },
"HANI_IOT": {
"inherits": ["LPC55S69_NS"],
"detect_code": ["0360"],
"components_add": ["SPIF"],
"extra_labels_remove": ["LPCXpresso"]
},
"NUCLEO_F030R8": { "NUCLEO_F030R8": {
"inherits": [ "inherits": [
"FAMILY_STM32" "FAMILY_STM32"